IEICE Electronics Express, Vol.20, No.23, 1–6
LETTER
Ultra-low-power lowpass filter with a novel complementary push-pull DC
offset calibration method applied to 5.8 GHz Doppler radar
Liangningyi Liu1 , Lei Chen1, a) , and Jie Su1
Abstract This paper presents a lowpass filter for 5.8 GHz Doppler radar
with an intermediate frequency signal hold function, which significantly reduces system power by interrupt mode operation. Additionally, it proposes
a novel complementary push-pull DC offset calibration method to calibrate
the DC voltage of the lowpass filter with the common mode voltage. Compared to traditional methods, the proposed scheme effectively stabilize the
quiescent operating point of the receiver. The experimental results show
that the power consumption of the proposed filter is 0.019 mW, calibrated
DC voltage is 1.65 V, and residual DC voltage is less than 1 mV.
Keywords: CPP-DC offset calibration, IF signal-hold, ultra-low-power
LPF, 5.8 GHz Doppler radar
Classification: Integrated circuits
1.
Introduction
The demand for narrow signal beamwidths and higher levels of integration has increased with recent developments
in high-performance electronic devices, and radar sensing
systems are steadily transitioning towards higher frequency
ranges. High operating frequencies allow wider signal bandwidths and increased Doppler shifts, thereby enhancing the
accuracy of distance and speed measurements [1, 2, 3]. In
comparison to radar operating in the 2.4 GHz frequency
band, chips designed to operate within the 5.8 GHz frequency band offer the advantages of higher sensitivity and
fixed frequency. Doppler radar is a cost-effective alternative to 5.8 GHz Frequency Modulated Continuous Wave
(FMCW) mode radar when applied to human sensing scenarios [4, 5]. Consequently, a growing interest now exists in
developing Doppler transceiver radar sensor chips capable of
operating in the 5.8 GHz band [6]. Additionally, developing
environmentally friendly and low-power electronic products
to reduce carbon emissions is of significant interest [7, 8].
However, the filters in radar transceiver systems often suffer from severe DC offset problems that may cause saturation
distortion of the entire system [9, 10]. Several approaches
have been proposed to address this issue, including AC coupling, analog high-pass filtering [11], DC negative feedback
loops [12, 13], and analog digital DC calibration [30, 31, 32].
However, these methods tend to occupy a large area of the
System on Chip (SoC), and require extended response and
1 School of Electronics and Information Engineering, Shanghai
University of Electric Power, Shanghai, 201306, China
a) chenlei@shiep.edu.cn
DOI: 10.1587/elex.20.20230380
Received August 16, 2023
Accepted October 6, 2023
Publicized October 18, 2023
Copyedited December 10, 2023
stabilization time [14, 15, 16]. Additionally, the majority
of conventional filters in radar systems are plagued by high
power consumption, which is not conducive to achieving
green and environmentally friendly goals [30].
In this paper, an ultra-low-power lowpass filter (LPF)
with a complementary push-pull DC offset calibration (CPPDCOC) method is proposed. This CPP-DCOC approach
generates a voltage to eliminate the offset voltage (Vos ) by
injecting or extracting current from the input of the LPF.
The calibration process is designed to operate only at system start-up, and the DC voltage can be calibrated approximately to the common mode voltage, effectively preventing
the system from saturation distortion. Additionally, the proposed LPF can be operated in work-sleep mode to reduce
power consumption by lowering the proportion of work cycles and raising the proportion of sleep cycles to achieve
energy conservation and emission reduction.
The remainder of this paper is organized as follows. Section 2 describes the architecture of the 5.8 GHz Doppler
radar system and analyses on the DC offset. Section 3
describes the implementation of the ultra-low power LPF
circuit and CPP-DCOC method. Section 4 presents the layout design and measurement results, and the conclusions are
presented in Section 5.
2.
Receiving architecture of 5.8 GHz Doppler radar
and DC offset mechanism
2.1
Architecture of the proposed ultra-low-power LPF
with CPP-DCOC
Figure 1 shows the receiving architecture of the 5.8 GHz
Doppler radar sensing system, which includes the receiver
section and intermediate frequency (IF) signal processing
section. To accelerate the system establishment process, DC
coupling is employed between the mixer and LPF [17].
The structure of the proposed LPF is mainly consist of
operational amplifier, CPP-DCOC block and the holding capacitor (CM ). The conventional DCOC achieves calibration
by injecting current into the input of the LPF, while the CPPDCOC proposed in this paper not only injects current into
it, but also draws excess current from the input, eliminating
Vos while making the DC voltage at the output of the LPF
near the common-mode voltage, which facilitates the linearity of the mixer and guarantees the gain of the receiving
circuit. When the LPF operates in continuous mode, the
interrupt control switch (SW_INT) remains ON to achieve
continuous lowpass filtering of the IF signal. When the LPF
1
Copyright © 2023 The Institute of Electronics, Information and Communication Engineers
IEICE Electronics Express, Vol.20, No.23, 1–6
Fig. 1
Receiving architecture of the 5.8 GHz Doppler radar system.
Fig. 2
Architecture ofthe proposed CPP-DC offset calibration.
is in interrupt mode, SW_INT is turned ON and OFF under
the control of LOGIC. However, excessive sleep time may
cause complete loss of IF signals, and the system may not
recognize IF signals if the LPF is established too slowly.
Thus, it is necessary to hold the IF signal through the CM
until the next duty cycle arrives.
2.2 Mechanism of DC offset in 5.8 GHz Doppler radar
In a 5.8 GHz Doppler radar system, the DC offset is a major
factor that can lead to system malfunctioning. One important
contributor to DC offset is device mismatch arising from the
use of short-channel devices [18, 20]. Another important
cause is the local oscillator leakage [19, 20, 21] in the highfrequency transceiver due to the variations in the position and
angle of the received signal from the antenna in practice.
The Vos of device mismatch [22] and Vos at the output of
the LPF can be expressed as
VGS − VT H
∆RL ∆(W/L)
Vos =
·
+
− ∆VT H
(1)
2
RL
W/L
Vosou t = (1 + Av ) Vosi n ≈ Av Vosi n .
(2)
When the LPF amplifies the IF signal with a gain (Av ),
any small DC offset at the input may be amplified, as shown
in Eq. (2), resulting in an output amplitude that exceeds the
power supply voltage. This phenomenon can lead to IF
saturation distortion and disrupt the normal operation of the
system.
3.
Design of the proposed LPF with CPP-DCOC
The proposed CPP-DCOC method comprises the CPP- comparator, SAR logic, and CPP-IDACs. The structure is shown
Fig. 3 Architecture of proposed the CPP-comparator.
in Fig. 2.
3.1 Design of the proposed CPP-comparator
Contrary to conventional DC offset calibration comparators,
those proposed in this paper compare the DC voltage at the
differential output of the LPF with the common mode voltage (VCM) of the LPF, which is shown in Fig. 3. Because the
CPP-DCOC calibration structure is capable of extracting and
injecting currents at the input of the LPF, two comparators
are correspondingly required for the determination. Assuming that the comparator output is 1 and 0 when the input V+ is
greater or lower than V− , respectively, four comparisons are
generated to determine whether to extract or inject current.
The results of the comparison are shown in Table I.
The CPP-DCOC comparator proposed in this paper does
not contain a clock, as shown in Fig. 4, which avoids the
clock feedthrough effect. The output of the comparator
comprises positive feedback with VIP and negative feedback
with VIN, which can convert the differential input signal
into a single-ended comparison result. The results of the
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IEICE Electronics Express, Vol.20, No.23, 1–6
Table I
Results of comparison.
Fig. 6
Circuit of the proposed CPP-IDACs.
Table II Results of CPP-DC offset calibration under PVT.
Fig. 4
Circuit of the proposed CPP-comparator.
LPF. The current values corresponding to the LSB cell is
I LSB =
Fig. 5 Framework of the proposed SAR logic.
comparison are sent to SAR logic for processing.
3.2 Design of the proposed SAR logic
The results generated by the comparator are delivered to the
SAR logic. The SAR logic generates an asynchronous clock
signal for each comparison outcome. Under the control of
a synchronous clock produced by a ring counter oscillator,
a total of 11 cycles are required for SAR logic with nine
comparisons. When the nine comparisons are completed,
the SAR logic sets the latch to 1, causing the entire calibration circuit to stop working. The SAR logical framework is
shown in Fig. 5.
3.3 Design of the proposed CPP-IDACs
To reduce the bit error rate generated by the comparator and
SAR logic, the control signals are first converted when they
enter the CPP-IDACs. The weight of each bit of the control
signal needs to be changed, i.e., the binary code is changed
to a split code (5 + 4) in the register, to prevent the high bit
misjudgment of the comparator from causing a significant
deviation in the results. When the 5-bit MSB is converted
into a 31-bit thermometer code, the remaining 4-bit LSB
remains as a binary code. The use of a thermometer code
also confers an advantage in that it eliminates mismatch
errors caused by these current sources [23]. These control
codes are subsequently employed to regulate whether the
CPP-IDACs inject or extract current from the input of the
V
osou t max
.
4
3
2 × 31 + 2 + 22 + 21 + 20 RF B
(3)
The proposed tail current source for CPP-IDACs uses a
cascode structure and operates in the saturation zone to increase its output impedance and avoid the effect of load variation on CPP-IDACs. The circuit diagram of CPP-IDACs is
shown in Fig. 6. The output impedance of CPP-IDAC can
be expressed as
Zimp = (gm3 ro3 + 1) · (gm2 ro1 ro2 + ro1 + ro2 ) .
(4)
The calibration time and DC voltage of the CPP-DCOC
under process, voltage, and temperature (PVT) variation are
presented in Table II. The simulation results indicate that the
DC voltage can closely approach the common mode voltage
following calibration, with a relatively short calibration time
of 53 µs.
3.4 Design of the proposed LPF
Active filters, unlike passive filters, remain unaffected by
changes in frequency or system impedance, whereas the
selection of RC topology enables precise gain and significant
bandwidth [24, 25]. The Butterworth filter is known for its
excellent passband flatness. In addition to their simplicity
and low power consumption, they also exhibit good overall
performance [26, 27]. Therefore, we chose to employ a
Butterworth transfer function filter. For a first-order LPF
that satisfies the Butterworth
√ response, the de-normalized
Butterworth coefficient is 2 when s = 10jwc . The transfer
function is
A0 wc
H(s) =
,
(5)
√
wc + 10 2wc
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IEICE Electronics Express, Vol.20, No.23, 1–6
Fig. 7 Circuit of the operational amplifier.
where A0 is the gain of the LPF and wc is the cut-off frequency. The attenuation of the first- order
LPF
√Butterworth
at the decadal frequency is 20 log10 1/ 101 = −20 dB.
Therefore, the first-order filter is usable in this paper.
As shown in Fig. 7, the operational amplifier of the proposed LPF is a two-stage amplifier with RC Miller compensation. The input differential pair PMOS is extended to an
N-well to isolate noise from the P-substrate. The first stage
uses a cascode structure to increase the gain of the op-amp.
Miller compensation separates the primary and secondary
poles to ensure the stability of the amplifier. SW_INT is
used to cut off the discharge path in the LPF in interrupt
mode, enabling the IF signal to be held.
The amplitude and frequency characteristics of the operational amplifier can be expressed as
A0 [1 − sCc (1/gm − Rc)]
(6)
1 + bs + cs2
gmp1 · gmn3
Av =
(7)
go1 · go2
go1 · go2
Pole1 = −
(8)
gmn3 · Cc
gmn3
Pole2 = −
(9)
CL
1
Zero = −
(10)
Cc (1/gmn3 − Rc)
gmp1
GBW = −
.
(11)
Cc
Where go1 and go2 is the 1st stage and 2nd stage output
admittance of the operational amplifier respectively. CL is
the load capacitance of LPF. As shown in Fig. 1, the off-chip
capacitor is chosen as the feedback capacitor (CFB ) for the
LPF because of the low frequency of IF at the receiver side.
The transfer function of the proposed LPF is
Fig. 8
Amplitude-frequency characteristics of the proposed LPF.
Fig. 9
Microphotograph of ultra-low-power LPF with CPP-DCOC.
A(s) =
H(s) = −
RF B /RI N
1 + sRF B CF B
(12)
The cut-off frequency of the LPF can be expressed as
fc =
1
2πRF B CF B
(13)
According to Eq. (12) and Eq. (13), amplitude-frequency
characteristics of the proposed LPF is shown in Fig. 8.
4.
Experimental results and comparison
To reduce process mismatch, the input differential pairs of
the operational amplifier are cross-matched [28]. Commoncentroid matching is also utilized to enhance linearity when
designing the layout of both the current mirror and analogue
switches [29]. The proposed LPF with CPP-DCOC occupies
a total area of 0.254 mm2 in the 55 nm CMOS. The 5.8 GHz
radar sensing system chip under a microscope is shown in
Fig. 9.
The chip is packaged and soldered to a PCB for testing,
with a supply voltage of 3.3 V. The gain of the LPF is set
to 45 dB. Upon initial power-up, the DC offset calibration
function is activated, and the output DC voltage of the LPF
is calibrated to 1.651 V. The time required for calibration is
approximately 53 µs. The DC voltage difference of differential outputs is less than 1 mV, as determined by observing
the oscilloscope and voltmeter. However, the conventional
current-only injection DCOC method causes the DC voltage at the LPF output to rise to 1.749 V, which may affect
the linearity and gain of the mixer, and even the quiescent
operating point of the operational amplifier. The calibration
process is shown in Fig. 10.
When the LPF is operating in continuous mode, its current
is 580 µA. However, the power consumption of the LPF,
which is controlled by digital registers to enable signals, can
be significantly reduced when operating in interrupt mode.
Assuming that the duty cycle of the LPF is set to 1/100 by
the digital register, the LPF operates only 1% of the time and
remains dormant 99% of the time during power-on, resulting
in a low LPF current of approximately 6 µA. As an interrupt
hold capacitor CM is positioned at the LPF output, the IF
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IEICE Electronics Express, Vol.20, No.23, 1–6
interrupt mode with a sine signal with 20 kHz frequency as
input.
Table III summarizes the performance of the LPF with
DCOC proposed in this paper and provides a comparison.
5.
Fig. 10
CPP- DC offset calibration process.
Conclusion
This paper proposes an LPF with CPP-DC offset calibration
for 5.8 GHz Doppler radar sensing systems. The approach
generates a calibrated DC value of approximately 1.651 V
at a supply of 3.3 V, with residue DC of less than 1 mV
within 53 µs. The mechanism ensures that the entire system
operates correctly with a gain adjustment range of 0–45 dB
in steps of 3 dB. By operating in interrupt mode with an
IF signal hold function, the LPF can decrease the power
consumption to 0.019 mW. The proposed LPF has an area
of 0.254 mm2 in a 55 nm CMOS.
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Fig. 11 IF signal of the system when operating in interrupt mode.
Table III
Performance and comparison.
signal is held, does not drop to 0, and can be set up quickly
in the next work cycle. Figure 11 illustrates the IF signal
obtained from the system receiver when operating in the
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