Both are same, one with
NOR and NAND.
Latches are controlled with
signal levels (Set and Reset)
Latches with Clock
transitions are flip-flops
Clock signals are frequent
signals between 0 and 1
Q is for active-low signal (0
or 1). Is the output
2’s complement: Find normal, invert bits, add 1
Signal Binary: Invert most significant (leftmost)
bit
Addition rules: 0 + 0 = 0, 1 + 1 = 0 w/ carry
Subtraction rules: 0 – 1 = 1 w/ borrow from left
bit
4-1 Mux has 2 select lines and 1 output line (4
Trains sharing 1 track)
3:8 Decoder has 3 input and 8 output (Mail
code for each mailbox)
D (Data latch), E (Enable), Register holds a bit
in each compartment, holding in array
Enabled Flip flop: Flip-Flop with enabled signal
(Mail-box analogy but main can also be taken
when door is open). Maintains signal when
disabled and updates on clock.
Resettable Flip flop: Flip-Flop with Reset signal.
Signal is 0 when reset and updates on clock.
Synchronous system: All signals follow a clock
signal
Race Condition: Situation where behavior of
system depends on timing of events with clock
signals.
FSM: Based on states and transitions (Traffic
light with diff signals based on input)
Moore machine: Vending machine analogy
where current state needs to be checked and
then output
Mealy machine: Vending machine analogy
where current state and new input is checked
together and then output
Sequential for both
AND & OR gates

4x1 & 2x1 ^
 Decoder 2^n Problem
Soda Problem ^
State Transition
Problem
Soda Problem ^