WaveLogic 5 Extreme 800G Transponder Module
Datasheet
Release 2.0
What’s inside…
Publication history
About this document
General description
Datapath descriptions
Optical specifications
Power specifications
Client electrical interface
Control interface
Mechanical specifications
Environmental specifications
Regulatory and reliability specifications
WaveLogic 5 Extreme 800G Transponder Module
Release 2.0
Copyright© 2019-2020 Ciena® Corporation
Datasheet
323-4100-110 Standard Issue 1
October 2020
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WaveLogic 5 Extreme 800G Transponder Module
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WaveLogic 5 Extreme 800G Transponder Module
Release 2.0
Copyright© 2019-2020 Ciena® Corporation
Datasheet
323-4100-110 Standard Issue 1
October 2020
v
Publication history
Version
Issue 1
Status
Standard
Date
October 2020
Changes
First Standard release of this document for Release
2.0.
Changes since Release 2 Preliminary Issue 1:
•
Removal of FOIC1.2 client support.
•
Change to polarization tracking tolerance
conditions, from 5dB peak PDL to 3dB peak
PDL.
•
Change to chromatic dispersion penalty
ranges for 200G, 400G.
•
Change in PreFEC BER threshold for
95Gbaud/400G mode.
•
Renamed SGMII to 1000BaseX. No functional
change.
•
Added timing specification for LI_HOST_SSF
pin.
•
Updated module photo.
•
Updated power specifications.
WaveLogic 5 Extreme 800G Transponder Module
Release 2.0
Copyright© 2019-2020 Ciena® Corporation
Datasheet
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vi
Contents
Publication history
Contents
About this document
1
2
3
4
5
6
7
8
v
vi
viii
Products covered by this document
Intended users of this document
References
viii
viii
viii
General description
1
1.1
High level specifications
1.2
Features
1.2.1
Hardware
1.2.2
Optical
1.2.3
Configuration and processing
1.3
Supported applications
Datapath descriptions
2
3
3
3
3
4
2.1
Transmitter datapath
2.2
Receiver datapath
2.2.1
Receiver datapath performance monitoring and defects
2.3
Client datapath
2.3.1
Client performance monitoring and defects
5
5
6
6
7
10
Optical specifications
12
Power specifications
17
Client electrical interface
18
Control interface
22
Mechanical specifications
27
Environmental specifications
32
3.1
3.2
3.3
Transmission mode summaries
Transmitter specifications
Receiver specifications
4.1
Power supply
5.1
5.2
Module datapath AcceleRate® connector pin list
Client SerDes electrical specifications
6.1
Ethernet Management Interface
6.2
Clocking
6.3
Functional I/O pins
6.3.1
MODEM_RST_B
6.3.2
LI_HOST_SSF
6.3.3
PM_TICK
6.3.4
MODEM_PWR_DWN_B
6.4
1.8V LVCMOS electrical characteristics
7.1
7.2
7.3
7.4
7.5
7.6
WL5e Module Interface to host
WL5e Module form factor
Optical fiber connectors
Highspeed Client/Host electrical connector
Management and Control Interface connector
+12V Power interface
8.1
8.2
8.3
Absolute maximum specifications
Operating conditions
Recommended airflow direction
WaveLogic 5 Extreme 800G Transponder Module
Release 2.0
Copyright© 2019-2020 Ciena® Corporation
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12
13
17
18
21
22
22
23
23
23
23
23
26
27
27
29
30
30
31
32
32
34
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9
Regulatory and reliability specifications
9.1
Regulatory and reliability specifications
WaveLogic 5 Extreme 800G Transponder Module
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35
Datasheet
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About this document
Products covered by this document
This document provides specifications for the following products:
Table 1 Products covered by this document
CIN
Description
176-4100-900
176-4100-910
176-4100-920
800G WL5E TRANSPONDER MODULE EXTENDED REACH
800G WL5E TRANSPONDER MODULE STANDARD REACH
800G WL5E TRANSPONDER MODULE DCI
Intended users of this document
This document is intended for Ciena® Optical Microsystems customers.
References
The following additional documents provide supplemental information to
this specification.
1. OIF IA # OIF-CEI-03.1 - Common Electrical I/O (CEI) – Electrical
and Jitter Interoperability agreements for 6G+ bps, 11G+ bps and
25G+ bps I/O, February 18, 2014.
2. ITU-T G.798 - Characteristics of Optical Transport Networks
Hierarchy Equipment Functional Blocks, December 2012.
3. IEEE 802.3ba - IEEE 802.3, Amendment 4: Media Access Control
Parameters, Physical Layers, and Management Parameters for 40
Gb/s and 100 Gb/s operation 2010.
4. IEEE 802.3bj - IEEE 802.3bj-2014, IEEE Standard for Ethernet
Amendment 2: Physical Layer Specifications and Management
Parameters for 100 Gb/s Operation Over Backplanes and Copper
Cables, June 2014.
5. IEEE P802.3bm - Draft Standard for Ethernet Amendment:
Physical Layer Specifications and Management Parameters for 40
Gb/s and 100 Gb/s Operation Over Fiber Optic Cables, 14th May
2014.
6. ITU-T G.709 - ITU-T G.709/Y.1331, Interfaces for the Optical
Transport Network, 02/2012.
7. 323-4100-310 WL5e Software User Guide, R2.0
8. 323-4100-200 WL5e Evaluation Board and GUI User Guide
WaveLogic 5 Extreme 800G Transponder Module
Release 2.0
Copyright© 2019-2020 Ciena® Corporation
Datasheet
323-4100-110 Standard Issue 1
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1
1 General description
The Ciena WaveLogic 5 Extreme 800G Transponder Module is a multirate, single carrier C-band flex grid coherent transceiver component,
capable of transmitting and receiving up to 800 Gbps of client payload.
Driven by advanced WaveLogic coherent DSP technology, and combined
with a high-bandwidth Coherent Driver Modulator (CDM) and micro
Intradyne Coherent Receiver (ICR), this transceiver provides flexible
coherent transmission in a compact, mountable form. This module
delivers the industry-leading solution for high-bandwidth, highperformance multi-haul line side DWDM transmission for both telecom
and data center applications, ultra-long haul and subsea. The WaveLogic
5 Extreme 800G Transponder Module supports operation at up to 95
GBaud and provides flexible, quasi-continuous capacity settings from 200
Gb/s to 800 Gb/s.
Client traffic is supported at either 28G NRZ or 56G PAM4. A wide range
of client types are supported, including provisionable FEC. Industryleading performance is enabled through advanced high-speed analog
design, best-in-class high gain FEC algorithms, non-linear compensation,
probabilistic constellations, and next-generation electro-optics. Fully
tunable through C-band frequency range, the module includes embedded
PRBS generator/analyzer and line and client (host) side loopbacks for
diagnostics.
Supported client signal types include both Ethernet and OTN.
Management of the module is accomplished using an Ethernet-based
management interface. A Software Development Kit (SDK) is available
from Ciena for direct integration into host platform software.
WaveLogic 5 Extreme 800G Transponder Module
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1.1 High level specifications
Table 1-1 WL5e module high level specifications
Form Factor:
Transmission modes:
Reach Cap:
Power:
Client Interface:
Voltage Supply:
Management Interface:
3.0" x 7.0" x 0.5"
C-band single carrier multi-rate
95.0 Gbaud (200G to 800G)
91.6 Gbaud (800G)
Extended: uncapped
Standard: 4500km
DCI: 300km
110 W (typical)
3x Samtec AcceleRate® Slim Body Cable Connector
400GE, over 400GAUI-8 (max 2)
100GE, over CAUI-4 (max 6)
100GE, over 100GAUI-2 (max 8)
OTU4 over OTL4.4 (max 6)
OTUCn (n=2,4,6) over FOIC1.4 (max 6)
12 Volts
by means of 1000BaseX (Ethernet)
Figure 1 WL5e Module
WaveLogic 5 Extreme 800G Transponder Module
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1.2 Features
1.2.1 Hardware
•
compact 3” x 7” x 0.5” form factor
•
aluminum top mounting plate that enables custom heatsink
installation
•
aluminum bottom plate for direct mounting to host PCB
•
30-pin connector + flex cable for low speed signals
•
0.5 meter fiber pigtail with LC connectors
•
support for low-loss, low skew high speed Samtec AcceleRate®
cables for client-side connectivity
•
Probabilistic Constellation Shaping (PCS) at 16QAM and 64QAM
•
enhanced coding gain through high performance Forward Error
Correction (FEC)
•
Extreme Chromatic Dispersion Tolerance (ECDT)
•
non-linear impairment mitigation through 4FDM (Frequency
Division Multiplexing)
1.2.2 Optical
1.2.3 Configuration and processing
•
OTN delay measurement, Trail Trace Indicator at line OTUCn,
ODUk and client OTUk
•
GCC0/1/2 overhead access
•
full PCS layer processing
•
KR4/KP4 FEC with optional bypass
•
full support for RMON Performance Monitoring
•
line facility and terminal loopback, client terminal loopback
•
line and client PRBS generator and checker
•
error insertion and monitoring
WaveLogic 5 Extreme 800G Transponder Module
Release 2.0
Copyright© 2019-2020 Ciena® Corporation
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1.3 Supported applications
The WaveLogic 5 Extreme 800G module is designed for use in
conjunction with a host platform to support DWDM transmission over
optical links in metro, regional, long-haul applications.
Various system applications are supported by the WaveLogic 5 Extreme
800G Transponder Module, including transponder, OTN-switched, packetswitched, or router interfaces. Typical applications are illustrated in Figure
1-2.
The module sub assembly can be used with external framer/mappers to
provide transport solutions for low rate, OTN and multi-service clients, or
with packet switch to provide WAN interface support in a switch/router
application. Additionally, due to the integrated client framer capabilities, it
can be used as a highly-integrated transponder for nx100GE or nx400GE
clients in a data center interconnect application, or also as a back-to-back
regen function in transmission networks.
Figure 1-2 Typical applications
Subsea/ULH/LH/Regional/Metro/DCI
LH/Regional/Metro
Metro/DCI
WaveLogic 5 Extreme 800G Transponder Module
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2 Datapath descriptions
The WaveLogic 5 Extreme 800G module is a complete implementation of
a high performance electro-optic coherent transceiver capable of
operating in high-demand telecom and datacenter applications.
The main functional blocks of the module are as follows:
•
transmitter datapath (WL5e DSP + Ciena CDM)
•
receiver datapath (WL5e DSP + Ciena uICR)
•
client datapath (WL5e DSP)
The functional block diagram of the transceiver (module) is illustrated
below.
Figure 2-1 WL5e module functional block diagram
Each functional block is described in the sections which follow in this
chapter.
2.1 Transmitter datapath
Once the client datapath circuit creates the FEC encoded frame, data
flows through the line-side DSP engine to create a multi-bit complex dualpolarization signal, that is, XI, XQ, YI, YQ. This signal is driven from the
DSP D-to-A converter outputs and encoded into a dual polarization optical
signal on an optical carrier through a high-performance Coherent Driver
Modulator (CDM).
A high-power narrow linewidth laser combined with a polarization
maintaining splitter provides transmission carrier as well as Rx local
oscillator functions.
The modulated carrier is then post-amplified by an onboard micro EDFA
for propagation over the optical fiber plant. Laser center frequency is
tunable over the entire C-band and is compatible with both flex and fixed
grid DWDM line systems.
WaveLogic 5 Extreme 800G Transponder Module
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2.2 Receiver datapath
The inbound optical signal carrying the desired data channel is passed to
a high performance integrated coherent intradyne (ICR) optical receiver
containing splitters, couplers, photodetectors and transimpedance
amplifiers, to produce the constituent XI, XQ, YI, YQ components.
LO power is obtained from the common on-board high-power laser.
The recovered amplified photocurrents from the four detector channels
are then passed into the DSP A-to-D converter stages for clock and data
recovery.
Received data is processed by the DSP and delivered to the FEC
decoder. Data then flows to the client blocks.
Optical taps are included in the receiver path for accurate monitoring of
the received signal throughout the optical path.
2.2.1 Receiver datapath performance monitoring and defects
Rx alarms/defects:
•
OTSi Loss of Signal
•
OTSi Rx power out-of-range
•
OTSi Loss of clock
•
OTSi Loss of frame
•
OTSi PreFEC Signal Fail
•
OTSi Dispersion out of range
•
OTSi Tx Tuning In Progress
•
OTSi Rx Frequency Prov Mismatch
•
OTN Loss of Frame
•
OTN Loss of Multiframe
•
OTN Backward Defect Indication
•
OTN Signal Degrade
•
OTN Client Signal Fail
•
OTN Alarm Indication Signal
•
OTN Incoming Alignment Error
•
OTN Trace ID Mismatch
•
OTN Open Connection Indication
•
OTN ODU Locked (LCK)
•
OTN Payload Mismatch
•
OTN Loss of Lock
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•
OTN Loss of Clock
Performance Monitoring:
•
PreFEC BER/Error Counts
•
FEC Overflow
•
Uncorrected FEC blocks
•
Module Temperature and Alarms
•
Measured Chromatic Dispersion
•
Measured DGD
•
Measured PDL
•
Measured eSNR
•
Tx Output Power
•
Rx Input Power
•
Carrier Frequency Offset or Frequency Lock Status
•
Q-Factor
•
Incoming Alignment Error
•
Backward Error Indication
•
BIP-8 counts
2.3 Client datapath
High speed client data is provided by means of the host interface. 100GE,
400GE, OTU4 and OTUCn are supported.
The module is designed to maximize the number of supported use cases
and can provide aggregation and transmission of various client protocols.
Figure 2-2 shows the datapath functional block diagram.
In a single module application, 24 bi-directional SerDes are available in a
group of 3 physical highspeed connectors (J1/J2/J3). Each connector can
support 8 SerDes, operating either in 56 Gbps PAM4 or 28 Gbps NRZ, to
support up to 800Gb/s traffic.
The 24 SerDes are allocated to eight SerDes banks, with each bank
representing a clock domain. This means a SerDes bank must be
dedicated to a given client signal, that is, a SerDes bank cannot be shared
for two different client signals that are not synchronous. This is illustrated
further in Figure 2.3.
WaveLogic 5 Extreme 800G Transponder Module
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Figure 2-2 WL5e module client datapath functional block diagram
Table 2-1 Supported Client Modes and Mappings
Client
Max
qty
FEC
Interface
Mapping: Client/Host => Line/Network
100GE
GMP
6
OFF
CAUI-4
100GE => GMP => ODU4 => PT22 Mux =>ODUCn
200G, 400G,
600G
100GE
GMP
6
KR4
CAUI-4
100GE => GMP => ODU4 => PT22 Mux =>ODUCn
200G, 400G,
600G
100GE
GMP
6
KP4
100GAUI-2
100GE => GMP => ODU4 => PT22 Mux =>ODUCn
200G, 400G,
600G
100GE ET
6
OFF
CAUI-4
100GE => GMP => PT22 Mux => ODUCn
800G
100GE ET
6
KR4
CAUI-4
100GE => GMP => PT22 Mux => ODUCn
800G
100GE ET
8
KP4
100GAUI-2
100GE => GMP => PT22 Mux => ODUCn
800G
OTU4
6
OFF
OTL4.4
OTU4 => ODU4 => PT22 Mux => ODUCn
200G, 400G,
600G
OTU4
6
GFEC
OTL4.4
OTU4 => ODU4 => PT22 Mux => ODUCn
200G, 400G,
600G
400GE
BMP
2
KP4
400GAUI-8
400GE => BMP => ODUFLEX => PT22 Mux => ODUCn
400G, 600G
400GE ET
2
KP4
400GAUI-8
400GE => GMP => ET
(Ciena proprietary Ethernet transcode mapping)
800G
OTUCn
n=2,4,6
KP4
FOIC1.4
OTUCn => ODUCn => OTUCn
200G, 400G,
600G
Transmission
Mode
Note: Clients identified as ET are using Ethernet transcoded mappings,
intended for Ethernet transport and Ethernet client hand-off. These clients
are intended for 800G ET transmission mode, which uses a Ciena
proprietary Ethernet transcode mapping. Client identified as GMP are
mapped into an OTN container (ODU4 or ODUFlex).
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Figure 2-3 Supported Client Mode configurations for each SerDes and Connector
Client traffic type provisioning is per SerDes bank. The 8 SerDes banks
are either quads (banks A, B, G, H) or duals (banks C, D, E, F). In some
traffic use cases, it is possible that a single client may be carried over
multiple SerDes banks. In such cases, all these SerDes must share a
single derived (recovered) reference clock.
These cases are as follows:
•
The dual SerDes can have a single 100G client carried across
SerDes C+D and E+F.
•
A single 400G client can be carried across A+B, and C+D+E+F
The supported SerDes mapping for various client protocols are listed in
the Table 2-1. 100GE/400GE and OTU4 clients of different mappings and
FEC types can be mixed and matched within a 400G subsystem. The
exception is OTUCn: no other client mode is allowed for either 400G
subsystem if client OTUCn (FOIC1.4) is used.
The output of client SerDes are aggregated to one of two 400G
subsystems, which maps and processes the various protocols all into line
OTUCn. The line adaptation layer then asynchronously adapts the data to
the line rate. The data is transported towards the line with SDFEC
encoding.
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The client/host interface data rates for different protocol configuration are
listed in Table 2-2.
Table 2-2 WL5e module client/host data rate
Protocol
Nominal
ppm
Serdes Rate (25G)
Serdes Rate (56G)
OTL4.4
111,809,973,568.28
20
27,953,052,441.94
-
CAUI-4
103,125,000,000.00
100
25,783,828,125.00
-
100GAUI
106,250,000,000.00
100
26,565,156,250.00
53,130,312,500.00
400GAUI
FOIC1.x
425,000,000,000.00
111,809,474,446.44
100
20
26,565,156,250.00
27,952,927,658.98
53,130,312,500.00
55,905,855,317.97
2.3.1 Client performance monitoring and defects
The following client (host) side Rx fault and performance monitoring (PM)
parameters are supported:
100GE/CAUI-4/PCS Defects:
•
SerDes Rx/Tx Loss of Clock
•
SerDes Rx Loss of Lock
•
SerDes Skew Out of Range
•
SerDes Rx/Tx Frequency Out of Range
•
PCS Rx/Tx Loss of Block Lock
•
PCS Rx High BER
•
PCS Rx/Tx Local Fault
•
PCS Rx/Tx Remote Fault
•
AUI Rx Loss of Lane Alignment
•
AUI Rx Loss of Alignment Marker
•
AUI Rx FEC HI SER (Severe Error)
•
AUI Tx Out of Alignment
100GE/CAUI-4/PCS PMs:
•
AUI Rx/Tx Error Block Counter
•
AUI Rx BER Counter
•
AUI Rx/Tx BIP Counter
•
Ethernet MAC PMs (RMON):
o
o
o
Rx/Tx frame count
Rx/Tx bad frame count
Rx/Tx octet count
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o
Rx/Tx bad octet count
o
Rx/Tx multicast count
o
Rx/Tx packet counts (segmented by frame length)
o
Rx/Tx broadcast count
OTN/OTL4.4/FOIC Defects:
•
OTL Rx Loss of Lane Alignment
•
OTL Rx Loss of Frame
•
OTL Rx Alarm Indication Signal
•
OTU Rx Loss of Frame
•
OTU Loss of Multiframe
•
OTU/ODU Rx Backward Defect Indication
•
OTU/ODU Rx Signal Degrade
•
OTU/ODU Rx Trace ID Mismatch
•
OTU/ODU Rx Alarm Indication Signal
•
OTU Rx Loss of Lane Alignment
•
ODU Rx Locked
•
ODU Rx Open Connection Indication
OTN/OTL4.4/FOIC PMs:
•
OTU/ODU Rx BIP Count
•
OTU/ODU Rx BEI Count
•
OTU Rx Incoming Alignment Error
•
OTU Rx Out of Frame
•
OTU Rx Out of Multiframe
•
OPU Rx PRBS Error Count
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3 Optical specifications
Optical specifications for both Tx and Rx interfaces, as well as
transmission mode specific performance data, are detailed in this section.
3.1 Transmission mode summaries
The WL5e Module is a flexible multi-haul transceiver that may be
operated in specific Transmission Modes listed in Table 3-1.
Table 3-1 Supported transmission modes
Transmission
Mode
Capacity
(Gbps)
Modulation
Supported Clients
800
800
Baud
(Gbaud)
91.6
95.0
800G
800G
PCS-64QAM
PCS-64QAM
600G
600
95.0
PCS-64QAM
400G
400
95.0
PCS-16QAM
100/400 GE only in Table 2-1
100/400 GE only in Table 2-1
100GE, 400GE, OTU4 client
types in Table 2-1
200G
200
95.0
PCS-16QAM
3.2 Transmitter specifications
Optical specifications for the Tx output of the WL5e Module are detailed in
Table 3-2 below. All values are worst-case, end-of-life unless noted
otherwise.
Table 3-2 Transmitter specifications
Parameter
Laser frequency tuning range
Value
191.25 THz to 196.125
THz
Laser tuning granularity
Output power tuning range
100 MHz
+4 dBm to -9 dBm
Tx optical return loss
Output power tuning granularity
Output power control accuracy
27 dB
0.1 dB
± 0.6 dB
Output power stability
Optical output power during
frequency tuning
Laser center frequency accuracy
± 0.2 dB
-30 dBm
± 1.5 GHz
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Note
Laser tuning range
expressed in frequency and
wavelength units.
Nominal optical output
power tuning range.
Power tuning step size.
EOL fiber launch power
difference between set
value and actual value over
wavelength, temperature,
and power adjustment
range
steady state
Tx output power is disabled
during frequency tuning.
EOL
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Parameter
Laser linewidth
Signal bandwidth: 91.6 Gbaud
Theoretical total signal bandwidth
Full width, 3dB down
Full width, 20dB down
Value
98.2 GHz
96.5 GHz
98.0 GHz
Signal bandwidth: 95 Gbaud
Theoretical total signal bandwidth
Full width, 3dB down
Full width, 20dB down
101.8 GHz
100.1 GHz
101.6 GHz
Pulse Shaping Alpha factor
1/14
Tx OSNR
Noise window from carrier
0 GHz
+/- 101.7GHz
+/- 203.4GHz
+/- 305.1GHz
Note
150 kHz
34.8 (min), 36.5 (typ)
35.5 (min), 38.1 (typ)
40.0 (min), 42.8 (typ)
47.3 (min), 51.1 (typ)
Typical values.
Single channel OSNR
measured at Tx output.
dB/12.5 GHz
Minimum Channel Spacing
91.6 Gbaud
95.0 Gbaud
100.0 GHz
102.5 GHz
For tightly spaced channels
in colorless applications.
Tx polarization dependent power
1.0 dB
Tx frequency change time
Tx baud change time
Combined Tx/Rx latency
Less than 5 minutes
Maximum power difference
between polarizations
Max
600G, 800G mode
200G, 400G mode
27 us
35 us
Line Protocol
Proprietary FlexO
Typical values.
Measured from client input
to client output not including
fibre propagation. 100GE
clients.
3.3 Receiver specifications
Optical specifications for the Rx input of the 5x7 Module are detailed in
Table 3-3 below. All values are worst-case, end-of-life unless noted
otherwise.
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Table 3-3 Receiver specifications
Parameter
Rx Local Oscillator
Rx input power damage threshold
Maximum Rx input power
Value
Shared with Tx
+14 dBm
+12 dBm
C-Band
CW
Total Power
Monitored Rx input power
accuracy
Input Power Range (per channel
power)
± 2.0 dB
Total Power
-7 dBm to +5 dBm
Across all transmission modes.
No power related OSNR penalty
when operating in this range.
Recommend target RX input
power = -7 dBm.
Minimum Rx input channel power
needed for error free operation
(Post-FEC BER <= 10-15) when
Rx OSNR >35 dB/0.1nm. Filtered
applications, typically unamplified
spans.
Rx Input Channel Power
Sensitivity
-25.0 dBm
200G
400G
600G
800G (95.0 Gbaud)
800G (91.6 Gbaud)
-16.5 dBm
Rx optical return loss
Required OSNR (PostFEC)
27 dB
[dB/12.5GHz]
200G
400G
600G
800G (95.0 Gbaud)
800G (91.6 Gbaud)
12.2
17.3
22.4
28.1
30.1
-25.0 dBm
-23.5 dBm
Note
-16.5 dBm
See Note 1 below.
EOL.
At Rx Input Power of -7 dBm.
OSNR required at Rx for errorfree (BER<=10-15) operation.
PMD tolerance
800G mode
200G, 400G, 600G mode
Optical Input Power Transient
Tolerance
30 ps mean, 90 ps peak
50 ps mean, 150 ps peak
4 dB
Maximum Polarization Tracking
Tolerance
1.5Mrad/s
PDL Tolerance (peak)
200G
9.0 dB
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Tolerance included in required
OSNR spec.
No additional penalty.
OSNR penalty < 0.5 dB.
Slew rate (10:90 %) >= 100us
Single event.
Tolerance to rate of change of
state-of-polarization (SOP)
For < 2 dB OSNR tracking
penalty.
400Gb/s transmission mode,
3dB peak PDL
Principal axis of PDL component
shall be aligned parallel to one of
Tx signal polarizations (X or Y).
Datasheet
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Parameter
400G
600G
800G
Rx Recovery Time
Value
7.5 dB
6.0 dB
4.5 dB
100 ms
Note
Noise is added after PDL
insertion.
preFEC BER is at threshold.
Typical value. Short term signal
interruption, time from signal
present to client traffic.
No laser frequency change.
Channel power delta < 5 dB
Chromatic Dispersion delta < 78
ns/nm
Chromatic Dispersion
Compensation Maximum Range
Total:
Tx Pre Comp:
Rx Post Comp:
-45,300 to 469,200 ps/nm
-5,700 to 429,600 ps/nm
± 39,600 ps/nm
Worst case for C-band
200G, 400G, 600G:
800G:
-45,300 to +469,200 ps/nm
-39,600 to +39,600 ps/nm
Pre-comp + Post-comp
Post-comp only
Chromatic dispersion penalty
<= 0.5dB OSNR penalty
200G
400G
600G
800G
450,000 ps/nm
450,000 ps/nm
140,000 ps/nm
20,000 ps/nm
Maximum dispersion for <= 0.5
dB OSNR penalty.
At 1550nm. Dispersion values for
other wavelengths can be
calculated using
CD( λ) = (CD@1550) * (1550/λ)2
Note 1: ROSNR test conditions as follows (unless stated otherwise):
•
Single wavelength present.
•
No dispersion.
•
Rx signal power >= -7dBm.
•
No PDL other than the Module itself.
•
PMD/DGD <= 50ps mean (200G/400G/600G) or <= 30ps mean
(800G).
•
<= 20krad/s rate of change of SOP.
•
ROSNR is defined to be constant across all frequency channels.
At different wavelength, ROSNR is defined by
OSNR_linear_per_0.1nm (λ) = (OSNR_linear_per_12.5GHz) x
(λο /λ nm)2 ,
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where λο = sqrt( c/12.5GHz ) = 1548.65735 nm.
Noise bandwidth of 0.1 nm = 12.5 GHz at 1548.65735 nm.
Note 2: PreFEC BER/Q threshold. The following PreFEC BER/Q
thresholds are included for informational purposes:
Transmission Mode
200G
400G
600G
800G (95Gbaud)
800G (91.6Gbaud)
PreFEC BER
Threshold
7.7E-02
3.9E-02
2.4E-02
1.7E-02
1.7E-02
Q threshold [dB]*
3.1
4.9
5.9
6.5
6.5
*
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4 Power specifications
4.1 Power supply
Table 4-1 WL5e Module 12V power specification
Parameter
Supply Voltage
Supply Current
Power Consumption
Supply Ripple
Transient Current
Peak Slew
Power in Low Power
Power in Reset
Min
10.8
Typ
12.0
7.9
95
Max
13.2
9.7
105
1.0
14
Units
V
A
W
% p-p
mA/ms
45
15
W
W
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Notes
12KHz to 20MHz
During provisioning in high
power mode.
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5 Client electrical interface
The high-speed client interface is intended to operate in CEI-28G-NRZMR and CEI-56G-PAM4-VSR applications. Client ingress and egress data
is accomplished using highspeed Samtec AcceleRate® connectors and
cables, supporting 28Gbps NRZ and 56Gbps PAM4.
High-speed client SerDes electrical interfaces are Current Mode Logic
(CML) and require AC coupling capacitors.
IMPORTANT
The AC coupling capacitors are not included in the
module design. They must be included in the host
design.
The total channel insertion loss of host interface + PCB + cable + pair of
connectors should be less than 10 dB at 14 GHz.
Sample connector and cable option part numbers are described in Section
7.4.
5.1 Module datapath AcceleRate® connector pin list
The 24 client SerDes are mapped to 3 connectors (J1/J2/J3). The SerDes
clock groups and pin assignments are listed in Table 5-1.
Table 5-1 Module SerDes Datapath AcceleRate® Connector Pin List
Module Twin-Ax
Connector
Twin-Ax Connector
Pin Number
Direction
J3
J3
J3
J3
J3
J3
J3
J3
4
6
10
12
16
18
22
24
IN
IN
IN
IN
IN
IN
IN
IN
J3
J3
J3
J3
J3
J3
3
5
9
11
15
17
OUT
OUT
OUT
OUT
OUT
OUT
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Lane
Diff
Pair
0
0
0
0
0
0
0
0
SerDes
Clock
Group
A
A
A
A
A
A
A
A
0
0
1
1
2
2
3
3
N
0
0
0
0
0
0
A
A
A
A
A
A
0
0
1
1
2
2
N
Data
Slice
P
N
P
N
P
N
P
P
N
P
N
P
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323-4100-110 Standard Issue 1
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19
J3
J3
21
23
OUT
OUT
0
0
A
A
3
3
N
J3
J3
J3
J3
J3
J3
J3
J3
28
30
34
36
40
42
46
48
IN
IN
IN
IN
IN
IN
IN
IN
1
1
1
1
1
1
1
1
B
B
B
B
B
B
B
B
0
0
1
1
2
2
3
3
N
J3
J3
J3
J3
J3
J3
J3
J3
27
29
33
35
39
41
45
47
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
1
1
1
1
1
1
1
B
B
B
B
B
B
B
B
0
0
1
1
2
2
3
3
N
J2
J2
J2
J2
J2
J2
J2
J2
4
6
10
12
3
5
9
11
IN
IN
IN
IN
OUT
OUT
OUT
OUT
2
2
2
2
2
2
2
2
C
C
C
C
C
C
C
C
0
0
1
1
0
0
1
1
N
J2
J2
J2
J2
J2
J2
J2
J2
16
18
22
24
15
17
21
23
IN
IN
IN
IN
OUT
OUT
OUT
OUT
2
2
2
2
2
2
2
2
D
D
D
D
D
D
D
D
2
2
3
3
2
2
3
3
N
J2
J2
J2
28
30
34
IN
IN
IN
3
3
3
E
E
E
0
0
1
N
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P
P
N
P
N
P
N
P
P
N
P
N
P
N
P
P
N
P
N
P
N
P
P
N
P
N
P
N
P
P
N
Datasheet
323-4100-110 Standard Issue 1
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20
J2
J2
J2
J2
J2
36
27
29
33
35
IN
OUT
OUT
OUT
OUT
3
3
3
3
3
E
E
E
E
E
1
0
0
1
1
P
J2
J2
J2
J2
J2
J2
J2
J2
40
42
46
48
39
41
45
47
IN
IN
IN
IN
OUT
OUT
OUT
OUT
3
3
3
3
3
3
3
3
F
F
F
F
F
F
F
F
2
2
3
3
2
2
3
3
N
J1
J1
J1
J1
J1
J1
J1
J1
4
6
10
12
16
18
22
24
IN
IN
IN
IN
IN
IN
IN
IN
4
4
4
4
4
4
4
4
G
G
G
G
G
G
G
G
0
0
1
1
2
2
3
3
N
J1
J1
J1
J1
J1
J1
J1
J1
3
5
9
11
15
17
21
23
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
4
4
4
4
4
4
4
4
G
G
G
G
G
G
G
G
0
0
1
1
2
2
3
3
N
J1
J1
J1
J1
J1
J1
J1
J1
28
30
34
36
40
42
46
48
IN
IN
IN
IN
IN
IN
IN
IN
5
5
5
5
5
5
5
5
H
H
H
H
H
H
H
H
0
0
1
1
2
2
3
3
N
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N
P
N
P
P
N
P
N
P
N
P
P
N
P
N
P
N
P
P
N
P
N
P
N
P
P
N
P
N
P
N
P
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21
J1
J1
J1
J1
J1
J1
J1
J1
27
29
33
35
39
41
45
47
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
5
5
5
5
5
5
5
5
H
H
H
H
H
H
H
H
0
0
1
1
2
2
3
3
Max
Unit
N
P
N
P
N
P
N
P
5.2 Client SerDes electrical specifications
Symbol
Parameter
Min
VOCM
Output Common Mode Voltage
1000 mV
VOD
Output Peak-Peak Differential Voltage
1100 mVpp_diff
VID
Input Peak-Peak Differential Voltage
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30
0
500
mVpp_diff
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6 Control interface
A 30-pin connector is on the WL5e module for control signals. A 30
conductor flex cable provides the connectivity from the WL5e module to
the host PCB for functional IOs, Ethernet management interface, and
clocking.
6.1 Ethernet Management Interface
The module is managed using an Ethernet-based 1000BaseX interface.
Details can be found in the WL5e software user guide.
6.2 Clocking
A host-generated source clock is not required to be fed to the WL5e
module in typical applications. All clocking required is generated on-board
to the module. However, synchronization to a host-generated source clock
is optionally available, and specific clocks are made available as output
from the module for synchronization:
•
•
Physical Layer Sync (PLS) [Future]: By default, the digital client
layers (for example, ODUCn, ODU4) that terminate on the module
are timed using the module's local oscillator. The digital client
layers can optionally be synchronized to the module using the
Physical Layer Sync (PLS) feature, specifically the PLS_REFCLK
input signal. Doing so allows the client layers to be used to carry
physical layer synchronization. The PLS feature is provided to
support SyncE (synchronous Ethernet) and SyncO (synchronous
OTN). The DPLL (digital phase lock loop) in the client logic can
use the external PLS input to reference free-running 100GE,
ODU4 and OTUCn rates. The PLS output can be used to drive an
external DPLL in the client logic on the host to derive the rate from
100GE, ODU4 or OTUCn rates from the datapath in either
direction. There are 2 clocks associated with PLS:
•
Physical Layer Sync Ref Clock (PLS_REFCLK): Input to
WL5e module.
•
Physical Layer Sync Off-ramp Received Clock
(PLS_OFR_RCVD_CLK): Output from WL5e module.
C2C_Sync [Future]: for mated module configurations (available in
future releases), the host must provide a synchronization signal to
both modules. Signal characteristics are listed in Table 6-1.
Note: The PLS and C2C_Sync features are planned for a future release.
Information is provided here to enable optional host connectivity in
advance.
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6.3 Functional I/O pins
6.3.1 MODEM_RST_B
The Module Reset pin (MODEM_RESET_B) is an input signal from the
host platform indicating that the module should go into RESET condition.
This input is active LOW and has a nominal (40K ohm) pull down resistor
on the module input pin. When LOW, it holds the module in reset, and the
module is not accessible using the module IP address. This is traffic
affecting.
6.3.2 LI_HOST_SSF
The Line Host Server Signal Fail pin (LI_HOST_SSF) is a status output
signal from the module. It is intended to be used for protection switching
by the host. The output is active HIGH. The timing for this pin is specified
in Table 6-1.
Table 6-1: LI_HOST_SSF timing specification
Parameter
Typical
Max
LI_HOST_SSF turn on time (from loss of optical
signal)
4ms
10ms
LI_HOST_SSF turn off time (from return of
optical signal)
1s
2s
6.3.3 PM_TICK
The PM Tick pin (PM_TICK) is an input signal from the host platform
indicating when the module should latch performance monitoring data.
This input is active on the rising edge of the signal, and it is assumed that
the timing of the signal is set according to host requirements. Nominal
timing is 1 second intervals.
IMPORTANT
The host PCB should not allow the PM_TICK to float.
6.3.4 MODEM_PWR_DWN_B
The Low Power pin (PWR_DWN_B) is an input signal from the host
platform indicating when the module should enter a low power standby
state. This input is active LOW and has a weak 50K Pull Up on the
module. If desired, the host can apply a 20K pull down or stronger to keep
the modem powered down by default (a host design may require this if the
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device that would actively drive this signal is not alive at power-up); can
be actively driven high or float (if there is no pull-down on the host) to exit
low power mode; powers down most of the module for a low power mode.
However, the 1000BaseX management interface is active, and basic
queries are accessible through the module IP address.
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Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Table 6-2 Management connector pin list
IO
Type
Description
1.8V LVCMOS; DC; 40K Pull
RESET (Active
MODEM_RST_B
IN
down on Module. Resets the
Low)
Module. Traffic affecting.
GROUND
GROUND
Ethernet Management Interface;
1000BaseX
1.25-2.5 Gbs
Main communication interface to
OUT
_MODEM2HOST_P
Diff pair
module. 1V diff pkpk; AC couple
on host using 100nF.
Ethernet Management Interface;
1000BaseX
1.25-2.5 Gbs
Main communication interface to
OUT
_MODEM2HOST_N
Diff pair
module. 1V diff pkpk; AC couple
on host, using 100nF.
1.8V LVCMOS ; DC; Value may
LI_HOST_SSF
OUT STATUS
toggle during 12V power up.
before reset released.
GROUND
GROUND
Ethernet Management Interface;
1000BaseX
1.25-2.5 Gbs
Main communication interface to
IN
_HOST2MODEM_P
Diff pair
module. 0.3V diff pkpk Min; AC
coupled on module.
Ethernet Management Interface;
1000BaseX
1.25-2.5 Gbs
Main communication interface to
IN
_HOST2MODEM_N
Diff pair
module. 0.3V diff pkpk Min; AC
coupled on module.
GROUND
GROUND
1.8V LVCMOS; DC; Host should
PM_TICK
IN
CLOCK
not allow pin to float.
Vendor Reserved
N/C
Leave unconnected.
Vendor Reserved
N/C
Leave unconnected.
1Hz, 10us pulse. Sent from host
to both modules in mated config,
C2C_Sync (1PPS)
IN
1.8V LVCMOS
less than 10ns of skew. For future
use.
GROUND
GROUND
Vendor Reserved
N/C
Leave unconnected.
Vendor Reserved
N/C
Leave unconnected.
1.8V LVCMOS; No host
termination required; For future
GPIO_0
BI
TBD
use. Note: Signal may toggle on
startup.
1.8V LVCMOS; No host
termination required; For future
GPIO_1
BI
TBD
use. Note: Signal may toggle on
startup.
Pull-up to 3.3V using 100ohm
Vendor Reserved
N/C
(nominal) recommended.
Vendor Reserved
N/C
Leave unconnected.
1.8V LVCMOS ; DC coupled. For
PLS_OFR_RCVD_CLK
OUT CLOCK
future use.
1.8V LVCMOS; No host
GPIO_3
BI
TBD
termination required; For future
Name
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23
24
GROUND
Vendor Reserved
N/C
25
GPIO_2
BI
26
GROUND (MOD_ABS)
27
PLS_REFCLK_P
IN
CLOCK
28
PLS_REFCLK_N
IN
CLOCK
29
GROUND
30
MODEM_PWR_DWN_B
use. Note: Signal may toggle on
startup.
GROUND
Leave unconnected.
1.8V LVCMOS; No host
termination required; For future
use. Note: Signal may toggle on
startup.
<100 Ohms to GND on Module;
Host can use this pin to indicate
module presence.
AC Coupled (AC coupling
capacitors on module); 125MHz
or 155.52 MHz typical frequency;
+/-20ppm frequency stability;
100mVpp to 1800mVpp
differential voltage; 400V/us slew
min; duty cycle 40% min, 60%
max; jitter 1ps rms max (12KHz
to 20MHz). For future use.
TBD
GROUND
GROUND
IN
Active Low
1.8V LVCMOS; 10K Pull Down
on module; Powers down much
of the module for a low power
mode.
6.4 1.8V LVCMOS electrical characteristics
Pins specified as 1.8V LVCMOS functionality described above shall meet
the electrical characteristics described in Table 6-3.
Table 6-3 1.8V LVCMOS Electrical specifications
Parameter
Symbol
Min
Typ
Max
Units
Input High Voltage
VIH
1.17
2.1
V
Input Low Voltage
VIL
-0.3
0.63
V
Input Leakage Current
IIN
-
-
uA
Output High Voltage
VOH
1.35
-
V
Output Low Voltage
VOL
-
0.45
V
Output High Current
IOH
-
10
-
mA
Output Low Current
IOL
-
10
-
mA
Input Capacitance
Ci
-
10
pF
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7 Mechanical specifications
7.1 WL5e Module Interface to host
There are 4 primary host interfaces to the WL5e module:
•
High-speed datapath, using Samtec AcceleRate® connectors.
•
12V power, by means of brass stand-offs (screw-attach to host
PCB).
•
Clock and Control, by means of a 30-pin flex cable (cable included
with module).
•
Optical interconnect, by means of fiber pigtails with LC connectors.
These are illustrated in Figure 7-1 and described in sections 7-3 to 7-6.
Figure 7-1 Module Interface to Host
7.2 WL5e Module form factor
The WL5e module, shown in Figure 7-2, is constructed as a 76.2mm x
179.6mm x 18.8mm module with aluminum mounting plates on top and
bottom. The top plate has available heatsink mounting points, as indicated
in Figure 7-3. The bottom plate is intended for direct contact to the host
PCB, with module mounting points as indicated in Figure 7-4.
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Figure 7-2 Mechanical model
Figure 7-3 Mechanical drawing (top view)
Note: All dimensions are in millimeters.
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Figure 7-4 Mechanical drawing (bottom and side views)
Note: All dimensions are in millimeters.
7.3 Optical fiber connectors
The WL5e Module employs duplex LC connectors. The default fiber pigtail
length is 0.5m.
•
White fiber = Tx
•
Blue fiber = Rx
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7.4 Highspeed Client/Host electrical connector
The module electrical connectors are intended to be used with Samtec
AcceleRate® high speed cables, supporting 28Gbps NRZ and 56Gbps
PAM4. Host connector and cable options are shown in Table 7-2.
Table 7-1 Module high-speed connector
Samtec
Part Number
Connector
Samtec AcceleRate® Slim Body
Cable Connector
ARF6-16-S-RA-TR
Table 7-2 Module options to host PCB
Options to Host PCB
Samtec
Part Number
Board Vertical Connector
ARF6-16-S-D-A
Board Right Angle Connector
High Speed Cable
QSFP28 Direct Cage Connect Cable
QSFPDD Direct Cage Connect
Cable
ARF6
ARC-6 Series
Cable
FQSFP
FQSFP-DD
The high-speed client Pin List is contained in Table 5-1.
7.5 Management and Control Interface connector
The form factor of the management interface connector is 2x15 pins, 1mm
spacing header, female. Advanced Interconnect Part Number is DHS230844GG-M.
The flex ribbon cable is supplied with the module. The mating connector
(host-side) and mechanical cable hold-down is supplied by the host.
Pinout and signal descriptions are in Table 6-2.
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7.6 +12V Power interface
The power to the WL5e module is brought through brass standoffs, which
are incorporated into the module design. The host provides two 7.5mm
copper pads as contact points for the module power entry, secured by
brass screws from the underside of the host PCB. Details are shown in
Figure 7-5 below.
Figure 7-5 Power connection to module
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8 Environmental specifications
This section describes the environmental and reliability specifications for
the WL5e Module.
8.1 Absolute maximum specifications
Table 8-1 Absolute maximum specifications
Parameter
Storage Temperature
Storage Relative Humidity
ESD rating: DC pins
Min
-40 C
5%
ESD rating: RF pins
Max
85 C
95%
500V
Note
Non-Condensing
Human Body Model
250V
Human Body Model
8.2 Operating conditions
Table 8-2 Operating conditions
Parameter
Operating Case Temperatures
Min
Max
Note
Used for thermal modeling and external
measurements (thermocouples).
Long-term operating:
Measurement point #1 (TMP1)
Measurement point #2 (TMP2)
Measurement point #3 (TMP3)
-5C*
-5C*
-5C*
76C
62C
75C
*Min case temperatures are minimum start-up
temperatures.
Short-term operating:
Measurement point #1 (TMP1)
Measurement point #2 (TMP2)
Measurement point #3 (TMP3)
-5C*
-5C*
-5C*
84C
67C
80C
Operating Humidity
5%
85%
If all three measurement points are below the
maximums, all components inside the module
will be below the temperature limit for the
operating condition. See diagram below for
measurement locations.
Definitions:
Long-term operating: Standard maximum
operating conditions for the device, no
restriction on duration.
Short-term operating: A period of not more
than 96 consecutive hours and a total of not
more than 15 days in 1 year. This refers to a
total of 360 hours in any given year, but no
more than 15 occurrences during that 1-year
period.
Note: Internal sensors that monitor specific
component temperatures and are readable by
means of the software interface are defined in
the WL5e Software User Guide.
Relative Humidity
Non-Condensing
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8.3
Recommended airflow direction
The recommended airflow direction to provide cooling to the module is
shown below. This direction is to ensure the optics section of the module
receives the coolest airflow that is not pre-heated by the DSP section.
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9 Regulatory and reliability
specifications
9.1 Regulatory and reliability specifications
The following table lists the regulatory and reliability specifications for the
WL5e Module.
Table 9-1 Regulatory and reliability specifications
Category
Safety
Specification
IEC 60825-1:2014
IEC 62368-1:2014 (Ed.2)
FDA CDRH21 CFR-1040
ESD
Telcordia GR-78-CORE Issue 2
High speed pins – 250V
All other pins – 500V
21CFR47 FCC Part 15, Class A
CISPR 32:2012 Class A
Electromagnetic
Emission
Electromagnetic
Immunity
CISPR 35: 2015 (Ed.2)
Flammability
Telcordia GR-63-CORE Issue 5
Transportation
vibration
Handling (drops)
Telcordia GR-63-CORE / ETSI
EN 300 019-1-2 (Class 2.3)
Telcordia GR-63-CORE / ETSI
EN 300 019-1-2 (Class 2.3)
RoHS 2011/65/EU
GR-468-CORE
GR-1312-CORE
RoHS
Reliability
Reliability
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Remarks
The module is designed to comply
with Class 1M Laser.
For installation and use in Restricted
Access Locations.
Human Body Model
C=100pF, R=1.5kOhms
This module is designed to comply
with Class A electromagnetic
emission.
Target enclosure must provide ≥ 20dB
of shielding effectiveness up to 10
GHz to achieve compliance.
Target enclosure must provide ≥ 20dB
of shielding effectiveness up to 10
GHz to achieve compliance.
Conforms with fire resistance criteria
by means of the needle flame test per
ATIS 0600307.2014.
Datasheet
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Datasheet
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Release 2.0
Publication: 323-4100-110
Document status: Standard
Issue 1
Document release date: October 2020
CONTACT CIENA
For additional information, office locations, and phone numbers, please visit the
Ciena web site at www.ciena.com