See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/258157119 Real-time soft-error testing of 40nm SRAMs Conference Paper · April 2012 DOI: 10.1109/IRPS.2012.6241814 CITATIONS READS 33 979 9 authors, including: Jean-Luc Autran S. Serre Aix-Marseille University Aix-Marseille University 415 PUBLICATIONS 6,024 CITATIONS 12 PUBLICATIONS 188 CITATIONS SEE PROFILE SEE PROFILE Daniela Munteanu Sergey S. Semikh French National Centre for Scientific Research VedaProject 235 PUBLICATIONS 3,292 CITATIONS 42 PUBLICATIONS 955 CITATIONS SEE PROFILE All content following this page was uploaded by Jean-Luc Autran on 04 October 2015. The user has requested enhancement of the downloaded file. SEE PROFILE Real-Time Soft-Error Testing of 40nm SRAMs J.L. Autran, S. Serre, D. Munteanu, S. Martinie, S. Semikh, S. Sauze IM2NP – UMR CNRS 7334 Aix-Marseille University Marseille, France Phone: (+33) 413-559-717 – jean-luc.autran@univ-amu.fr S. Uznanski, G. Gasiot, P. Roche Rad-hard and Ultra Low Voltage Group STMicroelectronics Crolles, France Abstract— This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed. Keywords- soft-error rate, real-time testing, SRAM, atmospheric neutrons, single-event upset, multiple cell upset. I. INTRODUCTION Terrestrial neutron-induced soft-errors in modern electronics circuits are currently one of the major concerns in reliability issues. Understanding the underlying mechanisms and quantifying the Soft-Error Rate (SER) under natural radiation at ground level are primarily crucial for the development of future semiconductor technologies. Among all the experimental techniques envisaged to characterize the neutron SER, the “real-time” approach is based on the continuous survey of a large number of test chips subjected to the natural radiation environment at ground level [1]. The method is obviously time consuming (typical test durations are expressed in months or years) and expensive, but it drastically limits the introduction of experimental artifacts due, for example in accelerated tests, to beam uniformity/fluctuations, dosimetry errors, chip misalignment with respect to the beam or difference in the source spectrum introduced by the cut-off energy of the accelerator at high energies, well below the one characterizing natural radiation. In order to benefit from a permanent facility dedicated to real-time testing, we have developed since 2005 a test platform at mountain altitude, the Altitude Test Single-event European Platform (ASTEP). Located in south French Alps at 2552 m of elevation, ASTEP has been continuously used from this date to investigate the impact of atmospheric particles on the SER of circuits manufactured in different technological nodes (130 and 65 nm) [2-4]. The platform has been also hosted a neutron monitor since 2008 and an atmospheric muon counter since This work is currently supported by the CATRENE Project #CA303 OPTIMISE (OPTImisation of Mitigations for Soft, firm and hard Errors) and by the French Ministry of Industry under research convention #092930487. July 2011 to monitor in real-time the particle flux incident on the microelectronics experiments deployed on ASTEP [5]. In the direct continuation of this effort, we installed in March 2011 a new experiment dedicated to the real-time SER characteriza-tion of SRAM circuits fabricated in CMOS 40 nm. The present paper is the first published work concerning this experiment. Details related to the test chip, the automatic test equipment and the ASTEP platform are given in Section II. Measurement data are reported in Section III. These data are analyzed in terms of Single Bit Upsets (SBU), Multiple Cell Upset (MCU), physical bitmap on the memory plan and convergence of the SER. Finally, in Section IV, these results are confronted to Monte Carlo simulations obtained with the TIARA code and accelerated test measurements performed at the TRIUMF Neutron Facility. II. EXPERIMENTAL DETAILS A. 40nm SRAM test chip Real-time measurements have been performed on bulk SRAMs fabricated by STMicroelectronics using a commercial CMOS low power process in 40 nm technology (optical shrink of the 45 nm technological node). This process is based on a Boro-Phospho-Silicate Glass (BPSG)-free Back-End Of Line (BEOL) which eliminates the major source of 10B in the circuits and drastically reduces the possible interaction between 10 B and low – thermal energy neutrons. The test chip, called PROMO40v5, is shown in Figure 1. It embeds more than 14 Mbit of standard- and high-density, single- and dual-port SRAMs as well as a collection of standard devices from ST production libraries. Table I gives the different SRAM instances considered in this study. A total of 512 test chips packaged in SBGA cavity down packages have been considered for the real-time experiment setup (Figure 2), representing more than 7 Gbit of memory capacity under test. TABLE I. Name SP-RAM 1 SP-RAM 2 DP-RAM PROMO40V5 SRAM INSTANCE LIST Capacity 5 Mbit 2 MBit 5 Mbit 2 MBit 896 kbit Layout cell Area (µm2) Nominal Core voltage (V) 0.374 0.299 0.741 1.1 V SP RAM2 2 Mbit SP RAM2 5 Mbit SP RAM1 5 Mbit SP RAM1 2 Mbit DP RAM1 896 kbit Figure 1. Layout (left) and die (right) of the PROMO40v5 test chip (area 5.1×4.7 mm2) fabricated by STMicroelectronics in CMOS low power 40 nm technology. The different Single-Port (SP) and (Dual-Port) SRAM instances considered in this study are indicated (total of 14,896 kbit per chip). Automatic Test Equipment Panel #1 256 devices Control PC Panel #2 256 devices Mechanical supports DUT board Figure 2. General view of the real-time experiment installed on the ASTEP Plateform. Inset: detail of a one of the 64 DUT board with 8 PROMO40v5 chips in SBGA cavity down packages. B. Real-time SER automatic test equipment The dedicated test equipment, fully compliant with all the specifications of the JEDEC standard JESD89A [6], has been designed and constructed for the purposes of this study. Figure 2 shows a general view of the full setup installed on the ASTEP platform. The system is composed of two main panels (panels #1 and #2 on Fig. 2) mounted on rigid mechanical supports allowing a possible orientation of the circuits with respect to the vertical (in the present study, the two panels have been placed horizontally on wooden pallets). Each panel consists of an assembly of 32 DUT boards, each DUT board embeds 8 test chips (see the inset of Fig. 2) with the back side of the SBGA cavities oriented upward. The core of the tester is a "all in one" integrated test board, mainly based on a CPU running under Linux and a state-of-the art FPGA. This tester, remotely controlled via an ethernet link, is able to perform all requested operations, such as writing/reading data to the chips, comparing the output data to the written data and recording details on the possible detected errors. The CPU (500 MHz) handles the high speed communication links to the control computer and the configuration of most of the hardware parts on the test board. Usually the CPU is controlled remotely, but it can be operated in standalone mode. The CPU interface to the FPGA is a very high speed connection (more than 3.3 Gbit/s), to maximize the data flow from the test core to the control computer. The FPGA controls the real-time operations under the CPU control. The test sequences and the signals to the tested DUTs are driven by the FPGA, to be sure that timings are under control for each step of the execution. The main operating frequency of the FPGA is 200 MHz. The FPGA also controls a very large amount of DDR2 memory (4Gbit in this case) for buffering during real time operations. Up to 284 signals can be programmed to interface the tested devices. This particular setup uses 205 signals for interfacing up to 1024 devices. The tester can accommodate very long cables to the tested DUTs, in this case 6 meters high speed ribbons are used. Finally, the tester hardware embeds also the peripherals needed for the test monitoring, such as current/voltage sensing, temperature monitoring and control and external synchronization. External power supplies integrated to this setup are Agilent N6700B with four high-performance and precision DC power modules. Accuracies of the power supplies programming and measurement is 0.06% for the voltage values and 0.1% for the current ones. The test sequences (algorithms) for the test can be changed "on the fly", depending on the needs and the DUT response to radiation. For the present experiment, the specific high speed (low dead time) dynamic test algorithm, illustrated in Figure 3, has been considered. After initializing the full memory plan with the considered test pattern, the tester searches for error in loop until an error is detected. This loop, which corresponds to a complete scan of the full memory plan (2×256 chips for the two arrays), is performed one time every ~2.5 s. When an error is detected, the tester reads and verifies the full memory to determine the nature of the error and eventually discriminate soft errors from Single-Event Latchup (SEL) or Single-Event Failure Interrupt (SEFI) events. As shown in Fig. 3, we adopt an arbitrary threshold of 64 simultaneously detected flips to continue the test (soft error(s) detected) or to stop the measurement cycle if errors cannot be corrected (SEFI or SEL Figure 3. Dynamic algorithm used to search and to classify single-event errors during the irradiation (here under natural terrestrial environment). High Voltage distribution HD Polyethylene box (8 cm thick) Lead rings (thickness 5 cm) High pressure He3 detector tube LND 253109 Canberra ACHNP97 charge amplifier Polyethylene coaxial tube (2.5 cm thick) Keithley KUSB 3116 acquisition module High voltage source Low voltage source Figure 4. Left: Front view of the Plateau de Bure Neutron Monitor (PdBNM) showing the three cylindrical 3He detectors surrounded by polyethylene and lead materials [5]. Right: PdBNM response (sum of the thee detectors expressed in counts/h) recorded from March 2011 to January 2012. Data are uncorrected from atmospheric pressure and averaged over one hour. The averaged value (304,073 counts/h) of the hourly counting rate during this period indicates an acceleration factor of 6.08 with respect to the reference location New-York City [5].The interruption of data recording in July/August 2011 corresponds to a maintenance period. The peak at ~350,000 counts/h on December 17, 2011 corresponds to the passage of the Joachim storm in France (depression peak at 730 hPa). detected). For the 40 nm SRAM under test, the probability to detect, in the same read loop, one or several soft error events involving more than 64 bit flips is quasi null, thus justifying this threshold value adopted in the error detection algorithm. C. Atmospheric neutron flux monitoring The ASTEP platform (latitude +44° 38’ 02’’, longitude East 5° 54’ 26’’, altitude 2552 m [7]) is characterized by an average acceleration factor (AF) of the atmospheric neutron flux (with respect to New-York City, NYC) experimentally measured at 6.3 during the installation of the Plateau de Bure Neutron Monitor in 2008 (Figure 4 left) [5]. Figure 4 (right) shows the PdBNM counting rate and the atmospheric pressure during the period of the real-time SER experiment, evidencing up to ~30% variations for both signals which are perfectly anti-correlated. This is due to the development of the atmospheric particle showers which is closer to the ground surface when the pressure (measuring the height of the air column at the vertical of the site) is lower. From data of Fig. 4 and following the procedure explained in [5], we are able to accurately re-estimate the acceleration factor for the testing period [March 2011, January 2012] to 6.08. This value is slightly reduced since 2008 due to the increase of the solar activity (progression of the solar cycle #24), the neutron flux at ground level and the solar activity being anti-correlated. This value is also nearly identical to the value given by the neutron flux calculator [8] referenced in the JEDEC standard [6]: considering the average value of atmospheric pressure of ~745 hPa, and a 50% solar modulation, one obtains an acceleration factor of 6.06 for the ASTEP location. Our experimental value AF = 6.08 will thus be considered in the following to express the measured SER values with respect to the reference location New-York City. III. REAL-TIME SER RESULTS In the following, all numerical SER results have been normalized by a common arbitrary scaling factor, set lower than 3×. The real order of magnitude for the reported data is thus not significantly altered. For the purposes of the real-time experiment, the different SRAM instances have been biased at their nominal supply core voltage of 1.1 V; a checkerboard pattern (alternating logical 0 and 1 into the two directions of the physical memory plan) has been written at the beginning of the test into the SRAMs. Figure 5 (top) shows the cumulative number of events and bit flips detected in the two single-port SRAM instances versus test duration (expressed in MBit×h). A data analysis summarized in Table II shows that a total of 40 events (respectively 36 events) has been detected for SP-RAM1 (resp. for SP-RAM2) in 6702 h of operation, representing 105 bit flips (resp. 103 bit flips). For the dual-port DP-RAM instance (data not shown), only 5 events have been detected for a total of 8 bit flips. No Single-Event Failure Interrupt (SEFI), Single-Event Latchup (SEL) or microlatchup events have been detected for the three instances. Due to the limited number of MBit under test for the DP-SRAM, the number of detected events is clearly not enough sufficient to be statistically representative; results will thus be analyzed in a further study after accumulating ~10 times more data. Figure 5 (bottom and inset) shows the occurrence of the events as a function of their multiplicity. Single bit upsets are considered as events of unit multiplicity, two cell upsets as events of multiplicity 2, etc. The analysis of these data shows that events with multiplicities above or equal to 2 represent about the half of the detected events but, at the same time, more than 80% of the total number of bit flips. These results, obtained for the first time on 40 nm SRAM circuits from real- 60 40 100 Altitude SEE Test European Platform 80 60 40 20 20 0 0 SP-RAM1 SP-RAM2 15 10 5 0 0 5 Cumulated number of events 80 40nm SRAM technology Number of detected events Event multiplicity Cumulated number of bit flips 100 10 15 20 22 21 20 9 8 7 6 5 4 3 2 1 0 SP-RAM1 SP-RAM2 1 2 3 4 5 6 7 8 9 10 11 16 17 Event multiplicity 6 Cumulated number of Mbit.h (x10 ) Figure 5. Cumulated number of events, bit flips (top) and event multiplicity (bottom) as a function of experiment duration expressed in number of Mbit.h for the two single-port SRAM instances defined in Table I. Single Bit Upsets (SBU) are counted as events of unit multiplicity. Right inset: histogram of the event multiplicities for the two SP-RAM instances. TABLE II. EXPERIMENAL RESULTS FOR THE REAL-TIME SER 40NM EXPERIMENT ON THE ASTEP PLATFORM. SER VALUES ARE GIVEN FOR NEW-YORK CITY CONDITIONS AND NORMALIZED BY A COMMON ARBITRARY SCALING FACTOR. Start time (UTC) Reporting time (UTC) Test duration in days Test duration in hours Downtime in hours Effective test duration in hours Nominal VDD voltage in core (V) Temperature (°C) Test chip under test SRAM instances Chip capacity in Mbit MBit under test Cumulated number of Mbit×h Total number of events Total number of Single Bit Upset (SBU) Total number of Multiple Cell Upsets (MCU) / MCU flips Total number of bit flips Total number of Single-Event Failure Interrupt (SEFI) Total number of Single Event Latchup (SEL) SER in bit flips [FIT/Mbit] lower/upper confidence limits at 90% SER in Events [FIT/Mbit] lower/upper confidence limits at 90% SEL [FIT/Mbit] lower/upper confidence limits at 90% time measurements under natural radiation, reveal the extreme importance of multiple cell upsets at ground level for such a deca-nanometer technology. Figure 6 shows the physical bitmaps of these different MCUs in the memory plan, with multiplicities ranging from 2 to 17. The four cases with the largest multiplicities (≥ 10) of a SP-RAM1 7.0 3584.0 2.28×107 40 21 19 / 84 105 0 0 759 648 / 892 289 225 / 376 0 0 / 22 3/11/2011 0:57 01/20/2012 15:00 315.6 7574 872 6702 1.10 20.0 512 SP-RAM 2 7.0 3584.0 2.28×107 36 20 16 / 83 103 0 0 747 637 / 880 261 200 / 345 0 0 /22 DP-RAM 0.886 448.0 2.87×106 5 3 2/5 8 0 0 459 269 / 828 287 150 / 603 0 0 / 172 total of five detected correspond to the SP-RAM2 instance, which is a high-density SRAM with a 25% reduced cell area with respect to the standard one (SP-RAM1). This is coherent with the increase of the MCU sensitivity when increasing the technological integration and thus when reducing the memory cell area. SP-RAM1 and SP-RAM2 instances also exhibit a ❸ 1(×4) 2(×4) 1(×3) 2(×2) ❺ 2000 ❹ 1(×2) 2(×2) ❼ 1(×1) 2(×3) ❹ 1(×0) 2(×1) ❿ ❻ Soft-Error Rate SER (FIT/Mbit) ❷ SP-SRAM1 1800 1600 1400 1200 1000 800 600 400 200 ×10 6 0 0 1(×5) 2(×0) ⓫ ⓫ 6 8 10 12 14 16 18 20 22 Cumulated number of MBit.h 1(×0) 2(×1) 2000 ❿ 1800 1(×0) 2(×1) 1(×0) 2(×1) 1(×0) 2(×1) 4 1(×2) 2(×0) ⓱ 1(×1) 2(×0) Figure 6. Physical bitmaps of the different MCUs detected for the two SPRAM types (SP-RAM1 and SP-RAM2) during the real-time experiment. Circled numbers indicate the event multiplicity, bold numbers 1 and 2 indicate the SP-RAM type and values in parenthesis give the occurrence of the drawn MCU per instance. similar number of SBU (respectively 21 and 20) and a slightly different number of MCU events (resp. 19 and 16), representing a total of 84 and 83 bit flips, respectively. The average number of bit flip per MCU is thus equal to 4.4 for SP-RAM1 and 5.2 for SP-RAM2, evidencing that the event probability is slightly less for high density than for standard SRAM but, at the same time, that the average size of these events is higher for instance 2 than for instance 1. The topological shape of the MCUs detected for both instances can be explained by the combination of the SRAM layout (alternative structure of vertical p-wells and n-wells) with the checkerboard pattern used to fill the memory plan [9]. This is the reason why one can observe, for example, numerous horizontal pairs of adjacent cells (impact on the sensitive N-MOS drain of two adjacent cells, these two drains being located in the same vertical p-well) vertically aligned and a systematic alternating of sensitive and not sensitive horizontal rows (effect of the physical checkerboard). For all events characterized by a large multiplicity (≥5), it is clear that MCUs are preferentially in columns, due to the mechanisms charge diffusion-collection (and possibly the bipolar amplification) that propagate into the well directly impacted by the ionizing particle at the origin of the observed MCU. Figure 7 shows the convergence of the SER for the two standard and high-density SP-SRAMs as a function of test Soft-Error Rate SER (FIT/Mbit) 1(×1) 2(×2) 2 SP-SRAM2 1600 1400 1200 1000 800 600 400 200 0 0 2 4 6 8 10 12 14 16 18 20 22 ×106 Cumulated number of MBit.h Figure 7. Convergence of the Soft-Error Rate (SER) during the real-time experiment for the two instances SP-RAM1 and SP-RAM2. The upper and lower limits of the SER confidence interval for 90% based on the chi-squared distribution are also plotted. All values are normalized by a common arbitrary scaling factor. duration. The convergence is less regular than previously observed on other technologies (130 to 65 nm) [2-4], due to the occurrence of very large multiplicity MCU events (≥ 10) introducing sudden increases of the SER (staircases or “kinks” on the curve). From these figures, it is clear that the duration of the real-time experiment should be ideally increased to smooth by averaging the impact on the SER of (rare) MCU events of large multiplicities. We report in Table II values of the SER determined at this stage of the experiment, expressed in bit flips and in events. The upper and lower confidence intervals at 90% level based on the chi-squared distribution are also indicated in order to estimate the experimental error margins. These values must be further corrected from the contribution of the internal chip radioactivity (alpha-particle emission) to be interpreted as neutron-induced soft-error rates (see next section). IV. ACCELERATED TESTS AND TIARA SIMULATION For the specific purposes of the study, the test chip PROMO40v5 was extensively characterized using both neutron and alpha accelerated tests in separate test campaigns conducted at the TRIUMF Neutron Facility at the University of British Columbia [10] and at STMicroelectronics (Crolles), TABLE III. EXPERIMENAL RESULTS FOR THE SER MEASUREMENTS USING ACCELERATED TESTS (VALUES ARE NORMALIZED BY A COMMON ARBITRARY SCALING FACTOR) SER characterization technique SER definition SP-RAM1 SP-RAM 2 DP-RAM SER in bit flips 880 1038 665 [FIT/Mbit] Accelerated neutron irradiation * at TRIUMF facility SER in Events 360 391 427 [FIT/Mbit] SER in bit flips 471 780 434 [FIT/Mbit] Accelerated alpha-particle irradiation 241 ** using an Am source SER in Events 435 670 433 [FIT/Mbit] * 2 ** 2 Extrapolation: 13 n/cm /h Combined with alpha-emissivity measurements (0.00092 alpha /cm /h) at wafer-level performed with a XIA UltraLo-1800 alpha particle counter respectively. Several test chips packaged into the same SBGA cavity down package and originated from the same technological lot than the chips used in the real-time setup have been characterized with also the same core hardware tester, software, test algorithm and test conditions (checkerboard pattern, VDD = 1.1 V). For the accelerated neutron test, the average flux during the experiment was 2.6×106 n/cm2/s above 1 MeV. Concerning the accelerated alpha-particle test, it was performed with an Am241 isotope source with an activity of 3.7 MBq (100 µCi). Table III summarizes the different values obtained from these accelerated SER measurements in terms of bit flip and event SER. Results are expressed for NYC conditions for the neutron-SER; alpha-SER values are the result of combined irradiation tests using the americium source and alphaemissivity measurements at wafer-level performed with an XIA UltraLo-1800 alpha particle counter. Such a combination of techniques associated with a modeling and simulation work as described in [11-12] allows us to be very confident on the alpha-SER values extracted, even if no underground test has been already performed for the present 40 nm test chip. Accelerated neutron irradiation results of Table III show that close values are obtained for the neutron event SER related to the two SP-SRAM instances, whereas SP-RAM2 shows a slightly larger sensitivity to MCU events than SP-RAM1 instance, as evidenced in the real-time experiment. Concerning the alpha-SER, much larger values both in events and in bit flips are clearly measured on the high-density instance with respect to the standard one, suggesting that the robustness of the high-density SRAM is ultimately inferior to the one of the standard cell. From these alpha-SER values, real-time SER results from Table II can be corrected from the contribution of the internal chip radioactivity, following the equation [3]: - | = real-time | − for which a 30% discrepancy between accelerated and realtime characterizations was systematically observed (see also Figure 10 in next section). On the other hand, 30% variations in the results remain very acceptable with respect to all the possible causes of divergence between the two experimental approaches [13]. In complement to the accelerated tests, we performed neutron SER simulation for the standard layout SRAM using TIARA, our C++ object-oriented Monte-Carlo simulation platform for the analysis of circuit response to various radiation environments and particle types. The simulation methodology has been described in detail in [14]. Additional information about the SRAM geometry and materials can be also found in [15]. Figure 8 shows the evolution of the neutron SER as a function of the number of primary neutrons (JEDEC atmospheric reference spectrum [6]) incident on 20×20 SRAM TABLE IV. NEUTRON-SER DEDUCED FROM DATA OF TABLE II AND CORRECTED FROM THE CONTRIBUTION OF ALPHA-PARTICLE EMISSION (VALUES ARE NORMALIZED BY A COMMON ARBITRARY SCALING FACTOR). SER in bit flips [FIT/Mbit] SER in events [FIT/Mbit] SP-RAM1 SP-RAM 2 DP-RAM 682 618 388 217 151 216 - where AF=6.08 is the acceleration factor of the ASTEP platform. Final results for the neutron-SER estimated from this equation are given in Table IV. The comparison of these results with data of Table III highlights a relatively large discrepancy between the two approaches: the accelerated SER is found ~30% larger than the real-time SER for SP-RAM1 and 68% larger for SP-RAM2 (71% also for DP-RAM). On one hand, these results lead to a conclusion similar to those of our previous studies on the 130 nm [2] and 65 nm [3] nodes Figure 8. Soft-Error Rate (SER) as a function of the number of incident primary neutrons obtained from TIARA Monte Carlo simulation. The upper and lower limits of the SER confidence interval for 90% based on the chisquared distribution are also plotted. The values are normalized by a common arbitrary scaling factor. Single-Port SRAM 100 90 80 Number of bit flips 40 nm (VDD = 1.1 V) Standard cell Checkerboard pattern 65 nm (VDD = 1.2 V) 130 nm (VDD = 1.2 V) 70 60 50 40 Altitude SEE Test European Platform 30 20 10 Neutron SER in bit flips (FIT/Mbit) 110 Single-Port SRAM 1000 800 Standard cell Real-time SER (ASTEP) TIARA Monte Carlo simulation Accelerated SER (TRIUMF) 600 400 200 0 130 nm 0 4 8 12 16 20 24 28 6 Figure 9. Cumulated number of bit flips as a function of experiment duration for the 130, 65 and 40 nm SP-SRAMs (standard cell). Tests have been conducted on the ASTEP platform under nominal conditions for the three technologies: room temperature, checkerboard test pattern and VDD = 1.2 V (130 and 65nm) or 1.1 V (40 nm). Experiment periods are [March 31, 2006 – November 6, 2006] for the 130 nm, [January 21, 2008 – May 7, 2009] for the 65 nm and [March 11, 2011 – January 20, 2012] for the 40 nm. In this last paragraph, we confront the different results of the present study with data measured in the past on the ASTEP platform and at the TRIUMF facility or simulated using the TIARA code for the 130 and 65 nm SRAM technologies [2,3,4,14,15]. Figure 9 shows the cumulated distributions of bit flips obtained during the different real-time experiments 2.4 Standard cell 2.2 2.0 Emissivity measurements at wafer level (XIA UltraLo-1800) 1600 1.8 1.6 1200 1.4 800 1.2 1.0 400 Underground measurements (LSM) Accelerated 241 test (Am ) 0.8 0 0.6 130 nm 65 nm 40 nm 2 SYNTHESIS AND SER TRENDS Single-Port SRAM 2000 -3 V. Figure 10. Comparison of the neutron soft-error rate values obtained from real-time measurements on ASTEP, TIARA Monte Carlo simulation and accelerated test at TRIUMF facility for standard density SRAMs manufactured in 130, 65 [4] and 40 nm. The real-time values are corrected from alpha-particle contribution directly deduced from undergound SER measurements (130 and 65 nm) or estimated from the combination of accelerated tests (Am241 source) and emissivity measurements at wafer level (40 nm). All these values are normalized by a common arbitrary scaling factor. α-particle emissivity (x10 α/cm /h) cell array (checkerboard pattern). The curve indicates a convergence of the SER around 486 FIT/Mbit. A detailed analysis shows that MCU events represent 54% of the total number of bit flips, with event multiplicities ranging from 2 to 7. These values are lower than those observed on ASTEP, for memory, 682 FIT/Mbit and 80% respectively with event multiplicities detected up to 17. We think that the origin of this discrepancy may be due, in part, to the increase in the sensitivity of the 40 nm SRAM of other types of atmospheric particles (protons, muons) [16], not already taken into account the simulation. Another possible cause may be the physical model currently implemented in TIARA (diffusion-collection model [14]). This model does not take into account, in its current version, the mechanism of bipolar amplification potentially responsible, at the level of technological integration, of upset propagation in the impacted wells and consequently at the origin of large multiplicity events in columns (Figure 6). The deficit in the number of large MCU events in the simulation should be the signature of this physical model limitation for the present 40 nm node. As a reminder, for the 65 nm technology, TIARA simulation perfectly fits the experimental neutron SER within a few percents of uncertainty only. The quantitative impact of the other types of particles and the bipolar amplification on the SER will be investigated in a future dedicated work. 40 nm Technological node 32 Cumulated number of Mbit.h (x10 ) α-SER in bit flips (FIT/Mbit) 0 65 nm Technological node Figure 11. Evolution of the soft-error rate due to the internal chip radioactivity (alpha-particle emission) with the SRAM technological node. SER values are directly deduced from undergound SER measurements conducted at the Underground Laboratory of Modane (LSM) for the 130 and 65 nm technologies and deduced from the combination of accelerated tests (Am241 source) and emissivity measurements for the 40 nm one.These SER values are normalized by a common arbitrary scaling factor. The alphaparticle emissivity values measured at wafer-level using a XIA LLC ultra low background alpha-particle counter (model UltraLo-1800) are also indicated for the three technologies (average of several wafer measurements). conducted in altitude. As previously noted for the convergence of the SER (section III), this figure highlights the increasing difficulty to extract a unique slope (i.e. a unique SER value) from such staircase distributions when pushing the technological integration. This is due to the emergence of large multiplicity events, detected for the first time for the 65 nm SRAM (up to 7 cell upsets) and, currently, of very large events (up to 17 cells) for the 40 nm. For comparison, only a few events involving two adjacent cells were detected for the Total bit flip SER (FIT/Mbit) 5000 130, 65 and 40 nm SRAM (SP-SRAM) 4000 alpha alpha + neutron neutron ASTEP acceleration factor AF decreasing by factor ~2 3000 decreasing by factor ~5 2000 1000 0 130 U65 65 U130 Underground (LSM) 40 espace 130SSER65 65SSER40 40 espace 130Deconv65 65Deconv40 40 -U40 SSER130 Deconv130 ASER 241 ( Am) Altitude (ASTEP) Normalized (New-York City) Figure 12. Synthesis of experimental real-time SER values obtained for 130, 65 and 40 nm SP-SRAM from altitude and underground experiments and normalization of the SER at the reference flux of New-York City (sea-level) taking into account i) the alpha contribution for the altitude test and ii) the ASTEP acceleration factor AF for the neutron flux in altitude. 130 nm technology. All these multiple cell events introduce irregular staircases on the bit flip distributions, then forcing us to consider much longer experiment durations (and/or larger setups to accumulate more Mbit×h) for ultra-scaled technologies. This point may be a potential experimental difficulty (or an economic constraint) for future real-time experiments with 32 nm SRAMs and below. Figures 10 and 11 show the evolution of the neutron and alpha-SER, respectively, for the three generations of circuits (standard cell single-port SRAMs). Despite the differences between the various estimations (real-time, accelerated test and simulation) already discussed in section IV, Figure 10 highlights a global trend for the neutron-SER which is found to be minimal for the 65 nm node and to re-increase of about a factor 2 for the 40 nm technology. Note that these different experimental or simulation approaches give the same tendency and that accelerated neutron tests systematically overestimate the SER with respect to real-time experiments. Such an overestimation is currently not understood. In the same time, Figure 11 demonstrates a constant decreasing evolution of the alpha-SER which has been reduced by a factor ~4 between the 130 nm and the 40 nm nodes. This tendency is well correlated with the values of alpha-particle emissivity measured at waferlevel for these technologies, evidencing a strong decrease from typical values of 2.3×10-3 alpha/cm2/h for the 130 nm technology to 0.92×10-3 alpha/cm2/h for the 40 nm one. From a manufacturer point-of-view, this illustrates the important effort conducted these ten last years to reduce the alpha emission rate for the semiconductor processing and packaging materials (drastic selection of the materials and chemical precursors used, in-line characterization, etc.). A future underground experiment will be therefore required to confirm, via real-time SER measurements, this estimated value of the alpha-SER for the current 40 nm SRAM technology. Finally, Figure 12 shows in a different form the data of Figs. 10 and 11 and provides a global comprehensive overview on the three technological generations 130, 65 and 40 nm in terms of evolution of alpha and neutron soft error rates. Our results clearly evidence a decrease by a factor ~5 of the alpha-SER between the 130 and 40 nm technologies and a reduction by a factor ~2 of the total (neutron+alpha) SER. Another interesting result is the evolution with the technological integration of the respective weights of the alpha and neutron contributions in the overall SER. Fig. 12 shows that for the 130 and 65 nm nodes, the alpha-SER was highly dominant (up to 80% of the total SER value), while for the 40 nm technology, the neutron-SER now represents more than 60% of the total SER. This result shows in particular that the 40 nm design is not just a shrink of the 65 nm one; such a trend is certainly the results of a complex combination of different effects reflecting not only the changes performed at material level but also the emergence of new sensitivity mechanisms (in particular the bipolar amplification propagating upsets in same type semi-conductor regions – wells) when pushing the scaling down of the circuits. VI. CONCLUSION In conclusion, we reported for the first time the complete results concerning a real-time SER experiment involving more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and exposed ~7500 h to the natural terrestrial environment on the ASTEP platform. Our results show the extreme importance of multiple cell upsets for this technology (representing 80% of the total of the bit flips detected) and the difficulty that the large multiplicity events represent to extract a confident SER value from the experiment bit flip distribution in time. Using complementary measurements (alpha-particle irradiation and emissivity measurements at wafer level), we were able to separate neutron from alpha-particle contributions and to estimate the soft-error rate of this 40 nm SRAM to 682 FIT/Mbit for atmospheric neutrons and 471 FIT/Mbit for alpha-particle emission. Compared to previous 130 nm and 65 nm technologies from the same manufacturer and characterized in the same conditions, the study confirms the continuous and drastic reduction of the alpha-SER, very-well correlated with the reduction of the alpha-particle emissivity measured at material (wafer) level. Concerning the evolution of the neutron-SER and after a constant reduction with the circuit downscaling until the 65 nm node, we observed a significant increase of this neutron-SER for the 40 nm SRAM, possibly due to a non negligible sensitivity to other atmospheric particles or to the emergence of new mechanisms at these deca-nanometer dimensions. Future experimental and modeling work is clearly required to investigate and quantify these new mechanisms for future ultra-scaled technologies. ACKNOWLEDGMENTS The authors would like to thank D. Gautier and F. Vermont (EASII-IC, Grenoble, France) for their contribution to the development of the real-time setup and B. Dwyer-McNally (XIA LLC) for his support concerning the implementation of the UltraLo-1800 at IM2NP Labs and his expertise in the field of alpha-particle metrology. The logistical support of the Institute for Radioastronomy at Millimeter Wavelengths (IRAM) is finally gratefully acknowledged. REFERENCES [1] [2] [3] [4] [5] [6] J.F. Ziegler, H. Puchner, SER – History, Trends and Challenges, Cypress Semiconductor, 2004. J.L. Autran, P. Roche, J. Borel, C. Sudre, K. Castellani-Coulié, D. Munteanu, T. Parrassin, G. Gasiot, J.P. Schoellkopf, "Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130nm SRAM", IEEE Transactions on Nuclear Science, 2007, Vol. 54, n°4, p. 1002-1009.J.L. Autran et al. IEEE Transactions on Nuclear Science, Vol. 56, 2009, Vol. 56, n°4, p. 2258-2266. J.L. Autran, P. Roche, S. Sauze, G. Gasiot, D. Munteanu, P. Loaiza, M. Zampaolo, J. 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