Soft Switching Three Level Inverter (S3L Inverter)
Manfred W. Gekeler
HTWG KONSTANZ
HOCHSCHULE KONSTANZ TECHNIK, WIRTSCHAFT UND GESTALTUNG
UNIVERSITY OF APPLIED SCIENCES
Brauneggerstrasse 55
D – 78462 Konstanz; Constance, Germany
Phone: +49 / (0) – 7531.206.220
Fax: +49 / (0) – 7531.206.87.220
E-mail: gekeler@htwg-konstanz.de
URL: http://www.htwg-konstanz.de
Keywords
«Voltage Source Inverter (VCS)», «Multilevel Converters», «Converter Circuit», «Soft Switching»,
«ZCZVS Converters», «Energy Efficiency», «Pulse Width Modulation»
Abstract
The Soft Switching Three Level Inverter – abbreviated to S3L Inverter – was first introduced in 2011.
It is a novel circuit topology for PWM inverters, whose areas of application include electrical drives
and grid-tie inverters for photovoltaic installations and wind power plants, and for power supplies. It is
of very simple design and therefore inexpensive. It is implemented completely as soft switching and
hence offers very low switching losses. This means that its efficiency is very high, and it can achieve
very high values for the switching frequency. This paper begins by describing how the device
functions. It then goes on to discuss specialised methods of control. A variant of the S3L Inverter with
a deactivatable snubber circuit is presented. A quantitative comparison between a well-known hard
switching NPC 3-level inverter and the novel S3L Inverter using 90 kVA (three-phase) prototypes
illustrates the advantages of the S3L inverter.
Introduction
PWM (pulse width modulated) inverters have been used for a long time in electrical drives, as grid-tie
inverters for photovoltaic installations and wind power plants, and in power supplies. They are usually
implemented as 2-level or as 3-level inverters and are typically operated with switching frequencies in
the range from a few kHz to about 20 kHz.
State of the Art
In the 2-level and 3-level inverters mentioned above, the power semiconductors that are employed –
MOSFETs, IGBTs, GTOs and IGCTs – are usually operated in hard-switching mode. The resulting
switching losses add up to give significant average values for the power dissipated [1], especially for
high values of switching frequency, and thus limit the efficiency.
A first approach towards reducing the switching losses consists of the implementation of “soft” instead
of “hard” switching so as to achieve low-loss switching [2]. There been numerous suggestions
regarding this, e.g. [3], [4], [5]; they have not really gained acceptance in practice.
Another approach consists of the use of 3-level inverters [6], [7], [8], [9]. The fact that the output
voltage has 3 levels means that lower switching frequencies can be used. The voltage jumps that occur
on switching the power semiconductor are reduced by a factor of 2, and the switching losses are
correspondingly smaller. These 3-level inverters have therefore represented the state of the art for
many years and are available in a variety of designs as “Neutral Point Clamped Three Level Inverters“
(„NPC Inverters“).
Soft Switching Three Level Inverter (S3L - Inverter)
The Soft Switching Three Level Inverter (abbreviated to S3L Inverter) was presented for the first time
in 2011 [10]. It combines the proven technology of the 3-level inverter with the advantages of soft
switching. In the course of its development, we succeeded in finding a particularly simple and hence
inexpensive circuit topology. Its losses are very small, its efficiency is particularly high, and it allows
the use of very high values for the switching frequency. Limitations in the rate of current increase di/dt
and the rate of voltage increase du/dt are additional advantageous properties.
Design of the S3L Inverter
Fig. 1 shows the schematic circuit diagram of the S3L Inverter. The 4 IGBTs V1 to V4 and the 4
diodes D1 to D4 form a 3-level inverter of the kind known as an NPC II inverter [7] or as a T-type
inverter [11]. For the load voltage uLoad one obtains the three values + Ud/2 , 0 and – Ud/2 . By using an
appropriate PWM control method, it is possible to generate an approximately sinusoidal load current
with a specifiable frequency and amplitude in the usual manner.
Snubber Circuit
Dh1
Ud /2
V1
C1
D2
Dh2
L
D1
V2
0
Dh3
Ud /2
Dh4
V3
C2
D3
V4
D4
Load
uLoad
Fig. 1: Schematic circuit diagram of the „Soft Switching Three Level Inverter“ („S3L Inverter“)
Now a novel snubber circuit has been added to this 3-level inverter; see Fig. 1. It consists of just seven
simple passive components: the snubber inductor L, the two snubber capacitors C1 and C2, and the
four snubber diodes Dh1 to Dh4. It is of note that the snubber capacitors C1 and C2, the snubber
diodes Dh1 to Dh4 and the snubber inductor L are very small.
How the S3L Inverter functions
Since the S3L Inverter was only presented to the public in 2011 [10], [12] and is therefore not yet well
known, its method of function shall be described in the following in abbreviated form. A detailed
description can be found in [10].
Switching states
The three switching states are specified first in Table I. Also specified are which of the 4 IGBTs are
switched on (ON) and which are switched off (OFF).
Commutation processes
For the purpose of analysis, the changeovers between these switching states, i.e. the commutation
processes, are now considered in more detail. There are 12 of these in total, 8 of which are allowed
and 4 of which are not allowed (Table II).
Table. I: Switching states of three level inverter
Switching state:
uLoad
+
+ Ud/2
Conducting:
V1 or D1
V1
V2
V3
V4
ON
OFF
ON
OFF
0
0
V2 and D2
or V3 and D3
OFF
ON
ON
OFF
–
– Ud/2
V4 or D4
OFF
ON
OFF
ON
Table II: Commutation processes of S3L Inverter
Load current positive
Commutation
Allowed Involved
V1 → D3, V3
yes
C2
D3, V3 → V1
yes
C2
D3, V3 → D4
yes
C1
D4 → D3, V3
yes
C1
V1 → D4
no
D4 → V1
no
-
Load current negative
Commutation
Allowed
Involved
D1 → D2, V2
yes
C2
D2, V2 → D1
yes
C2
D2, V2 → V4
yes
C1
V4 → D2, V2
yes
C1
D1 → V4
no
V4 → D1
no
-
The commutation processes with a load current of zero can also be specified as special cases. For
reasons of symmetry (zero load current), three of these suffice.
Table III: Commutation processes of S3L Inverter with zero load current
Commutation
V1 → D3, V3
D3, V3 → V1
V1 → D4
Allowed
yes
yes
no
Zero load current
Involved
Commutation
C2
D1 → D2, V2
C2
D2, V2 → D1
D1 → V4
Allowed
yes
yes
no
Involved
C1
C1
-
Each of these commutation processes operates in a slightly different way. By way of explanation, one
commutation process shall be described in more detail as an example. The sequence of events is
illustrated by highlighting the current-carrying pathways in red; see Fig. 2. It shall be assumed that the
load current remains approximately constant during a commutation process.
Commutation V1 → D3, V3
Before the commutation process begins, V1 carries the positive load current I Load. V3 is switched on
(but does not carry any current, because of diode D3); V2 and V4 are switched off. The output
terminal is connected to the positive terminal of the input DC voltage. The capacitor C1 is discharged;
the capacitor C2 is charged to – Ud. The current in the snubber inductor L is zero. (Fig. 2a)
The commutation process V1 → D3, V3 begins when V1 is switched off. At the same time, V2 is
switched on. V3 remains switched on; V4 remains switched off. The commutation process that then
follows can be split into two time periods.
During time period 1 ( t0 ≤ t < t1 ) two current circuits arise. C2 forms an oscillating circuit with V2,
D2, L, Ud/2 and Dh4. At the same time, load current I Load flows through C2, the load, the midpoint of
Ud, Ud/2 and Dh4. The two current circuits are superposed on one another (Fig. 2b). The important
thing is that the current through V1 falls very rapidly to zero, whereas the voltage at V1 only rises at a
limited rate (see Fig. 3b), so that the product of the voltage and the current, i.e. the power dissipated,
assumes only very small values. The process of switching off V1 is therefore soft switching.
The time period 1 of the commutation process ends when C2 is discharged and D4 begins to conduct.
At approximately the same time, the current through inductor L falls to zero, D2 blocks, V3 and D3
begin to conduct. Since a constant voltage with a value of Ud/2 is now applied to L during this time
period 2 ( t1 ≤ t < t2 ), the current through it increases linearly with time; conversely, the current
through D4 falls linearly with time (Fig. 2c).
As soon as the current through D4 reaches zero and, at the same time, the current through the snubber
inductor assumes the value of the load current, the commutation period comes to its end. D4 is
blocking, V3 and D3 are carrying the load current. C2 is discharged (Fig. 2d).
Fig. 2 shows in red the parts of the S3L Inverter through which current flows during the different time
periods of the commutation under consideration. Fig. 3 shows the corresponding variation with time of
several voltages and currents. High values of iV1 and uV1 do not occur simultaneously; hence the
switching process is soft switching and the switching losses remain very small.
0 0
V1
u V1
L
0
iL
C2
Load
u C2
u Load
a) Before commutation
0 0
V1
u V1
L
0
iL
C2
Load
u C2
u Load
a)
b)
c)
d)
Fig. 3a): black: uLoad ; red: iL ; blue: uC2
a), b), c), d): see Fig. 2
b) Commutation period 1
0 0
V1
u V1
L
0
iL
C2
0 0
Load
u C2
u Load
c) Commutation period 2
0 0
V1
u V1
L
0
iL
C2
0 0
Load
u C2
u Load
a)
b)
c)
d)
Fig. 3b): red: iV1 ; blue: uV1
a), b), c), d): see Fig. 2
d) After commutation
Fig. 2: Commutation V1 → D3, V3
Fig. 3: Commutation V1 → D3, V3
It may be noted that all the changes in the current through V2, D2, V3 and D3 take place only at a
limited rate di/dt. The process of switching on V3 is also soft switching; the power dissipated is only
small. Also of importance is the fact that the current through D4 (also D1 to D3) only falls with
limited di/dt; this reduces considerably the reverse recovery charge and the losses resulting from it.
The other commutation processes (Table II) operate in a similar manner. It should be particularly
emphasised that all the commutation processes operate in a soft switching manner and that there are no
limitations whatsoever on either the magnitude of the load current or the load angle (0° to 360°).
Up until now the existence of idealised conditions, i.e. loss-free inverter circuit, has been assumed. In
reality, of course, losses must be taken into account, especially in the power semiconductors. This will
be discussed in more detail at a later point.
Control of S3L Inverter
The S3L Inverter can, like any other 3-level PWM inverter, be operated with open loop control or
closed loop control. With open loop control, as it is often used in frequency inverters, for example, the
PWM is typically sinusoidally weighted. This can be done in the usual manner by means of vector
control or by using sine-triangle modulation. The result obtained in the first step is a signal with three
levels, as illustrated for a simple example as uLoad /(Ud/2) in Fig. 4a).
u Load
1
Ud /2
0
-1
S_V1 1
0
S_V2 1
0
S_V3 1
0
S_V4 1
0
Fig. 4: Control signals S_V1 to S_V4
t
S_V3
yellow: dead time
S_V4
t
t
t
t
S_V3
S_V4
S_V3
S_V4
no dead time
red: "negative
dead time"
(overlapping)
Fig. 5: Dead time and overlapping („negative dead time“)
Obtaining the control signals for the IGBTs
This signal uLoad /(Ud/2) corresponds to line 2 in Table I and specifies whether the load voltage uLoad
should assume the value + Ud/2, 0 or – Ud/2. It must now be converted into four control signals S_V1,
S_V2, S_V3 and S_V4 for the IGBTs V1, V2, V3 and V4. This is done by taking lines 4 to 7 from
Table I and converting them into time-dependent signals as illustrated in Fig. 4. It can be seen from
Table I or Fig.4 that S_V2 is given by inverting S_V1 and that S_V3 is given by inverting S_V4.
Dead time
With a hard switching 3-level inverter (i.e. an NPC II or T-type inverter), it would be essential to
ensure that V1 and V2 are never conducting at the same time; the same would apply to V3 and V4.
(Of course, V1 and V4 are also not allowed to conduct at the same time; however, according to Table
II, commutations V1 → D4 and V4 → D1 are prohibited from the outset for the SL3 Inverter in any
case.) In order to guarantee this, V1 is first switched off, and only after a brief interval, which is often
referred to as “dead time”, may V2 be switched on. The same applies to the other switchovers between
V2 and V1, and between V3 and V4. Dead time of this kind is indicated in yellow in Fig. 5.
The S3L Inverter has no need of such dead time. It proves to be extremely robust with regard to the
control signals. It can be operated either with dead time, or without dead time, or even with “negative
dead time”, that is, overlapping. The reason for this is the snubber inductor L. If, for example, V1 and
V2 are conducting at the same time, then the rate at which the current through L increases is limited to
small values between about 25 A/μs for inverters in the power range of about 100 kW and a maximum
of about 100 A/μs for inverters in the MW range.
Overlapping („Negative Dead time“)
This overlapping can be usefully employed to counter an effect that was ignored in the preceding
consideration of the commutation processes. Namely, the assumption was made here that the complete
S3L Inverter functions without losses. In reality, of course, this is not the case. All the power
semiconductors and the snubber inductor exhibit losses, as do the snubber capacitors to a smaller
degree. This means that the oscillating circuits that are formed during the various commutation
processes, from L and C1 and from L and C2, are lossy. Because of these losses, the snubber
capacitors do not fully charge to Ud or, as the case may be, do not fully discharge to zero during some
commutation processes as is actually desired. As a consequence of this, the following commutation
processes no longer take place in a fully soft switching manner. The outcome is a mixture of hard and
soft switching.
In order to explain this, the commutation process illustrated in Fig. 2 should be re-examined. The high
side IGBT V1 can only switch off in a soft manner, that is, with a du/dt that is limited by the snubber
capacitor C2, if this capacitor is charged to Ud at the moment when V1 is switched off. If this is not
the case, due to the aforementioned reasons, then the switch-off of V1 begins in a hard manner, i.e.
with a very high du/dt, and only when C2 is able to carry current does the switching process transition
to soft switching with a limited du/dt.
In practice, it turns out that this effect is evident only for small values of load current. The reason for
this is that for larger values of the load current, the losses in the oscillating circuits formed from L and
C1 or C2 are compensated by the load current; however, this is not the case for small values.
There are two ways of dealing with this effect. One way is to simply ignore it. This is permissible
because it does only arise for small load currents, and because only a part of the commutation process
occurs in a hard switching manner. It is true that switching losses do arise, as is the case for all hard
switching processes, but because the switched current has small values and only part of the switching
process occurs in a hard switching manner, these switching losses are low and can be accepted. The
prototype of the S3L Inverter that is illustrated in the following section functions in this manner and
nevertheless achieves better efficiency than a hard switching NPC inverter.
This effect can, however, be countered by the use of “negative dead time”, i.e. overlapping. That
means the commutation process shown in Fig. 2 starts with an overlapping of V1 and V2, as illustrated
in Fig. 6. This causes a current to build up in L. Thus energy is fed into the snubber inductor. Only
then is V1 switched off. The energy stored in L gives rise to the process that then follows, in which the
oscillation changes in such a way as to cause C2 to discharge to zero. This ensures that following
commutation processes take place in a completely soft switching manner.
0
V1
0
V2
0
Load
Fig. 6: blue: overlap V1, V2; red: load current
To summarise: In the simplest case, it is possible to dispense with both a dead time and an overlap
time. If it is desired that the use of soft switching be ensured for all instances of operation, an overlap
time that has a constant value for all commutation processes can be introduced. In addition, the
controller developed by HTWG Konstanz on the basis of the DSP TMS 320 F 28335 also offers the
facility to set a different dead time or overlap time for each commutation process; this could, for
example, be reset each time as a function of the instantaneous value of the load current.
Variable switching frequency
The introduction of a variable switching frequency represents an interesting possible technique for
reducing the losses and hence increasing the efficiency.
In single-phase 3-level inverters, and in 3-phase designs in which the neutral point of the load is
connected to the centre tap of the DC voltage Ud, it is observed that, for a given fixed switching
frequency, the ripple on the load current varies considerably.
This is depicted over one period of the approximately sinusoidal load current in Fig. 7. It can be seen
that the ripple on the load current in the region of the zero crossing is very small, then at about half of
the peak value it exhibits relatively large values, and in the region of the peak value it becomes small
again.
Δi = 5 A
Δi = 13A
Δi = 7 A
fsw = 34 kHz
Δi = 7 A
Δi = 3A
fsw = 12 kHz
Fig. 7: Load current with
Fig. 8: Load current with
fixed switching frequency
variable switching
frequency
Fig. 9: Variation of switching
frequency fsw between
12 kHz and 34 kHz
The smoothing inductance at the output of the inductor is typically selected such that the maximum of
this current ripple does not exceed a predefined value. However this value is then undershot by a
significant margin in the vicinity of the zero current crossing and the current peak. The following
considerations are thus based on the idea of also allowing the ripple to approach the predefined value
in the vicinity of the zero current crossing and the current peak.
The switching frequency must be adjusted in order to do this. It can now be selected to be very much
lower in the vicinity of the zero current crossing and the current peak. This causes the mean value of
the switching frequency to fall and hence the switching losses to become smaller. The reduction in the
switching frequency in the vicinity of the current peak plays the primary role in this, since the
switching losses are large here.
This is especially true for hard switching 3-level inverters, but the soft switching S3L inverter also
benefits from this technique. For despite the significantly reduced switching losses, there still remain
some small losses that can be reduced in this way by using a variable switching frequency.
The level at which the switching frequency is set depends on the time t and the electrical angle ωt , as
well as on the modulation depth m of the sinusoidally weighted PWM signal; see Fig. 10 and Eq. (1).
m = 0,5
34 kHz
fsw =
m = 0,9
12 kHz
0°
90°
180°
(
)
Ud
m sin(ωt ) − m 2 sin 2 (ωt ) (1)
ΔiLoad ⋅ LLoad
with:
f sw :
switching frequency
ΔiLoad : preset value of current ripple (= constant)
LLoad : load inductance
ω:
angular frequency of fundamental of
load current
m:
modulation depth
Fig. 10: Variation of switching frequency; modulation depth m = 0,5; 0,6; 0,7; 0,8; 0,9
Fig. 8 and Fig. 9 show the result. It can be seen that the current ripple is approximately constant and
that the switching frequency changes.
Soft Switching 3 Level – Hard Switching 2 Level (S3L-H2L) Inverter
Circuit Topology
By making a slight alteration to the switching topology of the S3L inverter, it is possible to obtain an
interesting variant of the design, which shall be referred to as a soft switching three-level – hard
switching two-level inverter (abbreviated to S3L-H2L inverter). Fig. 11 shows the schematic circuit
diagram.
OFF
0
0
OFF
out of operation
Fig. 11: S3L operation mode
Fig. 12: H2L operation mode
This topology differs from that shown in Fig. 1 in that the two IGBTs at the centre are connected
differently, and the two snubber capacitors are not connected directly to the output clamp, but are
instead connected via the two centre IGBTs and their antiparallel diodes.
With this topology, soft switching three level operation like that of the topology shown in Fig. 1 is
possible. All the remarks made previously in this paper concerning commutation processes and
methods of control remain valid in every respect. This S3L operating mode is highlighted in green in
Fig. 11.
In addition, though, there is now also the possibility of permanent blocking the two centre IGBTs. The
effect of this is to disconnect the centre tap of the input DC voltage as well as the complete snubber
circuit. This is symbolised in Fig. 12 by the circuit highlighted in red. What remains is a perfectly
normal hard switching 2-level inverter, highlighted in green in Fig. 12.
Control of S3L-H2L Inverter
The method used to control the hard switching two-level operating mode that is now possible must
switch off the two centre IGBTs. The high side and low side IGBTs, which, together with their
antiparallel diodes, now form a conventional hard switching 2-level inverter, can be controlled in
exactly the same manner as that normally used for inverters of this type. Above all, it is important that
a suitable dead time is set for this.
The switchover between S3L operation and H2L operation may be, on the one hand, long-lasting. On
the other hand, it is also possible to multible toggle between both operating modes within one cycle of
the load current, as depicted in Fig. 13. In the following section, we explain where these two toggling
techniques can be usefully employed.
H2L S3L H2L S3L H2L S3L H2L
H2L
S3L
Fig. 13: Multible toggling between S3L- and H2L- operation modes within one cycle of ILoad
Fields of Application for the S3L-H2L Inverter
One application for multiple toggling within one cycle of the fundamental oscillation of the load
current, as depicted on the left of Fig. 13, is based on the observation that for very small instantaneous
values of the load current, that is, in the vicinity of the zero crossing, soft switching is not strictly
necessary. This is because, for very small values of the instantaneous load current, the switching losses
that occur during hard switching are also only very small. Conversely, the snubber circuit exhibits its
own losses; these losses also arise for very small values of the instantaneous load current. It may
therefore be the case that, for such small currents, the losses incurred by the snubber circuit itself
might be greater than the switching losses for hard switching. This is why there is a shift to H2L
operation here.
Another possible field of application is the provision of fault ride through capability for photovoltaic
inverters. In future, these must continue to supply current to the grid even during a grid failure. The
modulation depth must be set close to zero when doing so. For 3-level inverters, this means that the
current flows almost exclusively through the two centre IGBTs. However, economic considerations
dictate that these IGBTs are dimensioned only for normal operation with a relatively large modulation
depth and hence a low current load. In an event necessitating fault ride though, their capacity would
therefore be exceeded. In order to avoid cost-intensive over-dimensioning of the centre IGBTs, it is
instead possible to toggle to H2L operation in the event of a failure, thus providing fault ride through.
Comparison of S3L Inverter with NPC I Inverter
The outstanding results that have been achieved with a 3-phase S3L inverter have already been
described in [10]. This inverter had a DC voltage of a maximum of 1000 V, an output of 20 kVA and
was operated with a switching frequency of up to 34 kHz.
In order to demonstrate the advantages of the S3L technology at higher power output levels too, a
direct comparison was made between an S3L inverter and a hard switching NPC II (T-type) 3-level
inverter. Both inverters were configured for single-phase power output of 30 kVA. The DC voltage in
both cases was 700 V; the switching frequency was 17 kHz.
Fig. 14 shows the results of the comparison. The efficiency of the S3L inverter is noticeably higher
than that of the NPC II inverter. The difference becomes clearly visible when the relative losses, rather
than the efficiencies, are compared; see Fig. 15. Of particular note is the fact that the cooling systems
for S3L inverters can be smaller dimensioned.
3
98,4
S3L
98,2
PV / PN [%]
98
eta [%]
2,5
NPC II
97,8
97,6
97,4
2
1,5
S3L
1
NPC II
97,2
0,5
97
0
10
20
Fig. 14: Comparison of efficiencies
P[kW]
30
0
0
5
10
15
20
P[kW]
25
30
Fig. 15: Comparison of relative losses PV PN
Summary
The soft switching three-level inverter (abbreviated to S3L inverter) is an innovative circuit topology
for PWM inverters. With a simple and, in principle, lossless snubber circuit, which is constructed
using just a few passive components, it avoids switching losses in the IGBTs and diodes. In
combination with an optimised PWM control method, which, among other things, works with a
variable switching frequency, it is possible to achieve very high efficiencies at the same time as a high
switching frequency, as a comparison with a hard switching NPC II inverter shows. One circuit variant
permits toggling between soft switching 3-level operation and hard switching 2-level operation.
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Conference on Power Electronics and Applications) 2011; August 2011, Birmingham, UK; ISBN
9789075815153
[12] Gekeler, Manfred W.: Weich schaltender 3 - Stufen - Pulswechselrichter mit verlustfreiem
Entlastungsnetzwerk (Soft Switching Three Level Inverter with non-dissipative Snubber Circuit (S3L Inverter));
Internationaler VDE ETG-Kongress 2011 (ETG-Fachbericht 130 Teil B), November 2011, D-Würzburg, ISBN
978-3-8007-3376-7, S. 264-270