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1
A Full Ka-Band Power Amplifier With 32.9% PAE
and 15.3-dBm Power in 65-nm CMOS
Haikun Jia , Member, IEEE, Clarissa C. Prawoto, Baoyong Chi , Member, IEEE,
Zhihua Wang, Fellow, IEEE, and C. Patrick Yue, Fellow, IEEE
Abstract— This paper presents a CMOS broadband millimeter
wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network
is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA’s output matching network,
the inductance ratio should be equal to the load/source resistance
ratio to achieve broadband impedance transformation. And
the coupling coefficient (k) of the MCR can be determined
from the no gain ripple condition. Fabricated in 65-nm CMOS
process, the PA chip achieves 32.9% peak power added efficiency,
15.3-dBm saturated output power ( Psat ), and 12.9-dBm output
1-dB compression point ( P1 dB ). The fractional bandwidth of the
PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band
(26.5 to 40 GHz).
Index Terms— Power amplifier (PA), broadband matching
techniques, coupled resonator, Ka-band, CMOS.
I. I NTRODUCTION
D
RIVEN by the ever-growing demand for broadband
mobile data traffic, various mm-wave bands ranging
from 28 GHz to 80 GHz are being evaluated for 5G cellular networks to deliver wireless backhaul connectivity over
10 Gb/s [1]. Circuit and system designs for the lower millimeter wave (mm-wave) frequency band (28 GHz∼32 GHz)
have been reported recently [2]–[8]. Power amplifiers (PAs)
are one of the most critical building blocks among those
designs. A high output power and high-efficiency PA is needed
to reduce the size and power consumption of the system and
to increase the communication distance. To make full use of
the wide lower mm-wave frequency band, broadband is also
desirable. However, it is still a challenge to achieve both high
efficiency and broadband for CMOS process.
Many broadband techniques have been proposed in recent
years [9]–[15]. In [9], the staggering technique is used to
increase the bandwidth of a low noise amplifier (LNA),
in which each amplification stage has a slightly different resonant frequency, thus creating an overall broadband response.
However, the staggering technique requires multiple amplification stages which may not be true in the lower mm-wave
frequency band. It also sacrifices the gain of the PA.
Broadband can be achieved by high order matching networks.
The recently reported fourth order networks for bandwidth
Manuscript received August 26, 2017; revised November 22, 2017 and
January 6, 2018; accepted January 25, 2018. This work was supported by
the Research Grant Council of Hong Kong SAR Government, China, under
Grant 16212114 and Grant 16201815. This paper was recommended by
Associate Editor D. Zito. (Corresponding author: C. P. Yue.)
H. Jia, C. C. Prawoto, and C. P. Yue are with the Hong Kong University
of Science and Technology, Hong Kong (e-mail: eepatrick@ust.hk).
B. Chi and Z. Wang are with the Institute of Microelectronics, Tsinghua
University, Beijing 100084, China.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2018.2799983
enhancement are summarized in [10] and shown in Fig. 1.
In these four types of fourth order network, the magnetically coupled resonator (MCR) in Fig. 1(c) and magnetically
and capacitively coupled resonator (MCCR) in Fig. 1(d) are
transformer based. Since the transformer provides more
degrees of design freedom while only occupies similar
chip area as a single inductor, those two types of coupled
resonator is more attractive than their counterparts shown
in Fig. 1(a) and Fig. 1(b). A lot of MCR based PAs have
been reported [16]–[19]. In [16], a mm-wave PA using MCR
is designed in 65nm CMOS process. It achieves 14.35 dBm
saturated output power (Psat ) and 9.7 GHz bandwidth from
57.2 GHz to 66.9 GHz. However, the transformer in this
design is used as a tuned transformer, which does not fully
exploit the transformer’s broadband potential. Similar tuned
transformer based mm-wave PAs are presented in [17]–[19].
Another MCR based mm-wave PA is reported by Bassi et al.
in [13], which achieves the state-of-the-art 51% fractional
bandwidth from 40 GHz to 67 GHz and a peak PAE of 16%
without power combining. The analysis of the MCR based
PA design is also reported. In their analysis, the MCR is first
converted into its π-type equivalent model and then Norton
transformations are applied for impedance scaling. However,
the theoretical calculation is overcomplicated to provide an
intuitive design guideline for the MCR based PAs. In [14],
the MCCR shown in Fig. 1(d) is designed for a broadband
receiver. However, as compared in [10], at a given bandwidth
the gain ripple of the MCCR is smaller ripple than that of
the capacitively coupled resonator (CCR) shown in Fig. 1(a),
but larger than that of the MCR in Fig. 1(c). It is not
desirable to add extra coupling capacitance to the network.
Vigilante, and Reynaert [10] have investigated the second
order effects of the MCR due to the transformer’s physical
layout implementation which is often neglected in prior works.
The second order effects are used to further improve the
bandwidth. Using their design methods, they successfully
demonstrate an E-band receiver in 28nm CMOS process with a
remarkable 27.5 GHz 3 dB bandwidth and less than 1 dB gain
ripple. However, their analysis are focusing on the LNA and
receiver design. The impedance transformation, which is very
important for PA matching network design, is not addressed
in their work.
By fully exploring the potential of the MCR, we have
demonstrated a PA with the state-of-the-art 63.3% fractional
bandwidth, covering the full Ka-band (26.5 GHz to 40 GHz),
and 32.9% peak PAE [20]. The MCR matching network is analyzed theoretically from the uncoupled resonant frequency ω,
Q factor and peak impedance R P instead of the inductance L,
capacitance C and resistance R. The results show that these
parameters are more convenient to use in the MCR matching network design, which leads to simple and straightforward design equation. Leveraging these equations and insight,
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Fig. 2. The magnitude response of the individual uncoupled RLC tank and
its resonant frequency ω0 , Q, and peak impedance RP .
equations:
ω= √
1
LC
R
Q=
ωL
RP = R
Fig. 1. Four types of broadband coupled resonators [10]. (a) Capacitively
coupled resonator. (b) Inductively coupled resonator. (c) Magnetically coupled
resonator. (d) Magnetically and capacitively coupled resonator.
a straight-forward design method for a PA output matching
network is proposed. The example in this paper shows the
design method is efficient and easy to use, which can help
future’s designers. We have also explored the bandwidth and
gain ripple trade-off, and given the accurate condition for no
gain ripple. To the best of our knowledge, the accurate no gain
ripple condition has not been mentioned in other works.
The paper is organized as follows. Section II analyzes
the MCR theoretically, including the symmetrical and asymmetrical cases. Section III discusses how to use the MCR
in a broadband PA output matching network and an input/
inter-stage matching network design. Section IV describes the
design of a broadband PA prototype. Section V presents the
measured results. Finally, Section VI draws the conclusions.
II. T HE M AGNETICALLY C OUPLED R ESONATOR
Fig. 2 shows the simplified schematic of an MCR, which
consists of two inductors with coupling between them, two
capacitors and two resistors. Seven parameters are sufficient
to describe this simplified MCR. They are L 1 , C1 and R1 of the
left resonator, L 2 , C2 and R2 of the right resonator and the
coupling coefficient k between them. We can also describe
the MCR using a new parameter set consisting of angular
frequency ω, quality factor Q, and peak impedance R P .
These parameters are more convenient to use when the peak
impedances at the two ends of the matching network are fixed,
as in the output matching network of a PA. For an uncoupled tank at each side of the MCR, the conversion between
the two set of parameters can be done using the following
(1.1)
(1.2)
(1.3)
The ω, Q, and R P can be estimated from the magnitude
response of the uncoupled tank as shown in Fig. 2. Using the
new parameter set, we also have seven parameters to describe
the MCR: ω1 , Q 1 and R P1 of the left had side uncoupled
resonator, ω2 , Q 2 and R P2 of the right hand side uncoupled
resonator and the coupling k between them. These seven
parameters are used in a 2-port network model to analyze the
MCR. The complete equation for Z 21 of the MCR is calculated
as (2), as shown at the bottom of the next page. Note that
s = jω in (2).
A. Symmetrical MCR
First, consider the case of a symmetrical MCR, where
ω1 = ω2 = ω0 , Q1 = Q2 = Q (R P1 and R P2 do not need
to be equal to each other). Z 21 in (2) is then simplified to
(3), as shown at the bottom of the next page. From (2) and (3),
we can see that R P1 and RP2 only appear in the equation as
constant factors. The bandwidth properties are not impacted
by the peak impedance, which makes the analysis easier.
At the pole frequencies of the MCR, the phase of Z21 should
be either 0° or ±180°, which means the imaginary part of Z21
is zero. We can calculate the two pole frequencies by letting
the real part of the denominator of (3) equal to zero. Assuming
2Q 2 1 − k 2 , the two pole frequencies ω H and ω L are
calculated as:
ω0
(4.1)
ωH ≈ √
1−k
ω0
ωL ≈ √
(4.2)
1+k
From (4.1) and (4.2), we can see that a larger k pushes the
two pole frequencies away from each other. This property of
MCR has been well studied previously in [15], [21], and [22].
Fig. 3 shows the simulated Z 21 of the symmetrical MCR with
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JIA et al.: FULL Ka-BAND PA WITH 32.9% PAE AND 15.3-dBm POWER IN 65-nm CMOS
Fig. 3. The simulated |Z21 | of the symmetrical MCR different k when Q=5.
3
Fig. 4. The calculated and simulated gain ripple with different k and Q for
the symmetrical MCR.
Q = 5 and different k. When k is large, the Z 21 has two equal
amplitude peaks corresponding to the pole frequencies. As k
becomes smaller, the two amplitude peaks move towards each
other until they finally merge together. We are interested in
the condition that the two amplitude peaks are just about to
merge because this is also the condition that |Z 21 | achieves the
maximal flatness and has no gain ripple. To do this, we need
to calculate the amplitude of Z 21 at its two pole frequencies:
R p1 R p2
(5)
|Z 21( j ω H )| = |Z 21 ( j ω L )| =
2
In (3), if we let the image part of the denominator equal to
zero, we can calculate the frequency ω X where the phase of
Z 21 is −90°, which is:
ω0
ωX = √
(6)
1 − k2
At this frequency, |Z 21 | is calculated as:
√
1 − k2k Q |Z 21( j ω X )| =
R p1 R p2
1 − k2 + k2 Q2
|Z 21 ( j ω H,L )|
1 − k2 + k2 Q2
= √
|Z 21 ( j ω X )|
2 1 − k2k Q
(7)
(8)
Fig. 4 shows the calculated gain ripple using (6) along with
simulated results for different k and Q values. It can be seen
that the calculated and simulated results are very close to
each other, which means (8) provides a good estimation of
Z 21 (s)
the ripple. If we let the ripple in (8) equal to 1, we can derive
the no gain ripple condition:
k 2 (1 + Q 2 ) = 1
From (4.1), (4.2) and (6), it is not difficult to find out ω X
always locates between the two pole frequencies ω H and ω L .
In addition, ω X is close to the in-band valley amplitude
frequency. We can estimate the gain ripple using the amplitude
shown in (5) and (7):
R=
Fig. 5. The simulated |Z21| of the symmetrical MCR with Q=1.5 and k
satisfies kQ=1 and k2 (Q2 +1)=1.
(9)
It should be noted that no gain ripple condition (9) is more
precise than previous equation k Q = 1 mentioned in [12]
and [15]. Fig. 5 compares the |Z21| under these two equations
when Q = 1.5. It can be seen that k Q = 1 still gives 0.5 dB
magnitude ripple although it has a wider 3-dB bandwidth.
When Q is sufficiently high, these two equations produce
similar results. However, noticeable difference is observed
when Q is small, which is exactly the case in the PA’s output
matching network. When Q is smaller than 1, the k Q = 1
equation even results in an unpractical k value of greater
than 1. In a multi-stage PA design, the inter-stage and the
input matching networks usually have higher Q than the output
matching network due to the smaller transistor size and the
higher impedance looking into the gate of the output transistor.
Similar to an RLC resonator, there is a tradeoff between the
P1 R P2
·s
Q 1 Q 2 kω12 ω22 QR1 Q
2 ω1 ω2
2
=
Q 1 Q 2 (1−k 2)s 4 +(Q 1 ω2 + Q 2 ω1 )(1−k 2)s 3 + ω1 ω2 (1−k 2 )+ Q 1 Q 2 ω1 +ω22 s 2 +ω1 ω2 (Q 1 ω1 + Q 2 ω2 )s + Q 1 Q 2 ω12 ω22
(2)
√
k Qω03 R P1 R P2 · s
Z 21 (s) =
(3)
(1 − k 2 )Q 2 s 4 + 2(1 − k 2 )Qω0 s 3 + (1 − k 2 + 2Q 2 )ω02 s 2 + 2Qω03 s + Q 2 ω04
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4
Fig. 6. The calculated normalized GBW of the MCR with 0 dB and 3 dB
ripple and simple RLC resonator.
bandwidth and Q in the MCR. Therefore, it is more difficult to
design the inter-stage and the input stage matching networks
to have the wide bandwidth of the output matching network.
Since the bottleneck of the PA’s bandwidth is at the interstage or the input matching network, it is sub-optimal to make
a gain ripple and bandwidth tradeoff at the output matching
network. When k 2 1 + Q 2 < 1, the two amplitude peaks of Z 21
merge into one peak as shown in Fig. 3. The in-band amplitude
valley does not exist anymore. In this case, we can define
the in-band gain ripple to be 1. However, we do not want to
design our MCR in this condition because both the gain and
bandwidth are sacrificed as shown in Fig. 3. The complete
expression for the gain ripple of a symmetrical MCR is:
⎧
2
2 2
⎨1 − k + k Q
k2 (1 + Q 2 ) ≥ 1
√
2k Q
R=
(10)
2
1
−
k
⎩
1
k2 (1 + Q 2 ) < 1
To fairly compare the symmetrical MCR with a simple RLC
resonator where a single inductor is used to resonate capacitors
C1 and C2 , the gain bandwidth production (GBW) is used.
Although we can calculate the 3-dB bandwidth from (3),
the closed-form solution is in form of the roots of a fourth
order polynomial equation, and is too complicated to offer
any insight into the design. Instead, a numerical method is
used to calculate an accurate 3-dB bandwidth √
and gain by
letting the amplitude of Z 21 in (3) equal to 1/ 2 times of
the peak amplitude shown in (5). Fig. 6 compares the GBW
of the RLC resonator to the √
MCR with both 0 dB and 3 dB
gain ripple, normalized to ωo R P1 R P2 /2. Note that the gain
here is a trans-impedance gain. It can be seen that the MCR
enhances the GBW of the RLC resonator by 1.4 times with
no gain ripple. When 3-dB gain ripple is allowed, the GBW
of the MCR further increases to 3.1 times. Fig. 5 also shows
that the normalized GBW decreases when Q increases, which
means the bandwidth and Q trade-off still exists for the MCR.
B. Asymmetrical MCR
Until now the MCR is assumed to be symmetrical. However,
frequency and Q mismatch may exist in a real circuit, resulting
in different peak impedances of Z 21 . Fig. 7 shows simulated
magnitude response of an MCR with different ω1 /ω2 ratios,
at equal Q 1 and Q 2 values. We can observe two properties
when the frequency mismatch exists. Firstly, the magnitude
response decreases due to the frequency mismatch. Secondly,
the peak amplitude is no longer equal to each other as in
the symmetrical case. Fig. 8 shows simulated results when
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Fig. 7.
The simulated |Z21| of the MCR with frequency mismatch.
Fig. 8. The simulated |Z21| of the MCR with both frequency mismatch and
Q mismatch.
both frequency and Q mismatch exist. It is interesting to see
that when the ratio of Q increases towards the ratio of ω,
the higher impedance peak drops while the lower impedance
peak grows. And they become equal again when the ratio of
Q equals to the ratio of ω. In other words, Q mismatch can
compensate for ω mismatch, resulting in equal peak amplitude.
The peak amplitude at pole frequencies of a general MCR can
be derived as:
|Z 21( j ω H )|
R P1 R P2
Q 1 Q 2 ω1 ω2
=
| − (ω2 Q 1 + ω1 Q 2 )(1 − k 2 )ω2H + ω12 ω2 Q 1 + ω22 ω1 Q 2 |
Q 1 Q 2 kω12 ω22
(11.1)
|Z 21( j ω L )|
=
R P1 R P2
Q 1 Q 2 ω1 ω2
| − (ω2 Q 1 + ω1 Q 2 )(1 − k 2 )ω2L + ω12 ω2 Q 1 + ω22 ω1 Q 2 |
Q 1 Q 2 kω12 ω22
(11.2)
In which ω H and ω L are as follows:
2
2 + ω2 +
ω
ω12 + ω22 − 4 1 − k 2 ω12 ω22
1
2
2
ωH =
2 1 − k2
2
2 + ω2 −
ω
ω12 + ω22 − 4 1 − k 2 ω12 ω22
1
2
2
ωL =
2 1 − k2
(12.1)
(12.2)
In (11.1) and (11.2), when ω1 /ω2 = Q 1 /Q 2 = α, we can
derive that:
√
kα R P1 R P2
|Z 21 ( j ω H )| = |Z 21 ( j ω L )| =
(13)
(α 2 − 1)2 + 4k 2 α 2
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JIA et al.: FULL Ka-BAND PA WITH 32.9% PAE AND 15.3-dBm POWER IN 65-nm CMOS
Fig. 9.
The simulated normalized (a) gain, BW and (b) GBW of the
asymmetrical MCR with different α and Q.
Fig. 11.
5
The simulated |Z21| of the unsymmetrical MCR with different k.
Fig. 10. The simulated in-band gain ripple of the asymmetrical MCR with
different α and Q.
It proves that the peak amplitudes at the two pole frequencies
are equal again when the frequency mismatch ratio is equal
to the Q mismatch ratio.
The maximum value of the peak
√
amplitude in (13) is R P1 R P2 /2. It is achieved if and only
if α = 1. It shows that maximum |Z 21| peak occurs when the
MCR is symmetrical, which is consistent with the simulation
results in Fig. 5.
Similarly, a closed form solution for the 3-dB bandwidth
is too complicated as a guideline for MCR design. Therefore,
we use simulation approach to investigate the 3-dB bandwidth.
In the simulation, we assume ω1 = αω2 , Q 1 = α Q 2 = α Q,
and Q is chosen to be 2, 5 and 10. k is determined by the
no gain ripple condition in (9). The results are shown in the
Fig. 9 and Fig. 10. The gain in√the Fig. 9(a) is the transimpedance gain normalized √to R P1 R P2 /2, and the 3-dB
bandwidth is normalized to ω1 ω2 . From Fig. 9(a), we can
see that the gain deceases as α moves away from 1, which is
consistent to the prediction by equation (13). It also shows
the frequency mismatch can increase the 3-dB bandwidth.
However, as shown in Fig. 9(b), the gain drops faster than
the increase in bandwidth, thus the GBW of an asymmetrical
MCR is always less than the symmetrical one. This indicates
that a symmetrical MCR is always preferred.
Besides the GBW drop, another penalty of an asymmetrical
MCR is the gain ripple. Fig. 10 shows simulated result of
ripple magnitude at different α and Q values. We can see
that the symmetrical MCR (α = 1) has the minimum gain
ripple at a particular Q, and the ripple increases when α moves
away from 1. In a practical design, the Q and the gain ripple
requirement would determine how far away from 1 the α can
go. In addition, Fig. 11 shows the effect of k due to frequency
mismatch. Similar to the symmetrical case, a higher k pushes
the two peaks away from each other.
Fig. 12. (a) The simplified single ended output matching network of the PA,
(b) the single ended output matching network initial design, and (c) the
simulated gain of the output stage using the initial calculated parameters.
The inset shows the enlarged view of the gain.
III. PA M ATCHING N ETWORK D ESIGN
To use an MCR in a broadband PA matching network,
the values of the MCR seven parameters need to be determined. The analysis in Section II serves as a bridge connecting the design parameters to our design targets, which
include bandwidth, gain ripple, efficiency, etc. It provides a
guideline about how to achieve impedance matching over a
wide frequency range efficiently. In this section, the design
of MCR based matching network will be introduced using
two specific cases, the output matching network and interstage/input matching network of a PA.
A. Output Matching Network
Fig. 12(a) shows a simplified output matching network in its
single-ended equivalent form. Usually, a load pull simulation is
first performed on the output transistor at a certain input power
level and at a certain bias voltage to determine the optimal
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load impedance at the drain of the output transistors. In this
design, the conjugate of the optimum load impedance equals to
a 37.5 resistor (R S ) in parallel with a 123 fF capacitor (C S ).
Then the output matching network needs to transform the 50
load resistance and the pad parasitic capacitance (25 fF in this
design) into the desired optimal impedance.
Due to the heavy loading on both sides of the MCR,
the output matching network is a low-Q network, which is
good for broadband matching. Also, the loaded Q is usually
much smaller than the unloaded Q of the transformer itself
at the frequency range of interest. Therefore, we can safely
ignore the intrinsic parasitic resistance of the transformer.
Then the R P on both sides of the MCR are determined solely
by the load and source resistances. The MCR here needs to
transform a low Q fixed R P network into another low Q
fixed R P network in the output matching network. In the real
implementation, we need to improve the unloaded Q of the
transformer itself as much as possible to reduce the power
dissipation of the transformer.
Using the analysis in the previous section, a simple and
straight-forward design method can be developed as follows:
1) Using a symmetrical MCR for maximal peak |Z 21 | and
GBW, we have ω1 = ω2 = ω0 and Q 1 = Q 2 = Q.
2) Assume an initial value for the primary coil parasitic capacitance C p . Usually, we do not want extra
capacitance in the MCR because it reduces the GBW.
At the given frequency, larger capacitance means the
inductance needs to be smaller. For a fixed R P network,
the Q is calculated as:
4) According to the no gain ripple condition shown in (9),
the desired coupling coefficient k is:
Q=
RP
ω0 L
(14)
It can be seen that Q increases as L decreases, which
results in a smaller normalized GBW as shown in Fig. 6.
However, we have to tolerate the parasitic capacitance
of the transformer. According to our past experience,
C P of 10∼20 fF is a good initial guess for an on-chip
transformer at this frequency. In this design, we chose
15 fF for the initial guess.
3) Calculate Q using the total capacitance on the left
side and the desired center operating frequency. In this
design, the total capacitance is 138 fF, and the center
operating frequency is 32 GHz. We use the geometrical
mean of the two pole frequencies to estimate the center
operating angular frequency ωC :
ω2
ωC2 = ω H ω L = √ 0
1 − k2
And Q can be expressed as:
Q = ωo R S (C S + C p )
(15)
(16)
Note that the Q here is the uncoupled Q as defined
before. Using (15), (16) and the no gain ripple condition
in (9), Q is calculated as:
√
−1 + 1 + 4α 4
(17)
Q=
2
in which:
α = ωC R S (C S + C p )
(18)
Using the data we have, Q is calculated to be 0.83.
1
k= 1 + Q2
(19)
Then k is calculated to be 0.77 in this design.
5) Calculate L 1 using the following equation:
L1 =
R 2S (C S + C p )
1
=
Q2
ω02 (C S + C p )
(20)
In this design, L 1 is calculated to be 282 pH.
6) From ω1 = ω2 and Q 1 = Q 2 , we know that the
inductance ratio on the two sides of the MCR must be
equal to the resistance ratio:
L1
RS
=
L2
RL
C2
RS
=
C1
RL
(21.1)
(21.2)
Then
L2 =
RL
L1
RS
(22)
In this design, L 2 is calculated to be 376 pH.
7) The total capacitance C2 needed on the right side tank is:
RS
C1
(23)
RL
It is calculated to be 104 fF, which means an additional
79 fF capacitance (CS ) needs to be added in parallel
with the 25 fF pad capacitance.
At this stage, initial transformer design has been completed. Equations (17)-(20) and (22)-(23) are key to the MCR
design. All the coupled resonator parameters are marked
in Fig. 12(b). To verify the calculated parameters, we simulated this MCR together with the output transistor. The gain is
shown in Fig. 12(c). It can be seen that the initial calculation is
close to the optimal parameters. A broadband output matching
is achieved although there is still about 0.5 dB ripple.
However, another verification step is required, that is replacing the simplified single ended MCR model to a realistic one
consisting of a transformer and capacitor. The calculated L,
C and k values shown in this section serve as the design
goal of the transformer design. Since a transformer is intrinsically affected by process dependent higher order parasitic,
its implementation require several design iterations involving
electromagnetic simulations.
C2 =
B. Inter-Stage/Input Matching Network
Fig. 13 shows a simplified single-ended circuit of an interstage matching network. The input matching network is similar
to Fig. 13, except that the input transistor should be replaced
with 50 source resistor and the pad parasitic capacitor,
therefore its schematic is not given here. The load of the
matching network is the input impedance of the transistor in
the next stage, which is usually a high impedance consisting
of the gate capacitance in series with a small gate resistance.
The Q at the right hand side of the MCR is dominated by
the unloaded Q of the transformer itself. Therefore it is a
relatively high Q network compared to the left hand side of
the MCR where the Q is low due to the source resistance of
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JIA et al.: FULL Ka-BAND PA WITH 32.9% PAE AND 15.3-dBm POWER IN 65-nm CMOS
7
Fig. 13. The simplified singled ended inter-stage matching network of the PA.
Fig. 15.
The 3-D view of the output matching network including a
transformer, leakage inductor, balance capacitor and G-S-G pad.
Fig. 14.
The schematic of the proposed MCR based broadband PA.
the driver transistor. Both the higher Q at the right hand side
and the Q mismatch make the inter-stage matching network
more difficult to design compared with the output matching
network, especially considering the broadband requirement.
Another difficulty comes from the fact that the peak impedance
at the right hand side of the MCR depends on the transformer
itself. Unlike the output matching network, it is not a fixed
R P network anymore. The tight coupling between R P and Q
makes the analysis in Section II less efficient for inter-stage
matching. There are two approaches to extend the bandwidth
of the inter-stage matching network. The first one is to use
the asymmetrical MCR as discussed in Section II. We have
already discussed that the frequency mismatch in the MCR
can increase the bandwidth. The second one is to simply
place a resistor at the right hand side of the MCR [13], thus
extending the bandwidth by introducing extra loss into the
resonator. Both approaches sacrifice the gain for bandwidth,
and are roughly compared in this section.
Assume that we have an asymmetrical MCR with R P1 =
2R P2 and Q 1 = 2Q 2 = 4. If the asymmetrical MCR approach
is used for the matching network, the normalized GBW
drops from 0.723 to 0.610 compared with the symmetrical
coupled resonator from Fig. 9(b). It is about 1.18 times GBW
degradation. On the other hand, if we add an extra resistor
in parallel with R P1 to make R P1 = √R P2 and Q 1 = Q 2 ,
then the peak impedance drops from 2 R P2 /2 to R P2 /2,
which is about 1.41 times decrease. The bandwidth stays the
same as the symmetrical case. Thus the GBW degradation
of the case placing a resistor is about 1.4 times, which is
worse than the asymmetrical case. However, the asymmetrical
MCR pays more penalty on the gain ripple than simply placing
a resistor. If the same amount of ripple is allowed in the
approach of placing a resistor, its GBW will be better than the
asymmetrical coupled resonator. Based on this consideration,
we recommend the method of adding a resistor for broadband
PA’s inter-stage matching network to the other designers,
although the asymmetrical MCR is employed in this work.
Fig. 16. (a) The transformer together with leakage inductor and (b) its
equivalent schematic.
The extra resistor also offers more flexibility in the design
of the inter-stage matching network. After adding a proper
resistor, the inter-stage matching network becomes a fixed RP
network. Thus the design procedure for the output matching
network described before can be directly used.
IV. T HE PA C IRCUIT I MPLEMENTATION
The schematic of the broadband PA is shown in Fig. 14. The
PA is designed in 65nm CMOS general purpose process, which
includes RF transistor models and one 3.4μm thick ultrathick metal layer. The power amplifier has two amplification
stages. The transistor sizes of the first and second stage is
64μm/60nm and 128μm/60nm, respectively. Both stages use
neutralization capacitors to improve gain, reverse isolation and
stability. The capacitances are 23 fF for the first stage and
45 fF for the second stage. Three customized transformers are
used for the input, inter-stage, and output matching networks.
Fig. 15 shows the 3-D view of the output matching network,
which includes a transformer, a leakage inductor, an output
G-S-G pad and an extra capacitor for frequency balance.
According to our previous analysis, we need to optimize
both the inductance ratio and the k in order to achieve
the broadband response requirement. It is difficult to adjust
the inductance ratio or k alone without influence the other
parameter in the real transformer design. A large number of
time-consuming iterations are needed to obtain a transformer
with the designed parameters. To account for this issue,
a leakage inductor is added to provide a convenient way to
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Fig. 19. The 3-D view of (a) the inter-stage matching network and (b) input
matching network.
inductor and its equivalent form. The effective inductance
and k can be calculated using (24.1)-(24.3). Note that the
analysis in Section II is based on a general simplified transformer model with no assumption about its implementation.
Therefore the new parameter set shown in (24.1)-(24.3) can
be used in the analysis.
L pri = L pri
Fig. 17. The simulated results of the output matching transformer with and
without the leakage inductor: (a) L, (b) Q, (c) k.
Fig. 18. (a) The simulated real and image part of the input impedance of the
output matching network. (b) The simulated efficiency of the output matching
network.
tune the transformer parameters. Although the loaded Q of
the output resonator is largely determined by the source and
load resistance, it is important to improve the unloaded Q of
the transformer itself in order to reduce the power dissipating
in the transformer itself. The 3.4μm top metal layer is used to
implement the primary coil and the leakage inductance, while
three metal layers from M6 to M8 are stacked to implement
the secondary coil. Fig. 16 shows the transformer with leakage
L sec = L sec + L 2
k = k
L sec
L sec + L 2
(24.1)
(24.2)
(24.3)
In this design, the outer diameter of the leakage inductor
is 66.5 μm. The inductance is 156 pH. The 3.4μm ultrathick metal layer provided by the process enables the Q of the
leakage inductor to be as high as 27 at 32 GHz. Fig. 17 shows
the simulated inductance, Q and k of the transformer with
and without the leakage inductor. It can be seen that as
predicted by (24.1)-(24.3), the primary inductance of the transformer is unaffected by the leakage inductor. The secondary
inductance increases while the k decreases with the leakage
inductor.
After MCR matching, the impedance seen by the drain of
output transistors is shown in Fig. 18(a). Note that the source
capacitance is included in the coupled resonator. The MCR
transforms the 50 load resistance to about 37.5 over a
wide frequency range. As mentioned in [17], the efficiency
of the output matching network can be calculated from its
Maximum Available Gain (MAG) by ηmax = 10 M AG/10 [17].
Fig. 18(b) shows the simulated result, from which we can see
that the maximum efficiency is as high as 82.3%, and is higher
than 80% over the full Ka band range. The efficiency of the
output network is crucial for the efficiency of the whole PA.
The input and inter-stage matching transformers are shown
in Fig. 19(a) and Fig. 15(b), respectively. Since the Q fac-
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JIA et al.: FULL Ka-BAND PA WITH 32.9% PAE AND 15.3-dBm POWER IN 65-nm CMOS
Fig. 20. The simulated impedance of the uncoupled resonators and the
impedance when the magnetically coupling is applied with the uncoupled
frequencies (a) shifting towards opposite direction, (b) aligning with each
other.
9
Fig. 22.
The measurement setup for the PA.
Fig. 23.
The measured and simulated S-parameters of the broadband PA.
high-frequency peak by several dB, thus reducing the overall
bandwidth of the matching network. Comparing Fig. 20(a) and
Fig. 20(b), we can also see that the frequency mismatch
reduces the magnitude of the peak impedance as discussed
before.
Fig. 21. The microphotograph of the broadband PA, the core area of which
is 0.64 mm∗ 0.17 mm.
tor here is much higher than the output matching network,
a smaller k is preferred. Note that an extra matching capacitor
is added to the primary coil of the input matching transformer.
The outer diameter of the input and inter-stage matching transformers are 132 μm and 130 μm, respectively. For the input
matching transformer, the primary and secondary inductances
are 246 pH and 443 pH, respectively, with k of 0.47. For the
inter-stage matching transformer, the primary and secondary
inductances are 609 pH and 233 pH, respectively with k
of 0.34. The results are also marked in Fig. 15.
The asymmetrical MCR is used for both input and interstage matching networks. The impedances (|Z 21|) of each
tank at the two ends of the matching network are shown
in Fig. 20(a), for both without coupling and when k = 0.34
is applied. It can be seen that a mismatch is intentionally
introduced to the uncoupled resonant frequencies of the two
tanks to extend the bandwidth. As a comparison, the simulated
|Z 21 | when the two uncoupled resonant frequencies align is
shown in Fig. 20(b). Applying the same coupling coefficient,
the low-frequency peak of |Z 21 | becomes higher than the
V. M EASURED R ESULTS
A prototype of the broadband PA was fabricated in a 65nm
CMOS process, the chip micrograph is shown in Fig. 21. The
core area of the PA is 0.64 mm × 0.17 mm, excluding the pads.
The area of input, inter-stage and output matching networks
are 0.023 mm2 , 0.025 mm2 and 0.044 mm2 , respectively. The
supply voltage of the broadband PA is 1.0 V. The S-parameters
and the linearity of the PA are measured using an on-chip
probing system. The power supply and the bias voltage of the
PA are wire-bonded to a PCB board, while the input/output
signals are connected using high-frequency G-S-G probes.
A network analyzer and a spectrum analyzer with upper frequency limit of 67 GHz are used to measure the S-parameters
and the output power, respectively. The measurement results
are shown in Fig. 22. The insertion loss of the coupler? and
the G-S-G probes has been calibrated out from the measured
results. Fig. 23 shows the measured small signal performance
together with simulated results. Using the proposed broadband
matching technique, the measured gain (S21) of the broadband
PA is larger than 19.0 dB in the frequency range from
21.6 GHz to 41.6 GHz, or a fractional bandwidth of 63.3%,
which covers the entire Ka band. The measured gain at 32 GHz
is 20.8 dB. However, there is 3.8 dB measured gain ripple in
band, while the simulated gain ripple in band is only 2.0 dB.
It may be caused by modeling inaccuracy of both active and
passive devices. Also, since the PA is a part of a wireless
transmitter, impedance matching to 50 is not performed at
the input of the standalone PA, resulting in matching loss.
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10
Fig. 24.
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The measured large signal performance of the wideband PA at different frequencies.
TABLE I
C OMPARISON OF R ECENT M M -WAVE PA S
As will be shown later, the wireless transmitter integrating
this PA supports error-free QPSK data rate of 16 Gbps.
Fig. 24 shows the measured large signal performance at
24 GHz, 32 GHz and 40 GHz. At 32 GHz, the broadband
PA achieves a 15.3 dBm saturated output power, a 12.9 dBm
output 1-dB compression point and a 32.9% peak PAE. Note
that the reflection at the input power due to the poor S11 has
some impact on the PAE but it is not significant. Using the
measured data at 32 GHz, if we assume the input is perfectly
matched, the peak PAE can increase to 34.0% at most, which
is 1.1% difference with the measured data. The measured
OIP3 is 17.7 dBm at 32 GHz. Fig. 25 shows the Psat as a
function of frequency. The 3-dB bandwidth of the saturated
output power is even larger than that of the small signal
gain. The ripple is also suppressed. Since the saturated output
power is dominated by the output stage, we can infer that the
small signal gain ripple is contributed by the input and interstage matching networks, which is consistent with our previous
analysis. The input and inter-stage matching networks have a
higher Q compared with the heavily loaded output matching
network, therefore they have larger gain ripple at a similar
bandwidth.
The broadband PA is also integrated into a 32 GHz QPSK
transmitter system [25] shown in Fig. 26(a). The input stage
of the PA is slightly modified from the standalone version.
In the measurement, baseband non-return-to-zero (NRZ) signal
is applied at the input of the wireline receiver. It is then
de-multiplexed into two paths, modulated by a QPSK modulator, and finally amplified by the proposed PA. The PA
Fig. 25.
The measured saturated output power over frequency.
output signal is demodulated on-chip into baseband signal,
measured using a sub-sampling oscilloscope and a PRBS error
checker. In the experiment, the entire data link successfully
demonstrates an error-free (bit error rate < 10−12 ) data rate
of 16 Gbps (8 Gbps per I/Q path), which is possible due to
the broadband property of the PA. Fig. 26(b) shows the output
eye-diagram. The highest supported data rate of the PA cannot
be determined due to the bandwidth limitation of the analog
baseband.
The measured performance of the PA is summarized
and compared with similar works recently published
in Table I. Among these works, the proposed broadband PA
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JIA et al.: FULL Ka-BAND PA WITH 32.9% PAE AND 15.3-dBm POWER IN 65-nm CMOS
11
R EFERENCES
Fig. 26. (a) The measured setup for the QPSK transmitter system with
the proposed PA integrated. (b) The measured 16 Gbps burth curve and eye
diagram at the on-chip demolution’s output.
achieves the widest bandwidth. It also has a better power
efficiency and a larger output power.
VI. C ONCLUSION
In this paper, the design and analysis of an MCR based
broadband PA in Ka-band are discussed. The MCR matching
network is analyzed theoretically using its uncoupled resonant frequency, Q factor and peak impedance instead of the
typical inductance, capacitance, and resistance. A simple yet
useful equations are derived to provide a guideline to the
MCR matching network design. Based on these equations
and guideline, a straight-forward design method for a PA
output matching network is proposed. For the PA output
matching network, the key is to let the inductance ratio of
the MCR to be equal to the load/source resistance ratio and
to choose the k according to the no gain ripple condition to
achieve a broadband impedance transformation. For the PA
input/inter-stage matching network, the uncoupled resonant
frequencies of the LC networks at the two sides of the MCR
are intentionally shifted towards the opposite directions to
extend the bandwidth. Using these design strategies, a full
Ka-band PA prototype is designed and fabricated in 65nm
CMOS process. The measured results show that the PA chip
achieves 32.9% PAE, 15.3 dBm Psat and 12.9 dBm output
P1dB . The fractional bandwidth of the PA is the state-of-theart 63.3%, from 21.6 GHz to 41.6 GHz, which covers the full
Ka-band (26.5 GHz to 40 GHz).
[1] Ericsson Mobility Report: The Need for Spectrum Harmonization. Accessed: Sep. 8, 2016. [Online]. Available:
https://www.ericsson.com/res/docs/2016/mobility-report/emr-june-2016the-need-for-spectrum-harmonization.pdf
[2] B. Sadhu et al., “A 28 GHz 32-element phased-array transceiver IC with
concurrent dual polarized beams and 1.4 degree beam-steering resolution
for 5G communication,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
Dig. Tech. Papers, Feb. 2017, pp. 128–129.
[3] Y.-S. Yeh, B. Walker, E. Balboni, and B. A. Floyd, “A 28-GHz 4-channel
dual-vector receiver phased array in SiGe BiCMOS technology,” in
Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), May 2016,
pp. 352–355.
[4] Y. Yeh, B. Walker, E. Balboni, and B. Floyd, “A 28-GHz phased-array
receiver front end with dual-vector distributed beamforming,” IEEE
J. Solid-State Circuits, vol. 52, no. 5, pp. 1230–1244, May 2017.
[5] G.-S. Jeong, W. Kim, J. Park, T. Kim, H. Park, and D.-K. Jeong,
“A 0.015-mm2 inductorless 32-GHz clock generator with wide
frequency-tuning range in 28-nm CMOS technology,” IEEE
Trans. Circuits Syst. II, Exp. Briefs, vol. 64, no. 6, pp. 655–659,
Jun. 2017.
[6] A. Agrawal and A. Natarajan, “A scalable 28 GHz coupled-PLL in
65 nm CMOS with single-wire synchronization for large-scale 5G
mm-wave arrays,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig.
Tech. Papers, Jan./Feb. 2016, pp. 38–39.
[7] S. Shakib, M. Elkholy, J. Dunworth, V. Aparin, and K. Entesari,
“A wideband 28 GHz power amplifier supporting 8×100 MHz carrier
aggregation for 5G in 40 nm CMOS,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 44–45.
[8] S. Shakib, H.-C. Park, J. Dunworth, V. Aparin, and K. Entesari,
“A 28 GHz efficient linear power amplifier for 5G phased arrays in
28 nm bulk CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
Dig. Tech. Papers, Jan./Feb. 2016, pp. 352–353.
[9] K. Hadipour, A. Ghilioni, A. Mazzanti, M. Bassi, and F. Svelto,
“A 40 GHz to 67 GHz bandwidth 23 dB gain 5.8 dB maximum
NF mm-wave LNA in 28 nm CMOS,” in Proc. IEEE RFIC Symp.,
May 2015, pp. 327–330.
[10] M. Vigilante and P. Reynaert, “On the design of wideband transformerbased fourth order matching networks for E-band receivers in 28-nm
CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 8, pp. 2071–2082,
Aug. 2017.
[11] A. Jahanian and P. Heydari, “A CMOS distributed amplifier with active
input balun using GBW and linearity enhancing techniques,” in Proc.
IEEE RFIC Symp., Jun. 2011, pp. 1–4.
[12] S. V. Thyagarajan, A. M. Niknejad, and C. D. Hull, “A 60 GHz drainsource neutralized wideband linear power amplifier in 28 nm CMOS,”
IEEE Trans. Circuits Syst. I. Reg. Papers, vol. 61, no. 8, pp. 2253–2262,
Aug. 2014.
[13] M. Bassi, J. Zhao, A. Bevilacqua, A. Ghilioni, A. Mazzanti, and
F. Svelto, “A 40–67 GHz power amplifier with 13 dBm PSAT and 16%
PAE in 28 nm CMOS LP,” IEEE J. Solid-State Circuits, vol. 50, no. 7,
pp. 1618–1628, Jul. 2015.
[14] V. Bhagavatula, T. Zhang, A. R. Suvarna, and J. C. Rudell, “An ultrawideband IF millimeter-wave receiver with a 20 GHz channel bandwidth
using gain-equalized transformers,” IEEE J. Solid-State Circuits, vol. 51,
no. 2, pp. 323–331, Feb. 2016.
[15] C.-H. Li, C.-N. Kuo, and M.-C. Kuo, “A 1.2-V 5.2-mW 20–30-GHz
wideband receiver front-end in 0.18-μm CMOS,” IEEE Trans. Microw.
Theory Techn., vol. 60, no. 11, pp. 3502–3512, Nov. 2012.
[16] W. Ye, K. Ma, K. S. Yeo, and Q. Zou, “A 65 nm CMOS power amplifier
with peak PAE above 18.9% From 57 to 66 GHz using synthesized
transformer-based matching network,” IEEE Trans. Circuits Syst. I. Reg.
Papers, vol. 62, no. 10, pp. 2533–2543, Oct. 2015.
[17] D. Zhao and P. Reynaert, “A 60-GHz dual-mode class AB power
amplifier in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 10,
pp. 2323–2337, Oct. 2013.
[18] J. Chen and A. M. Niknejad, “A compact 1V 18.6 dBm 60 GHz
power amplifier in 65 nm CMOS,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 432–433.
[19] D. Chowdhury, A. M. Niknejad, and P. Reynaert, “Design considerations for 60 GHz transformer-coupled CMOS power amplifiers,” IEEE
J. Solid-State Circuits, vol. 44, no. 10, pp. 2733–2744, Oct. 2009.
[20] H. Jia, C. C. Prawoto, B. Chi, Z. Wang, and C. P. Yue, “A 32.9%
PAE, 15.3 dBm, 21.6–41.6 GHz power amplifier in 65 nm CMOS
using coupled resonators,” in Proc. IEEE Asian Solid-State Circuit
Conf. (A-SSCC) Dig. Tech. Papers, Nov. 2016, pp. 345–348.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
[21] G. Mangraviti et al., “A 52–66GHz subharmonically injection-locked
quadrature oscillator with 10 GHz locking range in 40 nm LP CMOS,”
in Proc. IEEE RFIC Symp., Jun. 2012, pp. 309–312.
[22] H. Jia, B. Chi, L. Kuang, and Z. Wang, “A W-band injection-locked
frequency doubler based on top-injected coupled resonator,” IEEE Trans.
Microw. Theory Techn., vol. 64, no. 1, pp. 210–218, Jan. 2016.
[23] N. Kalantari and J. F. Buckwalter, “A nested-reactance feedback power
amplifier for Q-band applications,” IEEE Trans. Microw. Theory Techn.,
vol. 60, no. 6, pp. 1667–1675, Jun. 2012.
[24] C. R. Chappidi and K. Sengupta, “A frequency-reconfigurable mm-wave
power amplifier with active-impedance synthesis in an asymmetrical
non-isolated combiner,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
Dig. Tech. Papers, Jan./Feb. 2016, pp. 344–345.
[25] H. Jia, G. Zhu, Y. Wang, Z. Wang, and C. P. Yue, “A 16-Gb/s
millimeter-wave CMOS transmitter with integrated optical receiver for
5G baseband-over-fiber systems,” in Proc. IEEE Photon. Soc. Summer
Topical Meeting Ser. (SUM), Jul. 2017, pp. 209–210.
[26] J. Zhao, E. Rahimi, F. Svelto, and A. Mazzanti, “A SiGe BiCMOS
E-band power amplifier with 22% PAE at 18 dBm OP1dB and 8.5% at
6 dB back-off leveraging current clamping in a common-base stage,”
in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers,
Feb. 2017, pp. 42–43.
[27] D. Pepe, D. Zito, A. Pallotta, and L. Larcher, “1.29-W/mm2 23-dBm
66-GHz power amplifier in 55-nm SiGe BiCMOS with in-line coplanar
transformer power splitters and combiner,” IEEE Microw. Wireless
Compon. Lett., vol. 27, no. 12, pp. 1146–1148, Dec. 2017.
Haikun Jia received the B.S. and Ph.D. degrees
in electronics engineering from Tsinghua University,
Beijing, China, in 2009 and 2015, respectively.
He is currently a Post-Doctoral Fellow with the
Department of Electrical and Computer Engineering,
Hong Kong University of Science and Technology.
He research interests are in the field of millimeterwave and high-speed circuit and system design,
including PA, VCO, and FMCW radar.
Zhihua Wang (SM’04–F’17) received the B.S.,
M.S., and Ph.D. degrees in electronic engineering
from Tsinghua University, Beijing, China, in 1983,
1985, and 1990, respectively. In 1983, he joined the
faculty at Tsinghua University, where he has been a
Full Professor since 1997 and the Deputy Director
of the Institute of Microelectronics since 2000. From
1992 to 1993, he was a Visiting Scholar with
Carnegie Mellon University, Pittsburgh, PA, USA.
From 1993 to 1994, he was a Visiting Researcher
with KU Leuven, Leuven, Belgium. He is the
co-author of ten books and book chapters, over 90 papers in international journals, and over 300 papers in international conferences. He holds 58 Chinese
patents and four U.S. patents. His current research interests include CMOS
radio frequency integrated circuit (RFIC), biomedical applications, radio
frequency identification, phase locked loop, low-power wireless transceivers,
and smart clinic equipment with combination of leading edge CMOS RFIC
and digital imaging processing techniques. He was an Official Member of
the China Committee for the Union Radio-Scientifique Internationale from
2000 to 2010. He served as a Technologies Program Committee Member of the
IEEE International Solid-State Circuit Conference from 2005 to 2011. He has
been a Steering Committee Member of the IEEE Asian Solid-State Circuit
Conference since 2005. He has served as the Deputy Chairman of the Beijing
Semiconductor Industries Association and the ASIC Society of Chinese
Institute of Communication, as well as the Deputy Secretary General of the
Integrated Circuit Society in the China Semiconductor Industries Association.
He was one of the chief scientists of the China Ministry of Science and
Technology serves on the Expert Committee of the National High Technology
Research and Development Program of China (863 Program) in the area of
information science and technologies from 2007 to 2011. He was the Chairman of the IEEE Solid-State Circuit Society Beijing Chapter from 1999 to
2009. He has served as the Technical Program Chair of the 2013 A-SSCC.
He served as the Guest Editor for the IEEE J OURNAL OF S OLID -S TATE
C IRCUITS Special Issue in 2006 and 2009. He is an Associate Editor of
the IEEE T RANSACTIONS ON B IOMEDICAL C IRCUITS AND S YSTEMS and
the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS -PART II: E XPRESS
B RIEFS .
Clarissa C. Prawoto received the B.Eng. and
M.Phil. degrees from the Hong Kong University of Science and Technology, in 2014 and
2017, respectively, where she is currently pursuing the Ph.D. degree. Her research interests
include high-speed interconnect design and technology, millimeter-wave RF IC design, and wireless
power transfer interface design.
Baoyong Chi received the B.S. degree in microelectronics from Peking University, Beijing, China,
in 1998, and the Ph.D. degree from Tsinghua University, Beijing, in 2003. From 2006 to 2007, he
was a Visiting Assistant Professor with Stanford
University, Stanford, CA, USA. He is currently
a Professor with the Institute of Microelectronics,
Tsinghua University. In his 12 years of academic
experience, he has authored or co-authored over
140 academic papers and two books, and has been
issued over 15 patents. His current research interests
include RF/MM-wave integrated circuit design, analog integrated circuit
design, and monolithic wireless transceiver analog front-end. He has been a
TPC member of A-SSCC since 2005 and VLSI-DAT since 2009. He served as
a Guest Editor for a special issue of the IEEE T RANSACTIONS ON C IRCUITS
AND S YSTEMS –II and as an MOOP Member of the Science China Information
Science.
C. Patrick
Yue (S’93–M’98–SM’05–F’15)
received the B.S.E.E. degree (Hons.) from The
University of Texas at Austin in 1992, and the
M.S. and Ph.D. degrees in electrical engineering
from Stanford University, Stanford, CA, USA, in
1994 and 1998, respectively.
He is a Professor with the Electronic and
Computer Engineering Department, and the
Founding Director of the Hong Kong University of
Science and Technology (HKUST)-Qualcomm Joint
Research and Innovation Laboratory at HKUST. His
current research interests include CMOS wireless and optical communication
IC design, high-frequency device modeling, LED SoC for visible light
communication and micro-display systems, and wireless power transfer for
IoT Applications.