7/9/22, 4:06 PM
Timing Exceptions | Success is all yours... :) :)
Timing Exceptions
Hi Guys,
Here is a post related to timing exceptions (Often asked topic in the interviews ;) )
Basis of Timing Exceptions
Timing exceptions are exclusively derived from circuit specifications at two broad levels:
The first level is derived from the system architecture. All system clocks and the clock-to-clock
relationship (synchronous / asynchronous / multi-cycle) are defined for each functional mode of
operation. System level control signals, which remain static during circuit operation, are also
identified.
The second level of timing exceptions are provided by IP or module designers. These deal with
signals internal to their module.
Types of Exceptions
False Paths
A false path is an attribute, set on a timing path, which obviates the need to perform any timing
checks on that timing path, thereby making the path invalid for purposes of static timing analysis.
The following examples depict commonly encountered scenarios that warrant the use of false path
timing exceptions:
1. Timing paths between asynchronous clocks. Signals traversing across asynchronous clock
domains require to be ‘synchronized’ to the destination clock domain. This is achieved by
inserting synchronizer circuitry as shown in Fig. 1.
2. Timing paths through static control signals, that do not change during the course of circuit
operation. Note that such signals should not change value at all during the course of circuit
operation.
Figure 1: Synchronizer Circuit
Multicycle Paths
A mutlicycle timing path is one that, functionally, requires either more or less than one (default) clock
cycle. Therefore, timing checks on such paths are adjusted accordingly. It is important to note that
multicycle attributes are handled separately for setup and hold checks. A multicycle attribute for
setup checks on a timing path adjusts the hold check automatically, on the basis of the definition of
a hold check. This automatic adjustment of hold check can be re-adjusted by specifying a multicycle
attribute for hold. Examples in Fig. 2 show how this works.
Note that multicycle exceptions, specially, re-adjustment of the hold check must be defined carefully,
keeping in mind the circuit functionality. A setup multicycle attribute does not automatically imply
readjustment of hold checks as shown in Fig. 2. Conversely, a mutlicycle setup timing exception,
without a corresponding multicycle hold exception will make timing closure difficult for the affected
timing path.
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7/9/22, 4:06 PM
Timing Exceptions | Success is all yours... :) :)
Figure 2: Setup and Hold Multicycle Paths
Multicycle timing exceptions are commonly applied to timing paths between synchronous clocks
which have different frequencies (one is derived from the other, or from a common source). Fig. 3
shows some examples.
Figure 3: Multicycle Paths across Synchronous Clocks (Different Frequencies)
However, note that all such paths (Fig. 3) are not necessarily multicycle.
Setting Case
This attribute relates to specifying a specific logic value (0 or 1) to a signal. Although this is not
strictly a timing exception, its impact on timing analysis is similar to that of a false path exception.
However, a case statement differs from a false path exception on two basic concepts:
1. A case statement can make associated timing paths invalid (Fig. 4). Therefore, it can have wider
implications on circuit timing as compared to a false path statement. This is desirable from a
timing point of view.
2. In general, all nodes in the fanout cone of a signal associated with a case statement is excluded
from all delay calculation related computation, including transition time calculations. This is
undesirable, and must be mitigated by running an additional delay calculation without any case
statements.
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Timing Exceptions | Success is all yours... :) :)
Figure 4: False Path vs Case
Disabled Timing Arcs
As the name suggests, this timing exception relates to disabling a timing arc. All timing paths
passing through a disabled timing arc become invalid. User specified timing arc disabling is not
commonly used, but is useful in certain advanced scenarios.
Set Maximum delay
The propagation delay through the combinational path must be less than or equal to max delay
Set minimum delay
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