ECE2300
Midterm #2
Combinational Logic
Applications
Spring 2025
Problem
Max
Scores
P1
16
P2
16
P3
20
P4
16
P5
16
P6
16
P7 (EC)
5
Total
105
Raw
Scores
Scaled
Scores
/100
/200
This is an open-book, open-note, asynchronous timed test of 120 minutes
(including the time to scan and upload). I am allowed to use any textbooks or
notes, whether online or printed, to assist me while I take the test. The test is
made available at 12:00pm on the exam date, and I have until 11:59pm the
following day to submit my work to Canvas. This applies to all students,
including those under DRC policies.
I will NOT do the following during the entire test window from 12:00pm to
11:59pm the following day:
• Have someone else take the test on my behalf.
• Communicate with another person or with any AI or expert-like interactive
platform to provide help or to get help, in verbal, written, electronic, or any
other form.
If I violate the above restrictions, I agree to receive a score of zero point for this
test with no appeal.
_____________________________
Student Name
________________________
Date
_____________________________
Student Signature
1
ECE2300
Midterm #2
Combinational Logic
Applications
Spring 2025
Problem 1 — 16 pts
Now We want to design a circuit for Z = | X - 1 |, which stands for the absolute value of X - 1. We
do that in the two steps below.
EA
T
a. Show the block diagram for computing Y = X - 1, where X=X7X6X5X4X3X2X1X0 and
Y=Y7Y6Y5Y4Y3Y2Y1Y0 are signed 2C numbers. Use a single 8-bit Adder/Subtracter and
clearly label all inputs and outputs. All inputs should have a label or a value. Any output(s) not
used should be marked NC (i.e. No Connect).
B7 B6 B5 B4 B3 B2 B1 B0
A7 A6 A5 A4 A3 A2 A1 A0
A+B /adder
A-B
8-bit
CH
Cout
Cin
S7 S6 S5 S4 S3 S2 S1 S0
NO
T
b. Show the block diagram for computing Z = | Y | = | X - 1 |, where Y=Y7Y6Y5Y4Y3Y2Y1Y0 is the
output of the adder/subtractor from the previous step and Z=Z7Z6Z5Z4Z3Z2Z1Z0. is the
absolute value of Y. Use another 8-bit Adder/Subtracter and clearly label all inputs and
outputs. All inputs should have a label or a value. Any output(s) not used should be marked
NC (for No Connect).
B7 B6 B5 B4 B3 B2 B1 B0
Cout
A7 A6 A5 A4 A3 A2 A1 A0
A+B /adder
A-B
8-bit
Cin
S7 S6 S5 S4 S3 S2 S1 S0
Is it possible to use an adder instead of an adder/subtractor for Step a? for Step b? Justify
your answers.
DO
c.
2
ECE2300
Midterm #2
Combinational Logic
Applications
Problem 2 —16 pts
Spring 2025
S2 S1 S0
We want to implement the function table
at right using one 4-to-1 multiplexer to
choose among 4 inputs P, Q, R, T.
a. Fill out the truth table of an encoder
that takes the three inputs S2, S1, S0
and generates the two select signals
C1, C0 for the 4-to-1 multiplexer. You
are free to determine which input is
selected based on C1C0 values.
C1 C0
0 0 0
0 0 1
EA
T
0 1 0
0 1 1
1 0 0
1 0 1
b. Derive and minimize the expressions C1 and C0 of the encoder.
1 1 0
Draw the block diagram showing the multiplexer and the encoder and the connections in
between. Label all inputs, outputs, and connections clearly.
NO
T
c.
CH
1 1 1
DO
d. The output of the above multiplexer is now connected to the
data input of a 1-to-8 demultiplexer according to the figure
shown at right, where D2 = MSB and D0 = LSB. Show the truth
tables for D2, D1, and D0 as functions of S2, S1, S0. Then
derive their minimized expressions.
3
ECE2300
Midterm #2
Combinational Logic
Applications
Spring 2025
Problem 3 — 20 pts
FA
The circuit at right represents
one slice of a 4-bit ALU.
Cin
A
B
R
Cout
Cin
A
B
Invert
R
Cout
Cin
A
B
Cin
A
B
Invert
F0 F1
b. Fill out the function table below for
the 4-bit ALU
R
NO
T
Invert
F0 F1
CH
Invert
EA
T
a. Connect the four slices to
form the 4-bit ALU in such
a way that it can perform
A + B and A - B. Label
inputs and outputs of all
slices.
Cout
F0 F1
R
Cout
F0 F1
F1 F0
Invert
0 0
0
0 0
1
0 1
0
0 1
1
1 0
0
1 0
1
1 1
0
1 1
1
Operation
DO
c. Even though we don’t have an explicit XNOR function, we can still get R = A XNOR B. State
what you need to apply at the inputs of the ALU to provide the XNOR function.
d. What values do we get at the outputs R (and Cout for arithmetic) for the following inputs:
-
F1F0 = 00, Invert = 0, A = 1010, B = 0011
R = ___________
Cout = ___
F1F0 = 00, Invert = 1, A = 1010, B = 0011
R = ___________
Cout = ___
F1F0 = 01, Invert = 0, A = 1010, B = 0011
R = ___________
F1F0 = 01, Invert = 1, A = 1010, B = 0011
R = ___________
F1F0 = 10, Invert = 0, A = 1010, B = 0011
R = ___________
F1F0 = 11, Invert = 0, A = 1010, B = 0011
R = ___________
4
ECE2300
Midterm #2
Combinational Logic
Applications
Spring 2025
Problem 6 — 16 pts
You are asked to model the following pseudo-code with digital logic:
// increment by 1
// decrement by 1
// R gets the same value as A
EA
T
if (P > Q) then R = A + 1,
else if (P < Q) then R = A - 1,
else R = A;
where P and Q are single-bit inputs, A and R represent 8-bit numbers.
CH
a. Show the truth table and the logic diagram of a single-bit comparator, where the inputs are P
and Q, and where the outputs are Gt (Greater than), Lt (Less than), and Eq (Equal to).
DO
NO
T
b. Use minimal logic to implement the pseudo code in the form of its block diagram. The
following logic blocks and gates are available to you: 8-bit adders, single-bit comparators (like
the one above), multiplexers (any appropriate size), basic gates (NOT, AND, OR), derived
gates (NAND, NOR, XOR, XNOR).
5
ECE2300
Midterm #2
Combinational Logic
Applications
Spring 2025
Problem 5 — 16 pts
Design a circuit that implements Y = 10*X + 53, where X = X2X1X0 is a 3-bit unsigned number.
The constants 10 and 53 are decimal numbers.
EA
T
a. What is the decimal range for Y? How many bits does Y need to hold the result?
CH
b. Noting that 10*X = 8*X + 2*X, line up each bit of the three addends to show which bit position
requires addition.
53 in binary =>
2*X in binary =>
8*X in binary =>
+
_______________________________
NO
T
Y in binary =>
DO
c. Using a minimal number of 4-bit adders, design the above circuit.
6
ECE2300
Midterm #2
Combinational Logic
Applications
Spring 2025
Problem 6 — 16 pts
A2 A1 A0
0 0 0
0 0 1
0 1 0
EA
T
Design a circuit that accepts a 3-bit input A = A2A1A0 and provides a 2-bit
output B = B1B0, the value of which represents the number of 0s at its inputs.
For example, A=011 contains one 0, so B=01. Similarly, A=100 contains two
0s and will produce B=10.
a. Show the truth table (at right) for this circuit.
B1 B0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CH
b. You are allowed to use only one 3-to-8 decoder, one 4-to-2 encoder, and
two 3-input OR gates. Draw the block diagram that implements the
desired circuit. Label all inputs, outputs, and internal connections as
clearly as possible.
In the above design, do we need the 4-to-2 encoder to provide a V(alid) output? Explain.
NO
T
c.
d. Do we need the 4-to-2 encoder to be priority encoder? Explain.
Problem 7 — 5 pts Extra Credit
DO
There is an error in the following implementation of the carry-out logic of a full adder. Identify the
error and propose a fix (that may involve changing some
logic gate). Show the work.
7