EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
EET206 – DIGITAL EELECTRONICS (L-T-P 3-1-0)
MODULE 1
Number Systems and Codes: Binary, Octal and hexadecimal conversions- ASCII code, Excess -3
code, Gray code, BCD, Error detection codes-Parity method.
Signed numbers- representation, addition and subtraction, Fixed point and floating-point
representation.
Logic gates, Universal gates, TTL and CMOS logic families-Internal diagram of TTL NAND gate
and CMOS NOR gate. Comparison of CMOS and TTL performance
MODULE 2
Boolean Laws and theorems, Sum of Products method, Product of Sum method – K map
representation and simplification (up to four variables) - Pairs, Quads, Octets, Don’t care
conditions.
Combinational circuits: Adders -Full adder and half adder, Subtractors- half subtractor and full
subtractor, 4-bit parallel binary adder/subtractor, Carry Look ahead adders.
MODULE 3
Comparators, Parity generators and checkers, Encoders, Decoders, , BCD to seven segment
decoder, Code converters, Multiplexers, Demultiplexers, Architecture of Arithmetic Logic Units
(Block schematic only).
-MODULE 4
Flip-Flops, SR, JK, D and T flip-flops, JK Master Slave Flip-flop, Preset and clear inputs,
Conversion of flip-flops.
Registers -SISO, SIPO, PISO, PIPO.
Up/Down Counters: Asynchronous Counters – Modulus of a counter – Mod-N counters Ring
counter, Johnson Counter
Synchronous counters, Design of Synchronous counters
MODULE 5
State Machines: State transition diagram, Moore and Mealy Machines
Digital to Analog converter –Specifications, Weighted resistor type, R-2R Ladder type.
Analog to Digital Converter – Specifications, Flash type, Successive approximation type.
Programmable Logic Devices - PAL, PLA, FPGA (Introduction and basic concepts only)
Introduction to Verilog, Implementation of AND, OR, half adder and full adder. Note: Course
assignments may be given in Verilog programming
1
2
3
CO1
CO2
CO3
CO4
CO5
REFERENCE BOOKS
Floyd T.L, “Digital Fundamentals”, 10/e, Pearson Education, 2011
Anand Kumar A., “ Fundamentals of Digital Circuits”, PHI Learning Pvt Ltd, 2012
Morris Mano M., “Digital Design”, Pearson Education, 2013
COURSE OUTCOMES
After the completion of the course the student will be able to
Identify various number systems, binary codes and formulate digital functions using
Boolean algebra.
Design and implement combinational logic circuits.
Design and implement sequential logic circuits.
Compare the operation of various analog to digital and digital to analog conversion
circuits.
Explain the basic concepts of programmable logic devices and VHDL.
Page 1 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
No. of
Lectures
MODULE
TOPIC COVERAGE
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Number systems and Binary codes (10 hours)
Introduction, Binary, Octal and hexadecimal conversions
ASCII code, Excess -3 code, Gray code, BCD
Error detection codes –Parity Codes
Signed numbers representation, addition and subtraction
Fixed point and floating-point representation
Logic gates and universal gates
TTL and CMOS logic families-Internal diagram of TTL NAND gate and
CMOS NOR gate. Comparison of CMOS and TTL performance
Boolean Algebra and Adders (9 hours)
Boolean Laws and theorems
Standard forms and canonical forms, Sum of Products method, Product of
Sums method
K-map representation and simplification (upto four variables) -Pairs,
Quads, Octets, Don’t care conditions. Realisation using universal gates
Adders - Full adder and half adder – Subtractors, half subtractor and full
subtractor
4-bit parallel binary adder/subtractor
Carry Look-ahead adders
Combinational Logic Circuits (9 hours)
2- and 4-bit magnitude comparator.
Parity generators and checkers
Encoder, Decoder-BCD to decimal and BCD to seven segment decoders
Realisation of Code converters
Multiplexers and implementation of functions, Demultiplexers
Architecture of Arithmetic Logic Units (Block schematic only)
Sequential circuits (10 hours)
Flip-Flops, SR, JK, D and T flip-flops, JK Master Slave Flip-flop, Preset
and clear inputs
Conversion of flip-flops
Registers -SISO, SIPO, PISO, PIPO
Up/Down Counters: Asynchronous Counters – Modulus of a counter –
Mod-N counters
Ring counter, Johnson Counter.
Design of Synchronous counters
State Machines, D/A and A/D converters and PLDs (7 hours)
State Machines: State transition diagram, Moore and Mealy Machines
Digital to Analog converter – R-2R ladder, weighted resistors
Analog to Digital Converter - Flash ADC, Successive approximation
Programmable Logic Devices - PAL, PLA-function implementation FPGA (Introduction and basic concepts only)
Introduction to VHDL, Implementation of AND, OR, half adder and full
adder.
2
2.1
2.2
2.3
2.4
2.5
2.6
3
3.1
3.2
3.3
3.4
3.5
3.6
4
4.1
4.2
4.3
4.4
4.5
4.6
5
5.1
5.2
5.3
5.4
5.5
2
1
1
1
2
1
2
1
2
2
2
1
1
2
1
2
1
2
1
2
2
1
2
1
2
1
1
1
2
2
Page 2 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
MODULE 1 – NUMBER SYSTEMS & BINARY CODES
Number Systems and Codes: Binary, Octal and hexadecimal conversions- ASCII code, Excess -3
code, Gray code, BCD, Error detection codes-Parity method.
Signed numbers- representation, addition and subtraction, Fixed point and floating-point
representation.
Logic gates, Universal gates, TTL and CMOS logic families-Internal diagram of TTL NAND gate
and CMOS NOR gate. Comparison of CMOS and TTL performance
1
Number systems and Binary codes (10 hours)
1.1
Introduction, Binary, Octal and hexadecimal conversions
2
1.2
ASCII code, Excess -3 code, Gray code, BCD
1
1.3
Error detection codes –Parity Codes
1
1.4
Signed numbers representation, addition and subtraction
1
1.5
Fixed point and floating-point representation
2
1.6
Logic gates and universal gates
1
1.7
TTL and CMOS logic families-Internal diagram of TTL NAND gate and
2
CMOS NOR gate. Comparison of CMOS and TTL performance
DIGITAL ELECTRONICS Vs ANALOG ELECTRONICS
The most significant difference between analog and digital electronics is that analog electronics deals
with continuously varying signals while the digital electronics deals with two state (binary) signals.
Basis of difference
ANALOG ELECTRONICS
DIGITAL ELECTRONICS
Definition
Analog electronics is the branch of Digital electronics is the branch of
electronics which deals with the electronics that deals with the
study of systems with analog signals. study of systems with digital
signals.
Type of signal used
Analog electronics involves the use Digital electronics uses discrete
of continuous time (analog) signals. time signals or two state signals.
Components used
Analog electronics mostly uses Digital electronics uses active
passive circuit components like elements only.
resistors, capacitors, etc. But
sometimes, active components like
transistors are also used.
Power consumption
Analog electronic systems consume Digital
electronic
systems
more power.
consume comparatively less
power.
Noise & distortion
In analog electronics, high noise and In digital electronics, there is very
distortion of signals is there.
low noise and distortion of
signals.
Processes involved
Analog electronics mainly deals with Digital electronics mainly deal
amplification, wireless transmission, with multiplexing, encoding,
rectification, etc. of the continuous decoding, analyzing, switching,
time signals.
mixing, etc. of the discrete time
signals.
Applications
Analog electronics is widely used in Digital electronics is extensively
radio and audio devices such as FM used
in
computers,
data
radios, TVs, telephones, etc.
processing
and
storage,
automation, digital watches and
many other digital devices.
Page 3 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
NUMBER SYSTEM
A system that is used for representing numbers is called the number system. In digital electronics, the
numbers are used to represent the information. Hence, it is important to learn and understand different
types of number systems so we can easily represent and interpret the information in the form of
numbers.
There are several types of number systems and the basis of this classification is the base or radix of
the number system. The base or radix of the number system is the total number of symbols used to
denote the numbers in the number system.
Depending on the base or radix, number systems can be classified into the following four major types:
 Decimal Number System
 Binary Number System
 Octal Number System
 Hexadecimal Number System
Number system
Decimal
Binary
Octal
Hexadecimal
Base
10
2
8
16
Digits / Symbols used
0,1,2,3,4,5,6,7,8,9
0,1
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7,8,9, A, B, C, D, E, F
Decimal Number System
The system of numbers which has base or radix 10, i.e. uses total 10 symbols to represent numbers
of the system is called decimal number system. The digits / symbols used in the decimal number
system are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9; where each of these symbols assigned a specific value.
The decimal number system is a position value system, which means the value of the digit depends
on the position in the number. To understand the concept of position value system, consider the
following example.
Let a decimal number 1234 which has total four digits, this number can also be written as follows:
(1103 )  (2 102 )  (3  101 )  (4 10 0 )  1234
Hence, from this example, we can see that the value of different digits of the number depends on their
respective position in the number.
Binary Number System
A number system with base or radix 2 is called binary number system. The binary number system
uses only 2 symbols (0 and 1) to represent binary numbers. All modern digital devices like computers,
combinational circuits, sequential circuits, etc. use the binary number system to operate.
The weights of binary system can be given by
Binary number
24
23
22
21
20
2-1
2-2
2-3
Equivalent decimal
16
8
4
2
1
0.5 0.25 0.125
Page 4 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Octal Number System
A number system which has base 8 is called an octal number system. Therefore, the octal number
system uses 8 symbols, (0, 1, 2, 3, 4, 5, 6, 7) to represent the number.
The weights of octal system can be given by
Octal number
83
82
81
80
8-1
8-2
Equivalent decimal 512
64
8
1
0.125 0.01562
Hexadecimal Number System
The number system with base or radix 16 is called as hexadecimal number system. Thus, the
hexadecimal number system uses 16 symbol to represent numbers. These symbols are 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, A, B, C, D, E, F where, A = 10; B = 11; C = 12; D = 13; E = 14; F = 15.
Octal number
162
161
160
16-1
16-2
Equivalent decimal 256
16
1
0.0625 0.0039
The hexadecimal number system is extensively used in microprocessors and microcontrollers. The
most significant advantage of hexadecimal number system over binary number system is that the
hexadecimal numbers are much shorter in size than the binary numbers, which makes these
hexadecimal numbers more readable.
BINARY TO DECIMAL
CONVERSIONS
110.1012 
 (1 22 )  (1 21 )  (0  20 )  (1 21 )  (0  22 )  (1 23 )
 (1 4)  (1 2)  (0  1)  (1  0.5)  (0  0.25)  (1 0.125)
 6.62510
OCTAL TO DECIMAL
246.288 
 (2  82 )  (4  81 )  (6  80 )  (2  81 )  (8  82 )
 166.37510
HEXADECIMAL TO
DECIMAL
1F .01B16 
 (1161 )  (15 160 )  (0 161 )  (1162 )  (1116 3 )
 31.006591810
DECIMAL TO BINARY
13.37510 = 1101.0112
DECIMAL TO OCTAL
73. 7510 = 111.68
Integer part
Operation Result Remainder
13/2
6
1 (LSB)
6/2
3
0
3/2
1
1
1/2
0
1 (MSB)
Integer part
Operation Result Remainder
73/8
9
1 (LSB)
9/8
1
1
1/8
0
1 (MSB)
Fractional part
Operation Result Carry
0.375 x 2 0.75
0
0.75 x 2
0.5
1
0.5 x 2
0
1
Fractional part
Operation Result Carry
0.75 x 8
0
6
Page 5 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
DECIMAL TO
HEXADECIMAL
82.2510 = 52.416
OCTAL TO BINARY
Integer part
Operation Result Remainder
82/16
5
2 (LSB)
5/16
0
5 (MSB)
352.5638 
Fractional part
Operation Result Carry
0.25 x 16
0
4
 011 101 010 . 101 110 011
 (011101010.101110011) 2
HEXADECIMAL TO
BINARY
A46.0916 
 1010 0100 0110.0000 1001
 (101001000110.00001001) 2
BINARY TO OCTAL
BINARY TO
HEXADECIMAL
OCTAL TO
HEXADECIMAL
HEXADECIMAL TO
OCTAL
101012 =
= 010 101
= 28 58
= 258
1011001110.0110111012 =
=0010 1100 1110.0110 1110 10002
= 2CE.6E816
Octal  Decimal  Hexadecimal
Hexadecimal  Decimal  Octal
We can convert a binary number into its equivalent decimal number as follows:
Let a binary number 1101 and we have to convert it into an equivalent decimal number, then
(1 23 )  (1 2 2 )  (0  21 )  (1 20 )  13
(1101) 2  (13)10
What is the decimal equivalent of (11001) 2 .
Ans:
(11001) 2  1 24  1 23  1 20  16  8  1  (25)10
What is the decimal equivalent of (1001.1001) 2 .
Ans:
(1001.1001) 2  1 23  1  2 0  1 21  1  24  8  1  0.5  0.0625  (9.5625)10
What is the decimal equivalent of (1100.0101)2.
Ans: (12.3125)10
What is the decimal equivalent of 10011011001.101102.
Ans: (1241.6875)10
What is the maximum number that we can count up to using 10 bits?
Ans: 2 N  1  210  1  1023
How many bits are needed to count up to a maximum of 511?
Page 6 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Ans: 2 N  1  511; N  9
What is the weight of the MSB of a 16-bit number?
Ans: 215  32768
CONVERSION FROM DECIMAL TO BINARY
Convert 3710 to binary.
Ans: Using repeated division method,
Operation
37/2
18/2
9/2
4/2
2/2
1/2
3710  1001012
Result
18
9
4
2
1
0
Remainder
1
LSB
0
1
0
0
1
MSB
Convert 163.87510 to binary.
Ans: Using repeated division method,
Operation Result
163/2
81
81/2
40
40/2
20
20/2
10
10/2
5
5/2
2
2/2
1
1/2
0
Remainder
1
LSB
1
0
0
0
1
0
1
MSB
Operation Result
0.875 x 2 0.75
0.75 x 2
0.5
0.5 x 2
0
Carry
1
1
1
163.87510 = 10100011.1112
Convert each decimal number to binary
a) 23 b) 57 c) 45.5 d) 105.15
CONVERSION FROM OCTAL TO DECIMAL
Let an octal number 124 and we need to find its equivalent in decimal, then
(1 82 )  (2  81 )  (4  80 )  84
Page 7 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
(124)8  (84)10
What is the decimal equivalent of 35616 .
Ans:
35616  3  162  5  161  6  160  768  80  6  85410
CONVERSION FROM DECIMAL TO OCTAL
Convert 100. 510 to octal.
Ans:
Operation Result Remainder
100/8
12
4
LSB
12/8
1
4
1/8
0
1
MSB
Operation Result
0.5 x 8
0
Carry
4
100. 510 = 144.48
CONVERSION FROM HEXADECIMAL TO DECIMAL
A hexadecimal number can be converted into an equivalent decimal number as follows:
(1162 )  ( A 161 )  ( F 160 ) 
(1 162 )  (10  161 )  (15 160 )  431
(1AF )16  (431)10
CONVERSION FROM DECIMAL TO HEXADECIMAL
Convert 42310 to hex.
Ans: Using repeated division method,
Operation Result Remainder
423/16
26
7
LSB
26/16
1
10
1/16
0
1
MSB
42310  1A716
Convert 100.12510 to hex.
Ans:
Operation Result
Remainder
100/16
6
4
LSB
6/16
0
6
MSB
Page 8 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Operation Result
0.25 x 16
0
Carry
2
100.12510 = 64.216
CONVERSION FROM BINARY TO OCTAL
Step 1: Divide the binary digits into groups of three (starting from the right)
Step 2: Convert each group of three binary digits to one octal digit
Convert 101012 to octal.
Ans:
101012 = 010 101 = 28 58 = 258
CONVERSION FROM OCTAL TO BINARY
Step 1: Convert each octal digit to a 3-digit binary number (the octal digits may be treated as decimal
for this conversion)
Step 2: Combine all the resulting binary groups (of 3 digits each) into a single binary number
Convert 258 to binary.
Ans:
258 = 210 510 = 0102 1012 = 101012
CONVERSION FROM BINARY TO HEXADECIMAL
Step 1: Divide the binary digits into groups of four (starting from the right)
Step 2: Convert each group of four binary digits to one hexadecimal digit
Find the hex equivalent of 1011001110.0110111012.
Ans:
1011001110.0110111012 = 0010 1100 1110.0110 1110 10002 = 2CE.6E816
CONVERSION FROM HEXADECIMAL TO BINARY
Step 1: Convert each hexadecimal digit to a 4-digit binary number (the hexadecimal digits may be
treated as decimal for this conversion)
Step 2: Combine all the resulting binary groups (of 4 digits each) into a single binary number
Find the binary equivalent of (17E.F6)16
Ans:
(17E.F6)16 = 0001 0111 1110.1111 01102 = 101111110.11110112
Page 9 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
CONVERSION TABLE
The following table shows the decimal numbers from 0 to 15 and their equivalent binary, octal and
hexadecimal numbers
Decimal
Binary
Octal
Hexadecimal
Number
Number
Number
Number
0
0000
0
0
1
0001
1
1
2
0010
2
2
3
0011
3
3
4
0100
4
4
5
0101
5
5
6
0110
6
6
7
0111
7
7
8
1000
10
8
9
1001
11
9
10
1010
12
A
11
1011
13
B
12
1100
14
C
13
1101
15
D
14
1110
16
E
15
1111
17
F
All digital systems require to implement only two states, i.e., low (off) and high (on) that can be easily
implemented using the binary number system. Hence, in digital electronics, the binary number system
is most widely used because it uses the minimum number of digits. However, the hexadecimal number
system is also used in some specialized digital devices such microprocessors and microcontrollers.
Express the following numbers in decimal
(a) (10110.0101)2
(b) (16.5)16
(c) (26.24)8
(d) (DADA.B)16
(e) (1010.1101)2
BINARY CODES
The binary coding system (mentioned above) becomes very cumbersome to handle when used to
represent larger decimal numbers. To overcome this shortcoming, and also to perform many other
special functions, several binary codes are used.
Binary Coded Decimal (BCD) Code
Binary-coded decimal is a way to convert decimal numbers into their binary equivalents. However,
binary-coded decimal is not the same as simple binary representation.
Page 10 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The BCD equivalent of a decimal number is written by replacing each decimal digit in the integer
and fractional parts with its four-bit binary equivalent.
As an example, the BCD equivalent of (23.15)10 is written as (0010 0011.0001 0101)BCD. The BCD
code described above is more precisely known as the 8421 BCD code, with 8, 4, 2 and 1 representing
the weights of different bits in the four-bit groups, starting from MSB and proceeding towards LSB.
Each digit is encoded separately. The full number is first segregated into its individual digits. These
digits are then represented by their equivalent 4-bit binary-coded decimal codes as shown in this truth
table.
Digit
BCD
Code
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
As an example, consider a decimal number 1764.
1
7
0001
0111
6
0110
4
0100
BCD code is 0001 0111 0110 0100.
Features of BCD code
 A number with k decimal digits will require 4k bits in BCD.
 The binary-coded decimal representation of a number is not the same as its simple binary
representation. For example, in binary form, the decimal quantity 1895 appears as
11101100111. In binary-coded decimal, it appears as 0001100010010101.
 A decimal number in BCD is the same as its equivalent binary number only when the
number is between 0 and 9.
 The binary combinations 1010 through 1111 are not used and have no meaning in BCD.
 Compared to the binary system, it is easy to code and decode binary-coded decimal numbers.
Thus, binary-coded decimal offers a fast and efficient system to convert decimal numbers into
binary numbers.
 Binary-coded decimal is useful in digital displays, where it can be difficult to manipulate or
display large numbers.
Excess-3 code
Page 11 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The excess-3 code is another important BCD code. It is particularly significant for arithmetic
operations as it overcomes the shortcomings encountered while using the 8421 BCD code to add two
decimal digits whose sum exceeds 9. The excess-3 code has no such limitation, and it considerably
simplifies arithmetic operations.
The excess-3 code for a given decimal number is determined by adding ‘3’ to each decimal digit in
the given number and then replacing each digit of the newly found decimal number by its four-bit
binary equivalent. It may be mentioned here that, if the addition of ‘3’ to a digit produces a carry, as
is the case with the digits 7, 8 and 9, that carry should not be taken forward. The result of addition
should be taken as a single entity and subsequently replaced with its excess-3 code equivalent.
Digit
Excess-3
Code
0
0011
1
0100
2
0101
3
0110
4
0111
5
1000
6
1001
7
1010
8
1011
9
1100
As an example, let us find the excess-3 code for the decimal number 597.
 The addition of ‘3’ to each digit yields the three new digits/numbers ‘8’, ‘12’ and ‘10’.
 The corresponding four-bit binary equivalents are 1000, 1100 and 1010 respectively.
 The excess-3 code for 597 is therefore given by: 1000 1100 1010 = 100011001010.
Find the excess-3 equivalent of (237.75)10.
Ans: Integer part = 237. The excess-3 code for (237)10 is obtained by replacing 2, 3 and 7 with the four-bit
binary equivalents of 5, 6 and 10 respectively. This gives the excess-3 code for (237)10 as: 0101 0110
1010 = 010101101010
Fractional part = .75. The excess-3 code for (.75)10 is obtained by replacing 7 and 5 with the four-bit
binary equivalents of 10 and 8 respectively. That is, the excess-3 code for (.75) 10 = .10101000
Combining the results of the integral and fractional parts, the excess-3 code for (237.75) 10 =
010101101010.10101000.
Find the decimal equivalent of the excess-3 number 110010100011.01110101.
Ans: The excess-3 code = 110010100011.01110101 = 1100 1010 0011.0111 0101. Subtracting 0011 from
each four-bit group, we obtain the new number as: 1001 0111 0000.0100 0010. Therefore, the decimal
equivalent = (970.42)10
Gray Code
Page 12 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Gray code is an unweighted binary code in which two successive values differ only by 1 bit.
The following table lists the binary and Gray code equivalents of decimal numbers 0–15.
Decimal
Binary
Gray
0
0000
0000
1
0001
0001
2
0010
0011
3
0011
0010
4
0100
0110
5
0101
0111
6
0110
0101
7
0111
0100
8
1000
1100
9
1001
1101
10
1010
1111
11
1011
1110
12
1100
1010
13
1101
1011
14
1110
1001
15
1111
1000
Note: The last and the first entry also differ by only 1 bit. This is known as the cyclic property of the
Gray code.
Binary to Gray code conversion
A given binary number can be converted into its Gray code equivalent by going through the following
steps:
1 Begin with the most significant bit (MSB) of the binary number. The MSB of the Gray code
equivalent is the same as the MSB of the given binary number.
2 The second most significant bit, adjacent to the MSB, in the Gray code number is obtained by
adding the MSB and the second MSB of the binary number and ignoring the carry, if any. That
is, if the MSB and the bit adjacent to it are both ‘1’, then the corresponding Gray code bit
would be a ‘0’.
3 The third most significant bit, adjacent to the second MSB, in the Gray code number is obtained
by adding the second MSB and the third MSB in the binary number and ignoring the carry, if
any.
4 The process continues until we obtain the LSB of the Gray code number by the addition of the
LSB and the next higher adjacent bit of the binary number.
Example of conversion process – (1011)2 to Gray code
Page 13 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Binary
Gray code
Binary
Gray code
Binary
Gray code
Binary
Gray code
1011
1--1011
11-1011
1111011
1110
Gray code to Binary conversion
A given Gray code number can be converted into its binary equivalent by going through the following
steps:
1 Begin with the most significant bit (MSB). The MSB of the binary number is the same as the
MSB of the Gray code number
2 The bit next to the MSB (the second MSB) in the binary number is obtained by adding the
MSB in the binary number to the second MSB in the Gray code number and ignoring the
carry, if any.
3 The third MSB in the binary number is obtained by adding the second MSB in the binary
number to the third MSB in the Gray code number. Again, carry, if any, is to be ignored.
4 The process continues until we obtain the LSB of the binary number
Example of conversion process –Gray code 1110 to binary
Gray Code
1110
Binary
1--Binary
10-Binary
101Binary
1011
Applications of Gray code:
1 The Gray code is used in the transmission of digital signals as it minimizes the occurrence of
errors
2 The Gray code is preferred in angle-measuring devices.
3 The Gray code is used for labelling the axes of Karnaugh maps
4 The use of Gray codes to address program memory in computers minimizes power
consumption
5 Gray codes are also very useful in genetic algorithms
Error Detection Codes: Parity Bit Method
Error Detection Codes: The binary information is transferred from one location to another location
through some communication medium. The external noise can change bits from 1 to 0 or 0 to 1. This
changes in values changes the meaning of actual message and is called error. For efficient data
transfer, there should be an error detection and correction codes. An error detection code is a binary
Page 14 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
code that detects digital errors during transmission. To detect error in the received message, we add
some extra bits to the actual data.
Parity Bit Method: It is the simplest technique for detecting and correcting single-bit errors that may
have occurred during the transmission. The MSB of an 8-bits word is used as the parity bit and the
remaining 7 bits are used as data or message bits. The parity of 8-bits transmitted word can be either
even parity or odd parity.
Even parity -- Even parity means the number of 1's in the given word including the parity bit should
be even.
Odd parity -- Odd parity means the number of 1's in the given word including the parity bit should
be odd.
The parity bit can be set to 0 and 1 depending on the type of the parity required.
 For even parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is even.
Shown in fig. (a).
 For odd parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is odd.
Shown in fig. (b).
How Does Error Detection Take Place?
Suppose that a sender wants to send the data 1001011 using even parity check method. It will add the
parity bit as shown below.
The receiver will decide whether an error has occurred by counting whether the total number of 1s is
even.
Parity checking at the receiver can detect the presence of an error if the parity of the receiver signal
is different from the expected parity. That means, if it is known that the parity of the transmitted
Page 15 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
signal is always going to be "even" and if the received signal has an odd parity, then the receiver can
conclude that the received signal is not correct. If an error is detected, then the receiver will ignore
the received byte and request for retransmission of the same byte to the transmitter.
ASCII Code
The ASCII stands for American Standard Code for Information Interchange. ASCII codes are used
to represent alphanumeric data in computers, communications equipment and other related devices.
The ASCII code is made up of a three-bit group, which is followed by a four-bit code.
The ASCII Code is a 7 alphanumeric code.
This code can represent 127 different characters.
 The ASCII code starts from 0016 to 7F16 (0 to 127).
 Code 48 to 57 is used to represent numbers 0 to 9.
 Code 65 to 90 is used to represent letters A to Z
 Code 97 to 122 is used to represent letters a to z.
The ASCII characters are classified into the following groups:


Control Characters
The non-printable characters used for sending commands to the PC or printer are known as control
characters. We can set tabs, and line breaks functionality by this code.
Special Characters
All printable characters that are neither numbers nor letters come under the special characters. These
characters contain technical, punctuation, and mathematical characters with space also.
Numbers Characters
This category of ASCII code contains ten Arabic numerals from 0 to 9. The range from 48 to 57
comes under this category.
Letters Characters
In this category, two groups of letters are contained, i.e., the group of uppercase letters and the group
of lowercase letters. The range from 65 to 90 and 97 to 122 comes under this category.
Decimal Character
Decimal Character
Decimal Character
Code
Code
Code
48
0
65
A
97
a
49
1
66
B
98
b
50
2
67
C
99
c
Page 16 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
51
52
53
54
55
56
57
3
4
5
6
7
8
9
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Example: Binary to ASCII
(100101011000011110110)2 =
= 1001010 1100001 1110110
= (64+8+2)10 (64+32+1)10 (64+32+16+4+2)10
= (74)10 (97)10 (118)10
= Jav
64
32
16
8
1
64
32
16
8
1
64
32
16
8
1
0
0
1 0 1 0
4
2
1
1
0
0 0 0 1
4
2
1
1
1
0 1 1 0
4
2
1
SIGNED NUMBERS
Page 17 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Different formats used for binary representation of both positive and negative decimal numbers
include the sign-bit magnitude method, the 1’s complement method and the 2’s complement method.
Sign- magnitude representation
In the sign-bit magnitude representation of positive and negative decimal numbers, the MSB
represents the ‘sign’, with a ‘0’ denoting a plus sign and a ‘1’ denoting a minus sign. The remaining
bits represent the magnitude.
For example: In 5-bit representation, + 9 is represented by 01001 and – 9 is represented by 11001
Though this method of representing the signed numbers is straight forward, yet it is not normally used
in the digital system since the realization of this method by digital circuit is very complex. The most
commonly used method for representing the signed binary numbers is 2’s complement method.
Note:
For positive number, MSB = 0
For negative number, MSB = 1
1’s complement representation
In the 1’s complement format, the positive numbers remain unchanged. The negative numbers are
obtained by taking the 1’s complement of the positive counterparts.
For example: In 5-bit representation, + 9 is represented by 01001 and – 9 is represented by 10110.
2’s complement representation
In the 2’s complement representation of binary numbers, the MSB represents the sign, with a ‘0’ used
for a plus sign and a ‘1’ used for a minus sign. The remaining bits are used for representing magnitude.
Positive magnitudes are represented in the same way as in the case of sign-bit or 1’s complement
representation. Negative magnitudes are represented by the 2’s complement of their positive
counterparts.
For example: In 5-bit representation, + 9 is represented by 01001 and – 9 is represented by 10111.
The 2’s complement format is very popular as it is very easy to generate the 2’s complement of a
binary number and also because arithmetic operations are relatively easier to perform when the
numbers are represented in the 2’s complement format.
Note: Representation of positive number is same in all the three representations.
For negative number, MSB = 0
Represent +120 and -120 in i) sign-magnitude form ii) 1’s complement form and iii) 2’s
complement form using 8 bits.
Ans:
Operation Result
Remainder
120/2
60
0
LSB
60/2
30
0
30/2
15
0
15/2
7
1
7/2
3
1
3/2
1
1
1
0
1
MSB
Page 18 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
+120
-120
Sign-magnitude form
01111000
11111000
I’s complement form
01111000
10000111
2’s complement form
01111000
10001000
Represent the following binary numbers in i) sign-magnitude form and ii) 2’s complement form
using 8 bits.
a) +3 and -3
b) +14 and -14
c) +82 and -82
d) +127 and -127
Ans:
Sign-magnitude form
2’s complement form
+3
00000011
00000011
-3
10000011
11111101
+14
00001110
00001110
-14
10001110
11110010
+82
01010010
01010010
-82
11010010
10101110
+127
01111111
01111111
-127
11111111
10000001
Represent -101.703125 in i) sign-magnitude form ii) 1’s complement form and iii) 2’s complement
form using 8 bits for integer and 8 bits for fraction.
Ans:
Operation Result
Remainder
101/2
50
1
LSB
50/2
25
0
25/2
12
1
12/2
6
0
6/2
3
0
3/2
1
1
1
0
1
MSB
Operation
0.703125 x 2
0.40625 x 2
0.8125 x 2
0.625 x 2
0.25
0.5
Result
0.40625
0.8125
0.625
0.25
0.5
0
Carry
1
0
1
1
0
1
Page 19 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Sign-magnitude form
11100101.10110100
I’s complement form
10011010.01001011
2’s complement form
10011010.01001100
(adding 0.00000001)
Express the following decimal numbers using 8 bits in a) sign-magnitude form b) 1’s complement
form and c) 2’s complement form.
i)
-34
ii)
+57
iii)
-99
iv)
+115
BINARY ADDITION / SUBTRACTION IN 2’S COMPLEMENT FORM
The 2’s complement is the most commonly used code for processing positive and negative binary
numbers. It forms the basis of arithmetic circuits in modern computers. When the decimal numbers
to be added are expressed in 2’s complement form, the addition of these numbers, following the basic
laws of binary addition, gives correct results. Final carry obtained, if any, while adding MSBs should
be disregarded.
Note If MSB of the sum term (sign bit) is 0, the result is positive and is in true binary form.
1
Note If MSB of the sum term (sign bit) is 1, the result is negative and is in 2’s compliment
2
form.
To illustrate this, we will consider the following four different cases:
1. Both the numbers are positive.
2. Larger of the two numbers is positive.
3. The larger of the two numbers is negative.
4. Both the numbers are negative.
Case 1
Consider the decimal numbers +37 and +18.
The 2’s complement of +37 in eight-bit representation = 00100101.
The 2’s complement of +18 in eight-bit representation = 00010010.
The addition of the two numbers, that is, +37 and +18, is performed as follows
0 0 1 0 0 1 0 1
+ 0 0 0 1 0 0 1 0
0 0 1 1 0 1 1 1
The decimal equivalent of (00110111)2 is (+55)10, which is the correct answer.
Case 2
Consider the decimal numbers +37 and -18.
The 2’s complement of +37 in eight-bit representation = 00100101.
The 2’s complement of -18 in eight-bit representation = 11101110.
Page 20 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The addition of the two numbers, that is, +37 and -18, is performed as follows
0 0 1 0 0 1 0 1
+ 1 1 1 0 1 1 1 0
0 0 0 1 0 0 1 1
The final carry has been disregarded.
The decimal equivalent of (00010011)2 is +19, which is the correct answer.
Case 3
Consider the decimal numbers +18 and -37.
The 2’s complement of +18 in eight-bit representation = 00010010.
The 2’s complement of -37 in eight-bit representation = 11011011.
The addition of the two numbers, that is, +18 and -37, is performed as follows
0 0 0 1 0 0 1 0
+ 1 1 0 1 1 0 1 1
1 1 1 0 1 1 0 1
The decimal equivalent of (11101101)2 is -19, which is the correct answer.
Case 4
Consider the decimal numbers -18 and -37.
The 2’s complement of -18 in eight-bit representation = 11101110.
The 2’s complement of -37 in eight-bit representation = 11011011.
The addition of the two numbers, that is, +18 and -37, is performed as follows
1 1 1 0 1 1 1 0
+ 1 1 0 1 1 0 1 1
1 1 0 0 1 0 0 1
The final carry has been disregarded.
The decimal equivalent of (11001001)2 is -55, which is the correct answer.
Different steps to be followed to do addition in 2’s complement arithmetic are summarized as follows:
1
Represent the two numbers to be added in 2’s complement form
2
Do the addition using basic rules of binary addition
3
Disregard the final carry, if any
4
The result of addition is in 2’s complement form
Subtract 14 from 46 using the 8-bit 2’s complement arithmetic.
Ans:
Operation Result
14/2
7
7/2
3
3/2
1
1/2
0
Remainder
0
LSB
1
1
1
MSB
+14 = 00001110
Page 21 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
2’s complement of -14 = 11110010
Operation Result
Remainder
46/2
23
0
LSB
23/2
11
1
11/2
5
1
5/2
2
1
2/2
1
0
1/2
0
1
MSB
+46 = 00101110
46 – 14 =
0 0 1 0 1 1 1 0
+ 1 1 1 1 0 0 1 0
0 0 1 0 0 0 0 0
Since the sign bit is 0, the result is in true binary form.
64
32
16
8
4
2
1
0
1
0
0 0 0 0
46 – 14 = 32.
Subtract 75 from 26 using the 8-bit 2’s complement arithmetic.
Ans:
Operation Result
Remainder
75/2
37
1
LSB
37/2
18
1
18/2
9
0
9/2
4
1
4/2
2
0
2/2
1
0
1/2
0
1
MSB
+75 = 01001011
2’s complement of -75 = 10110101
Operation Result
Remainder
26/2
13
0
LSB
13/2
6
1
6/2
3
0
3/2
1
1
1/2
0
1
MSB
+26 = 00011010
26 – 75 =
0 0 0 1 1 0 1 0
+ 1 0 1 1 0 1 0 1
1 1 0 0 1 1 1 1
Page 22 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Since the sign bit is 1, the result is in 2’s complement form.
Sign-magnitude form is 10110001
64
32
16
8
4
2
1
0
1
1
0 0 0 1
26 – 75 = -(32+16+1) = -49
Find 43.25 – 89.75 using the 12-bit (8 bits for integer and 4 bits for fraction) 2’s complement
arithmetic.
Ans:
Operation Result
Remainder
89/2
44
1
LSB
44/2
22
0
22/2
11
0
11/2
5
1
5/2
2
1
2/2
1
0
1/2
0
1
MSB
+89 = 01011001
Operation
Result
Carry
0.75 x 2
0.5
1
0.5 x 2
0
1
+89.75 = 01011001.1100
2’s complement of -89.75 = 10100110.0100
Operation Result
43/2
21
21/2
10
10/2
5
5/2
2
2/2
1
1/2
0
Remainder
1
LSB
1
0
1
0
1
MSB
+43 = 00101011
Operation
0.25 x 2
0.5 x 2
Result
0.5
0
Carry
0
1
+43.25 = 00101011.0100
43.25 - 89.75 =
+
0
1
0
0
1
1
0
0
1
0
0
1
1
1
1
0
.
.
0
0
1
1
0
0
0
0
Page 23 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1 1 0 1 0 0 0 1 .
1
Since the sign bit is 1, the result is negative and in 2’s complement form.
Sign magnitude form = 00101110.1000
64
32
16
8
4
2
1
0.5
0.25
0.125
0.0625
0
1
0
1 1 1 0
1
0
0
0
0
0
0
43.25 - 89.75 = - (32 + 8 + 4 + 2 + 0.5) = -46.5
BINARY ADDITION / SUBTRACTION IN 1’S COMPLEMENT FORM
In binary subtraction in 1’s complement form, if there is a carry, add the carry to the LSB. Now, if
the MSB is 0, the result is positive and is in true binary form. If the MSB is 1 (whether there is carry
or no carry), the result is negative and is in 1’s complement form.
Subtract 14 from 25 using the 8-bit 1’s complement arithmetic.
Ans:
Operation Result
Remainder
14/2
7
0
LSB
7/2
3
1
3/2
1
1
1/2
0
1
MSB
+14 = 00001110
1’s complement of -14 = 11110001
Operation Result
Remainder
25/2
12
1
LSB
12/2
6
0
6/2
3
0
3/2
1
1
1/2
0
1
MSB
+25 = 00011001
25 – 14 =
0 0 0 1 1 0 0 1
+ 1 1 1 1 0 0 0 1
0 0 0 0 1 0 1 0
There is an end around carry.
0 0 0 0 1 0 1 0
+
1
0 0 0 0 1 0 1 1
Since the sign bit is 0, the result is positive and in true binary form.
64
32
16
8
0
0
0
1 0 1 1
4
2
1
25 – 14 = 8 + 2 + 1 = 11.
Page 24 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Subtract 25 from 14 using the 8-bit 1’s complement arithmetic.
Ans:
Operation Result
Remainder
25/2
12
1
LSB
12/2
6
0
6/2
3
0
3/2
1
1
1/2
0
1
MSB
+25 = 00011001
1’s complement of -25 = 11100110
Operation Result
14/2
7
7/2
3
3/2
1
1/2
0
Remainder
0
LSB
1
1
1
MSB
+14 = 00001110
14 – 25 =
0 0 0 0 1 1 1 0
+ 1 1 1 0 0 1 1 0
1 1 1 1 0 1 0 0
Since the sign bit is 1, the result is negative and in 1’s complement form.
Sign magnitude form = 10001011
64
32
16
8
4
2
1
0
0
0
1 0 1 1
14 – 25 = - (8 + 2 + 1) = -11.
Find 43.25 – 89.75 using the 12-bit (8 bits for integer and 4 bits for fraction) 1’s complement
arithmetic.
Ans:
Operation Result
Remainder
89/2
44
1
LSB
44/2
22
0
22/2
11
0
11/2
5
1
5/2
2
1
2/2
1
0
1/2
0
1
MSB
+89 = 01011001
Operation
Result
Carry
0.75 x 2
0.5
1
0.5 x 2
0
1
Page 25 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
+89.75 = 01011001.1100
1’s complement of -89.75 = 10100110.0011
Operation Result
43/2
21
21/2
10
10/2
5
5/2
2
2/2
1
1/2
0
Remainder
1
LSB
1
0
1
0
1
MSB
+43 = 00101011
Operation
0.25 x 2
0.5 x 2
Result
0.5
0
Carry
0
1
+43.25 = 00101011.0100
43.25 - 89.75 =
0 0 1 0 1 0 1 1 .
0
1 0 1 0 0 1 1 0 .
0
1 1 0 1 0 0 0 1 .
0
Since the sign bit is 1, the result is negative and in 1’s complement form.
Sign magnitude form = 10101110.1000
+
64
32
16
8
4
2
1
0.5
0.25
0.125
0.0625
0
1
0
1 1 1 0
1
0
0
0
1
0
1
0
1
1
0
1
1
43.25 - 89.75 = - (32 + 8 + 4 + 2 + 0.5) = -46.5
Find -8.25 – 4.75 using the 10-bit (6 bits for integer and 4 bits for fraction) 1’s complement
arithmetic.
Ans:
Sign-magnitude form of 8.25 = 001000.0100
1’s complement of -8.25 = 110111.1011
Sign-magnitude form of 4.75 = 000100.1100
1’s complement of -4.75 = 111011.0011
-8.25 - 4.75 =
+
1
1
1
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
.
.
.
1
0
1
0
0
1
1
1
1
1
1
0
1
1
0
0
1
0
.
1
1
1
1
1
0
0
1
0
.
1
1
1
0
1
1
There is an end around carry.
+
Page 26 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Since the sign bit is 1, the result is negative and in 1’s complement form.
Sign magnitude form = 101101.0000
16
8
4
2
1
0.5
0.25
0.125
0.0625
0
1 1 0 1
0
0
0
0
-8.25 - 4.75 = - (8 + 4 + 1) = -13
Convert each pair of decimal numbers to 10-bit binary and add using the 2’s complement form.
i)
46 and 25
ii)
46 and -25
iii)
-46 and 25
iv)
-46 and -25
Convert each pair of decimal numbers to 10-bit binary and add using the 1’s complement form.
i)
46 and 25
ii)
46 and -25
iii)
-46 and 25
iv)
-46 and -25
Fixed Point Representation
In computers, fixed-point representation is a real data type for numbers. It has a fixed number of bits
for the integral and fractional parts. For example, if given fixed-point representation is IIIII.FFF, we
can store a minimum value of 00000.001 and a maximum value of 99999.999.
There are three parts of the fixed-point number representation: Sign bit, Integral
part, and Fractional part. The below figure depicts it.
Sign bit: - The fixed-point number representation in binary uses a sign bit. The negative number has
a sign bit 1, while a positive number has a bit 0.
Integral part: - The integral part in fixed-point numbers is of different lengths at different places. It
depends on the register's size; for an 8-bit register, the integral part is 4 bits.
Fractional part: - The Fractional part is of different lengths at different places. It depends on the
registers; for an 8-bit register, the fractional part is 3 bits.
How to write numbers in Fixed-point notation
The number considered is 4.5
Step 1: We will convert the number 4.5 to binary form. 4.5 = 100.1
Page 27 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Step 2: Represent the binary number in fixed-point notation with the following format
Floating Point Representation
Floating-point numbers are in general expressed in the form
N  m  be
where m is called the mantissa, e is called the exponent, and b is the base of the number system.
In the case of decimal, hexadecimal and binary number systems will be written as follows:
Decimal system
N  m  10e
Hexadecimal system
N  m  16e
Binary system
N  m  2e
For example, decimal numbers 0.0003754 and 3754 will be represented in floating-point notation as
3.754 × 10−4 and 3.754 × 103 respectively.
Floating Point representation doesn't reserve any specific number of bits for the integer or fractional
parts. But instead, it reserves certain bits for the mantissa and a fixed number of bits to the exponent.
A floating-point representation has three parts: Sign bit, Exponent Part, and Mantissa. We can see
the below diagram to understand these parts.
Sign bit:- The floating-point numbers in binary uses a sign bit. A negative number has a sign bit 1,
while a positive number has a sign bit 0. The sign of any number depends on mantissa, not on
exponent.
Mantissa Part: - The mantissa part (fractional part) is of different lengths at different places. It
depends on registers like for a 16-bit register, and mantissa part is of 10 bits.
Exponent Part: - It is the power of the number. It depends on the size of the register. For example,
in the 16-bit register, the exponent part is of 5 bits.
How to write numbers in Floating-point notation
The number considered is 53.5
Step 1: We will convert the number 53.5 to binary form. 53.5 = 110101.1
Step 2: Normalize the number (base is 2) = (1.101011) * 25.
Step 2: Represent the binary number in floating-point notation with the following format
The binary representation of IEEE 754 floating point is given below:
Page 28 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Convert the decimal number 53.5 to a single precision floating point binary number.
Ans:53.5  110101.1  1.10101100000000000000000  25
0
00000101
10101100000000000000000
Advantages of Fixed-Point Representation
1
Fixed point representation is easy to implement
2
Fixed-point calculations can be completed more quickly than floating-point calculations.
Disadvantages of Fixed-Point Representation
1
In fixed point representation, range of representable numbers is limited
2
Compared to floating-point numbers, fixed-point numbers are less precise.
3
Fixed-point programming is sometimes more difficult than floating-point programming.
This is due to the fact that fixed-point values are less precise, making it more crucial to
take precautions to prevent overflow and underflow.
Advantages of Floating-Point Representation
1
Greater range of numbers can be represented
Disadvantages of Floating-Point Representation
1
More storage space is needed
2
Slower processing times
3
Lack of precision – some real numbers can only be represented approximately.
LOGIC GATES
A logic gate is a basic building block of a digital circuit that has two inputs and one output. The
relationship between the input and the output is based on a certain logic. These gates are implemented
using electronic switches like transistors, diodes. But, in practice, basic logic gates are built using
CMOS technology, FETs, and MOSFETs.
Page 29 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
There are three basic logic gates, namely the OR gate, the AND gate and the NOT gate. Other logic
gates that are derived from these basic gates are the NAND gate, the NOR gate, the EXCLUSIVEOR gate and the EXCLUSIVE-NOR gate.
A truth table lists all possible combinations of input binary variables and the corresponding outputs
of a logic system. When the number of input binary variables is only one, then there are only two
possible inputs, i.e. ‘0’ and ‘1’. If the number of inputs is two, there can be four possible input
combinations, i.e. 00, 01, 10 and 11.
AND gate
An AND gate is a logic circuit having two or more inputs and one output. The AND gate produces
an output of "1" only when all of its inputs are "1"; otherwise, the output is "0". It is represented by
the Boolean expression Y = A.B (read as Y equals A AND B).
A two-input AND gate is shown below.
A
B
Y  A B
A
B
Y
0
0
1
1
0
1
0
1
0
0
0
1
OR gate
An OR gate is a logic circuit that performs an OR operation on the circuit’s inputs. The OR operation
produces a result (output) of 1 whenever any input is a 1. Otherwise, the output is 0. It is represented
by the Boolean expression “Y = A + B” (read as Y equals A OR B).
A two-input OR gate is shown below.
A
Y  A B
B
A
B
Y
0
0
1
1
0
1
0
1
0
1
1
1
NOT gate
A NOT gate is a one-input, one-output logic circuit whose output is always the complement of the
input. A logic ‘0’ at the input produces a logic ‘1’ at the output, and vice versa.
A
YA
A
Y
0
1
1
0
X-OR gate
The EXCLUSIVE-OR gate, commonly written as X-OR gate, is a two-input, one-output gate. If both
the input signals are the same, the output is 0. Otherwise, the output is 1.
A
B
Y  A B
A
B
Y
0
0
1
1
0
1
0
1
0
1
1
0
Page 30 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The output of a two-input X-OR gate is expressed by Y  A  B  AB  AB .
Note: Three or more variable X-OR gates do not exist. When more than two variables are to be XOred, a number of two-input X-OR gages will be used.
NAND gate
NAND stands for NOT AND. An AND gate followed by a NOT circuit makes it a NAND gate. The
output of a NAND gate is a logic ‘0’ when all its inputs are a logic ‘1’. For all other input
combinations, the output is a logic ‘1’. NAND gate operation is logically expressed as Y  A.B .
A
B
Y  A B
A
B
Y
0
0
1
1
0
1
0
1
1
1
1
0
NOR gate
NOR stands for NOT OR. An OR gate followed by a NOT circuit makes it a NOR gate. The output
of a NOR gate is a logic ‘1’ when all its inputs are logic ‘0’. For all other input combinations, the
output is a logic ‘0’. The output of a two-input NOR gate is logically expressed as Y  A  B .
A
Y  A B
B
A
B
Y
0
0
1
1
0
1
0
1
1
0
0
0
X-NOR gate
EXCLUSIVE-NOR (commonly written as X-NOR) means NOT of X-OR, i.e. the logic gate that we
get by complementing the output of an X-OR gate. If both the input signals are the same, the output
is 1. Otherwise, the output is 0. The output of a two-input X-NOR gate is logically expressed as
Y  A  B  A  B  A.B  A.B .
A
Y  A B
B
A
B
Y
0
0
1
1
0
1
0
1
1
0
0
1
Draw the logic diagram and construct the truth table for the expression X  AB  BC  AC
Ans:C
A
B
X  AB  BC  AC
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
1
1
1
1
Page 31 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
A
0
1
1
1
0
1
0
1
1
B
AB  BC  AC
Show that A  B  AB  AB and construct the corresponding logic diagrams.
Ans:-
A
B
A B
A
B
AB
AB
AB  AB
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
0
0
1
1
0
A
A B
B
A
B
AB  AB
Show that A  B  ( A  B ) AB and construct the corresponding logic diagrams.
Ans:-
A
B
A B
A
B
A B
AB
( A  B ) AB
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1
0
A
B
A B
Page 32 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
A
B
( A  B ) AB
UNIVERSAL GATES
All fundamental gates (NOT, AND, OR) can be realized by using either only NAND or only NOR
gate. Hence, any Boolean expression can be implemented using either only NAND gates or only NOR
gates. It is for this reason that NAND and NOR gates are called universal gates.
NAND as Universal Gate
1
NOT gate
2
AND gate
A
YA
A
B
Y  A B
A
3
OR gate
Y  A B
B
NOR as Universal Gate
1
NOT gate
2
OR gate
A
A
B
YA
A B
Y  A B
A
3
AND gate
B
Y  A B
 A B
Page 33 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
TTL and CMOS logic families
The types of transistors with which all integrated circuits are implemented are either MOSFETs or
BJTs. A circuit technology that uses MOSFETs is CMOS (Complementary MOS). Circuit technology
that uses BJTs is called TTL (transistor-transistor logic). All gates and other functions can be
implemented with either type of circuit technology.
CMOS
CMOS (complementary metal-oxide semiconductor) is a popular method of constructing digital
integrated circuits. Due to its low power consumption, good noise immunity, compatibility with
various voltage levels, and adaptability in circuit design, CMOS technology has become the preferred
choice for designing digital integrated circuits. It is used in a variety of applications, including
microprocessors.
MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used to construct CMOS logic
gates. MOSFETs have three terminals and are made up of a metal gate, an insulating layer (oxide),
and a semiconductor channel. NMOS (n-type MOSFET) and PMOS (p-type MOSFET) transistors
are used in CMOS.
In CMOS, the use of both NMOS and PMOS transistors in each logic gate is referred to as
"complementary." Low-voltage logic levels (0 or ground) are handled by NMOS transistors, whereas
high-voltage logic levels (1 or power supply voltage) are handled by PMOS transistors. This
arrangement makes optimal use of power and decreases static power usage.
Combinations of NMOS and PMOS transistors are used to construct CMOS logic gates. The CMOS
inverter, NAND gate, NOR gate, and XOR gate are the most common CMOS gates. These gates can
be connected together in order to create more complicated digital circuits
Page 34 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Note:
The n-channel MOS conducts when its gate-to-source voltage is positive.
The p-channel MOS conducts when its gate-to-source voltage is negative.
Either type of device is turned off if its gate-to-source voltage is zero.
CMOS NOR Gate
The following figure shows CMOS NOR gate with two inputs.
The operation of a CMOS NOR gate is as follows:
 When both inputs are LOW, Q1 and Q2 are ON and Q3 and Q4 are OFF. As a result, the output
is pulled HIGH through the ON resistance of Q1 and Q2 in series.
 When input A is LOW and input B is HIGH, Q1 and Q4 are ON, Q2 and Q3 are OFF. The
output is pulled LOW through the low ON resistance of Q 4 to ground.
 When input A is HIGH and input B is LOW, Q1 and Q4 are OFF, Q2 and Q3 are ON. The
output is pulled LOW through the low ON resistance of Q 3 to ground.
Page 35 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT

When both inputs are HIGH, Q1 and Q2 are OFF, Q3 and Q4 are ON. As a result, the output is
pulled LOW through the ON resistance of Q3 and Q4 in parallel to ground.
A
L
L
H
H
B
L
H
L
H
Q1
ON
ON
OFF
OFF
Q2
ON
OFF
ON
OFF
Q3
OFF
OFF
ON
ON
Q4
OFF
ON
OFF
ON
Y
H
L
L
L
TTL
TTL (transistor-transistor logic) is a widely used digital logic family in the design of integrated
circuits. It is well-known for its durability, fast performance, and compatibility with a wide range of
input and output devices.
The bipolar transistor is the active switching element used in all TTL circuits. A BJT has two
junctions, the base-emitter junction and the base-collector junction.
When the base is approximately 0.7V more positive than the emitter and when sufficient current is
provided into the base, the transistor turns ON and goes into saturation. In saturation, the transistor
ideally acts like a closed switch between the collector and the emitter.
When the base is less than 0.7V than the emitter, the transistor turns OFF and becomes an open switch
between the collector and the emitter.
In general, a HIGH on the base turns the transistor ON and makes it a closed switch. A LOW on the
base turns the transistor OFF and makes it an open switch.
In TTL, some BJTs have multiple emitters.
Page 36 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
TTL NAND gate
Here, A and B are inputs and Y is the output. Q1 is a multi-emitter transistor.
Diode equivalent of Q1 is shown below.
A LOW on either input A or input B forward biases the corresponding diodes (D 1 or D2 – base-emitter
junction) and reverse biases D3 (base-collector junction). There is current through R 1 and the baseemitter junction of Q1 to the LOW input. A LOW provides a path to ground for the current. There is
no current into the base of Q2, so it is OFF. Collector of Q2 is high, thus turning Q4 ON. A saturated
Q4 provides a low resistance path from VCC to the output. Hence there will be a HIGH on the output
for a LOW on the input. At the same time, the emitter of Q2 is at ground potential, keeping Q3 OFF.
If both inputs A and B are HIGH, the emitter–base junction of Q 1 is reverse biased, and the collector–
base junction is forward-biased. This condition permits current through R 1 and the base-collector
junction of Q1 into the base of Q2, thus driving Q2 into saturation. As a result, Q3 is turned ON by Q2,
and its collector voltage, which is the output, is near ground potential. Hence, there will be a LOW
output. At the same time, the collector of Q2 is at a sufficiently low voltage level to keep Q4 OFF.
Diode D ensures that Q4 will turn OFF when Q2 is ON.
Page 37 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Difference between CMOS and TTL
The following table highlights the major differences between CMOS and TTL:
Characteristics
Voltage Levels
Power Consumption
Technology
Noise Immunity
Fan-Out Capability
Speed
Power Supply
Applications
CMOS
Wide range of voltage levels
Low
MOSFET
High
High fan-out capability
Slow propagation delays
Typically operates at 5V or 3.3V
Battery-operated devices, highdensity ICs
TTL
Fixed voltage levels (typically 5V)
High
Bipolar Junction Transistor (BJT)
Low
Lower fan-out capability
Fast propagation delays
Typically operates at 5V
High-speed applications, memory
systems
Page 38 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
MODULE 2
Boolean Laws and theorems, Sum of Products method, Product of Sum method – K map
representation and simplification (up to four variables) - Pairs, Quads, Octets, Don’t care
conditions.
Combinational circuits: Adders -Full adder and half adder, Subtractors- half subtractor and full
subtractor, 4-bit parallel binary adder/subtractor, Carry Look ahead adders.
2
Boolean Algebra and Adders (9 hours)
2.1
Boolean Laws and theorems
1
2.2
Standard forms and canonical forms, Sum of Products method, Product of
2
Sums method
2.3
K-map representation and simplification (upto four variables) -Pairs, Quads,
2
Octets, Don’t care conditions. Realisation using universal gates
2.4
Adders - Full adder and half adder – Subtractors, half subtractor and full
2
subtractor
2.5
4-bit parallel binary adder/subtractor
1
2.6
Carry Look-ahead adders
1
BOOLEAN ALGEBRA
Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It uses only the binary
numbers i.e. 0 and 1. Elementary algebra deals with numerical operations whereas Boolean algebra
deals with logical operations.
LAWS OF BOOLEAN ALGEBRA
Commutative law of addition
A B  B  A
1
Commutative laws
Commutative law of multiplication A.B  B. A
Associative law of addition
A  ( B  C )  ( A  B)  C
2
Associative laws
A.( B.C )  ( A.B ).C
Associative law of multiplication
3
Distributive law
4
Law 1
A.( B  C )  A.B  A.C
Law 2
A  BC  ( A  B )( A  C )
A  BC  ( A  B )( A  C )
Proof:
( A  B )( A  C )  AA  AC  BA  BC  A  AC  AB  BC  A(1  C  B )  BC  A  BC
BASIC RULES OF BOLEAN ALGEBRA
A.0  0
1
A.1  A
2
A. A  A
3
4
A. A  0
5
6
7
8
A0  A
9
A A
A 1  1
A A  A
AND Laws
OR Laws
A A 1
Page 39 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
10
11
A  AB  A
A( A  B)  A
12
A  AB  A  B
10
Rule
A  A.B  A
Proof
A  A.B  A(1  B )  A
11
A( A  B )  A
A( A  B )  A. A  A.B  A  A.B  A(1  B )  A
12
A  AB  A  B
A  AB  ( A  AB )  AB  A  AB  AB  A  B ( A  A)  A  B
De Morgan’s Theorem
De Morgan’s theorems are used to solve the expressions of Boolean Algebra. It is a very powerful
tool used in digital design. According to the first theorem the complement of a sum equals the product
of complements, while according to the second theorem the complement of a product equals the sum
of complements.
De Morgan’s Theorem 1
A  B  A.B
De Morgan’s Theorem 2
A.B  A  B
Verification of De Morgan’s Theorem 1
A
B
A B
0
0
1
1
0
1
0
1
0
1
1
1
A B
1
0
0
0
A
1
1
0
0
B
1
0
1
0
A.B
1
0
0
0
A.B
1
1
1
0
A
1
1
0
0
B
1
0
1
0
A B
1
1
1
0
Hence A  B  A.B
Verification of De Morgan’s Theorem 2
A.B
A
B
0
0
1
1
0
1
0
1
0
0
0
1
Hence A.B  A  B
Prove that AB  AC  BC  AB  AC
Ans: AB  AC  BC 
 AB  AC  ( A  A) BC
 AB  AC  ABC  ABC
Page 40 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
 AB (1  C )  AC (1  B )  AB  AC
Reduce the expression f  AB  A  AB
Ans: f  AB  A  AB
 AB. A. AB
 AB. A. AB
 AB. AB
0
OR
f  AB  A  AB
 AB. A. AB
 AB. A.( A  B )
 AB ( A  B )
 AB A  ABB )
0
Reduce the expression f  A  B  AC  ( B  C ) D 
Ans: f  A  B  AC  ( B  C ) D 
 A  ABC  BBD  BCD
 A(1  BC )  BD  BCD
 A  BD (1  C )
 A  BD
Reduce the expression f  ( B  BC )( B  BC )( B  D )
Ans: f  ( B  BC )( B  BC )( B  D )
 B (1  C )( BB  BD  BBC  BCD )
 B ( B  BD  BCD )
 BB  BBD  BBCD
 B  BD
 B (1  D )
B
Reduce the expression f  A  C  D
Ans: f = ACD
Reduce the expression f  ( X  Y  Z )( X  Y  Z ) X
Page 41 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Prove that AB  AC  ABC ( AB  C )  1
Prove that AB  ABC  A( B  AB)  0
Prove that ABC  AB  BC  AB
Prove that RST ( R  S  T )  RST
BOOLEAN FUNCTIONS AND THEIR REPRESENTATIONS
A boolean function is defined by an algebraic expression consisting of binary variables, constants
such as 0 and 1, and the logic operation symbols. Whereas a variable in a boolean function is defined
as a variable or a symbol which is generally an alphabet that depicts the logical quantities such as 0
or 1.
For a given set of values of the binary variables concerned, the boolean function can hold a value of
0 or 1. For example, the boolean function A  BC is defined in terms of three binary variables (A, B,
C), where A, B, C can take either 0 or 1 only.
SUM OF PRODUCT (SOP)
Sum of product (SOP) form is a form in which the function is the sum of number of product terms.
Minterm: Minterm is a product term which contains all the variables of the function either in
complemented or uncomplemented form. A minterm assumes the value 1 only for one combination
of the variables. An n variable function can have 2n minterms.
C
Minterm
A
B
0
0
0
m  ABC
0
0
0
1
m1  ABC
0
1
0
m2  ABC
0
1
1
m3  ABC
1
0
0
m4  ABC
1
0
1
m5  ABC
1
1
0
m6  ABC
1
1
1
m7  ABC
Types of Sum of Product (SOP) Forms
There are few different forms of Sum of Product.
 Canonical (standard) SOP Form
 Non-Canonical SOP Form
 Minimal SOP Form
Page 42 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Canonical (standard) SOP Form
It is formed by ORing the minterms of the function for which the output is true (=1). In standard SOP
form, all the variables appear in each product term in the expression.
Canonical SOP expression is represented by summation sign ∑ and minterms in the braces for which
the output is true.
For example, a function truth table is given below.
C
f (A,B,C)
A
B
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
For this function the canonical SOP expression is
f ( A, B, C )   (m1 , m2 , m3 , m5 ) which means that the function is true for the min terms {1, 2, 3, 5}.
By expanding the summation we get.
f ( A, B, C )  m1  m2  m3  m5
Now putting min terms in the expression
f ( A, B, C )  ABC  ABC  ABC  ABC
Another way of representing the function is
f ( A, B, C )   m(1, 2, 3,5)
Canonical form contains all inputs either complemented or non-complemented in its product terms.
Non-Canonical SOP Form
As the name suggests, this form is the non-standardized form of SOP expressions. The product terms
are not the min terms but they are simplified. Let’s take the above function in canonical form as an
example.
f  ABC  ABC  ABC  ABC
 ABC  AB (C  C )  ABC
 ABC  AB  ABC
This expression is still in Sum of Product form but it is non-canonical or non-standardized form.
Minimal SOP Form
This form is the most simplified SOP expression of a function. It is also a form of non-canonical
form. Minimal SOP form can be made using Boolean algebraic theorems but it is very easily made
using Karnaugh map (K-map).
Minimal SOP form is preferred because it uses the minimum number of gates and input lines. it is
commercially beneficial because of its compact size, fast speed, and low fabrication cost.
Let’s take an example of the function given above in canonical form.
Page 43 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
f
0
1
1
1
0
1
0
0
Canonical SOP can be converted to minimal SOP. It can be converted using Karnaugh map or
Boolean algebraic theorems. The K-map method is very easy and its example has been done above
in the minimal SOP form.
K-map of above function is given below.
According to the K-map, the output expression will be
F  BC  AB
This is the most simplified & optimized expression for the said function. This expression requires
only two 2-input AND gates & one 2-input OR gate. However, the canonical form needs four 3-input
AND gates & one 4-input OR gate, which is relatively more costly than minimal form
implementation.
Conversion from Minimal SOP/non-canonical SOP to Canonical SOP Form
Canonical form has minterms and minterms consists of all inputs either complemented or noncomplemented. So we will multiply every term of minimal SOP with the sum of missing input’s
complemented and non-complemented form. Example of conversion for the above function in
minimal SOP form is given below.
F  AB  BC
 AB (C  C )  BC ( A  A)
 ABC  ABC  ABC  ABC
Now, this expression is in canonical form.
PRODUCT OF SUM (POS)
POS form consists of two or more OR terms (sums) that are ANDed together. Each OR term contains
one or more variables in complemented or uncomplemented form. Examples are
1. f  ( A  B  C ).( A  B  C ).( A  B  C ).( A  B  C )
2. f  ( B  C ).( A  B ).( A  B  C )
Page 44 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Maxterm
Maxterm is a sum term which contains all the variables of the function either in complemented or
uncomplemented form.
Maxterm means the term or expression that is true for a maximum number of input combinations or
that is false for only one combination of inputs.
In maxterm, each variable whose value is assigned to 1 is represented in the complemented form. The
variable whose value is assigned to 0 is represented in the uncomplimented form. We can represent
maxterm with ‘M’.
Max terms for 3 input variables are given below.
C
Minterm
A
B
0
0
0
M0  A  B  C
0
0
1
M1  A  B  C
0
1
0
M2  A B  C
0
1
1
M3  A  B  C
1
0
0
M4  A  B  C
1
0
1
M5  A  B  C
1
1
0
M6  A  B  C
1
1
1
M7  A  B  C
3 inputs have 8 different combinations so it will have 8 maxterms.
In maxterm, each input is complemented because Maxterm gives ‘0’ only when the mentioned
combination is applied and Maxterm is complement of minterm.
M 3  m3  ABC  A  B  C
Types of Product Of Sum Forms
There are different types of Product of Sum forms.
 Canonical POS Form
 Non – Canonical Form
 Minimal POS Form
Canonical POS Form
In canonical POS form, we have all the variables present in a complimented or un-complimented
form in each maxterm.
Canonical POS expression is represented by ∏ and maxterms for which output is false in brackets
as shown in the example given below.
C
f
A
B
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
Page 45 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
f ( A, B, C )   ( M 0 , M 4 , M 6 , M 7 )
f ( A, B, C )  M 0 .M 4 .M 6 .M 7
f ( A, B, C )  M (0, 4, 6, 7)
f  ( A  B  C ).( A  B  C ).( A  B  C ).( A  B  C )
Non – Canonical Form
The product of sum expression that is not in standard form is called non-canonical form.
Let’s take the above-given function as an example.
f  ( A  B  C ).( A  B  C ).( A  B  C ).( A  B  C )
 ( B  C ).( A  A).( A  B  C ).( A  B  C )
 ( B  C ).( A  B  C ).( A  B  C )
The expression achieved is still in Product of Sum form but it is non-canonical form.
Minimal POS Form
This is the most simplified and optimized form of a POS expression which is non-canonical. Minimal
Product of Sum form can be achieved using Boolean algebraic theorems or using Karnaugh map.
Minimal POS form uses less number of inputs and logic gates during its implementation, that’s why
they are being preferred over canonical form for their compact, fast and low-cost implementation.
Let’s take the above-given function as example.
K-map of the function
Minimal expression using K-map
f ( A, B, C )  ( B  C ).( A  B )
The achieved expression is the minimal product of sum form. It is still Product of Sum expression.
But it needs only 2 inputs two OR gates and a single 2 input AND gate. However, the canonical
form needs 4 OR gates of 3 inputs and 1 AND gate of 4 inputs.
Conversion from Minimal POS to Canonical form POS
As we know the canonical form of POS has max terms and max terms contains every input either
complemented or non-complemented. So we will add every sum term with the product of
complemented and non-complemented missing input. Example of its conversion is given below.
Minimal POS form
f ( A, B, C )  ( B  C ).( A  B )
Page 46 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
(A̅+B̅) term is missing C input so we will add (CC̅) with it. (B+C) term is missing A input so we will
add (AA̅) with it.
f ( A, B, C )  ( AA  B  C ).( A  B  CC )
 ( A  B  C ).( A  B  C ).( A  B  C ).( A  B  C ) (Note: A  BC  ( A  B )( A  C ) )
This expression is now in canonical form.
Conversion From Canonical POS to SOP
The product of Sum expression can be converted into Sum of Product form only if the expression is
in canonical form. Canonical POS and canonical SOP are inter-convertible i.e. they can be converted
into one another. Example of POS to SOP conversion is given below.
POS canonical form
f  ( A  B  C ).( A  B  C ).( A  B  C ).( A  B  C )
In canonical form each sum term is a maxterm so it can also be written as:
f   (M 0 , M 4 , M 6 , M 7 )
The remaining combinations of inputs are minterms of the function for which its output is true. To
convert it into SOP expression first we will change the symbol to summation (∑) and use the
remaining minterm.
f   (m1 , m2 , m3 , m5 )
Now we will expand the summation sign to form canonical SOP expression.
f  ABC  ABC  ABC  ABC
Min terms are complement of maxterms for the same combination of inputs.
Expand f ( A, B )  A  B to minterms and maxterms.
Ans: -
f  A  B  A( B  B )  B( A  A)
 AB  AB  AB  AB
 AB  AB  AB
 01  00  10
 m1  m0  m2
  m(0,1, 2)
The minterm m3 is missing in the SOP form. Hence, maxterm will be M3 in POS form.
f  M3
Expand f  A( A  B ) B to minterms and maxterms.
Ans: f  A( A  B ) B  ( A  BB )( A  B )( AA  B )
 ( A  B )( A  B)( A  B)( A  B)( A  B )
 ( A  B )( A  B )( A  B )
 00  01 10
Page 47 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
 M 0 M 1M 2
  M (0,1, 2)
Minterm in SOP form is
f  m3
OR
f  A( A  B ) B  AAB  ABB
 AB
 11
 m3
Design a logic circuit that has three inputs, A, B, and C, and whose output will be HIGH only when
a majority of the inputs are HIGH.
Ans: C
f
A
B
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
f  ABC  ABC  ABC  ABC
 ABC  ABC  ABC  ABC  ABC  ABC
 BC ( A  A)  AC ( B  B )  AB (C  C )
 AB  BC  AC
f  AB  BC  AC
KARNAUGH MAP
Karnaugh Maps offer a graphical method of reducing a digital circuit to its minimum number of gates.
The map is a simple table containing 1s and 0s that can express a truth table or complex boolean
expression describing the operation of a digital circuit. The map is then used to work out the minimum
number of gates needed, by graphical means rather than by algebra.
Page 48 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The shape and size of the map is dependent on the number of binary inputs in the circuit to be
analysed.
2 input circuits with inputs A and B require maps with 22 = 4 cells
3 input circuits with inputs A B and C require maps with 23 = 8 cells
4 input circuits with inputs A B C and D require maps with 24 = 16 cells
The Karnaugh map can be populated with data from either a truth table or a Boolean equation.
As an example, Table shows the truth table for the 3 input together with the Boolean expressions
derived from each input combination that results in a logic 1 output.
C
F
F
A
B
0
0
0
0
0
0
1
0
0
1
0
1
ABC
0
1
1
1
ABC
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
1
ABC
ABC
ABC
Boolean equation is
F  ABC  ABC  ABC  ABC  ABC
All the truth table rows that produced a logic 1 have now been entered into the map and those lines
that produced a logic 0 can be ignored, so the remaining three cells are left blank.
Circuit simplification in any Karnaugh map is achieved by combining the cells containing 1 to make
groups of cells. In grouping the cells it is necessary to follow six rules.
Page 49 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Karnaugh Map Rules
1. Groups should contain as many ‘1’ cells (i.e. cells containing a logic 1) as possible and no blank
cells.
2. Groups can only contain 1, 2, 4, 8, 16 or 32... etc. cells (powers of 2).
3. A ‘1’ cell can only be grouped with adjacent ‘1’ cells that are immediately above, below, left or
right of that cell; no diagonal grouping.
4. Groups of ‘1’ cells can overlap. This helps make smaller groups as large as possible, which is an
advantage in finding the simplest solution.
5. The top/bottom and left/right edges of the map are considered to be continuous (as shown in figure
below), so larger groups can be made by grouping cells across the top and bottom or left and right
edges of the map.
6. There should be as few groups as possible.
Example:
A
0
0
0
B
0
0
1
C
0
1
0
F
0
0
1
ABC
0
1
1
1
ABC
F
Page 50 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
0
0
0
1
0
1
1
1
0
1
ABC
ABC
ABC
1
1
1
1
Using the Karnaugh map rules on the 3-input map created from above table, there are just 2 possible
groups, as shown in figure below.
Step 1
Taking the (blue) group of 4 first, notice that it spans two rows vertically, and so contains rows A=0
and A=1, therefore A changes within the group so cannot appear in the expression.
The blue group also spans two columns and so contains BC=11 and BC=10. Here, C = both 1 and 0,
but B=1 in both columns.
Therefore, the only input that does not change in the blue group is B, so the Boolean expression for
the blue group is simply B.
Step 2
Looking at the (green) group of 2, A does not change but BC changes from 01 to 11. This indicates
that although B changes, C does not. Hence there are two non-changing inputs in this group - A and
C.
Putting the results of the simplification together by ‘ANDing’ any non-changing inputs within a single
group, and ‘ORing’ the different groups, produces the simplified Boolean equation for the whole
circuit:
F  B  A.C
This result agrees with the simplification using Boolean algebra as shown below.
F  ABC  ABC  ABC  ABC  ABC
 AB (C  C )  ABC  AB (C  C )
 AB  ABC  AB
 ( A  A) B  ABC
 B  ABC
 B  AC
Page 51 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
f 1
f C
f D
f B
f  BD
f  AC
f  BC
f  BD
f  AD
f  BD
f  ABD
f  BC D
f  BC D
f  AC D  AC D
f  ABCD
f  ABC
f  ABD
f B
Page 52 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Pairs, Quads and Octets
Pair
After constructing K – map, the pairs quads and octets of adjacent 1’s in the K – map are made for
getting the minimal Boolean expression. A pair eliminates one variable with its complement; a quad
eliminates two variables with their complements and an octet eliminates three variables with their
complements.
In K-map, two adjacent 1s (vertically or horizontally) are encircled. The diagonally adjacent 1s are
never encircled. The encircled 1s forms the pairs.
Consider the first pair, the two 1s contained in the pair has the binary numbers 000 and 001 for the
variables ABC. In the binary numbers, the variable A changes from 0 to 1 (complemented to uncomplemented), so this variable is dropped with its complement. The binary number left is 00 having
the term (in SOP form) as BC . Similarly, consider the second pair, The two 1s contained in this pair
have the binary numbers 011 & 010 for variables ABC. The variable C changes from 1 to 0 so this
variable is dropped with its complement. The remaining (common) binary number 01 for variables
AB will have the term (in SOP) as AB .
Using Boolean algebra in the first pair, ABC  ABC  ( A  A) BC  BC .
Using Boolean algebra in the second pair, ABC  ABC  AB (C  C )  AB .
Quads
In the K –map if four 1s are adjacent in a row or column or in the form of a square, then these 1s are
encircled called as quads.
The variables which changes from complemented to uncomplemented or vice versa are dropped and
the variables which are common in all the four 1s of a quad are considered to write term in SOP form.
In the K – map of three variables, the encircled group of 1s shows the quad whose four elements
represent the binary numbers 000, 001, 011 & 010 for variables ABC. In the binary numbers, 0 for A
is common for all the four binary numbers; so A (in SOP form) is the term for this quad. The variables
BC are dropped as each of the variable changes 0 to 1 or 1 to 0.
Using Boolean algebra, ABC  ABC  ABC  ABC  AB  AB  A .
Octets
The eight adjacent 1s are encircled in a K – map known as octet.
Page 53 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
An octet eliminates three variables with their complements and gives a term of one variable in a K –
map of four variables. In the binary numbers, 1 for D is common for all the four binary numbers; so
D (in SOP form) is the term for this octet.
The main advantage of using a Karnaugh map for circuit simplification is that the Karnaugh method
uses fewer rules, and these rules can be applied systematically rather than intuitively as with Boolean
algebra. Therefore with a little practice the Karnaugh system should produce more reliable
minimisation. Although Karnaugh mapping may have only slight advantages over Boolean algebra
in simple circuits, the advantages become more apparent when minimising more complex circuits.
Don’t Care condition:
There may arise a case when for a given combination of input we may not have a specified output or
the input combination may be invalid. The combinations for which we don't have any output
expression specified are called don't care combination.
For Example, in Excess-3 code, binary input states 0000, 0001, 0010, 1101, 1110 and 1111 are
unspecified and are also represented by don't care.
These don't care conditions in the K-Map are denoted by an x (cross) symbol.
General rules to be followed while minimizing the expressions using K-Map which include don't
care conditions are as follows,
1. After forming the K-Map, fill 1's at the specified positions corresponding to the given
minterms. Fill x at the positions where don't care combinations are present.
2. Now, Encircle the groups in the K-Map. One thing to be kept in mind is, now we can
treat Don't Care conditions (x) as 1s if these help in forming the largest groups. No such
group can be encircled whose all the elements are x.
3. If still there are 1s left which doesn't get encircled in any of the groups, then these
isolated 1s are encircled individually.
4. Now, recheck all the encircled groups, and remove any redundancy if present.
5. Write the Boolean expression for each encircled group.
6. The final minimal expression can be obtained by ORing each Boolean expressions that were
obtained from each group.
While designing K-Map using SOP form, don't care conditions (x) are considered as 1, if it helps
form the largest group, otherwise it is considered as 0 and are left during encircling. On the contrary,
while designing a K-Map using POS form, don't care conditions (x) are considered as a 0, if it helps
form the largest group, otherwise it is considered as 1 and are left during encircling.
Page 54 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
We will fill 1s at the appropriate minterm positions and also the don't care positions will be filled
with (x).
F  ACD  BC  BD
Significance of “Don’t Care” Conditions:
Don’t Care conditions has the following significance in designing of the digital circuits:
1. Simplification of the output: These conditions denotes inputs that are invalid for a given
digital circuit. Thus, they can used to further simplify the boolean output expression of a
digital circuit.
2. Reduction in number of gates required: Simplification of the expression reduces the
number of gates to be used for implementing the given expression. Therefore, don’t cares
make the digital circuit design more economical
3. Reduced Power Consumption: While grouping the terms along with don’t cares reduces
switching of the states. This decreases the memory space that is required to represent a given
digital circuit which in turn results in less power consumption.
4. Represent Invalid States in Code Converters: These are used in code converters. For
example- In design of 4-bit BCD-to-XS-3 code converter, the input combinations 1010, 1011,
1100, 1101, 1110, and 1111 are don’t cares.
Determine the minimum expression for the following K map.
Ans:-
Page 55 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
f  AC  BC  AC D
Determine the minimum expression for the following K map.
Ans:-
f  BD  BC  AD
Determine the minimum expression for the following K map.
Ans:-
f  C  AB
Reduce the expression using K map.
f   m(8,9)   d (10,11,12,13,14,15)
f A
Reduce the expression using K map.
Page 56 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
f   m(2,3, 4,5)   d (10,11,12,13,14,15)
f  BC  BC  B  C
Reduce the expression using K map.
f   m(1, 2,5, 6,9)   d (10,11,12,13,14,15)
f  CD  C D  C  D
PRODUCT OF SUM (POS) FORMS
Plot the expression f  ( A  B )( A  B )( A  B ) on the K-map
f   M (0, 2,3)
Reduce the expression f  ( A  B )( A  B)( A  B ) using K-map
f  AB
Reduce the expression f   M (2,8, 9,10,11,12,14) using K-map
Page 57 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
f  ( B  C  D)( A  B )( A  D )
Reduce the expression
f   M (0,1, 2, 3, 4, 7) using K-map and implement it in AOI
(AND/OR/INVERT) logic as well as in NOR logic.
f  A( B  C )( B  C )
Implementation using AOI logic is
Implementation using NOR gates
f  A( B  C )( B  C )  A  B  C  B  C
Page 58 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Combinational circuits: Adders -Full adder and half adder, Subtractors- half subtractor and full
subtractor, 4-bit parallel binary adder/subtractor, Carry Look ahead adders.
Types of Logic Circuits: There are two types of Digital circuits depending on their output and
memory used:
(i) Combinational circuit, and
(ii) Sequential circuit
A combinational circuit consists of logic gates whose outputs at any time are determined from only
the present combination of inputs and they have no memory. Some examples are half adder, full
adder, half subtractor and full subtractor.
A sequential circuit consists of logic gates whose outputs at any time are determined from both the
present combination of inputs and previous output. That means sequential circuits use memory
elements to store the value of previous output. Some examples are counters and shift registers
Combinational Circuit
Its output is determined by the present values of
its input only.
It does not have a memory
Feedback is not present
Its operation can be described by a truth table.
Sequential Circuit
Its output is determined by the present values of
the input as well as the past values of the output.
It has a memory
It has a feedback path from output to input.
Its operation can be described by truth table and
timing diagram.
It does not have a clock signal.
It may or may not have a clock signal but most
sequential circuits have a clock signal.
Faster operation
Slower operation
Examples are adder, subtractor, multiplexer, Examples are counters, shift registers
decoder, comparator.
HALF ADDER
A half adder is one which adds two binary digits simultaneously. It also falls in the category of
combinational circuits. Let A and B are the two binary digits which are to be added together and are
the two valued input variables. It will give two outputs as Sum and Carry.
Page 59 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
Boolean expression for the SUM output is S  AB  AB  A  B
Boolean expression for the CARRY output is C  AB
The expression for sum S is nothing but the exclusive OR function of the two input digits A and B.
Realisation of half-adder using NAND gates:
S  AB  AB  AB  AA  AB  BB
 A( A  B )  B ( A  B )
 A. AB  B. AB
 A. AB.B. AB
C  AB  AB
A. AB
AB
B. AB
OR
S  AB  AB
S  AB  AB
S  AB. AB
C  AB  AB
Page 60 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
AB
AB
AB
Realisation of half-adder using NOR gates:
S  AB  AB  AB  AA  AB  BB
 A( A  B )  B ( A  B )
 ( A  B )( A  B )
 A B  A B
C  AB  AB  A  B
A
A B
A B
B
OR
S  AB  AB
S  AB  AB
S  AB. AB  ( A  B).( A  B)  A  B  A  B
C  AB  AB  A  B
Page 61 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
A B
A B
A B
FULL ADDER
Full adder takes three inputs namely A, B, and C in. Where, A and B are the two binary digits, and
Cin is the carry bit from the previous stage of binary addition. The sum output of the full adder is
obtained by XORing the bits A, B, and C in. While the carry output bit (Cout) is obtained using AND
and OR operations.
Inputs
Outputs
A
B
Cin
S
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
From the truth table, it is clear that the sum output of the full adder is equal to 1 when only 1 input is
equal to 1 or when all the inputs are equal to 1. While the carry output has a carry of 1 if two or three
inputs are equal to 1.
S  ABCin  ABC in  ABC in  ABCin
 ( AB  AB)C in  ( AB  AB)Cin
 ( A  B )C in  ( A  B )Cin
(Note: A  B  AB  AB  AB. AB  ( A  B )( A  B)  AB  AB )
Page 62 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
 A  B  Cin
Cout  AB  ACin  BCin
The sum (S) of the full-adder is the XOR of A, B, and C in.
OR
Cout  AB  ABCin  ABCin  AB  ( A  B )Cin
Implementation of full adder using half adders
Cout  ABCin  ABC in  ABCin  ABCin
 ( AB  AB)Cin  AB (C in  Cin )
 ( A  B )Cin  AB
A B
AB
S  A  B  Cin
Cout  ( A  B )Cin  AB
The following are the important advantages of full adder over half adder
Page 63 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Full adder provides facility to add the carry from the previous stage.
 The power consumed by the full adder is relatively less as compared to half adder.
 Full adder can be easily converted into a half subtractor just by adding a NOT gate in the
circuit.
 Full adder produces higher output than half adder.
 Full adder is one of the essential part of critic digital circuits like multiplexers.
 Full adder performs operation at higher speed.
HALF-SUBRACTOR
A half-subtractor is a combinational circuit that can be used to subtract one bit from another and
produces the difference. It also has an output to specify if a 1 has been borrowed.
A half-subtractor is a combinational circuit with two inputs A and B and two outputs d (difference)
and b (borrow).
The truth table of a half-subtractor is shown below.
A
B
d
b
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0

d  AB  AB  A  B
b  AB
Realisation of half-subtractor using NAND gates:
d  AB  AB  AB  AA  AB  BB
 A( A  B )  B ( A  B )
 A. AB  B. AB
 A. AB.B. AB
b  AB  B ( A  B )  B ( AB)  B( AB )
Page 64 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
A. AB
AB
B. AB
Realisation of half-subtractor using NOR gates:
d  AB  AB  AB  AA  AB  BB
 A( A  B )  B ( A  B )
 ( A  B )( A  B )
 A B  A B
b  AB  A( A  B)  A( A  B )  A  A  B
A
A B
A B
B
FULL SUBTRACTOR
The half-subtractor can be used only for LSB subtraction. If there is a borrow during the subtraction
of the LSBs, it affects the subtraction in the next higher column. Such a subtraction is performed by
a full-subtractor.
Full subtractor takes three inputs namely A, B, and bin (borrow-in).
Inputs
Outputs
A
B
bin
d
bout
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
Page 65 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
d  ABbin  ABbin  ABb in  ABbin
 ( AB  AB )bin  ( AB  AB)bin
 ( A  B )bin  ( A  B )bin
(Note: A  B  AB  AB  AB. AB  ( A  B )( A  B)  AB  AB )
 A  B  bin
bout  AB  Abin  Bbin
OR
bout  ABbin  ABbin  ABbin  ABbin  ( AB  AB )bin  AB (bin  bin )
bout  A  B.bin  AB
Page 66 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
4-BIT BINARY PARALLEL ADDER / SUBTRACTOR
The operations of both addition and subtraction can be performed by a one common binary adder.
Subtraction A – B can be done by taking the 2’s complement of B and adding it to A. The 2’s
complement can be obtained by taking the 1’s complement and adding 1 to the least significant bit.
The 1’s complement can be implemented with inverters and a 1 can be added to the sum through the
input carry.
A 4-bit adder-subtracter circuit is shown below. The addition and subtraction operations can be
combined into one circuit with one common binary adder by including an exclusive-OR gate with
each full adder.
The mode input M control the operation. When M = 0, the circuit is an adder and when M = 1, the
circuit becomes a subtractor. Each X-OR gate received input M and one of the inputs of B. When M
= 0, we have B  0  B . The full adder receive the value of B, the input carry is 0, and the circuit
performs A plus B. When M = 1, we have B  1  B and Cin = 1. The inputs are all complemented
and a 1 is added through the input carry. The circuit performs the operation A plus the 2’s complement
of B. Hence subtraction operation A – B is performed.
4-Bit Carry Look-ahead Adder
CLA adder is faster in terms of operational speed.
For parallel adder, it takes propagation delay to have output.
In parallel adders, carry output of each full adder is given as a carry input to the next higher state.
Hence, it is not possible to produce carry and sum outputs of any state unless a carry input is available
for that state. So, for computation to occur, the circuit has to wait until the carry bit propagated to all
states. This induces carry propagation delay in the circuit.
The propagation delay of the adder is calculated as “the propagation delay of each gate times the
number of stages in the circuit”. For the computation of a large number of bits, more stages have to
be added, which makes the delay much worse. Hence, to solve this situation, Carry Look-ahead Adder
was introduced.
The object of carry lookahead is to provide all of the carry bits for an adder at the same time instead
of waiting for them to ripple through the adders.
Truth table for a full-adder is
Page 67 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
A1
0
0
0
0
1
1
1
1
Full Adder 1
B1
C0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
C1
0
0
0
1
0
1
1
1
C1  A1 B1C0  A1 B1C0  A1B1 C0  A1 B1C0
 ( A1 B1  A1 B1 )C0  A1 B1 (C0  C0 )
 ( A1  B1 )C0  A1 B1
In general, for any full adder,
Ci  Ai Bi  ( Ai  Bi )Ci 1
Gi  Ai Bi = Carry generated and
Pi  Ai  Bi = Carry propagated
Hence, output carry of a full-adder can be expressed in terms of both the generated carry G i and
propagated carry Pi.
Ci  Gi  PC
i i 1
C0  G0  P0Cin
C1  G1  PC
1 0  G1  P1 (G0  P0Cin )  G1  PG
1 0  P1 P0 Cin
C2  G2  P2G1  P2 PG
1 0  P2 P1 P0 Cin
C3  G3  P3G2  P3 P2G1  P3 P2 PG
1 0  P3 P2 P1 P0Cin
Cin is the only carry that must be known for all of these calculations.
Each full-adder, calculates Pi and Gi, and sends them to the Carry Look Ahead Unit. This will take
only one gate delay. The CLA Unit simultaneously calculates the C i for all of its adders. This will
take two gate delays. The carry C3 for the next group of adder units is also calculated. All the fulladders calculate the sum simultaneously.
For full adder, sum S is given by
Si  Ai  Bi  Ci 1  Pi  Ci 1
S 0  P0  Cin
S1  P1  C0
S 2  P2  C1
S3  P3  C0
Page 68 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Page 69 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
MODULE 3
Comparators, Parity generators and checkers, Encoders, Decoders, BCD to seven segment decoder,
Code converters, Multiplexers, Demultiplexers, Architecture of Arithmetic Logic Units (Block
schematic only).
3
Combinational Logic Circuits (9 hours)
3.1
2- and 4-bit magnitude comparator.
2
3.2
Parity generators and checkers
1
3.3
Encoder, Decoder - BCD to decimal and BCD to seven segment decoders
2
3.4
Realisation of Code converters
1
3.5
Multiplexers and implementation of functions, Demultiplexers
2
3.6
Architecture of Arithmetic Logic Units (Block schematic only)
1
MAGNITUDE COMPARATOR
A magnitude comparator is a combinational circuit that compares two binary numbers in order to
find out whether one binary number is equal, less than, or greater than the other binary number. We
logically design a circuit with 2 inputs and three output terminals, one for A > B condition, one for A
= B condition, and one for A < B condition.
The circuit works by comparing the bits of the two numbers starting from the most significant bit
(MSB) and moving toward the least significant bit (LSB). At each bit position, the two corresponding
bits of the numbers are compared. If the bit in the first number is greater than the corresponding bit
in the second number, the A>B output is set to 1, and the circuit immediately determines that the
first number is greater than the second. Similarly, if the bit in the second number is greater than the
corresponding bit in the first number, the A<B output is set to 1, and the circuit immediately
determines that the first number is less than the second.
If the two corresponding bits are equal, the circuit moves to the next bit position and compares the
next pair of bits. This process continues until all the bits have been compared. If at any point in the
comparison, the circuit determines that the first number is greater or less than the second number, the
comparison is terminated, and the appropriate output is generated.
If all the bits are equal, the circuit generates an A=B output, indicating that the two numbers are
equal.
1-Bit Magnitude Comparator
A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs
each for two single-bit numbers and three outputs to generate less than, equal to, and greater than
between two binary numbers.
The truth table for a 1-bit comparator is given below.
A
B
A<B
A=B
A>B
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
Page 70 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
From the above truth table logical expressions for each output can be expressed as follows.
A>B: G  AB
A<B: L  AB
A=B: E  AB  AB
Note:
For X-NOR gate,
output is 1 when both
input bits are equal.
A
B
Y  A B  A B
A
B
Y
0
0
1
1
0
1
0
1
1
0
0
1
2-Bit Magnitude Comparator
A comparator used to compare two binary numbers each of two bits is called a 2-bit magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and greater
than between two binary numbers.
The truth table for a 2-bit comparator is given below.
Inputs
Outputs
A1
A0
B1
B0 A<B A=B A>B
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
Page 71 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
1
0
From the above truth table, K-map for each output can be drawn as follows.
Truth Table of Output A>B
G  A1 B1  A0 B1 B 0  A1 A0 B 0
Truth Table of Output A=B
E  A1 A0 B1 B 0  A1 A0 B1 B0  A1 A0 B1 B0  A1 A0 B1 B 0
 A1 B1 ( A0 B 0  A0 B0 )  A1 B1 ( A0 B0  A0 B 0 )
 ( A0 B 0  A0 B0 )( A1 B1  A1 B1 )
 ( A0  B0 )( A1  B1 )
Truth Table of Output A<B
L  A1B1  A0 B1 B0  A1 A0 B0
Page 72 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
By using these Boolean expressions, we can implement a logic circuit for this comparator as given
below.
PARITY GENERATOR AND CHECKER
Majority of modern communication is digital in nature i.e. it is a combination of 1’s and 0’s. The
digital data is transmitted either through wires (in case of wired communication) or wireless. Even in
an advanced mode of communication, there will be errors while transmitting data (due to noise).
The simplest of errors is corruption of a bit i.e., a 1 may be transmitted as a 0 or vice-versa. To confirm
whether the received data is the intended data or not, we should be able to detect errors at the receiver.
PARITY BIT
The parity generating technique is one of the most widely used error detection techniques for the data
transmission. In digital systems, when binary data is transmitted and processed, data may be subjected
to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.
Hence, a Parity Bit is added to the word containing data in order to make number of 1s either even or
odd. The message containing the data bits along with parity bit is transmitted from transmitter to the
receiver.
At the receiving end, the number of 1s in the message is counted and if it doesn’t match with the
transmitted one, it means there is an error in the data. Thus, the Parity Bit it is used to detect errors,
during the transmission of binary data.
A Parity Generator is a combinational logic circuit that generates the parity bit in the transmitter. On
the other hand, a circuit that checks the parity in the receiver is called Parity Checker. A combined
circuit or device of parity generators and parity checkers are commonly used in digital systems to
detect the single bit errors in the transmitted data.
Page 73 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Even Parity and Odd Parity
The sum of the data bits and parity bits can be even or odd. In even parity, the added parity bit will
make the total number of 1s an even number, whereas in odd parity, the added parity bit will make
the total number of 1s an odd number.
The basic principle involved in the implementation of parity circuits is that sum of odd number of 1s
is always 1 and sum of even number of 1s is always 0. Such error detecting and correction can be
implemented by using X-OR gates (since X-OR gate produce zero output when there are even number
of inputs).
Parity Generator
It is combinational circuit that accepts an n-1 bit data and generates the additional bit that is to be
transmitted with the bit stream. This additional or extra bit is called as a Parity Bit.
In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream and
the parity bit is ‘1’ if there are odd number of 1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and the
parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us discuss both even and odd
parity generators.
Even Parity Generator
Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three inputs A,
B and C are applied to the circuit and output bit is the parity bit P. The total number of 1s must be
even, to generate the even parity bit P.
The figure below shows the truth table of even parity generator in which 1 is placed as parity bit in
order to make all 1s as even when the number of 1s in the truth table is odd.
3-bit message
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
C
0
1
0
1
0
1
0
1
Even parity
bit (P)
0
1
1
0
1
0
0
1
The K-map simplification for 3-bit message even parity generator is
P  ABC  ABC  ABC  ABC
 A( BC  BC )  A( BC  BC )
Page 74 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
 A( B  C )  A( B  C )
 A BC
The above expression can be implemented by using two X-OR gates. The 3-bit message along with
the parity generated by this circuit which is transmitted to the receiving end where parity checker
circuit checks whether any error is present or not.
A B
A B C
Odd Parity Generator
Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three inputs are A,
B and C and P is the output parity bit. The total number of bits must be odd in order to generate the
odd parity bit.
In the given truth table below, 1 is placed in the parity bit in order to make the total number of bits
odd when the total number of 1s in the truth table is even.
3-bit message
Odd parity
bit (P)
C
A
B
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
The truth table of the odd parity generator can be simplified by using K-map as
P  ABC  ABC  ABC  ABC
 A( BC  BC )  A( BC  BC )
 A( B  C )  A( B  C )
 A B C
The above Boolean expression can be implemented by using one X-OR gate and one X-NOR gate in
order to design a 3-bit odd parity generator.
Page 75 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The logic circuit of this generator is shown in below figure, in which two inputs are applied at one XOR gate, and this X-OR output and third input is applied to the X-NOR gate, to produce the odd
parity bit. It is also possible to design this circuit by using two X-OR gates and one NOT gate.
A B C
BC
Parity Check
It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even
parity checker or odd parity checker depending on the type of parity generated at the transmission
end. When this circuit is used as even parity checker, the number of input bits must always be even.
Even Parity Checker
Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit, which checks the possibility of error on
the data. Since the data is transmitted with even parity, four bits received at circuit must have an even
number of 1s.
If any error occurs, the received message consists of odd number of 1s. The output of the parity
checker is denoted by PEC (Parity Error Check).
The below table shows the truth table for the Even Parity Checker in which PEC = 1 if the error
occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if the
4-bit message has even number of 1s.
4-bit received message
Parity Error
Check Cp
A
B
C
P
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
The above truth table can be simplified using K-map as shown below.
Page 76 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
P  ABCP  ABC P  ABC P  ABCP  ABCP  ABC P  ABC P  ABCP
 AB (CP  C P )  AB (C P  CP )  AB (CP  C P )  AB(C P  CP)
 ( AB  AB )(CP  C P )  ( AB  AB )(C P  CP )
 ( A  B )(C  P )  ( A  B )(C  P )
 ( A  B )  (C  P )
The above logic expression for the even parity checker can be implemented by using three X-OR
gates as shown in figure. If the received message consists of five bits, then one more X-OR gate is
required for the even parity checking.
A B
( A  B )  (C  P )
CP
Odd Parity Checker
Consider that a three bit message along with odd parity bit is transmitted at the transmitting end. Odd
parity checker circuit receives these 4 bits and checks whether any error are present in the data.
If the total number of 1s in the data is odd, then it indicates no error, whereas if the total number of
1s is even then it indicates the error since the data is transmitted with odd parity at transmitting end.
The below figure shows the truth table for odd parity generator where PEC =1 if the 4-bit message
received consists of even number of 1s (hence the error occurred) and PEC= 0 if the message contains
odd number of 1s (that means no error).
4-bit received message
A
B
C
P
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Parity Error
Check Cp
1
0
0
1
0
1
1
0
Page 77 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
The above truth table can be simplified using K-map as shown below.
P  ABC P  ABCP  ABCP  ABC P  ABC P  ABCP  ABCP  ABC P
 AB (C P  CP )  AB (CP  C P )  AB (C P  CP )  AB (CP  C P)
 ( AB  AB )(C P  CP )  ( AB  AB )(CP  C P )
 ( A  B )(C  P )  ( A  B )(C  P )
 ( A  B )  (C  P )
A B
( A  B )  (C  P )
CP
ENCODERS & DECODERS
Binary code of N digits can be used to store 2N distinct elements of coded information. This is what
encoders and decoders are used for. Encoders convert 2N lines of input into a code of N bits
and Decoders decode the N bits into 2N lines.
DECODER
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One of
these outputs will be active High based on the combination of inputs present, when the decoder is
enabled. That means decoder detects a particular code.
Page 78 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A & B and four outputs Y0, Y1, Y2 & Y3. The block diagram of 2
to 4 decoder is shown in the following figure.
One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’. The Truth
table of 2 to 4 decoder is shown below.
Enable
E
0
1
1
1
1
Inputs
A
B
x
x
0
0
0
1
1
0
1
1
Y0
0
1
0
0
0
Outputs
Y1 Y2
0
0
0
0
1
0
0
1
0
0
Y3
0
0
0
0
1
From Truth table, we can write the Boolean functions for each output as
Y0  E. A.B
Y1  E. A.B
Y2  E. A.B
Y3  E. A.B
Each output is having one product term. So, there are four product terms in total. We can implement
these four product terms by using four AND gates having three inputs each & two inverters.
The circuit diagram of 2 to 4 decoder is shown in the following figure.
Y0  E. A.B
Y1  E. A.B
Y2  E. A.B
Y3  E. A.B
Page 79 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
3 to 8 Decoder
Let 3 to 8 Decoder has two inputs A & B and 8 outputs Y0, Y1, Y2, Y3, Y4, Y5 Y6 & Y7. The block
diagram of 3 to 8 decoder is shown in the following figure.
The Truth table of 3 to 8 decoder is shown below.
Enable
E
0
1
1
1
1
1
1
1
1
A
x
0
0
0
0
1
1
1
1
Inputs
B
x
0
0
1
1
0
0
1
1
C
x
0
1
0
1
0
1
0
1
Y0
0
1
0
0
0
0
0
0
0
Y1
0
0
1
0
0
0
0
0
0
Y2
0
0
0
1
0
0
0
0
0
Outputs
Y3 Y4
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
Y5
0
0
0
0
0
0
1
0
0
Y6
0
0
0
0
0
0
0
1
0
Y7
0
0
0
0
0
0
0
0
1
From Truth table, we can write the Boolean functions for each output as
Y0  E. A.B.C
Y1  E. A.B.C
Y2  E. A.B.C
Y3  E. A.B.C
Y4  E. A.B.C
Y5  E. A.B.C
Y6  E. A.B.C
Y7  E. A.B.C
The circuit diagram of 3 to 8 decoder is shown in the following figure.
Page 80 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Y0  E. A.B.C
Y1  E. A.B.C
Y2  E. A.B.C
Y3  E. A.B.C
Y4  E. A.B.C
Y5  E. A.B.C
Y6  E. A.B.C
Y7  E. A.B.C
ENCODER
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the input,
which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is optional to
represent the enable signal in encoders.
4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y0, Y1, Y2 & Y1 and two outputs A & B. The block diagram of 4
to 2 Encoder is shown in the following figure.
At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output. The Truth table of 4 to 2 encoder is shown below.
Inputs
Outputs
Y0 Y1 Y2 Y3
A
B
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
1
1
Page 81 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
From Truth table, we can write the Boolean functions for each output as
A  Y2  Y3
B  Y1  Y3
We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.
8 to 3 encoder (Octal to Binary Encoder)
Octal to binary Encoder has eight inputs, Y0 to Y7 and three outputs A, B & C. The block diagram of
octal to binary Encoder is shown in the following figure.
At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary code.
The Truth table of octal to binary encoder is shown below.
Inputs
Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
From Truth table, we can write the Boolean functions for each output as
A  Y4  Y5  Y6  Y7
B  Y2  Y3  Y6  Y7
C  Y1  Y3  Y5  Y7
Page 82 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
MULTIPLEXER (MUX)
Multiplexer is a logic circuit that accepts several data inputs and allows only one of them at time as
output. The routing of the desired data input to the output is controlled by SELECT inputs.
Multiplexer has maximum of 2n data inputs, ‘n’ selection lines and single output line. One of these
data inputs will be connected to the output based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination will select only one data input. Multiplexer is also called as Mux.
2x1 Multiplexer
2x1 Multiplexer has two data inputs D1 & D0, one selection line S0 and one output Y. The block
diagram of 2x1 Multiplexer is shown in the following figure.
One of these 2 inputs will be connected to the output based on the input at the select line. Truth
table of 2x1 Multiplexer is shown below.
Select Input
Output
S0
Y
0
D0
1
D1
Boolean function from truth table is
Y  S0 D0  S0 D1
Logic diagram is shown below.
Page 83 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
4x1 Multiplexer
4x1 Multiplexer has four data inputs D3, D2, D1 & D0, two selection lines S1 & S0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on the combination of inputs present at
these two selection lines. Truth table of 4x1 Multiplexer is shown below.
Selection lines
S1
S0
0
0
0
1
1
0
1
1
Output
Y
D0
D1
D2
D3
Boolean function for output, Y is
Y  S1 S 0 D0  S1S 0 D1  S1 S 0 D2  S1S0 D3
The logic diagram of 4x1 multiplexer is shown in the following figure.
Use a 4 x 1 MUX to implement the logic function f ( A, B, C )   (1, 2, 4, 7) . Choose A and B as
select inputs.
Ans:- A and B are the select inputs S1 and S0 of a 4 x 1 MUX.
S1
S0
f
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
f C
Page 84 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
f C
f 0
f 1
Use a 8 x 1 MUX to implement the logic function
f  A B C
Ans:- We can assume inputs A, B and C as select inputs S2, S1 and S0 of a 8 x 1 MUX.
S2
S1
S0
f
A
B
C
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Page 85 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Implement the function f (a, b, c )  ab  bc using 4 x 1 mux. Choose a and b as select inputs.
Implement the function f (a, b, c)   m(1,5, 6, 7) using 4 x 1 mux.
DEMULTIPLEXER
A multiplexer takes several inputs and transmits one of them to the output. A demultiplexer performs
the reverse operation; it takes a single input and distributes it over several outputs.
Demultiplexer (Demux) has single input, ‘n’ selection lines and maximum of 2n outputs. The input
will be connected to one of these outputs based on the values of selection lines.
1x4 Demultiplexer
1x4 Demultiplexer has one input D, two selection lines, S1 & S0 and four outputs Y3, Y2, Y1 &Y0.
The block diagram of 1x4 Demultiplexer is shown in the following figure.
The single input D will be connected to one of the four outputs, Y 3 to Y0 based on the values of
selection lines S1 & S0. The Truth table of 1x4 Demultiplexer is shown below.
Inputs
S1 S0
0
0
0
1
1
0
1
1
Y3
0
0
0
D
Outputs
Y2 Y1
0
0
0
D
D
0
0
0
Y0
D
0
0
0
From the above Truth table, we can write the Boolean functions for each output as
Y0  S1 S0 D
Y1  S1 S0 D
Y2  S1S0 D
Y3  S1S0 D
The logic diagram of 1x4 Demultiplexer is shown in the following figure.
Page 86 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
BCD to DECIMAL DECODER
A BCD to decimal decoder takes four binary lines A, B, C and D with D being the LSB, and decodes
them into a decimal value, 0–9 using a logic circuit. It is a 4 line to 10 line decoder.
BCD
Output
A
B
C
D
Y
0
0
0
0
0
Y0  ABC D
0
0
0
1
1
Y1  ABCD
0
0
1
0
2
Y2  ABC D
0
0
1
1
3
Y3  ABCD
0
1
0
0
4
Y4  ABC D
0
1
0
1
5
Y5  ABCD
0
1
1
0
6
Y6  ABC D
0
1
1
1
7
Y7  ABCD
1
0
0
0
8
Y8  ABC D
1
0
0
1
9
Y9  ABCD
The logic circuit for BCD to decimal decoder is shown below.
Page 87 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
BCD to SEVEN SEGMENT DECODER
Page 88 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Decimal
Digit
0
1
2
3
4
5
6
7
8
9
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Input
B
C
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pattern
abcdef
bc
abged
abgcd
fgbc
afgcd
afgcde
abc
abcdefg
abcdfg
a
1
0
1
1
0
1
1
1
1
1
x
x
x
x
x
x
b
1
1
1
1
1
0
0
1
1
1
x
x
x
x
x
x
c
1
1
0
1
1
1
1
1
1
1
x
x
x
x
x
x
Output
d
1
0
1
1
0
1
1
0
1
1
x
x
x
x
x
x
e
1
0
1
0
0
0
1
0
1
0
x
x
x
x
x
x
f
1
0
0
0
1
1
1
0
1
1
x
x
x
x
x
x
g
0
0
1
1
1
1
1
0
1
1
x
x
x
x
x
x
Truth table - a
Page 89 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
a  A  C  BD  BD
Truth table - b
b  B  CD  C D
Truth table - c
c CDB
Truth table - d
d  A  BC  BD  BCD  C D
Truth table - e
Page 90 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
e  BD  C D
Truth table - f
f  A  C D  BD  BC
Truth table - g
g  A  C D  BC  BC
The logic diagram is shown below.
Page 91 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
a
BD
BD
B
b
C
c
CD
CD
D
BC
B
A
d
BD
BCD
CD
BD
e
CD
f
CD
BD
BC
g
CD
BC
BC
CODE CONVERTER
A code converter is a logic circuit that changes data presented in one type of binary code to another
type of binary code, such as BCD to binary, BCD to 7segment, binary to BCD, BCD to XS3, binary
to Gray code, and Gray code to binary.
BINARY TO GRAY CODE CONVERTER
Gray Code system is a binary number system in which every successive pair of numbers differs in
only one bit.
Let B3, B2, B1, B0 be the bits representing the binary numbers, where B0 is the LSB and B3 is the
MSB, and let G3, G2, G1, G0 be the bits representing the gray code of the binary numbers, where G 0
is the LSB and G3 is the MSB.
Page 92 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The truth table for the conversion is
Binary
Gray Code
B 3 B 2 B 1 B 0 G3 G2 G1 G0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
To find the corresponding digital circuit, we will use the K-Map technique for each of the gray code
bits as output with all of the binary bits as input.
K – map for G0 is
K – map for G1 is
G0  B1 B0  B1 B0  B0  B1
K – map for G2 is
G2  B3 B2  B3 B2  B2  B3
G1  B1 B2  B2 B1  B1  B2
K – map for G3 is
G3  B3
Page 93 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The logic circuit for binary to Gray code conversion is given below.
ARITHMETIC & LOGIC UNIT
An ALU is a critical component of a computer's central processing unit (CPU) responsible for
performing arithmetic and logical operations.
The ALU receives inputs from registers and produces outputs based on the instruction it receives. It
executes calculations using binary numbers and manipulates them using logic gates. By combining
and manipulating these inputs, the ALU generates the desired output, which is then stored back in the
registers for further processing.
The primary components of an ALU include arithmetic circuits (adders and subtractors), logic circuits
(AND, OR, XOR gates), and control circuits. The arithmetic circuits perform mathematical
operations like addition and subtraction, while the logic circuits handle logical operations such as
AND, OR, and XOR. The control circuits coordinate and control the flow of data and operations
within the ALU.
The basic ALU operates on integers rather than floating point numbers. Two numbers (operands), A
and B, are presented to the input of the ALU, and also an instruction - formally called an 'opcode',
such as 'add', 'subtract', 'multiply', 'divide', 'compare'. The ALU carries out the requested operation on
A and B and produces an output result.
Along with the result, a set of status flags are set which include 'Zero', 'Carry', 'Negative', 'Overflow'.
Page 94 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
-MODULE 4
Flip-Flops, SR, JK, D and T flip-flops, JK Master Slave Flip-flop, Preset and clear inputs,
Conversion of flip-flops.
Registers -SISO, SIPO, PISO, PIPO.
Up/Down Counters: Asynchronous Counters – Modulus of a counter – Mod-N counters Ring
counter, Johnson Counter
Synchronous counters, Design of Synchronous counters
4
4.1
4.2
4.3
4.4
4.5
4.6
Sequential circuits (10 hours)
Flip-Flops, SR, JK, D and T flip-flops, JK Master Slave Flip-flop, Preset
and clear inputs
Conversion of flip-flops
Registers -SISO, SIPO, PISO, PIPO
Up/Down Counters: Asynchronous Counters – Modulus of a counter –
Mod-N counters
Ring counter, Johnson Counter.
Design of Synchronous counters
2
2
1
2
1
2
SEQUENTIAL CIRCUITS
The combinational circuit does not use any memory. Hence the previous state of input does not have
any effect on the present state of the circuit. But sequential circuit has memory so output can vary
based on input. This type of circuits uses present input, output, clock and a memory element.
Block diagram of a sequential circuit is given below.
S.No.
Combinational Circuits
Sequential Circuits
1
Output variables at any instant depends only Output variables at any instant depends not
on the present input variables.
only on the present input variables but also
on the past history of the system.
2
Memory unit is not required
Memory unit is required to store the past
history of the input variables.
3
Combinational circuits are faster because Sequential circuits are slower than
the delay between the input and the output is combinational circuits.
due to propagation delay of gates only.
4
Combinational circuits are easy to design.
Sequential circuits are comparatively harder
to design.
Page 95 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
CLASSIFICATION OF SEQUENTIAL CIRCUITS
Synchronous sequential circuits
Asynchronous sequential circuits
The sequential circuits which are controlled by The sequential circuits which are not controlled
a clock are called synchronous sequential by a clock are called asynchronous sequential
circuits. These circuits will be active only when circuits. In asynchronous sequential circuit,
clock signal is present.
events can take place any time the inputs are
applied.
LATCH
Latches are digital circuits that store a single bit of information and hold its value until it is updated
by new input signals. They are used in digital systems as temporary storage elements to store binary
information.
A latch is a type of level-triggered memory circuit, i.e., it checks the input and, responds to the input
changes immediately and changes the output accordingly.
Latch has two stable states, often called “set” and “reset,” and two outputs. The state of the latch can
be changed by applying a certain combination of signals to its inputs. Once the state has been set, it
will remain there until a different combination of signals is applied to the inputs.
FLIP-FLOP
A flip-flop is an edge-triggered type of memory circuit, i.e., it checks the input but changes the output
only when the clock signal changes.
Unlike a latch, a flip-flop has a clock input that determines when the state of the flip-flop can be
changed. The output of the flip flop will change based on its current state and the inputs, but only
when the clock signal changes.
Comparison of Latch & Flip-flop
Benchmark
Latch
Flip Flop
It is designed using
Logic gates.
Latches along with a clock.
It changes the output
when the
Input changes.
Input and the clock signal changes.
It is sensitive to the
The applied input signal, but
only when enabled.
Applied input and the clock signal.
Does it always have a
clock signal?
No. Latches don’t have clock
signals.
Yes.
Works using
Binary inputs.
Binary input and the clock signal.
Type of memory circuit
Level-triggered (outputs can
change as soon as the inputs
change)
Edge-triggered
Operation type
It performs
operations.
It performs synchronous operations.
Types
J-K, S-R, D, and T.
asynchronous
J-K, S-R, D, and T.
Page 96 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Is it capable of working
as a register?
No.
Yes.
Operating speed
Fast in comparison to flipflop.
Slow in comparison to a latch.
Analysing the circuit is
Quite complex in comparison
to flip-flops.
Quite easy in comparison to a latch.
Area
It requires less area
comparison to flip-flops.
in
It requires more area in comparison to
a latch.
Power requirement
It requires less power in
comparison to flip-flops.
It requires more power in comparison
to a latch.
Robustness
Less robust in comparison to
flip flop.
More robust in comparison to a latch.
Is it protected against
any faults?
No.
Yes.
SR Latch
SR latch (Set/Reset) works independently of clock signals and depends only upon S and R inputs, so
they are also called as asynchronous devices. SR latch can be created in two ways- by using NAND
gates and also can be implemented using NOR gates. SR latch created by NAND gates is sometimes
called an inverted SR latch.
SR Latch – NOR gate
R
S
Q
Q
Note: For a NOR gate, when any input is 1, output is zero.
Case 1: S=1, R=0
In this case, since S = 1, output of the second NOR gate will be 0 i.e., Q  0 . Since both inputs to
first NOR gate are 0s, so the output will be Q  1 . Thus, this condition of latch is known as Set
Condition.
Case 2: S=0 and R=0
Now, suppose, initially the value of Q  1 and Q  0 (above state). Now, when S=0 and R=0, output
of second NOR gate Q will be 0 since one of the inputs is 1. Since both the inputs of first NOR gate
are zeros, output Q will be 1. In this case, output in the next state remains the same as the output in
the previous state. This condition of the latch is known as Memory condition / Latched state.
Case 3: S=0, R=1
Page 97 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
In this case, since R = 1, output of the first NOR gate will be 0 i.e., Q  0 . Since both inputs of second
NOR gate are 0s, its output will be Q  1 . Thus, this condition of latch is known as Reset Condition.
Case 4: S=0 and R=0
Now, suppose, initially the value of Q  0 and Q  1 (above state). Now, when S=0 and R=0, output
of first NOR gate Q will be 0 since one of the inputs is 1. Since both the inputs of second NOR gate
are zeros, output Q will be 1. In this case, output in the next state remains the same as the output in
the previous state. This condition of the latch is known as Memory condition / Latched state.
Case 4: R=1, S=1
At both gates, outputs Q  0 and Q  0 , which is absurd and does not follow the basic working of
latch, both Q and Q must be complementary to each other. So, this condition of latch is known
as Invalid state /Forbidden state.
S
R
0
0
1
1
0
1
0
1
Q
Q
Latch
0
1
1
0
Invalid
SR Latch - NAND gate
S
R
Q
Q
Note: For a NAND gate, when any input is 0, output is 1.
Case 1: S=0, R=1
Since S = 0, output at the first NAND gate will be 1 i.e., Q  1 . Since both the inputs of second
NAND gate are 1, the output Q  0 (set condition)
Case 2: S=1, R=1
Now, suppose, initially the value of Q  1 and Q  0 (above state). Now, when S=1 and R=1, output
of first NAND gate Q will be 1 since one of the inputs is 0. Since both the inputs of second NAND
gate are 1s, output Q  0 . In this case, output in the next state remains the same as the output in the
previous state (No change).
Case 3: S=1, R=0
In this case, since R = 0, output at the second NAND gate will be 1 i.e., Q  1 . Since both the inputs
to first NAND gate will be 1s, the output will be Q  0 (reset condition)
Case 4: S=1 and R=1
Now, initially the value of Q  0 and Q  1 (above state). Now, when S=1 and R=1, output of second
NAND gate Q will be 1 since one of the inputs is 0. Since both the inputs of first NAND gate are 1s,
Page 98 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
output Q will be 0. In this case, output in the next state remains the same as the output in the previous
state (No change).
Case 4: R=0, S=0
At both gates, outputs Q  1 and Q  1 , which is absurd and does not follow the basic working of
latch, both Q and Q' must be complementary to each other (Invalid or Forbidden state).
S
Q
R
Q
0
0
1
1
0
1
0
1
Invalid
1
0
0
1
No change
Digital systems can operate either asynchronously or synchronously. In asynchronous systems, the
outputs of logic circuits can change state any time one or more of the inputs changes. An
asynchronous system is generally more difficult to design and troubleshoot than a synchronous
system.
In synchronous systems, the exact times at which any output can change states are determined by a
signal commonly called the clock. This clock signal is generally a rectangular pulse train or a square
wave. The clock signal is distributed to all parts of the system. The changes in the output occur either
at positive (rising) edge or at the negative (falling) edge of the clock pulse. Such type of triggering is
known as edge triggering.
So the flip-flops should either be positive edge triggered flip-flops or negative edge triggered flipflops. A small triangle shown at the clock terminal of the flip-flop indicates the positive edge triggered
flip-flop. However, small triangle with a bubble at the clock terminal of the flip-flop indicates the
negative edge triggered flip-flop.
Q
S
S
CLK
R
Q
CLK
Q
R
Q
Page 99 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
SR FLIP FLOP
S*
S
Q
R*
R
Q
For an SR latch, the truth table is
S*
R*
0
0
1
1
0
1
0
1
Q
Q
Invalid
1
0
0
1
No change
Here, S *  S .CLK  S  CLK
R*  R.CLK  R  CLK
For the SR flip-flop, the truth table is given as
CLK
S
Q
R
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
CLK
0
1
1
1
1
Q
S*
R*
Memory
Memory
x
1
1
0
0
x
1
0
1
0
0
1
1
0
Invalid
S
x
0
0
1
1
R
x
0
1
0
1
Qn+1
Qn
Qn
0
1
Invalid
Characteristic table of an SR flip-flop is given below:
S
Qn
R
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Qn+1
0
0
1
Invalid
1
0
1
Invalid
Page 100 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Boolean expression for Qn+1 is
Qn 1  S  Qn R (characteristic equation of SR flip-flop)
Excitation table of SR flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
S
0
1
0
x
R
x
0
1
0
D FLIP-FLOP
D flip-flop is a modified clocked SR flip-flop and has only one input in addition to the clock pulse.
S
Q
D
S
Q
CLK
R*
R
CLK
D
0
x
1
0
1
1
Characteristic table of a D flip-flop is given below:
Qn
D
0
0
0
1
1
0
1
1
Boolean expression for Qn+1 is
Qn 1  D (characteristic equation of D flip-flop)
Excitation table of D flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Q
R
Q
Qn+1
Qn
0
1
Qn+1
0
1
0
1
D
0
1
0
1
Page 101 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
J-K FLIP-FLOP
JK stands for Jack Kilby.
Among the various types of flip flops, JK Flip Flop stands out as one of the most versatile and widely
used.




J
Q
K
Q
J=0, K=0: In this state, flip-flop retains its preceding state. It neither sets nor resets itself,
making it stable.
J=0, K=1: This input combination forces flip flop to reset, resulting in Q=0 and Q̅=1. It is
often referred to as the “reset” state.
J=1, K=0: Here, flip flop resides in the set mode, causing Q=1 and Q̅=0. It is known as the
“set” state.
J=1, K=1: This combination toggles flip flop. If the previous state is Q=0, it switches to Q=1
and vice versa.
CLK
J
K
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Q
Q
memory
memory
0
1
1
0
memory
Working of JK flip-flop when J = 1 and K = 1.
Case 1: Let us assume initially Q  1 and Q  0 . With J =1 and K = 1, output changes to Q  0 and
Q 1
J
Q
1 0
K
Q
0 1
Case 2: Let us assume initially Q  0 and Q  1 . With J =1 and K = 1, output changes to Q  1 and
Q0
Page 102 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
J
Q
0 1
K
Q
1 0
Truth table of JK flip-flop is
CLK
0
1
1
1
1
J
x
0
0
1
1
K
x
0
1
0
1
Characteristic table of an JK flip-flop is given below:
J
Qn
K
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Qn+1
Qn
Qn
0
1
Qn
Qn+1
0
0
1
1
1
0
1
0
Boolean expression for Qn+1 is
Qn 1  Q n J  Qn K (characteristic equation of JK flip-flop)
Excitation table of JK flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
J
0
1
x
x
K
x
x
1
0
Page 103 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
PROPOGATION DELAY
The propagation delay refers to the time it takes for a change in the input signal to be reflected in the
output of a flip flop. It is the delay between the input transition and the corresponding
output transition.
Propagation delay time is specified for the rising and falling outputs. It is measured between the
50% level of the clock to the 50% level of the output.
RACE AROUND PROBLEM
For J-K flip-flop, if J=K=1, and if CLK=1 for a long period of time, then Q output will toggle as long
as CLK is high, which makes the output of the flip-flop unstable or uncertain. This problem is called
race around condition in J-K flip-flop.
Let us consider the inputs J = 1 and K = 1, and the output Q = 0. After the propagation delay (let Δt)
of the flip-flops, the output of the JK flip-flops changes from 0 to 1. As we know, the output of the
JK flip-flops is connected to its inputs. Hence, the output also acts as input, and thus after the next
delay (Δt), the output will change from 1 to 0. This process will continue till the end of the applied
clock signal. Thus, the output of the JK flip-flops is uncertain. This condition of JK flip-flops is called
the race-around condition. (Toggling more than once during a clock cycle is called race-around
condition)
Race-around condition in JK flip-flops is shown in Figure below, where T is the total duration of
clock pulse.
Page 104 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The problem of the race-around condition does not exist in the flip-flops where the inputs do not
change during the presence of clock pulse. But, in the case of JK flip-flops, the inputs change during
the clock pulse due to the feedback path present between inputs and outputs. Hence, in JK flip-flops,
the race around condition is a major problem.
Methods to eliminate race around condition
There are three methods to eliminate race around condition as described below:
Increasing the delay of flip-flop
The propagation delay (t) should be made greater than the duration of the clock pulse (T). But it is
not a good solution as increasing the delay will decrease the speed of the system.
Use of edge-triggered flip-flop
If the clock is High for a time interval less than the propagation delay of the flip flop then race around
condition can be eliminated. This is done by using the edge-triggered flip flop rather than using the
level-triggered flip-flop.
Use of master-slave JK flip-flop
If the flip flop is made to toggle over one clock period, then race around condition can be eliminated.
This is done by using Master-Slave JK flip-flop.
MASTER-SLAVE JK FLIP-FLOP (pulse triggered)
J
J
QM
Q
K
K
Q
QM
The most practical way to solve the problem of race-around condition in JK flip-flops is to use the
JK flip-flops in the Master and Slave Mode. In the master-slave mode of JK flip-flops, two JK flipflops are cascaded.
The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a
series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output
from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back
to inputs of the master flip flop. In addition to these two flip-flops, the circuit also includes
an inverter. The inverter is connected to clock pulse in such a way that the inverted clock pulse is
given to the slave flip-flop. In other words, if CLK=0 for a master flip-flop, then CLK=1 for a slave
flip-flop and if CLK=1 for master flip flop then it becomes 0 for slave flip flop.
Remember:
CLK = 1; J = 1, K = 1
Master flip-flop toggles
Slave flip-flop is inactive
CLK = 0; J = 1, K = 1
Master flip-flop inactive
Slave flip-flop toggles
Page 105 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Working of a master slave flip flop –
Assume initially Q  0 and Q  1 .
1
When CLK is HIGH, J=0 and K=1, QM  0 and Q M  1 . J and K inputs of slave will be 0 and
1 respectively. When CLK becomes LOW, the clock forces the slave to reset. Q  0 and Q  1
. Hence, the slave copies the master
2
When CLK is HIGH, J=1 and K=0, QM  1 and Q M  0 . J and K inputs of slave will be 1 and
0 respectively. When CLK becomes LOW, the clock forces the slave to set. Q  1 and Q  0 .
Hence, the slave copies the master
3
When CLK is HIGH, J=1 and K=1, output of master toggles. QM  0 and Q M  1 . J and K
inputs of slave will be 0 and 1 respectively. When CLK becomes LOW, the clock forces the
slave to toggle the output. Q  0 and Q  1 .
4
If J=0 and K=0, the flip flop is disabled and Q remains unchanged
Timing Diagram of a Master Slave flip flop when J = 1 and K = 1.
A master-slave flip-flop is also called a pulse-triggered flip-flop because the length of the time
required for its output to change state equals the width of one clock cycle.
T FLIP-FLOP (Toggle flip-flop)
A T flip-flop has a single control input, labelled T for toggle. When T is HIGH, the flip-flop toggles
on every new clock cycle. When T is LOW, the flip-flop remains in whatever state it was before.
Q
J
CLK
K
T
Q
Q
Q
Page 106 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
CLK
Q
T
0
1
1
Q
memory
memory
x
0
1
memory
Truth table of T flip-flop is
CLK
0
1
1
T
x
0
1
Characteristic table of an T flip-flop is given below:
Qn
T
0
0
0
1
1
0
1
1
Boolean expression for Qn+1 is
Qn 1  Qn  T (characteristic equation of T flip-flop)
Excitation table of T flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn+1
Qn
Qn
Qn
Qn+1
0
1
1
0
T
0
1
1
0
FLIP-FLOP CONVERSION
Steps for flip-flop conversion:
Step 1 Note available flip-flop and required flip-flop
Step 2 Write characteristic table of required flip-flop
Step 3 Write excitation table of available flip-flop
Step 4 Find Boolean expression
Step 5 Make circuit
SR TO D FLIP-FLOP CONVERSION
Available FF = SR
Required FF = D
Characteristic table of D flip-flop is
Qn
0
0
1
1
D
0
1
0
1
Qn+1
0
1
0
1
Page 107 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Excitation table of SR flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn
0
0
1
1
S
0
1
0
x
S
0
1
0
x
Qn+1
0
1
0
1
D
0
1
0
1
R
x
0
1
0
R
x
0
1
0
Boolean expression is
SD
RD
Circuit of required D flip-flop is
S
Qn
CLK
R
D TO SR FLIP-FLOP CONVERSION
Available FF = D
Required FF = SR
Characteristic table of SR flip-flop is
Qn
0
0
0
0
1
1
1
1
S
0
0
1
1
0
0
1
1
Qn
R
0
1
0
1
0
1
0
1
Qn+1
0
0
1
Invalid
1
0
1
Invalid
Page 108 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Excitation table of D flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn
0
0
0
0
1
1
1
1
S
0
0
1
1
0
0
1
1
D
0
1
0
1
Qn+1
0
0
1
Invalid
1
0
1
Invalid
R
0
1
0
1
0
1
0
1
D
0
0
1
x
1
0
1
x
Boolean expression is
D  S  Qn R
Circuit of required SR flip-flop is
Qn
D
CLK
Qn
SR TO JK FLIP-FLOP CONVERSION
Available FF = SR
Required FF = JK
Characteristic table of JK flip-flop is
Qn
0
0
0
0
1
1
J
0
0
1
1
0
0
K
0
1
0
1
0
1
Qn+1
0
0
1
1
1
0
Page 109 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
1
Excitation table of SR flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn
0
0
0
0
1
1
1
1
J
0
0
1
1
0
0
1
1
K
0
1
0
1
0
1
0
1
0
1
1
0
S
0
1
0
x
R
x
0
1
0
Qn+1
0
0
1
1
1
0
1
0
S
0
0
1
1
x
0
x
0
R
x
x
0
0
0
1
0
1
Boolean expression is
R  Qn K
S  Qn J
Circuit of required JK flip-flop is
S
Qn
CLK
JK TO SR FLIP-FLOP CONVERSION
Available FF = JK
Required FF = SR
Characteristic table of SR flip-flop is
Qn
0
0
0
0
S
0
0
1
1
R
Qn
R
0
1
0
1
Qn+1
0
0
1
Invalid
Page 110 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
Invalid
J
0
1
x
x
K
x
x
1
0
Qn+1
0
0
1
1
1
0
1
0
J
0
0
1
x
x
x
x
x
Excitation table of JK flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
S
0
0
1
1
0
0
1
1
Qn
0
0
0
0
1
1
1
1
R
0
1
0
1
0
1
0
1
K
x
x
x
x
0
1
0
x
Boolean expression is
J R
J S
Circuit of required JK flip-flop is
S
Qn
CLK
Qn
R
D TO JK FLIP-FLOP CONVERSION
Available FF = D
Required FF = JK
Characteristic table of JK flip-flop is
Qn
0
0
0
0
J
0
0
1
1
K
0
1
0
1
Qn+1
0
0
1
1
Page 111 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
0
Excitation table of D flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn
0
0
0
0
1
1
1
1
J
0
0
1
1
0
0
1
1
K
0
1
0
1
0
1
0
1
D
0
1
0
1
Qn+1
0
0
1
1
1
0
1
0
D
0
0
1
1
1
0
1
0
Boolean expression is
D  Q n J  Qn K
Circuit of required JK flip-flop is
Qn
D
CLK
Qn
JK TO D FLIP-FLOP CONVERSION
Available FF = JK
Required FF = D
Characteristic table of D flip-flop is
Qn
0
D
0
Qn+1
0
Page 112 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
0
1
1
0
1
1
Excitation table of JK flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn
0
0
1
1
D
0
1
0
1
1
0
1
J
0
1
x
x
K
x
x
1
0
J
0
1
x
x
Qn+1
0
1
0
1
K
x
x
1
0
Boolean expression is
J D
KD
Circuit of required D flip-flop is
J
Qn
CLK
K
SR TO T FLIP-FLOP CONVERSION
Available FF = SR
Required FF = T
Characteristic table of T flip-flop is
Qn
T
0
0
0
1
1
0
1
1
Excitation table of SR flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn
Qn+1
0
1
1
0
S
0
1
0
x
R
x
0
1
0
Page 113 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Qn
0
0
1
1
S
0
1
x
0
Qn+1
0
1
1
0
T
0
1
0
1
R
x
0
0
1
Boolean expression is
R  QnT
S  Q nT
Circuit of required T flip-flop is
S
Qn
CLK
Qn
R
T TO SR FLIP-FLOP CONVERSION
Available FF = T
Required FF = SR
Characteristic table of SR flip-flop is
Qn
0
0
0
0
1
1
1
1
S
0
0
1
1
0
0
1
1
Excitation table of T flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
Qn+1
0
0
1
Invalid
1
0
1
Invalid
R
0
1
0
1
0
1
0
1
T
0
1
1
0
Page 114 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Qn
0
0
0
0
1
1
1
1
S
0
0
1
1
0
0
1
1
R
0
1
0
1
0
1
0
1
Qn+1
0
0
1
Invalid
1
0
1
Invalid
T
0
0
1
x
0
1
0
x
Boolean expression is
T  Q n S  Qn R
Circuit of required SR flip-flop is
Qn
T
CLK
Qn
D TO T FLIP-FLOP CONVERSION
Available FF = D
Required FF = T
Characteristic table of T flip-flop is
Qn
0
0
1
1
T
0
1
0
1
Qn+1
0
1
1
0
Excitation table of D flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
D
0
1
0
1
Page 115 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Qn
0
0
1
1
Qn+1
0
1
1
0
T
0
1
0
1
D
0
1
1
0
Boolean expression is
D  Q nT  Qn T
Circuit of required T flip-flop is
Qn
D
CLK
Qn
T TO D FLIP-FLOP CONVERSION
Available FF = T
Required FF = D
Characteristic table of D flip-flop is
Qn
0
0
1
1
D
0
1
0
1
Qn+1
0
1
0
1
Excitation table of T flip-flop is given below:
Qn
Qn+1
0
0
0
1
1
0
1
1
T
0
1
1
0
Qn
0
0
1
1
D
0
1
0
1
Qn+1
0
1
0
1
T
0
1
1
0
Page 116 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Boolean expression is
T  Q n D  Qn D
Circuit of required T flip-flop is
Qn
T
CLK
Qn
ASYNCHRONOUS INPUTS
For the clocked flip-flops, the S, R, J, K, and D inputs are referred to as control inputs. These inputs
are also called synchronous inputs because their effect on the FF output is synchronized with the CLK
input. The synchronous control inputs must be used in conjunction with a clock signal to trigger the
FF.
Most clocked FFs also have one or more asynchronous inputs that operate independently of the
synchronous inputs and clock input. These asynchronous inputs can be used to set the FF to the 1
state or clear (reset) the FF to the 0 state at any time, regardless of the conditions at the other inputs.
The asynchronous inputs are override inputs, which can be used to override all the other inputs in
order to place the FF in one state or the other.
Consider a J-K flip-flop with two asynchronous inputs designated PRESET and CLEAR. These are
active-LOW inputs, as indicated by the bubbles on the FF symbol. Let’s examine the various cases.
PRESET
CLEAR
1
1
The asynchronous inputs are inactive and the FF is free to respond to the
J, K, and CLK inputs; in other words, the clocked operation can take
place.
0
1
Q is immediately set to 1 no matter what conditions are present at the J,
K, and CLK inputs. The CLK input cannot affect the FF while PRESET
= 0.
1
0
Q is immediately cleared to 0 independent of the conditions on the J, K,
or CLK inputs. The CLK input has no effect while CLEAR = 0.
0
0
This condition should not be used because it can result in an ambiguous
response.
Page 117 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
J
Q
J
Q
Q
K
Q
CLK
K
Truth table is given below:
PRESET CLEAR
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
CLK
x
x
x
0
1
1
1
1
J
x
x
x
x
0
0
1
1
K
x
x
x
x
0
1
0
1
Qn+1
Not used
1
0
Qn
Qn
0
1
Qn
Many clocked FFs that are available as ICs will have both of these asynchronous inputs; some will
have only the input. Some FFs will have asynchronous inputs that are active-HIGH rather than activeLOW. For these FFs the FF symbol would not have a bubble on the asynchronous inputs.
COUNTER
Counting is frequently required in digital systems to record the number of events occurring in a
specified interval of time. Normally a counter is used for counting the number of pulses coming at
the input line in a specified time period.
Counter is a sequential circuit for counting pulses. It is a group of flip-flops with a clock signal
applied. Synchronous and asynchronous counters are the two widely used counters in digital circuits.
Asynchronous counters:
Asynchronous counter is one in which the flip-flops within the counter do not change states at exactly
the same time because they do not have a common clock pulse.
Asynchronous counters are made up of a series of flip flops that are connected in series. The clock is
applied to the first flip flop only. The second flip-flop is triggered by the transition that occurs at the
output of the first flip-flop. Similarly, the clock input of the third flip-flop is triggered by the output
of the second flip-flop and so on. Their operation and implementation are straightforward and hence
minimum hardware is required. Since each flip-flop is triggered by the previous flip-flop, the speed
of operation is limited. These types of counters are also called ripple counters.
2-bit Asynchronous UP Counter (negative edge triggered)
A 2-bit counter consists of 2 flip-flops and has 4 states. It can count from 00 2 to 112.
Page 118 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
CLK
J0
Q0
J1
Q1
K0
Q0
K1
Q1
CLK is only connected to 1st flip-flop FF0.
The second flip-flop clock is driven by Q0 of first flip-flop.
Both flip-flop inputs are always HIGH.
Q0 changes state at the negative-edge of clock.
Q1 changes state at the negative-edge of the Q0
The two flip-flops are not triggered at the same time because clock and Q0 transitions do not occur
at the same time.
Both flip-flops are connected for toggle operation (J=1, K=1) and are assumed to be initially RESET
(Q0=0, Q1=0). To observe the output of the counter, let’s apply 4 pulses to the CLK input of the first
flip-flop (this is LSB) and observe the output at Q 0 and Q1. All flip-flops are negative edge triggered.
The truth table is given below:
Negative clock
Q1
Q0
Count
transition
0
0
0
a
0
1
1
b
1
0
2
c
1
1
3
d
0
0
0
The timing diagram of 2-bit asynchronous counter is shown below.
3-bit Asynchronous UP Counter (negative edge triggered)
A 3-bit counter consists of three flip-flops and has 8 states. It can count from 000 2 to 1112.
Page 119 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Q1
J0
J2
CLK
CLK
K0
Q0
CLK
Q1
K2
Q2
To observe the output of the counter, let’s apply 8 pulses to the CLK input of the first flip-flop (this
is LSB) and observe the output at Q0, Q1 and Q2. Both J and K inputs are connected to logic HIGH.
All flip-flops are negative edge triggered.
Q0 changes state at the negative-edge of clock.
Q1 changes state at the negative-edge of the Q0
Q2 changes state at the negative-edge of the Q1
The truth table is given below:
Negative clock
Q2
transition
0
a
0
b
0
c
0
d
1
e
1
f
1
g
1
h
0
The timing diagram is shown below:
Q1
Q0
Count
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
0
Page 120 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
2-bit Asynchronous UP Counter (positive edge triggered)
Positive
clock
transition
J
J
Q
Q
a
CLK
CLK
b
Q
Q
K
K
c
d
Q0 changes state at the positive-edge of clock.
Q1
Q0
Count
0
0
1
1
0
0
1
0
1
0
0
1
2
3
0
Q1 changes state at the positive-edge of the Q 0
The timing diagram of 2-bit asynchronous counter (positive edge triggered) is shown below.
Q0
3-bit Asynchronous UP Counter (positive edge triggered)
J
J
Q
CLK
K
Q
J
CLK
Q
K
Q
CLK
Q
K
Q
Q0 changes state at the positive-edge of clock.
Q1 changes state at the positive-edge of the Q 0
Q2 changes state at the positive-edge of the Q1
The truth table is given below:
Page 121 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Positive
clock
transition
a
b
c
d
e
f
g
h
The timing diagram is shown below:
Q2
Q1
Q0
Count
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
0
3-bit Asynchronous DOWN Counter
A 3-bit counter consists of three flip-flops and has 8 states. It can count from 111 2 to 0002.
Q1
J0
CLK
CLK
K0
Q0
J2
CLK
Q1
K2
Q2
To observe the output of the counter, let’s apply 8 pulses to the CLK input of the first flip-flop (this
is LSB) and observe the output at Q0, Q1 and Q2. Both J and K inputs are connected to logic HIGH.
All flip-flops are negative edge triggered.
Q0 changes state at the negative-edge of clock.
Page 122 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Q1 changes state at the negative-edge of the Q 0
Q2 changes state at the negative-edge of the Q1
The truth table is given below:
Negative clock
Q2
transition
1
a
1
b
1
c
0
d
1
e
1
f
1
g
1
h
0
Q1
Q0
Count
1
1
0
1
0
0
1
1
0
1
0
1
1
0
1
0
1
0
0
1
2
3
4
5
6
7
0
The timing diagram is shown below:
Q0
Q1
Q2
Page 123 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
MOD-N ASYNCHRONOUS COUNTER
MOD number of a counter as defined as the number of states that the counter goes through in each
complete cycle before it recycles back to its starting state.
A modulus-M counter is a counter where M represents the number of states present in the counter.
Here, M  2 N , where N represents the number of flip-flops required to design the modulus-M
counter.
For example, the modulus-6 counter has 6 states. Here, the value of N is 3. That means 3 flip-flops
are required to design the modulus-6 counter.
For a modulus-10 (decade) counter, 4 flips are required.
To count M clock pulses which is less than N (N=2n), we need to take the help of a reset terminal
(CLR) of the flip-flops. A combinational circuit is designed such that all the flip-flops can reset after
count M.
Design a mod-6 asynchronous counter
It starts from 0 (=000) and it will count up to 5 (=101).
Q2
Q1
Q0
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
When the counter reaches the state 110, all the flip-flops should go to reset state (=000).
Q1
J0
CLK
CLK
K0
Q0
J2
CLK
Q1
K2
Q2
Page 124 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Design a mod-10 asynchronous counter (Decade counter)
It starts from 0 (=0000) and it will count up to 9 (=1001).
Q3
0
0
0
0
0
0
0
0
1
1
0
1
2
3
4
5
6
7
8
9
Q2
0
0
0
0
1
1
1
1
0
0
Q1
0
0
1
1
0
0
1
1
0
0
Q0
0
1
0
1
0
1
0
1
0
1
When the counter reaches the state 1010, all the flip-flops should go to reset state (=0000).
Q1
J0
CLK
CLK
K0
Q0
J2
J3
CLK
Q1
K2
CLK
Q2
K3
Q3
Page 125 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Difference Between Synchronous and Asynchronous Counters
Application of the clock
The complexity of design
Frequency of operation
Hardware requirements
Propagation delay
Asynchronous Counter
The clock signal is applied to
the first flip-flop only. The
output of the first flip-flop is
connected to the clock input of
the next flip-flop.
Its circuit is easy to design for
a high number of flip-flops
The frequency is lower. Single
clock for the whole counter.
The count ripple through.
Overall operation is slow.
It uses minimum possible
hardware (logic gates)
The propagation delay is quite
high.
Synchronous Counter
All flip-flops are connected to
the same clock and all are
triggered simultaneously.
Its circuit becomes complex as
the number of flip-flops
increases.
Individual clocks for every
flop-flop. No need for setting
time. Hence overall operation
is faster.
Their hardware requirements
(logic gates) are relatively
high.
The propagation delay is less.
SYNCHRONOUS COUNTERS
These counters are made up of a series of flip flops, synchronized with the same clock signal. All of
the flip-flops change their state simultaneously with a single clock pulse – at the same
time. Synchronous counters work at a much higher frequency than their counterpart ripple counters,
as there is no cumulative delay between the two flip-flops.
Steps to design Synchronous counter:
Page 126 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Step 1
Step 2
Step 3
Step 4
Step 5
Identify number of bits and flip-flop
Write excitation table of flip-flop
Make state diagram and state table
Find Boolean expression
Make circuit
Design a 2-bit synchronous counter using JK – flip-flops
Step 1 Identify number of bits and flip-flop
No. of bits = 2 Flip-flop = J K
Step 2
Write excitation table of flip-flop
Qn
0
0
1
1
Step 3
J
0
1
x
x
K
x
x
1
0
Make state diagram and state table
Present State
Q1
Q0
0
0
0
1
1
0
1
1
Step 4
Qn+1
0
1
0
1
Next State
Q1 *
Q0 *
0
1
1
0
1
1
0
0
Inputs
J1
0
1
x
x
K1
x
x
0
1
J0
1
x
1
x
K0
x
1
x
1
Find Boolean expression
Page 127 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
J1  Q0
Step 5
K1  Q0
K0  1
J0  1
Make circuit
Q0
Q1
Q0
Q1
CLK
CLK
Q0
Q1
Design a 3-bit synchronous counter using T – flip-flops
Step 1 Identify number of bits and flip-flop
No. of bits = 3 Flip-flop = T
Step 2
Write excitation table of flip-flop
Qn
0
0
1
1
Step 3
Qn+1
0
1
0
1
T
0
1
1
0
Make state diagram and state table
Page 128 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Present States
Q2
Q1
Q0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Q2
0
0
0
1
1
1
1
0
Step 4
Solve Boolean expression
Step 5
Make circuit
*
Next States
Q1*
Q0 *
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
Q0
CLK
Q1
CLK
Q0
T2
0
0
0
1
0
0
0
1
Inputs
T1
0
1
0
1
0
1
0
1
T0
1
1
1
1
1
1
1
1
Q2
CLK
Q1
Q2
Page 129 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Design a 2-bit synchronous UP/DOWN counter using JK – flip-flops
Step 1 Identify number of bits and flip-flop
No. of bits = 2 Flip-flop = J K
Step 2
Write excitation table of flip-flop
Qn
0
0
1
1
Step 3
J
0
1
x
x
K
x
x
1
0
Make state diagram and state table
Present State
Q1
Q0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Step 4
Qn+1
0
1
0
1
M
0
1
0
1
0
1
0
1
Next State
Q1 *
Q0 *
1
1
0
1
0
0
1
0
0
1
1
1
1
0
0
0
J1
1
0
0
1
x
x
x
x
Inputs
K1
J0
x
1
x
1
x
x
x
x
1
1
0
1
0
x
1
x
K0
x
x
1
1
x
x
1
1
Find Boolean expression
Page 130 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Step 5
J1  Q0 M  Q0 M
K1  Q0 M  Q0 M
J1  1
K1  1
Make circuit
Q0
Q1
CLK
CLK
Q0
Q1
Design a 3-bit synchronous Up-Down counter using T – flip-flops
Step 1 Identify number of bits and flip-flop
No. of bits = 3 Flip-flop = T
Step 2
Write excitation table of flip-flop
Qn
0
0
1
1
Step 3
Qn+1
0
1
0
1
T
0
1
1
0
Make state diagram and state table
Page 131 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Present States
Q2
Q1
Q0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Step 4
Mode
M
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q2
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
*
Next States
Q1 *
Q0 *
1
1
0
1
0
0
1
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
1
0
0
1
1
1
1
0
0
0
T2
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
Inputs
T1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
T0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Solve Boolean expression
K – map for T2 is
K – map for T1 is
Page 132 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
T2  Q1Q0 M  Q1 Q0 M
T1  Q0 M  Q0 M
T0  1
Step 5
Make circuit
Q0
Q1
CLK
CLK
Q0
Q2
CLK
Q1
Q2
Design a 3-bit synchronous counter to count 0, 3, 5, 6, 0 …. using T – flip-flops
Step 1 Identify number of bits and flip-flop
No. of bits = 3 Flip-flop = T
Step 2 Write excitation table of flip-flop
Qn
0
0
1
1
Step 3
Qn+1
0
1
0
1
T
0
1
1
0
Make state diagram and state table
Page 133 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Present States
Q2
Q1
Q0
0
0
0
0
1
1
1
0
1
1
1
0
Step 4
Q2
0
1
1
0
*
Next States
Q1*
Q0 *
1
1
0
1
1
0
0
0
Inputs
T1
1
1
1
1
T2
0
1
0
1
T0
1
0
1
0
Solve Boolean expression
T0  Q1
T2  Q1
Step 5
Make circuit
Q0
Q1
CLK
Q2
CLK
Q0
CLK
Q1
Q2
RING COUNTER
A ring counter is a typical application of the Shift register. The only change is that the output of the
last flip-flop is connected to the input of the first flip-flop in the case of the ring counter but in the
case of the shift register it is taken as output.
Q0
CLK
Q1
CLK
Q2
CLK
Q3
CLK
In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flops simultaneously.
Therefore, it is a Synchronous Counter. Also, here we use Overriding input (ORI) for each flip-flop.
Preset (PR) and Clear (CLR) are used as ORI. When PR is 0, then the output is 1. And when CLR is
0, then the output is 0. Both PR and CLR are active low signal that always works in value 0.
PR = 0  Q = 1
Page 134 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
CLR = 0  Q = 0
Working:
ORI is connected to Preset (PR) in FF0 and it is connected to Clear (CLR) in FF1, FF2 and FF3. Thus,
output Q0 = 1 is generated at FF0, and the rest of the flip-flop generates output Q = 0. So the initial
state is 1000.
This Preseted 1 is generated by making ORI low and that time Clock (CLK) becomes don’t care.
After that ORI is made to high and apply low clock pulse signal as the Clock (CLK) is negative edge
triggered. After that, at each clock pulse, the preseted 1 is shifted to the next flip-flop and thus forms
a Ring.
The sequence table is shown below.
ORI CLK Q0
Q1
Q2
Q3
Clock pulse No.
LOW
x
1
0
0
0
0
1
0
1
0
0
1

1
0
0
1
0
2

1
0
0
0
1
3

1
1
0
0
0
4

No. of states in Ring counter = No. of flip-flop used
Here, no. of states = 4 and the 4 states are shown below.
1000
0100
0010
0001
The timing diagram is given below:
In ring counter, only n out of 2n states are utilized.
Ring counter is non-self-starting meaning it requires external intervention to initialize the counter.
Page 135 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
JOHNSON COUNTER
In Johnson counter, the complemented output Q 3 of last flip flop is connected to the input of first flip
flop. Johnson counter is also called twisted ring counter or creeping counter.
The number of states in a twisted ring counter is twice the number of flip-flops used. For example, a
4-bit twisted ring counter has eight states: 0000, 1000, 1100, 1110, 1111, 0111, 0011, and 0001. The
bit pattern repeats every eight clock cycles.
Initially all the FFs are reset. The state of the counter is 0000. After each clock pulse, the output level
of Q0 is shifted to Q1, the level of Q1 to Q2, the level of Q2 to Q3 and the level of Q3 to Q4. The
sequence is repeated after every eight clock pulses.
Q0
CLK
Q1
Q2
CLK
Q3
CLK
CLK
Q3
The sequence table is shown below.
CLR CLK Q0
LOW
x
0
1
1

1
1

1
1

1
1

1
0

Q1
0
0
1
1
1
1
Q2
0
0
0
1
1
1
Q3
0
0
0
0
1
1
0
0
1
1

0
0
0
1

1
0
0
0
0

The state diagram of a Johnson counter is shown below.
1
1
Clock pulse No.
0
1
2
3
4
5
6
7
8
Page 136 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The timing diagram of Johnson counter is shown below:
The Johnson counter has same number of flip flop but it can count twice the number of states the ring
counter can count.
It can self-start from an all-zero state, eliminating the need for external initiation.
REGISTER
Flip-flop is used to store 1 bit data. To increase storage capacity, we use a group of flip-flops, which
is referred as register.
By using N number of flip-flops, we can store N bits data of register which can store N bits word.
For example, consider a 4-bit register.
Data formats
i)
Serial – We can store one bit at a time
ii)
Parallel – We can store all bits at a time
Classification of Registers:
We can classify register based on input and output.
Page 137 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
SISO (Serial Input & Serial Output)
2
SIPO (Serial Input & Parallel Output)
3
PISO (Parallel Input & Serial Output)
4
PIPO (Parallel Input & Parallel Output)
Classifications can be done based on applications
1. Shift register (store bits one by one; examples are SISO, SIPO, PISO)
2. Storage register (store data completely at a time; example is PIPO)
A register capable of shifting its binary information either to the right or to the left is called a shift
register. The logical configuration of a shift register consists of a chain of flip flops connected in
cascade, with the output of one flip flop connected to the input of the next flip flop. All flip flops
receive a common clock pulse which causes the shift from one stage to the next.
SISO Shift Register
The logic diagram of a 4-bit serial-in, serial-out, shift-right, shift register is shown in figure. With
four stages ie, four FF's, the register can store upto 4 bits of data. Serial data is applied at the D input
of the first FF. The Q output of the first FF is connected to the D input of the second FF, the Q output
of the second FF is connected to the D input of the third FF and the Q output of the third FF is
connected to the D input of the fourth FF. The data is outputted from the Q terminal of the last FF.
When serial data is transferred into a register, each new bit is clocked into the first FF at the positivegoing edge of each clock pulse. The bit that was previously stored by the first FF is transferred to the
second FF. The bit that was stored by the second FF is transferred to the third FF, and so on. The bit
that was stored by the last FF is shifted out.
Page 138 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Q3
Q2
Q1
Q0
Q0
Let the input be Din = 1011.
CLK
Initially


Din
1
1
Q3
0
1
1
Q2
0
0
1
Q1
0
0
0
Q0
0
0
0


0
1
0
1
1
0
1
1
0
1
clock
N
clock
pulses
N–1
clock
pulses
1
2
3
4
5
6
7
Q0
0
0
0
1
0
1
1
Page 139 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
For a N – bit shift register, N clock pulses are required to store data and an additional N-1 clock
pulses are required to take data from Q0. Hence, for total processing, (2N – 1) clock pulses are
required.
SIPO Shift Register
In this type of register, the data bits are entered into the register serially, but the data stored in the
register is shifter out in parallel form.
On the first clock pulse, the first bit of the serial input enters the first flip-flop and the existing data
in the register shifts by one position. On the second clock pulse, the second bit of the serial input
enters the first flip-flop and the existing data in the register shifts by one position. This process
continues.
Q3
Q3
Q1
Q2
Q2
Q1
Q0
Q0
Q0
Let the input be Din = 1011.
CLK
Initially




Din
1
1
0
Q3
0
1
1
0
Q2
0
0
1
1
Q1
0
0
0
1
Q0
0
0
0
0
1
1
0
1
1
Page 140 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Here, only N clocks are required for storing data. We don’t need additional N – 1 clocks to get output.
PISO Shift Register
The shift register which uses parallel input and generates serial output is known as the parallel input
serial output shift register or PISO shift register.
In PISO shift registers, the data is loaded onto the register in parallel format while it is retrieved from
it serially.
The following figure shows a PISO shift register which has a control-line Shift / Load and
combinational circuit (AND and OR gates) in addition to the basic register components (flip-flops)
fed with clock.
Page 141 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Shift / Load
Q3
Q2
Q1
Q0
Here Shift / Load control line is used to select the functionality of the shift register amongst shift or
load at a given instant of time. This is because when the Shift / Load line is made low, A2 AND gates
of all the combinational circuits become active while A1 gates become inactive. Thus the bits of the
input data word (Data in) appearing as inputs to the gates A 2 are passed on as the outputs of OR gates
at each individual combinational circuit. This causes the individual bits of the data in to be
loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the
bit b3 which gets directly stored into FF3 at the first clock tick). This indicates that all the bits of the
input data word are stored into the register components at the same clock tick.
Shift / Load
Next, Shift / Load line is driven high to activate the gates A1 of the combinational circuits which in
turn disables the gates A2. This causes output bit of each flip-flop to appear at the output of the OR
gate driving the very-next flip-flop (except the last flip-flop FF3) i.e. output bit of FF3 (Q3) appears
as the output of OR gate 1 (O1) connected to D2; Q2 = output of O2 = D1 and so on. At this stage, if
the rising edge of the clock pulse appears, then Q3 appears at Q2, Q2 appears at Q1 and Q1 appears at
Q0.
Page 142 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Shift / Load
This is nothing but right-shift of the data stored within the register by one-bit. Similarly, it is seen
that for each of the further clock pulses applied, one bit exits the PISO shift register through the output
pin of flip-flop FF0, which is nothing but the serial output. Thus, one requires n clock cycles to obtain
the entire n-bit input data word as a serial output of PISO shift register.
Let the input be 1011. (b3 = 1; b2 = 0; b1 = 1, b0 = 1)
Q0
CLK
Q3
Q2
Q1
Shift / Load
Data Out
Initially
0
0
0
0
  Data
Loading


0
1
0
1
1 (= b0)



1
1
1
0
1 (= b1)
Data


Retrieval
1
1
1
1
0 (= b2)

1
1
1
1
1 (= b3)

Shift / Load
Page 143 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
PIPO Shift Register
The shift register which uses parallel input and generates parallel output is known as the parallel input
parallel output shift register or PIPO shift register.
Each flip-flop can store one bit of data. The data can be loaded into the flip-flops simultaneously
through the parallel input. Once the data is loaded, it can be read out simultaneously from each flipflop through the parallel outputs.
Q3
Q2
Q1
Q0
Q0
Q3
Q2
Q1
Q0
Both data storage as well as data recovery occur at a single (and at the same) clock pulse in PIPO
registers.
The PIPO register shown in figure above is not capable of shifting the data bits. In order to convert
PIPO register of above figure into PIPO shift register, one has to modify its circuit by adding
combinational circuit and control line.
Page 144 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
MODULE 5
State Machines: State transition diagram, Moore and Mealy Machines
Digital to Analog converter –Specifications, Weighted resistor type, R-2R Ladder type.
Analog to Digital Converter – Specifications, Flash type, Successive approximation type.
Programmable Logic Devices - PAL, PLA, FPGA (Introduction and basic concepts only)
Introduction to Verilog, Implementation of AND, OR, half adder and full adder. Note: Course
assignments may be given in Verilog programming
5
5.1
5.2
5.3
5.4
5.5
State Machines, D/A and A/D converters and PLDs (7 hours)
State Machines: State transition diagram, Moore and Mealy Machines
Digital to Analog converter – R-2R ladder, weighted resistors
Analog to Digital Converter - Flash ADC, Successive approximation
Programmable Logic Devices - PAL, PLA - function implementation - FPGA
(Introduction and basic concepts only)
Introduction to VHDL, Implementation of AND, OR, half adder and full adder.
1
1
1
2
2
FINITE STATE MACHINE
For a combinational circuit, output depends on the present inputs and for a sequential circuit output
depends on the present inputs and the present state of the memory elements. Memory element is a
group of flip-flops. For a combinational circuit, we will get the same output for a given set of inputs.
But for a sequential circuit, we may not get the same output, for a given set of inputs; it depends on
the present state of the memory elements.
Finite state machine is abstract model to represent the sequential circuits. All the synchronous
sequential circuits (synchronous counters, registers) are knowns as the finite state machine. It has
finite number of internal states. Every FSM has inputs and outputs and finite set of internal states.
In finite state machine, depending on how the output is generated, we have a two FSM models.
i)
Mealy machine
ii)
Moore machine
In the Mealy machine, the output is a function of the present state of the internal memory element
as well as the present inputs.
Page 145 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
First combinational circuit block generates the input for the memory element. According to these
inputs at the next clock edge, the state of the memory element change. So basically, this combinational
logic will decide the next state of the memory element. The input to the combinational block is the
external inputs as well as the present state of the memory element. The present output of this memory
element is going to the output combinational circuit. So this output combinational block will generate
the output of the overall circuit. Now, in the case of Mealy type FSM, the present external inputs will
also be the inputs to this output combinational block. The overall output of the Mealy machine, it is
the function of the present state of the memory element as well as the present input to the circuit.
On the other hand, in the Moore machine, the only difference is that, these external inputs are not
connected to this output block. That means, in the Moore type FSM, the output is the function of only
the present states of the memory element.
The following sequential circuit is an example of the Moore machine.
Q0
CLK
Q1
CLK
The following sequential circuit is an example of the Mealy machine.
Page 146 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Q0
CLK
Q1
CLK
STATE TRANSITION DIAGRAM
Behaviour of the FSM can be represented in 3 different ways
i)
State transition diagram is the pictorial representation of the behaviour of FSM.
ii)
State table is the tabular representation of the behaviour of FSM.
iii)
State equations is the algebraic representation of the behaviour of FSM.
In state diagram, each possible output state is represented as circle. In the following example, the four
possible states are represented in the circle and each state is assigned the specific value – may be with
characters or binary values.
Transition from one state to another state is represented by arrows. The value on the arrow indicates
the input which leads to the state transition. The value next to the input represents the output for that
input.
The generic Mealy model is shown below:
Input
Output
Input
Output
Input
Output
Input
Output
Page 147 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
In the following example, if the circuit is in 00 state and if we apply 1 as an input, then the output of
the circuit will become 0 and it will go into the state 01 state. If we apply 0 as an input, then the output
of the circuit will become 1 and it remain in the same state 00. From the state diagram, we can
understand the number of inputs and outputs, as well as the number of states of the finite state
machine. It also shows that how the change in the input leads to the state transition and the change in
the output. So this state diagram is a diagram of the Mealy machine where the output is a function of
both the present states and the input.
1
0
1
0
0
1
1
1
0
0
0
1
0
0
1
1
The state table for the above Mealy machine is shown below.
Present State
Input
Next State
Q1
Q0
X
Q1*
Q0*
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
Output
Y
1
0
1
0
0
1
0
1
In Moore machine, the output is a function of only the present state of the memory elements. Hence,
in Moore machines, the output is represented in the circle itself.
The generic Moore model is shown below:
State
Output
State
Output
In the example shown below, if the circuit is in 00 state and if the current input is 0, then the circuit
will remain in the same state. It means the next state will be equal to 00. In the 00 state, the output Y
will be equal to 1. Similarly, in the same state, if the input is equal to 1, then the next state will be
equal to 01 and the corresponding output will be equal to 1. From the state diagram, we can easily
draw the state table.
Page 148 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
00
1
01
1
10
0
11
0
The state table for the above Moore machine is shown below.
Present State
Input
Next State
Q1
Q0
X
Q1*
Q0*
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
Output
Y
1
1
1
1
0
0
0
0
Design and implement a logic circuit to obtain the following state transition diagram.
Present States
Q1
Q0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
00
0
01
0
11
1
10
0
Input
X
0
1
0
1
0
1
0
1
Next States
Q1 *
Q0 *
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
FF Inputs
D1
D0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
Output
Z
0
0
0
0
0
0
1
1
Page 149 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
D0  X (Q1  Q0 )
D1  X (Q1  Q0 )
Q1
Q1
Q0
Q0
Design and implement a logic circuit to obtain the following state transition diagram.
1
0
0
0
0
0
0
0
1
0
Next States
Q1 *
Q0 *
0
0
0
1
0
0
1
0
0
0
FF Inputs
D1
D0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
Present States
Q1
Q0
0
0
0
0
0
1
0
1
1
0
1
0
Input
X
0
1
0
1
0
Output
Z
0
0
0
0
0
Page 150 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
1
1
1
0
1
1
1
0
1
1
0
1
D1  X (Q1  Q0 )
1
0
1
1
0
1
1
0
1
0
0
1
D0  X (Q1  Q0 )
Q1
Q1
Q0
Q0
PROGRAMMABLE LOGIC DEVICES (PLD)
An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to
perform different functions is called a Programmable Logic Device (PLD).
The internal logic gates and/or connections of PLDs can be changed/configured by a programming
process.
PLDs are typically built with an array of AND gates (AND-array) and an array of OR gates (ORarray).
Different types of standard PLDs are PROM (Programmable Read Only Memory), PLA
(Programmable Logic Array), PAL (Programmable Array Logic) and FPGA (Field Programmable
Gate Array).
A typical PLD may have hundreds to millions of gates.
PLA and PAL are types of Programmable Logic Devices (PLD) which are used to design
combinational logic together with sequential logic. The significant difference between the PLA and
Page 151 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
PAL is that the PLA consists of the programmable array of AND and OR gates while PAL has the
programmable array of AND but a fixed array of OR gate. PLD’s provides a more simple and flexible
way of designing the logic circuits where the number of functions can also be increased.
BASIS
PLA
PAL
Stands for
Programmable Logic Array
Programmable Array Logic
Construction
Programmable array of AND and
OR gates.
Programmable array of AND gates and
fixed array of OR gates.
Availability
Less prolific
More readily available
Flexibility
Provides more programming
flexibility.
Offers less flexibility, but more likely used.
Cost
Expensive
Intermediate cost
Number of
functions
Large number of functions can be Provides the limited number of functions.
implemented.
Speed
Slow
High
Applications of PLA
There are various applications of PLA. Some main applications of PLA are as follows:
1. It is utilized as a counter.
2. It is utilized as a decoder.
3. It is utilized to give control over the datapath.
4. It is utilized as a BUS interface in programming Input/Output.
Implement the Boolean expressions Y1  AB  AC and Y2  BC  AC using PLA.
Ans:PLA has programmable AND array and programmable OR array.
Page 152 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
AB
AC
Y1  AB  AC
BC
AC
Y2  BC  AC
Implement the Boolean expressions Y1  AB  AC and Y2  BC  AC using PAL.
Ans:PAL has programmable AND array and fixed OR array.
AB
AC
BC
AC
Y1  AB  AC
Y2  BC  AC
Page 153 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
AB
AC
Y1  AB  AC
BC
AC
Y2  BC  AC
Implement a full adder using PLA.
Ans:-
A
0
0
0
0
1
1
1
1
Inputs
B
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
Outputs
S
Cout
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
S  ABCin  ABC in  ABC in  ABCin
Cout  AB  ACin  BCin
The sum (S) of the full-adder is the XOR of A, B, and C in.
Page 154 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
ABCin
ABC in
ABC in
ABCin
AB
BCin
ACin
A combinational circuit is defined by the function F1= ∑ m (3,5,7), F2 = ∑ m (4,5,7). Implement
the circuit using a PLA which consists of 3 inputs (A, B and C), 3 product terms and two outputs.
Ans:Inputs
Outputs
A
B
C
F1
F2
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
F1  BC  AC
F2  AB  AC
Page 155 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
AC
BC
F1  AC  BC
AB
F2  AB  AC
ANALOG TO DIGITAL CONVERSION
An Analog to Digital Converter (ADC) converts an analog signal into a digital signal.
SUCCESSIVE APPROXIMATION ADC
This ADC technique most frequently includes general applications. A successive approximation
type ADC produces a digital output, which is approximately equal to the analog input by using
successive approximation technique internally.
The ADC comprises a sample & hold circuit (S/H), a comparator, a digital-to-analog converter
(DAC), a successive approximation register (SAR), and a control circuit. The schematic is shown
below:
The sample and hold (S/H) circuit samples the input analog signal and holds (freezes) its value at a
constant level for a specified minimum period of time. This sampled signal is compared with the
output signal of the digital-to-analog converter (DAC).
The output of SAR is converted to analog output by the DAC and this analog output is compared with
the input analog sampled value in the Op-Amp comparator. This Op-Amp provides a high or low
pulse based on the difference through the logic circuit.
The MSB is initially set to 1 with the remaining two bits set as 00. Output of SAR will be 100. The
digital equivalent voltage VDAC is compared with the analog input voltage Vin. If the analog input
Page 156 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
voltage is higher than the digital equivalent voltage, the MSB is retained as 1 and the second MSB is
set to 1 (ie. SAR output = 110). Otherwise, the MSB is set to 0 and the second MSB is set to 1 (ie
SAR output = 010).
D D D 
Note: VDAC  Vref  2  1  0 
4
8 
 2
As an example, consider Vin = 5V and Vref = 8V.
Initially, SAR output is 100.
D D D 
1 0 0
VDAC  Vref  2  1  0   8       4V
4
8 
2 4 8
 2
Since Vin > VDAC, second most significant bit is set to 1. Hence, SAR output will be 110.
1 1 0
Now, VDAC  8       6V
2 4 8
Since Vin < VDAC, SAR output will change to 101.
1 0 1
VDAC  8       5V
2 4 8
Conversion Time (Tc)
It is the time when an analog-to-digital converter needs to completely convert continuous signals to
digital signals. The basis of the conversion time is the number of bits, because the N number of bits
takes the N number of clock cycles. Each bit iteration takes one cycle. So, the general conversion
time formula is:
Tc  N  TCLK
The conversion time is independent of the input voltage, which is not the case in the majority of the
other ADCs.
Advantages:
1. High Accuracy
2. Low power consumption
3. Easy to use
Page 157 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
4. Low conversion time
5. Conversion time is independent of the analog input signal.
Disadvantages:
1. Circuit is complex
BINARY WEIGHTED RESISTOR DAC
DAC converts digital input into analog output. Here, digital bits are applied as input and at the output
according to the applied digital inputs, we will get the analog output. In addition to the input and
output, a reference voltage is also applied to the DAC. This reference voltage may be generated
internally or externally. The reference voltage decides the maximum output voltage which is possible
for the given DAC.
The resolution of an ADC is given by the number of bits. It depicts the number of output levels a
DAC can generate. The general formula for resolution is:
 2N
where N represents the number of bits. For a 4-bit DAC, the resolution will be 16.
Step Size
It is the smallest change that a DAC can produce in the output, or we can say that it is a difference
between two consecutive voltage levels of the DAC. It is determined by dividing the reference voltage
by 2, with power equivalent to the number of bits.
Vref
 N
2
SPECIFICATIONS OF DAC
The D/A converters are available in the form of ICs with different specifications for their
performances. These specifications include: 1. Resolution 2. Accuracy 3. Monotonicity 4. Settling
time
1
Resolution
2
Accuracy
SPECIFICATIONS OF DAC
It is defined by the smallest possible change in the analog output voltage
as a fraction of the full-scale output range.
V
Resolution  n FS where VFS = Full scale analog output voltage and n is
2 1
the number of bits.
If an 8-bit DAC is considered for an example, there are 28 or 256 possible
values of output analog voltage. Hence the smallest change in the output
voltage is 1/255th of full-scale output voltage.
Accuracy indicates the deviation of actual output from the expected
output.
Page 158 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
3
Linearity
4
Temperature
Sensitivity
5
Settling time
6
Speed
7
Monotonicity
Accuracy depends on the accuracy of the resistor used in the ladder, and
the precision of the reference voltage used.
The relation between the digital input and analog output should be linear.
However, practically it is not so due to the error in the values of the resistor
used for the resistive network.
The analog output voltage of the Digital to Analog converter should not
change due to changes in temperature. But practically the analog output is
a function of temperature. It is so because the resistance values and OpAmp parameters change with changes in temperature.
Theoretically, the analog output voltage should change instantaneously in
response to the change in its digital input.
Practically the analog output of the Digital to Analog converter does not
change instantaneously. Due to the resistor and Op-Amp in the circuits,
oscillations are observed at the output.
The time required to settle the analog output within 1/2 LSB of the final
value after the change in digital input is called settling time. The settling
time should be as short as possible.
It is defined as the time needed to perform a conversion from digital to
analog. It is also defined as the number of conversions that can be
performed per second. The speed of DAC should be as high as possible.
A monotonic DAC is the one whose analog output increases for an
increase in digital input. A monotonic characteristic is essential in control
applications, otherwise oscillations can result. If a DAC has to be
monotonic, the error should be less than ±(1/2) LSB at each output level.
BINARY WEIGHTED RESISTOR DAC
The binary-weighted-resistor DAC employs the characteristics of the inverting adder Op Amp circuit.
In this type of DAC, the output voltage is the inverted sum of all the input voltages. If the input
resistor values are set to multiples of two: 1R, 2R and 4R, the output voltage would be equal to the
sum of V1, V2/2 and V3/4. V1 corresponds to the most significant bit (MSB) while V3 corresponds to
the least significant bit (LSB).
The circuit for a 4-bit DAC using binary weighted resistor network is shown below:
Page 159 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
The binary inputs, bi (where i = 1, 2, 3 and 4) have values of either 0 or 1. The value, 0, represents an
open switch while 1 represents a closed switch.
The operational amplifier is used as a summing amplifier, which gives a weighted sum of the binary
input based on the voltage, Vref. For a 4-bit DAC, the relationship between Vout and the binary input
is as follows:
V R b b b 
Vout   ref f  2  1  0 
R 2 4 8
b2
b1
b0
Vout
0
0
0
0
0
0
1
Vref / 8
0
1
0
2Vref / 8
0
1
1
3Vref / 8
1
0
0
4Vref / 8
1
0
1
5Vref / 8
1
1
0
6Vref / 8
1
1
1
7Vref / 8
FLASH TYPE ADC
Flash Type ADC is based on the principle of comparing analog input voltage with a set of reference
voltages.
An N-bit flash ADC consists of 2N-1 comparators, 2N numbers of matched resistors, and a priority
encoder.
Resistor Voltage Divider Circuit
The resistive voltage divider is a simple circuit network of resistors that scales down an input voltage
connected to it.
Page 160 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
Comparator
The comparator is a basic operational amplifier that compares two analog voltages V in and Vref. Its
output is in the form of a binary signal. The input voltage connects to the positive end, while the other
voltage, or reference voltage, connects to the negative end of the comparator.
If Vin > Vref, output will be 1 and if Vin < Vref, output will be 0.
Priority Encoder
An encoder is a logic circuit that comes with 2N inputs. It gives the binary code with respect to the
corresponding high input. It produces errors if more than one input is in the high state. So, to counter
this problem, the flash ADC uses a priority encoder. The priority encoder does not produce ambiguous
results even if two or more inputs are in a high state simultaneously. Instead, it delivers the binary
code on a priority basis. The priority mechanism can either be ascending or descending.
Let’s consider N inputs, with the Nth input being the highest priority input. If three inputs, i.e., N-1,
4, and 2, are high at the same time, then the priority encoder will generate a binary code corresponding
to the N-1 input line.
Consider a 3-bit flash type ADC. This consists of seven comparators, a resistive voltage divider
circuit that contains eight series resistors, and a priority encoder. We apply the input analog voltage
to the positive terminal of the comparator and the reference voltage to the negative end of the
comparator.
V1 
Vref R
8R

Vref
8
Page 161 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
V2 
Vref  2 R
8R

Vref
4
Reference Voltage
V1
Vref / 8
V2
2Vref / 8
V3
3Vref / 8
V4
4Vref / 8
V5
5Vref / 8
V6
6Vref / 8
V7
7Vref / 8
These reference voltages of each comparator reveal that there is a difference of one least significant
bit among each of the reference voltages.
1 LSB = Vref / 8
Each comparator compares the input voltage to the reference voltage accordingly. Here are two cases:
If the input voltage is less than the reference voltage of the comparator, then the output of the
comparator is low. Whereas if the input voltage is greater than the reference voltage of the particular
comparator, then its output will be high.
The priority encoder is dependent on these comparators. The outputs of the comparators determine
the binary code produced by the encoder.
To completely comprehend the working of the flash ADC, we take an example reference and input
voltage, i.e., Vref = 8 V and Vin = 3.3 V, respectively. Then,
Reference Voltage
V1
Vref / 8 = 1
V2
2
V3
3
V4
4
V5
5
V6
6
V7
7
The analog input voltage is compared with all the comparator’s reference voltages of the Flash analog
to digital converter. After comparison, we notice that the reference voltages of the first three
comparators, i.e., 1 V, 2 V, and 3 V, are less than the 3.3 V input. That is why the output of the first
three comparators is high while the remaining comparators are in a low state.
The outputs of these comparators become the inputs of the priority encoder. Here, the encoder is a
descending-order priority encoder. As three input lines of the encoder are high at the same time,
priority will be given to the highest value which is 3, and a corresponding output binary code (011)
is generated.
Sample & Hold Circuit
This is the process through which a flash analog-to-digital converter takes a continuous analog input
and converts it into a binary output. For this ADC to be accurate, the input voltage must not vary;
Page 162 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
otherwise, it affects the output and produces errors. To tackle this, the flash ADC is used in
combination with a sample and hold circuit. The respective circuit samples the input circuit and holds
that sample circuit until the conversion is complete and the next signal arrives.
R – 2R LADDER NETWORK
The following diagram shows the R-2R 3-bit ladder DAC. The leftmost side of the circuitry has the
least significant bit, i.e., b0, whereas b2, which is the most significant bit, connects to the amplifier.
The binary inputs are given through the binary switches. So, when we need a high bit, simply connect
the relevant bit to the reference voltage, and when we require a low bit, the switch connects to the
ground potential.
For the R – 2R ladder network, determine the Thevenin’s equivalent voltage V TH and resistance
RTH when a) V0 = V, V1 = 0, V2 = 0 b) V0 = 0, V1 = 1, V2 = 0 c) V0 = 1, V1 = 1, V2 = 0 and d) V0
= 0, V1 = 0, V2 = V.
Ans:RTH in all cases:
Step 1: 2Ω // 2Ω  Req = 1Ω
Step 2: 1Ω & 1Ω in series  Req = 2Ω
Step 3: 2Ω // 2Ω  Req = 1Ω
Step 4: 1Ω & 1Ω in series  Req = 2Ω
Step 5: 2Ω // 2Ω  Req = 1Ω
RTH = 1Ω
Page 163 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
VTH in different cases:
Case 1 (001)
 2 1 0  VA   0.5V 
 1 2.5 1 V    0 

 B 

 0 1 1.5  VC   0 
2 1 0
  1 2.5 1  2(2.5 1.5  1)  1( 1 1.5)  4
0 1 1.5
2 1 0.5V
1 2.5 0
0 1 0
0.5V 1 V



4
8
Case 2 (010)
 2 1 0  VA   0 
 1 2.5 1 V    0.5V 

 B 

 0 1 1.5  VC   0 
VC 
2 1 0
1 2.5 0.5V
VC 
0 1 0


0.5V  2 2V

4
8
Case 3 (011)
Page 164 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
 2 1 0  VA   0.5V 
 1 2.5 1 V    0.5V 

 B 

 0 1 1.5  VC   0 
2 1 0.5V
1 2.5 0.5V
0 1 0
0.5V 1  0.5V  2 3V



4
8
Case 4 (100)
 2 1 0  VA   0 
 1 2.5 1 V    0 

 B 

 0 1 1.5  VC   0.5V 
VC 
2 1 0
1 2.5 0
VC 
0 1 0.5V


0.5V (5  1) 4V

4
8
b2
b1
b0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
VTH
Vref

8R
2Vref

8R
3V
 ref
8R
4V
 ref
8R
5V
 ref
8R
6V
 ref
8R
7V
 ref
8R







VOUT
R f Vref
R 8
R f 2Vref
R 8
R f 3Vref
R 8
R f 4Vref
R 8
R f 5Vref
R 8
R f 6Vref
R 8
R f 7Vref
R
8
Page 165 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
For example, if Rf = R, Vref = -8V,
b2
0
0
0
1
1
1
1
b1
0
1
1
0
0
1
1
b0
1
0
1
0
1
0
1
VOUT
1
2
3
4
5
6
7
Comparison of Weighted Resistor DAC and R-2R Ladder DAC
Sl.No. Parameter
Weighted Resistor DAC
R-2R Ladder DAC
1
Simplicity
Simple
Slightly complicated
2
Range of resistor values
A wide range is required
Resistors of only two
values are required
3
Number of resistors per bit
One
Two
4
Ease of expansion
Not easy to expand for more
bits
Easy to expand
1
Resolution
2
Quantization
error
3
Conversion
time
SPECIFICATIONS OF ADC
Resolution can also be defined as the ratio of change in the value of input
voltage Vi, needed to change the digital output by 1 LSB.
V
Resolution  n FS where VFS = Full scale analog input voltage and n is
2 1
the number of bits.
The digital output is not always an accurate representation of the analog
input. For example, any input voltage between 1/8 and 2/8 of full scale
will be converted to a digital word of “001”. This approximation process
is called quantization and the error due to quantization is called
quantization error.
The maximum value of quantization error is ±1/2 LSB.
VFS
QE 
2(2 n  1)
The quantization error should be as small as possible. It can be reduced by
increasing the number of bits.
It is defined as the total time required for an A/D converter to convert an
analog signal to digital output. It depends on the conversion technique and
propagation delay of the circuit components.
Page 166 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
FPGA
FPGA stands for Field Programmable Gate Array which is an IC that can be programmed to
perform a customized operation for a specific application. They have thousands of gates. Languages
such as VHDL and Verilog are used to write the code for FPGA programming.
Architecture
It consists of thousands of fundamental elements called Configurable Logic Blocks (CLBs) which
are surrounded by a system of programmable interconnects known as a fabric, which directs signal
between CLBs and I/O blocks interface between the FPGA and external device.
Logic Block consists of Multiplexers, Full Adders, D flip flop, a lookup table (LUT) which is the
basic building block of the FPGA. LUTs determines the output for any given source of input. LUTs
with 4-6 input bits are widely used and can even go up to 8 bits after experiments. D flip flop stores
the output of LUT.
Advantages:
 FPGAs provide better performance than a general CPU as they are capable of handling
parallel processing.
 FPGAs are reprogrammable.
 They are cost-efficient.
 FPGAs allow to finish the development of the product in a very short time, so they are
available in the market in a shorter time.
Disadvantages:
 They have high power consumption and programmers do not have any control over power
optimization.
 The programming of FPGA is not as simple as C programming.
 They are only used where the production volume is low.
Applications of FPGA
Image processing in SDRs
Defence equipment
ASIC prototyping
Wireless communications like WCDMA, WiMAX, etc.
High-performance computers
Different equipment used for diagnosis
Equipment used in therapy
Consumer electronics
Residential set-top boxes, etc.
Flat-panel displays
VHDL
VHDL stands for Very High-Speed Integration Circuit Hardware Description Language. It is an
IEEE standard hardware description language that is used to describe and simulate the behavior of
complex digital circuits.
VHDL Program Structure
Page 167 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT

All the VHDL programs consist of at least two components: Entity and Architecture

It may have additional components like configuration, package declaration, body, etc. as per
requirements
The structure of the VHDL program is like:
LIBRARY library_name;
USE library_name.package_name.pacakage_parts;
ENTITY entity_name IS
PORT (port_name : port mode port_type;
port_name : port_mode port_type;
port_name : port_mode port_type;
.
.
.
);
ARCHITECTURE archi_name OF entity_name IS
declarations
BEGIN
code (sequential or concurrent statements)
.
.
.
END archi_name;
Library declaration:
The library contains all the piece of code that is used frequently. It will allow us to reuse them again
and again. Also, this can be shared with other designs
It starts with keyword LIBRARY followed by library name
There are three libraries usually used in all VHDL codes

IEEE – specifies multilevel logic system

std – resource library for VHDL design environment

work – used for saving our project work and program file (.vhd)
However, in program code, we need to declare only the IEEE library because the other two libraries
are default libraries
Now to add library packages and its part USE keyword is used with library name, library packages,
and package parts. For example in the IEEE library, the package is std_logic_1164 and to add all its
part we can write
LIBRARY ieee
USE ieee.std_logic_1164.all
Page 168 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
So all VHDL programs start with above two statements for library declaration
Entity declaration:
Entity defines input-output connections of the digital circuit with which it can interact with other
components/circuits
It declares the number of inputs given to the circuit and the number of outputs taken out form the
circuit.
Also, it declares any intermediate signals that are used within the circuit itself.
Entity declaration starts with the keyword ENTITY. The user has to give desire name to entity often
related to a circuit that is being designed like ‘mux,’ ‘decoder,’ ‘adder,’ ‘counter’ etc. (the rule of
thumb for any VHDL program is the program file name must be same as entity name)
Inside entity, input-output pins of a circuit are declared using keyword PORT
PORT (means interfacing pins) are declared with port_name, port_mode, and port_type
port_name – it’s a user-defined name of the input-output pin
port_mode – there are four types of port mode IN, OUT, INOUT and BUFFER. IN indicates an input
pin, that can be read-only. OUT indicates an output pin and its write-only. Both these pins are
unidirectional. INOUT pin is bidirectional that can be read as well as write. BUFFER is used for the
intermediate output
port_type – it can be BIT, BIT_VECTOR, STD_LOGIC, etc
After declaring all interfaces, the entity declaration ends with keyword END followed by entity name
Let us see an entity example for two-input AND gate.
ENTITY and_gate IS
PORT (A, B : IN BIT;
Y : OUT BIT);
END and_gate;
Similarly, we can write an entity for half adder as
ENTITY half_adder IS
PORT (A, B : IN BIT;
S, C : OUT BIT);
END half_adder;
Architecture:
Architecture declares the functionalities of the digital circuit
It gives internal details of an entity that means how input-output are interconnected
Page 169 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
It describes behaviour of the circuit means how the circuit generates required output from given inputs
The architecture declaration starts with keyword ARCHITECTURE followed by architecture_name
and entity_name
The BEGIN keyword indicates the starting of the architecture body. The body includes sequential or
concurrent statements that describe circuit functionality
The architecture body ends with keyword END followed by architecture_name
Here is the architecture of 2 input AND gate (the entity is as given above).
ARCHITECTURE and_gate_arch OF and_gate IS
BEGIN
Y<= A and B;
END and_gate_arch;
Similarly, let us write architecture for half adder
ARCHITECTURE half_adder_arch OF half_adder IS
BEGIN
S <= A xor B;
C <= A and B;
END half_adder_arch;
There are three different modelling styles for architecture body

Data flow style – in this modelling style the circuit is described using concurrent
statements

Behavioral style – in this modelling style the circuit is described using sequential
statements

Structural style – in this modelling style the circuit is described using different
interconnected components
VHDL program – OR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OR_gate is
port ( A, B : in STD_LOGIC;
Y : out STD_LOGIC);
end OR_gate;
architecture OR_gate_arch of OR_gate is
begin
Y <= A or B;
end OR_gate_arch;
Page 170 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
VHDL program – AND
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_gate is
port ( A, B : in STD_LOGIC;
Y : out STD_LOGIC);
end AND_gate;
architecture AND_gate_arch of AND_gate is
begin
Y <= A and B;
end AND_gate_arch;
VHDL program – HALF ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
port (A, B : in STD_LOGIC;
S, C : out STD_LOGIC);
end half_adder;
architecture half_adder_arch of half_adder is
begin
S <= A xor B;
C <= A and B;
end half_adder_arch;
VHDL program – FULL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
port ( A, B, Cin : in STD_LOGIC;
S, Cout : out STD_LOGIC);
end full_adder;
architecture full_adder_arch of full_adder is
begin
sum <= A xor B xor Cin;
cout <= (A and B) or (B and Cin) or (A and Cin);
end full_adder_arch;
Page 171 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
VERILOG
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital
system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any
digital hardware by using HDL at any level.
Verilog code for OR gate
module or_gate ( o, a, b );
input a, b;
output o;
assign o = a | b;
endmodule
Verilog code for AND gate
module and_gate ( o, a, b );
input a, b;
output o;
and g1(o, a, b);
endmodule
Verilog code for Half Adder
module half_adder ( carry, sum, a, b );
input a, b;
output sum, carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
Verilog code for Full Adder
module full_adder ( c_out, sum, a, b, c_in );
input a, b, c_in;
output sum, c_out;
assign sum = a ^ b ^ c_in;
assign c_out = (a & b) | (b & c_in) | (a & c_in);
endmodule
Page 172 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
B.Tech Degree S4 (S,FE) / S2 (PT) (S) Examination January 2024 (2019 scheme)
Course Code: EET206
Course Name: DIGITAL ELECTRONICS
Max. Marks: 100
Duration: 3 Hours
Qn.No.
Part A
Marks
Answer all questions; each question carries 3 marks
1
Implement NOT circuit using a two input EX-OR gate.
3
2
Subtract decimal number 22 from 17 using 8-bit 2’s complement method.
3
3
Using the Boolean laws and rules, simplify the logic expression
3
Z  ( A  B )( A  B)
4
Convert the following function into standard POS and express as maxterms
3
Y ( A, B, C )  ( A  B )( B  C )( A  C ) .
5
6
7
8
9
10
11 a)
b)
12 a)
b)
13 a)
b)
Draw the circuit for a 4 x 1 MUX and explain operation.
Draw the circuit to Decimal to BCD encoder circuit and explain.
Determine the number of flip-flops needed to construct a register capable of
storing (i) a 6 bit binary number (ii) hexadecimal numbers upto F (iii) octal
numbers upto 10.
Draw the circuit and timing diagram for a 2 bit ripple counter using D flip flop.
Draw the circuit of flash ADC and explain.
Write the structural mode of three input AND gate in Verilog HDL.
Part B
(Answer one full question from each module, each question carries 14
marks)
Module 1
Convert the following
a) (1001011)gray = ( )2
b) (10110110.0011)2 = ( )BCD
c) (5762)8 = ( )16
d) (76)10 = ( )gray
e) Attach the proper even parity bit to 10100100 and odd parity bit to
11111000.
Convert the decimal number 3.248 x 104 to a single precision floating point
binary number.
With example explain any to representations for signed binary numbers.
Explain the working of TTL NAND gate with the help of internal diagram.
Module 2
Using k-map determine the minimal sum of product expression and realize the
simplified expression using only NAND gates
f ( w, x, y, z ))   M (0, 2,3, 7,8,9,10)
Show that a full adder can be constructed with two half adders and an OR gate.
3
3
3
3
3
3
10
4
4
10
10
4
Page 173 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
14 a)
Use a K-map to simplify AC  B  B( B  C )  to a minimum SOP form.
4
b)
Realize a 4 bit look ahead carry adder. What is the advantage over a ripple
adder?
Module 3
10
15 a)
Implement the Boolean function F ( A, B, C , D )   m(1,3, 4,11,12,13,14,15)
7
b)
16 a)
b)
17 a)
b)
18 a)
b)
19 a)
b)
20 a)
b)
using 8:1 multiplexer.
Design and draw implementation circuit for an odd parity generator circuit for
4 bit binary data.
Design two bit comparator using decoder.
Draw the implementation circuit of a 1:8 Demultiplexer using two 1:4
demultiplexers.
Module 4
Illustrate the conversion of (a) a J-K flip-flop into a D flip-flop and (b) a J-K
flip-flop into a T flip-flop. Explain.
Show how an asynchronous counter with J-K flip-flops can be implemented
having a modulus of twelve with a straight binary sequence from 0000
through1011. Also draw the timing diagram.
Design a counter to produce the following binary sequence.
1,4,3,5,7,6,2,1,….
Use J-K flip-flops.
Draw the circuit and timing diagrams of a 3 bit SISO shift register.
Module 5
Explain the working of successive approximation ADC with the help of an
example.
Differentiate Moore and Mealy state machines.
Explain the working of R-2R ladder type DAC with the help of an example.
What is its advantage over weighted resistor type DAC?
Compare PAL and PLA with their logic implementation.
***
7
8
6
4
10
10
4
10
4
10
4
Page 174 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
B.Tech Degree S4 (R,S) / S2 (PT) (R,S) Examination June 2023 (2019 scheme)
Course Code: EET206
Course Name: DIGITAL ELECTRONICS
Max. Marks: 100
Duration: 3 Hours
Qn.No.
Part A
Marks
Answer all questions; each question carries 3 marks
1
Convert l0l10010 to hexadecimal and Octal
3
2
Draw the truth table and explain the operation of EX-OR and EX-NOR gates
3
3
3
Get the dual of the expression AB  AC  ABC ( AB  C )  1 .
4
5
6
7
8
9
10
11 a)
b)
12 a)
b)
13 a)
b)
Derive the expression for sum and carry of a full adder.
Explain a 2-bit comparator.
Draw the circuit of a 1 to 4 Demultiplexer and explain.
Explain the truth table and excitation table of a JK flip flop.
What are the asynchronous inputs of a flip flop? Why are they called so?
Draw the state diagram of a 3-bit binary down counter.
What is FPGA?
Part B
(Answer one full question from each module, each question carries 14
marks)
Module 1
Perform the following (i) 165.87510 to binary (ii) 4BAC16 to binary (iii) 37810
to octal.
What are universal gates. Why are they called so?
With the help of a neat diagram explain CMOS NAND gate.
Describe error detection and correction using parity checking.
Module 2
Design and set up a half adder/subtractor circuit with mode control.
Obtain
the
simplified
POS
expression
using
Kmap
Y   m(1,3, 7,11,15)  d (0, 2, 4)
3
3
3
3
3
3
3
7
7
7
7
7
7
14 a)
b)
Using a neat circuit explain a 3 bit carry look ahead adder.
Write and explain any five basic laws of Boolean algebra.
Module 3
9
5
15 a)
Implement f ( x, y, z )   m(1, 2, 6, 7) using 4 x 1 MUX.
7
b)
16 a)
b)
Explain a 3 to 8 decoder
Design and set up a Binary to BCD converter circuit
How is priority encoder different from encoder?
Module 4
Draw the logic circuit of SR flip flop and explain it.
7
10
4
17 a)
7
Page 175 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
b)
18 a)
b)
19 a)
b)
20 a)
b)
What is modulus of a counter. Draw the circuit of an asynchronous decade
counter.
Enumerate the steps for design of a synchronous counter.
Draw the circuit of 4-bit ring counter and give the timing diagram.
Module 5
Design a 4-bit weighted resistor DAC whose full-scale output voltage is -5V.
The logic levels are logic 1 = +5 V and logic 0 = 0 V. What is the output voltage
when the input is 1101?
Give the Verilog code for AND gate.
Explain Flash type A/D converter.
Differentiate PAL and PLA.
***
7
7
7
10
4
10
4
Page 176 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
Fourth Semester B.Tech Degree Examination June 2022 (2019 scheme)
Course Code: EET206
Course Name: DIGITAL ELECTRONICS
Max. Marks: 100
Duration: 3 Hours
Qn.No.
Part A
Marks
Answer all questions; each question carries 3 marks
1
Perform the addition 3716 + 2916.
3
2
Using 2's complement method, perform the additions:
3
a) 21 – 42
b) -46 – 25
3
Using Boolean algebra techniques, simplify the expression
3
BD  B ( D  E )  D ( D  F ) .
4
Convert the expression ( A  B )(C  B ) to standard SOP form.
3
5
What are select lines and what is its importance in the case of multiplexers and
demultiplexers, explain with example.
Design full adder circuit with decoder IC.
What is the difference between J-K flipflop and S-R flipflop, Explain with truth
table and logic implementation?
With respect to circuit what is the difference between a ring counter and a
Johnson counter?
Differentiate between Moore and Mealy machines.
State the applications of FPGA.
Part B
(Answer one full question from each module, each question carries 14
marks)
Module 1
Draw and explain the circuit for CMOS NOR gate.
What are the parameters significant to the logic families. Explain any three and
compare TTL and CMOS logic on these parameters.
Convert the following numbers:
a) (1010110110111)2 = ( )16
b) (0.4D8)16 = ( )2
c) (214)10 = ( )16
d) (101011011011)2 = ( )8
e) (0.725)8 = ( )2
f) (9264)10 = ( )8
g) (467)8 = ( )16
Module 2
3
6
7
8
9
10
11
12
13 a)
b)
Convert the SOP expression AB  AB  AC D to standard SOP form.
State and explain De Morgans theorem.
3
3
3
3
3
14
14
5
4
Page 177 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
c)
Apply De Morgans theorem to the expression ABC  ( D  E ) .
5
14
Explain a look ahead carry generator with relevant expressions and circuit and
give reason for its high speed of operation.
Module 3
14
15
Implement the Boolean function F ( A, B, C , D )   (1, 3, 4,11,12,13,15) using
14
16 a)
b)
17 a)
b)
18
19 a)
b)
20
8:l MUX and external gates.
Explain the operation of a 2-bit magnitude comparator.
Write the applications of a multiplexer and describe the implementation of a
three variable function using multiplexer with a suitable example.
Module 4
What is Race-Around condition of J-K Flip-Flop? Suggest a method to avoid
Race-Around condition of J-K Flip-Flop.
Design and implement a J- K flip flop using D flipflop
What is modulus of a counter and design a synchronous MOD-5 counter with
state diagram and relevant truth tables.
Module 5
What are the important specifications of a A/D converter?
Why a weighted resistor type D/A converter is called so? Draw the schematic
and explain.
Implement a full adder using Verilog
***
7
7
7
7
14
7
7
14
Page 178 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
Fourth Semester B.Tech Degree Examination July 2021 (2019 scheme)
Course Code: EET206
Course Name: DIGITAL ELECTRONICS
Max. Marks: 100
Duration: 3 Hours
Qn.No.
Part A
Marks
Answer all questions; each question carries 3 marks
1
Convert
3
a) (7483)10 into hexadecimal
b) 1 1001 0100 into Gray Code
2
Realize NOT, AND and OR gate using NAND gates only.
3
3
State and explain De Morgan's theorem
3
4
3
Prove that A  AB  A  B .
5
6
7
8
9
10
11 a)
b)
12 a)
b)
13 a)
b)
14 a)
b)
Draw a 4-bit gray to binary code converter circuit.
Draw the block diagram of ALU.
Explain Preset and Clear inputs of a flip-flop.
Draw the logic diagram of a 4 bit Johnson counter and explain its working.
Draw and explain R-2R ladder type DAC.
Differentiate between PLA and PAL.
Part B
(Answer one full question from each module, each question carries 14
marks)
Module 1
Subtract 46 from 99 using 1's complement and 2's complement methods.
Compare both methods.
Draw and Explain TTL NAND gate implementation.
With neat diagram, explain the operation of CMOS NOR gate.
Explain the error detection using parity method in digital transmission. Discuss
how odd parity error detection carried out for transmitting the letter 'B' in ASCII
code.
Module 2
Design a full subtractor circuit using basic gates.
Reduce the expression using K map,
F ( A, B, C , D )   m(6, 7,8,10,11,15)  d (0, 2,3, 4, 5,9,14) .
3
3
3
3
3
3
Draw and explain 4-bit parallel adder/subtractor circuit.
6
8
Express F ( A, B, C , D)  A  BC  C  AC in standard SOP and POS forms.
7
7
7
7
7
7
Module 3
15 a)
b)
Realize a 2-bit comparator circuit.
Implement the function F ( A, B, C , D )   m(0, 2, 4, 7,9,14) using 4 x 1 MUX.
8
6
Page 179 of 180
EET206 Digital Electronics Lecture Notes by T.G. Sanish Kumar, EED, GECT
16 a)
b)
17 a)
b)
18 a)
b)
19 a)
b)
Differentiate decoder and encoder. Design a BCD to decimal decoder circuit.
Design an even parity generator circuit for 3-bit messages.
Module 4
Design a mod-12 asynchronous counter using J-K flip flops. Draw the timing
diagram.
Explain different types of shift registers.
Design mod-14 synchronous counter using T-flip flop by explaining the steps
in detail.
Convert J-K flip-flop to T flip-flop.
Module 5
Compare Mealy and Moore state machine models with example.
Explain the working of
a) successive approximation ADC and
b) Flash type ADC
8
6
8
6
10
4
6
8
20 a)
Implement the function F ( A, B, C , D )   m(3, 7,8,9,11,15) using PLA.
6
b)
Implement AND gate and a half adder circuit using VHDL
***
8
Page 180 of 180