Digital Circuits
Homework 1
1. Convert the circuit of Fig. 1 to one using only NAND gates. Then write the output expression
for the new circuit, simplify it using DeMorgan’s theorems, and compare it with the expression
for the original circuit.
Fig. 1
2. Convert the circuit of Fig. 2 to one using only NOR gates. Then write the expression for the
new circuit, simplify it using DeMorgan’s theorems, and compare it with the expression for the
original circuit.
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Fig. 2
3. Show how a two-input NOR gate can be constructed from two-input NAND gates.
4. Modify the circuit of Fig. 3 so that A1 = 0 is needed to produce DRIVE = 1 instead of A1 = 1.
Fig. 3
5. Show how x = ABC can be implemented with one two-input NOR and one two-input
NAND gate.
6. Fig. 4 represents a relative-magnitude detector that takes two three-bit binary numbers, x2x1x0 and
y2y1y0 and determines whether they are equal and, if not, which one is larger. There are three
outputs, defined as follows:
1 M = 1 only if the two input numbers are equal.
○
2 N = 1 only if x2x1x0 is greater than y2y1y0.
○
E
A
E
A
A
2
3 P = 1 only if y2y1y0 is greater than x2x1x0.
○
Design the logic circuitry for this detector. The circuit has six inputs and three outputs and is
therefore much too complex to handle using the truth-table approach. Refer to Example 4-17
as a hint to how you might start to solve this problem.
E
A
A
Fig. 4
7. (a) Under what conditions will an OR gate allow a logic signal to pass through to its output
unchanged?
(b) Repeat (a) for an AND gate.
8. (a) A technician testing a logic circuit sees that the output of a particular INVERTER is stuck
LOW while its input is pulsing. List as many possible reasons as you can for this faulty
operation.
(b) Repeat part (a) for the case where the INVERTER output is stuck at an indeterminate logic
level.
9. In Example 4-24, we listed three possible faults for the situation of Fig. 5. What procedure
would you follow to determine which of the faults is the actual one?
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Fig. 5
10. Fig. 6 is a combinational logic circuit that operates an alarm in a car whenever the driver
and/or passenger seats are occupied and the seat belts are not fastened when the car is started.
The active-HIGH signals DRIV and PASS indicate the presence of the driver and passenger,
respectively, and are taken from pressure-actuated switches in the seats. The signal IGN is
active-HIGH when the ignition switch is on. The signal BELTD is active-LOW and indicates
that the driver’s seat belt is unfastened; BELTP is the corresponding signal for the passenger
seat belt. The alarm will be activated (LOW) whenever the car is started and either of the front
seats is occupied and its seat belt is not fastened.
(a) Verify that the circuit will function as described.
(b) Describe how this alarm system would operate if Z1-2 were internally shorted to ground.
(c) Describe how it would operate if there were an open connection from Z2-6 to Z2-10.
Fig. 6
11. In some microcomputers, the MPU can be disabled for short periods of time while another
device controls the RAM, ROM, and I/O. During these intervals a special control signal
( DMA ) is activated by the MPU and is used to disable (deactivate) the device select logic so
that the RAM , ROM , and I / O are all in their inactive state. Modify the circuit of Fig. 7
so that RAM , ROM , and I / O will be deactivated whenever the signal DMA is active,
regardless of the state of the address code.
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Fig. 7
12. In Problem 5-16, we saw how an edge-triggered D flip-flop can be operated in the toggle mode.
Explain why this same idea will not work for a D latch.
Fig. 8
D flip-flop connected to toggle (Problem 5-16)
13. Suppose that the circuit of Fig. 9 is malfunctioning so that data are being transferred to X for
either of the address codes 11111110 or 11111111. What are some circuit faults that could be
causing this?
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Fig. 9
Example of microprocessor transferring binary data to an external register
14. Modify the circuit of Fig. 9 so that the MPU has eight data output lines connected to transfer
eight bits of data to an eight-bit register made up of two 74HC175 ICs [Fig. 10(b)]. Show all
circuit connections.
Fig. 10 (a) A single edge-triggered D flip-flop and
(b) an actual IC (74HC175 quad flip-flop with common clock and clear)
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15. The output pulse width from a 74121 OS is given by the approximate formula
t p ≈ 0.7 RT CT
where RT is the resistance connected between the REXT / C EXT pin and VCC , and CT is the
capacitance connected between the C EXT pin and the REXT / C EXT pin. The value for RT
can be varied between 2 and 40㏀, and CT can be as large as 1000μF.
(a) Show how a 74121 can be connected to produce a negative-going pulse with a 5-ms
duration whenever either of two logic signals (E or F) makes a NGT. Both E and F are
normally in the HIGH state.
(b) Modify the circuit so that a control input signal, G, can disable the OS output pulse
regardless of what occurs at E or F.
16. Convert the FA circuit of Fig. 11 to all NAND gates.
Fig. 11
Complete circuitry for a full adder
17. A full adder can be implemented in many different ways. Fig. 12 shows how one may be
constructed from two half adders. Construct a truth table for this arrangement, and verify that
is operates as a FA.
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Fig. 12
18. Add the necessary logic circuitry to Fig. 13 to accommodate the transfer of data from memory
into the A register. The data values from memory are to enter the A register through its D
inputs on the PGT of the first TRANSFER pulse; the data from the sum outputs of the FAs
will be loaded into A on the PGT of the second TRANSFER. In other words, a LOAD pulse
followed by two TRANSFER pulses is required to perform the complete sequence of loading
the B register from memory, loading the A register from memory, and then transferring their
sum into the A register. (Hint: Use a flip-flop X to control which source of data gets loaded
into the D inputs of the accumulator.)
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Fig. 13 (a) Complete four-bit parallel adder with register;
(b) signals used to add binary numbers from memory and store their sum in the accumulator
19. Add the necessary logic to Fig. 14 to produce a single HIGH output whenever the binary
number at A is exactly the same as the binary number at B. Apply the appropriate select input
code (three codes can be used).
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Fig. 14
74 HC382 ALU chips connected as an eight-bit adder
20. A technician breadboards the adder/subtractor of Fig. 15. During testing, she finds that
whenever an addition is performed, the result is 1 more than expected, and when a subtraction
is performed, the result is 1 less than expected. What is the likely error that the technician made
in connecting this circuit?
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Fig. 15 Parallel adder/subtractor using the 2’s complement system
21. Figure 16 represents a multiplier circuit that takes two-bit binary numbers, x1x0 and y1y0, and
produces an output binary number z3z2z1z0 that is equal to the arithmetic product of the two
input numbers. Design the logic circuit for the multiplier. (Hint: The logic circuit will have four
inputs and four outputs.)
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Fig. 16 Multiplier circuit
22. Figure 17 shows the intersection of a main highway with a secondary access road. Vehicledetection sensors are placed along lanes C and D (main road) and lanes A and B (access road).
These sensor outputs are LOW (0) when no vehicle is present and HIGH (1) when a vehicle is
present. The intersection traffic light is to be controlled according to the following logic:
1. The east-west (E-W) traffic light will be green whenever both lanes C and D are occupied.
2. The E-W light will be green whenever either C or D is occupied but lanes A and B are not
both occupied.
3. The north-south (N-S) light will be green whenever both lanes A and B are occupied but C
and D are not both occupied.
4. The N-S light will also be green when either A or B is occupied while C and D are both
vacant.
5. The E-W light will be green when no vehicles are present.
Using the sensor outputs A, B, C, and D as inputs, design a logic circuit to control the traffic
light. There should be two outputs, N-S and E-W, that go HIGH when the corresponding light
is to be green. Simplify the circuit as much as possible and show all steps.
Fig. 17
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23. When the combination lock of Figure 18 is tested, it is found that entering the correct
combination does not open the lock. A logic probe check shows that entering the correct first
combination sets Q1 HIGH, but entering the correct second combination produces only a
momentary pulse at Q2. Consider each of the following faults and indicate which one(s) could
produce the observed operation. Explain each choice.
(a) Switch bounce at SWA, SWB, or SWC.
(b) CLR input of Q2 is open.
(c) Connection from NAND gate 4 output to NAND gate 3 input is open.
Fig. 18
24. Design a look-ahead carry circuit for the adder of Figure 13 that generates the carry C3 to be
fed to the FA of the MSB position based on the values of A0, B0, C0, A1, B1, A2, and B2. In
other words, derive an expression for C3 in terms of A0, B0, C0, A1, B1, A2, and B2. (Hint: Begin
by writing the expression for C1 in terms of A0, B0, and C0. Then write the expression for C2 in
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terms of A1, B1, and C1. Substitute the expression for C1 into the expression for C2. Then write
the expression for C3 in terms of A2, B2, and C2. Substitute the expression for C2 into the
expression for C3. Simplify the final expression for C3 and put it in sum-of-products form.
Implement the circuit.)
25. In a typical microprocessor ALU, the results of every arithmetic operation are usually (but not
always) transferred to the accumulator register, as in Figures 13 and 15. In most microprocessor
ALUs, the result of each arithmetic operation is also used to control the states of several
special flip-flops called flags. These flags are used by the microprocessor when it is making
decisions during the execution of certain types of instructions. The three most common flags
are:
S(sign flag). This FF is always in the same state as the sign of the last result from the ALU.
Z(zero flag). This flag is set to 1 whenever the result from an ALU operation is exactly 0.
Otherwise, it is cleared to 0.
C(carry flag). This FF is always in the same state as the carry from the MSB of the ALU.
Using the adder/subtractor of Figure 15 as the ALU, design the logic circuit that will
implement these flags. The sum outputs and C4 output are to be used to control what state
each flag will go to upon the occurrence of the TRANSFER pulse. For example, if the sum is
exactly 0 (i.e., 0000), the Z flag should be set by the PGT of TRANSFER; otherwise, it should
be cleared.
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