Topics in IC Design
2.1 Introduction to Phase-Locked
Loop
Deog-Kyoon Jeong
dkjeong@snu.ac.kr
School of Electrical and Computer Engineering
Seoul National University
2020 Fall
Outline
 Introduction
 Charge-Pump PLL building blocks
 Charge-Pump PLL dynamics
 Clock Synthesizers
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What is PLL?
 A negative feedback system where an oscillator-generated
signal is frequency and phase locked to a reference signal
Clkref
(in)
err
Phase
Detector
err
err
err
Loop
Filter
err
Vctrl Voltage-Controlled
Oscillator
err
ClkVCO
(out)
Frequency & phase locked!!
Clkref
ClkVCO
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PLL Applications (1)
 On-chip clock generator with reduced skew – Zero delay buffer
 Resolves skew problem due to on-chip clock tree
Chip boundary
Aligned
Data
Clock
Aligned
Phase
Detector
Loop
Filter
Voltage-Controlled
Oscillator
On-chip clock tree
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PLL Applications (2)
 Clock frequency multiplication – On-chip clock generation
 Frequency synthesizer – Many RF applications
fin
Frequency
Divider
N
Phase-frequency
Detector
Loop
Filter
Voltage-Controlled
Oscillator
fout
Frequency
Divider
M
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f out 
M
f in
N
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PLL Applications (3)
 Jitter reduction
 PLL filters out low frequency jitter of input clock
Ckin
Phase
Detector
Loop
Filter
Voltage-Controlled
Oscillator
Ckout
Ckin
Ckout
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PLL Applications (4)
 Multi-phase clock generation
 Multi-phase clock is very useful in many applications
Ckin
Phase
Detector
Loop
Filter
Voltage-Controlled
Oscillator
Ckout[0:3]
Ckin
Ckout[0]
Ckout[1]
90 shifted
4-phase clock
Ckout[2]
Ckout[3]
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PLL Applications (5)
 Clock and data recovery
 Extracts timing information from NRZ data pattern
Dout
NRZ
Data(Din)
NRZ Phase
Detector
0
1
1
Loop
Filter
0
1
0
Voltage-Controlled
Oscillator
0
1
0
0
DIN
Ckout
0
PLL aligns falling edge of Ckout with data
transition, so that the data is sampled at
optimal point!!
Ckout
DOUT
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PLL Building Blocks
 Voltage controlled oscillator (VCO)
 Phase detector (PD)
 Charge pump (CP)
 Loop filter (LF)
 Frequency divider
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Charge-Pump PLL
 Most of recent PLLs are of the charge-pump type
 PFD + CP – Converts digital phase-error signal to analog
current
 4 essential building blocks – VCO, PFD, CP, and loop filter
 1 optional building block – Frequency divider
Ckin
up
Phase-frequency down
Detector
Charge Qerr
Pump
Loop
Filter
Vctrl
VCO
Ckout
Frequency
Divider
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VCO
 Self-resonating clock generator
 LC tank, ring oscillator, relaxation oscillator …
 Performance parameters
 Center frequency (No meaning for CP-PLL)
 Tuning range
 Tuning linearity
 Power dissipation
 Supply rejection ratio
 Spectral purity
f
Vctrl
VCO
Periodic pulses
with frequency, f
Tuning
range
KVCO (Hz/V)
Vctrl
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VCO
 VCO gain – KVCO (Hz/V or rad/s/V)
 Large gain means wide tuning range, but more sensitive to control line
noise in PLL
 Phase noise of VCO
 If input clock is clean, VCO is a dominant noise source in PLL
 White noise is modulated by VCO as a “skirt-like shape”
Clock spectrum
- Ideal
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Clock spectrum
- With noise
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Due to supply noise, device noise, etc…
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VCO Phase Noise Model
 Leeson’s model
White noise modulated by VCO + flicker noise
White noise modulated by VCO
White noise floor
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Low Noise VCO
 Use high-Q resonator
 Maximize signal swing – May result in more power dissipation
 Fast slew rate – Reduces signal transition time
 Symmetrical waveform
 Robustness against flicker noise
 Reduces low frequency phase noise
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LC-Tank Oscillator
 LC resonator as VCO
 Low noise
 Insensitive to PVT variation
 High-frequency
 Narrow tuning range
 Requires additional fabrication steps for spiral inductor – Thick top metal
L
Negative resistance to compensate LC tank
loss due to finite metal conductance
MOS varactor for frequency control : Cvar
VCTRL
f 
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2 LC var
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Ring Oscillator
 Chain of variable delay elements
 Easy to implement
 Low cost
 Wide range
 Very sensitive to PVT variation
 Noisier than LC-tank
Td
Td
Td
Odd number of inversions
M stages
1
f
2MTd
CV
Td 
I
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Single stage delay: Delay is controlled by varying C or V or I
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Delay Element Examples
Vout
Vcont
Speed up
Vin
Slow down
(a) Capacitive tuning
Vcont
Vin
Vcont
(c) Delay variation by positive feedback
(b) Starved inverter
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Multipath Oscillator
 When oscillation frequency is low. Extend the frequency by 30%.
 One input of the delay inverter comes from the previous delay
stage
 Extra input comes early from the 2nd previous delay stage
 Must be careful about the false mode.
 Check with various initial conditions
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Design Tips on Ring Oscillator
 RO phase noise is too large for high precision PLL applications the main source of PLL output jitter
 Differential structure for less supply sensitivity
 Latch added at the output for faster rise/fall times
 Too many stages can cause harmonic lock
 Symmetric rise/fall times for less phase noise against flicker noise
 Multipath RO for higher frequency
 PVT variation can cause 1:3 oscillating frequency
 Possible use of LD regulator for less variation and less jitter
 Use of supply as the control voltage
 Level translation is required
 Less swing might increase jitter
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Phase Detector
 Definition
V1
V2
Vout
Phase
Detector
Vout

 XOR gate as phase detector
V1
V2
Vout
Vout
 
V1
V2
Vout
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Phase Frequency Detector
avg(up – dn)
Different frequency (Frequency detection)
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Same frequency (Phase detection)
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PFD Non-ideality
 Dead zone – Occurs when PFD doesn’t respond to small phase
errors
DN pulse is too narrow - ignored by charge pump
 Phase offset – Due to circuit or device mismatch
Vout
Offset

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Design Tips on PFD
 Intentionally introduce delay by adding delay on reset path
 Identical wide pulses on up and dn in the locked state must be cancelled in
the charge pump
 Reduce delay offset in up and dn path to the charge pump
 Reference spur appears at PLL output
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Reference Spur
 In the frequency multiplier
Ckin
up
Phase-frequency down
Detector
Charge Qerr
Pump
Loop
Filter
Vctrl
VCO
Ckout
Frequency
Divider (/N)
Clock power spectrum
Reference spur
(PM modulated)
0
N*fREF
fREF
f
(output)
(input)
Vcntl
(=fREF)
t
TREF
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Charge Pump
 Converts PFD phase error(digital) to charge(analog)
 Issues
 Equal up/down current over entire Vctrl range
 Minimum coupling between switching signals & Vctrl
 PVT insensitive pumping current
 Charge sharing between loop filter cap & CP internal nodes
 Output resistance of the transistors
IP
Parasitic cap
Vctrl
Vctrl
IP
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Design tips on Charge Pump
 A differential charge pump is more accurate
 Equalize up/down current over the entire voltage range
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Loop Filter
 Low pass filter composed in passive RC network
 Type
 Capacitor only – Unstable
 Resistor only – Stable, but lock range is very narrow
 2nd order – Integral path (Set average VCO frequency) + proportional path
(Instantaneous phase correction)
 3rd order – 2nd order LF + additional cap to smooth large IR ripple on Vctrl
R
C
C
Unstable
1st order
2nd order
R
C1
C2
3rd order
Impractical
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Design tips on Loop Filter
 Main source of reference spur in the frequency multiplier
 Beware the leakage current of the capacitor made with thin
oxide of the MOS - Causes spur
Due to leakage
Vcntl
(=fREF)
t
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Frequency Divider
 Type
 Cascade of div-2 – Divide by powers of 2 only
 Integer-N divider – Counter-based FSM
 Fractional-N divider – Alternates div-N & div-N+1 operation to generate
fractional frequency using sigma-delta modulator
 Sigma-delta modulator
 Keeps the average by dithering
 Noise shaping operation moves noise to higher frequency (easily
removed)
 Prevents spur (only fractional spur present)
 Third-order SDM can fully remove fractional spur as well
Fractional bits
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Design tips on Frequency Divider
 Divider operating frequency range > entire VCO oscillation
frequency range under PVT variation (NOT functional operating
oscillation frequency)
 Use dual-modulus prescaler for high frequency division
 Minimum delay – Logic delay degrades PLL loop stability
 Try to reduce jitter with supply variation
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PLL Dynamics
 PLL s-domain model
 PLL dynamics analysis using Bode plot
 Jitter in PLL
 PLL design procedure
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PLL s-domain model
 Assumption – PLL operation frequency is much higher than PLL
loop responding speed
 Loop bandwidth >> f0 by the factor of > 10
 Can ignore sampling nature of PLL, and consequently, can be modeled in sdomain, not in z-domain
 PLL can be viewed as a linear system with phase-input &
phase-output
Clkref
(in)
Phase err
Detector
in
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Charge
Pump
H(s)
Loop Vctrl
Filter
out
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VCO
H( s )
ClkVCO
(out)
 out
 in
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VCO Model
 Beware the unit –rad/s/V
 Multiply by 2 when unit is [Hz/V]
Vcont
VCO
y(t)

(= 2f)
0
 out   0  KVCO  vcont (t )

y (t )  A0 cos  0t  KVCO  vcont (t )dt

Excess phase : out (t )  KVCO  vcont (t )dt
KVCO (Hz/V)
out
KVCO
Transfer function :
(s) 
Vcont
s
Vcont
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PFD and Charge Pump Model
up
Ref
Ierr
ref
+
_
VCO

err
CP
IP/2
Ierr
vco
dn
I1=I2=IP
Average error current over a reference cycle: Ierr
I err 
VCO
 err
 IP
2
Ref
up
dn
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Loop Filter Model
R
C1
R
C1
2nd order
Ierr
C2
ZLF(s)
Vcont
3rd order
2nd order

1  s / z 1
 
Z LF ( s )   R 
sC
sC1
1

3rd order

1  1
RC1s  1
1
s / z 1

Z LF ( s )   R 


sC1  sC2 RC1C2 s 2  ( C1  C2 )s ( C1  C2 )s s /  p  1

(z 
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C  C2
1
, p  1
)
RC1
RC1C2
Usually C1 > 10C2
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Loop Filter Model
 Second order loop filter causes ripple on the Vcont
up
R
C1
dn
2nd order
Proportional term
Vcont
(2nd order)
Integral term
R
C1
C2
Vcont
(3rd order)
Up/dn current cancelled
3rd order
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Bode Plot Premier – 2nd Order PLL
|T|
KVCO I p
s / z  1
T ( s)  K
,K 
2
s
2 C1
-40dB/dec
0dB
z
c
-20dB/dec
T ( jc ) 1 
c 
|H|
I p KVCO R
2
if z  c
Jitter peaking : Due to low frequency zero
-3dB
-20dB/dec
T
-90
-135
-180
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Phase margin (PM)
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Bode Plot Premier – 3rd Order PLL
|T|
-40dB/dec
-20dB/dec
0dB
c
z
p
KVCO I p
1 s / z  1
T (s)  K 2
,K 
s s / p 1
2 (C1  C2 )
T ( j c ) 1   c 
-40dB/dec
I p KVCO R
2 ( 1  C2 / C1 )
|H|
-3dB
-40dB/dec
T
-90
-135
-180
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PM
To maximize PM, c must be located at
geometric mean of z and p , i.e.,
c=(zp)1/2
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Tuning Design Parameters
 Tuning of R
1 I PKVCO
s 2 2C
|T|
1 I PR  KVCO
s
2
c 
z 
large R
1
RC
K vco I P R
2
log 
small R
|H|
log 
Higher bandwidth, larger PM,
larger IR noise (reference spur)
large R
small R
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Tuning Design Parameters
 Tuning of C
|T|
large C
small C
z 
log 
1
RC
|H|
log 
Higher bandwidth, smaller PM (unstable)
large C
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small C
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Tuning Design Parameters
 Tuning of IP
|T|
large Ip
log 
|H|
small Ip
log 
Higher bandwidth, larger PM,
larger IR noise (reference spur)
large Ip
small Ip
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PLL Linear Model
 PLL linear model in s-domain
in +
PFD
_

err

CP
IP/2
in
Ierr
err
+

_
Vctrl VCO
LF
ZLF(s)
KVCO/s
T(s)
out
out
 Open loop transfer function T(s) = out / err
K
IP
 Z LF ( s )  VCO
2
s
 Closed loop transfer function H(s) = out / in
T( s ) 
H( s ) 
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T( s )
1 T( s )
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PLL Transfer Function of 2nd-order PLL
 Closed loop transfer function H(s)
I p KVCO R

I p KVCO
2 s   2
2
2 C
n
n
H(s ) 

I p KVCO R I p KVCO s 2  2 s   2
2
s s

n
n
2
2 C
s
 
n
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I p KVCO
2 C
 
I p KVCO C R
2 2
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Open-loop Transfer Function
• Open-loop unit gain frequency
 Closed-loop bandwidth
• Phase Margin?
[Crawford - Advanced Phase-Lock Techniques]
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PLL Jitter
 All the loop components may contribute jitter
 PLL output jitter can be reduced through proper bandwidth selection
 Two important cases
 When input noise is dominant
 When VCO noise is dominant
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PLL Jitter Transfer
 Input noise
 O/N = H(s) → Low pass filter!!
 Bandwidth should be lower for noise rejection
|H(j)|
N
I
+
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PD
& CP
LPF
VCO
O
0dB
-3dB
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c

46
Closed-Loop Transfer Function
2 s   2
n
n
H(s ) 
s 2  2 s   2
n
n
 
I p KVCO
n
2 C
 
I p KVCO C R
2 2
[Crawford - Advanced Phase-Lock Techniques]
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PLL Jitter Transfer
 VCO noise
 O/N = 1 - H(s) → High pass filter!!
 Bandwidth should be higher for noise rejection
 Same c
|1-H(j)|
I
N
PD
& CP
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LPF
VCO
+
O
0dB
-3dB
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c

48
Closed-Loop Transfer Function
• VCO jitter transfer function
s2
H ( s )  1  H(s) 
2
s 2  2 s   2
n
n
• If
, peaking occurs
[Crawford - Advanced Phase-Lock Techniques]
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PLL Linear Model with FB Divider
 PLL linear model in s-domain
in +
PFD
_

err
CP
IP/2
Ierr
Vctrl VCO
LF
ZLF(s)
KVCO/s
out
1/M
 Open loop transfer function T(s) = out / err
K
IP
1
 Z LF (s)  VCO 
2
s M
 Closed loop transfer function H(s) = out / in
T ( s)
H ( s)  M 
All the stability analysis is on the modified T(s)
1  T ( s)
Loop gain is reduced by M
T (s) 
Phase is multiplied by M – Frequency as well
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PLL Design Procedure
 Determine PLL spec
 Operation range, bandwidth, power budget, jitter peaking …
 Design VCO
 Should have the proper operation range over PVT variation
 Determine KVCO
 Design loop filter
 Determine proper pole-zero location
 Determine RC values – Should be practical (R=100 ~ 10k, Cmax = 200pF)
 Determine charge pump current
 PM should be considered – More than 60
 Several A ~ 1mA
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