Keysight PCI Express® 5.0 CEM TX Test Procedures Version 0.9
PCI Express® 5.0 CEM TX Signal
Quality Testing for Keysight
UXR-Series, Z-Series, V-Series,
MXR Series, or equivalent RealTime Oscilloscopes
Version 0.9
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Keysight PCI Express® 5.0 CEM TX Test Procedures Version 0.9
Copyright © 2002-2022 PCI-SIG ®
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owners.
The PCI-SIG disclaims all warranties and liability for the use of this document and the
information contained herein and assumes no responsibility for any errors that may appear in
this document, nor does the PCI-SIG make a commitment to update the information
contained herein.
Contact the PCI-SIG office to obtain the latest revision of this document
Questions regarding this document or membership in the PCI-SIG may be forwarded to:
PCI-SIG 3855 SW 153rd Drive Beaverton, OR 97006 Phone: 503-619-0569
Fax: 503-644-6708 e-mail Administration@pcisig.com http://www.pcisig.com
DISCLAIMER
This document is provided "as is" with no warranties whatsoever, including any
warranty of merchantability, non-infringement, fitness for any particular purpose, or
any warranty otherwise arising out of any proposal, specification, or sample. The PCISIG
disclaims all liability for infringement of proprietary rights, relating to use of
information in this specification. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted herein.
PCI-SIG disclaims all warranties and liability for the use of this document and the information
contained herein and assumes no responsibility for any errors that may appear in this document,
nor does PCI-SIG make a commitment to update the information contained herein.
This test procedure document is provided “as is” without any warranties of any kind, including any
warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any use, proposal, specification, or sample. PCI-SIG disclaims all liability
for infringement of proprietary rights, relating to use of information in this specification. No
license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted
herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Copyright © 2018, 2019, 2021 PCI-SIG
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Revision History
Version
Date
Summary of Changes
Contributor(s)
0.3
9.25.2021
Rick Eads
0.9
3/24/2022
Initial Draft
PCIe 5 TX Preset, TX Signal
Quality, Jitter Testing
Updated Screen Shots
Rick Eads
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Table of Contents
Revision History .................................................................................................................................................................................. 3
Table of Contents ................................................................................................................................................................................ 4
Overview ............................................................................................................................................................................................... 5
Software Requirements ....................................................................................................................................................................... 8
Oscilloscope Setup .............................................................................................................................................................................. 9
[PHY 2.1] Add-in Card Transmitter Preset Test for 32GT/s....................................................................................................13
[PHY 2.11] System Board Transmitter Preset Test for 32GT/s ...............................................................................................16
[PHY 2.3] Add-in Card Transmitter BASE Specification Jitter Test at 32GT/s ....................................................................20
[PHY 2.10] System Board Transmitter Base Specification Jitter Test at 32GT/s ..................................................................23
[PHY 2.1] Add-in Card Transmitter Signal Quality Test for 32GT/s. .....................................................................................26
[PHY 2.7] System Board Transmitter Signal Quality Test for 32GT/s....................................................................................32
[PHY 2.17] System Board Reference Clock (100MHz) Jitter Test ............................................................................................38
Post Processing Waveform Data with SigTest Phoenix..............................................................................................................40
Post Processing with ClockJitterTool 5_0_2 ................................................................................................................................49
Appendix A.........................................................................................................................................................................................51
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Overview
This document contains the procedure for testing PCI Express 5.0 CEM based
endpoint and root complex devices that support 32GT/s using Keysight real time
oscilloscopes including the UXR-Series, Z-Series, V-Series, Q-Series, X-Series or other
equivalent Keysight oscilloscope having a minimum bandwidth of 33GHz (for signal
quality measurements) and MXR-Series of 5GHz (for reference clock measurements).
For the purposes of this document, Keysight “real-edge” channels (Z-Series) capable
of bandwidth above 33GHz are not included in this test procedure.
This document provides details on:
1. Measuring the correct transmitter equalization values for each preset and verifying
that the chosen transmitter equalization value for signal quality testing meets eye
height and other jitter requirements using the PCISIG’s PCIe 5.0 Compliance Test
Fixtures (CBB5, CLB5, and Variable ISI Channel) at speeds of 32GT/s.
2. Measuring root complex reference clock for phase jitter using the Intel Clock Jitter
tool [add revision]
3. Analyzing the data used to test the endpoint or root complex device against the
PCIe 5.0 CEM specification is done using SigTest Phoenix Version 5.0.24 or later.
Note: The tests described in this document are intended to provide information about
the tests that will be used in PCI-SIG compliance program. This testing is not a
replacement for an exhaustive test validation plan. Also, all content in this test
procedure is subject to change without notice.
Please read through this entire document before you proceed with testing your
endpoint or root complex device so that you may become familiar with the overall
testing procedure.
Please refer to the following documents on www.pcisig.com for more specific
information related to the PCI Express 5.0 specification.
•
•
•
PCI Express® Base Specification Revision 5.0, Ver. 1.0
PCI Express® Card Electromechanical Specification Revision 5.0, Ver. 1.0
PCI Express Architecture PHY Test Specification Revision 5.0, Version 1.0
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Hardware Requirements
Oscilloscope: This document was developed using Keysight digital storage
oscilloscope, Model# UXR0334A having a bandwidth of 33 GHz. This scope gives a
maximum sampling rate of 128GS/s on four channels simultaneously and up to 2G
of acquisition memory. References to other Keysight Oscilloscopes such as the UXRSeries, *Z-Series, *V-Series, *Q-Series and *X-Series are also implied by any reference
to the V-Series as all share the same user interface for the testing purposes described
in this document.
*For sample rates below 128GSa/s, 2:1 interpolation is allowed for 32GT/s
measurements using SigTest Phoenix.
Figure 1 Keysight UXR Series 33GHz, 4-channel, real time oscilloscope
1. Cables:
a) 2.92mm(m)-2.92mm(m) phase matched cable pair ~ 1m in length,
Huber+Suhner. Qty=2 pairs for root complex testing, qty=1 pair for endpoint
testing. NOTE: It is recommended cables pairs be phase matched to 1ps.
These must be ordered separately. (Use Huber+Suhner PN: 85105115 or PCI
SF102E/11SK/11SK/914mm)
b) Short MMPX (female) to 2.92mm (female) connectors (supplied with CEM 5.0
test fixture kit H+S PN: 85119609 or 024E430CR092KCR4PM1PSSTD)
Qty = 2 for Add-in Card testing, Qty = 4 for System testing
c) MMPX (female) to MMPX (female) connector cable assembly (supplied with
CEM 5.0 test fixture kit H+S PN: 85120962), 1 foot long. Qty = 1 matched
pair (2 total)
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Figure 2 Cables, adapters, and accessories for PCIe 5.0 testing
2. Accessories
Terminators (MMPX, female, 50-ohm, Huber+Suhner, qty=30)
ATX Power Supply with 24-pin connector for add-in cards (qty=1)
3. Test Fixtures
Revision 5.0 Compliance Base Board (CBB), Compliance Load Board (CLB), &
variable ISI board (the ISI board is used only for RX testing at 32GT/s).
Figure 3 PCIe 5.0 CEM compliance fixtures consist of two CLBs (a x4/x8 and a x1/x16 board), one CBB and a
variable ISI channel board
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
The compliance fixtures required for testing include a CBB for endpoint testing and
one of two CLBs for root complex testing that support x1, x4, x8, or x16 CEM slot
widths on the root complex device. Test fixtures can be purchased from the PCI-SIG
at http://pcisig.com/specifications/order-form.
Software Requirements
1. SigTest Phoenix
PCI Express 5.0 TX Compliance is measured using the PCI-SIG’s SigTest
Phoenix tool. This tool can be downloaded from Intel at:
http://www.intel.com/high-speed-io. This document was written using
SigTest Phoenix 5.1.02 for testing at 32GT/s.
2. PCIe 5.0 at lower data rates
For testing PCIe at lower data rates of 2.5G, 5G, and 8GT/s, use SigTest
3.2.0.3 and follow the test procedures written for testing PCI Express 3.0. For
testing PCIe at 16GT/s, use SigTest 4.0.52 and follow the test procedure
written for testing PCIe 4.0 devices. These versions of SigTest can be
downloaded from the same location noted above. This document focuses
only on testing at 32GT/s.
3. Clock Jitter Tool
For system testing it is necessary to validate that the 100MHz system
reference clock operates within the allowable amount of phase jitter specified
for PCIe 5.0 root port devices. This tool can be downloaded at
http://www.intel.com/high-speed-io. This document was written using Clock
Jitter Tool 5.0.2.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Oscilloscope Setup
For all TX measurements of your PCIe 5.0 device you need to setup your oscilloscope
to be able to capture the waveforms with enough depth and bandwidth to ensure good
signal integrity. This section reviews basic setup procedures for ensuring your signals
are properly scaled, that your bandwidth is set correctly, and that your memory depth
and channel setup is optimized for making PCIe 5.0 measurements.
It is assumed that you are already working with an oscilloscope that has been properly
calibrated and that the cables you are using have also been calibrated and the
oscilloscope channels have been de-skewed. Refer to the PCIe 3.0 test procedures to
review how this is done if needed. (Refer to the next section for CBB5 Setup).
1. It is usually a good practice to start any instrument configuration process by
initializing the instrument to a consistent state. For convenience, you may want
to press the Default Setup on the front panel of the oscilloscope before you
begin.
2. Configuring the acquisition and oscilloscope memory.
a) For PCIe 5.0 the minimum oscilloscope bandwidth required is 33GHz. To set
this bandwidth, select Setup -> Acquisition from the drop-down menu.
b) On this screen you want to do the following steps:
a. Turn Sin(x)/x Interpolation off
b. Set the sample rate to the maximum (manually). In this case we are
using 128 GSa/s. If your oscilloscope cannot support a maximum
sample rate of 128GSa/s, you must enable 2:1 interpolation.
c. Set the memory depth appropriate to capture 2M UI. With 128GSa/s
we need to set the memory depth to 8M points. Depending on the
scope you are using, the actual number of points you need to capture
2M UI could be different. For example, if you are using a Keysight
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
scope able to sample at 80GSa/s with bandwidth set to 33GHz, set the
memory depth to 5M points, and enable Sin(x)/x Interpolation at 2:1
(This will yield a 10M waveform record after 2x interpolation is
applied)
d. Set the bandwidth to 33GHz.
Turn off Sin(x)/x
interpolation
Set oscilloscope bandwidth to
33GHz
Sampling rate should be at
least 128GSa/s.
Set the oscilloscope
acquisition memory to 10M
points.
3. Auto scale the signal
a) Once you have connected your 32GT/s signal to the oscilloscope and your
DUT is transmitting P0 at the proper level of de-emphasis, you want to be sure
that the oscilloscope’s dynamic range is optimized for the amplitude of the
signal. To do this you turn on the channels for each of the differential signals
(D+, D-, and CLK+, CLK- if appropriate) you plan to capture. Then select
Control -> Auto scale from the drop-down menu.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Select Auto scale to properly
set the maximum dynamic
range of the oscilloscope.
b) With both channels of the differential signal now properly scaled, you want to
setup a hardware differential channel by selecting Setup -> Channel 1 from
the drop-down menu.
Select Differential Channels
c) Since now both differential signals have been combined into one combined
signal in hardware, you can now turn off the second differential signal (it is
now showing the common mode of the differential channel). To do this you
select the second channel (in this case it is Channel 3) on the Channel screen
and then you turn it off.
Turn the second differential
channel (in this case channel 3)
off.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
d) Now set the scale so that the entire waveform is on-screen. This is for your
convenience and may help ensure that you are able to save all of the
waveforms with the proper number of unit intervals in your data files. Use the
drop-down menu Setup -> Horizontal to enter this selection. For the scope in
this example, 14us/division was used as shown.
Set the horizontal scale to show
the entire waveform on screen
(optional)
e) You should see a screen that looks something like this: (P0 at 32GT/s is
displayed).
Figure 4 A properly scaled and configured PCIe 5.0 Signal from an endpoint device ready to be analyzed
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
The nomenclature “[PHY 2.x]” refers to the section of the PCI Express Architecture
PHY Test Specification Rev 5.0 and designates the numbered test assertion in that
document.
[PHY 2.1] Add-in Card Transmitter Preset Test for 32GT/s
This procedure determines whether the device under test produces the correct TX
transmitter equalization for each of the eleven (P0-P10) presets. Lanes which are not
being tested should be terminated with 50-ohm terminations.
1. Configure the CBB5 as shown below. This connection setup is used for both
Preset Testing and add-in Card BASE Jitter Testing.
Toggle button
Turn SSC On
Toggle circuit output
Connect MMPX-2.92mm cable
pair to lane0
ATX Power Supply
connection
Connect toggle circuit to RX
Lane0 using MMPX-MMPX
cable pair
Connect 1m MMPX2.92mm cable pair to inputs
of your Oscilloscope
Attach 50-ohm
terminators to
active but unused
TX lanes
Oscilloscope
Figure 5 Add-in card connection diagram for PCIe 5.0 endpoint transmitter (TX) testing of TX Presets
2. Make sure that the CBB is supplying SSC enabled clock (-0.5% SSC downspread) for this test.
3. Assuming your oscilloscope is properly setup and is currently displaying P0 at
32GT/s and is properly scaled and configured, these are the next steps to
capturing and analyzing the presets P0-P10. First you will want to setup a
location in which you can store your data. Select File -> Save -> Waveform to
open the file management dialog page.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
File->Save->Waveform
4. Then select the new folder icon in order to create a new folder in your directory
of choice.
Select this icon to create a
working directory for your
waveform files.
5. When you have selected your directory, then pick an appropriate name for your
data file and save that file as a “Type Waveform Files (Binary Data (*.bin)”.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Enter a name for your data
file that helps to identify it
along with the preset it
contains, and lane number if
appropriate.
Be sure to select the “bin”
file type.
6. Next, using the toggle button on the CBB5, cycle through all the DUT presets
P1-P10 and repeat the above process to save a file for each of the 11 presets.
TIP: Using the naming convention described by the SigTest Phoenix CLI
Documentation document included with the SigTest Phoenix 5.0.24 installation,
SigTest Phoenix can automatically input and analyze all the preset files in a given
container folder. The file name should contain a substring of the form _Pnn_t_
where 'nn' is the preset number between 00 and 10 and 't' is the type of the
waveform: 'd' for differential, for example, “TID1001_Ln00_P04_d_32GT.bin"
indicates a differential measurement of preset 4.
7. After you have captured Preset P10, press the toggle button two more times and
you should see a toggle pattern (101010 repeating). Capture this waveform to an
appropriate file name. You will use this later while post processing your data to
determine your pulse width jitter.
8. Refer now to the section in this document entitled “Data Post Processing” for
instructions on how to analyze the data you have captured.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
[PHY 2.11] System Board Transmitter Preset Test for
32GT/s
This section of the test procedure shows how to measure the system board or root
complex transmitter to determine whether the proper levels of de-emphasis are being
generated for each of the 11 presets P0-P10 at 32GT/s.
9. There are two Compliance Load Boards in the PCIe 5.0 CEM fixture kit. Choose
the load board appropriate for the lane width of the slot you plan to test (either
x1, x4, x8, or x16). For unused lanes, be sure to terminate them appropriately
with MMPX 50-ohm terminators. Note each board has an RX and TX side.
Figure 6 CLB5 Fixtures for x1, x16 and x4, x8 testing
10. Once you determine the lane width of the CEM connector interface on your
system board that you want to test, configure the appropriate CLB5 as shown in
the example below. This photo shows the connection necessary to use the CLB
toggle function to force the DUT to switch between the TX compliance patterns.
Reference Clock SMP
connections for x16 side of CLB
for dual port testing
Connect a pair of MMPXMMPX cables between the
toggle circuit and lane0 of the
RX side for the lane you want
to test
Reference Clock SMP
connections for x1 side of CLB
for clock testing.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
11. On the TX side of the CLB5, connect the MMPX-SK short cables to the
2.92mm, 1m cables and then connect those cables to the lane that you want to
test. This setup is used for System Preset, BASE Jitter, Signal Quality, and
Reference clock testing.
Toggle button to switch between
different TX compliance states
for the x16 side of the CLB.
Oscilloscope
Use the short MMPX-2.92mm cables to connect
to the CLB TX output and then connect that
cable to the oscilloscope inputs. If you have
mechanical interference issues you may need to
use different cable pairs and MMPX-2.92mm
adapter pairs.
Figure 7 System board connection diagram for PCIe 5.0 transmitter (TX) testing of TX Presets
12. Assuming your oscilloscope is properly setup and is currently displaying P0 at
32GT/s and is properly scaled and configured, these are the next steps to capture
and analyze the presets P0-P10. First you will want to setup a location in which
you can store your data. Select File -> Save -> Waveform to open the file
management dialog page.
File->Save->Waveform
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
13. Then select the new folder icon to create a new folder in your directory of choice.
Select this icon to create a
working directory for your
waveform files.
14. When you have selected your directory, then pick an appropriate name for your
data file and save that file as a “Type Waveform Files (Binary Data (*.bin)”
Enter a name for your data
file that helps to identify it
along with the preset it
contains, and lane number if
appropriate.
Be sure to select the “bin”
file type.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
15. Next, using the toggle button on the CBB5, cycle through all the remaining DUT
presets P1-P10 and repeat the above process to save a file for each of the 11
presets.
TIP: Using the naming convention described by the SigTest Phoenix CLI
Documentation document included with the SigTest Phoenix 5.0.24 (or later)
installation, SigTest Phoenix is able to automatically input and analyze all the
preset files in a given container folder. The file name should contain a substring
of the form _Pnn_t_ where 'nn' is the preset number between 00 and 10 and 't' is
the type of the waveform: 'd' for differential, for example,
“TID1001_Ln00_P04_d_32GT.bin" indicates a differential measurement of
preset 4.
16. Refer now to the section in this document entitled “Data Post Processing” for
instructions on how to analyze the data you have captured.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
[PHY 2.3] Add-in Card Transmitter BASE Specification
Jitter Test at 32GT/s
This procedure is run on all card electromechanical form factor Add-in Cards that
operate at 32.0 GT/s. This test verifies that the Add-in Card produces TTX-UPW-TJ, TTXUPW-DJDD, TTX-UTJ, and TTX-UDJDD below the CEM 5.0 Specification limit. Lanes which are
not being tested should be terminated with 50-ohm terminations.
1. Setup the oscilloscope to capture 2M UI of transmitter data only as described in
the “Oscilloscope Setup” section of this document.
2. Insert the Add-in Card under test into a compliance base board (CBB) revision
5.0 without power.
3. Make sure that the compliance toggle outputs (MMPX connectors J5 and J85) on
the CBB main board are connected to receive lane zero on the CBB via
appropriate MMPX to MMPX cables.
4. Terminate all Tx lanes with 50-ohm terminations except for lane under test.
5. Connect the Tx lane under test to a high-speed oscilloscope or equivalent data
capture instrument via phase matched, low loss MMPX to 2.92mm cables or
MMPX-2.92mm adapter and phase matched, low loss 2.92mm to 2.92mm cables.
6. Make sure that the CBB is supplying SSC enabled clock (-0.5% down-spread)
for this test.
Move CBB 5.0 SSC switch to
select -0.5% SSC enabled.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
7. Power on the CBB.
8. Push the compliance toggle button on the CBB (inject a 1 ms pulse of a 100 MHz
clock signal into receive lane zero of the Add-in Card under test) until the pattern
is the 32.0 GT/s Jitter Measurement Pattern (Lanes 0/8/16/24—setting #47 in
the PCIe 5.0 Base Specification).
PCIE 5.0 Jitter Pattern
9. Measure the transmitted waveform with a high-speed oscilloscope or equivalent
data capture instrument with the maximum bandwidth set to 33 GHz. Minimum
sampling rate of 128 GS/s is required. If the real time oscilloscope doesn’t
support the required 128 GS/s sampling rate, it is permitted to use Sinx/x
interpolation with maximum 2x sampling to achieve minimum 4 samples per UI.
10. Capture at least 2.0 million unit-intervals of data (2.0 X 106 X 31.25ps = 62.5 µs)
by selecting File->Save->Waveform.
File->Save->Waveform
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Enter a name for your data
file that helps to identify it
along with the preset it
contains, and lane number if
appropriate.
Be sure to select the “bin”
file type.
11. Measure TTX-UPW-TJ, TTX-UPW-DJDD, TTX-UTJ, and TTX-UDJDD at 1e12 using the SigTest Phoenix analysis program with the 32.0 GT/s Pulse Width
Jitter template file (PCIe/5_0/Base/ Optimize_CTLE.dat).
12. If the SigTest Phoenix analysis program indicates the system’s jitter parameters
at 1e-12 are less than or equal to indicated in the Table below, the electrical
compliance test passes and is complete for this lane.
Jitter Parameter
Jitter (Max) (ps)
TTX-UPW-TJ
6.25
TTX-UPW-DJDD
2.5
TTX-UTJ
6.25
TTX-UDJDD
3.125
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
[PHY 2.10] System Board Transmitter Base Specification
Jitter Test at 32GT/s
This procedure is run on all card electromechanical form factor systems that operate at
32.0 GT/s. This test verifies that the system produces TTX-UPW-TJ, TTX-UPW-DJDD, TTX-UTJ,
and TTX-UDJDD below the CEM 5.0 Specification limit.
1. Power down the system under test.
2. Insert the compliance load board revision 5.0 into the slot to be tested.
Rx+
Rx-
Tx+
Tx-
Toggle
CLB5
High Speed 32
GT/s data
signals.
System Board
3. Make sure that the compliance toggle outputs (MMPX connectors J5 and J85) on
the CLB are connected to receive lane zero on the CLB via appropriate MMPX
to MMPX cables.
4. Connect the Tx lane under test to a high-speed oscilloscope or equivalent data
capture instrument via phase matched, low loss MMPX to 2.92mm cables or
MMPX to 2.92mm adaptors and phase matched, low loss 2.92 to 2.92mm cables.
5. Terminate all Tx lanes with 50-ohm terminations except for the lane under test.
6. Power on the system under test. The system will use SSC enabled or SSC
disabled reference clock to be consistent with settings for the system during
normal operation.
7. Push the compliance toggle button on the CLB (inject a 1 ms pulse of a 100
MHz clock signal into receive lane zero of the system under test) until the
pattern is the 32.0 GT/s Jitter Measurement Pattern (Lanes 0/8/16/24—setting
#47 in the PCIe 5.0 Base Specification).
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
PCIE 5.0 Jitter Pattern
8. Measure the transmitted waveform with a high-speed oscilloscope or equivalent
data capture instrument with the maximum bandwidth set to 33 GHz. Minimum
sampling rate of 128 GS/s is required. If the real time oscilloscope doesn’t
support the required 128 GS/s sampling rate, it is permitted to use Sinx/x
interpolation with maximum 2x sampling to achieve minimum 4 samples per UI.
9. Capture at least 2.0 million unit-intervals of data (2.0 X 106 X 31.25ps = 62.5 µs).
File->Save->Waveform
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Enter a name for your data
file that helps to identify it
along with the preset it
contains, and lane number if
appropriate.
Be sure to select the “bin”
file type.
10. Measure TTX-UPW-TJ, TTX-UPW-DJDD, TTX-UTJ, and TTX-UDJDD at 1e12 using the SigTest Phoenix analysis program with the 32.0 GT/s Pulse Width
Jitter template file (PCIe/5_0/Base/ Optimize_CTLE.dat).
11. If the SigTest Phoenix analysis program indicates the system’s jitter parameters
at 1e-12 are less than or equal to indicated in the Table below, the electrical
compliance test passes and is complete for this lane.
Jitter Parameter
Jitter (Max) (ps)
TTX-UPW-TJ
6.25
TTX-UPW-DJDD
2.5
TTX-UTJ
6.25
TTX-UDJDD
3.125
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
[PHY 2.1] Add-in Card Transmitter Signal Quality Test for
32GT/s.
This section of the test procedure verifies that the signaling of the add-in card device
meets the eye diagram and other requirements. Lanes that are not being tested should
be terminated with 50-ohm MMPX terminators.
Configure the measurement connection setup as indicated below. Note that this is an
end-of-channel test and as such requires that you embed the maximum allowable
channel loss as per the PCIe 5.0 CEM connection using InfiniiSim. The particular S4P
file that you embed is determined by several factors including the loss of your cables,
your particular CEM fixture trace, connector losses, and adapter losses. For more
detail on characterizing your fixtures and cables, please refer to Appendix B. PCIe 5.0
Electrical Test Fixture Characterization in the PCI Express Architecture PHY Test
Specification Revision 5.0, Version 0.9.
12. Setup the oscilloscope to capture 2M UI of transmitter data only as described in
the “Oscilloscope Setup” section of this document.
13. Adding package model losses. Since PCIe 5.0 is a die-pad to die-pad standard it is
necessary to apply the root complex package model to the waveforms that you
plan to capture and then process later using SigTest Phoenix. To do this you
need to first make sure that your oscilloscope is licensed to support the InfiniiSim
Waveform Transformation Toolset (if you need to obtain a license please contact
you Keysight representative).
a) This procedure assumes you are setup to use hardware differential channels 13. Select the drop-down menu Setup -> Channel 1…
b) In the InfiniiSim dialog box select 4 Port (Channels 1-3). Then click Setup.
Then click the Setup Wizard.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Select the 4-port differential
channel for InfiniiSim
Then click on the Setup
Wizard button
Then click on the Setup
Wizard
c) Follow along with the steps that the Setup Wizard takes you through, clicking
Next as needed until you get to the page where it asks, Select the InfiniiSim
model you want to use.
Click on the “add insertion
loss of a fixture or cable”
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
d) Once you get to the Simulation Block Setup in the wizard, you need to
specify the PCI-SIG’s root complex reference package model that is included
with the SigTest Phoenix 5.1.02 distribution (or later) in the S-Params directory
of the SigTest Phoenix installation folder. The file chosen in this instance is
called: RC_TL_21p5dB.s4p.
Name the Infiniisim transfer
function that will embed the
package model. Then click
Next, then click Finish.
Select the appropriate
package model. In this case it
is the 21.5db model.
Then click Next
e) Now you must name the transfer function you will use to apply the reference
channel model. You only have to do this once assuming you do not change
the measurement setup environment (channel assignments) so in the future
you can bypass the InfiniiSim setup and just recall this loss model once the
setup has been completed.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Name the Infiniisim transfer
function that will embed the
package model. Then click
Next, then click Finish.
Then click Next
f) Once the transfer function is computed by the oscilloscope software, close out
of the dialogs and return to the main Infiniium oscilloscope home screen. On
this screen you will now see the DUT’s waveform with the 21.5dB channel and
package model applied.
Data Signal from System
DUT.
6dB loss model applied
to data signal
14. Press the Compliance Mode Toggle Button on the CBB5 until you arrive at PCIe
5.0 P0. It may help to first reset the DUT and count off the proper sequence of
button pushes until you cycle through the 2.5G, 5G, 8G and 16GT/s compliance
signals. The PCI-SIG’s compliance program requires that you pass the PCIe 5.0
CEM signal quality test with one of the presets (P0-P10). You can choose to test
any preset you prefer; however, in preliminary testing we have found that Preset
P5 usually gives passing results with most devices tested thus far. You may test
other presets but one must pass to be in compliance.
Waveform Capture. Once you have selected the proper 32GT/s preset that you want
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
to test, select File -> Save -> Waveform from the drop-down menu on the
oscilloscope.
File->Save->Waveform
Then select the new folder icon in order to create a new folder in your directory of
choice.
Select this icon to create a
working directory for your
waveform files.
When you have selected your directory, then pick an appropriate name for your data
file and save that file as a “Type Waveform Files (Binary Data (*.bin)”
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Enter a name for your data
file that helps to identify it
along with the preset it
contains, and lane number if
appropriate.
Be sure to select the “bin”
file type.
15. Test all TX lanes that the device support, saving waveform files with the
appropriate preset as needed. To do this change your connection to the CBB5
that you want to test next, being sure to continue to maintain 50-ohm
terminations on all lanes not being tested.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
[PHY 2.7] System Board Transmitter Signal Quality Test
for 32GT/s.
This section of the test procedure verifies that the signaling of the System Board
device meets the eye diagram and other requirements. Lanes that are not being tested
should be terminated with 50-ohm MMPX terminators.
Configure the measurement connection setup as indicated below. Note that this is an
end-of-channel test and as such requires that you embed the maximum allowable
channel loss as per the PCIe 5.0 CEM connection using InfiniiSim. The S4P file that
you embed is determined by several factors including the loss of your cables, your
CEM fixture trace and connector losses, and adapter losses. For more detail on
characterizing your fixtures and cables, please refer to Appendix B. PCIe 5.0 Electrical
Test Fixture Characterization in the PCI Express Architecture PHY Test Specification
Revision 5.0, Version 0.9.
Rx+
Rx-
Tx+
Tx-
Toggle
CLB5
High Speed 32
GT/s data
signals.
System Board
1.
Setup the oscilloscope to capture 2M UI of transmitter data only as described in
the “Oscilloscope Setup” section of this document.
Data setup on CH1-3 shown
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
2. Adding trace and package model losses. Since PCIe 5.0 is a die-pad to die-pad
standard it is necessary to embed the necessary trace and end point package model
losses to the waveforms that you plan to capture and then process later using
SigTest Phoenix. To do this you need to first make sure that your oscilloscope is
licensed to support the InfiniiSim Waveform Transformation Toolset (if you need
to obtain a license please contact you Keysight representative).
g) This procedure assumes you are setup to use hardware differential channels 13. Select the drop-down menu Setup -> Channel 1…
h) In the InfiniiSim dialog box select 4 Port (Channels 1-3). Then click Setup.
Then click the Setup Wizard.
Then click on the Setup
Wizard button
Select the 4-port differential
channel for InfiniiSim
Then click on the Setup
button
Then click on the Setup
Wizard
i) Follow along with the steps that the Setup Wizard takes you through, clicking
Next as needed until you get to the page where it asks, Select the InfiniiSim
model you want to use.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
You will be adding Insertion
Loss so select this model
j) Once you get to the Simulation Block Setup in the wizard, you need to
specify the PCI-SIG’s endpoint reference package model that is included with
the SigTest Phoenix 5.1.02 distribution (or later) in the S-Params directory of
the SigTest Phoenix installation folder. The file used in this instance is called:
NRC_TL_6dB.s4p.
Select the appropriate
channel + package model. In
this case it is the 6dB model.
Then click Next
k) Now you must name the transfer function you will use to apply the reference
package model and appropriate traces losses to achieve your target total max
channel loss. You only have to do this once assuming you do not change the
measurement setup environment (channel assignments, fixtures, or cables) so
in the future you can bypass the InfiniiSim setup and just recall this package
model once the setup has been completed.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Name the Infiniisim transfer
function that will embed the
package model. Then click
Next, then click Finish.
l) Once the transfer function is computed by the oscilloscope software, close the
dialogs, and return to the main Infiniium oscilloscope home screen. On this
screen you will now see the DUT’s waveform with the package model applied.
Data Signal from System
DUT.
6dB loss model applied
to data signal
3. Press the Compliance Mode Toggle Button on the CLB5 until you arrive at PCIe
5.0 P0 at 32GT/s. It may help to first reset or power-off the DUT and count off
the proper sequence of button pushes until you cycle through the 2.5G, 5G, 8G
and 16GT/s compliance signals. The PCI-SIG’s compliance program requires
that you pass the PCIe 5.0 CEM signal quality test with one of the presets (P0P10). You can choose to test any preset you prefer; however, in preliminary
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
testing we have found that Preset P5 usually gives passing results with most
devices tested thus far. You may test other presets but one must pass to be in
compliance.
Waveform Capture. Once you have selected the proper 32GT/s preset that you want
to test, select File -> Save -> Waveform from the drop-down menu on the
oscilloscope.
File->Save->Waveform
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Then select the new folder icon in order to create a new folder in your directory of
choice. When you have selected your directory, then pick an appropriate name for
your data file and save that file as a “Type Waveform Files (Binary Data (*.bin)”
In the case of System Board waveform files be sure to also select All Waveforms in
the Waveform Source field. This ensure that you save both the data waveform and its
associated clock waveform in one file. This helps ensure that the data and clock
waveforms are always together and never out of sync.
Select this icon to create a
working directory for your
waveform files.
Enter a name for your data
file that helps to identify it
along with the preset it
contains, and lane number if
appropriate.
Be sure to select the “bin”
file type.
Make sure to select All Data
and then select All
Waveforms
Test all TX lanes that the device supports, saving waveform files with the appropriate
preset as needed. To do this change your connection to the CLB5 lane you want to
test next, being sure to continue to maintain 50-ohm terminations on all lanes not
being tested.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
[PHY 2.17] System Board Reference Clock (100MHz) Jitter
Test
The CEM 5.0 specification has removed the requirement to measure the TX signal
quality using Dual Port (capturing data and clock), so this test was introduced to
ensure the System's 100 MHz reference clock does not violate the CEM 5.0
specification clock jitter limit.
1. Connect the edge mounted SMP’s on the CLB to a high-speed oscilloscope or
equivalent data capture instrument via phase matched, low loss SMP to 2.92mm
cables or SMP to 2.92mm adapters and phase matched, low loss 2.92 to 2.92mm
cables. Use appropriate edge mounted SMP’s for the CLB card edge used.
2. The system will use SSC enabled or SSC disabled reference clock to be consistent
with settings for the system during normal operation.
3. Capture transmitted clock waveform with a high-speed oscilloscope or equivalent
data capture instrument with the maximum bandwidth set to 5 GHz. The sample
rate used should be the highest sample rate available on your oscilloscope. For
Keysight UXR-Series scopes this will be either 128GSa/s or 256 GSa/s. It is
critical to use the fastest sample rate available to minimize aliasing even though
you will be setting the oscilloscope bandwidth to 5GHz.
256GSa/s, 5GHz BW, 205M
points of acquisition
memory.
4. Confirm that the waveform is the clock waveform at 100 MHz. SSC can be On
or Off depending on system configuration (use same SSC configuration as used
for TX signal quality test). It is important to know if SSC is enabled or not when
analyzing the clock waveform with the clock jitter tool.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
5. Capture at least 80,000 clock cycles (80,000 X 10 ns = 1.6 ms). Save the
waveform with an appropriate name in a .bin format. Depending on the sample
rate of your oscilloscope, please refer to the following table to determine the
minimum acquisition memory needed to capture 80,000 clock cycles.
Oscilloscope Sample Rate (GSa/s)
Memory Required for 80K Clock Cycles (MBytes)
16
12.8
20
16
40
32
80
64
128
102.4
160
128
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256
204.8
Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Post Processing Waveform Data with SigTest Phoenix
1. Preset Tests (AIC and System). Using SigTest Phoenix, Version 5.0.24 or later,
verify the presets at 32GT/s. First boot the SigTest Phoenix.exe application then
click Generation 5_0 and then click on Preset_TestAC then click Confirm.
Click on Gen5
Then Preset_TestAC
2. Next, click on Browse on the Preset Values Screen to select the directory where
the preset waveforms have been saved.
TIP: Using the naming convention described by the PCIe 5.0 Phi Test Spec file
included with the SigTest Phoenix 5.0.45 installation, SigTest Phoenix is able to
automatically input and analyze all the preset files in each container folder. The
file name should contain a substring of the form _Pnn_t_ where 'nn' is the preset
number between 00 and 10 and 't' is the type of the waveform: 'd' for differential.
For example, “TID1001_Ln00_P04_d_32GT.bin" indicates a differential
measurement of preset 4.
If you have not saved waveform files using this nomenclature, you can still test
the presets by selecting and testing every preset waveform individually.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Click here to specify a
directory of waveforms to
test.
3. Once you have selected the directory where the waveform files are located, click
on the Test button to invoke the preset test. SigTest Phoenix will then load all 11
waveforms (or individual waveforms if you have chosen that mode of operation)
and perform the preset test. A text file summarizing the results of the preset test
will be saved to the selected waveform file directory when you press the Exit
button.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Select the No_CTLE
Template
4. Signal Quality Tests: AIC. To test an add-in card (AIC) for signal quality we do
two tests. The first test is the AIC signal quality data test. The second test uses
the 32GT/s Jitter Measurement Pattern (setting #47 in the PCIe 5.0 BASE
Specification) you saved while saving the preset data to perform the BASE Jitter
Tests.
a) To test signal quality of the add-in card you load and analyze the preset
waveform that you saved which included the appropriate S4P embedded trace
loss and package model loss applied. The technology template you use is called
CARD Then Click Confirm.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Select Card
b) After you click Confirm, a dialog screen will appear where you select the file
you wish to analyze for 32GT/s Signal Quality.
Load the waveform file (.bin)
with the trace loss and
package model applied
Click Load and Verify Data File
Select Optimize_CTLE_SSC Template
Select Test
c) Measure extrapolated (at 1e-12) Eye Height and extrapolated (at 1e-12) Eye
Width using the SigTest Phoenix analysis program with the 32.0 GT/s Add-in
Card transmitter test template file (PCIe\5_0\Card\optimize_CTLE_SSC.dat).
Manual sweeping of CTLE_SSC using Sigtest templates is allowed if optimize
CTLE template gives closed eye
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
5. BASE Jitter Tests: AIC. Next select the BASE jitter tests and load the 32.0
GT/s Jitter Measurement Pattern (Lanes 0/8/16/24—setting #47 in the PCIe
5.0 Base Specification).
a. Select BASE tests in Sigtest Phoenix.
Click on Generation 5_0
Then BASE
Then Confirm
b. Measure TTX-UPW-TJ, TTX-UPW-DJDD, TTX-UTJ, and TTX-UDJDD at 1e-12 using
the SigTest Phoenix analysis program with the 32.0 GT/s optimize CTLE template file
(PCIe/5_0/Base/ Optimize_CTLE.dat).
Load the waveform file (.bin)
for the file you want to
analyze.
Click Load and Verify Data File
Select Optimize_CTLE Template
Click Test
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
c. Results. The results screen is shown below:
6. Signal Quality Tests: System Board. To test a system board for signal quality
we need to load the proper waveform.
a) To test signal quality of the system board you load and analyze the preset
waveform that you saved which included the appropriate trace loss and
package model losses embedded with the capture waveform and should also
include both data and clock in the file.
Click on Generation 5_0
Then System
Then Confirm
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
b) Measure Extrapolated Eye Height (at 1e-12) and extrapolated Eye Width (at
1e-12) using SigTest Phoenix analysis program with the appropriate choice of
template file:
If the system SSC is turned Off
(Templates\PCIe\5_0\System\Optimize_CTLE.dat).
If the system SSC is turned on
(Templates\PCIe\5_0\System\Optimize_CTLE_SSC.dat).
Manual sweeping of CTLE using Sigtest templates is allowed if optimize CTLE
template gives closed eye.
Load the waveform file (.bin)
you wish to analyze.
Click Load and Verify Data File
Select appropriate Template
Click Test
c) After you click Test, a results screen similar to that shown below will appear
after the data waveform analysis is completed.
d) If the SigTest analysis program indicates the extrapolated Eye Width (at 1e-12) is greater
than or equal to 9.688 ps and Extrapolated Eye Height (at 1e-12) is greater than or equal
to 17.5 mV, the electrical compliance test passes and is complete, otherwise the test fails.
If the test fails, the next system transmitter equalization preset setting should be selected
(by pushing the compliance toggle button) and this test procedure should be repeated until
the system board passes for one of the presets or all transmitter equalization preset
settings (Preset 0-Preset 10 have been tested. You are required to pass the signal quality tests
for one preset. Only one preset for a given device and lane must pass.
e) Repeat the SigTest Phoenix signal Quality Tests for every lane you wish to test.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
7. BASE Jitter Tests: System. Select the BASE jitter tests and load the 32.0
GT/s Jitter Measurement Pattern (Lanes 0/8/16/24—setting #47 in the PCIe
5.0 Base Specification). The system will use SSC enabled or SSC disabled
reference clock to be consistent with settings for the system during normal
operation.
a. Select BASE tests in Sigtest Phoenix
Click on Generation 5_0
Then BASE
Then Confirm
b. Measure TTX-UPW-TJ, TTX-UPW-DJDD, TTX-UTJ, and TTX-UDJDD at 1e-12 using
the SigTest Phoenix analysis program with the 32.0 GT/s optimize CTLE template file
(PCIe/5_0/Base/ Optimize_CTLE.dat).
Load the waveform file (.bin)
for the file you want to
analyze.
Click Load and Verify Data File
Select Optimize_CTLE Template
Click Test
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
c. Results
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Post Processing with ClockJitterTool 5_0_2
This section shows how to analyze your clock waveform with the Intel Clock Jitter
Tool. This document is based on version 5.0.2 of this tool. The tool can be
downloaded here:
https://www.intel.com/content/www/us/en/collections/technology/high-speed-iotools.html?grouping=rdc+Content+Types&sort=title%3Aasc&s=Newest
1. Configure the ClockJitterTool for PCIe 5.0 clock measurements and load the
captured clock file into the ClockJitterTool. Then Select RUN.
Select PCIe 5.0 as the
standard you are testing.
Load the clock waveform file
(.bin) you wish to analyze.
Click RUN
after you load
the clock
waveform.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Select the reference clock
waveform you want to
analyze and then click Open.
2. If the analysis program indicates that the Max HF Rj RMS jitter is less than 200
fs, the system clock compliance test passes and is complete.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Appendix A
Keysight Technologies offers an automated compliance application to facilitate
automated measurements of PCIe 5.0 devices. This product is called the D9050PCIC
PCI Express 5.0 Transmitter Electrical Performance Validation and Compliance
Software tool. Please contact your local Keysight representative for more information
about this tool or visit www.keysight.com/find/pcie for more information and to
arrange for a trial license..
The D9050PCIC supports testing of PCIe 5.0 devices according to the BASE and
CEM 5.0 specifications for all speeds from 2.5GT/s to 32GT/s.
Select the speeds you want to test as
well as the preset to be used for
signal quality testing.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
Select CEM tests you want to run
for each speed your device
supports.
The D9050PCIC also includes the ability to automatically control your device under
test to facilitate the selection of each compliance toggle signal as needed for any given
test saving time by freeing you up from manual toggle selection.
Configure the tool for automated
DUT control to select each
required compliance pattern.
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
The D9050PCIC also allows you to select the individual loss function needed for
testing either PCIe 5.0 add-in cards or motherboards when you select your lane
configurations.
For 32GT/s CEM testing,
configure your DUT with each loss
function required on a per lane
basis
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Keysight PCI Express® 5.0 CEM Test Procedures Version 0.9
When testing is completed, the D9050PCIC produces an HTML report summarizing
all the testing completed.
54