In-Circuit Self-Test (ICST) of Power MOS
Transistors: Measuring Gate Charge as an Indicator
of Oxide Stress and Device Reliability
Anil Kumar Behera#1 , Michael Benegiamo#2 , Luca Moriconi+3 ,
Giulia Orecchini#4 , Valentina Palazzi#5 , Federico Alimenti#6
#
1
Department of Engineering, University of Perugia, ITALY
+
ELES Semiconductor Equipment, Todi, ITALY
anilkumar.behera@dottorandi.unipg.it, 2 michael.benegiamo@studenti.unipg.it, 3 luca.moriconi@eles.com
4
giulia.orecchini@unipg.it, 5 valentina.palazzi@unipg.it, 6 federico.alimenti@unipg.it
Abstract—The gate charge required to turn on a MOS
transistor is closely related to oxide damage and can therefore
be used as an indicator of device reliability and aging over
the lifetime of power electronic systems. This paper proposes
a novel approach to measure the turn-on gate charge that
does not require the drain/source terminals to be disconnected
from the high-current path. Such an approach, therefore, can
be applied to MOSFETs operating under real conditions. The
idea is experimentally validated for a half-bridge inverter
case study and the in-circuit results are consistent with those
obtained for the isolated MOSFETs. Although at a preliminary
stage, this work shows that In-Circuit Self-Test (ICST) is a
promising methodology for reliability assessment and predictive
maintenance of power electronic systems.
Index Terms—In-Circuit Self-Test, power MOS transistors,
power electronic systems, reliability, aging.
I. I NTRODUCTION
Ruggedness and ability to operate in harsh environments are
key features of power electronic devices and systems in the
most challenging applications. Wide bandgap semiconductor
devices, which offer advantages such as higher voltage
handling capability, higher switching frequency, higher
electron mobility and lower losses, have a relatively more
vulnerable gate oxide, and its degradation must be carefully
considered. Reliability and mantainability, that are a relevant
and very important issues in system engineering [1], [2], can
be effectively addressed only if the device stress and aging are
continuosly measured. This means that the device reliability
qualification tests, typically carried out at production level on
isolated devices [3], [4], must be complemented with in-circuit
monitoring, i.e. monitoring of the power transistors embedded
in the real circuit where they operate.
The precursors of degradation and increase in junction
temperature with its effective tracking to monitor health of
device during operation is of very high significance. The
determination of hierarchy of commonly explored Temperature
Sensitive Electrical Parameters (TSEP) under such conditions
is a big challenge. The design of auxiliary circuits embedded
to applications to estimate state of health and zeroing into
a effective TSEP with a high sensitivity is a major point of
discussion. All the conventional TSEP’s are discussed at great
length based on mission profiles [5] and it is found out that
the threshold voltage variations are a very powerful indicator
of junction temperature and gate-oxide degradation.
A detailed analysis of junction temperature extraction
through dynamic threshold voltage extraction is given
in [6]. However the dependence on gate resistance, parasitic
inductances and reference voltage makes it complicated and
less robust. Moreover it does not separate the effects of gate
oxide degradation from the junction temperature estimation
by threshold voltage tracking and hence makes the algorithm
workable only under mildly aged conditions.
The use of voltage source as a driver increases the
complications in analytical equations which can be overcome
with a current source driver instead. A novel gate conduction
model is also proposed in [7] where a voltage source driver
has been deployed. However the algorithm followed is long in
particular due to the effect of source inductance. A constant
current driver source can tackle the source inductance effects,
and hence is the basis of this paper.
A similar idea has been proposed in [8] and the feasibility
has been validated. The lower speed requirement for data
acquisition serves as a key advantage in this method. However
the area of accuracy is still open for improvement. A major
challenge that needs to be addressed is to find TSEP’s in the
same methodology that addresses junction temperature, and
gate oxide degradation separately and lays out the principles
behind it clearly [9]. The proposed current source driver
based threshold voltage estimating circuit based on capacitance
changes can be dually effective towards junction temperature
and gate oxide degradation estimation as well.
Studies such as [9] show that threshold voltage measurement
is quite complex to perform in-situ, as it requires the
drain/source terminals of the Device Under Test (DUT) to be
rerouted to the measurement circuit. This is critical because
high currents flow through the drain/source, and any additional
loss along this path (due to measurement mode switching) is
absolutely unacceptable.
In this paper, a novel approach to the above problem
is proposed for the first time. Instead of focusing on the
threshold voltage, we consider the turn-on gate charge, which
is not only strictly related to the threshold voltage, but also
on
determines the on-drain-to-source resistance (rds
), i.e. the
main contribution to switching losses. The beauty of the
proposed approach is that the turn-on gate charge (and its
dependence on the gate-to-source voltage) can be determined
without disconnecting the drain/source terminals of the power
MOSFET from the high-current path, thus resulting in a true
In-Circuit Self-Test (ICST) methodology. To validate the idea,
a case study inverter with gate charge ICST is discussed,
showing that only gate rerouting is required.
II. M ATERIAL AND METHODS
on
One of the most important transistor parameters is rds
,
the drain-to-source resistance in the on state. In fact, such
a resistance has a significant impact on the switching losses
and the maximum static current for a given thermal budget
(thermal power dissipated by the package to reach the
maximum junction temperature). A very important relationship
that can be demonstrated using simple MOSFET models is that
on
rds
is inversely proportional to the turn-on gate charge Qg as:
on
rds
=
L2
µn Qg
(1)
where L is the channel length and µn is the carrier mobility
on
(electrons for a n-channel device). As a consequence rds
can
be indirectly monitored determining the turn-on gate charge,
and this is the basic idea of the present study.
A. Half-bridge inverter
To demonstrate the feasibility of in-circuit measurement
of the turn-on gate charge and, more specifically, the
gate-to-source voltage as a function of gate charge during
the turn-on transient, the half-bridge inverter shown in Fig. 1
is considered. This circuit consists of two equal n-channel
MOSFETs, namely M1 (Lo side) and M2 (Hi side) and
two equal capacitors: C1 and C2. During operation, the two
transistors alternately turn on and off, generating an AC
waveform at the load terminals (i.e., between the M1/M2
midpoint and the C1/C2 midpoint). A driver integrated circuit
(IC) is used to generate, from the input PWM waveform, the
two signals that control the transistor gates. The driver uses
a bootstrap circuit (diode DB and capacitor CB) to switch on
M2 even if the driver supply Vcc is less than or equal to the
main bridge supply Vs .
The gate charge ICST is implemented by the red
components in the schematic of Fig. 1. For simplicity, only the
Lo-side MOSFET is considered, but with circuit modifications
the same principle can be applied to the Hi-side transistor.
The two switches S1 and S2 are necessary to isolate the gate
terminals of M1 and M2 from the driver IC, so that the charge
transient can be measured. These switches are not critical due
to the high gate impedances. In addition to S1 and S2, the
ICST is based on the resistor Ra , which is used to inject the
Fig. 1. Schematic of a half-bridge inverter with gate charge ICST capability
(components in red). The two switches S1 and S2 are necessary to isolate the
gate terminals of M1 and M2 from the driver IC, allowing the gate charge
experiment. Apart from S1 and S2, the ICST is based on the resistor Ra
(used to inject the charge into the gate) and on the resistor Rb (needed for
the drain biasing). The procedure is as follows: first the charge pin goes high
and Ra is supplied with 5 V. The gate-to-source voltage Vgs is measured
and the gate charge Qg is evaluated. Finally, the charge pin goes low and
the charge is removed from the gate: this corresponds to a reset of the ICST,
which is now ready for another measurement cycle.
charge into the gate, and the resistor Rb , needed to bias the
drain during the self-test.
The self-test procedure is as follows: first, the charge pin
goes high and Ra is applied to Va (not shown in the figure).
Then the gate-to-source voltage Vgs is measured and the gate
charge Qg is evaluated. Finally, the charge pin goes low and
the charge is removed from the gate: this corresponds to a
reset of the ICST, which is now ready for another measurement
cycle. As can be seen, the method described does not require
the drain/source terminals of M1 to be routed to a specific
test circuit and does not alter the high current path of the
inverter. During the transient measurement, the bridge supply
Vs is disconnected from the main line, while the transistor
drain is supplied with the test voltage Vb .
Finally, it is worth noting that the proposed gate charge
ICST can be extended to other inverter or DC/DC converter
configurations; this discussion is beyond the scope of this
paper and will be done in future work.
B. Measuring the gate charge
As described above with a few elements, it is possible to
measure the gate charge transient of transistor M1. During
such an experiment, the gate-to-source voltage Vgs is recorded
over time and, knowing the resistance Ra , it is possible to
estimate the transient gate current and thus the gate charge.
In particular, the gate charge Qg at the discrete time n is
calculated with the following iteration (equivalent to a discrete
integration):
Qg [n] =
Va − Vgs [n]
∆t + Qg [n − 1]
Ra
(2)
The first gate charge transient measurements have been
performed on isolated MOSFETs to obtain ground truth values
for both Vgs and Qg . The target device is the RFP50N06, an
n-channel power transistor capable of switching up to 50 A
at 60 V, with a 22 mΩ drain-to-source resistance [10]. The
experiment is based on the same elements shown in Fig. 1
and is executed automatically by an Arduino Uno system.
The obtained results are shown in Fig. 2 (top panel), where
the measured Vgs is plotted as a function of Qg , the latter
calculated with eqn. 2. In this test, Rb = 100 Ω, while the drain
is biased with Vb equal to 5 and 10 V respectively. From the
analysis of the graph, it can be seen that the gate-to-source
voltage is almost constant during channel formation and is
about 3.2 V. Such a plateau ends with a turn-on charge of
about 20 nC at 5 V and 25 nC at 10 V. The black curve
is obtained by leaving the drain open and gives a plateau of
2.2 V, which is quite close to the device threshold voltage.
The bottom panel of Fig. 2 represents the SPICE simulations
of the isolated MOSFET charge transient. These were obtained
using the device model reported in [10] and developed
according to [11]. It can be seen that the simulated behavior
is in very good agreement with the experiments.
After validating the ICST procedure for isolated MOSFETs,
the half-bridge breadboard of Fig. 3 is implemented. This
breadboard uses two RFP50N06 power transistors, two
2200 µF electrolytic capacitors and an Arduino Uno R3 for
self-test automation and data transfer to a PC. In the first
experiment, switches S1 and S2 of Fig. 1 are closed and
a 30 kHz square wave is applied to the PWM input. The
measured AC voltage on a 10 Ω is represented in Fig. 4 and
clearly shows the normal inverter operation.
In the second experiment, switches S1 and S2 are instead
open and ICST mode is enabled. Fig. 5 shows the gate
transient results for Rb equal to 100 Ω (top panel) and 10 Ω
(bottom panel), respectively. Both the turn-on charge and
the height of the voltage plateau are compatible with those
obtained for the isolated MOSFET in the same condition, thus
validating the proposed methodology.
The results obtained well demonstrate the feasibility
of the ICST concept and constitute the starting point
for a more structured activity. The next steps of this
research will be mainly in three directions. First, a new
family of breaboards will be developed and tested. These
beardboards will include at least two different types of
gate-to-source voltage (V)
III. R ESULTS
5
4
3
2
open drain
Vb = 5 V
Vb = 10 V
1
0
0
5
10
15
20
gate charge (nC)
25
30
25
30
5
gate-to-source voltage (V)
where Vgs [n] is the nth sample of the gate-to-source voltage.
The iteration starts at Qg [0] = 0 (initial conditions). In
the above relationship, Va is the voltage applied to the
charge terminal of Fig. 1 (5 V in our case), and Ra is the
corresponding series resistance (1.5 MΩ in our case), and ∆t
is the sampling time interval (104 µs in our case). The discrete
time n ranges from zero to the maximum number Ns of
samples taken; the continuous time is given by: t = n ∆t.
In future work, Ra will be replaced by a programmable
current generator to simplify the charge calculation.
4
3
2
Vb = 5 V
Vb = 10 V
1
0
0
5
10
15
20
gate charge (nC)
Fig. 2. Measured (top) and simulated (bottom) turn-on gate charge of the
isolated MOS transistor. In both cases a drain resistance Rb = 100 Ω is
considered. The turn-on charge is 20 nC for Vb = 5 V, and 25 nC for Vb =
10 V. During channel formation the gate-to-source voltage is almost constant
and equal to about 3.2 V. The black curve is obtained with an open drain and
gives a 2.2 V plateau, quite close to the threshold voltage.
power circuits (namely the half-bridge inverter and a boost
DC/DC converter), and at the same time provide a deeper
integration between microcontroller, analog switches and all
the necessary components to make ICST effective. The new
boards can be used for long-term experiments. Second, the
effect of temperature on MOSFET parameters will be carefully
studied, [12]. Third, a threshold degradation experiment will
be performed by stressing the power MOSFET with high
temperature, current and voltage conditions for a long time
(weeks/months). This will be done using the equipment
available at ELES Semiconductor, a company whose primary
business is designing semiconductor IC reliability solutions.
IV. C ONCLUSION
This paper reports, for the first time, a half-bridge inverter
with in-circuit self-test capability of the power MOSFET
devices. The turn-on gate charge is an indicator of device
gate-to-source voltage (V)
5
4
3
2
Vb = 5 V
Vb = 10 V
1
0
0
10
15
20
gate charge (nC)
25
30
25
30
5
gate-to-source voltage (V)
Fig. 3. Half-bridge inverter breadboard with gate charge ICST capability. The
inverter is based on two RFP50N06 silicon n-channel MOS transistors (60 V,
50 A, 22 mΩ) from Fairchild Semiconductors. Two 2200 µF electrolytic
capacitors complete the half-bridge. The driver uses a 100 nF bootstrap
capacitor. An Arduino Uno R3 is exploited to perform the in-circuit self-test
and to download the measured data to a PC.
5
4
3
2
Vb = 5 V
Vb = 10 V
1
0
0
Fig. 4. Half-bridge inverter output waveform for a main supply voltage Vs =
18 V DC. The output voltage is measured on a 10 Ω load. The bridge is driven
with a 30 kHz symmetric square wave signal (TTL compatible).
5
10
15
20
gate charge (nC)
Fig. 5. Measured turn-on gate charge of the in-circuit MOS transistor in two
conditions: Rb = 100 Ω (top) and Rb = 10 Ω (bottom). In both cases the
half-bridge power supply Vs is disconnected. The turn-on gate charge is about
25 nC with Vb = 10 V, a value similar to that of the isolated MOSFET.
project (https://opeva.eu/).
reliability and lifetime aging, and can be determined without
disconnecting the source/drain terminals from the high-current
path of the inverter. Experiments have shown that the gate
charge of the isolated transistor and that measured in-circuit
are compatible, thus validating the proposed methodology.
Although at a preliminary stage, this study shows that
ICST is a promising approach for reliability assessment and
predictive maintenance of power electronic circuits, especially
in mission-critical devices such as those used in automotive
and aerospace systems.
ACKNOWLEDGEMENT
This work was supported by the the Italian Ministry of
University and Research (MUR) with the “PNRR 2023,
D.M. 117” action, and with the “PON 2022 Ricerca e
Innovazione, D.M. 1062” action. The work is also supported
by the European Commission with the OPEVA research
The authors also wish to acknowledge the kind support of
ELES Semiconductors, Todi, Italy.
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