MOS Capacitor
Simple capacitance model
Gate and body form MOS
capacitor
Operating modes
 Accumulation
 Depletion
 Inversion
polysilicon gate
silicon dioxide insulator
Vg < 0
+
-
p-type body
(a)
0 < Vg < Vt
In accumulation there is no depletion
layer. The remaining capacitor is the
(b)
oxide capacitance.
+
-
depletion region
Vg > Vt
+
-
inversion region
depletion region
(c)
Series connection of two capacitors: the capacitance of the
oxide and the capacitance of the depletion layer.
1
1/26/2021
Threshold Voltage
The threshold voltage is defined as the gate-body voltage that causes
the surface to change from p-type to n-type
For this condition, the surface potential has to equal the negative of
the p-type potential
Apply KCL around loop:
Gate (n poly)
VGB  VT +−
+
VGS  VFB  Vox  VBS

Vox

VBS − − − − − − 

s
Vox  Eoxtox 
tox Es
 ox
qNa xdep qNa 2 s
2qNa (2 p )
Es 

s 
s
 s qNa
s
1
VTn  VFB  2 p 
2q s N a (2 p )
Cox
2
1/26/2021
Q-V Curve for MOS Capacitor
QG
QN (VGB )
QB ,max
VFB
VTn
VGB (V )
• In accumulation, the charge is simply proportional to
the applies gate-body bias
• In inversion, the same is true
• In depletion, the charge grows slower since the
voltage is applied over a depletion region
3
1/26/2021
MOS CV Curve
C
QG
Cox
Cox
QN (VGB )
QB ,max
VFB
•
•
•
•
VTn
VGB (V )
VFB
VTn
VGB
Small-signal capacitance is slope of Q-V curve
Capacitance is linear in accumulation and inversion
Capacitance is depletion region is smallest
Capacitance is non-linear in depletion
4
1/26/2021
Depletion Layer Thickness
The width of the induced space charge region adjacent to the oxide
semiconductor interface can be calculate as:
Adjacent figure shows the
space charge region in a p-type
semiconductor substrate.
The potential fb is the
difference (in volts) between Efi
and Ef and is given by
The energy-band diagram in the p-type
semiconductor, indicating surface potential.
The potential s is called the surface potential; it is the difference (in volts) between
Ef, measured in the bulk semiconductor and Ef; measured at the surface. The surface
potential is the potential difference across the space charge layer.
The space charge width can now be written
5
1/26/2021
The electron concentration at the
surface is the same as the hole
concentration in the bulk material.
The applied gate voltage creating
this condition is known as the
threshold voltage.
6
1/26/2021
7
1/26/2021
Frequency Effect
The generation of electrons that
produces a change in the inversion
charge density occurs at a particular
rate. If the ac voltage across the MOS
capacitor changes rapidly, the change in
the inversion layer charge will not be
able to respond.
The C-V characteristics is a function of the
frequency of the ac signal used to measure
the capacitance
8
1/26/2021
The MOSFET
The metal-oxide-semiconductor field-effect transistor (MOSFET) is the most
important device for forefront high-density integrated circuits such as microprocessors
and semiconductor memories. It is also becoming an important power device.
MOSFET STRUCTURE
A common MOSFET is a four-terminal
device that consists of a p-type
semiconductor substrate into which two
n+-regions, the source and drain, are
formed, usually by ion implantation. The
Si02 gate dielectric is formed by
thermal oxidation of Si for a high quality
Si02-Si interface. The metal contact on
the insulator is called the gate; heavily
doped poly-silicon or a combination of
silicide and poly-silicon is more commonly
used as the gate electrode.
9
1/26/2021
The basic device parameters are the
channel length L, which is the distance
between the two metallurgical n+-p
junctions; the channel width W; the
insulator thickness tox; the junction
depth rj, and the substrate doping NA
rj
In a silicon integrated circuit, a MOSFET is surrounded by a thick oxide (called the
field oxide to distinguish it from the gate oxide) or a trench filled with insulator to
electrically isolate it from adjacent devices.
Vgs = 0
Vgd
The source contact will be used as the voltage
reference throughout this section. When ground
or a low voltage is applied to the gate, the main
channel is shut off, and the source-to-drain
electrodes correspond to two p-n junctions
connected back to back.
When a sufficiently large positive bias is applied
to the gate so that a surface inversion layer (or
channel) is formed between the two n+-regions,
the source and the drain are then connected by a
conducting surface n-channel through which a
large current can flow.
+
-
g
+
-
s
d
n+
n+
p-type body
b
10
1/26/2021
The electronic current flows from d to s.
As Ids increases with Vds similar to linear
resistor.
Channel pinches off and Ids independent
of Vds. We say current saturates similar to
current source
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg – Vs
Vgd = Vg – Vd
Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion
terminals
Vg
+
+
Vgd
-
-
+
Vgs
Vs
Vds
Vd
11
1/26/2021
MOS structure looks like parallel plate capacitor while operating in
inversions
Gate – oxide – channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon
gate
W
tox
L
n+
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body
p-type body
 Charge is carried by electron
 Electrons are propelled by the lateral electric field between source and drain
E = Vds/L
 Carrier velocity v proportional to lateral E-field
v = µE
µ called mobility
 Time for carrier to cross channel:
t=L/ v
12
1/26/2021
Now we know
 How much charge Qchannel is in the channel
 How much time t each carrier takes to cross
Qchannel
t
W
V
 Cox Vgs  Vt  ds Vds
2
L
V
  Vgs  Vt  ds Vds
where
2


I ds 
W
 = Cox
L
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
V
I ds   Vgs  Vt  dsat Vdsat
2



V V 

2
gs
2
t
13
1/26/2021
nMOS transistor modes can be summarized :


0
Vgs  Vt


V
I ds    Vgs  Vt  ds Vds Vds  Vdsat
2
 
2


Vgs  Vt 
Vds  Vdsat


2
cutoff
linear
saturation
Example: Consider an ideal n-channel MOSFET with parameters L = 1.25 µm, µn = 650cm2/V
s. Cox = 6.9 × 10-8 F/m2. and VT = 0.65 V. Design the channel width W such that Id(sat) = 4 mA
for VGS = 5 Volt.
𝑊𝜇𝑛 𝐶𝑜𝑥
𝐼𝑑(𝑠𝑎𝑡) =
(𝑉𝑔𝑠 − 𝑉𝑇 )2
2𝐿
𝑊 × 650 × 6.9 × 10
−
4 × 10 3 =
−
2 × 1.25 × 10 6
𝑊 =11.8 µm
−8
(5 − 0.65)2
14
1/26/2021
n-channel MOS transistor I-V characteristics curve.
With zero bias at the gate,
the source and the drain are
separated by p-region. In this
condition no current.
ID=gD VDS
If the gate is applied with a
sufficient +ve voltage, an electron
inversion layer is created at the
oxide-s.c interface.
The layer connects the source and
the drain and the current is flow.
A gate voltage is required to create the inversion
layer, hence the term enhancement type
The carrier in the inversion layer are electrons hence
the term n-channel MOSFET(n MOS)
VGS>VT
GND
+
15
1/26/2021
16
1/26/2021
G
G
B
S
D
p+
n+
n+
L
xj
B
S
D
n+
p+
p+
L
xj
n-type well
PMOS
NMOS
p-type substrate
Why use n-Channel over p-Channel?
 Complementary MOS: Both P and N type devices
 Create a n-type body in a p-type substrate through compensation.
This new region is called a “well”.
 To isolate the PMOS from the NMOS, the well must be reverse
biased (pn junction)
17
1/26/2021