Chapter 3
3.1. (a)
(b)
x1 x2 x3
f
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
#transistors = NOT gates 2 + AND gates 8 + OR gates
= 3 2 + 4 8 + 1 10 = 48
3.2. (a) In problem 3.1 the canonical SOP for f is
f = x1 x2 x3 + x1x2 x3 + x1x2x3 + x1x2x3
This expression is equivalent to f in Figure P3.2, as derived below.
x1
x2
x2 x3 + x2 x3
x3
x1 x2 x3 + x1 x2 x3 +
x3
x1 x2 x3 + x1 x2 x3
x2 x3 + x2 x3
(b) Assuming the multiplexers are implemented using transmission gates
#transistors = NOT gates 2 + MUXes 6
= 1 2 + 3 6 = 20
3-1
3.3. (a) A SOP expression for f in Figure P3.3 is:
f = (x1 x2 ) x3
= (x1 x2 )x3 + (x1 x2 )x3
= x1 x2 x3 + x1x2 x3 + x1 x2x3 + x1x2x3
which is equivalent to the expression derived in problem 3.2.
(b) Assuming the XOR gates are implemented as shown in Figure 3.61b
#transistors = XOR gates 8
= 2 8 = 16
3.4. Using the circuit
The number of transistors needed is 16.
3.5. Using the circuit
The number of transistors needed is 20.
3.6. (a)
x1 x2 x3
f
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3-2
(b) The canonical SOP expression is
f = x1 x2 x3 + x1x2 x3 + x1x2 x3 + x1 x2x3 + x1 x2 x3
The number of transistors required using only AND, OR, and NOT gates is
#transistors = NOT gates 2 + AND gates 8 + OR gates 12
= 3 2 + 5 8 + 1 12 = 58
3.7. (a)
x1 x2 x3 x4
f
x1 x2 x3 x4
f
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(b)
f = x1 x2x3 x4 + x1 x2x3 x4 + x1x2x3 x4
= x1 x3x4 + x2 x3 x4
The number of transistors required using only AND, OR, and NOT gates is
#transistors = NOT gates 2 + AND gates 8 + OR gates 4
= 4 2 + 2 8 + 1 4 = 28
3.8.
VDD
Vx
1
Vx
3
Vx
2
Vf
3-3
3.9.
Vf
Vx
3
Vx
4
Vx
1
Vx
2
3.10. Minimum SOP expression for f is
f = x2x3 + x1 x3 + x2 x4 + x1 x4
= (x1 + x2)(x3 + x4)
which leads to the circuit
VDD
Vf
Vx
1
Vx
3
Vx
2
Vx
4
3.11. Minimum SOP expression for f is
f = x4 + x1 x2 x3
which leads to the circuit
3-4
VDD
Vf
Vx
4
Vx
1
Vx
2
Vx
3
3.12.
VDD
VDD
Vf
Vx
Vy
Vz
3-5
3.13.
VDD
VDD
Vy
Vx
Vz
Vz
Vy
Vf
Vz
Vy
Vy
Vz
Vx
3.14. (a) Since VDS VGS , VT the NMOS transistor is operating in the saturation region:
2
ID = 12 kn W
L (VGS , VT )
2
= 10 A
V2 5 (5 V , 1 V) = 800 A
(b) In this case VDS < VGS , VT , thus the NMOS transistor is operating in the triode region:
1
W
2
ID = kn L (VGS , VT )VDS , 2 VDS
A
1
2
= 20 V2 5 (5 V , 1 V) 0:2 V , 2 (0:2 V) = 78 A
0
0
3.15. (a) Since VDS VGS , VT the PMOS transistor is operating in the saturation region:
2
ID = 21 kp W
L (VGS , VT )
2
= 5 A
V2 5 (,5 V + 1 V) = 400 A
(b) In this case VDS > VGS , VT , thus the PMOS transistor is operating in the triode region:
1V 2
ID = kp W
(V
,
V
)V
,
L GS T DS 2 DS
1 (,0:2 V)2 = 39 A
= 10 A
5
(
,
5
V
+
1
V)
(
,
0:2)
V
,
V2
2
0
0
3-6
3.16.
RDS
3.17.
RDS
= 1= kn W
L (VGS , VT )
mA
= 1= 0:020 V2 10 (5 V , 1 V) = 1:25 k
0
= 1= kn W
L (VGS , VT )
mA
= 1= 0:040 V2 10 (3:3 V , 0:66 V) = 947
0
3.18. Since VDS < (VGS , VT ), the PMOS transistor is operating in the saturation region:
2
ISD = 12 kp W
L (VGS , VT )
2
= 50 A
V2 (,5 V + 1 V) = 800 A
0
Hence the value of RDS is
RDS = VDS =IDS
= 4:8 V=800 A = 6 k
3.19. Since VDS < (VGS , VT ), the PMOS transistor is operating in the saturation region:
2
ISD = 21 kp W
L (VGS , VT )
2
= 80 A
V2 (,3:3 V + 0:66 V) = 558 A
0
Hence the value of RDS is
RDS = VDS =IDS
= 3:2 V=558 A = 5:7 k
3.20. The low output voltage of the pseudo-NMOS inverter can be obtained by setting Vx = VDD and evaluating
the voltage Vf . First we assume that the NMOS transistor is operating in the triode region while the PMOS is
operating in the saturation region. For simplicity we will assume that the magnitude of the threshold voltages
for both the NMOS and PMOS transistors are equal, so that
VT = VT N = ,VT P
The current flowing through the PMOS transistor is
p
2
ID = 12 kp W
Lp (,VDD , VT P )
= 12 kp (,VDD , VT P )2
= 12 kp (VDD , VT )2
0
3-7
Similarly, the current going through the NMOS transistor is
1V 2
n
ID = kn W
(V
,
V
)V
,
Ln x T N f 2 f
= kn (Vx , VT N )Vf , 12 Vf2
= kn (VDD , VT )Vf , 12 Vf2
0
Since there is only one path for current to flow, we can equate the currents flowing through the NMOS and
PMOS transistors and solve for the voltage Vf .
kp (VDD , VT )2 = 2kn (VDD , VT )Vf , 1 V 2
2 f
kp(VDD , VT )2 , 2kn(VDD , VT )Vf + knVf2 = 0
This quadratic equation can be solved using the standard formula, with the parameters
a = kn; b = ,2kn(VDD , VT ); c = kp (VDD , VT )2
which gives
r
2
Vf = ,2ab 4ab 2 , ac
r
= (VDD , VT ) (VDD , VT )2 , kkp (VDD , VT )2
"
r
= (VDD , VT ) 1 1 , kkp
n
#
n
Only one of these two solutions is valid, because we started with the assumption that the NMOS transistor
is in the triode region while the PMOS is in the saturation region. Thus
"
r
Vf = (VDD , VT ) 1 , 1 , kkp
n
3.21. (a)
#
p
2
Istat = 12 kp W
Lp (VDD , VT )
2
= 12 A
V2 1 (5 V , 1 V) = 192 A
0
(b)
n
RDS = 1= kn W
(V
,
V
)
Ln GS T
= 1= 0:060 mA
4
(5
V
,
1
V)
= 1:04 k
V2
0
(c) Using the expression derived in problem 3.20
A
p
kp = kp W
=
24
Lp
V2
A
n
=
240
kn = kn W
Ln
V2
0
0
3-8
"
r
24
= (5 V , 1 V) 1 , 1 , 240
= 0:21 V
VOL = Vf
#
(d)
PD = IstatVDD
= 192 A 5 V = 960 W 1mW
(e)
RSD P = VSD =ISD
= (VDD , Vf )=Istat
= (5 V , 0:21 V)=0:192 mA = 24:9 k
(f ) The low-to-high propagation delay is
1:7C
tpLH =
kp WLpp VDD
0
1:7 70 fF = 0:99 ns
24 VA2 1 5 V
=
The high-to-low propagation delay is
1:7C
tpHL =
kn WLnn VDD
0
1:7 70 fF = 0:1 ns
60 VA2 4 5 V
=
3.22. (a)
p
2
Istat = 12 kp W
Lp (VDD , VT )
2
= 48 A
V2 1 (5 V , 1 V) = 768 A
0
(b)
n
RDS = 1= kn W
(V
GS , VT )
Ln
4
(5
V
,
1
V)
= 1:04 k
= 1= 0:060 mA
V2
0
(c) Using the expression derived in problem 3.20
A
Wn
A
p
kp = kp W
L = 96 V2 kn = kn L = 240 V2
0
0
p
n
3-9
"
r
96
= (5 V , 1 V) 1 , 1 , 240
= 0:90 V
VOL = Vf
#
(d)
PD = IstatVDD
= 768 A 5 V = 3840 W 3:8mW
(e)
RSD P = VSD =ISD
= (VDD , Vf )=Istat
= (5 V , 0:90 V)=0:768 mA = 5:34 k
(f ) The low-to-high propagation delay is
1:7C
tpLH =
kp0 WLpp VDD
1:7 70 fF = 0:25 ns
96 VA2 1 5 V
=
The high-to-low propagation delay is
1:7C
kn WLnn VDD
1:7 70 fF = 0:1 ns
=
60 VA2 4 5 V
tpHL =
3.23. (a)
0
p
2
Istat = 12 kp W
Lp (VDD , VT )
2
= 12 A
V2 1 (5 V , 1 V) = 192 A
0
(b) The two NMOS transistors in series can be considered equivalent to a single transistor with twice the
length. Thus
RDS
n
= 1= kn W
Ln (VGS , VT )
mA
= 1= 0:060 V2 2 (5 V , 1 V) = 2:08 k
0
(c) Using the expression derived in problem 3.20
A
p
kp = kp W
=
24
Lp
V2
A
n
=
120
kn = kn W
Ln
V2
0
0
3-10
"
r
24
= (5 V , 1 V) 1 , 1 , 120
= 0:42 V
VOL = Vf
#
(d)
PD = IstatVDD
= 192 A 5 V = 960 W 1mW
(e)
RSDP = VSD =ISD
= (VDD , Vf )=Istat
= (5 V , 0:42 V)=0:192 mA = 23:9 k
(f ) The low-to-high propagation delay is
1:7C
tpLH =
kp WLpp VDD
0
1:7 70 fF = 0:99 ns
24 VA2 1 5 V
=
The high-to-low propagation delay is
1:7C
tpHL =
kn WLnn VDD
0
1:7 70 fF = 0:2 ns
60 VA2 2 5 V
=
3.24. (a)
p
2
Istat = 12 kp W
Lp (VDD , VT )
2
= 12 A
V2 1 (5 V , 1 V) = 192 A
0
(b) The two NMOS transistors in parallel can be considered equivalent to a single transistor with twice the
width. Thus
n
RDS = 1= kn W
(VGS , VT )
L
n
= 1= 0:060 mA
8
(5
V
,
1
V)
= 520
V2
0
(c) Using the expression derived in problem 3.20
A
p
kp = kp W
=
24
Lp
V2
A
n
=
480
kn = kn W
Ln
V2
0
0
3-11
"
r
24
= (5 V , 1 V) 1 , 1 , 480
= 0:10 V
VOL = Vf
#
(d)
PD = IstatVDD
= 192 A 5 V = 960 W 1mW
(e)
RSD P = VSD =ISD
= (VDD , Vf )=Istat
= (5 V , 0:10 V)=0:192 mA = 25:5 k
(f ) The low-to-high propagation delay is
tpLH =
=
1:7C
kp WLpp VDD
0
1:7 70 fF = 0:99 ns
24 VA2 1 5 V
The high-to-low propagation delay is
1:7C
kn WLnn VDD
1:7 70 fF = 0:05 ns
=
60 VA2 8 5 V
tpHL =
0
3.25. (a)
NM H = VOH , VIH = 0:5 V
NM L = VIL , VOL = 0:7 V
(b)
VOL = 8 0:1 V = 0:8 V
NM L = 1 V , 0:8 V = 0:2 V
3.26. Under steady-state conditions, for an n-input CMOS NAND gate the voltage levels VOL and VOH are 0 V
and VDD , respectively. No current flows in a CMOS gate in the steady-state. Thus there can be no voltage
drop across any of the transistors.
3.27. (a)
(b)
PNOT gate = fCV 2
= 75 MHz 150 fF (5 V)2 = 281 W
Ptotal = 0:2 250; 000 281 W = 14 W
3-12
3.28. (a)
PNOT gate = fCV 2
= 125 MHz 120 fF (3:3 V)2 = 163 W
(b)
Ptotal = 0:2 250; 000 163 W = 8:2 W
3.29. (a) The high-to-low propagation delay is
1:7 150 fF
1:7C
tpHL =
=
= 0:255 ns
kn WLnn VDD 20 VA2 10 5 V
0
(b) The low-to-high propagation delay is
tpLH =
1:7C
1:7 150 fF
=
= 0:638 ns
kp WLpp VDD 8 VA2 10 5 V
0
(c) For equivalent high-to-low and low-to-high delays
tpHL = tpLH
1:7C
1:7C
=
Wp
kn WLnn VD D
kp Lp VD D
k
Wp = knp Wn
Lp
Ln
12:5
m
= 0:5 m
0
0
0
0
3.30. (a) The high-to-low propagation delay is
tpHL =
1:7C = 1:7 150 fF = 0:193 ns
kn WLnn VDD 40 VA2 10 3:3 V
0
(b) The low-to-high propagation delay is
tpLH =
1:7C
1:7 150 fF
=
= 0:483 ns
kp0 WLpp VDD 16 VA2 10 3:3 V
(c) For equivalent high-to-low and low-to-high delays
tpHL = tpLH
1:7C
1:7C
=
W
W
n
kn Ln VD D
kp Lpp VD D
k
Wp = knp Wn
Lp
Ln
8:75
= 0:35 m
m
0
0
0
0
3-13
3.31. The two PMOS transistors in a CMOS NAND gate are connected in parallel. The worst case current to drive
the output high happens when only one of these transistors is turned “ON”. Thus each transistor has to have
W
the same dimensions as the PMOS transistor in the inverter, namely Lpp = 4.
n
The two NMOS transistors are connected in series. If each one had the ratio W
Ln , then the two transistors
could be thought of as one equivalent transistor with a 2WLnn ratio. Thus each NMOS transistor must have
n
twice the width of that in the inverter, namely W
Ln = 4.
3.32. The two NMOS transistors in a CMOS NOR gate are connected in parallel. The worst case current to drive
the output low happens when only one of these transistors is turned “ON”. Thus each transistor has to have
n
the same dimensions as the NMOS transistor in the inverter, namely W
Ln = 2.
W
The two PMOS transistors are connected in series. If each of these transistors had the ratio Lpp , then the two
W
transistors could be thought of as one transistor with a 2Lpp ratio. Thus each PMOS transistor must be made
n
twice as wide as that in the inverter, namely W
Ln = 8.
3.33. The worst case path in the PMOS network contains two transistors in series. Thus each PMOS transistor must
be twice as wide the transistors in the inverter. The worst case path in the NMOS network also contains two
transistors in series. Similarly, each NMOS transistor must be twice as wide as those in the inverter.
3.34. The worst case PMOS path contains three transistors in series so each transistor must be three times as wide
as the PMOS transistors in the inverter. The worst case NMOS path contains two transistors in series. Thus
the NMOS transistors must be two times as wide.
3.35. (a) The current flowing through the inverter is equal to the current flowing through the PMOS transistor. We
shall assume that the PMOS transistor is operating in the saturation region.
p
2
Istat = 12 kp W
Lp (VGS , VTp )
2
= 120 A
V2 ((3:5 V , 5 V) + 1 V) = 30 A
0
(b) The current flowing through the NMOS transistor is equal to the static current Istat. Assume that the
NMOS transistor is operating in the triode region.
1V 2 n
Istat = kn W
(V
,
V
)V
,
Tn DS
Ln GS
2 DS
1 2
30 A = 240 A
V2 2:5 V Vf , 2 Vf
0
1 = 20Vf , 4Vf2
Solving this quadratic equation yields Vf = 0:05V. Note that the output voltage Vf satisfies the assumption
that the PMOS transistor is operating in the saturation region while the NMOS transistor is operating in the
triode region. (c) The static power dissipated in the inverter is
PS = IstatVDD = 30 A 5 V = 150 W
(d) The static power dissipated by 250,000 inverters.
250; 000 Ps = 37:5 W
3-14
3.36.
x1
x2
x3
NOR plane
VDD
VDD
P1
P2
P3
P4
NOR plane
f1
f2
3.37.
x1
x2
x3
NOR plane
VDD
VDD
P1
P2
P3
P4
NOR plane
f1
3-15
f2
3.38.
x1
x2
x3
NOR plane
VDD
VDD
S1
S2
S3
S4
NOR plane
f1
f2
3.39.
x1
x2
x3
NOR plane
VDD
VDD
S1
S2
S3
S4
NOR plane
f1
3-16
f2
3.40.
x1
x2
x3
NOR plane
VDD
VDD
VDD
VDD
VDD
f1
NOR plane
3.41.
x1
x2
x3
NOR plane
VDD
VDD
VDD
VDD
VDD
f1
NOR plane
3-17
3.42.
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
= m1
= m2
= m4
= m7
= m1 + m2
= m1 + m4
= m1 + m7
= m2 + m4
= m2 + m7
= m4 + m7
= m1 + m2 + m4
= m1 + m2 + m7
= m1 + m4 + m7
= m2 + m4 + m7
= m1 + m2 + m4 + m7
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
f2
= m0
= m3
= m5
= m6
= m0 + m3
= m0 + m5
= m0 + m6
= m3 + m4
= m3 + m6
= m5 + m6
= m0 + m3 + m5
= m0 + m3 + m6
= m0 + m5 + m6
= m3 + m5 + m6
= m0 + m3 + m5 + m6
3.43.
3-18
3.44.
x1
x2
x1
x3
x2
x3
0
0
1
0
x1 x2
0
1
1
1
0
0
0
1
x1 x2 + x1 x3
0
1
1
1
x1 x3
0
0
1
0
x1 x2 + x1 x3 + x2 x3
x2 x3
3.45. The canonical SOP for f is
f = x1 x2x3 + x1x2 x3 + x1x2 x3 + x1x2x3 + x1 x2x3
This expression can be manipulated into
f = x1 x2 + x1x3 + x1 x2
= x2 + x1x3
The circuit is
x1
x3
0
0
1
0
x1 x3
0
1
1
1
x2
3.46. The canonical SOP for f is
x2 + x1 x3
f = x1x2 x4 + x2x3 x4 + x1 x2x3
This expression can be manipulated into
f = x2 (x1 x4 + x3x4 ) + x2 (x1x3 )
Using functional decomposition we have
f = x2f1 + x2 f2
where
f1 = x1 x4 + x3x4
f2 = x1 x3
3-19
The circuit is
x1
x1 x4 + x3 x4
x3
x4
x1 x2 x4 + x2 x3 x4 + x1 x2 x3
0
x1
x1 x3
x3
x2
3.47. The canonical SOP for f is
f = x1x2 x4 + x2x3 x4 + x1 x2x3
This expression can be manipulated into
f = x2 (x1 x4 + x3x4 ) + x2 (x1x3 )
Using functional decomposition we have
f = x2f1 + x2 f2
where
f1 = x1 x4 + x3x4
f2 = x1 x3
The function f1 requires one 2-LUT, while f2 requires three 2-LUTs. We then need three additional 3-LUTs
to realize f , as illustrated in the circuit
x1
x1 x4
x4
x1 x4 + x3 x4
x1 x2 x4 + x3 x2 x4
x3
x4
x3 x4
x1 x2 x4 + x2 x3 x4 + x1 x2 x3
x2
x1
x1 x2 x3
x1 x3
x3
3.48.
g
h
j
k
= x2 x3
= x1
= x2
= x3
3-20
3.49. (a)
x1
x2 0
x1 • 0 + x1 x2
x3 x1 x2 + x3 • 1 = x1 x2 + x3
1
1
(b)
0
0
1
x3
1
0
x3
0
x3 • 0 + x3 ( x1 + x2 ) = x1 x3 + x2 x3
x1 x2 + x1 • 1 = x1 + x2
x2 1
3.50. (a)
x1
x1
x1 x2
x2
1
x1 x2 • x3 = x1 x2 + x3
1
x3
1
1
x3
3-21
(b)
x1
x2
x1 x2 x4
x4
x1 x2 x4 • x1 • x2 x3 x4 = x1 x2 x4 + x1 + x2 x3 x4
x1
x2
x3
x2 x3 x4
x4
1
1
3.51.
x4
LIBRARY ieee ;
USE ieee.std logic 1164.all ;
ENTITY prob3 51 IS
PORT ( x1, x2, x3, x4 : IN
STD LOGIC ;
f
: OUT STD LOGIC ) ;
END prob3 51 ;
ARCHITECTURE LogicFunc OF prob3 51 IS
BEGIN
f <= (x2 AND NOT x3 AND NOT x4) OR
(NOT x1 AND x2 AND x4) OR
(NOT x1 AND x2 AND x3) OR (x1 AND x2 AND x3) ;
END LogicFunc ;
3.52.
LIBRARY ieee ;
USE ieee.std logic 1164.all ;
ENTITY prob3 52 IS
PORT ( x1, x2, x3, x4 : IN
STD LOGIC ;
f
: OUT STD LOGIC ) ;
END prob3 52 ;
ARCHITECTURE LogicFunc OF prob3 52 IS
BEGIN
f <= (x1 OR x2 OR NOT x4) AND
(NOT x2 OR x3 OR NOT x4) AND
(NOT x1 OR x3 OR NOT x4) AND
(NOT x1 OR NOT x3 OR NOT x4) ;
END LogicFunc ;
3-22
3.53.
LIBRARY ieee ;
USE ieee.std logic 1164.all ;
ENTITY prob3 53 IS
PORT ( x1, x2, x3, x4, x5, x6, x7 : IN STD LOGIC ;
f
: OUT STD LOGIC ) ;
END prob3 53 ;
ARCHITECTURE LogicFunc OF prob3 53 IS
BEGIN
f <= (x1 AND x3 AND NOT x6) OR
(x1 AND x4 AND x5 AND NOT x6) OR
(x2 AND x3 AND x7) OR
(x2 AND x4 AND x5 AND x7) ;
END LogicFunc ;
3.54. The circuit in Figure P3.10 is a two-input XOR gate. Since NMOS transistors are used only to pass logic 0
and PMOS transistors are used only to pass logic 1, the circuit does nor suffer from any major drawbacks.
3.55. The circuit in Figure P3.11 is a two-input XOR gate. This circuit has two drawbacks: when both inputs are
0 the PMOS transistor must drive f to 0, resulting in f = VT volts. Also, when x1 = 1 and x2 = 0, the
NMOS transistor must drive the output high, resulting in f = VDD , VT .
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