Symbolic Simulation at Register Transfer Level Thesis

۱ ‫ﺩﺍﻧﺸﮕﺎﻩ ﺻﻨﻌﺘﻲ ﺷﺮﻳﻒ‬ ‫ﺩﺍﻧﺸﻜﺪﻩ ﻣﻬﻨﺪﺳﻲ ﻛﺎﻣﭙﻴﻮﺗﺮ‬ ‫ﭘﺎﻳﺎﻥﻧﺎﻣﻪ ﺑﺮﺍﻱ ﺩﺭﻳﺎﻓﺖ ﺩﺭﺟﻪ ﻛﺎﺭﺷﻨﺎﺳﻲ ﺍﺭﺷﺪ‬ ‫ﺩﺭ ﺭﺷﺘﻪ ﻣﻬﻨﺪﺳﻲ ﻛﺎﻣﭙﻴﻮﺗﺮ‪ ،‬ﮔﺮﺍﻳﺶ ﻣﻌﻤﺎﺭﻱ ﺳﻴﺴﺘﻢﻫﺎﻱ ﻛﺎﻣﭙﻴﻮﺗﺮﻱ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ‬ ‫ﻧﮕﺎﺭﺵ‪:‬‬ ‫ﺳﻌﻴﺪ ﻣﻴﺮﺯﺍﺋﻴﺎﻥ‬ ‫ﺍﺳﺘﺎﺩ ﺭﺍﻫﻨﻤﺎ‪:‬‬ ‫ﺩﻛﺘﺮ ﺷﺎﻫﻴﻦ ﺣﺴﺎﺑﻲ‬ ‫ﺍﺳﺘﺎﺩ ﻣﺸﺎﻭﺭ‪:‬‬ ‫ﺩﻛﺘﺮ ﺣﻤﻴﺪ ﺳﺮﺑﺎﺯﯼﺁﺯﺍﺩ‬ ‫ﺗﺎﺑﺴﺘﺎﻥ ‪۱۳۸۳‬‬ ‫‪۲‬‬ ‫ﺑﻪ ﻧﺎﻡ ﺧﺪﺍ‬ ‫ﺩﺍﻧﺸﮕﺎﻩ ﺻﻨﻌﺘﯽ ﺷﺮﻳﻒ‬ ‫ﺩﺍﻧﺸﮑﺪﻩﻱ ﻣﻬﻨﺪﺳﯽ ﮐﺎﻣﭙﻴﻮﺗﺮ‬ ‫ﭘﺎﻳﺎﻥﻧﺎﻣﻪ ﮐﺎﺭﺷﻨﺎﺳﯽ ﺍﺭﺷﺪ‬ ‫ﻋﻨﻮﺍﻥ‪ :‬ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ‬ ‫ﻧﮕﺎﺭﺵ‪ :‬ﺳﻌﻴﺪ ﻣﻴﺮﺯﺍﺋﻴﺎﻥ‬ ‫ﮐﻤﻴﺘﻪ ﻣﻤﺘﺤﻨﻴﻦ‪:‬‬ ‫ﺍﺳﺘﺎﺩ ﺭﺍﻫﻨﻤﺎ‪ :‬ﺩﮐﺘﺮ ﺷﺎﻫﻴﻦ ﺣﺴﺎﺑﯽ‬ ‫ﺍﻣﻀﺎ‪:‬‬ ‫ﺍﺳﺘﺎﺩ ﻣﺸﺎﻭﺭ‪ :‬ﺩﮐﺘﺮ ﺣﻤﻴﺪ ﺳﺮﺑﺎﺯﯼﺁﺯﺍﺩ‬ ‫ﺍﻣﻀﺎ‪:‬‬ ‫ﺍﺳﺘﺎﺩ ﻣﺪﻋﻮ‪ :‬ﺩﮐﺘﺮ‬ ‫ﺍﻣﻀﺎ‪:‬‬ ‫ﺗﺎﺭﻳﺦ‪:‬‬ ‫‪۳‬‬ ‫ﺗﻘﺪﻳﻢ ﺑﻪ ﭘﺪﺭ ﻭ ﻣﺎﺩﺭ ﻋﺰﻳﺰﻡ‬ ‫ﺑﻪ ﭘﺎﺱ ﻣﺤﺒﺖﻫﺎ ﻭ ﻓﺪﺍﮐﺎﺭﻱﻫﺎﻳﺸﺎﻥ‬ ‫ﻭ ﺑﻪ ﺧﻮﺍﻫﺮﻫﺎ ﻭ ﺑﺮﺍﺩﺭ ﻋﺰﻳﺰ‬ ‫ﮐﻪ ﺩﺭ ﺗﻤﺎﻣﻲ ﻣﺮﺍﺣﻞ ﻣﺸﻮﻗﻢ ﺑﻮﺩﻧﺪ‬ ‫ﺃ‬ ‫ﻗﺪﺭﺩﺍﻧﻲ‬ ‫ﺩﺭ ﺍﻳﻨﺠﺎ ﻻﺯﻡ ﺍﺳﺖ ﺍﺯ ﮐﻠﻴﻪ ﺍﻓﺮﺍﺩﻱ ﮐﻪ ﻣﺮﺍ ﺩﺭ ﺍﻧﺠﺎﻡ ﺍﻳﻦ ﭘﺎﻳﺎﻥﻧﺎﻣﻪ ﮐﻤﮏ ﻧﻤﻮﺩﻩﺍﻧﺪ‪ ،‬ﺧﺼﻮﺻـﹲﺎ ﺍﺳـﺘﺎﺩ ﮔﺮﺍﻣـﻲ‬ ‫ﺁﻗﺎﻱ ﺩﮐﺘﺮ ﺷﺎﻫﻴﻦ ﺣﺴﺎﺑﻲ ﻭ ﺟﻨﺎﺏ ﺁﻗﺎﯼ ﺍﻣﻴﺮﺣﺴﻴﻦ ﻗﺮﻩﺑﺎﻏﯽ ﮐﻪ ﺩﺭ ﻣﺮﺍﺣﻞ ﻣﺨﺘﻠﻒ ﺍﻧﺠـﺎﻡ ﺍﻳـﻦ ﭘـﺮﻭﮊﻩ ﺑـﺎ‬ ‫ﻣﺴﺎﻋﺪﺕﻫﺎ ﻭ ﺭﺍﻫﻨﻤﺎﻳﻲﻫﺎﻱ ﺧﻮﺩ ﻣﺮﺍ ﻳﺎﺭﻱ ﮐﺮﺩﻧﺪ‪ ،‬ﺗﺸﮑﺮ ﮐﻨﻢ‪.‬‬ ‫ﺏ‬ ‫ﭼﮑﻴﺪﻩ‪:‬‬ ‫ﺭﻭﺵ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ‪ ،‬ﺭﻭﺷﯽ ﺍﺳﺖ ﮐﻪ ﺩﺭ ﺁﻥ ﺑﺎ ﺗﺮﮐﻴﺐ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻭ ﺭﻭﺷﻬﺎﯼ ﻧﻤﺎﺩﻳﻦ‪ ،‬ﺗﮑﻨﻴﮑـﯽ ﻧﻴﻤـﻪ‪-‬‬ ‫ﺻﻮﺭﯼ ﺟﻬﺖ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﻃﺮﺣﻬﺎ ﺍﺭﺍﻳﻪﻣﻲﺩﻫﺪ‪ .‬ﺍﻳﻦ ﺭﻭﺵ ﮐﻪ ﺍﺳﺎﺳﺎ ﺑﺮﺍﯼ ﻃﺮﺣﻬﺎ ﺩﺭ ﺳﻄﺢ ﮔﻴـﺖ ﻭ ﻳـﺎ ﺩﺭ‬ ‫ﺣﺎﻟﺖ ﮔﺴﺘﺮﺵﻳﺎﻓﺘﻪ ﺑﺮﺍﯼ ﻃﺮﺣﻬﺎ ﺩﺭ ﺳﻄﺢ ﺑﻴﺖ ﮐﺎﺭ ﻣﻲﮐﻨﺪ‪ ،‬ﺑﺎ ﺍﻓﺰﻭﺩﻥ ﻳـﮏ ﻣﻘـﺪﺍﺭ ‪ x‬ﺑـﻪ ﺩﻭ ﻣﻘـﺪﺍﺭ ‪ ۱‬ﻭ ‪۰‬‬ ‫ﻣﻌﻤﻮﻝ ﻣﻨﻄﻘﯽ ﻭ ﺩﺭ ﻧﻈﺮ ﮔﺮﻓﺘﻦ ﺗﺮﺗﻴﺐ ﺑﺮﺍﯼ ﺍﻳﻦ ﺳﻪ ﻣﻘﺪﺍﺭ‪ ،‬ﻗﺪﺭﺕ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻌﻤﻮﻝ ﺭﺍ ﺍﻓﺰﺍﻳﺶ ﻣﻲﺩﻫـﺪ‪.‬‬ ‫ﻳﮏ ﻣﺸﮑﻞ ﺍﺳﺎﺳﯽ ﺍﻳﻦ ﺭﻭﺵ ﮐﺎﺭﮐﺮﺩﻥ ﺩﺭ ﺳﻄﺢ ﺑﻴﺖ ﻣﻲﺑﺎﺷﺪ ﮐﻪ ﺍﺯ ﺁﻥ ﻋﻤـﻼ ﺩﺭ ﺳـﻄﻮﺡ ﺍﻧﺘﻘـﺎﻝ ﺛﺒـﺎﺕ ﻭ‬ ‫ﺑﺎﻻﺗﺮ ﺑﻪ ﺁﺳﺎﻧﯽ ﻧﻤﯽﺗﻮﺍﻥ ﺍﺳﺘﻔﺎﺩﻩ ﮐﺮﺩ‪ .‬ﻫﺪﻑ ﺍﺯ ﺍﻧﺠﺎﻡ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﺍﺭﺍﻳﻪ ﺭﻭﺷﯽ ﺑﺮﺍﯼ ﺷـﺒﻴﻪﺳـﺎﺯﯼ ﻧﻤـﺎﺩﻳﻦ ﺩﺭ‬ ‫ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻭ ﺑﺎﻻﺗﺮ ﺑﺎ ﺩﺭ ﻧﻈﺮ ﮔﺮﻓﺘﻦ ﺁﺭﺍﻳﻪﻫﺎﯼ ﺑﻴﺘﯽ ﺩﺭ ﻋﻤﻞ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻭ ﻫﻤﭽﻨﻴﻦ ﭘﻴﺸﻨﻬﺎﺩ ﺭﻭﺷـﯽ‬ ‫ﺑﺮﺍﯼ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻧﻮﻉ ‪ integer‬ﺑﺮﺍﯼ ﻋﻤﻞ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﮐﻠﻤﺎﺕ ﮐﻠﻴﺪﯼ‪ -۱ :‬ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ‪ -۲‬ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ‬ ‫ﺝ‬ ‫‪ -۳‬ﺩﺭﺳﺘﯽﻳﺎﺑﯽ‬ ‫ﻓﻬﺮﺳﺖ ﻣﻄﺎﻟﺐ‬ ‫‪ -۱‬ﻣﻘﺪﻣﻪ ‪١.......................................................................................................................................‬‬ ‫‪ -۱-۱‬ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ ‪٢ ...................................................................................................................‬‬ ‫‪ -۲-۱‬ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﻮﺭﯼ ‪٤ ......................................................................................................................‬‬ ‫‪ -۱-۲-۱‬ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ‪٤ ..............................................................................................................‬‬ ‫‪ -۳-۱‬ﻫﺪﻑ ﭘﺮﻭﮊﻩ ﻭ ﺳﺎﺧﺘﺎﺭ ﭘﺎﻳﺎﻥﻧﺎﻣﻪ ‪٥ ..................................................................................................‬‬ ‫‪ -۲‬ﻃﺮﺍﺣﻲ ﻭ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺳﻴﺴﺘﻤﻬﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ ‪٦.................................................................................‬‬ ‫‪ -۱-۲‬ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﻲ ‪٦ ..........................................................................................................................‬‬ ‫‪ -۲-۲‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ‪١٠ ...............................................................................................‬‬ ‫‪ -۳-۲‬ﻣﺘﻐﻴﺮ ﻭ ﺗﻮﺍﺑﻊ ﺑﻮﻟﻲ ﻭ ﻧﺤﻮﻩ ﻧﻤﺎﻳﺶ ﺁﻧﻬﺎ ‪١٣ .....................................................................................‬‬ ‫‪١٤ ............................................................................................................................... BDD-۱-۳-۲‬‬ ‫‪ -۴-۲‬ﻣﺪﻟﻬﺎﻱ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺑﺮﺍﻱ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻃﺮﺍﺣﻲ ‪١٧ .........................................................................‬‬ ‫‪ -۱-۴-۲‬ﻣﺪﻝ ﺷﺒﻜﻪ ﺳﺎﺧﺘﺎﺭﻱ ‪١٧ ........................................................................................................‬‬ ‫‪ -۲-۴-۲‬ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ‪١٩ ...................................................................................................................‬‬ ‫‪ -۳-۴-۲‬ﻣﺪﻝ ﺭﻳﺎﺿﻲ ﺑﺮﺍﻱ ‪ FSM‬ﻫﺎ ‪٢٠ ..............................................................................................‬‬ ‫‪ -۵-۲‬ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ ‪٢١ .................................................................................................................‬‬ ‫‪ -۶-۲‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺻﻮﺭﻱ ‪٢٤ ....................................................................................................................‬‬ ‫‪ -۱-۶-۲‬ﭘﻴﻤﺎﻳﺶ ﻧﻤﺎﺩﻳﻦ ﺣﺎﻟﺘﻬﺎ ‪٢٦ ......................................................................................................‬‬ ‫‪ -۷-۲‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ‪٢٨ .....................................................................................................................‬‬ ‫ﺩ‬ ‫‪ -۱-۷-۲‬ﺍﻟﮕﻮﺭﻳﺘﻤﻬﺎﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ‪٢٩ .....................................................................................‬‬ ‫‪ -۲-۷-۲‬ﻣﺸﻜﻼﺕ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ‪٣١ ............................................................................................‬‬ ‫‪ WLDD-۳‬ﻫﺎ‪٣٤ ..............................................................................................................................‬‬ ‫‪ -۱-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻋﻤﻠﻜﺮﺩﻱ )‪٣٤ ............................................... (Functional Decision Diagram‬‬ ‫‪ -۱-۱-۳‬ﺑﺴﻂ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ ﻳﺎ ﺩﺍﻭﻳﻮ ﻣﺜﺒﺖ )‪٣٥ ............................................................ (Positive Davio‬‬ ‫‪ -۲-۱-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪٣٦ .............................................................................................................. FDD‬‬ ‫‪ -۲-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻋﻤﻠﻜﺮﺩﻱ ﻛﺮﻭﻧﻜﺮ )‪٣٧ ........................................................................... (KFDD‬‬ ‫‪ -۱-۲-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪٣٨ ...........................................................................................................KFDD‬‬ ‫‪ ۳-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭﺩﻭﻳﻲ ﭼﻨﺪ ﭘﺎﻳﺎﻧﻪﺍﻱ )‪ (MTBDD‬ﻳﺎ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺟﺒﺮﻱ )‪٣٩ ............. . (ADD‬‬ ‫‪ -۱-۳-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪٤٠ .......................................................................................................MTBDD‬‬ ‫‪ -۴-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭﺩﻭﻳﻲ ﺑﺎ ﻳﺎﻟﻬﺎﻱ ﻭﺯﻥ ﺩﺍﺭ )‪٤٢ ............................................................ (EVBDD‬‬ ‫‪ -۱-۴-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪٤٢ ....................................................................................................... EVBDD‬‬ ‫‪ -۵-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺩﻭﺩﻭﻳﻲ ﻣﻤﺎﻥ ‪٤٤ .................................................................................................... BMD‬‬ ‫‪ -۱-۵-۳‬ﺗﺎﺑﻊ ﺗﺠﺰﻳﻪ ﻣﻤﺎﻥ ‪٤٤ ...............................................................................................................‬‬ ‫‪ -۲-۵-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪٤٥ ............................................................................................................. BMD‬‬ ‫‪ -۶-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭ ﺭﮔﻪ ‪٤٦ .................................................................................................. HDD‬‬ ‫‪ -۱-۶-۳‬ﺗﺸﺎﺑﻪ ‪ MTBDD‬ﻭ‪٤٦ ................................................................................................ BMD‬‬ ‫‪ -۲-۶-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪٤٧ ............................................................................................................. HDD‬‬ ‫‪ -۷-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﻣﻤﺎﻥ ﺩﻭﺩﻭﻳﻲ ﺿﺮﺑﻲ )‪٤٨ .................................................................................... (*BMD‬‬ ‫‪ -۱-۷-۳‬ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ‪٤٨ ......................................................................................................... *BMD‬‬ ‫ﻩ‬ ‫‪ -۸-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﻣﻤﺎﻥ ﺩﻭﺩﻭﻳﻲ ﺿﺮﺑﻲ ﻛﺮﺍﻧﻜﺮ ‪٤٩ ..................................................................... K * BMD‬‬ ‫‪ -۹-۳‬ﺟﻤﻊﺑﻨﺪﻱ ﻭ ﻣﻘﺎﻳﺴﻪ ‪WLDD‬ﻫﺎ ‪٥٠ ................................................................................................‬‬ ‫‪ TED-۴‬ﻭ ‪٥٢ ...................................................................................................................... CTED‬‬ ‫‪ -۱-۴‬ﺩﻳﺎﮔﺮﺍﻡ ﺑﺴﻂ ﺗﻴﻠﻮﺭ )‪٥٣ ....................................................................................................... (TED‬‬ ‫‪ -۱-۱-۴‬ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ‪٥٤ ............................................................................................................. TED‬‬ ‫‪ -۲-۱-۴‬ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ )ﺑﺮﺍﻱ ﻋﻤﻠﮕﺮﻫﺎﻱ ﺿﺮﺏ ﻭ ﺟﻤﻊ(‪٥٦ ..............................................................‬‬ ‫‪ TED-۳-۱-۴‬ﻛﺎﻫﺶ ﻳﺎﻓﺘﻪ ‪٥٨ ............................................................................................................‬‬ ‫‪ -۴-۱-۴‬ﻧﻤﺎﻳﺶ ﺗﻮﺍﺑﻊ ﺑﻮﻟﻲ ﻭ ﺑﻮﻟﻲ‪-‬ﺟﺒﺮﻱ ﺑﺎ ﻛﻤﻚ ‪٥٩ ............................................................ TED‬‬ ‫‪ -۵-۱-۴‬ﻛﺎﺭﺑﺮﺩ‪ TED‬ﺩﺭ ﺩﺭﺳﺘﻲ ﻳﺎﺑﻲ‪٥٩ .............................................................................................‬‬ ‫‪٦٠ ...................................................................................................................................... CTED-۲-۴‬‬ ‫‪ -۱-۲-۴‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪٦١ ........................................................................................................... CTED‬‬ ‫‪ -۲-۲-۴‬ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ ‪٦٢ ...................................................................................................... CTED‬‬ ‫‪ -۵‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﭘﺮﻭﮊﻩ ‪٦٤ ...................................................................................................................‬‬ ‫‪ -۱-۵‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺷﺒﻴﻪﺳﺎﺯ ﻣﻨﻄﻘﻲ ﻭ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﺳﻄﺢ ﮔﻴﺖ‪٦٥ .................................................................‬‬ ‫‪ -۲-۵‬ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺷﺒﻴﻪﺳﺎﺯ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ‪٦٦ ......................................................................‬‬ ‫‪ -۱-۲-۵‬ﺳﺎﺧﺖ ﻳﻚ ﻟﻴﺴﺖ ﮔﺮﻩﻫﺎﻱ ﺳﻴﺴﺘﻢ ‪٦٧ ..................................................................................‬‬ ‫‪ -۲-۲-۵‬ﺳﺎﺧﺖ ﻟﻴﺴﺖ ﺑﻠﻮﻛﻬﺎﻱ ‪٦٨ ...................................................................................... always‬‬ ‫‪ -۳-۲-۵‬ﺳﺎﺧﺖ ‪ TED‬ﺑﻠﻮﻛﻬﺎﻱ‪٦٩ ........................................................................................ always‬‬ ‫‪ -۱-۳-۲-۵‬ﺍﻟﮕﻮﻱ ﻓﺎﻳﻠﻬﺎﻱ ‪٦٩ ......................................................................................... :always‬‬ ‫‪ -۲-۳-۲-۵‬ﺣﺬﻑ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ‪٧٠ ...........................................................................................‬‬ ‫ﻭ‬ ‫‪٧٣ ........................................................................................................... precompile-۳-۳-۲-۵‬‬ ‫‪ -۴-۳-۲-۵‬ﺩﺭﺧﺘﻬﺎﻱ‪٧٦ ....................................................................................................... :TED‬‬ ‫‪ -۴-۲-۵‬ﻣﺮﺗﺐ ﻛﺮﺩﻥ ﺑﻠﻮﻛﻬﺎﻱ ‪٨١ ......................................................................................... always‬‬ ‫‪ -۵-۲-۵‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﻣﺪﺍﺭ ‪٨١ ................................................................................................................‬‬ ‫‪ -۳-۵‬ﺗﺴﺖ ﺷﺒﻴﻪ ﺳﺎﺯ ‪٨٣ ..........................................................................................................................‬‬ ‫‪ -۱-۳-۵‬ﻣﺪﺍﺭ ﺑﺎ ﻗﺴﻤﺖ ﻛﻨﺘﺮﻟﻲ ﺑﻮﻟﻲ ﻭ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺟﺒﺮﻱ ‪٨٣ ...............................................................‬‬ ‫‪ -۲-۳-۵‬ﻣﺪﺍﺭ ﺑﺎ ﻗﺴﻤﺖ ﻛﻨﺘﺮﻟﻲ ﻭ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺳﻄﺢ ﻛﻠﻤﻪ ‪٨٦ ................................................................‬‬ ‫‪ -۳-۳-۵‬ﭘﺮﺩﺍﺯﻧﺪﻩﻱ ‪٨٨ ......................................................................................................... Parwan‬‬ ‫‪ -۶‬ﻧﺘﻴﺠﻪﮔﻴﺮﯼ ﻭ ﭘﻴﺸﻨﻬﺎﺩﺍﺕ ﺁﻳﻨﺪﻩ ‪٩٣ ................................................................................................‬‬ ‫ﮐﺘﺎﺑﻨﺎﻣﻪ‪٩٥ ........................................................................................................................................‬‬ ‫ﭘﻴﻮﺳﺘﻬﺎ ‪٩٧ .......................................................................................................................................‬‬ ‫ﭘﻴﻮﺳﺖ ﺍﻟﻒ ‪٩٧ .........................................................................................................................................‬‬ ‫ﭘﻴﻮﺳﺖ ﺏ ‪١٠٠.........................................................................................................................................‬‬ ‫ﭘﻴﻮﺳﺖ ﭖ ‪١٠٣.........................................................................................................................................‬‬ ‫ﺯ‬ ‫ﻓﻬﺮﺳﺖ ﺷﮑﻠﻬﺎ‪:‬‬ ‫ﺷﮑﻞ ‪۱-۲‬ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﯽ ﻳﮏ ﻣﺪﺍﺭ ﻣﺠﺘﻤﻊ ﺩﻳﺠﻴﺘﺎﻝ ‪٧ ................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۲-۲‬ﻣﻘﺎﻳﺴﻪ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻨﻄﻘﯽ ﻭ ﺩﺭﺳﺘﯽﻳﺎﺑﻲ ‪١٣ ...............................................................................‬‬ ‫ﺷﮑﻞ ‪ BDD -۳-۲‬ﻣﻌﺎﺩﻝ ﺗﻮﺍﺑﻊ )‪ f = (x + y )( p + q‬ﻭ ‪١٤ ............................................ G = w ⊕ x ⊕ y ⊕ z‬‬ ‫ﺷﮑﻞ ‪ -۴-۲‬ﻣﺪﻝ ﺷﺒﮑﻪ ﺳﺎﺧﺘﺎﺭﯼ ‪١٧ .............................................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۵-۲‬ﻣﺪﻝ ﺷﺒﮑﻪﺍﻱ ﺷﻤﺎﺭﻧﺪﻩ ﺳﻪ ﺑﻴﺘﯽ ‪١٨ ............................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۶-۲‬ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﻣﻮﺭ ﺑﺮﺍﯼ ﺷﻤﺎﺭﻧﺪﻩﻱ ﺳﻪ ﺑﻴﺘﻲ ‪١٩ .......................................................................‬‬ ‫ﺷﮑﻞ ‪ -۷-۲‬ﻣﺪﺍﺭ ﻣﺜﺎﻝ ‪ ۲-۲‬ﮐﻪ ﺑﺮﺍﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﺮﺗﺐ ﺷﺪﻩﺍﺳﺖ‪٢١ .............................................................‬‬ ‫ﺷﮑﻞ ‪ -۸-۲‬ﻣﻘﺎﻳﺴﻪ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﻭ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻨﻄﻘﯽ ‪٢٨ ....................................................................‬‬ ‫ﺷﮑﻞ ‪ -۹-۲‬ﻣﺪﻝ ﺗﮑﺮﺍﺭﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ‪٣١ ............................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۱-۳‬ﺩﺭﺧﺖ ‪ FDD‬ﻣﻌﺎﺩﻝ ﺗﺎﺑﻊ ‪٣٦ ........................................ f = a • b • d + b • c • d + b • c • d‬‬ ‫ﺷﮑﻞ ‪ -۲-۳‬ﮔﺮﺍﻑ ﮐﺎﻫﺶﻳﺎﻓﺘﻪ ﺩﺭﺧﺖ ﺷﮑﻞ ‪٣٧ ................................................................................... ۱-۳‬‬ ‫ﺷﮑﻞ ‪ MTBDD -۳-۳‬ﺗﺎﺑﻊ ‪f‬ﻭ ‪ g‬ﻭ ﺗﺮﮐﻴﺐ ﺁﻧﻬﺎ ﺑﺮ ﺍﺳﺎﺱ ﺭﺍﺑﻄﻪﻱ ‪٤١ ................................................ xj , xi‬‬ ‫ﺷﮑﻞ ‪ -۴-۳‬ﺟﺪﻭﻝ ﺩﺭﺳﺘﯽ ﻭ ‪ MTBDD‬ﺗﺎﺑﻊ ‪٤١ ...................................... f ( z, y ) = 8 − 20 z + 2 y + 4 zy‬‬ ‫ﺷﮑﻞ ‪ -۵-۳‬ﺟﺪﻭﻝ ﺩﺭﺳﺘﯽ ﻭ ‪ EVBDD‬ﺗﺎﺑﻊ ‪٤٣ ..................................... f ( x2 , x1 , x0 ) = 4 x2 + 2 x1 + x0‬‬ ‫ﺷﮑﻞ ‪ BMD -۶-۳‬ﺗﺎﺑﻊ ‪٤٥ ....................................................................... f ( z, y) = 8 − 20 z + 2 y + 4 zy‬‬ ‫ﺷﮑﻞ ‪ BMD -۷-۳‬ﺑﺎﺿﺮﺍﻳﺐ ﺻﺤﻴﺢ ﻭ ﺣﻘﻴﻘﻲ ﺗﺎﺑﻊ ‪٤٩ .. f ( x, y, z) = 8 − 20z + 2 y + 4 yz + 12x + 24xz + 15xy‬‬ ‫ﺷﮑﻞ ‪ K*BMD -۸-۳‬ﻋﺪﺩ ﺑﺎﻳﻨﺮﻱ ‪٥٠ ........................................................................................ x0 x1 x2 x3‬‬ ‫ﺷﮑﻞ ‪ -۱-۴‬ﮔﺮﻩ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ ﺩﺭ ﮔﺮﺍﻑ ‪٥٥ .............................................................................................. TED‬‬ ‫ﺷﮑﻞ ‪ TED -۲-۴‬ﻣﻌﺎﺩﻝ ﺗﻮﺍﺑﻊ ‪ X 2‬ﻭ ) ‪٥٥ ....................................................................... ( A + B)( A + 2C‬‬ ‫ﺡ‬ ‫ﺷﮑﻞ ‪ -۳-۴‬ﺳﺎﺧﺖ ﺗﺎﺑﻊ ) ‪ ( A + B)( A + 2C‬ﺑﺎ ﮐﻤﮏ ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ‪٥٧ .......................................................‬‬ ‫ﺷﮑﻞ ‪ -۴-۴‬ﻣﺪﺍﺭ ﻣﻌﺎﺩﻝ ﺗﻮﺍﺑـﻊ ‪ F1 = s1 ( A + B )( A − B ) + (1 − s1 ) D‬ﻭ ) ‪ F2 = s 2 D + (1 − s 2 )( A 2 − B 2‬ﻭ ‪TED‬‬ ‫ﻣﻌﺎﺩﻝ ‪٦٠ ..............................................................................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۵-۴‬ﺑﺎﺯﻧﻮﻳﺴﯽ ﻳﮏ ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﺩﺭ ‪٦١ ............................................................................. CTED‬‬ ‫ﺷﮑﻞ ‪ -۱-۵‬ﮐﺪ ﻳﮏ ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﻭ ﻣﻌﺎﺩﻝ ﺁﻥ ‪٧١ .......................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۲-۵‬ﮐﺪ ﻳﮏ ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﺗﻮﺩﺭﺗﻮ ﻭ ﻣﻌﺎﺩﻝ ﺁﻥ ‪٧٢ ...........................................................................‬‬ ‫ﺷﮑﻞ ‪ -۳-۵‬ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﺑﺎ ﻣﻘﺪﺍﺭ ﺩﻫﯽ ﺿﺮﺑﺪﺭﯼ ‪٧٢ .................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۴-۵‬ﻓﺮﺁﻳﻨﺪ ﺗﺎﺑﻊ ‪ compile‬ﺑﺮﺍﯼ ﻳﮏ ﻋﺒﺎﺭﺕ ‪٧٥ ...............................................................................‬‬ ‫ﺷﮑﻞ ‪ -۵-۵‬ﺷﮑﻞ ﻣﻌﺎﺩﻝ ﻗﺎﻋﺪﻩ ﺩﻭﻡ ﺗﺮﮐﻴﺐ ﺿﺮﺏ ‪٨٠ ..................................................................................‬‬ ‫ﺷﮑﻞ ‪ -۶-۵‬ﺣﺬﻑ ﺗﻮﺍﻥ ﺑﻴﺸﺘﺮ ﺍﺯ ﻳﮏ ﺑﺮﺍﯼ ﻣﺘﻐﻴﺮﻫﺎﯼ ﺑﻮﻟﯽ ‪٨٠ .....................................................................‬‬ ‫ﻁ‬ ‫ﻓﻬﺮﺳﺖ ﺟﺪﻭﻟﻬﺎ‪:‬‬ ‫ﺟﺪﻭﻝ ‪ -۱-۳‬ﺍﻧﺪﺍﺯﻩﻱ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ ﺳﻄﺢ ﻛﻠﻤﻪ ﻣﺘﻔﺎﻭﺕ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺟﺒﺮﻱ ﻣﻌﻤﻮﻝ‪٥١ ..................‬‬ ‫ﺟﺪﻭﻝ ‪ ۱-۵‬ﻣﺠﻤﻮﻋﻪ ﺩﺳﺘﻮﺭﺍﺕ ﭘﺮﺩﺍﺯﻧﺪﻩ ‪٩٠ ................................................................................... parwan‬‬ ‫ﻱ‬ ‫‪ -۱‬ﻣﻘﺪﻣﻪ‬ ‫ﺩﺭ ﺩﻫﻪﻱ ﮔﺬﺷﺘﻪ ﺻﻨﻌﺖ ﻧﻴﻤﻪﺭﺳﺎﻧﺎﻫﺎ ﺑﺎ ﻣﺸﮑﻞ ﺟﺪﻳﺪﯼ ﺩﺭ ﺳﺎﺧﺖ ﻣﺪﺍﺭﻫﺎﯼ ﻣﺠﺘﻤﻊ ﻣﻮﺍﺟﻪ ﺷﺪﻩ ﺍﺳـﺖ‪ .‬ﺍﺯ‬ ‫ﻳﮏﺳﻮ ﺍﻓﺰﺍﻳﺶ ‪ integration density‬ﻭ ﺳﺎﻳﺰ ‪ die‬ﺑﺎﻋﺚ ﻃﺮﺍﺣﯽ ﺗﺮﺍﺷﻪﻫﺎﻳﯽ ﺑﺎ ﺻﺪﻫﺎ ﻣﻴﻠﻴـﻮﻥ ﺗﺮﺍﻧﺰﻳﺴـﺘﻮﺭ‬ ‫ﺷﺪﻩ ﺍﺳﺖ ﻭ ﺍﺯ ﺳﻮﯼ ﺩﻳﮕﺮ ﻓﺸﺎﺭ ﺑﺎﺯﺍﺭ ﺑﺮ ﮔﺮﻭﻩ ﻃﺮﺍﺣﯽ ﺑﺮﺍﯼ ﺍﺭﺳﺎﻝ ﺳـﺮﻳﻌﺘﺮ ﻣﺤﺼـﻮﻻﺕ ﺟﺪﻳـﺪ ﺍﻓـﺰﺍﻳﺶ‬ ‫ﻳﺎﻓﺘﻪ ﺍﺳﺖ‪ ،‬ﺗﺎ ﺁﻧﺠﺎ ﮐﻪ ﺯﻣﺎﻥ ﻣﺘﻮﺳﻂ ﻋﺮﺿﻪﻱ ﻓﻦﺁﻭﺭﯼ ﺟﺪﻳﺪ ﺑﻪ ‪ ۲‬ﺳﺎﻝ ﺭﺳﻴﺪﻩ ﺍﺳﺖ‪ .‬ﺑﻪ ﺩﻟﻴﻞ ﺍﻳـﻦ ﻓﺮﺻـﺖ‬ ‫ﺍﻧﺪﮎ‪ ،‬ﺍﻃﻤﻴﻨﺎﻥ ﺍﺯ ﺍﻳﻦﮐﻪ ﻣﺪﺍﺭﻫﺎﯼ ﻣﺠﺘﻤﻊ ﻃﺮﺍﺣﯽ ﺷﺪﻩ‪ ،‬ﮐﺎﺭﮐﺮﺩ ﺩﺭﺳﺘﯽ ﺩﺍﺭﻧﺪ ﺑﻪ ﻳﮏ ﻣﺴﺎﻟﻪ ﺣﻴـﺎﺗﯽ ﺗﺒـﺪﻳﻞ‬ ‫ﺷﺪﻩﺍﺳﺖ‪ .‬ﻳﮏ ﺧﻄﺎ ﺩﺭ ﻃﺮﺍﺣﯽ ﻣﻲﺗﻮﺍﻧﺪ ﻋﺮﺿﻪ ﻣﺤﺼﻮﻝ ﺭﺍ ﺗﺎ ﭼﻨﺪ ﻣﺎﻩ ﺑﻪ ﺗﺎﺧﻴﺮ ﺑﻴﺎﻧﺪﺍﺯﺩ‪ .‬ﺍﻫﻤﻴـﺖ ﻣﻮﺿـﻮﻉ‬ ‫ﺩﺭ ﺍﻳﻨﺠﺎ ﻣﺸﺨﺺ ﻣﻲﺷﻮﺩ ﮐﻪ ﺑﻌﻀﯽ ﺍﺯ ﺍﻳﻦ ﻣﺪﺍﺭﻫﺎﯼ ﻣﺠﺘﻤﻊ ﺩﺭ ﺳﻴﺴﺘﻤﻬﺎﻳﯽ ﺑﻪﮐﺎﺭ ﻣـﯽﺭﻭﻧـﺪ ﮐـﻪ ﺧﻄـﺎ ﺩﺭ‬ ‫ﺁﻧﻬﺎ ﻣﻤﮑﻦ ﺍﺳﺖ ﺑﺎﻋﺚ ﺁﺳﻴﺒﻬﺎﯼ ﺟﺎﻧﯽ ﮔﺮﺩﺩ‪ .‬ﺑﻪ ﺩﻟﻴﻞ ﺍﻫﻤﻴﺖ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ‪ ،‬ﺑﺨﺶ ﺍﻋﻈﻤـﯽ ﺍﺯ ﻣﻨـﺎﺑﻊ ﻭ ﺯﻣـﺎﻥ‬ ‫ﻃﺮﺍﺣﯽ ﻭ ﺳﺎﺧﺖ ﺗﺮﺍﺷﻪ ﺻﺮﻑ ﺁﻥ ﻣﻲﺷﻮﺩ]‪.[۱‬‬ ‫ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻃﺮﺡ ﺷﺎﻣﻞ ﺗﻄﺒﻴﻖ ﮐﺎﺭﮐﺮﺩ ﻃﺮﺡ ﺍﻭﻟﻴﻪ ﻣﺪﺍﺭ ﺑﺎ ﺗﻮﺻﻴﻒ‪ ١‬ﻣﻄﻠﻮﺏ ﻣﯽﺑﺎﺷﺪ ﻭ ﮐﻠﻴﻪﯼ ﺍﻋﻤﺎﻟﯽ ﺭﺍ ﮐﻪ‬ ‫ﺑﺮﺍﯼ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻥ ﺍﻃﻤﻴﻨﺎﻥ ﺍﺯ ﺩﺭﺳﺖ ﮐﺎﺭ ﮐﺮﺩﻥ ﻣﺪﺍﺭ ‪-‬ﺑﺎ ﻓﺮﺽ ﻧﺒﻮﺩ ﺧﻄـﺎﯼ ﺳـﺎﺧﺖ‪ -‬ﺍﻧﺠـﺎﻡ ﻣـﻲﺷـﻮﺩ‪،‬‬ ‫‪Specification 1‬‬ ‫‪۱‬‬ ‫ﺩﺭﺑﺮﻣﯽﮔﻴﺮﺩ‪ .‬ﺍﻳﻦ ﮐﺎﺭ ﺑﻪ ﻣﺮﻭﺭ ﺯﻣﺎﻥ ﭘﻴﭽﻴﺪﻩﺗﺮ ﻣﻲﺷﻮﺩ ﺑﻪ ﻧﺤﻮﯼ ﮐﻪ ﭼﻨﺪﻳﻦ ﺗﻴﻢ ﻃﺮﺍﺣﯽ ﺗﺮﺍﺷﻪ ‪ %۸۰‬ﺍﺯ ﺯﻣﺎﻥ‬ ‫ﻃﺮﺍﺣﯽ ﺭﺍ ﺑﺮﺍﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﺮﻑ ﮐﺮﺩﻩﺍﻧﺪ‪ .‬ﺑﺮﺍﯼ ﻣﺜﺎﻝ ﭘﺮﺩﺍﺯﻧﺪﻩ ‪ Pentium IV‬ﺑﻴﺶ ﺍﺯ ‪ ۲۰۰‬ﻣﻴﻠﻴﺎﺭﺩ ﭼﺮﺧـﻪ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﺷﺪﻩﺍﺳﺖ‪ ،‬ﻭﻟﻲ ﺑﻪ ﻓﺮﺽ ﻓﺮﮐﺎﻧﺲ ‪ GHz۱‬ﺑﺮﺍﯼ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺗﻨﻬـﺎ ‪ ۲‬ﺩﻗﻴﻘـﻪ ﮐـﺎﺭﻱ ﺍﻳـﻦ ﺗﺮﺍﺷـﻪ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﺷﺪﻩﺍﺳﺖ‪ .‬ﺩﻟﻴﻞ ﺍﻳﻦ ﻣﺴﺎﻟﻪ ﭘﻴﺸﺮﻓﺖ ﺍﻧﺪﮎ ﺩﺭ ﺯﻣﻴﻨﻪﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺑﺎ ﻭﺟﻮﺩ ﺭﺷﺪ ﺳﺮﻳﻊ ﭘﻴﭽﻴﺪﮔﯽ‬ ‫ﻃﺮﺍﺣﯽ ﺍﺳﺖ‪.‬‬ ‫ﻗﺴﻤﺘﯽ ﺍﺯ ﺍﻳﻦ ﻣﺼﺮﻑ ﺑﺎﻻﯼ ﻣﻨﺎﺑﻊ ﺑﻪ ﺩﻟﻴﻞ ﺗﺠﺮﺑﯽ ﺑﻮﺩﻥ ﺭﻭﺷﻬﺎﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻣﯽﺑﺎﺷﺪ؛ ﺗﻘﺮﻳﺒـﺎ ﻫـﻴﭻ ﺭﻭﺵ‬ ‫ﺍﺳﺘﺎﻧﺪﺍﺭﺩﯼ ﺑﺮﺍﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻭﺟﻮﺩ ﻧﺪﺍﺭﺩ ﻭ ﺗﻤﺎﻣﯽ ﺭﻭﺷﻬﺎﯼ ﻣﻮﺟﻮﺩ ﺑﻪ ﺻﻮﺭﺕ ﻏﻴـﺮ ﺧﻮﺩﮐـﺎﺭ ﻣـﯽﺑﺎﺷـﻨﺪ‪.‬‬ ‫ﺩﻟﻴﻞ ﺩﻳﮕﺮ ﻋﺪﻡ ﭘﺸﺘﻴﺒﺎﻧﯽ ﮐﺎﻓﯽ ﺍﺯ ﺳﻮﯼ ﺻﻨﺎﻳﻊ ﺧﻮﺩﮐﺎﺭﺳﺎﺯﻱ ﻃﺮﺍﺣﯽ‪ ٢‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﺻﻨﺎﻳﻊ ﺩﺭ ﻗﺴﻤﺖ ﺳﻨﺘﺰ‬ ‫ﭘﻴﺸﺮﻓﺖ ﻣﻨﺎﺳﺒﯽ ﺩﺍﺷﺘﻪﺍﻧﺪ ﻭ ﻣﻲﺗﻮﺍﻧﻨﺪ ﭘﺎﺳﺨﮕﻮﯼ ﻃﺮﺍﺣﻴﻬﺎﯼ ﭘﻴﭽﻴﺪﻩ ﺍﻣﺮﻭﺯﯼ ﺑﺎﺷﻨﺪ‪ ،‬ﻭﻟﯽ ﺑﺎ ﻭﺟـﻮﺩ ﺍﻳـﻦ ﺩﺭ‬ ‫ﻗﺴﻤﺖ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺗﻘﺮﻳﺒﺎ ﻫﻴﭻ ﺗﻼﺷﻲ ﻧﺸﺪﻩﺍﺳﺖ ﻭ ﺗﻨﻬﺎ ﺍﺑﺰﺍﺭ ﭘﺮﮐﺎﺭﺑﺮﺩ ﺩﺭ ﺍﻳﻦ ﻗﺴﻤﺖ ﺷﺒﻴﻪﺳﺎﺯﻫﺎﯼ ﻣﻨﻄﻘﯽ‬ ‫ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﺍﻳﻦﮔﻮﻧﻪ ﺷﺒﻴﻪﺳﺎﺯﻫﺎ ﺍﺑﺰﺍﺭ ﺍﺻﻠﯽ ﺗﻴﻢ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺑﺮﺍﯼ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻥ ﺩﺭﮎ ﮐﻠﻲ ﺍﺯ ﺳﻴﺴـﺘﻢ ﻣـﻮﺭﺩ‬ ‫ﻧﻈﺮ ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻦ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯﻫﺎ ﻧﻤﯽﺗﻮﺍﻧﻨﺪ ﺩﺭﺳﺖ ﺑﻮﺩﻥ ﻫﻴﭻ ﺟﻨﺒﻪﺍﯼ ﺍﺯ ﻃﺮﺍﺣﯽ ﺭﺍ ﺗﻀﻤﻴﻦ ﮐﻨﻨﺪ‪.‬‬ ‫‪ -۱-۱‬ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ‬ ‫ﻣﻬﻨﺪﺳﺎﻥ ﺑﺮﺍﻱ ﺍﻃﻤﻴﻨﺎﻥ ﺍﺯ ﺩﺭﺳﺖ ﺑﻮﺩﻥ ﻋﻤﻠﮑﺮﺩ ﻃﺮﺍﺣﯽ ‪ ،‬ﻣﺠﻤﻮﻋﻪﺍﻱ ﺍﺯ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﻃﺮﺍﺣﻲ ﻣﻲﻛﻨﻨـﺪ‪.‬‬ ‫ﺳﭙﺲ ﺁﻧﻬﺎ ﺭﺍ ﺑﻪ ﻣﺪﻝ ﻃﺮﺡ ﺧﻮﺩ ﺍﻋﻤﺎﻝ ﻣﻲﻛﻨﻨﺪ ﻭ ﻧﺘﺎﻳﺞ ﺍﻳﻦ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺭﺍ ﺑﺎ ﻧﺘﺎﻳﺞ ﺩﻟﺨﻮﺍﻩ ﻣﻘﺎﻳﺴﻪ ﻣﻲﻛﻨﻨـﺪ‪.‬‬ ‫ﻫﺮ ﭼﻨﺪ ﺍﻳﻦ ﺭﻭﺵ ﺩﺍﺭﺍﯼ ﻣﺤﺪﻭﺩﻳﺘﻬﺎﻱ ﺑﺴﻴﺎﺭﻱ ﻣﻲﺑﺎﺷـﺪ‪ ،‬ﺍﻣـﺎ ﺍﻣـﺮﻭﺯﻩ ﺗﻨﻬـﺎ ﺭﻭﺵ ﻣﻮﺟـﻮﺩ ﺑـﺮﺍﻱ ﺑﺮﺭﺳـﻲ‬ ‫ﻋﻤﻠﻜﺮﺩ ﻣﺪﺍﺭﻫﺎﻱ ﻣﺠﺘﻤﻊ ﺍﻳﻨﮕﻮﻧﻪ ﺷﺒﻴﻪﺳﺎﺯﻳﻬﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﻟﻴﻞ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺷـﺒﻴﻪ ﺳـﺎﺯﻫﺎﻱ ﻣﻨﻄﻘـﻲ ﺑـﻪ ﻋﻨـﻮﺍﻥ‬ ‫ﺭﻭﺵ ﺍﺻﻠﻲ ﺑﺮﺍﻱ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﺳﻴﺴﺘﻤﻬﺎﻱ ﻫﻤﮕﺎﻡ‪ ،‬ﻗﺎﺑﻠﻴﺖ ﺑﺴﻂﭘﺬﻳﺮﻱ‪ ٣‬ﺁﻧﻬﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻳﻌﻨـﻲ ﺯﻣـﺎﻥ ﺍﺟـﺮﺍﻱ‬ ‫‪Design Automation 2‬‬ ‫‪Scalability 3‬‬ ‫‪۲‬‬ ‫ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﺑﺎ ﺍﻧﺪﺍﺯﻩ ﻃﺮﺡ ﻭ ﺗﻌﺪﺍﺩ ﺁﺯﻣﻮﻧﻬﺎ ﻧﺴﺒﺖ ﻣﺴﺘﻘﻴﻢ ﺩﺍﺭﺩ‪ .‬ﺍﺯ ﺳﻮﻱ ﺩﻳﮕﺮ ﺷﺒﻴﻪﺳـﺎﺯﻫﺎ ﺑﺴـﻴﺎﺭ ﺍﻧﻌﻄـﺎﻑ‬ ‫ﭘﺬﻳﺮ ﻫﺴﺘﻨﺪ؛ ﻳﻌﻨﯽ ﺍﺯ ﻳﻚ ﺳﻮ ﺷﺒﻴﻪﺳﺎﺯﻫﺎﻱ ﻣﺒﺘﻨﻲ ﺑﺮ ﺭﻭﻳﺪﺍﺩ ﺑﻪ ﺳﻴﺴﺘﻢ ﺍﺟﺎﺯﻩ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﭼﻨﺪ ﭘﺎﻟﺲ ﺳـﺎﻋﺖ‬ ‫ﻣﻲﺩﻫﻨﺪ ﻭ ﺍﺯ ﺳﻮﻱ ﺩﻳﮕﺮ ﻣﻲﺗﻮﺍﻥ ﺷﺒﻴﻪﺳﺎﺯﻫﺎﻱ ﻣﺒﺘﻨﻲ ﺑﺮ ﺭﻭﻳﺪﺍﺩ ﻭ ﻣﺒﺘﻨﻲ ﺑﺮ ﭼﺮﺧﻪ ﺭﺍ ﺑﺎ ﻫـﻢ ﺗﺮﻛﻴـﺐ ﻛـﺮﺩ‪.‬‬ ‫ﻣﺘﺎﺳﻔﺎﻧﻪ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯﻫﺎ ﺗﻨﻬﺎ ﻣﻲﺗﻮﺍﻧﻨﺪ ﺑﺨﺶ ﻛﻮﭼﻜﻲ ﺍﺯ ﻛﻞ ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﻃﺮﺡ ﺭﺍ ﺑﺮﺭﺳﻲ ﻛﻨﻨﺪ‪ ،‬ﺑﻪ ﺧﺼـﻮﺹ‬ ‫ﺍﮔﺮ ﻃﺮﺍﺣﻲ ﺑﺰﺭﮒ ﻭ ﭘﻴﭽﻴﺪﻩ ﺑﺎﺷﺪ‪ .‬ﺯﻳﺮﺍ ﺩﺭ ﻫﺮ ﭼﺮﺧﻪ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺗﻨﻬﺎ ﻳﻚ ﺗﺮﻛﻴﺐ ﻭﺭﻭﺩﻱ ﻭ ﻓﻀﺎﻱ ﺣﺎﻟـﺖ‬ ‫ﺑﺮﺭﺳﻲ ﻣﻲﺷﻮﺩ‪ .‬ﺍﺯ ﺳﻮﻱ ﺩﻳﮕﺮ ﻃﺮﺍﺡ ﺑﺎﻳﺪ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﺭﺍ ﺑﺮﺍﻱ ﺑﺮﺭﺳﻲ ﺑﺨﺶ ﻣﻮﺭﺩﻧﻈﺮ ﺍﺯ ﻓﻀﺎﻱ ﺣﺎﻟﺖ‬ ‫ﺳﻴﺴﺘﻢ ﺑﻪ ﺻﻮﺭﺕ ﺩﺳﺘﻲ ﻃﺮﺍﺣﻲ ﻛﻨﺪ‪.‬‬ ‫ﻱ ﮐﻠﻴﻪﻱ ﺗﺮﺗﻴﺒﻬﺎﻱ ﻣﻤﻜﻦ ﻭﺭﻭﺩﻱ ﺑﺮﺍﻱ ﻳﻚ ﺳﻴﺴﺘﻢ ﺑﺰﺭﮒ ﻭ ﭘﻴﭽﻴﺪﻩ ﻏﻴﺮﻣﻤﻜﻦ ﺍﺳﺖ‪ .‬ﻣﻌﻴـﺎﺭ‬ ‫ﻼ ﺷﺒﻴﻪﺳﺎﺯ ِ‬ ‫ﻋﻤ ﹰ‬ ‫ﺻﻨﻌﺘﻲ ﺑﺮﺍﻱ ﺍﻧﺪﺍﺯﻩﮔﻴﺮﻱ ﻛﻴﻔﻴﺖ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻳﻚ ﻃﺮﺡ‪ ،‬ﻣﻴﺰﺍﻥ ﭘﻮﺷﺶ ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﺳﻴﺴﺘﻢ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺩﺭ‬ ‫ﺍﻳﻦ ﺭﻭﺵ ﺗﻌﺪﺍﺩ ﺣﺎﻻﺗﻲ ﺍﺯ ﺳﻴﺴﺘﻢ ﻛﻪ ﺑﺮﺭﺳﻲ ﺷﺪﻩﺍﻧﺪ ﺷﻤﺎﺭﺵ ﻣﻲﺷﻮﺩ‪ ،‬ﻛـﻪ ﺩﺭ ﺻـﻮﺭﺕ ﺍﻃـﻼﻉ ﺍﺯ ﺍﻧـﺪﺍﺯﻩ‬ ‫ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﻳﺎ ﺗﻌﺪﺍﺩ ﺣﺎﻟﺘﻬﺎﻱ ﻗﺎﺑﻞ ﺩﺳﺘﺮﺳﻲ ﺳﻴﺴﺘﻢ‪ ،‬ﻣﻴﺰﺍﻥ ﭘﻮﺷﺶ ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑـﻪ ﺻـﻮﺭﺕ‬ ‫ﻳﻚ ﻧﺴﺒﺖ ﺑﺪﺳﺖ ﺁﻭﺭﺩ‪.‬‬ ‫ﻳﻜﻲ ﺍﺯ ﻣﻬﻤﺘﺮﻳﻦ ﻣﻌﺎﻳﺐ ﺭﻭﺵ ﺷﺒﻴﻪﺳﺎﺯﻱ‪ ،‬ﻃﺮﺍﺣﻲ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺗﻮﺻﻴﻒ ﺳﻴﺴﺘﻢ ﻣـﻲﺑﺎﺷـﺪ‪.‬‬ ‫ﻲ ﻋﻤﻠﮑﺮ ِﺩ ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺩﺭ ﺗﻮﺻـﻴﻒ ﺍﻭﻟﻴـﻪ ﻣـﻮﺭﺩ ﺗﻮﺟـﻪ ﻗـﺮﺍﺭ‬ ‫ﺩﺭ ﻧﺘﻴﺠﻪ ﺩﺭ ﻃﺮﺍﺣﻲ ﺑﺮﺩﺍﺭ ﺗﺴﺖ ﺗﻨﻬﺎ ﺑﺮﺭﺳ ِ‬ ‫ﻣﻲﮔﻴﺮﺩ‪ .‬ﻟﻴﻜﻦ‪ ،‬ﮔﺎﻫﻲ ﺩﺭ ﺑﻌﻀﻲ ﻃﺮﺍﺣﻴﻬﺎﻱ ﭘﻴﭽﻴﺪﻩ‪ ،‬ﻣﺪﺍﺭ ﺩﺭ ﺷﺮﺍﻳﻂ ﻣﺮﺯﻱ ﺭﻓﺘﺎﺭ ﻏﻴﺮﻗﺎﺑﻞ ﭘﻴﺶﺑﻴﻨﻲ ﺍﺯ ﺧـﻮﺩ‬ ‫ﻧﺸﺎﻥ ﻣﻲﺩﻫﺪ‪ .‬ﺩﺭ ﺍﻛﺜﺮ ﻣﻮﺍﺭﺩ ﻣﻬﻨﺪﺳﺎﻥ ﺍﺯ ﺭﻓﺘﺎﺭ ﻫﺮ ﻣﺎﺟﻮﻝ ﺩﺭ ﺍﺭﺗﺒﺎﻁ ﺑﺎ ﻣﺎﺟﻮﻟﻬﺎﻱ ﺩﻳﮕﺮ ﻧﺎﺁﮔﺎﻩ ﻫﺴـﺘﻨﺪ ﻭ ﺩﺭ‬ ‫ﻧﺘﻴﺠﻪ ﺍﻳﻦ ﺣﺎﻟﺘﻬﺎ ﺑﺮﺭﺳﻲ ﻧﻤﻲﺷﻮﻧﺪ‪ ،‬ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﺍﻳﻦ ﺣﺎﻟﺘﻬﺎ ﻣﻲﺗﻮﺍﻧﺪ ﺑﺎﻋﺚ ﺍﻳﺠﺎﺩ ﺍﺛﺮﺍﺕ ﻣﺨﺮﺑﻲ ﺩﺭ ﺭﻓﺘﺎﺭ‬ ‫ﻛﻠﻲ ﺳﻴﺴﺘﻢ ﺷﻮﺩ‪ .‬ﺑﻪ ﻣﺮﻭﺭ ﺯﻣﺎﻥ ﻃﺮﺍﺣﺎﻥ ﺑﻪ ﺍﻳﻦ ﻧﺘﻴﺠﻪ ﻣﻲﺭﺳﻨﺪ ﻛﻪ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺑﻪ ﻭﺳﻴﻠﻪ ﺷﺒﻴﻪﺳـﺎﺯﻫﺎ ﺑـﺮﺍﻱ‬ ‫ﻣﺪﺍﺭﻫﺎﻱ ﻣﺠﺘﻤﻌﻲ ﻛﻪ ﺭﻭﺯﺑﻪ ﺭﻭﺯ ﭘﻴﭽﻴﺪﻩﺗﺮ ﻭ ﺑﺰﺭﮔﺘﺮ ﻣﻲﺷﻮﻧﺪ‪ ،‬ﻣﻨﺎﺳﺐ ﻧﻴﺴﺖ‪.‬‬ ‫‪۳‬‬ ‫‪ -۲-۱‬ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﻮﺭﯼ‬ ‫ﺗﻌﺮﻳﻒ ﮐﻠﯽ ﺩﺭﺳﺘﻲﻳﺎﺑﯽ ﺻﻮﺭﯼ ﺍﺛﺒﺎﺕ ﺳﺎﺯﮔﺎﺭﯼ ﻣﺪﺍﺭﻫﺎﯼ ﻣﺠﺘﻤﻊ ﺩﻳﺠﻴﺘﺎﻝ ﭘﻴـﺎﺩﻩﺳـﺎﺯﯼ ﺷـﺪﻩ ﻭ ﺗﻮﺻـﻴﻒ‬ ‫ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺍﺑﺘﺪﺍ ﺑﺎﻳﺪ ﺗﻮﺻﻴﻒ ﺳﻴﺴﺘﻢ ﺑﻪ ﺻﻮﺭﺕ ﮐﺎﻣﻞ ﺗﻌﺮﻳﻒ ﺷﺪﻩﺑﺎﺷﺪ ﺗـﺎ ﺍﺯ ﺁﻥ ﻳـﮏ‬ ‫ﻣﺪﻝ ﺩﻗﻴﻖ )ﭘﻴﺎﺩﻩﺳﺎﺯﯼ( ﺳﺎﺧﺘﻪﺷﻮﺩ ﻭ ﺩﺭ ﭘﺎﻳﺎﻥ ﺍﺛﺒﺎﺕ ﺷﻮﺩ ﮐﻪ ﺍﻳﻦ ﻣـﺪﻝ ﺗﻤـﺎﻡ ﺧﻮﺍﺳـﺘﻪﻫـﺎﯼ ﺑﻴـﺎﻥﺷـﺪﻩ ﺩﺭ‬ ‫ﺗﻮﺻﻴﻒ ﺳﻴﺴﺘﻢ ﺭﺍ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﺭﻭﺵ ﻧﺴﺒﺖ ﺑﻪ ﺭﻭﺵ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﻧﺘﺎﻳﺞ ﺟـﺎﻣﻊﺗـﺮﯼ ﺩﺭ ﺍﺧﺘﻴـﺎﺭ ﺗـﻴﻢ‬ ‫ﻃﺮﺍﺣﯽ ﻗﺮﺍﺭ ﻣﻲﺩﻫﺪ‪ .‬ﺑﺮﺍﯼ ﻣﺜﺎﻝ ﻣﯽﺗﻮﺍﻥ ﺗﻀﻤﻴﻦ ﮐﺮﺩ ﮐﻪ ﻳﮏ ﺧﺼﻮﺻﻴﺖ ﺩﺭ ﻃﺮﺡ ﺩﺭ ﺍﺯﺍﯼ ﮐﻠﻴﻪ ﻭﺭﻭﺩﻳﻬﺎﯼ‬ ‫ﻒ ﺩﻗﻴﻖ ﻳﮏ ﺳﻴﺴﺘﻢ ﻭ ﺍﺛﺒﺎﺕ ﺳـﺎﺯﮔﺎﺭﻱ ﺁﻥ‬ ‫ﯽ ﺗﻮﺻﻴ ِ‬ ‫ﻣﻤﮑﻦ ﺑﺮﻗﺮﺍﺭ ﺍﺳﺖ‪ .‬ﺍﻣﺮﻭﺯﻩ ﺑﻪ ﺩﻟﻴﻞ ﭘﻴﭽﻴﺪﻩ ﺑﻮﺩﻥ ﻃﺮﺍﺣ ِ‬ ‫ﻭ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ‪ ،‬ﺍﻳﻦ ﺭﻭﺵ ﺩﺭ ﺻﻨﻌﺖ ﻏﻴﺮﻗﺎﺑﻞ ﺍﺳﺘﻔﺎﺩﻩ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺭﻭﺷـﻬﺎﯼ ﺩﺭﺳـﺘﯽﻳـﺎﺑﯽ ﺻـﻮﺭﯼ ﻓﻘـﻂ ﺩﺭ‬ ‫ﻣﺤﻴﻄﻬﺎﯼ ﺗﺤﻘﻴﻘﺎﺗﯽ ﺩﺍﻧﺸﮕﺎﻫﻬﺎ ﺑﺮﺭﺳﯽ ﻣﻲﺷﻮﻧﺪ ﻭ ﺗﻨﻬﺎ ﺑﺮﺍﯼ ﻣﺴﺎﻳﻞ ﺑﺎ ﺣﺠﻢ ﮐﻮﭼﮏ ﻗﺎﺑﻞ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺑﺎﺷﺪ‪،‬‬ ‫ﻟﻴﮑﻦ ﺑﺤﺮﺍﻥ ﺩﺭﺳﺘﻲﻳﺎﺑﯽ‪ ،‬ﻳﻌﻨﯽ ﻧﺎﮐﺎﺭﺁﻣﺪﯼ ﺭﻭﺷﻬﺎﯼ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﻓﻌﻠﯽ ﺑﺮﺍﯼ ﺗﻀـﻤﻴﻦ ﺩﺭﺳـﺖﺑـﻮﺩﻥ ﻃـﺮﺡ‪،‬‬ ‫ﺑﺎﻋﺚ ﺷﺪﻩﺍﺳﺖ ﺗﺎ ﺗﻤﺎﻳﻞ ﺑﺮﺍﯼ ﺑﺪﺳﺖﺁﻭﺭﺩﻥ ﺍﻟﮕﻮﺭﻳﺘﻢ ﺟﺪﻳﺪ ﺩﺭﺳﺘﻲﻳﺎﺑﯽ ﺍﻓﺰﺍﻳﺶ ﻳﺎﺑﺪ‪ .‬ﺧﺼﻮﺻﺎ ﺩﺭ ﺩﻩ ﺳﺎﻝ‬ ‫ﮔﺬﺷﺘﻪ‪ ،‬ﮐﻪ ﺣﺘﻲ ﺷﺎﻫﺪ ﺗﻮﻟﻴﺪ ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﯼ ﺩﺭﺳﺘﻲﻳﺎﺑﯽ ﺻـﻮﺭﯼ ﺗﺠـﺎﺭﯼ ﺑـﻮﺩﻩﺍﻳـﻢ‪ .‬ﻭﻟـﯽ ﻣﺸـﮑﻼﺗﯽ ﻣﺎﻧﻨـﺪ‬ ‫ﭘﻴﭽﻴﺪﮔﯽ ﺍﻟﮕﻮﺭﻳﺘﻤﻬﺎ ﻭ ﻣﺼﺮﻑ ﺯﻳﺎﺩ ﻣﻨﺎﺑﻊ ﻳﺎ ﻧﻴـﺎﺯ ﺑـﻴﺶ ﺍﺯ ﺣـﺪ ﺍﻟﮕﻮﺭﻳﺘﻤﻬـﺎ ﺑـﻪ ﻣﻬﻨﺪﺳـﺎﻥ ﺑـﺮﺍﯼ ﻃﺮﺍﺣـﯽ‬ ‫ﺗﻮﺻﻴﻒ ﺳﻴﺴﺘﻢ ﻣﺎﻧﻊ ﺍﺯ ﺍﻳﻦ ﺷﺪﻩ ﺍﺳﺖ ﮐﻪ ﺍﻳﻦ ﺍﺑﺰﺍﺭﻫﺎ ﺍﺯ ﮐﺎﺭﺍﻳﻲ ﻻﺯﻡ ﺑﺮﺧﻮﺭﺩﺍﺭ ﺑﺎﺷﻨﺪ‪.‬‬ ‫‪ -۱-۲-۱‬ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﺍﻣﻴﺪ ﺍﺻﻠﯽ ﺩﺭ ﺭﻭﺷﻬﺎﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﻮﺭﯼ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﺪﻩﻱ ﺍﺻـﻠﯽ ﺍﻳـﻦ ﺭﻭﺵ‪ ،‬ﺷـﺒﻴﻪ‪-‬‬ ‫ﻦ ﺷﺒﻴﻪ‪-‬‬ ‫ﺳﺎﺯﯼ ﻃﺮﺡ ﺑﺎ ﮐﻤﮏ ﻧﻤﺎﺩﻫﺎﯼ ﺑﻮﻟﯽ ﺑﻪ ﺟﺎﯼ ﻣﻘﺎﺩﻳﺮ ﺛﺎﺑﺖ ﺩﻭﺩﻭﻳﻲ ﺩﺭ ﻭﺭﻭﺩﯼ ﻣﺪﻝ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺣﻴ ِ‬ ‫ﺳﺎﺯﯼ‪ ،‬ﺍﻳﻦ ﺭﻭﺵ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻣﺘﻐﻴﺮﻫﺎﯼ ﺑﻮﻟﯽ ﻭﺭﻭﺩﻱ ﻭ ﺳﺎﺧﺘﺎﺭ ﻣﺪﺍﺭ‪ ،‬ﻳﮏ ﻋﺒﺎﺭﺕ ﺑﻮﻟﯽ ﺑﺮﺍﯼ ﺧﺮﻭﺟﯽ ﻣﺪﻝ‬ ‫ﺑﺪﺳﺖ ﻣﻲﺁﻭﺭﺩ‪ .‬ﻳﻌﻨﯽ ﺩﺭ ﭘﺎﻳﺎﻥ ﻫﺮ ﭼﺮﺧﻪ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﺠﻤﻮﻋﻪﯼ ﺗﻤﺎﻡ ﺣﺎﻻﺗﯽ ﮐﻪ ﺍﻳﻦ ﻣﺪﺍﺭ ﺩﺭ ﻳـﮏ ﭘـﺎﻟﺲ‬ ‫‪۴‬‬ ‫ﺳﺎﻋﺖ ﻣﻲﺗﻮﺍﻧﺪ ﺁﻧﻬﺎ ﺭﺍ ﻣﻼﻗﺎﺕ ﮐﻨﺪ ﺑﻪ ﺻﻮﺭﺕ ﻳﮏ ﻋﺒﺎﺭﺕﺑﻮﻟﻲ ﺑﺪﺳﺖﻣﻲﺁﻳﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠـﻪ ﺍﻳـﻦ ﺭﻭﺵ ﺩﺍﺭﺍﯼ‬ ‫ﺍﻳﻦ ﻗﺎﺑﻠﻴﺘﻬﺎ ﻣﻲﺑﺎﺷﺪ‪ -۱ :‬ﺩﺭﺳﺘﻲﻳﺎﺑﯽ ﺣﺎﻟﺘﻬﺎﯼ ﺯﻳﺎﺩﯼ ﺍﺯ ﻃﺮﺡ ﺑﻪ ﺻﻮﺭﺕ ﻣﻮﺍﺯﯼ ﻭ ﭘﻮﺷﺶ ﺑﻴﺸﺘﺮ ﻧﺴﺒﺖ ﺑـﻪ‬ ‫ﺭﻭﺵ ﻣﻌﻤﻮﻝ ﺷﺒﻴﻪﺳﺎﺯﯼ‪ -۲.‬ﺍﺛﺒﺎﺕ ﺧﺼﻮﺻﻴﺎﺗﯽ ﺍﺯ ﺳﻴﺴﺘﻢ ﮐﻪ ﺩﺍﻣﻨـﻪ ﺯﻣـﺎﻧﯽ ﻣﺤـﺪﻭﺩ ﺩﺍﺭﻧـﺪ‪ .‬ﻣﺸـﮑﻞ ﺍﻳـﻦ‬ ‫ﺭﻭﺵ‪ ،‬ﺍﻧﺠﺎﻡ ﻋﻤﻠﻴﺎﺕ ﺯﻳﺎﺩ ﺑﺮ ﺭﻭﯼ ﻋﺒﺎﺭﺗﻬﺎﯼ ﺑﻮﻟﯽ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺍﺳﺘﻔﺎﺩﻩ ﺯﻳﺎﺩ ﺍﺯ ﺣﺎﻓﻈﻪ ﻭ ﻣﻨﺎﺑﻊ ﺳﻴﺴﺘﻢ ﺍﺳﺖ‪.‬‬ ‫‪ -۳-۱‬ﻫﺪﻑ ﭘﺮﻭﮊﻩ ﻭ ﺳﺎﺧﺘﺎﺭ ﭘﺎﻳﺎﻥﻧﺎﻣﻪ‬ ‫ﻫﺪﻑ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﻃﺮﺍﺣﯽ ﻭ ﺍﺟﺮﺍﯼ ﻳﮏ ﻣﺪﻝ ﺟﺪﻳﺪ ﺑﺮﺍﯼ ﺍﺳﺘﻔﺎﺩﻩ ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺍﻳﻦ ﻣـﺪﻝ‬ ‫ﺗﻼﺵ ﻣﻲﮐﻨﺪ ﺗﺎ ﺑﺎ ﺍﺿﺎﻓﻪﮐﺮﺩﻥ ﻳﮏ ﺳﺮﻱ ﺍﻣﮑﺎﻧﺎﺕ ﺟﺪﻳﺪ ﺑﻪ ﻣﺪﻟﻬﺎﯼ ﻣﻮﺟﻮﺩ ﺳﻄﺢ ﺗﻮﺻﻴﻒ ﻣﻮﺭﺩ ﺑﺮﺭﺳﯽ ﺭﺍ‬ ‫ﺑﻪ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺑﺎﻻ ﺑﺒﺮﺩ‪.‬‬ ‫ﺩﺭ ﻓﺼﻞ ‪ ۲‬ﺍﺑﺘﺪﺍ ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﯽ ﻳﮏ ﻣﺪﺍﺭ ﻣﺠﺘﻤﻊ ﻣﺮﻭﺭ ﺧﻮﺍﻫﺪ ﺷﺪ ﻭ ﺩﺭﺳﺘﻲﻳﺎﺑﯽ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘـﺎﻝ ﺛﺒـﺎﺕ‬ ‫ﺗﻌﺮﻳﻒ ﻣﻲﮔﺮﺩﺩ ﻭ ﺍﻫﻤﻴﺖ ﺁﻥ ﺩﺭ ﻃﻮﻝ ﭼﺮﺧﻪ ﻃﺮﺍﺣﯽ ﻣﻮﺭﺩ ﺑﺮﺭﺳﯽ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ ﻣﺰﺍﻳﺎ ﻭ ﻣﻌﺎﻳـﺐ ﺩﺭﺳـﺘﯽ‪-‬‬ ‫ﻳﺎﺑﯽ ﺻﻮﺭﯼ ﻭ ﺑﻪ ﺻﻮﺭﺕ ﺧﺎﺹ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺑﻴﺎﻥ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫ﺩﺭ ﻓﺼﻞ‪ ۳‬ﻣﺪﻟﻬﺎﯼ ﻣﻮﺟﻮﺩ ﺑﺮﺍﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﺍﺭﺍﻳﻪ ﻭ ﺩﺭ ﭘﺎﻳﺎﻥ ﻓﺼﻞ ﺍﻳﻦ ﻣﺪﻟﻬﺎ ﺑﺎﻫﻢ ﻣﻘﺎﻳﺴﻪ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫ﺩﺭ ﻓﺼﻞ ‪ ۴‬ﻳﻚ ﻣﺪﻝ ﺟﺪﻳﺪ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻋﺒﺎﺭﺍﺕ ﺑﻮﻟﻲ – ﺟﺒﺮﯼ ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﺪﻝ ﺳﻌﻲ ﻣﻲﺷﻮﺩ‬ ‫ﺗﺎ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺑﺴﻂ ﺗﻴﻠﻮﺭ ﻭ ﻋﺒﺎﺭﺕ ﺟﺒﺮﻱ ﻣﻌﺎﺩﻝ ﻋﺒﺎﺭﺍﺕ ﺑﻮﻟﻲ ﻳﻚ ﮔﺮﺍﻑ ﺑﺮﺍﻱ ﻣﺪﻝﻛﺮﺩﻥ ﻋﺒـﺎﺭﺍﺕ ﺑـﻮﻟﻲ‬ ‫ﺻﺤﻴﺢ ﻃﺮﺍﺣﻲ ﺷﻮﺩ‪ ،‬ﺳﭙﺲ ﺑﺎ ﺍﺿﺎﻓﻪ ﻛﺮﺩﻥ ﻋﺒﺎﺭﺕ ﻣﻘﺎﻳﺴﻪﺍﻱ ﺑﻪ ﻣﺪﻝ ﻗﺎﺑﻠﻴﺖ ﻣـﺪﻝﺳـﺎﺯﻱ ﻗﺴـﻤﺖ ﻛﻨﺘﺮﻟـﻲ‬ ‫ﻣﺪﺍﺭ ﺭﺍ ﻣﻲﺩﻫﻴﻢ‪ .‬ﺍﻳﻦ ﻋﻤﻞ ﺑﺎﻋﺚ ﻛﺎﻫﺶ ﺍﻧﺪﺍﺯﻩﻱ ﺩﺭﺧﺖ ﻣﺪﻝ ﺩﺭ ﻣﻘﺎﻳﺴﻪ ﺑﺎ ﺭﻭﺷﻬﺎﻱ ﻗﺒﻠﻲ ﻣﻲ ﮔﺮﺩﺩ‪.‬‬ ‫ﺩﺭ ﻓﺼﻞ ‪ ۵‬ﺭﻭﺵ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺍﻳﻦ ﻣﺪﻝ ﺩﺭ ﻳﮏ ﺯﺑﺎﻥ ﺑﺮﻧﺎﻣﻪﻧﻮﻳﺴﯽ ﺳﻄﺢ ﺑﺎﻻ ﻳﻌﻨﯽ ‪ Visual C++‬ﻭ ﺗﻐﻴﻴـﺮﺍﺕ‬ ‫ﺍﻳﻦ ﻣﺪﻝ ﺑﺮﺍﯼ ﺁﺳﺎﻥ ﺷﺪﻥ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺑﻴﺎﻥ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺩﺭ ﻓﺼﻞ ﭘﺎﻳﺎﻧﯽ ﻧﻴﺰ ﻧﺘﺎﻳﺞ ﺍﻳﻦ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﻭ ﭘﻴﺸﻨﻬﺎﺩﺍﺕ ﺁﻳﻨﺪﻩ ﻣﻄﺮﺡ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫‪۵‬‬ ‫‪ -۲‬ﻃﺮﺍﺣﻲ ﻭ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺳﻴﺴﺘﻤﻬﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ‬ ‫ﺩﺭ ﺍﻳﻦ ﻓﺼﻞ ﻗﺒﻞ ﺍﺯ ﺁﺷﻨﺎﻳﻲ ﺑﺎ ﺭﻭﺷﻬﺎﻱ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ‪ ،‬ﻓﺮﺁﻳﻨﺪ ﻃﺮﺍﺣﻲ ﻣﺪﺍﺭﻫﺎﻱ ﻣﺠﺘﻤﻊ ﻣـﺮﻭﺭ ﻣـﻲﮔـﺮﺩﺩ‪ .‬ﺩﺭ‬ ‫ﻃﻮﻝ ﻓﺮﺁﻳﻨﺪ ﻃﺮﺍﺣﻲ‪ ،‬ﻳﻚ ﺳﻴﺴﺘﻢ ﺩﻳﺠﻴﺘﺎﻝ ﺍﺯ ﻣﺮﺍﺣﻞ ﻣﺨﺘﻠﻔﻲ ﻣﻲﮔﺬﺭﺩ ﺗـﺎ ﺍﺯ ﺗﻮﺻـﻴﻒ ﺍﻭﻟﻴـﻪ ﺑـﻪ ﻣﺤﺼـﻮﻝ‬ ‫ﻧﻬﺎﻳﻲ ﺗﺒﺪﻳﻞ ﺷﻮﺩ‪ .‬ﺩﺭ ﻫﺮﻳﻚ ﺍﺯ ﺍﻳﻦ ﻣﺮﺍﺣﻞ ﻳﻚ ﺗﻮﺻﻴﻒ ﺟﺪﻳﺪ ﺍﺯ ﺳﻴﺴﺘﻢ ﺑﺪﺳﺖ ﻣﻲﺁﻳـﺪ‪ ،‬ﻛـﻪ ﻧﺴـﺒﺖ ﺑـﻪ‬ ‫ﻒ ﻣﺮﺍﺣﻞ ﻗﺒﻠﻲ ﺟﺰﺋﻴﺎﺕ ﺑﻴﺸﺘﺮﻱ ﺍﺯ ﺳﻴﺴﺘﻢ ﺭﺍ ﺑﻴﺎﻥ ﻣﻲﮐﻨﺪ‪.‬ﺩﺭ ﺍﻳﻦ ﺑﺨﺶ ﺍﺑﺘﺪﺍ ﻳـﻚ ﺗﻮﺻـﻴﻒ ﻛﻠـﻲ ﺍﺯ‬ ‫ﺗﻮﺻﻴ ِ‬ ‫ﺍﻳﻦ ﻣﺮﺍﺣﻞ ﺍﺭﺍﻳﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺳﭙﺲ ﻣﻔﺎﻫﻴﻢ ﺭﻳﺎﺿﻲ ﻣﻮﺭﺩ ﻧﻴﺎﺯ‪ ،‬ﺳﺎﺧﺘﺎﺭ ﻣﺪﺍﺭﻫﺎ ﻭ ‪ FSM‬ﻣﺮﻭﺭ ﻣﻲﮔﺮﺩﺩ‪ .‬ﺩﺭ ﺍﺩﺍﻣﻪ‬ ‫ﺍﻳﻦ ﻓﺼﻞ ﺍﻟﮕﻮﺭﻳﺘﻢ ‪ compiled level logic simulation‬ﻛﻪ ﻫﺴﺘﻪ ﺍﺻﻠﻲ ﺩﺭﺳﺘﻲﻳـﺎﺑﻲ ﺍﻣـﺮﻭﺯ ﺍﺳـﺖ‪ ،‬ﺑﻴـﺎﻥ‬ ‫ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﺍﻟﮕﻮﺭﻳﺘﻢ ﺩﺭ ﺍﻭﺍﺧﺮ ﺩﻫﻪ ‪ ۸۰‬ﻣﻄﺮﺡ ﺷﺪ ﻭ ﻫﻨﻮﺯ ﺭﻭﺵ ﺍﺻﻠﻲ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺩﺭ ﺻﻨﻌﺖ ﻣـﻲﺑﺎﺷـﺪ‪.‬‬ ‫ﺩﺭ ﺑﺨﺶ ‪ ۶-۲‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺻﻮﺭﻱ ﻣﺮﻭﺭ ﻣﻲﺷﻮﺩ ﻭ ﻣﺜﺎﻟﻬﺎﻳﻲ ﺍﺯ ﺭﻭﺷﻬﺎﻱ ﻣﻮﺟﻮﺩ ﻣﻄﺮﺡ ﻣﻲﺷﻮﺩ‪ ،‬ﺩﺭ ﺑﺨـﺶ‬ ‫‪ ۷-۲‬ﺗﻮﺻﻴﻒ ﺩﻗﻴﻘﻲ ﺍﺯ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﻣﻄﺮﺡ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱-۲‬ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﻲ‬ ‫ﺷﻜﻞ ‪ ۱-۲‬ﻧﻤﺎﻳﺎﻧﮕﺮ ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﻲ ﺍﺯ ﻣﺮﺣﻠﻪ ﺗﻮﺻﻴﻒ ﺗﺎ ﻣﺤﺼﻮﻝ ﻧﻬﺎﻳﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻃﺮﺍﺣﻲ ﺩﺭ ﺍﻳﻦ ﺷـﻜﻞ‬ ‫ﺑﻪ ﺻﻮﺭﺕ ﺑﺎﻻ ﺑﻪ ﭘﺎﻳﻴﻦ ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﻲ ﺩﺭ ﺻﻨﻌﺖ ﺑﺴﻴﺎﺭ ﭘﻴﭽﻴﺪﻩﺗﺮ ﺍﺯ ﺍﻳـﻦ ﺷـﻜﻞ‬ ‫‪۶‬‬ ‫ﺍﺳﺖ ﻭ ﺩﺍﺭﺍﯼ ﺗﻌﺪﺍﺩ ﺯﻳﺎﺩﻱ ﻣﺴﻴﺮ ﺑﺎﺯﮔﺸﺖ ﺍﺯ ﻣﺮﺍﺣﻞ ﭘﺎﻳﻴﻦ ﺑﻪ ﺑﺎﻻﺗﺮ ﻣﯽﺑﺎﺷﺪ‪ .‬ﺗﺎ ﺩﺭ ﭘﺎﻳـﺎﻥ ﻃﺮﺍﺣـﯽ ﺗﻤـﺎﻣﻲ‬ ‫ﻣﺤﺪﻭﺩﻳﺘﻬﺎﯼ ﻣﻄﺮﺡ ﺷﺪﻩ ﺩﺭ ﺗﻮﺻﻴﻒ‪ ،‬ﺷﺎﻣﻞ ﻋﻤﻠﻜﺮﺩ ﻣﺪﺍﺭ‪ ،‬ﻣﺴﺎﺣﺖ ﺗﺮﺍﺷـﻪ ﺣﺎﺻـﻞ‪ ،‬ﺯﻣﺎﻧﺒﻨـﺪﻱ‪ ،‬ﻣﺼـﺮﻑ‬ ‫ﺍﻧﺮﮊﻱ ﻭ ﻫﺰﻳﻨﻪ ﺭﺍ ﺑﺮﺁﻭﺭﺩﻩ ﺳﺎﺯﺩ‪.‬‬ ‫ﺷﮑﻞ ‪۱-۲‬ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﯽ ﻳﮏ ﻣﺪﺍﺭ ﻣﺠﺘﻤﻊ ﺩﻳﺠﻴﺘﺎﻝ ]‪[۱‬‬ ‫ﺗﻮﺻﻴﻒ ﻃﺮﺍﺣﻲ ﻣﻌﻤﻮ ﹰﻻ ﺑﻪ ﺻـﻮﺭﺕ ﻣـﺪﺍﺭﻛﻲ ﺍﺳـﺖ ﻛـﻪ ﺩﺭ ﺁﻧﻬـﺎ ﻋﻤﻠﻜـﺮﺩ ﻣﺤﺼـﻮﻝ ﻧﻬـﺎﻳﻲ ﻭ ﻫﻤﭽﻨـﻴﻦ‬ ‫ﻣﺤﺪﻭﺩﻳﺘﻬﺎﻳﻲ ﻛﻪ ﺩﺭ ﺳﺎﺧﺖ ﻣﺤﺼﻮﻝ ﻧﻬﺎﻳﻲ ﺑﺎﻳﺪ ﺑﺮﺁﻭﺭﺩﻩ ﺷﻮﺩ ﺑﻴﺎﻥﺷﺪﻩﺍﺳﺖ‪.‬‬ ‫‪۷‬‬ ‫ﻓﺮﺁﻳﻨﺪ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻥ ﻳﮏ ﺭﺍﻩﺣﻞ ﺩﺭﺳﺖ ﻭ ﻗﺎﺑﻞﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺍﺯ ﻳﮏ ﺗﻮﺻﻴﻒ ﻃﺮﺡ ﻃﺮﺍﺣﯽ ﻋﻤﻠﮑـﺮﺩ‪ ٤‬ﻧﺎﻣﻴـﺪﻩ‬ ‫ﻣﻲﺷﻮﺩ‪ ،‬ﮐﻪ ﺷﺎﻣﻞ ﺍﻓﺮﺍﺯ ﺳﻴﺴﺘﻢ ﺑﻪ ﺳﺨﺖﺍﻓﺰﺍﺭ ﻭ ﻧـﺮﻡﺍﻓـﺰﺍﺭ ﻭ ﻃﺮﺍﺣـﯽ ﻳـﮏ ﺭﻳﺰﻣﻌﻤـﺎﺭﯼ‪ ٥‬ﺍﺳـﺖ‪ .‬ﻃﺮﺍﺣـﯽ‬ ‫ﻋﻤﻠﮑﺮﺩ ﻣﻌﻤﻮﻻ ﺑﻪ ﺻﻮﺭﺕ ﺳﻠﺴﻠﻪﻣﺮﺍﺗﺒﯽ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ ﺑﺎ ﺍﻳﻦ ﺭﻭﺵ ﻃﺮﺍﺡ ﻣﻲﺗﻮﺍﻧﺪ ﺩﺭ ﻫﺮ ﻟﺤﻈﻪ ﺭﻭﯼ ﻳﮏ‬ ‫ﺑﺨﺶ ﺍﺯ ﺳﻴﺴﺘﻢ ﺗﻤﺮﮐﺰ ﮐﻨﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺗﻮﺻﻴﻒ ﺳﺎﺧﺘﺎﺭﯼ‪ ،‬ﻫﺮ ﻗﺴﻤﺖ ﺍﺯ ﻃﺮﺍﺣﯽ ﺭﺍ ﺑﻪ ﺻـﻮﺭﺕ ﻣﺎﺟﻮﻟﻬـﺎﯼ‬ ‫ﻣﺴﺘﻘﻞ ﺑﻴﺎﻥ ﻣﻲﮐﻨﺪ‪ ،‬ﮐﻪ ﻫﺮ ﻳﮏ ﺍﺯ ﺁﻧﻬﺎ ﻳﮑﯽ ﺍﺯ ﻋﻤﻠﮑﺮﺩﻫﺎﯼ ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺩﺭ ﮐﻞ ﺳﺎﺧﺘﺎﺭ ﺭﺍ ﺑﺮ ﻋﻬـﺪﻩ ﻣـﻲ‪-‬‬ ‫ﮔﻴﺮﺩ‪ .‬ﺑﺮﺍﯼ ﻫﺮ ﻳﮏ ﺍﺯ ﺍﻳﻦ ﻣﺎﺟﻮﻟﻬﺎ ﻭﺍﺳﻂ‪٦‬ﻫﺎﯼ ﻭﺭﻭﺩﯼ ﺧﺮﻭﺟﯽ ﻭ ﭘﺮﻭﺗﮑﻞ ﺍﺭﺗﺒﺎﻃﯽ ﺁﻥ ﺑﺎ ﻣﺎﺟﻮﻟﻬﺎﯼ ﺩﻳﮕـﺮ‬ ‫ﺑﻪ ﺧﻮﺑﯽ ﺗﻌﺮﻳﻒ ﺷﺪﻩﺍﺳﺖ‪ .‬ﻳﮑﯽ ﺍﺯ ﻧﺘﺎﻳﺞ ﺍﻳﻦ ﻣﺮﺣﻠﻪﻱ ﻃﺮﺍﺣﯽ ﻳﮏ ﺗﻮﺻﻴﻒ ﻋﻤﻠﮑـﺮﺩ‪ ٧‬ﻣـﻲﺑﺎﺷـﺪ ﮐـﻪ ﺑـﻪ‬ ‫ﺻﻮﺭﺕ ﻳﮏ ﺯﺑﺎﻥ ﺳﻄﺢ ﺑﺎﻻ ﻣﺎﻧﻨﺪ ‪ C‬ﺑﻴﺎﻥﺷﺪﻩ ﻭ ﻧﻤﺎﻳﺎﻧﮕﺮ ﺭﻓﺘﺎﺭ ﺳﻴﺴﺘﻢ ﺑﺎ ﺩﻗﺖ ﻳﮏ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﻭ ﻧﺤـﻮﻩﻱ‬ ‫ﻣﺎﺟﻮﻝﺑﻨﺪﻱ ﺁﻥ ﺍﺳﺖ‪ .‬ﺍﻳﻦ ﺑﺮﻧﺎﻣﻪ ﺑﻪ ﻋﻨﻮﺍﻥ ﻣﺪﻟﻲ ﺑﺮﺍﯼ ﺑﺮﺭﺳﯽ ﺻﺤﺖ ﺭﻓﺘﺎﺭ ﻃﺮﺍﺣﻴﻬﺎ ﺩﺭ ﻣﺮﺍﺣﻞ ﺑﻌـﺪﯼ ﺑـﻪ‬ ‫ﮐﺎﺭ ﻣﻲﺭﻭﺩ‪.‬‬ ‫ﺑﻌﺪ ﺍﺯ ﻃﺮﺍﺣﯽ ﻣﺪﻝ‪ ،‬ﺗﻴﻢ ﻃﺮﺍﺣﯽ ﺳﺨﺖﺍﻓﺰﺍﺭ ﺑﻪ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ)‪ (RTL‬ﻣﻲﺭﻭﻧﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺗﻮﺻـﻴﻒ‬ ‫ﻋﻤﻠﮑﺮﺩ ﺑﻬﻴﻨﻪﺳﺎﺯﻱ ﻣﻲﺷﻮﺩ‪ :‬ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﻭ ﻋﻤﻠﮕﺮﻫﺎﻱ ﻫـﺮ ﻣـﺎﺟﻮﻝ ﺑـﻪ ﻭﺳـﻴﻠﻪﻱ ﻳـﮏ ﺯﺑـﺎﻥ ﺗﻮﺻـﻴﻒ‬ ‫ﺳﺨﺖﺍﻓﺰﺍﺭ‪ (HDL) ٨‬ﻃﺮﺍﺣﯽ ﻣﻲﺷﻮﺩ ﻭ ﺳﻴﺴﺘﻢ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﻣﺪﺍﺭ ﺍﺭﺍﻳﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺩﺭ ﭘﺎﻳﺎﻥ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﻃﺮﺍﺣﯽ ﻋﻤﻠﮑﺮﺩ ﻣﺎ ﭘﺎﻳﺎﻥ ﻣﻲﭘﺬﻳﺮﺩ ﻭ ﻧﻮﺑﺖ ﺑﻪ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻣـﻲﺭﺳـﺪ‪ .‬ﺩﺭﺳـﺘﯽﻳـﺎﺑﯽ ﺩﺭ‬ ‫ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻳﻌﻨﯽ ﺑﻪﺩﺳﺖﺁﻭﺭﺩﻥ ﺍﻃﻤﻴﻨﺎﻥ ﮐﺎﻓﯽ ﺍﺯ ﺍﻳﻨﮑﻪ ﻃﺮﺍﺣﻲ ﺩﺭ ﻧﺒﻮﺩ ﻣﺸﮑﻞ ﺳﺎﺧﺖ ﺩﺭﺳـﺖ ﮐـﺎﺭ‬ ‫ﻣﻲﮐﻨﺪ‪ .‬ﺩﻟﻴﻞ ﺍﺻﻠﯽ ﺍﻧﺠﺎﻡ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺍﻳﻦ ﺍﺳﺖ ﮐﻪ ﻗﺒﻞ ﺍﺯ ﻋﻤﻞ ﭘﺮﻫﺰﻳﻨﻪﻱ ﺳﺎﺧﺖ ﺗﺮﺍﺷﻪ ﺧﻄﺎﻫﺎﯼ ﻃﺮﺍﺣـﯽ‬ ‫ﺣﺬﻑ ﺷﻮﺩ‪ .‬ﺩﺭ ﺣﻴﻦ ﻣﺮﺣﻠﻪ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺗﻴﻢ ﻃﺮﺍﺣـﯽ ﺑـﺎ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ ﺭﻭﺷـﻬﺎ ﻭ ﺍﺑـﺰﺍﺭ‬ ‫‪Functional Design 4‬‬ ‫‪Micro Architecture 5‬‬ ‫‪Interface 6‬‬ ‫‪Functional Description 7‬‬ ‫‪Hardware Description Language 8‬‬ ‫‪۸‬‬ ‫ﮔﻮﻧﺎﮔﻮﻥ ﺳﻌﯽ ﻣﻲﮐﻨﺪ ﮐﺎﺭﮐﺮﺩ ﻃﺮﺡ ﺭﺍ ﺑﺎ ﺗﻮﺻﻴﻒ ﺍﻭﻟﻴﻪ ﺳﻴﺴﺘﻢ ﺗﻄﺒﻴـﻖ ﺩﻫـﺪ‪ [۴ ،۳ ،۲] .‬ﺩﺭ ﺻـﻮﺭﺕ ﻋـﺪﻡ‬ ‫ﺗﻄﺎﺑﻖ ﺍﻳﻦ ﺩﻭ ﻣﻮﺭﺩ‪ ،‬ﻃﺮﺡ ﺗﻐﻴﻴﺮ ﻣﯽﮐﻨﺪ‪ .‬ﺣﺘﯽ ﺩﺭ ﻣﻮﺍﺭﺩﯼ ﺍﻣﮑﺎﻥ ﺩﺍﺭﺩ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻳﮏ‬ ‫ﺗﻨﺎﻗﺾ ﻳﺎ ﺍﻏﻤﺎﺽ ﺭﺍ ﺩﺭ ﺗﻮﺻﻴﻒ ﺍﻭﻟﻴﻪ ﺳﻴﺴﺘﻢ ﻧﺸﺎﻥ ﺩﻫﺪ‪.‬‬ ‫ﺩﺭ ﺷﻜﻞ ‪ ۱-۲‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻣﺮﺣﻠﻪ ﻣﺠﺰﺍ ﺩﺭ ﭼﺮﺧﻪ ﻃﺮﺍﺣﻲ ﻣﻄﺮﺡ ﺷﺪﻩ‬ ‫ﺍﺳﺖ‪ .‬ﻟﻴﻜﻦ ﺩﺭ ﺻﻨﻌﺖ‪ ،‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻣﺪﻝ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺑﻪ ﺻـﻮﺭﺕ ﻣـﻮﺍﺯﻱ ﻫﻤـﺮﺍﻩ ﺑـﺎ ﻣﺮﺍﺣـﻞ ﺑﻌـﺪﻱ‬ ‫ﻃﺮﺍﺣﻲ ﺗﺎ ﻣﺮﺣﻠﻪ ﻱ ﺳﺎﺧﺖ ‪ layout‬ﺗﺮﺍﺷﻪ ﺍﺩﺍﻣﻪ ﭘﻴﺪﺍ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﺑﺨﺶ ﺑﻌـﺪﻱ ﺭﻭﺷـﻬﺎﻱ ﺩﺭﺳـﺘﻲﻳـﺎﺑﻲ ﺩﺭ‬ ‫ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻛﻪ ﺍﻣﺮﻭﺯﻩ ﺩﺭ ﺻﻨﻌﺖ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﻣﺮﻭﺭ ﺧﻮﺍﻫﺪ ﺷﺪ‪.‬‬ ‫ﻣﺮﺣﻠﻪ ﺑﻌﺪﻱ ﺩﺭ ﭼﺮﺧﻪ ﻃﺮﺍﺣﻲ‪ ،‬ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﻭ ﺑﻬﻴﻨﻪ ﺳﺎﺯﻱ ﻣﺪﻝ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠـﻪ‬ ‫ﻳﻚ ﻣﺪﻝ ﻫﻤﺮﺍﻩ ﺑﺎ ﺟﺰﺋﻴﺎﺕ ﺍﺯ ﻣﺪﺍﺭ ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ ﻛﻪ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻣﺤﺪﻭﺩﻳﺘﻬﺎﻱ ﻃﺮﺡ ﺑﻬﻴﻨﻪﺳﺎﺯﻱ ﺷﺪﻩﺍﺳﺖ‪.‬‬ ‫ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﻳﻚ ﻃﺮﺡ ﻣﻲﺗﻮﺍﻧﺪ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻣﺼﺮﻑ ﺗﻮﺍﻥ ﻳﺎ ﺳﺎﻳﺰ ﺗﺮﺍﺷﻪ ﻧﻬﺎﻳﻲ ﻳﺎ ﺁﺯﻣﻮﻥﭘﺬﻳﺮﻱ ﻣﺤﺼﻮﻝ ﺑﻬﻴﻨﻪ‪-‬‬ ‫ﺳﺎﺯﻱ ﺷﻮﺩ‪ .‬ﻣﺪﻝ ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠﻪ‪ ،‬ﻃﺮﺡ ﺭﺍ ﺑﻪ ﻭﺳﻴﻠﻪﻱ ﮔﻴﺘﻬﺎﻱ ﻣﻨﻄﻘﻲ ‪ AND‬ﻭ ‪ OR‬ﻳﺎ ﻋﻨﺎﺻـﺮ‬ ‫ﺣﺎﻓﻈﻪ ﺗﻮﺻﻴﻒ ﻣﻲﻛﻨﺪ‪ .‬ﺑﻬﻴﻨﻪ ﺳﺎﺯﻱ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﮔﻴﺖ ﺣﺎﺻﻞ ﺑﺮﺍﺳﺎﺱ ﻣﺤﺪﻭﺩﻳﺘﻬﺎﻳﻲ ﻣﺎﻧﻨﺪ ﺳـﺮﻋﺖ ﻳـﺎ‬ ‫ﻣﺼﺮﻑ ﺗﻮﺍﻥ ﻳﻜﻲ ﺍﺯ ﻣﺸﻜﻞﺗﺮﻳﻦ ﻣﺮﺍﺣﻞ ﺩﺭ ﻓﺮﺁﻳﻨﺪ ﻃﺮﺍﺣﻲ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻣﻌﻤﻮ ﹰﻻ ﺷﺎﻣﻞ ﭼﻨﺪ ﻣﺮﺣﻠﻪ ﺳـﻌﻲ ﻭ‬ ‫ﺧﻄﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﺑﻬﻴﻨﻪﺳﺎﺯﻱ ﻣﻤﻜﻦ ﺍﺳﺖ ﺑﺎﻋﺚ ﻇﺎﻫﺮﺷﺪﻥ ﺧﻄﺎﻫﺎﻱ ﻋﻤﻠﻜﺮﺩ ﺷﻮﻧﺪ‪.‬‬ ‫ﺗﺎ ﺍﻳﻦ ﻣﺮﺣﻠﻪﻱ ﻃﺮﺍﺣﻲ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﻱ ﻃﺮﺍﺣﻲ ﺑﺎ ﻛﻤﻚ ﻛﺎﻣﭙﻴﻮﺗﺮ ﺑﺴﻴﺎﺭ ﻧﺎﭼﻴﺰ ﺍﺳﺖ ﻭ ﺗﻘﺮﻳﺒﹰﺎ ﺗﻤﺎﻣﻲ‬ ‫ﺍﻳﻦ ﻣﺮﺍﺣﻞ ﺑﻪ ﺻﻮﺭﺕ ﺩﺳﺘﻲ ﺗﻮﺳﻂ ﺗﻴﻢ ﻃﺮﺍﺣﻲ ﻭ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ ،‬ﺍﺯ ﻣﺮﺣﻠﻪ ﺳـﺎﺧﺖ ﻭ ﺑﻬﻴﻨـﻪ‪-‬‬ ‫ﺳﺎﺯﻱ ﺍﻛﺜﺮ ﻣﺮﺍﺣﻞ ﺑﻪ ﺻﻮﺭﺕ ﺧﻮﺩﻛﺎﺭ ﻳﺎ ﺣﺪﺍﻗﻞ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﺑﺰﺍﺭﻫﺎﻱ ﻃﺮﺍﺣﻲ ﺑـﺎ ﻛﻤـﻚ ﻛـﺎﻣﭙﻴﻮﺗﺮ ﺍﻧﺠـﺎﻡ‬ ‫ﻣﻲﺷﺪ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺧﻮﺩﻛﺎﺭﺳﺎﺯﻱ ﻣﺮﺣﻠﻪﻱ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺩﺭ ﺳـﻄﺢ ﺍﻧﺘﻘـﺎﻝ ﺛﺒـﺎﺕ ﮔـﺎﻡ ﺑﻌـﺪﻱ ﺑـﺮﺍﻱ ﺻـﻨﺎﻳﻊ‬ ‫ﺳﺎﺯﻧﺪﻩ ﺍﺑﺰﺍﺭ ﻃﺮﺍﺣﻲ ﺑﺎ ﻛﻤﻚ ﻛﺎﻣﭙﻴﻮﺗﺮ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﭘﺲ ﺍﺯ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﮔﻴﺖ ﺳﺎﺧﺘﻪ ﺷﺪﻩ‪ ،‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﻣﺮﺣﻠﻪﻱ ﺩﺭﺳﺘﻲﻳـﺎﺑﻲ ﺳـﻄﺢ‬ ‫‪۹‬‬ ‫ﮔﻴﺖ ﻳﺎ ﻭﺍﺭﺳﻲ ﻫﻢﺍﺭﺯﻱ‪ ،‬ﻫﺪﻑ ﺍﺻﻠﻲ ﺍﺛﺒﺎﺕ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﺩﺭ ﻣﺮﺣﻠﻪ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﻫﻴﭻ ﺧﻄﺎﻳﻲ ﺩﺭ ﻃﺮﺡ ﻭﺍﺭﺩ‬ ‫ﻧﺸﺪﻩ ﺍﺳﺖ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﻛﻪ ﺑﻪ ﺻﻮﺭﺕ ﺧﻮﺩﻛﺎﺭ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻗﺒﻞ ﺍﺯ ﻣﺮﺣﻠـﻪ‬ ‫ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺑﺎ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﮔﻴﺖ ﭘﺲ ﺍﺯ ﻣﺮﺣﻠﻪ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﻣﻘﺎﻳﺴﻪ ﻣﻲﺷﻮﺩ ﺗﺎ ﻣﻌﺎﺩﻝ ﺑﻮﺩﻥ ﻋﻤﻠﻜﺮﺩ ﺍﻳﻦ ﺩﻭ‬ ‫ﺗﻮﺻﻴﻒ ﺭﺍ ﺍﺛﺒﺎﺕ ﺷﻮﺩ‪.‬‬ ‫ﭘﺲ ﺍﺯ ﺍﻳﻦ ﻣﺮﺣﻠﻪ‪ .‬ﻣﺮﺣﻠﻪﻱ ﻧﮕﺎﺷﺖ ﻣﺪﺍﺭ ﺑﺮﺍﺳﺎﺱ ﺗﻜﻨﻮﻟﻮﮊﻱ ﻗﺮﺍﺭ ﺩﺍﺭﺩ ﻧﺘﻴﺠﻪﻱ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺗﻮﺻﻴﻒ ﻣـﺪﺍﺭ‬ ‫ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ‪ Layout‬ﻫﻨﺪﺳﻲ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺩﺭ ﭘﺮﻭﺳﺲ ‪ fabrication‬ﺍﺳﺘﻔﺎﺩﻩ ﻣـﻲﺷـﻮﺩ ﺩﺭ ﭘﺎﻳـﺎﻥ ﺗﺮﺍﺷـﻪ‬ ‫ﺳﺎﺧﺘﻪ ‪،‬ﺗﺴﺖ ﻭ ﺑﺴﺘﻪﺑﻨﺪﯼ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺍﻳﻦ ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﻲ ﺍﻳﺪﻩﺍﻝﮔﺮﺍﻳﺎﻧﻪ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﻣﺮﺣﻠﻪﻱ ﺳﺎﺧﺖ ﺑﻪ ﺩﻟﻴﻞ ﺗﻐﻴﻴﺮﺍﺕ ﺗﻮﺻﻴﻒ ﺳﻴﺴـﺘﻢ‬ ‫ﻭ ﻛﺸﻒ ﺧﻄﺎ ﺩﺭ ﻣﺮﺣﻠﻪﻱ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺑﺎﺭﻫﺎ ﻭ ﺑﺎﺭﻫﺎ ﺗﮑﺮﺍﺭ ﻣﻲﺷﻮﺩ‪ ،‬ﻫﺮ ﻳﮏ ﺍﺯ ﻧﺘـﺎﻳﺞ‬ ‫ﺍﻳﻦ ﺗﮑﺮﺍﺭﻫﺎ ﺑﺎﻳﺪ ﺗﻤﺎﻣﯽ ﻣﺮﺍﺣﻞ ﺑﻌﺪ ﺍﺯ ﺁﻥ ﺭﺍ ﻃﻲ ﻛﻨﺪ‪ .‬ﻳﻜﻲ ﺍﺯ ﻣﻬﻤﺘـﺮﻳﻦ ﻣﺸـﻜﻼﺕ ﺗـﻴﻢ ﻃﺮﺍﺣـﻲ ﺑـﺮﺁﻭﺭﺩﻩ‬ ‫ﺳﺎﺧﺘﻦ ﺗﻘﺎﺿﺎﻱ ﺭﻭﺯﺍﻓﺰﻭﻥ ﺑﺎﺯﺍﺭ ﺑﺮﺍﻱ ﺳﻴﺴﺘﻤﻬﺎﻱ ﺑﺎ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺑﺎﻻﺗﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﻓﺸﺎﺭ ﺑﺎﻋﺚ ﻣـﻲﺷـﻮﺩ‬ ‫ﺗﻴﻢ ﻃﺮﺍﺡ ﺩﺭ ﻃﻮﻝ ﭼﺮﺧﻪﻱ ﻃﺮﺍﺣﻲ‪ ،‬ﺩﺍﻳﻤﺎ ﻃﺮﺡ ﺭﺍ ﺑﻬﻴﻨﻪﺳﺎﺯﻱ ﮐﻨﻨﺪ‪.‬‬ ‫ﺍﺭﺿﺎﻱ ﻣﺤﺪﻭﺩﻳﺘﻬﺎﻱ ﺯﻣﺎﻧﻲ ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺩﺭ ﺗﻮﺻﻴﻒ ﺳﻴﺴﺘﻢ ﺑﻪ ﻧﺤﻮﻱ ﻛﻪ ﻃﺮﺍﺣﻲ ﻣﺎ ﻋﻤﻠﻜﺮﺩ ﻣـﻮﺭﺩﻧﻈﺮ ﺭﺍ‬ ‫ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‪ .‬ﻣﻌﻤﻮ ﹰﻻ ﺍﺯ ﻋﻬﺪﻩﻱ ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﻱ ﺧﻮﺩﻛﺎﺭﺳﺎﺯﻱ ﺧـﺎﺭﺝ ﺍﺳـﺖ ﻭ ﻧﻴـﺎﺯ ﺑـﻪ ﻛﻤـﻚ ﺍﺯ ﺳـﻮﻱ ﺗـﻴﻢ‬ ‫ﻃﺮﺍﺣﻲ ﺩﺍﺭﺩ‪ .‬ﻣﻌﻤﻮ ﹰﻻ ﺑﺮﺭﺳﻲ ﺑﺮﺁﻭﺭﺩﻩﺷﺪﻥ ﻣﺤﺪﻭﺩﻳﺘﻬﺎﻱ ﺳﻴﺴﺘﻢ ﺗﺎ ﭘﺎﻳـﺎﻥ ﻣﺮﺣﻠـﻪ ﻃﺮﺍﺣـﻲ ‪ layout‬ﻣﻤﻜـﻦ‬ ‫ﻧﻴﺴﺖ ﻭ ﺩﺭ ﺻﻮﺭﺕ ﻋﺪﻡ ﺑﺮﺁﻭﺭﺩﻩﺷﺪﻥ ﻣﺤﺪﻭﺩﻳﺘﻬﺎ ﺗﻴﻢ ﻃﺮﺍﺣﻲ ﺭﻭﺵ ﺩﻳﮕـﺮﻱ ﺑـﺮﺍﻱ ﺑﻬﻴﻨـﻪﺳـﺎﺯﻱ ﺳﻴﺴـﺘﻢ‬ ‫ﺍﻧﺘﺨﺎﺏ ﻣﻲ ﻛﻨﻨﺪ‪.‬‬ ‫‪ -۲-۲‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ‬ ‫ﻫﻤﺎﻥ ﮔﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺨﺶ ﻗﺒﻠﻲ ﮔﻔﺘﻪ ﺷﺪ ﺑﺮﺭﺳﻲ ﺻﺤﺖ ﻋﻤﻠﻜـﺮﺩ ﻳـﻚ ﻣـﺪﺍﺭ ﻳﻜـﻲ ﺍﺯ ﻣﻬﻤﺘـﺮﻳﻦ ﻧﻜـﺎﺕ ﺩﺭ‬ ‫‪۱۰‬‬ ‫ﭼﺮﺧﻪ ﻃﺮﺍﺣﻲ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻫﺰﻳﻨﻪﻱ ﺑﺎﻻﻱ ﺳﺎﺧﺖ ﺗﺮﺍﺷﻪﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ‪ ،‬ﺿﺮﺭ ﻧﺎﺷﻲ ﺍﺯ ﺑـﺎﻗﻲ‬ ‫ﻣﺎﻧﺪﻥ ﻳﻚ ﺧﻄﺎ ﺗﺎ ﻣﺮﺣﻠﻪ ﺳﺎﺧﺖ ﺗﺮﺍﺷﻪ ﻣﻲﺗﻮﺍﻧﺪ ﺑﺴﻴﺎﺭ ﻫﻨﮕﻔﺖ ﺑﺎﺷﺪ‪ .‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺩﺭ ﺳـﻄﺢ ﺍﻧﺘﻘـﺎﻝ ﺛﺒـﺎﺕ‬ ‫ﻳﮑﯽ ﺍﺯ ﺩﺷﻮﺍﺭﺗﺮﻳﻦ ﻣﺮﺍﺣﻞ ﻃﺮﺍﺣﯽ ﻭ ﺳﺎﺧﺖ ﺳﻴﺴﺘﻤﻬﺎﯼ ﺩﻳﺠﻴﺘـﺎﻝ ﻣـﻲﺑﺎﺷـﺪ ﻭ ﺍﻣـﺮﻭﺯﻩ ﺑـﻪ ﮐﻤـﮏ ﺷـﺒﻴﻪ‪-‬‬ ‫ﺳﺎﺯﻳﻬﺎﯼ ﻃﻮﻻﻧﯽ ﻣﺪﺕ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻣﻲﮔﺮﺩﺩ ﻭ ﺣﺘﯽ ﺩﺭ ﻣﻮﺍﺭﺩﯼ ﺗﻴﻢ ﻃﺮﺍﺡ ﻳـﮏ ﺑﺮﻧﺎﻣـﻪ ﺑـﺮﺍﯼ ﺗﺴـﺖ ﻃـﺮﺡ‬ ‫ﺧﻮﺩ ﻃﺮﺍﺣﯽ ﻣﯽﮐﻨﻨﺪ‪ ،‬ﻭﻟﯽ ﺍﻳﻦ ﺑﺮﻧﺎﻣﻪ ﺣﺪﺍﮐﺜﺮ ﺑﺮﺍﯼ ﺗﺴﺖ ﻣﺪﺍﺭﻫﺎﯼ ﻣﺸﺎﺑﻪ ﮐﺎﺭﺍﻳﯽ ﺩﺍﺭﺩ‪ .‬ﻫﻤﭽﻨﻴﻦ ﺭﻭﺷـﻬﺎﯼ‬ ‫ﯽ ﺳﺨﺖﺍﻓﺰﺍﺭ ﺑﺮﺍﯼ ﺩﺭﺳـﺘﯽﻳـﺎﺑﯽ ﺭﻭﺵ‬ ‫ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻫﻴﭽﮕﻮﻧﻪ ﺍﺳﺘﺎﻧﺪﺍﺭﺩﯼ ﻧﺪﺍﺭﻧﺪ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﻫﺮ ﺗﻴﻢ ﻃﺮﺍﺣ ِ‬ ‫ﻣﺨﺼﻮﺹ ﺑﻪ ﺧﻮﺩ ﺩﺍﺭﻧﺪ‪ ،‬ﮐﻪ ﺁﻥ ﻫﻢ ﺑﺮﺍﯼ ﻫﺮ ﻃﺮﺡ ﺗﻐﻴﻴﺮ ﻣﻲﮐﻨﺪ‪ .‬ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺍﻳﻦ ﻣﺴﺎﻳﻞ ﻋﺠﻴﺐ ﻧﻴﺴﺖ ﮐـﻪ‬ ‫‪ ۸۰‬ﺩﺭﺻﺪ ﻣﻨﺎﺑﻊ ﺗﻴﻢ ﻃﺮﺍﺡ ﺻﺮﻑ ﺩﺭﺳﺘﻲﻳﺎﺑﯽ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫ﺭﻭﺵ ﻣﻌﻤﻮﻝ ﺻﻨﺎﻳﻊ ﺑﺮﺍﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ‪ ،‬ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﻋﻤﻠﮑﺮﺩ‪ ٩‬ﻣﻲﺑﺎﺷـﺪ‪ .‬ﺩﺭ ﺍﻳـﻦ ﺭﻭﺵ ﻋﻤﻠﮑـﺮﺩ ﻃـﺮﺡ ﺑـﺎ‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺗﻌﺪﺍﺩﯼ ﻭﺭﻭﺩﯼ ﻣﻌﻨﯽﺩﺍﺭ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻣﻲﺷﻮﺩ ﻭ ﺧﺮﻭﺟﯽ ﺑﺪﺳﺖﺁﻣﺪﻩ ﺑﺎ ﺧﺮﻭﺟﯽ ﺩﻟﺨـﻮﺍﻩ ﺗﻄﺒﻴـﻖ‬ ‫ﺩﺍﺩﻩﻣﻲﺷﻮﺩ‪ .‬ﻣﺪﻟﻲ ﮐﻪ ﺑﺮﺍﯼ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﻪ ﮐﺎﺭ ﻣﻲﺭﻭﺩ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺍﺳﺖ‪ ،‬ﮐـﻪ ﻭﺭﻭﺩﻱ ﺗﺴـﺖ‬ ‫ﺑﻪ ﮐﻤﮏ ﻳﮏ ﺑﺮﻧﺎﻣﻪ ﺷﺒﻴﻪﺳﺎﺯ ﻳﺎ ﻳﮏ ﻣﺎﺷﻴﻦ ﺑﻪ ﺁﻥ ﺍﻋﻤﺎﻝ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﺩﺭ ﺩﻭ ﻻﻳﻪ ﺻﻮﺭﺕ ﻣﻲﮔﻴﺮﺩ‪ :‬ﻻﻳﻪ ﻣﺎﺟﻮﻝ ﻭ ﻻﻳﻪ ﺗﺮﺍﺷﻪ‪ .‬ﺩﺭ ﻻﻳﻪ ﻣـﺎﺟﻮﻝ ﻫـﺮ ﻣـﺎﺟﻮﻝ ﺍﺯ ﻃـﺮﺡ‬ ‫ﻣﺴﺘﻘﻼ ﺗﺤﻠﻴﻞ ﻣﻲﺷﻮﺩ‪ .‬ﮐﻪ ﺷﺎﻣﻞ ﺍﻳﺠﺎﺩ ﺗﻤﺎﻡ ﻣﺠﻤﻮﻋﻪ ﺗﺴﺘﻬﺎﯼ ﻻﺯﻡ ﺑﺮﺍﯼ ﻳﮏ ﻣﺎﺟﻮﻝ ﻣﻲﺑﺎﺷﺪ ﮐﻪ ﻫﺮ ﮐـﺪﺍﻡ‬ ‫ﺍﺯ ﺁﻧﻬﺎ ﻳﮑﯽ ﺍﺯ ﺟﻨﺒﻪﻫﺎﯼ ﮐﺎﺭﯼ ﺁﻥ ﻣﺎﺟﻮﻝ ﺭﺍ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﻣﻲﮐﻨﻨﺪ‪ .‬ﻃﺮﺍﺣﯽ ﺍﻳﻦ ﻣﺠﻤﻮﻋﻪ ﺍﺯ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ‬ ‫ﮐﺎﺭ ﺑﺴﻴﺎﺭ ﺯﻣﺎﻧﺒﺮﯼ ﺍﺳﺖ‪ ،‬ﺯﻳﺮﺍ ﻫﺮ ﮐﺪﺍﻡ ﺍﺯ ﺁﻧﻬﺎ ﺑﺎﻳﺪ ﺑﻪ ﺻﻮﺭﺕ ﺩﺳﺘﯽ ﺑـﻪ ﻭﺳـﻴﻠﻪﻱ ﺍﻋﻀـﺎﯼ ﺗـﻴﻢ ﻣﻬﻨﺪﺳـﻲ‬ ‫ﻃﺮﺍﺣﯽﺷﻮﻧﺪ‪ .‬ﺑﻌﻼﻭﻩ ﺍﻳﻦ ﺗﺴﺘﻬﺎ ﻓﻘﻂ ﺑﺮﺍﯼ ﻫﻤﻴﻦ ﻣﺎﺟﻮﻝ ﮐـﺎﺭﺍﻳﻲ ﺩﺍﺭﻧـﺪ‪ .‬ﺑـﻪ ﺗـﺎﺯﮔﯽ ﺗﻌـﺪﺍﺩﯼ ﺍﺯ ﺍﺑﺰﺍﺭﻫـﺎﯼ‬ ‫‪ CAD‬ﻗﺎﺑﻠﻴﺖ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﻋﻤﻠﮑﺮﺩ ﺭﺍ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻩﺍﻧﺪ‪ .‬ﺍﻳﻦ ﺍﺑﺰﺍﺭﻫﺎ ﻗﺎﺑﻠﻴـﺖ ﻃﺮﺍﺣـﯽ ﻭ ﺍﻋﻤـﺎﻝ ﺑﺮﺩﺍﺭﻫـﺎﯼ‬ ‫ﺗﺴﺖ ﻭ ﺑﺮﺭﺳﯽ ﺧﺮﻭﺟﯽ ﻣﺎﺟﻮﻝ ﺭﺍ ﺩﺭ ﺍﺧﺘﻴﺎﺭ ﮐﺎﺭﺑﺮ ﻗﺮﺍﺭ ﻣﻲﺩﻫﺪ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺯﻣﺎﻥ ﺗﺴﺖ ﺭﺍ ﮐﺎﻫﺶ ﻣﻲﺩﻫﺪ‪.‬‬ ‫‪Functional Validation 9‬‬ ‫‪۱۱‬‬ ‫ﭘﺲ ﺍﺯ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺑﺮﺍﯼ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﯽ ﺩﺭ ﻻﻳﻪ ﺗﺮﺍﺷﻪ‪ ،‬ﮐﻞ ﺳﻴﺴﺘﻢ ﺑﻪ ﻋﻨﻮﺍﻥ ﻳﮏ ﻣﺠﻤﻮﻋﻪ ﮐﺎﻣﻞ ﺑﺮﺭﺳﯽ ﻣـﻲ‪-‬‬ ‫ﺷﻮﺩ‪ .‬ﺩﺭ ﺍﻳﻦ ﻻﻳﻪ ﺗﻤﺮﮐﺰ ﺭﻭﯼ ﺗﻌﺎﻣﻞ ﺑﻴﻦ ﻣﺎﺟﻮﻟﻬﺎ ﻣﻲﺑﺎﺷﺪ ﻭ ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻨﮑﻪ ﻧﻴﺎﺯﻣﻨﺪ ﻣﺤﺎﺳﺒﺎﺕ ﺑﻴﺸﺘﺮﯼ ﻣﻲ‪-‬‬ ‫ﺑﺎﺷﺪ ﻭﻟﯽ ﺑﻴﺸﺘﺮ ﺑﻪ ﺻﻮﺭﺕ ﺧﻮﺩﮐﺎﺭ ﺍﻧﺠﺎﻡ ﻣﻲﺷـﻮﺩ‪ .‬ﺑﺮﺩﺍﺭﻫـﺎﯼ ﺗﺴـﺖ ﺑـﻪ ﺻـﻮﺭﺕ ﺗﺼـﺎﺩﻓﯽ ﻣﺘﻨﺎﺳـﺐ ﺑـﺎ‬ ‫ﻣﺤﺪﻭﺩﻳﺘﻬﺎﯼ ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺩﺭ ﺗﻮﺻﻴﻒ‪ ،‬ﺗﻮﻟﻴﺪ ﻣﻲﺷﻮﻧﺪ‪ ،‬ﺳﭙﺲ ﺑﻪ ﻃﻮﺭ ﻫﻤﺰﻣﺎﻥ ﺑـﻪ ﺗﻌـﺎﺭﻳﻒ ﺳـﻄﺢ ﺍﻧﺘﻘـﺎﻝ‬ ‫ﺛﺒﺎﺕ ﻭ ﺳﻄﺢ ﺑﺎﻻ ﺍﻋﻤﺎﻝ ﻣﻲﺷﻮﺩ ﻭ ﺧﺮﻭﺟﯽ ﺍﻳﻦ ﺩﻭ ﺑﺎ ﻫﻢ ﻣﻘﺎﻳﺴﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﻛﻴﻔﻴﺖ ﺍﻳﻦ ﻧﻮﻉ ﺩﺭﺳﺘﻲ ﻳﺎﺑﻲ ﻣﻌﻤﻮ ﹰﻻ ﺑﺎ ﻣﻴﺰﺍﻥ ﭘﻮﺷﺶ ﻣﺤﺎﺳﺒﻪ ﻣﻲ ﺷﻮﺩ‪ ،‬ﭘﻮﺷﺶ ﻣﻌﻴﺎﺭﻱ ﺑﺮﺍﺑـﺮ ﺑـﺎ ﻧﺴـﺒﺘﻲ ﺍﺯ‬ ‫ﻛﻞ ﺳﻴﺴﺘﻢ ﻛﻪ ﺩﺭﺳﺘﻲ ﻳﺎﺑﻲ ﺷﺪﻩ ﺍﺳﺖ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻨﻜﻪ ﻫﺪﻑ ﻧﻬﺎﻳﻲ ﺩﺭ ﺩﺭﺳﺘﻲ ﻳﺎﺑﻲ ﭘﻮﺷﺶ ‪100%‬‬ ‫ﺍﺳﺖ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ‪ ،‬ﺑﻪ ﺩﻟﻴﻞ ﻋﻤﻠﻜﺮﺩ ﺧﺎﺹ ﺧﻮﺩ‪ ،‬ﺗﻨﻬﺎ ﻣﻲﺗﻮﺍﻧﺪ ﺑﺨﺶ ﻛـﻮﭼﻜﻲ ﺍﺯ ﻓﻀـﺎﻱ ﺣﺎﻟـﺖ‬ ‫ﺳﻴﺴﺘﻢ ﺭﺍ ﭘﻮﺷﺶ ﺩﻫﺪ‪ .‬ﭘﻮﺷﺶ ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﺑﻪ ﺭﻭﺷﻬﺎﻱ ﻣﺘﻔﺎﻭﺗﻲ ﻣﺤﺎﺳﺒﻪ ﻣـﻲﺷـﻮﺩ‪ .‬ﺑـﺮﺍﻱ ﻣﺜـﺎﻝ ﭘﻮﺷـﺶ‬ ‫ﺧﻄﻲ ﺗﻌﺪﺍﺩ ﺧﻄﻮﻃﻲ ﺍﺯ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺭﺍ ﮐﻪ ﺩﺭ ﻃﻲ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺍﺳﺘﻔﺎﺩﻩ ﺷﺪﻩﺍﻧـﺪ‪ ،‬ﻣـﻲﺷـﻤﺎﺭﺩ‪.‬‬ ‫ﺣﺎﻟﺖ ﺩﻳﮕﺮ ﭘﻮﺷﺶ ﺣﺎﻟﺘﻬﺎ ﺍﺳﺖ ﻛﻪ ﺗﻌﺪﺍﺩ ﺗﻤﺎﻡ ﺣﺎﻻﺕ ﻣﻤﻜﻦ ﺍﺯ ﻃﺮﺍﺣﻲ ﻛـﻪ ﺷـﺒﻴﻪﺳـﺎﺯﻱ ﻭ ﺍﻋﺘﺒﺎﺭﺳـﻨﺠﻲ‬ ‫ﺷﺪﻩﺍﻧﺪ ﻣﻲﺷﻤﺎﺭﺩ‪ .‬ﺍﻳﻦ ﻣﻌﻴﺎﺭ ﻣﺨﺼﻮﺻﹰﺎ ﺩﺭ ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﺣﺪﻭﺩ ﺍﻧـﺪﺍﺯﻩ ﻛـﻞ ﻓﻀـﺎﻱ ﺣﺎﻟـﺖ ﺳﻴﺴـﺘﻢ ﻣﻮﺟـﻮﺩ‬ ‫ﻣﻲﺑﺎﺷﺪ ﺑﺴﻴﺎﺭ ﺍﺭﺯﺷﻤﻨﺪ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ ﻃﺮﺍﺡ ﻣﻲﺗﻮﺍﻧﺪ ﺍﺯ ﭘﻮﺷﺶ ﺣﺎﻟﺘﻬﺎ ﺑﺮﺍﻱ ﺗﻌﻴﻴﻦ ﻧﺴـﺒﺘﻲ ﺍﺯ ﻛـﻞ‬ ‫ﻃﺮﺡ ﻛﻪ ﺩﺭﺳﺘﻲ ﻳﺎﺑﻲ ﺷﺪﻩ ﺍﺳﺖ ﺍﺳﺘﻔﺎﺩﻩ ﻛﻨﺪ‪.‬‬ ‫ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﭘﻴﭽﻴﺪﻩﺗﺮﺷﺪﻥ ﻃﺮﺍﺣﻴﻬﺎ‪ ،‬ﻗﺴﻤﺘﻲ ﺍﺯ ﻛﻞ ﻓﻀﺎﻱ ﺣﺎﻻﺕ ﻛﻪ ﺭﻭﺵ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ ﻣـﻲﺗﻮﺍﻧـﺪ‬ ‫ﻣﻮﺭﺩ ﭘﻮﺷﺶ ﻗﺮﺍﺭ ﺩﻫﺪ‪ ،‬ﻛﻮﭼﻚ ﻣﻲﺷﻮﺩ ﻭ ﺍﻳﻦ ﺧﻮﺩ ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﺍﻳـﻦ ﻣﻮﺿـﻮﻉ ﺍﺳـﺖ ﻛـﻪ ﺍﻋﺘﺒﺎﺭﺳـﻨﺠﻲ‬ ‫ﻋﻤﻠﻜﺮﺩ ﺭﺍﻩ ﺣﻞ ﺩﺭﺳﺘﻲ ﺑﺮﺍﻱ ﻣﺴﺎﻟﻪ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻧﻴﺴﺖ‪ .‬ﺯﻳﺮﺍ ﺩﺭ ﻫﺮ ﭼﺮﺧﻪ ﺷﺒﻴﻪﺳـﺎﺯﻱ ﻳـﻚ ﻭ ﻓﻘـﻂ ﻳـﻚ‬ ‫ﺣﺎﻟﺖ ﻗﺒﻠﻲ ﻭ ﻳﻚ ﻭﺭﻭﺩﻱ ﺧﺎﺹ ﻣﻮﺭﺩ ﺑﺮﺭﺳﻲ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ ﻭ ﺍﻳـﻦ ﺑـﺎ ﺭﺷـﺪ ﻧﻤـﺎﻳﻲ ﭘﻴﭽﻴـﺪﮔﻲ ﺩﻳﺠﻴﺘـﺎﻝ‬ ‫ﻣﺘﻨﺎﺳﺐ ﻧﻴﺴﺖ‪.‬‬ ‫ﺭﻭﺷﻬﺎﯼ ﺩﻳﮕﺮﻱ ﻧﻴﺰ ﺑﺮﺍﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻃﺮﺍﺣﯽ ﺷﺪﻩﺍﻧﺪ‪ .‬ﺍﺯ ﺟﻤﻠﻪ ﺁﻧﻬﺎ ﺳـﻌﯽ ﺩﺭ ﺑﺪﺳـﺖ ﺁﻭﺭﺩﻥ ﻳـﮏ ﺍﺛﺒـﺎﺕ‬ ‫‪۱۲‬‬ ‫ﺭﻳﺎﺿﯽ ﺑﺮﺍﯼ ﺩﺭﺳﺖ ﺑﻮﺩﻥ ﻃﺮﺡ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺎ ﮐﻤﮏ ﺍﻳﻦ ﺭﻭﺵ ﻣﻲﺗﻮﺍﻥ ﺗﻀﻤﻴﻦ ﮐﺮﺩ ﮐﻪ ﺑﺮﺧﯽ ﺍﺯ ﺟﻨﺒﻪﻫـﺎ ﺩﺭ‬ ‫ﻣﺪﺍﺭ ﺑﻪ ﺍﺯﺍﯼ ﺗﻤﺎﻣﯽ ﺣﺎﻻﺕ ﺁﻥ ﺑﺮﻗﺮﺍﺭ ﺍﺳﺖ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺍﻋﺘﺒﺎﺭ ﺳﻴﺴﺘﻢ ﻣﺤﺪﻭﺩ ﺑﻪ ﻣﺠﻤﻮﻋﻪ ﺗﺴﺘﻬﺎﻳﻲ ﮐـﻪ ﺑـﻪ‬ ‫ﺳﻴﺴﺘﻢ ﺍﻋﻤﺎﻝ ﺷﺪﻩ ﻧﻤﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﮔﻮﻧﻪ ﻣﺘﺪﻫﺎ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﻮﺭﯼ‪ ١٠‬ﻧﺎﻡ ﮔﺬﺍﺭﻱ ﺷﺪﻩﺍﻧﺪ ﻭ ﺑﻪ ﻣﻨﺰﻟﻪﻱ ﺍﻋﻤـﺎﻝ‬ ‫ﮐﻠﻴﻪ ﻭﺭﻭﺩﻳﻬﺎﯼ ﻣﻤﮑﻦ ﺑﻪ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﺭﻭﺵ ﻳﮏ ﺟﻬﺶ ﺑﺰﺭﮒ ﺩﺭ ﺯﻣﻴﻨﻪ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺍﺳـﺖ‪ .‬ﺷـﮑﻞ‬ ‫ﺷﻤﺎﺭﻩﻱ‪ ۲-۲‬ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﺗﻔﺎﻭﺕ ﺑﻴﻦ ﺍﻳﻦ ﺩﻭ ﺭﻭﺵ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۲-۲‬ﻣﻘﺎﻳﺴﻪ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻨﻄﻘﯽ ﻭ ﺩﺭﺳﺘﯽﻳﺎﺑﻲ‬ ‫ﺩﺭ ﻳﮏ ﺳﻮ ﺑﻪ ﻧﻈﺮ ﻣﻲﺭﺳﺪ ﮐﻪ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﻮﺭﯼ ﺭﺍﻩﺣﻞ ﻧﻬﺎﻳﯽ ﻣﺸﮑﻞ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺍﺳـﺖ‪ ،‬ﻭﻟـﯽ ﺍﺯ ﺳـﻮﯼ‬ ‫ﺩﻳﮕﺮ ﺍﻳﻦ ﺭﻭﺷﻬﺎ ﺑﻪ ﻋﻠﺖ ﭘﻴﭽﻴﺪﮔﯽ ﺍﻟﮕﻮﺭﻳﺘﻤﻬﺎﯼ ﺁﻥ ﻧﺘﻮﺍﻧﺴﺘﻪﺍﻧـﺪ ﮐـﻪ ﺍﺯ ﭘـﺲ ﻣﺴـﺎﻳﻞ ﻣﻮﺟـﻮﺩ ﺩﺭ ﺻـﻨﻌﺖ‬ ‫ﺑﺮﺑﻴﺎﻳﻨﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺩﺭﺣﺪ ﺗﺌﻮﺭﻱ ﻭ ﺩﺍﻧﺸﮕﺎﻫﯽ ﺑﺎ ﮐﺎﺭﺑﺮﺩﻫﺎﯼ ﺗﺠﺮﺑﯽ ﺩﺭ ﺻﻨﻌﺖ ﺑﺎﻗﻲ ﻣﺎﻧﺪﻩﺍﻧﺪ‪.‬‬ ‫‪ -۳-۲‬ﻣﺘﻐﻴﺮ ﻭ ﺗﻮﺍﺑﻊ ﺑﻮﻟﻲ ﻭ ﻧﺤﻮﻩ ﻧﻤﺎﻳﺶ ﺁﻧﻬﺎ‬ ‫ﺑﺮﺍﻱ ﺁﺷﻨﺎﻳﻲ ﺑﺎ ﻧﺤﻮﻩ ﻧﻤﺎﻳﺶ ﺗﻮﺍﺑﻊ ﺑﻮﻟﻲ ﺍﺑﺘﺪﺍ ﻣﺮﻭﺭﻱ ﺑﺮ ﻗﻮﺍﻧﻴﻦ ﺍﺻﻠﻲ ﺟﺒﺮ ﺑﻮﻝ ﻣﻲ ﺷﻮﺩ‪ .‬ﺍﮔـﺮ ‪ B‬ﻧﻤﺎﻳـﺎﻧﮕﺮ‬ ‫ﻣﺠﻤﻮﻋﻪ ﺑﻮﻟﻲ }‪ {0,1‬ﺑﺎﺷﺪ‪ .‬ﻳﻚ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ﻳﻚ ﻣﺘﻐﻴﺮ ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺭﻭﻱ ﻣﺠﻤﻮﻋﻪ ‪ B‬ﻭ ﻳـﻚ ﺗـﺎﺑﻊ ﺑـﻮﻟﻲ‬ ‫ﻳﻚ ﻧﮕﺎﺷﺖ ‪ F : B n → B m‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ Fx‬ﻧﻤﺎﻳﻨﺪﻩ ﺍﻭﻟﻴﻦ ‪ cofactor‬ﺗﺎﺑﻊ ‪ F‬ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻣﺘﻐﻴﺮ ‪ xi‬ﺍﺳﺖ‪ ،‬ﻭ ﺣﺎﺻﻞ ﻳﻚ ﻗﺮﺍﺭ ﺩﺍﺩﻥ ﻣﺘﻐﻴﺮ ‪ xi‬ﻣﻲﺑﺎﺷﺪ ﻭ‬ ‫‪i‬‬ ‫‪ 0-cofactor‬ﺗﺎﺑﻊ ‪ F‬ﺑﺎ ‪ Fx‬ﻧﺸﺎﻥ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ ﻭ ﺣﺎﺻﻞ ﺻﻔﺮ ﻗﺮﺍﺭﺩﺍﺩﻥ ﻣﺘﻐﻴﺮ ‪ xi‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪i‬‬ ‫‪Formal Verification 10‬‬ ‫‪۱۳‬‬ ‫ﺑﺮﺩ ﺗﺎﺑﻊ ‪ F : B n → B m‬ﺑﺮﺍﺑﺮ ﺑﺎ ﺗﻤﺎﻡ ‪ m‬ﺗﺎﻳﻲ ﺍﺳﺖ ﻛﻪ ﻣﻲﺗﻮﺍﻥ ﺑﺎ ﺗﺎﺑﻊ ‪ F‬ﺑـﻪ ﺁﻥ ﺭﺳـﻴﺪ‪ ،‬ﻭ ﺁﻥ ﺭﺍ ﺑـﺎ )‪R(F‬‬ ‫ﻧﺸﺎﻥ ﻣﻲﺩﻫﻴﻢ‪.‬‬ ‫}‬ ‫‪BDD -۱-۳-۲‬‬ ‫{‬ ‫‪R ( F ) = y ∈ B m ∀x ∈ B n , F ( x) = y‬‬ ‫‪١١‬‬ ‫‪BDD‬ﻫﺎ ﻳﮏ ﺭﻭﺵ ﻓﺸﺮﺩﻩ ﻭ ﮐﺎﺭﺍ ﺑﺮﺍﯼ ﻧﻤﺎﻳﺶ ﻭ ﮐﺎﺭ ﺑﺎ ﺗﻮﺍﺑﻊ ﻧﻤﺎﺩﻳﻦ ﺑﻮﻟﯽ ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺍﻣـﺮﻭﺯﻩ ﺑـﻪ‬ ‫ﻋﻨﻮﺍﻥ ﻋﻨﺼﺮ ﮐﻠﻴﺪﯼ ﺩﺭ ﺗﻤﺎﻡ ﺭﻭﺷﻬﺎﯼ ﻧﻤﺎﺩﻳﻦ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺑﻪ ﮐـﺎﺭ ﻣـﻲﺭﻭﺩ ]‪ .[۵‬ﺑـﺎ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ ‪ BDD‬ﻳـﮏ‬ ‫ﻧﻤﺎﻳﺶ ﻳﮑﺘﺎ‪ ١٢‬ﺑﺮﺍﯼ ﺗﻮﺍﺑﻊ ﺑﻮﻟﯽ }‪ f : B n → B B = {0,1‬ﻃﺮﺍﺣﯽ ﻣﻲﺷﻮﺩ ﮐﻪ ﺑـﺎ ﮐﻤـﮏ ﺁﻥ ﺍﻋﻤـﺎﻟﯽ ﻣﺎﻧﻨـﺪ‬ ‫ﺗﺴﺖ ﺧﺼﻮﺻﻴﺎﺕ ﮐﺎﺭﮐﺮﺩ ﺳﻴﺴﺘﻢ ﺁﺳﺎﻧﺘﺮ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ BDD‬ﻳﮏ ﮔﺮﺍﻑ ﺭﻳﺸﻪﺩﺍﺭ ﻭ ﺟﻬﺖﺩﺍﺭ ﻭ ﺑﺪﻭﻥ ﺩﻭﺭ ﻣﻲﺑﺎﺷﺪ ﮐﻪ ﺑﺮﺍﯼ ﻳﮑﺘﺎ ﺑﻮﺩﻥ‪ ،‬ﺷﺮﺍﻳﻂ ﺧﺎﺹ ﺩﻳﮕـﺮﯼ ﺭﺍ‬ ‫ﻧﻴﺰ ﺑﺮﺁﻭﺭﺩﻩ ﻣﻲﮐﻨﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﮔﺮﺍﻑ ﻫﺮ ﻣﺴﻴﺮ ﺍﺯ ﺭﻳﺸﻪ ﺑﻪ ﺑﺮﮒ ﻧﻤﺎﻳﻨﺪﻩﻱ ﻃﺮﻳﻘﻪ ﻣﺤﺎﺳﺒﻪﻱ ﺧﺮﻭﺟﯽ ﺑﺮﺍﯼ ﻳﮏ‬ ‫ﺗﺮﮐﻴﺐ ﻭﺭﻭﺩﻱ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﻣﺜﺎﻝ ‪ :۱-۲‬ﺑﺨﺶ ﺍﻭﻝ ﺷﮑﻞ ‪ ۳-۲‬ﻧﻤﺎﻳﺎﻧﮕﺮ ‪ BDD‬ﺗﺎﺑﻊ )‪ f = (x + y )( p + q‬ﻣﻲﺑﺎﺷـﺪ‪ .‬ﻣـﻲﺗـﻮﺍﻥ ﺣﺎﺻـﻞ‬ ‫ﺗﺎﺑﻊ ﺭﺍ ﺑﻪ ﺍﺯﺍﯼ ﻫﺮ ﻣﻘﺪﺍﺭﯼ ﮐﻪ ﺑﻪ ﭼﻬﺎﺭ ﻣﺘﻐﻴﺮ ﻭﺭﻭﺩﯼ ﻧﺴﺒﺖ ﺩﺍﺩﻩﺷﻮﺩ ﺑﺎ ﻃﯽ ﻣﺴﻴﺮ ﻣﺘﻨﺎﺳـﺐ ﺑـﺎ ﺁﻥ ﺑﺪﺳـﺖ‬ ‫ﺁﻭﺭﺩ‪.‬‬ ‫‪.‬‬ ‫ﺷﮑﻞ ‪ BDD -۳-۲‬ﻣﻌﺎﺩﻝ ﺗﻮﺍﺑﻊ )‪ f = (x + y )( p + q‬ﻭ ‪[۱] G = w ⊕ x ⊕ y ⊕ z‬‬ ‫‪Binary Decision Diagram 11‬‬ ‫‪canonical 12‬‬ ‫‪۱۴‬‬ ‫ﺑﺨﺶ ﺩﻭﻡ ﺷﮑﻞ ‪ ۳-۲‬ﻧﻤﺎﻳﻨﺪﻩ ﺗﺎﺑﻊ ‪ G = w ⊕ x ⊕ y ⊕ z‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻫﻤﺎﻧﮕﻮﻧﻪ ﮐﻪ ﻣﺸﺎﻫﺪﻩ ﻣـﻲﺷـﻮﺩ ﺗﻌـﺪﺍﺩ‬ ‫ﮔﺮﻩﻫﺎﯼ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺩﺭ ﻧﻤﺎﻳﺶ ‪ XOR‬ﺗﻨﻬﺎ ﺩﻭ ﺑﺮﺍﺑﺮ ﺗﻌﺪﺍﺩ ﻣﺘﻐﻴﺮﻫﺎﯼ ﺗﺎﺑﻊ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺩﺭ ﻣﻘﺎﺑـﻞ ﻣـﺪﻟﻬﺎﻳﻲ‬ ‫ﻣﺎﻧﻨﺪ ﺟﺪﻭﻝ ﺩﺭﺳﺘﯽ ﻳﺎ ‪ SOP‬ﺑﺎ ﺍﻓﺰﺍﻳﺶ ﺗﻌﺪﺍﺩ ﻣﺘﻐﻴﺮﻫﺎ ﺭﺷﺪ ﻧﻤﺎﻳﻲ ﺩﺍﺭﻧﺪ‪.‬‬ ‫ﺑﺮﺍﯼ ﻳﮏ ﺗﺮﺗﻴﺐ ﺧﺎﺹ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺗﻮﺍﻥ ﺛﺎﺑﺖ ﮐﺮﺩ ﮐﻪ ‪ BDD‬ﺗﺎﺑﻊ ﻳﮏ ﻧﻤـﺎﻳﺶ ﻳﮑﺘـﺎ ﺧﻮﺍﻫـﺪ ﺑـﻮﺩ]‪ [۵‬ﻭ‬ ‫ﺯﻣﺎﻥ ﺑﺮﺭﺳﯽ ﻳﮑﺴﺎﻥ ﺑﻮﺩﻥ ﺩﻭ ‪ BDD‬ﺑﻪ ﺻﻮﺭﺕ ﺧﻄﯽ ﺧﻮﺍﻫﺪ ﺑﻮﺩ ﮐﻪ ﺍﺯ ﺯﻣﺎﻥ ﻣﻘﺎﻳﺴﻪ ﺩﻭ ﺗﺎﺑﻊ ﺑﺴـﻴﺎﺭ ﮐﻤﺘـﺮ‬ ‫ﻣﻲﺑﺎﺷﺪ‬ ‫‪ BDD‬ﺩﺍﺭﺍﯼ ﺩﻭ ﺑﺮﮒ ﺑﺎ ﻧﺎﻣﻬﺎﯼ "‪ "۰‬ﻭ "‪ "۱‬ﺍﺳﺖ ﮐﻪ ﻧﻤﺎﻳﺎﻧﮕﺮ ﺗﻮﺍﺑﻊ ﺑﻮﻟﯽ ﺻﻔﺮ ﻭ ﻳﮏ ﻫﺴﺘﻨﺪ‪ .‬ﻫﺮ ﮔـﺮﻩ ﻏﻴـﺮ‬ ‫ﺑﺮﮒ ﻧﻤﺎﻳﺎﻧﮕﺮ ﻳﮏ ﺗﺎﺑﻊ ﺑﻮﻟﯽ ﺍﺳﺖ ﮐﻪ ﺩﻭ ﻳﺎﻝ ﺑﺎ ﺍﺳﺎﻣﯽ "‪ "۰‬ﻭ "‪ "۱‬ﺍﺯ ﺁﻥ ﺧﺎﺭﺝ ﺷﺪﻩﺍﺳﺖ ﮐﻪ ﺑﺎ ﺁﻧﻬﺎ ﺩﻭ ﮔـﺮﻩ‬ ‫ﻣﺘﺼﻞ ﻣﻲﺷﻮﺩ ﮐﻪ ﻧﻤﺎﻳﺎﻧﮕﺮ ﺗﺠﺰﻳﻪ ﺗﺎﺑﻊ ﺍﺻﻠﻲ ﺑﻪ ﮐﻤـﮏ ﺗﺌـﻮﺭﻱ ﺷـﺎﻧﻮﻥ )‪f = xi f xi =0 + xi f xi =1 (1 ≤ i ≤ n‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﻪ ﻋﻼﻭﻩ ﺍﻳﻦ ‪ BDD‬ﺩﻭ ﺷﺮﻁ ﺩﻳﮕﺮ ﺭﺍ ﻧﻴﺰ ﺑﺮﺁﻭﺭﺩﻩ ﻣﻲﮐﻨـﺪ‪ BDD -۱ .‬ﻣﺮﺗـﺐ ﺍﺳـﺖ ﺍﮔـﺮ ﺩﺭ ﻫـﺮ‬ ‫ﻣﺴﻴﺮ ﺍﺯ ﺭﻳﺸﻪ ﺑﻪ ﺑﺮﮒ ﻫﺮ ﻣﺘﻐﻴﺮ ﻓﻘﻂ ﻳﮑﺒﺎﺭ ﻣﻼﻗﺎﺕ ﺷﻮﺩ ﻭ ﺩﺭ ﺗﻤﺎﻡ ﻣﺴﻴﺮﻫﺎ ﺗﺮﺗﻴﺐ ﻣﻼﻗـﺎﺕ ﻣﺘﻐﻴﺮﻫـﺎ ﻳﮑـﯽ‬ ‫ﺑﺎﺷﺪ‪ -۲ .‬ﻳﮏ ‪ BDD‬ﻫﻨﮕﺎﻣﯽ ﮐﺎﻫﺶﻳﺎﻓﺘﻪ‪ ١٣‬ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ ﮐﻪ ﺩﺍﺭﺍﯼ ﻫﻴﭻ ﺯﻳﺮﮔـﺮﺍﻑ ﺍﻳﺰﻭﻣﻮﺭﻓﻴـﮏ ﻳـﺎ ﮔـﺮﻩ‬ ‫ﺯﺍﻳﺪﯼ ﻧﺒﺎﺷﺪ‪.‬‬ ‫ﻳﮏ ‪ BDD‬ﮐﺎﻫﺶﻳﺎﻓﺘﻪ ﻭ ﻣﺮﺗﺐ ﻳﮏ ﻧﻤﺎﻳﺶ ﻳﮑﺘﺎ ﺑﺮﺍﯼ ﺗﻮﺍﺑﻊ ﺑﻮﻟﯽ ﺍﺳﺖ ﺯﻳﺮﺍ ﺑﺮﺍﯼ ﻫﺮ ﺗـﺎﺑﻊ ﺑـﻮﻟﯽ ﻳـﮏ ﻭ‬ ‫ﻓﻘﻂ ﻳﮏ ‪ BDD‬ﺗﻌﺮﻳﻒ ﻣﻲﮐﻨﺪ‪ .‬ﻣﺤﺎﺳﺒﻪ ﻣﻘﺪﺍﺭ ﻳﮏ ﻋﺒﺎﺭﺕ ﺑﻮﻟﯽ ﺑـﺎ ﺍﻋﻤـﺎﻝ ﺍﻟﮕﻮﺭﻳﺘﻤﻬـﺎﯼ ﺑﺎﺯﮔﺸـﺘﯽ ﺭﻭﯼ‬ ‫‪ BDD‬ﺍﻣﮑﺎﻥﭘﺬﻳﺮ ﺍﺳﺖ‪.‬‬ ‫ﻳﮏ ﺭﻭﺵ ﺑﻬﻴﻨﻪﺳﺎﺯﯼ ﺩﺭ ‪ BDD‬ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻳﺎﻟﻬﺎﯼ ﻣﮑﻤﻞ ﻣﻲﺑﺎﺷﺪ ]‪ .[۱‬ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﻳﮑـﯽ ﺍﺯ ﻳﺎﻟﻬـﺎﻱ ﻫـﺮ‬ ‫ﮔﺮﻩ ﺑﻪﻧﺎﻡ ﻳﺎﻝ ﻣﮑﻤﻞ ﺑﻪ ﻧﻘﻴﺾ ﺗﺎﺑﻊ ﺧﻮﺩ ﺩﺭ ‪ ،BDD‬ﻣﺘﺼﻞ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﻓﻘﻂ ﻳﮏ ﮔﺮﻩ ﺑﺮﮒ ﺑـﺎ ﻣﻘـﺪﺍﺭ‬ ‫‪Reduced 13‬‬ ‫‪۱۵‬‬ ‫ﻳﮏ ﻭﺟﻮﺩ ﺩﺍﺭﺩ‪ ،‬ﮐﻪ ﺑﺮﺍﯼ ﺳﺎﺧﺘﻦ ﮔﺮﻩ ﺑﺮﮒ ﺻﻔﺮ ﻳﺎﻝ ﻣﮑﻤﻞ ﺑﻪ ﮔﺮﻩ ﻳﮏ ﻣﺘﺼﻞ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﻣﻬﻤﺘﺮﻳﻦ ﻣﺸﮑﻞ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ‪ BDD‬ﻣﺸﺨﺺ ﮐﺮﺩﻥ ﺗﺮﺗﻴـﺐ ﻣﺘﻐﻴﺮﻫـﺎ ﺩﺭ ﺁﻥ ﺍﺳـﺖ‪ ،‬ﺯﻳـﺮﺍ ﺣﺠـﻢ ‪ BDD‬ﻭ ﺩﺭ‬ ‫ﻧﺘﻴﺠﻪ ﺣﺎﻓﻈﻪ ﻣﺼﺮﻓﯽ ﺩﺭ ﺁﻥ ﺑﻪ ﺷﺪﺕ ﻭﺍﺑﺴﺘﻪ ﺑﻪ ﺗﺮﺗﻴﺐ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﯼ ﻣﺜﺎﻝ ﺑﺮﺍﯼ ﻳﮏ ﺟﻤﻊ ﮐﻨﻨـﺪﻩ‪-‬‬ ‫ﻱ ‪-n‬ﺑﻴﺘﯽ ﺑﺎ ﻋﻤﻠﻮﻧﺪﻫﺎﯼ ‪ a‬ﻭ ‪ ،b‬ﺍﮔﺮ ﺗﺮﺗﻴﺐ ﺑﻴﺘﻬﺎ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ‪ a0 , a1 ,..., an , b0 , b1 ,..., bn‬ﺩﺭ ﻧﻈﺮ ﺑﮕﻴـﺮﻳﻢ‬ ‫‪ BDD‬ﺣﺎﺻﻞ ﺍﻧﺪﺍﺯﻩ ﻧﻤﺎﻳﻲ ﺧﻮﺍﻫﺪ ﺩﺍﺷﺖ ﻭﻟﯽ ﺍﮔﺮ ﺗﺮﺗﻴﺐ ﺑﻴﺘﻬﺎ ﺑﻪ ﺻـﻮﺭﺕ ‪ a0 , b0 , a1 , b1 ,..., an , bn‬ﺑﺎﺷـﺪ‬ ‫ﺍﻧﺪﺍﺯﻩ ‪ BDD‬ﺧﻄﯽ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪ .‬ﺩﺭ ﻋﻴﻦ ﺣﺎﻝ ﻣﺴﺎﻟﻪ ﻣﺮﺗﺐ ﮐﺮﺩﻥ ﻣﺘﻐﻴﺮﻫﺎ ﻳﮏ ﻣﺴﺎﻟﻪ ‪ NP-complete‬ﺍﺳـﺖ‬ ‫ﻭ ﺭﺍﻩﺣﻠﻬﺎﯼ ﻣﻌﻤﻮﻝ ﺍﺯ ﺭﻭﺷﻬﺎﯼ ﺍﺑﺘﮑﺎﺭﯼ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮐﻨﻨﺪ]‪ .[۷ ،۶‬ﺑﺮﺍﯼ ﻣﺜﺎﻝ‪ ،‬ﺗﺤﻠﻴﻞ ﺑﺮﺍﺳﺎﺱ ﺳﺎﺧﺘﺎﺭ ﺷـﺒﮑﻪ‬ ‫ﻣﻨﻄﻘﯽ‪ ،‬ﺭﻭﺵ ﭘﻮﻳﺎﯼ ﺗﻐﻴﻴﺮ ﺗﺮﺗﻴﺐ ﻣﺘﻐﻴﺮﻫﺎ ﭘﺲ ﺍﺯ ﺭﺳﻴﺪﻥ ﺍﻧﺪﺍﺯﻩﻱ ‪ BDD‬ﺑﻪ ﻳﮏ ﺣﺪ ﻣﻌﻴﻦ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺑﺎ ﻭﺟﻮﺩ ﻗﺪﺭﺗﻤﻨﺪ ﺑﻮﺩﻥ‪ BDD‬ﺩﺭ ﺳﻄﺢ ﮔﻴﺖ ﻭ ﻋﺒﺎﺭﺍﺕ ﺑﻮﻟﯽ ﻟﻴﮑﻦ ﺩﺭ ﺁﻥ ﻫﻴﭽﮕﺎﻩ ﺍﺯ ﺍﻃﻼﻋﺎﺕ ﺳﻄﺢ ﺑﺎﻻﻳﻲ‬ ‫ﮐﻪ ﺩﺭ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺩﺍﺩﻩ ﺑﻴﺎﻥ ﺷﺪﻩ ﺍﺳﺘﻔﺎﺩﻩﺍﯼ ﻧﮑﺮﺩﻩﺍﻳﻢ‪ ،‬ﺍﺯﺟﻤﻠﻪ ﺳﺎﺧﺘﺎﺭﻫﺎﯼ ﺗﮑﺮﺍﺭﯼ ﻣﺎﻧﻨـﺪ ﺟﻤـﻊ‪-‬‬ ‫ﮐﻨﻨﺪﻩﻫﺎ‪ .‬ﺍﮐﺜﺮ ﻣﺸﮑﻼﺕ ﻣﻮﺟﻮﺩ ﺩﺭ ﺭﻭﻧﺪ ﺍﺛﺒﺎﺕ ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺍﺯ ﻋﺪﻡ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺍﻃﻼﻋـﺎﺕ ﻧﺎﺷـﯽ ﻣـﻲ‪-‬‬ ‫ﺷﻮﺩ‪ .‬ﺩﺭ ﻣﻘﺎﺑﻞ ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﯼ ﺩﺭﺳﺘﯽﻳﺎﺏ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺑﺎﻻﯼ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺩﺍﺩﻩ ﺭﺍ ﺑـﻪ ﻳـﮏ ‪ netlist‬ﺗﺒـﺪﻳﻞ‬ ‫ﻣﻲﮐﻨﻨﺪ ﻭ ﺗﻤﺎﻡ ﺍﻃﻼﻋﺎﺕ ﺳﺎﺧﺘﺎﺭﯼ ﺭﺍ ﺍﺯﺑﻴﻦﻣﻲﺑﺮﻧﺪ‪.‬‬ ‫ﻳﮑﯽ ﺍﺯ ﺍﻳﻦ ﻣﺴﺎﻳﻞ ﮐـﺎﺭﺍﻳﻲ ﺁﻥ ﺭﻭﯼ ﺩﺭﺳـﺘﯽﻳـﺎﺑﯽ ﮐﺎﺭﺑﺮﺩﻫـﺎﯼ ﮐﻨﺘﺮﻟـﯽ ﺍﺳـﺖ‪ ،‬ﺩﺭﺳـﺘﻲﻳـﺎﺑﯽ ﻃﺮﺍﺣﻴﻬـﺎ ﺑـﺎ‬ ‫ﻣﺴﻴﺮﺩﺍﺩﻩﻱ ﺭﻳﺎﺿﯽ ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺑﺴﻴﺎﺭ ﭘﻴﭽﻴﺪﻩ ﺍﺳﺖ ﻭ ﺑﺮﺍﯼ ﻣﺘﻐﻴﺮﻫﺎﯼ ﺍﺯ ﻧﻮﻉ ‪ word‬ﺭﻭﺷﻬﺎﯼ ﺩﻳﮕـﺮﻱ ﺩﺭ‬ ‫ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﻮﺭﻱ ﻃﺮﺍﺣﯽ ﺷﺪﻩﺍﺳﺖ‪ ،‬ﻣﺎﻧﻨﺪ ﺍﺛﺒﺎﺕ ﺗﺌﻮﺭﻳﮏ‪ ،‬ﺩﺳﺘﮑﺎﺭﯼ ﺟﺒﺮﯼ‪ ،‬ﺩﻭﺑﺎﺭﻩ ﻧﻮﻳﺴـﯽ ﻋﺒـﺎﺭﺍﺕ ﺑـﻪ‬ ‫ﮐﻤﮏ ﺩﺭﺧﺖ ﺧﺼﻮﺻﻴﺎﺕ‪ .١٤‬ﺩﺭ ﺍﻳﻦ ﭘﺎﻳﺎﻥﻧﺎﻣﻪ ﺍﺑﺘﺪﺍ ﻣﺪﻟﻬﺎﻱ ﺗﻮﺳﻌﻪﻳﺎﻓﺘﻪ ﮐﻪ ﺗﺎ ﺑـﻪ ﺍﻣـﺮﻭﺯ ﺑـﺮﺍﯼ ‪ BDD‬ﺩﺍﺩﻩ‪-‬‬ ‫ﺷﺪﻩﺍﺳﺖ ﺍﺭﺍﻳﻪ ﻣﻲﮔﺮﺩﺩ‪ .‬ﺳﭙﺲ ﻳﮏ ﻣﺪﻝ ﺟﺪﻳﺪ ﮐﻪ ﺍﺯ ﺗﻤﺎﻡ ﻣﺪﻟﻬﺎﯼ ﻗﺒﻠﯽ ﺳﻄﺢ ﺑﺎﻻﺗﺮ ﻭ ﺳـﺮﻳﻌﺘﺮ ﻣـﻲﺑﺎﺷـﺪ‪،‬‬ ‫ﺍﺭﺍﻳﻪ ﻭ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫‪term re-writing using attribute syntax trees 14‬‬ ‫‪۱۶‬‬ ‫‪ -۴-۲‬ﻣﺪﻟﻬﺎﻱ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺑﺮﺍﻱ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻃﺮﺍﺣﻲ‬ ‫ﺭﻭﺷﻬﺎﻱ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻛﻪ ﺩﺭ ﺍﻳﻦ ﭘﺎﻳﺎﻥﻧﺎﻣﻪ ﺍﺭﺍﻳﻪ ﻣﻲﺷﻮﺩ ﺑﺮﺍﺳﺎﺱ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‬ ‫ﻛﻪ ﺑﻌﺪ ﺍﺯ ﻣﺮﺣﻠﻪ ﻃﺮﺍﺣﻲ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺩﺭ ﭼﺮﺧﻪ ﻃﺮﺍﺣﻲ ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ‪ .‬ﺩﺭ ﺣﺎﻟـﺖ ﻛﻠـﻲ ﺳﻴﺴـﺘﻢﻫـﺎ‪،‬‬ ‫ﺗﺮﺗﻴﺒﻲ ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﻳﻌﻨﻲ ﺩﺍﺭﺍﻱ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪﺍﻱ ﻣﺎﻧﻨﺪ ﺭﺟﻴﺴﺘﺮﻫﺎ ﻣﻲﺑﺎﺷﻨﺪ ﻛﻪ ﻭﻇﻴﻔﻪ ﻧﮕﻬﺪﺍﺭﻱ ﺣﺎﻟـﺖ ﻗﺒﻠـﻲ‬ ‫ﺳﻴﺴﺘﻢ ﺭﺍ ﺑﺮﻋﻬﺪﻩ ﺩﺍﺭﻧﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﻣﻘﺪﺍﺭ ﻫﺮ ﻧﻘﻄﻪ ﺍﺯ ﺳﻴﺴﺘﻢ ﻧﻪ ﺗﻨﻬﺎ ﺑﻪ ﻭﺭﻭﺩﻳﻬﺎﻱ ﻓﻌﻠﯽ ﺑﻠﻜﻪ ﺑﻪ ﻭﺭﻭﺩﻳﻬـﺎﻱ‬ ‫ﻗﺒﻠﻲ ﻭ ﺗﺮﺗﻴﺐ ﺁﻧﻬﺎ ﻧﻴﺰ ﻭﺍﺑﺴﺘﻪ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﺪﻟﻬﺎﻱ ﺗﻐﻴﻴﺮ ﺣﺎﻟﺖ‪ ١٥‬ﺑﺮﺍﻱ ﺑﻴﺎﻥ ﻋﻤﻠﻜﺮﺩ ﺳﻴﺴﺘﻢ ﺑﻪ ﻛﺎﺭ ﻣﻲﺭﻭﺩ‪ .‬ﺩﺭ‬ ‫ﺍﻳﻦ ﺑﺨﺶ ﻣﺜﺎﻟﻬﺎﻳﻲ ﺍﺯ ﺍﻳﻦ ﻣﺪﻟﻬﺎ ﻛﻪ ﻣﺒﺘﻨﻲ ﺑﺮ ﻧﻤﺎﻳﺶ ﮔﺮﺍﻓﻲ ﻳﺎ ﻣﺪﻝ ﺭﻳﺎﺿﻴﺎﺗﻲ ﻣﻲﺑﺎﺷﻨﺪ ﺍﺭﺍﻳﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱-۴-۲‬ﻣﺪﻝ ﺷﺒﻜﻪ ﺳﺎﺧﺘﺎﺭﻱ‬ ‫‪١٦‬‬ ‫ﻳﻚ ﻣﺪﺍﺭ ﺩﻳﺠﻴﺘﺎﻝ ﻣﻲﺗﻮﺍﻧﺪ ﺑﻪ ﺻﻮﺭﺕ ﺗﺮﻛﻴﺒﻲ ﺍﺯ ﮔﻴﺘﻬﺎﻱ ﻣﻨﻄﻘﻲ ﻭ ﻣﺠﻤﻮﻋﻪﺍﻱ ﺍﺯ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﻣﺪﻝ ﺷﻮﺩ‪.‬‬ ‫ﮔﻴﺘﻬﺎﻱ ﻣﻨﻄﻘﻲ ﻛﻪ ﻣﻌﻤﻮ ﹰﻻ ﺩﺭ ﺍﻳﻦ ﻣﺪﻝ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ ﻋﺒﺎﺭﺗﻨﺪ ﺍﺯ ‪.XOR, NOT, OR, AND :‬‬ ‫ﻳﻚ ﻣﺪﺍﺭ ﺗﺮﺗﻴﺒﻲ ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺍﻭﻟﻴﻪ ﻭ ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﺧﺮﻭﺟﻴﻬﺎﻱ ﺍﻭﻟﻴﻪ ﺩﺍﺭﺩ‪ .‬ﻓـﺮﺽ ﺍﻳـﻦ ﻣـﺪﻝ‪،‬‬ ‫ﺍﻳﺪﻩﺁﻝ ﺑﻮﺩﻥ ﻋﻨﺎﺻﺮ ﻣﻨﻄﻘﻲ ﻣﻲﺑﺎﺷﺪ؛ ﻳﻌﻨﻲ ﻫﻴﭻ ﺗﺄﺧﻴﺮﻱ ﺩﺭ ﺍﻧﺘﺸﺎﺭ ﻣﻘﺎﺩﻳﺮ ﺍﺯ ﻭﺭﻭﺩﻱ ﺑـﻪ ﺧﺮﻭﺟـﻲ ﻗﺴـﻤﺖ‬ ‫ﺗﺮﻛﻴﺒﻲ ﻣﺪﺍﺭ ﻧﺪﺍﺭﻳﻢ‪ .‬ﺷﻜﻞ ‪ ۴-۲‬ﺣﺎﻟﺖ ﻛﻠﻲ ﺍﻳﻦ ﻣﺪﻝ ﺭﺍ ﻧﻤﺎﻳﺶ ﻣﻲﺩﻫﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۴-۲‬ﻣﺪﻝ ﺷﺒﮑﻪ ﺳﺎﺧﺘﺎﺭﯼ‬ ‫‪state Transition Models 15‬‬ ‫‪Structural Network Model 16‬‬ ‫‪۱۷‬‬ ‫ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻨﻜﻪ ﺩﺭ ﻣﺪﺍﺭﻫﺎﻱ ﻭﺍﻗﻌﻲ ﻣﺎ ﺩﺍﺭﺍﻱ ﺑﻴﺶ ﺍﺯ ﻳﻚ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺑﺮﺍﻱ ﻛـﻞ ﺳﻴﺴـﺘﻢ ﻫﺴـﺘﻴﻢ‪ .‬ﺩﺭ ﺍﻳـﻦ‬ ‫ﻣﺪﻝ ﻓﺮﺽ ﻣﻲﺷﻮﺩ ﻛﻪ ﺗﻤﺎﻣﻲ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﻣﻮﺟﻮﺩ ﻳﻚ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﻣﺸﺘﺮﻙ ﺩﺍﺭﻧﺪ‪ .‬ﻟـﻴﻜﻦ ﺩﺭ ﺍﻳـﻦ ﻣـﺪﻝ‬ ‫ﻣﻲﺗﻮﺍﻥ ﺳﻴﺴﺘﻢ ﻫﺎﻱ ﺩﺍﺭﺍﻱ ﺑﻴﺸﺘﺮ ﺍﺯ ﻳﻚ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺭﺍ ﻧﻴﺰ ﺑﺎ ﻓﺮﺽ ﺩﺍﺷﺘﻦ ﻳﻚ ﺳﻴﮕﻨﺎﻝ ﭘـﺎﻟﺲ ﺳـﺎﻋﺖ ﻭ‬ ‫ﺍﺿﺎﻓﻪ ﻛﺮﺩﻥ ﺗﻌﺪﺍﺩﻱ ﻋﻨﺎﺻﺮ ﻣﻨﻄﻘﻲ ﺑﻪ ﻭﺭﻭﺩﻱ ﺳﻴﺴﺘﻢ‪ ،‬ﻣﺪﻝ ﻛﺮﺩ‪.‬‬ ‫ﻣﺜﺎﻝ ‪ :۲-۲‬ﺷﻜﻞ ‪ ۵-۲‬ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﻣﺪﻝ ﺷﺒﻜﻪ ﺳﺎﺧﺘﺎﺭﻱ ﻳﻚ ﺷﻤﺎﺭﻧﺪﻩ ﺳﻪ ﺑﻴﺘﻲ ﺑـﺎﻻ ﻭ ﭘـﺎﻳﻴﻦ ﻫﻤـﺮﺍﻩ ﺑـﺎ‬ ‫ﺳﻴﮕﻨﺎﻝ ‪ reset‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻭﺭﻭﺩﻳﻬﺎﻱ ﺍﻳﻦ ﺳﻴﺴﺘﻢ ﺳﻴﮕﻨﺎﻟﻬﺎﻱ ‪ reset‬ﻭ ‪ count‬ﻣﻲﺑﺎﺷﺪ ﻭ ﺧﺮﻭﺟﻲ ﺳﻴﺴﺘﻢ ﺳـﻪ‬ ‫ﺑﻴﺖ ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﻣﻘﺪﺍﺭ ﻓﻌﻠﻲ ﺷﻤﺎﺭﻧﺪﻩ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻭﺭﻭﺩﻱ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺑﻪ ﺻـﻮﺭﺕ ﺿـﻤﻨﻲ ﺣـﺬﻑ ﺷـﺪﻩ‬ ‫ﺍﺳﺖ‪.‬‬ ‫ﺷﮑﻞ ‪ -۵-۲‬ﻣﺪﻝ ﺷﺒﮑﻪﺍﻱ ﺷﻤﺎﺭﻧﺪﻩ ﺳﻪ ﺑﻴﺘﯽ‬ ‫ﺍﻳﻦ ﺳﻴﺴﺘﻢ ﺩﺍﺭﺍﻱ ‪ ۴‬ﻋﻨﺼﺮ ﺣﺎﻓﻈﻪ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻭﻇﻴﻔﻪﻱ ﺁﻧﻬـﺎ ﻧﮕﻬـﺪﺍﺭﻱ ﻣﻘـﺪﺍﺭ ﻓﻌﻠـﻲ ﺷـﻤﺎﺭﻧﺪﻩ ﻭ ﺟﻬـﺖ‬ ‫ﺷﻤﺎﺭﺵ ﺁﻥ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﻫﺮ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺳﻴﺴﺘﻢ ﻣﻘﺪﺍﺭ ﺷﻤﺎﺭﻧﺪﻩ ﺭﺍ ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﺳﻴﮕﻨﺎﻝ ﻭﺭﻭﺩﻱ ‪count‬‬ ‫ﻣﺴﺎﻭﻱ ﻳﻚ ﺑﺎﺷﺪ‪ ،‬ﺗﻐﻴﻴﺮ ﻣﻲﺩﻫﺪ‪ .‬ﺍﻳﻦ ﻣﻘﺪﺍﺭ ﺗﺎ ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﺑـﻪ ﻣـﺎﻛﺰﻳﻤﻢ ﺧـﻮﺩ ﺑﺮﺳـﺪ ﺍﻓـﺰﺍﻳﺶ ﻣـﻲﻳﺎﺑـﺪ ﻭ‬ ‫ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﺑﻪ ﻣﻘﺪﺍﺭ ‪ ۷‬ﺭﺳﻴﺪ‪ ،‬ﺷﺮﻭﻉ ﺑﻪ ﺷﻤﺎﺭﺵ ﺑﻪ ﭘﺎﻳﻴﻦ ﺗﺎ ﻋﺪﺩ ﺻﻔﺮ ﺭﺍ ﻣﻲﻛﻨﺪ‪ .‬ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﺳﻴﮕﻨﺎﻝ ‪reset‬‬ ‫ﺑﺮﺍﺑﺮ ﻳﻚ ﺷﻮﺩ‪ ،‬ﺷﻤﺎﺭﻧﺪﻩ ﺑﻪ ﻣﻘﺪﺍﺭ ﺻﻔﺮ ﻣﻲﺭﻭﺩ‪ .‬ﻗﺴﻤﺖ ﻧﻘﻄﻪﭼﻴﻦ ﺩﺭ ﺷﻜﻞ ﻧﺸﺎﻥ ﺩﻫﻨـﺪﻩﻱ ﺑﺨـﺶ ﺗﺮﻛﻴﺒـﻲ‬ ‫‪۱۸‬‬ ‫ﻣﺪﺍﺭ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۲-۴-۲‬ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ‬ ‫‪١٧‬‬ ‫ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﺭﻭﺵ ﺩﻳﮕﺮ ﻣﺪﻝﺳﺎﺯﻱ ﺭﻓﺘﺎﺭ ﻳﻚ ﺳﻴﺴﺘﻢ ﺗﺮﺗﻴﺒﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻛﻪ ﺑﻪ ﻭﺳﻴﻠﻪﻱ ‪ FSM‬ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩ‬ ‫ﻣﻲﺷﻮﺩ‪ .‬ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﻳﻚ ﮔﺮﺍﻑ ﺟﻬﺘﺪﺍﺭ ﺑﺮﭼﺴﺐ‪١٨‬ﺩﺍﺭ ﺍﺳﺖ ﻛﻪ ﻫﺮ ﮔﺮﻩ ﺁﻥ ﻧﻤﺎﻳﻨﺪﻩﻱ ﻳﻚ ﺣﺎﻟﺖ ﻣﻤﻜـﻦ‬ ‫ﺑﺮﺍﻱ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻳﺎﻟﻬﺎﻳﻲ ﻛﻪ ﮔﺮﻩﻫﺎ ﺭﺍ ﺑﻪ ﻫﻢ ﻣﺘﺼﻞ ﻣﻲﻛﻨﻨﺪ ﻧﻤﺎﻳﻨﺪﻩﻱ ﺗﻐﻴﻴﺮ ﺍﺯ ﻳﻚ ﺣﺎﻟـﺖ ﺑـﻪ ﺣﺎﻟـﺖ‬ ‫ﺩﻳﮕﺮ ﻣﻲﺑﺎﺷﻨﺪ ﻭ ﻭﺭﻭﺩﻱ ﺧﺎﺻﻲ ﻛﻪ ﻣﻲﺗﻮﺍﻧﺪ ﺩﺭ ﻳﻚ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺑﺎﻋـﺚ ﺍﻳـﻦ ﺗﻐﻴﻴـﺮ ﺷـﻮﺩ ﺭﻭﻱ ﺁﻥ ﻳـﺎﻝ‬ ‫ﻧﻮﺷﺘﻪ ﺷﺪﻩ ﺍﺳﺖ‪.‬‬ ‫ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﺗﻨﻬﺎ ﻣﻲﺗﻮﺍﻧﺪ ﻋﻤﻠﻜﺮﺩ ﺳﻴﺴﺘﻢ ﺭﺍ ﺑﻴﺎﻥ ﻛﻨﺪ‪ ،‬ﻭ ﺟﺰﺋﻴﺎﺕ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻣﺪﺍﺭﻱ ﻛـﻪ ﻣـﻲﺗﻮﺍﻧـﺪ ﺍﻳـﻦ‬ ‫ﻋﻤﻠﻜﺮﺩ ﺭﺍ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ ﺩﺭ ﻧﻈﺮ ﮔﺮﻓﺘﻪ ﻧﺸﺪﻩ ﺍﺳﺖ‪ .‬ﺧﺮﻭﺟﻲ ﺳﻴﺴﺘﻢ ﺩﺭ ﻫﺮ ﺣﺎﻟﺖ ﻧﻴﺰ ﺩﺭ ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﺑﻴﺎﻥ‬ ‫ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺩﺭ ﻣﺪﻝ ﻣﻴﻠﻲ )‪ ،(Mealy‬ﺧﺮﻭﺟﻲ ﺳﻴﺴﺘﻢ ﺑﻪ ﻳﺎﻟﻬﺎ ﻧﺴﺒﺖ ﺩﺍﺩﻩ ﺷـﺪﻩ ﺍﺳـﺖ‪ .‬ﻭﻟـﻲ ﺩﺭ ﻣـﺪﻝ ﻣـﻮﺭ‬ ‫)‪ (Moore‬ﮔﺮﻩﻫﺎ ﺑﻪ ﺻﻮﺭﺕ ﺩﻭ ﻗﺴﻤﺘﻲ ﺧﺮﻭﺟﻲ‪ /‬ﺣﺎﻟﺖ ﺑﻴﺎﻥ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺣﺎﻟﺖ ﺍﻭﻟﻴﻪ ﺳﻴﺴﺘﻢ ﺑﻪ ﺻـﻮﺭﺕ ﺩﻭ‬ ‫ﺩﺍﻳﺮﻩ ﺗﻮ ﺩﺭ ﺗﻮ ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺷﮑﻞ ‪ -۶-۲‬ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﻣﻮﺭ ﺑﺮﺍﯼ ﺷﻤﺎﺭﻧﺪﻩﻱ ﺳﻪ ﺑﻴﺘﻲ‬ ‫ﻣﺜﺎﻝ ‪ :۳-۲‬ﺷﻜﻞ ‪ ۶-۲‬ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﻣﻮﺭ ﻣﺪﻝ ﻛﻨﻨﺪﻩﻱ ﺷﻤﺎﺭﻧﺪﻩﻱ ﺳﻪ ﺑﻴﺘﻲ ﻣﺜﺎﻝ ‪ ۲-۲‬ﻣﻲﺑﺎﺷﺪ ﻫـﺮ ﺣﺎﻟـﺖ‬ ‫‪State diagram 17‬‬ ‫‪label 18‬‬ ‫‪۱۹‬‬ ‫ﻣﺸﺨﺺ ﻛﻨﻨﺪﻩ ﻣﻘﺪﺍﺭ ﺫﺧﻴﺮﻩ ﺷﺪﻩ ﺩﺭ ﺳﻪ ‪ ( x 2 , x1 , xo ) flip-flop‬ﻭ ﺟﻬﺖ ﺷﻤﺎﺭﺵ ﻣﻲﺑﺎﺷﺪ ﺭﻭﻱ ﻫـﺮ ﻳـﺎﻝ‬ ‫ﺳﻴﮕﻨﺎﻝ ﻭﺭﻭﺩﻱ ﻣﻮﺭﺩﻧﻴﺎﺯ ﺑﺮﺍﻱ ﺭﺳﻴﺪﻥ ﺍﺯ ﺣﺎﻟﺖ ﺍﺑﺘﺪﺍﻱ ﻳﺎﻝ ﺑﻪ ﺣﺎﻟﺖ ﺍﻧﺘﻬـﺎﻱ ﻳـﺎﻝ ﺩﺭ ﻳـﻚ ﭘـﺎﻟﺲ ﺳـﺎﻋﺖ‬ ‫ﻧﻮﺷﺘﻪ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺣﺎﻟﺖ ﺍﻭﻟﻴﻪ ﺳﻴﺴﺘﻢ ﻧﻴﺰ ﺑﺎ ﺩﻭ ﺩﺍﻳﺮﻩ ﺗﻮ ﺩﺭ ﺗﻮ ﻣﺸﺨﺺ ﺷﺪﻩ ﺍﺳﺖ‪.‬‬ ‫ﺑﺎﻳﺪ ﺗﻮﺟﻪ ﺩﺍﺷﺖ ﻛﻪ ﺩﺭ ﺣﺎﻟﺖ ﻛﻠﻲ ﺗﻌﺪﺍﺩ ﻭﺿﻌﻴﺘﻬﺎﻳﻲ ﻛﻪ ﻳﻚ ﺳﻴﺴﺘﻢ ﻣﻲﺗﻮﺍﻧﺪ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‪ ،‬ﺍﺯ ﺗﻤﺎﻡ ﺣﺎﻻﺗﻲ‬ ‫ﻛﻪ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﻣﻲﺗﻮﺍﻧﻨﺪ ﺑﮕﻴﺮﻧﺪ ﻛﻤﺘﺮ ﺍﺳﺖ‪.‬‬ ‫‪ -۳-۴-۲‬ﻣﺪﻝ ﺭﻳﺎﺿﻲ ﺑﺮﺍﻱ ‪ FSM‬ﻫﺎ‬ ‫ﻳﻚ ﺭﻭﺵ ﺩﻳﮕﺮ ﺑﺮﺍﻱ ﺑﻴﺎﻥ ﻛﺮﺩﻥ ‪ FSM‬ﻫﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺗﻮﺻﻴﻒ ﺭﻳﺎﺿﻲ ﺣﺎﻟﺘﻬـﺎ ﻭ ﻗﻮﺍﻋـﺪﻱ ﻛـﻪ ‪transition‬‬ ‫ﻼ ﻣﺸـﺨﺺ ﺑـﺎ ﻳـﻚ ‪ ۶‬ﺗـﺎﻳﻲ ﻣﺸـﺨﺺ‬ ‫ﺑﻴﻦ ﺣﺎﻟﺘﻬﺎ ﺭﺍ ﺍﻧﺠﺎﻡ ﻣﻲﺩﻫﺪ ﺍﺳﺖ‪ .‬ﺩﺭ ﺑﻴﺎﻥ ﺭﻳﺎﺿﻲ ﻳﻚ ‪ FSM‬ﻛـﺎﻣ ﹰ‬ ‫ﻣﻲﺷﻮﺩ ﻛﻪ‬ ‫) ‪M = ( I , O, S , δ , S o , λ‬‬ ‫ﺑﻪ ﺻﻮﺭﺗﻲ ﻛﻪ ‪:‬‬ ‫ ‪ I‬ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﻣﺮﺗﺐ )‪ (i, ..., im‬ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺑﻮﻟﻲ ﻭﺭﻭﺩﻱﻫﺎ ﺍﺳﺖ‪.‬‬‫ ‪ O‬ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﻣﺮﺗﺐ )‪ (o1, ..., op‬ﺍﺯ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ﺧﺮﻭﺟﻴﻬﺎ ﺍﺳﺖ‪.‬‬‫ ‪ S‬ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﻣﺮﺗﺐ )‪ (S1, ..., Sn‬ﺍﺯ ﺣﺎﻟﺘﻬﺎﻱ ﺳﻴﺴﺘﻢ ﺍﺳﺖ‪.‬‬‫‪δ : S × I : B n+m → S : B n‬‬ ‫‪-‬‬ ‫‪ δ‬ﺗﺎﺑﻊ ﺣﺎﻟﺖ ﺑﻌﺪﻱ ﺍﺳﺖ‪:‬‬ ‫‪-‬‬ ‫‪ λ‬ﺗﺎﺑﻊ ﺧﺮﻭﺟﻲ ﺳﻴﺴﺘﻢ ﺍﺳﺖ‪:‬‬ ‫‪-‬‬ ‫‪ S o‬ﺣﺎﻟﺖ ﺍﻭﻟﻴﻪ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪λ : S × I : B n+m → O : B P‬‬ ‫ﺗﻌﺮﻳــﻒ ﺑــﺎﻻ ﺑــﺮﺍﻱ ﻣــﺪﻝ ﻣﻴﻠــﻲ ‪ FSM‬ﻫــﺎ ﻣــﻲﺑﺎﺷــﺪ‪ ،‬ﺑــﺮﺍﻱ ﻣــﺪﻝ ﻣــﻮﺭ ﺗــﺎﺑﻊ ﺧﺮﻭﺟــﻲ ﺑــﻪ‬ ‫ﺻﻮﺭﺕ ‪ λ : S : B n → O : B P‬ﺩﺭ ﻣﻲﺁﻳﺪ‪.‬‬ ‫ﻣﺪﻝ ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﺑﺴﻴﺎﺭ ﻗﺎﺑﻞ ﺩﺭﻙﺗﺮ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻭﻟﻲ ﻣﺪﻝ ﺭﻳﺎﺿﻲ ﻳﻚ ﺗﻮﺻﻴﻒ ﺻﻮﺭﻱ ﺍﺯ ‪ FSM‬ﻣﻲﺑﺎﺷـﺪ‪.‬‬ ‫ﻣﺪﻝ ﺭﻳﺎﺿﻲ ﺑﺮﺍﻱ ﺳﻴﺴﺘﻤﻬﺎ ﺑﺎ ﺗﻌﺪﺍﺩ ﺣﺎﻟﺘﻬﺎﻱ ﺑﺴﻴﺎﺭ ﺯﻳﺎﺩ ﻣﻨﺎﺳﺒﺘﺮ ﻭ ﺑﺴﻴﺎﺭ ﻓﺸﺮﺩﻩﺗﺮ ﺍﺳﺖ ﺩﺭ ﻣﻘﺎﺑﻞ ﺩﻳـﺎﮔﺮﺍﻡ‬ ‫‪۲۰‬‬ ‫ﺣﺎﻟﺖ ﺩﺭ ﺳﻴﺴﺘﻤﻬﺎﻱ ﺑﺰﺭﮒ ﻏﻴﺮﻗﺎﺑﻞ ﺭﺳﻢ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۵-۲‬ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ‬ ‫ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻋﻤﻠﮑﺮﺩ ﻣﻌﻤﻮﻻ ﺗﻮﺳﻂ ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﯼ ﺷﺒﻴﻪﺳﺎﺯ ﺍﻧﺠﺎﻡ ﻣﻲﺷـﻮﺩ ﮐـﻪ ﺩﺭ ﺍﮐﺜـﺮ ﻣـﻮﺍﺭﺩ ﺍﺯ‬ ‫ﺍﻟﮕﻮﺭﻳﺘﻢ ﺑﺎﺭﺯﻳﻼﯼ ﻭ ﻫﺎﻧﺴﻮﻥ ]‪ [۱‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮐﻨﻨﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺍﺯ ﺗﻌﺮﻳﻒ ﺳﻄﺢ ﮔﻴﺖ ﻣﺪﺍﺭ ﺍﺳﺘﻔﺎﺩﻩ ﻣـﻲ‪-‬‬ ‫ﺷﻮﺩ ﻭ ﺍﺑﺘﺪﺍ ﺩﺭ ﺍﺯﺍﯼ ﻫﺮ ﮔﻴﺖ ﭼﻨﺪ ﻭﺭﻭﺩﯼ ﺩﻭ ﻳﺎ ﭼﻨﺪ ﮔﻴﺖ ﺩﻭ ﻭﺭﻭﺩﯼ ﻗﺮﺍﺭ ﻣـﻲﮔﻴـﺮﺩ ﺳـﭙﺲ ﺁﻧﻬـﺎ ﺭﺍ ﺑـﺮ‬ ‫ﺍﺳﺎﺱ ﻓﺎﺻﻠﻪ ﺁﻧﻬﺎ ﺍﺯ ﻭﺭﻭﺩﻳﻬﺎﯼ ﻣﺪﺍﺭ ﻣﺮﺗﺐ ﻣﻲﮐﻨﺪ‪ ،‬ﭘﺲ ﺍﺯ ﺁﻥ ﺍﻟﮕﻮﺭﻳﺘﻢ ﺑﻪ ﺍﺯﺍﯼ ﻫﺮ ﮔﻴﺖ ﻳﮏ ﺧـﻂ ﺑﺮﻧﺎﻣـﻪ‬ ‫ﺍﺳﻤﺒﻠﯽ ﻣﻌﺎﺩﻝ ﻗﺮﺍﺭ ﻣﯽﺩﻫﺪ‪ .‬ﺗﺮﺗﻴﺐ ﮔﻴﺘﻬﺎ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺗﺮﺗﻴﺐ ﺧﻄﻮﻁ ﺑﺮﻧﺎﻣﻪ ﺗﻀﻤﻴﻦ ﻣﻲﮐﻨﺪ ﮐـﻪ ﻭﺭﻭﺩﻳﻬـﺎﯼ‬ ‫ﻫﺮ ﺧﻂ ﺩﺭ ﻫﻨﮕﺎﻡ ﺍﺟﺮﺍﯼ ﺁﻥ ﻣﺸﺨﺺ ﺷﺪﻩﺍﺳﺖ‪ .‬ﺍﻳﻦ ﺑﺮﻧﺎﻣﻪ ﺍﺳﻤﺒﻠﯽ ﻧﻤﺎﻳﺎﻧﮕﺮ ﮐﻞ ﺳﻴﺴـﺘﻢ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺣـﺎﻝ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﯼ ﺑﺎ ﺍﻋﻤﺎﻝ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ ﺑﻪ ﻋﻨﻮﺍﻥ ﻭﺭﻭﺩﯼ ﺑﺮﻧﺎﻣﻪ ﺍﻧﺠﺎﻡ ﻣﻲﺷـﻮﺩ ﻭ ﮐﺎﻣﭙـﺎﻳﻠﺮ ﺍﺳـﻤﺒﻠﯽ ﺧﺮﻭﺟـﯽ‬ ‫ﺑﺮﻧﺎﻣﻪ ﺭﺍ ﻣﺤﺎﺳﺒﻪ ﻣﻲﮐﻨﺪ ﻭ ﺑﺮﺍﯼ ﺑﺮﺭﺳﻴﻬﺎﯼ ﺑﻌﺪﯼ ﺩﺭ ﻳﮏ ﻓﺎﻳﻞ ﺫﺧﻴﺮﻩ ﻣﻲﮐﻨﺪ‪.‬‬ ‫ﻣﺜﺎﻝ ‪ : ۴-۲‬ﺷﻜﻞ ﺷﻤﺎﺭﻩﻱ ‪ ۷-۲‬ﻣﺪﺍﺭ ﺳﻄﺢ ﮔﻴﺖ ﺷﻤﺎﺭﻧﺪﻩﻱ ﻣﺜﺎﻝ‪ ۲-۲‬ﺭﺍ ﻧﺸﺎﻥ ﻣﻲﺩﻫﺪ ﻛـﻪ ﺑـﺮﺍﻱ ﺍﺟـﺮﺍﻱ‬ ‫ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﺑﻪ ﻫﺮﻳﻚ ﺍﺯ ﮔﻴﺘﻬﺎﻱ ﺑﺨﺶ ﺗﺮﻛﻴﺒﻲ ﻳﻚ ﺷﻤﺎﺭﻩﻱ ﺳﻄﺢ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻓﺎﺻـﻠﻪﻱ ﺁﻥ ﺑـﺎ ﻭﺭﻭﺩﻱﻫـﺎ‬ ‫ﻧﺴﺒﺖ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ )ﺍﻋﺪﺍﺩ ‪ (Italic‬ﺩﺭ ﺍﺩﺍﻣﻪ ﺑﻪ ﻫﺮﻳﻚ ﺍﺯ ﮔﻴﺘﻬﺎ ﻳـﻚ ﻋـﺪﺩ )ﺍﻋـﺪﺍﺩ ﺗـﻮﭘﺮ( ﻛـﻪ ﻧﻤﺎﻳﻨـﺪﻩﻱ‬ ‫ﺷﻤﺎﺭﻩ ﺧﻂ ﺁﻧﻬﺎ ﺩﺭ ﻛﺪ ﺍﺳﻤﺒﻠﻲ ﻣﻲﺑﺎﺷﺪ ﻧﺴﺒﺖ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪.‬‬ ‫ﺷﮑﻞ ‪ -۷-۲‬ﻣﺪﺍﺭ ﻣﺜﺎﻝ ‪ ۲-۲‬ﮐﻪ ﺑﺮﺍﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﺮﺗﺐ ﺷﺪﻩﺍﺳﺖ‬ ‫‪۲۱‬‬ ‫ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﺻﻞ ﻣﻲﺗﻮﺍﻥ ﺑﺮﻧﺎﻣﻪ ﺍﺳﻤﺒﻠﻲ ﺯﻳﺮ ﺭﺍ ﻧﻮﺷﺖ‪ ،‬ﻫﺮﻳﻚ ﺍﺯ ﺧﻄﻮﻁ ﺩﺍﺭﺍﻱ ﺗﻨﺎﻇﺮ ﻳﻚ ﺑﻪ ﻳﻚ‬ ‫ﺑﺎ ﮔﻴﺘﻬﺎﻱ ﻣﺪﻝ ﺳﺎﺧﺘﺎﺭﻱ ﻣﺪﺍﺭ ﻣﻲﺑﺎﺷﻨﺪ‪.‬‬ ‫)‪1. r1 = NOT (x1‬‬ ‫)‪2. r2 = OR (x0, x1‬‬ ‫…‬ ‫)‪11. r11 = XOR (x0, count‬‬ ‫…‬ ‫)‪27. r27 = AND (r24, r12‬‬ ‫…‬ ‫ﺣﺎﻝ ﻛﺎﻣﭙﺎﻳﻠﺮ ﺑﻪ ﺍﺯﺍﻱ ﻫﺮﻳﻚ ﺍﺯ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﻳﻚ ﺧﺎﻧﻪﻱ ﺣﺎﻓﻈﻪ ﺍﺯ ﺳﻴﺴﺘﻢ ﺷﺒﻴﻪﺳﺎﺯ ﺗﺨﺼـﻴﺺ ﻣـﻲﺩﻫـﺪ‪.‬‬ ‫ﮐﺪ ﺍﺳﻤﺒﻠﯽ ﻣﻌﺎﺩﻝ ﮔﻴﺘﻬﺎﻱ ﺑﺎ ﭼﻨﺪ ﻭﺭﻭﺩﻱ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﺎ ﺗﺒﺪﻳﻞ ﻋﻤﻠﻜﺮﺩ ﺁﻧﻬـﺎ ﺑـﻪ ﭼﻨـﺪ ﻋﻤـﻞ ﺑﺪﺳـﺖ ﺁﻭﺭﺩ‪.‬‬ ‫ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﺩﺭ ﻣﺜﺎﻝ ‪ ۴-۲‬ﮔﻴﺖ ‪ XOR‬ﺳﻪ ﻭﺭﻭﺩﻱ ‪ ۷‬ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺩﺭﺁﻭﺭﺩ‪:‬‬ ‫)‪7. r2temp = XOR (up, x1‬‬ ‫)‪7bis. r7 = XOR(r7temp, x0‬‬ ‫ﻣﺸﺎﻫﺪﻩ ﻣﻲﺷﻮﺩ ﮐﻪ ﺑﺎ ﻳﮏ ﺗﺨﻤﻴﻦ ﺍﻭﻟﻴﻪ ﻭ ﻓﺮﺽ ﻳﮏ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺑﺮﺍﯼ ﺍﺟﺮﺍﯼ ﻫﺮ ﺧﻂ ﮐﺪ ﺍﺳﻤﺒﻠﯽ‪ ،‬ﺯﻣـﺎﻥ‬ ‫ﺍﺟﺮﺍﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﺑﺎ ﭘﻴﭽﻴﺪﮔﯽ ﻣﺪﺍﺭ ﻭ ﻃﻮﻝ ﺑﺮﺩﺍﺭ ﺗﺴﺖ ﺑﻪ ﺻﻮﺭﺕ ﺧﻄﯽ ﻣﺘﻨﺎﺳـﺐ ﺍﺳـﺖ‪ .‬ﺳـﺮﻋﺖ ﺑـﺎﻻ ﻭ‬ ‫ﺭﺷﺪ ﺧﻄﯽ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻨﻄﻘﯽ‪ ،‬ﺩﻻﻳﻞ ﺍﺻﻠﯽ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺭﻭﺵ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﻧﺎﻡ ﺭﻭﺷﯽ ﮐﻪ ﺑﻴﺎﻥ ﺷﺪ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﺒﺘﻨﯽ ﺑﺮ ﭼﺮﺧﻪ ﺑﻮﺩ‪ ،‬ﺭﻭﺵ ﺩﻳﮕﺮ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺑﻪﻭﺳﻴﻠﻪﻱ ﻧـﺮﻡﺍﻓـﺰﺍﺭ ﺭﻭﺵ‬ ‫ﻣﺒﺘﻨﯽ ﺑﺮ ﺭﻭﻳﺪﺍﺩ ﺍﺳﺖ‪ ،‬ﺗﻔﺎﻭﺕ ﺍﺻﻠﯽ ﺍﻳﻦ ﺩﻭ ﺭﻭﺵ ﺍﻳﻦ ﺍﺳﺖ ﮐـﻪ ﺩﺭ ﺭﻭﺵ ﺩﻭﻡ ﻫـﺮ ﮔﻴـﺖ ﻓﻘـﻂ ﻫﻨﮕـﺎﻣﯽ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻲﺷﻮﺩ ﮐﻪ ﻭﺭﻭﺩﯼ ﺁﻥ ﺗﻐﻴﻴﺮ ﮐﻨﺪ‪ .‬ﺍﻳﻦ ﺭﻭﺵ ﺑﺎﻋﺚ ﺩﻗﺖ ﺑﻴﺸﺘﺮ ﺩﺭ ﺷﺒﻴﻪﺳـﺎﺯﯼ ﻣـﻲﺷـﻮﺩ‪ ،‬ﺯﻳـﺮﺍ‬ ‫ﺍﺗﻔﺎﻗﺎﺗﯽ ﺭﺍ ﮐﻪ ﺩﺭ ﻣﻴﺎﻥ ﭼﺮﺧﻪ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺭﻭﯼ ﻣﻲﺩﻫﺪ‪ ،‬ﻧﻴﺰ ﺑﺮﺭﺳﯽ ﻣﻲﮐﻨﺪ‪.‬‬ ‫ﺍﺑﺰﺍﺭﻫﺎﻱ ﺗﺠﺎﺭﻱ ﺑﺴﻴﺎﺭﯼ ﺑﺮﺍﻱ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻳﻚ ﻳﺎ ﻫﺮ ﺩﻭ ﺭﻭﺷﯽ ﻛﻪ ﺩﺭ ﺑﺎﻻ ﺑﻴﺎﻥ ﺷﺪ ﺍﺭﺍﻳـﻪ ﺷـﺪﻩ ﺍﺳـﺖ‪ ،‬ﻛـﻪ‬ ‫ﻗﺎﺑﻠﻴﺖ ﺑﺮﺭﺳﻲ ﻣﺪﺍﺭﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ ﭘﻴﭽﻴـﺪﻩﻱ ﺍﻣـﺮﻭﺯ ﺭﺍ ﺩﺍﺭﺍ ﻣـﻲﺑﺎﺷـﻨﺪ‪ .‬ﺍﻳـﻦ ﻧﻜﺘـﻪ ﻗﺎﺑـﻞ ﺗﻮﺟـﻪ ﺍﺳـﺖ ﻛـﻪ‬ ‫‪۲۲‬‬ ‫ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﻱ ﺷﺒﻴﻪﺳﺎﺯ ﻣﺒﺘﻨﻲ ﺑﺮ ﭼﺮﺧﻪ ﺑﺮﺍﻱ ﺍﻓﺰﺍﻳﺶ ﻛﺎﺭﺍﻳﻲ ﺧﻮﺩ ﺑﻪ ﻛﺎﺭ ﺑﺮ ﺍﺟـﺎﺯﻩ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ ﭼﻨـﺪ ﭘـﺎﻟﺲ‬ ‫ﺳﺎﻋﺖ ﻭ ﺗﺮﻛﻴﺐ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻣﺒﺘﻨﻲ ﺑﺮ ﭼﺮﺧﻪ ﻭ ﻣﺒﺘﻨﻲ ﺑﺮ ﺭﻭﻳﺪﺍﺩ ﺭﺍ ﻣﻲﺩﻫﻨﺪ ‪ .‬ﺩﺭ ﻃﺮﺍﺣﻲ ﺳﻴﺴـﺘﻢ ﺩﻳﺠﻴﺘـﺎﻝ‪،‬‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻫﺎ‪ ،‬ﻫﺴﺘﻪﻱ ﺍﺻﻠﻲ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ ﺭﺍ ﺩﺭ ﺑﺮ ﻣﻲﮔﻴﺮﻧﺪ‪ .‬ﻭﻟﻲ ﻃﺮﺍﺣﻲ ﺑﺮﺩﺍﺭ ﺗﺴﺖ ﻣﻨﺎﺳﺐ ﺑـﺮﺍﻱ‬ ‫ﺳﻴﺴﺘﻢ ﻳﻚ ﻛﺎﺭ ﻭﻗﺖﮔﻴﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﻌﻤﻮ ﹰﻻ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﺑﻪ ﮔﻮﻧﻪﺍﻱ ﻃﺮﺍﺣـﻲ ﻣـﻲ ﺷـﻮﻧﺪ ﻛـﻪ ﻫـﺮ ﺭﺷـﺘﻪ‬ ‫ﻣﺮﺗﺐ ﺍﺯ ﺁﻧﻬﺎ ﻳﻜﻲ ﺍﺯ ﺟﻨﺒﻪﻫﺎﻱ ﻋﻤﻠﻜﺮﺩ ﻃﺮﺡ ﺭﺍ ﺑﺮﺭﺳﻲ ﻛﻨﺪ‪ .‬ﻫـﺮ ﺭﺷـﺘﻪ ﺍﺯ ﺑﺮﺩﺍﺭﻫـﺎﻱ ﺗﺴـﺖ ﺗﻮﺳـﻂ ﺗـﻴﻢ‬ ‫ﻣﻬﻨﺪﺳﺎﻥ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺑﺎ ﺩﺳﺖ ﻃﺮﺍﺣﻲ ﻣﻲﺷﻮﺩ‪ .‬ﺧﺮﻭﺟﻲ ﺣﺎﺻﻞ ﺍﺯ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻴﺰ ﺑﻪ ﺻـﻮﺭﺕ ﻏﻴﺮﺧﻮﺩﻛـﺎﺭ‬ ‫ﺑﺮﺭﺳﻲ ﻣﻲﺷﻮﺩ ﻛﻪ ﻫﺮ ﺩﻭ ﻣﺮﺣﻠﻪ ﻣﻨﺎﺑﻊ ﻭﻗﺖ ﺯﻳﺎﺩﻱ ﺍﺯ ﺗﻴﻢ ﻃﺮﺍﺣﻲ ﺭﺍ ﻫﺪﺭ ﻣﻲﺩﻫﻨﺪ‪ . .‬ﻳﮑﯽ ﺩﻳﮕﺮ ﺍﺯ ﻣﻌﺎﻳﺐ‬ ‫ﺍﻳﻦ ﺭﻭﺵ ﺍﻳﻦ ﺍﺳﺖ ﮐﻪ ﻃﺮﺍﺡ ﺑﺮﺍﯼ ﻃﺮﺍﺣﯽ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ ﻓﻘﻂ ﺑﻪ ﺗﻮﺻﻴﻒ ﻃﺮﺍﺣﯽ ﺗﻮﺟـﻪ ﻣـﻲﮐﻨـﺪ ﻭ ﺩﺭ‬ ‫ﻧﺘﻴﺠﻪ ﻣﺨﺼﻮﺻﺎ ﺩﺭ ﺳﻴﺴﺘﻤﻬﺎﯼ ﭘﻴﭽﻴﺪﻩ ﺍﺣﺘﻤﺎﻝ ﺑﺮﻭﺯ ﺍﺗﻔﺎﻗﺎﺕ ﻏﻴﺮﻗﺎﺑﻞ ﭘﻴﺶﺑﻴﻨﯽ ﻭﺟـﻮﺩ ﺩﺍﺭﺩ ﮐـﻪ ﺩﻟﻴـﻞ ﺁﻥ‬ ‫ﻋﺪﻡ ﺑﺮﺭﺳﯽ ﺷﺮﺍﻳﻂ ﻣﺮﺯﻱ ﺧﺎﺹ ﮐﻪ ﺗﻮﺳﻂ ﺗﻮﺻﻴﻒ ﻃﺮﺍﺣﯽ ﻣﺸﺨﺺ ﻧﺸﺪﻩﺍﻧﺪ‪ ،‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺨﺸﻬﺎﻱ ﻗﺒﻞ ﮔﻔﺘﻪ ﺷﺪ‪ ،‬ﺩﺭ ﺑﻌﻀﻲ ﺍﺯ ﺯﺑﺎﻧﻬﺎﻱ ﺑﺮﻧﺎﻣﻪﻧﻮﻳﺴﻲ ﺳﻄﺢ ﺑﺎﻻ ﺑﻪ ﻛﺎﺭﺑﺮ ﺍﻣﻜـﺎﻥ ﺩﺍﺩﻩ‬ ‫ﻣﻲﺷﻮﺩ ﻛﻪ ﺍﺯ ﺩﺳﺘﻮﺭﺍﺕ ﺁﻥ ﺑﺮﺍﻱ ﺍﻳﺠﺎﺩ‪ ،‬ﺍﻋﻤﺎﻝ ﻭ ﺑﺮﺭﺳﻲ ﻧﺘﺎﻳﺞ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﺍﺳﺘﻔﺎﺩﻩ ﻛﻨﺪ‪ .‬ﺍﻳﻦ ﺑﺮﻧﺎﻣـﻪﻫـﺎ‬ ‫ﻫﻤﺰﻣﺎﻥ ﺑﺎ ﺷﺒﻴﻪﺳﺎﺯ ﺍﺟﺮﺍ ﻣﻲﺷﻮﻧﺪ ﻭ ﺩﺭ ﻫﺮ ﻣﺮﺣﻠﻪ ﺩﺍﺩﻩﻫﺎﻱ ﺧﺮﻭﺟﻲ ﺁﻥ ﺭﺍ ﺩﺭﻳﺎﻓﺖ ﻛﺮﺩﻩ ﻭ ﻭﺭﻭﺩﻱ ﺟﺪﻳـﺪ‬ ‫ﺑﻪ ﺁﻥ ﻣﻲﺩﻫﺪ‪ .‬ﻣﺎﺟﻮﻝ ﺩﻳﮕﺮﻱ ﻛﻪ ﻣﻮﺍﺯﻱ ﺑﺎ ﺷﺒﻴﻪ ﺳﺎﺯ ﺍﺟﺮﺍ ﻣﻲﺷﻮﺩ‪ ،‬ﺍﺑﺰﺍﺭ ﭘﺮﺩﺍﺯﺵ ﺩﺍﺩﻩﻫﺎﻱ ﺧﺮﻭﺟـﻲ ﻣـﻲ‪-‬‬ ‫ﺑﺎﺷﺪ ﻛﻪ ﺩﺍﺩﻩﻫﺎ ﺭﺍ ﺍﺯ ﺧﺮﻭﺟﻲ ﺩﺭﻳﺎﻓﺖ ﻣﻲﻛﻨﺪ ﻭ ﺁﻧﻬﺎ ﺭﺍ ﭘﺮﺩﺍﺯﺵ ﻭ ﻓﺸﺮﺩﻩ ﻣﻲﮐﻨـﺪ‪ ،‬ﺑـﻪ ﺻـﻮﺭﺗﯽ ﮐـﻪ ﺑـﺮﺍﻱ‬ ‫ﻛﺎﺭﺑﺮ ﻗﺎﺑﻞ ﺩﺭﻙ ﺑﺎﺷﺪ‪.‬‬ ‫ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ﻃﺮﺡ ﺩﺭ ﻣﺮﻭﺭ ﺯﻣﺎﻥ ﺗﻐﻴﻴﺮ ﻣﻲﻛﻨﺪ‪ ،‬ﻣﻌﻤﻮ ﹰﻻ ﭼﻨﺪ ﻫﺰﺍﺭ ﻛﺎﻣﭙﻴﻮﺗﺮ ﺑﻄﻮﺭ ﻫﻤﺰﻣﺎﻥ ﻭﻇﻴﻔﻪ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺭﺍ‬ ‫ﺑﺮﻋﻬﺪﻩ ﺩﺍﺭﻧﺪ ﻭ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﺑﺮﺍﻱ ﻫﻔﺘﻪﻫﺎ ﺭﻭﻱ ﺁﻧﻬﺎ ﺍﺟﺮﺍ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺭﻭﺵ ﻣﻌﻤﻮﻝ ﺩﻳﮕﺮ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﺩﺭ ﺻﻨﻌﺖ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺷﺒﻴﻪﺳـﺎﺯﻫﺎﻱ ﺷـﺒﻪﺗﺼـﺎﺩﻓﻲ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺍﻳـﻦ ﺭﻭﺵ‬ ‫ﻣﻌﻤﻮ ﹰﻻ ﺑﺮﺍﻱ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﺩﺭ ﺳﻄﺢ ﺗﺮﺍﺷﻪ ﻳﺎ ﻣﺎﺟﻮﻟﻬﺎﻱ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺑـﻪ ﻛـﺎﺭ ﻣـﻲﺭﻭﺩ‪ .‬ﺩﺭ ﺍﻳـﻦ ﺭﻭﺵ‬ ‫‪۲۳‬‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﻪ ﻭﺳﻴﻠﻪﻱ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺘﻲ ﻛﻪ ﺑﻪ ﺻﻮﺭﺕ ﺗﺼـﺎﺩﻓﻲ ﻭﻟـﻲ ﺑـﺎ ﻣﺤـﺪﻭﺩﻳﺘﻬﺎﻱ ﻣﺸـﺨﺺ ﻃﺮﺍﺣـﻲ‬ ‫ﺷﺪﻩﺍﻧﺪ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﻳﻚ ﻣﺤﺪﻭﺩﻳﺖ ﻣﻲﺗﻮﺍﻧﺪ ﺑﮕﻮﻳﺪ ﻛﻪ ﺳﻴﮕﻨﺎﻝ ‪ reset‬ﺩﺭ ﻣﺪﺍﺭ ﻣﺜﺎﻝ ‪ ۲-۲‬ﻓﻘﻂ‬ ‫ﺑﺎﻳﺪ ﺩﺭ ﻳﻚ ﺩﺭﺻﺪ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﻓﻌﺎﻝ ﺷﻮﺩ‪ .‬ﻭﻟﻲ ﺑﺮﺩﺍﺭﻫﺎ ﺑﻪ ﺻﻮﺭﺕ ﺗﺼﺎﺩﻓﻲ ﺗﻮﻟﻴـﺪ ﻣـﯽﺷـﻮﻧﺪ‪ .‬ﻣﺰﻳـﺖ‬ ‫ﺍﺻﻠﻲ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺷﺒﻪ ﺗﺼﺎﺩﻓﻲ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﻓﺸﺎﺭ ﺭﻭﻱ ﺗﻴﻢ ﻃﺮﺍﺡ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﻛﺎﻫﺶ ﻣﻲﻳﺎﺑﺪ‪ .‬ﺑﺎ ﻭﺟﻮﺩ‬ ‫ﺍﻳﻦ ﺑﻪ ﻋﻠﺖ ﻧﺒﻮﺩﻥ ﮐﻨﺘﺮﻝ ﻫﻮﺷﻤﻨﺪ ﺭﻭﯼ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ ﻧﻤﯽﺗﻮﺍﻥ ﺑﺪﻭﻥ ﺩﺍﺷﺘﻦ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ ﺍﺿﺎﻓﯽ ﺑـﻪ‬ ‫ﭘﻮﺷﺶ ﻣﻨﺎﺳﺒﯽ ﺍﺯ ﺗﺴﺖ ﮐﻞ ﺳﻴﺴﺘﻢ ﺭﺳﻴﺪ‪.‬‬ ‫ﻧﻮﻉ ﺩﻳﮕﺮ ﺷﺒﻴﻪﺳﺎﺯﻫﺎ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯﻫﺎﯼ ﺷﺒﻪﺗﺼﺎﺩﻓﯽ ﻫﺴﺘﻨﺪ ﮐﻪ ﻣﻌﻤﻮﻻ ﺑـﺮ ﺭﻭﯼ ﺍﻣﻮﻻﺗﻮﺭﻫـﺎ ﺍﺟـﺮﺍ ﻣـﻲﺷـﻮﻧﺪ‪.‬‬ ‫ﺍﻣﻮﻻﺗﻮﺭﻫﺎ ﺷﺒﻴﻪﺳﺎﺯﻫﺎﯼ ﺳﺨﺖ ﺍﻓﺰﺍﺭﯼ ﻫﺴﺘﻨﺪ ﮐﻪ ﺭﻭﯼ ‪ FPGA‬ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺷﺪﻩﺍﻧﺪ‪.‬‬ ‫ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻨﻜﻪ ﺍﻣﻮﻻﺗﻮﺭﻫﺎ ﺩﻭ ﻳﺎ ﭼﻨﺪ ﺩﺭﺟﻪ ﺳﺮﻳﻌﺘﺮ ﺍﺯ ﺷﺒﻴﻪ ﺳﺎﺯﻫﺎﻱ ﻧﺮﻡ ﺍﻓﺰﺍﺭﻱ ﻫﺴﺘﻨﺪ‪ ،‬ﻭﻟﯽ ﺍﺟﺮﺍ ﻭ ﭘﻴﺎﺩﻩ‪-‬‬ ‫ﺳﺎﺯﻱ ﺁﻧﻬﺎ ﻫﺰﻳﻨﻪﻱ ﺑﺴﻴﺎﺭ ﺑﺎﻻﻳﻲ ﺩﺍﺭﺩ‪ ،‬ﮐﻪ ﺩﻟﻴﻞ ﺁﻥ ﻗﻴﻤﺖ ﺑﺎﻻﻱ ﺍﻳﻦ ﺳﺨﺖﺍﻓﺰﺍﺭﻫﺎ ﻭ ﻫﺰﻳﻨﻪﻱ ﭘﻴﻜﺮﺑﻨﺪﻱ ﺁﻧﻬﺎ‬ ‫ﺑﺮﺍﻱ ﻳﻚ ﻃﺮﺍﺣﻲ ﺧﺎﺹ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻧﻴﺎﺯﻣﻨﺪ ﭼﻨﺪ ﻫﻔﺘﻪ ﻛﺎﺭ ﻣﺪﺍﻭ ِﻡ ﺗﻴﻢ ﻃﺮﺍﺣﻲ ﺍﺳﺖ‪ .‬ﺑـﻪ ﻫﻤـﻴﻦ ﺩﻟﻴـﻞ ﺍﻳـﻦ‬ ‫ﻧﻮﻉ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﻓﻘﻂ ﺩﺭ ﻣﺪﺍﺭﻫﺎﻱ ﻣﺠﺘﻤﻊ ﺑﺎ ﻓﺮﻭﺵ ﺑﺎﻻ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺣﺘﻲ ﺍﮔﺮ ﺗﻴﻢ ﻃﺮﺍﺡ ﺗﻼﺵ ﺯﻳﺎﺩﻱ ﺑﺮﺍﻱ ﻃﺮﺍﺣﻲ ﺑﺮﺩﺍﺭﻫﺎﻱ ﺗﺴﺖ ﺍﻧﺠﺎﻡ ﺩﻫﺪ ﺗﺎ ﺑﻴﺸـﺘﺮﻳﻦ ﭘﻮﺷـﺶ ﺣﺎﻟـﺖ ﺭﺍ‬ ‫ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﺗﻨﻬﺎ ﻣﻲﺗﻮﺍﻧﺪ ﻗﺴﻤﺖ ﻛﻮﭼﻜﻲ ﺍﺯ ﻛﻞ ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﺳﻴﺴـﺘﻢ ﺭﺍ ﺑﭙﻮﺷـﺎﻧﺪ ﻭ ﺣﺘـﻲ ﺩﺭ‬ ‫ﺑﻌﻀﻲ ﻣﻮﺍﺭﺩ ﺧﻄﺎﻫﺎﻱ ﻣﻮﺟﻮﺩ ﺩﺭ ﻃﺮﺍﺣﻲ ﺭﺍ ﺗﺸﺨﻴﺺ ﻧﺪﻫﺪ‪.‬‬ ‫‪ -۶-۲‬ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺻﻮﺭﻱ‬ ‫ﺩﺭ ﻣﻘﺎﺑﻞ ﺍﻋﺘﺒﺎﺭﺳﻨﺠﻲ ﻋﻤﻠﻜﺮﺩ‪ ،‬ﻣﺘﺪﻫﺎﻱ ﺩﻭﺳﺘﻲﻳﺎﺑﻲ ﺻﻮﺭﻱ ﻭﺟﻮﺩ ﺩﺍﺭﻧﺪ‪ .‬ﺍﻳﻦ ﺭﻭﺷـﻬﺎ ﻣـﻲﺗﻮﺍﻧﻨـﺪ ﭘﻮﺷـﺶ‬ ‫ﺣﺎﻟﺖ ﺑﺎﻻﻳﻲ ﺑﺪﻫﻨﺪ ﻭ ﻛﻴﻔﻴﺖ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺭﺍ ﺑﺎﻻ ﺑﺒﺮﻧﺪ‪ .‬ﺩﺭﺳـﺘﯽﻳـﺎﺑﯽ ﺻـﻮﺭﯼ ﺑـﺎ ﻗﻮﺍﻋـﺪ ﺻـﻮﺭﯼ ﻭ ﺍﺛﺒـﺎﺕ‬ ‫ﻣﺴﺘﺪﻝ ﺳﻌﯽ ﺩﺭ ﺑﺪﺳﺖﺁﻭﺭﺩﻥ ﻳﮏ ﺧﺎﺻﻴﺖ ﮐﻠـﯽ ﻣﺴـﺘﻘﻞ ﺍﺯ ﻭﺭﻭﺩﯼ ﺑـﺮﺍﯼ ﻃـﺮﺡ ﺩﺍﺭﺩ ﮐـﻪ ﺩﺭ ﺍﺯﺍﯼ ﺗﻤـﺎﻡ‬ ‫‪۲۴‬‬ ‫ﺗﺮﮐﻴﺒﻬﺎﯼ ﻭﺭﻭﺩﯼ ﺑﺮﻗﺮﺍﺭ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺪﻳﻦ ﺭﻭﺵ ﺍﺣﺘﻤﺎﻝ ﺑﺮﺭﺳﯽ ﻧﺸﺪﻥ ﺑﻌﻀﯽ ﺣﺎﻟﺘﻬﺎﻱ ﺳﻴﺴﺘﻢ ﺍﺯ ﺑـﻴﻦ ﻣـﻲ‪-‬‬ ‫ﺭﻭﺩ‪ .‬ﺍﻳﻦ ﺭﻭﺵ ﺳﻌﻲ ﺩﺭ ﺗﮑﻤﻴﻞ ﺭﻭﺷﻬﺎﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﺩﺍﺭﺩ ﺯﻳﺮﺍ ﻣـﻲﺗﻮﺍﻧـﺪ ﺧﺼﻮﺻـﻴﺎﺕ ﺳﻴﺴـﺘﻢ ﺭﺍ ﺗﻌﻤـﻴﻢ‬ ‫ﺩﻫﺪ‪.‬‬ ‫ﺍﮐﺜﺮ ﻣﺘﺪﻫﺎﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺩﻭ ﺩﺳﺘﻪ ﮐﻠﯽ ﺗﻘﺴﻴﻢ ﮐـﺮﺩ‪ :‬ﻣﺒﺘﻨـﯽ ﺑـﺮ ﻣـﺪﻝ ﻭ ﺍﺛﺒـﺎﺕ ﺗﺌﻮﺭﻳـﮏ‪ .‬ﺩﺭ‬ ‫ﻣﺘﺪﻫﺎﯼ ﻣﺒﺘﻨﯽ ﺑﺮ ﻣﺪﻝ ﺑﺎ ﮐﻤﮏ ﺭﻭﺷﻬﺎﯼ ﻧﻤﺎﺩﻳﻦ ﻭ ‪ FSM‬ﻳﮏ ﺟﺴﺘﺠﻮ ﺩﺭ ﮐﻞ ﻓﻀﺎﯼ ﺟﻮﺍﺏ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺑﻬﺘﺮﻳﻦ ﻣﺘﺪ ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻟﮕﻮﺭﻳﺘﻢ ﭘﻴﻤﺎﻳﺶ ﻧﻤﺎﺩﻳﻦ ﺣﺎﻟﺘﻬﺎ‪ ١٩‬ﻣﻲﺑﺎﺷﺪ‪ ،‬ﮐﻪ ﺑﻪ ﮐﻤﮏ ﺍﻳﻦ ﺍﻟﮕـﻮﺭﻳﺘﻢ‬ ‫ﻣﻲﺗﻮﺍﻥ ﺗﻤﺎﻡ ﺣﺎﻟﺘﻬﺎﯼ ﻳﮏ ﺳﻴﺴﺘﻢ ﺑﺎ ﺣﺪﻭﺩ ﻫﺰﺍﺭ ‪ latch‬ﺭﺍ ﭘﻴﻤﺎﻳﺶ ﮐﺮﺩ‪ .‬ﻣﺒﻨﺎﯼ ﺍﻳﻦ ﺍﻟﮕﻮﺭﻳﺘﻢ ﺑﻴﺎﻥ ﺿﻤﻨﯽ ﻳـﺎ‬ ‫ﻏﻴﺮﺿﻤﻨﯽ ﺗﻤﺎﻡ ﺣﺎﻟﺘﻬﺎﻳﻲ ﺍﺳﺖ ﮐﻪ ﺗﺎ ﻫﺮ ﻣﺮﺣﻠﻪ ﺍﺯ ﭘﻴﻤﺎﻳﺶ ﻣﻼﻗﺎﺕ ﺷﺪﻩﺍﺳـﺖ‪ .‬ﺑـﺎ ﺗﻮﺟـﻪ ﺑـﻪ ﺭﺷـﺪ ﻧﻤـﺎﻳﻲ‬ ‫ﺣﺎﻟﺘﻬﺎ ﺑﺎ ﺍﻓﺰﺍﻳﺶ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ‪ ،‬ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺍﻳﻦ ﻧﺘﻴﺠﻪ ﺭﺳﻴﺪ ﮐـﻪ ﭘﻴﭽﻴـﺪﮔﯽ ﺍﻟﮕـﻮﺭﻳﺘﻢ ﺑـﺎ ﺍﻓـﺰﺍﻳﺶ ﻋﻨﺎﺻـﺮ‬ ‫ﺣﺎﻓﻈﻪ ﺑﻪ ﺻﻮﺭﺕ ﻧﻤﺎﻳﻲ ﺍﻓﺰﺍﻳﺶ ﻣﻲﻳﺎﺑﺪ‪ .‬ﺍﻳـﻦ ﻣﺸـﮑﻞ ﺍﻧﻔﺠـﺎﺭ ﺣﺎﻟﺘﻬـﺎ‪ ٢٠‬ﻧﺎﻣﻴـﺪﻩ ﻣـﻲﺷـﻮﺩ ﻭ ﺩﻟﻴـﻞ ﺍﺻـﻠﻲ‬ ‫ﻣﺤﺪﻭﺩﻳﺖ ﮐﺎﺭﺍﻳﻲ ﺍﻳﻦﮔﻮﻧﻪ ﺍﻟﮕﻮﺭﻳﺘﻤﻬﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺭﻭﺵ ﺩﻳﮕﺮﯼ ﮐﻪ ﺩﺭ ﺍﻳﻦ ﺩﺳﺘﻪ ﻗﺮﺍﺭ ﻣﻲﮔﻴـﺮﺩ ﺷـﺒﻴﻪﺳـﺎﺯﯼ‬ ‫ﻧﻤﺎﺩﻳﻦ‪ ٢١‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ ﻭﺭﻭﺩﻱ ﺑﻪ ﺻﻮﺭﺕ ﻧﻤﺎﺩﻳﻦ ﺑﻪ ﺳﻴﺴﺘﻢ ﻭﺍﺭﺩ ﻣـﻲﺷـﻮﺩ ﻭ ﺗـﺎ‬ ‫ﺧﺮﻭﺟﯽ ﻣﻨﺘﺸﺮ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺍﻳﻦ ﺭﻭﺵ ﺩﺭ ﺩﺭﺳﺘﻲﻳﺎﺑﯽ ﻣﺪﺍﺭﻫﺎﻳﯽ ﺑﺎ ﺗﻌﺪﺍﺩ ﺯﻳﺎﺩ ﻭﺭﻭﺩﯼ ﮐﺎﺭﺁﻳﻲ ﺩﺍﺭﺩ‪ ،‬ﮐﻪ ﺗﻌـﺪﺍﺩ‬ ‫ﺯﻳﺎﺩﯼ ﺣﺎﻟﺖ ﺑﺎ ﻳﮏ ﭘﻴﻤﺎﻳﺶ ﻧﻤﺎﺩﻳﻦ ﻣﺪﺍﺭ ﻣﻼﻗﺎﺕ ﻣﻲﺷﻮﻧﺪ‪ .‬ﻣﺸﮑﻞ ﺍﻳﻦ ﻣﺘﺪ ﻧﻴﺰ ﺍﻧﻔﺠﺎﺭ ﺣﺎﻟﺘﻬﺎ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺭﻭﺷﻬﺎﯼ ﻧﻤﺎﺩﻳﻦ ﻣﺒﻨﺎﯼ ﺭﻭﺵ ﺩﻳﮕﺮﻱ ﺍﺯ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻳﻌﻨﯽ ﻭﺍﺭﺳﯽ ﻫﻢﺍﺭﺯﯼ‪ ،٢٢‬ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺳﻌﯽ‬ ‫ﻣﻲﺷﻮﺩ ﮐﻪ ﺛﺎﺑﺖ ﮐﻨﻴﻢ ﺩﻭ ﻣﺪﻝ ﺷﺒﮑﻪﺍﯼ ﮐﺎﺭﮐﺮﺩ ﻳﮑﺴﺎﻧﯽ ﺩﺍﺭﻧﺪ‪.‬ﺩﺭ ﭼﻨﺪ ﺳﺎﻝ ﮔﺬﺷﺘﻪ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺭﻭﺵ‬ ‫ﺭﺍﻩﺣﻠﻬﺎﻳﻲ ﺑﺮﺍﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻣﺪﺍﺭﻫﺎ ﺩﺭ ﻣﻘﻴﺎﺱ ﺻﻨﻌﺘﯽ ﺑﻪﺩﺳﺖ ﺁﻣﺪﻩﺍﺳﺖ ﮐﻪ ﺑﺎ ﺗﻮﺟـﻪ ﺑـﻪ ﺭﻭﺵ ﮐـﺎﺭﯼ ﺁﻥ‬ ‫ﺩﻳﮕﺮ ﻣﺸﮑﻞ ﺍﻧﻔﺠﺎﺭ ﺣﺎﻟﺘﻬﺎ ﺭﺍ ﻧﺪﺍﺭﺩ‪ .‬ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻨﮑﻪ ﺭﻭﺵ ﻭﺍﺭﺳﯽ ﻫﻢﺍﺭﺯﯼ ﻣﺸﮑﻼﺕ ﺭﻭﺷـﻬﺎﯼ ﻧﻤـﺎﺩﻳﻦ ﺭﺍ‬ ‫‪Symbolic State Traversal Algorithm 19‬‬ ‫‪State Explosion 20‬‬ ‫‪Symbolic Simulation 21‬‬ ‫‪equivalency checking 22‬‬ ‫‪۲۵‬‬ ‫ﻧﺪﺍﺭﻧﺪ‪ ،‬ﻭﻟﻲ ﺍﻣﻴﺪ ﺍﺻﻠﯽ ﺻﻨﻌﺖ ﺑﺮﺍﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺻﻮﺭﯼ ﺭﻭﺷﻬﺎﯼ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺧﺎﻧﻮﺍﺩﻩ ﺩﻳﮕﺮ‪ -‬ﺭﻭﺷﻬﺎﯼ ﺍﺛﺒﺎﺕ ﺗﺌﻮﺭﻳﮏ‪ -‬ﺑﺮ ﻣﺒﻨﺎﯼ ﺭﻭﺷﻬﺎﯼ ﺗﺠﺮﻳﺪﯼ ﻭ ﺳﻠﺴﻠﻪﻣﺮﺍﺗﺒﻲ ﺩﺭﺳﺘﯽ ﻳﮏ ﺳﻴﺴـﺘﻢ‬ ‫ﺭﺍ ﺍﺛﺒﺎﺕ ﻣﻲﮐﻨﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺍﺯ ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﯼ ﺍﺛﺒﺎﺕﮔﺮ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﮔﻮﻧﻪ ﺭﻭﺷﻬﺎ ﻣﺤﺪﻭﺩﻳﺘﯽ ﺑـﺮﺍﯼ‬ ‫ﭘﻴﭽﻴﺪﮔﯽ ﻣﺪﺍﺭ ﺗﺤﺖ ﺑﺮﺭﺳﯽ ﻧﺪﺍﺭﺩ‪ ،‬ﻟﻴﮑﻦ ﻧﺮﻡﺍﻓﺰﺍﺭﻫﺎﯼ ﺍﻣﺮﻭﺯﻱ ﺑﻪ ﮐﻤﮏ ﺍﻧﺴﺎﻥ ﻧﻴﺎﺯﻣﻨـﺪ ﺍﺳـﺖ ﻭ ﺩﺭ ﻧﺘﻴﺠـﻪ‬ ‫ﺍﺳﺘﻔﺎﺩﻩﻱ ﺍﻳﻦ ﺭﻭﺵ ﺩﺭ ﺻﻨﻌﺖ ﺍﻣﮑﺎﻥﭘﺬﻳﺮ ﻧﻤﯽﺑﺎﺷﺪ‪.‬‬ ‫‪ -۱-۶-۲‬ﭘﻴﻤﺎﻳﺶ ﻧﻤﺎﺩﻳﻦ ﺣﺎﻟﺘﻬﺎ‬ ‫ﻳﻜﻲ ﺍﺯ ﺭﻭﺷﻬﺎﻳﻲ ﻛﻪ ﺩﺭ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺻﻮﺭﻱ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ ﭘﻴﻤﺎﻳﺶ ﻧﻤﺎﺩﻳﻦ ﺣﺎﻟﺘﻬﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ‬ ‫ﺳﻌﯽ ﻣﻲﺷﻮﺩ‪ ،‬ﻳﻚ ﺧﺼﻮﺻﻴﺖ ﺍﺯ ﻣﺪﺍﺭ ﺍﻧﺘﺨﺎﺏ ﺷﻮﺩ‪ ،‬ﺳـﭙﺲ ﺍﺛﺒـﺎﺕ ﺷـﻮﺩ ﮐـﻪ ﺁﻥ ﺧﺼﻮﺻـﻴﺖ ﺩﺭ ﺗﻤـﺎﻣﻲ‬ ‫ﺣﺎﻟﺘﻬﺎﻳﻲ ﻛﻪ ﻣﺪﺍﺭ ﺍﺯ ﺣﺎﻟﺖ ﺍﻭﻟﻴﻪ ﺑﻪ ﺁﻧﻬﺎ ﻣﻲﺗﻮﺍﻧﺪ ﺑﺮﺳﺪ‪ ،‬ﺑﺮﻗـﺮﺍﺭ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺑـﺮﺍﻱ ﻣﺜـﺎﻝ‪ ،‬ﺍﻳـﻦ ﺧﺼﻮﺻـﻴﺖ‬ ‫ﻣﻲﺗﻮﺍﻧﺪ ﻣﺸﺨﺺ ﻛﻨﺪ ﻛﻪ ﺍﮔﺮ ﺳﻴﺴﺘﻢ ﺩﺭﺳﺖ ﺭﺍﻩ ﺍﻧﺪﺍﺯﻱ ﺷﻮﺩ‪ ،‬ﻫﻴﭽﮕﺎﻩ ﻗﻔﻞ ﻧﻤﻲﻛﻨﺪ ﻭ ﻳـﺎ ﺩﺭ ﺧـﻂ ﻟﻮﻟـﻪﻱ‬ ‫ﻳﻚ ﺭﻳﺰﭘﺮﺩﺍﺯﻧﺪﻩ‪ ،‬ﻳﻚ ﺧﺼﻮﺻﻴﺖ ﻣﻲﺗﻮﺍﻧﺪ ﺍﻳﻦ ﺑﺎﺷﺪ ﻛﻪ ﻫﺮ ﺩﺳﺘﻮﺭ ﺑﻌﺪ ﺍﺯ ﻳﻚ ﺗﻌﺪﺍﺩ ﻣﺤﺪﻭﺩ ﭘﺎﻟﺲ ﺳﺎﻋﺖ‪،‬‬ ‫ﺖ ﻛﻠﻲ ﺍﺳـﺖ ﻛـﻪ ﺭﻓﺘـﺎﺭ ﻛﻠـﻲ ﺗﻤـﺎﻡ‬ ‫ﻑ ﺣﺎﻟ ِ‬ ‫ﺗﻤﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﺍﺛﺒﺎﺕ ﺧﺼﻮﺻﻴﺎﺗﻲ ﻣﺎﻧﻨﺪ ﺍﻳﻦ ﺩﻭ ﻧﻴﺎﺯﻣﻨﺪ ﻳﻚ ﮔﺮﺍ ِ‬ ‫ﺍﺟﺰﺍﻱ ﻣﻮﺟﻮﺩ ﺩﺭ ﺳﻴﺴﺘﻢ ﺭﺍ ﺑﻴـﺎﻥ ﻛﻨـﺪ‪ .‬ﭘـﺲ ﺍﺯ ﺁﻥ‪ ،‬ﻫـﺮ ﺣﺎﻟـﺖ ﺍﺯ ﮔـﺮﺍﻑ ﺑﺮﺭﺳـﻲ ﻣـﻲﺷـﻮﺩ ﻛـﻪ ﺁﻳـﺎ ﺁﻥ‬ ‫ﺧﺼﻮﺻﻴﺖ ﺭﺍ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷﺪ ﻳﺎ ﻧﻪ‪ .‬ﺑﺴﻴﺎﺭﻱ ﺍﺯ ﻣﺸﻜﻼﺕ ﻣﻮﺟﻮﺩ ﺩﺭ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺻﻮﺭﻱ ﺑـﻪ ﺩﻟﻴـﻞ ﻣﺸـﻜﻼﺕ‬ ‫ﻣﻮﺟﻮﺩ ﺩﺭ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻥ ﺣﺎﻟﺘﻬﺎﻱ ﻗﺎﺑﻞ ﺩﺳﺘﺮﺳﻲ ‪ FSM‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻳﻚ ﺣﺎﻟﺖ ﻗﺎﺑﻞ ﺩﺳﺘﺮﺳﻲ‪ ،‬ﺣـﺎﻟﺘﻲ ﺍﺳـﺖ‬ ‫ﻛﻪ ﺑﺎ ﻳﻚ ﺭﺷﺘﻪ ﺍﺯ ﻭﺭﻭﺩﻳﻬﺎ‪ ،‬ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺁﻥ ﺭﺳﻴﺪ‪ .‬ﺍﻳﻦ ﮔﻮﻧﻪ ﻣﺤﺎﺳﺒﻪﻫﺎ ﻣﻌﻤﻮﻻ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺟﺴﺘﺠﻮﯼ ﻋﻤﻖ‬ ‫ﺍﻭﻝ ﻧﻤﺎﺩﻳﻦ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ ﺗﺎ ﺗﻤﺎﻡ ﺣﺎﻻﺕ ﻗﺎﺑﻞ ﺩﺳﺘﺮﺳﻲ ﭘﻴﺪﺍ ﺷﻮﺩ‬ ‫ﺩﺭ ‪ FSM‬ﻣﺤﺎﺳﺒﻪ ﺣﺎﻟﺘﻬﺎﻱ ﻗﺎﺑﻞ ﺩﺳﺘﺮﺳﻲ ﺑﺮﺍﺳﺎﺱ ﭘﻴﻤﺎﻳﺶ ﺿﻤﻨﻲ ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﻣﻲﺑﺎﺷﺪ‪ .‬ﮔـﺎﻡ ﺍﺻـﻠﻲ ﺩﺭ‬ ‫‪۲۶‬‬ ‫ﭘﻴﻤﺎﻳﺶ ﻣﺤﺎﺳﺒﻪﻱ ﺗﺼﻮﻳﺮ‪ ٢٣‬ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﺣﺎﻟﺖ ﺩﺭ ﻳﻚ ﺩﻳﺎﮔﺮﺍﻡ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﺤﺎﺳﺒﻪ ﺗﺼـﻮﻳﺮ ﻳﻌﻨـﻲ ﻣﺤﺎﺳـﺒﻪ‬ ‫ﺗﻤﺎﻡ ﺣﺎﻻﺗﻲ ﻛﻪ ﺍﺯ ﺣﺎﻟﺖ ﻓﻌﻠﻲ ﺩﺭ ﻳﻚ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺁﻧﻬﺎ ﺭﺳﻴﺪ‪.‬‬ ‫ﻣﺜﺎﻝ ‪ :۵-۲‬ﺩﺭ ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﻟﺖ ﺷـﻜﻞ ‪ ۶-۲‬ﺗﺼـﻮﻳ ِﺮ ﻣﺠﻤﻮﻋـﻪ ﺣﺎﻟـﺖ }‪ {000-1‬ﺷـﺎﻣﻞ ﻣﺠﻤﻮﻋـﻪ ﺣﺎﻟﺘﻬـﺎﻱ‬ ‫}‪ {000-1, 001-1‬ﻣﻲﺑﺎﺷﺪ ﺯﻳﺮﺍ ﻫﺮﻛﺪﺍﻡ ﺍﺯ ﺁﻧﻬﺎ ﺑﺎ ﻳﻚ ﻳﺎﻝ ﺑـﻪ ﺣﺎﻟـﺖ ‪ 000-1‬ﻣﺘﺼـﻞ ﺷـﺪﻩﺍﻧـﺪ ﻳـﺎ ﺗﺼـﻮﻳﺮ‬ ‫ﻣﺠﻤﻮﻋﻪ ﺣﺎﻟﺖ }‪ {110-1,111-0‬ﻣﺠﻤﻮﻋﻪ ﺣﺎﻟﺖ }‪ {000-1,110-1,111-0,110-0‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺗﺤﻠﻴﻞ ﺩﺳﺘﺮﺳﻲﭘﺬﻳﺮﻱ ﺷﺎﻣﻞ ﻣﺸﺨﺺ ﻛﺮﺩﻥ ﻣﺠﻤﻮﻋﻪﺍﻱ ﺍﺯ ﺣﺎﻟﺘﻬﺎﺳﺖ ﻛﻪ ﻣﻲﺗﻮﺍﻥ ﺍﺯ ﺣﺎﻟﺖ ﺍﻭﻟﻴﻪ ﺑﺎ ﺗﻌـﺪﺍﺩ‬ ‫ﻧﺎﻣﻌﻴﻨﻲ ﮔﺬﺍﺭ‪ ٢٤‬ﺑﻪ ﺁﻥ ﺭﺳﻴﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﻣﺤﺎﺳﺒﻪﻱ ﺗﺼﻮﻳﺮ‪ ،‬ﮔﺎﻡ ﺍﺻﻠﻲ ﺩﺭ ﺗﺤﻠﻴﻞ ﺩﺳﺘﺮﺳﻲﭘـﺬﻳﺮﻱ ﻣـﻲﺑﺎﺷـﺪ‪.‬‬ ‫ﺍﻳﻦ ﺗﺤﻠﻴﻞ ﺑﺎﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﭘﻴﻤﺎﻳﺶ ﻋﻤﻖ ﺍﻭﻝ ﻧﻤﺎﺩﻳﻦ ﺍﻧﺠﺎﻡ ﻣﻲﺷـﻮﺩ‪ .‬ﺍﻳـﻦ ﺍﻟﮕـﻮﺭﻳﺘﻢ ﺩﺭ ﻫـﺮ ﻣﺮﺣﻠـﻪﻱ ﺍﺟـﺮﺍ‪،‬‬ ‫ﺗﺼﻮﻳﺮ ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﺍﺯ ﺣﺎﻟﺘﻬﺎ )‪ (From‬ﺭﺍ ﺑﺪﺳﺖ ﻣﻲﺁﻭﺭﺩ ﻭ ﺁﻥ ﺭﺍ ﺩﺭ ﻣﺠﻤﻮﻋﻪ ‪ To‬ﻣـﻲﺭﻳـﺰﺩ‪ .‬ﻣﺠﻤﻮﻋـﻪﻱ‬ ‫‪ To‬ﻧﻤﺎﻳﻨﺪﻩﻱ ﺗﻤﺎﻡ ﺣﺎﻻﺗﻲ ﺍﺳﺖ ﻛﻪ ﺑﺎ ﻳﻚ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺍﺯ ﺣﺎﻟﺘﻬﺎﻱ ﻣﻮﺟـﻮﺩ ﺩﺭ ‪ From‬ﻣـﻲﺗـﻮﺍﻥ ﺑـﻪ ﺁﻧﻬـﺎ‬ ‫ﺭﺳﻴﺪ‪ .‬ﺩﺭ ﮔﺎﻡ ﺑﻌﺪﯼ‪ ،‬ﺍﻟﮕﻮﺭﻳﺘﻢ ﺗﻤﺎﻡ ﺣﺎﻻﺗﻲ ﻛﻪ ﺩﺭ ‪ To‬ﻭﺟﻮﺩ ﺩﺍﺭﺩ‪ ،‬ﻭﻟﻲ ﻫﻴﭽﮕﺎﻩ ﺗﺼﻮﻳﺮ ﺁﻧﻬﺎ ﻣﺤﺎﺳﺒﻪ ﻧﺸﺪﻩ‬ ‫ﺍﺳﺖ ﺭﺍ ﺩﺭ ﻣﺠﻤﻮﻋﻪﻱ ‪ From‬ﻣﻲﺭﻳﺰﺩ‪ .‬ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ﺗﻌـﺪﺍﺩ ﺣـﺎﻻﺕ ﻣﻮﺟـﻮﺩ ﺩﺭ ‪ FSM‬ﻣﺤـﺪﻭﺩ ﺍﺳـﺖ‪ ،‬ﺍﻳـﻦ‬ ‫ﺗﻨﺎﻭﺏ ﺑﻪ ﺟﺎﻳﻲ ﺧﻮﺍﻫﺪﺭﺳﻴﺪ ﻛﻪ ﻫﻴﭻ ﺣﺎﻟﺖ ﺑﺮﺭﺳﻲﻧﺸﺪﻩ ﺟﺪﻳﺪﻱ ﺍﺿﺎﻓﻪ ﻧﺨﻮﺍﻫﺪ ﺷﺪ‪ ،‬ﺑﻪ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﻧﻘﻄـﻪ‬ ‫ﺛﺒﺎﺕ ﻣﻲﮔﻮﻳﻴﻢ‪ .‬ﻣﺠﻤﻮﻋﻪ ﺣﺎﻻﺕ ‪ Reached‬ﻛﻪ ﺍﺟﺘﻤﺎﻉ ﺗﻤﺎﻡ ﻣﺠﻤﻮﻋﻪﻫﺎﻱ ‪ To‬ﻣﻲﺑﺎﺷﺪ ﺷﺎﻣﻞ ﺗﻤﺎﻡ ﺣﺎﻟﺘﻬﺎﻱ‬ ‫ﻗﺎﺑﻞ ﺩﺳﺘﺮﺳﻲ ﺍﺯ ﺣﺎﻟﺖ ﺍﻭﻟﻴﻪ ‪ S o‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺣﺎﻟﺖ ﻛﻠﻲ ﺗﻌﺪﺍﺩ ﺗﻨﺎﻭﺑﻬﺎﻳﻲ ﻛﻪ ﺑﺮﺍﻱ ﺭﺳﻴﺪﻥ ﺑﻪ ﻧﻘﻄـﻪ ﺛﺒـﺎﺕ‬ ‫ﻻﺯﻡ ﺍﺳﺖ ﺑﺎ ﺗﻌﺪﺍﺩ ﺣﺎﻟﺘﻬﺎﻱ ‪ FSM‬ﺭﺍﺑﻄﻪ ﺧﻄﻲ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺑﺎ ﺗﻌﺪﺍﺩ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﺭﺍﺑﻄﻪ ﻧﻤﺎﻳﻲ ﺩﺍﺭﺩ‪.‬‬ ‫ﭘﻴﻤﺎﻳﺶ ﻧﻤﺎﺩﻳﻦ‪ ،‬ﻫﺴﺘﻪﻱ ﺭﻭﺵ ﻭﺍﺭﺭﺳﯽ ﻫﻢﺍﺭﺯﻱ ﻣﺪﻝ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﺪﻩﻱ ﺍﺻﻠﻲ ﺍﻳﻦ ﺭﻭﺵ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ‬ ‫‪ BDD‬ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﺗﻤﺎﻡ ﺗﻮﺍﺑﻊ ﻣﻮﺟﻮﺩ ﺩﺭ ﺳﻴﺴﺘﻢ ﻭ ﺑﺮﺭﺳﻲ ﺗﻤﺎﻡ ﺣﺎﻟﺘﻬﺎﻳﻲ ﻛﻪ ﺳﻴﺴﺘﻢ ﺁﻧﻬﺎ ﺭﺍ ﭘﻴﻤﺎﻳﺶ ﻛﺮﺩﻩ‬ ‫‪Image 23‬‬ ‫‪Transition 24‬‬ ‫‪۲۷‬‬ ‫ﺍﺳﺖ‪ ،‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﺸﻜﻞ ﺍﺻﻠﻲ ﺍﻳﻦ ﺭﻭﺵ ﺭﺷﺪ ﻧﻤﺎﻳﻲ ‪ BDD‬ﺳﺎﺧﺘﻪ ﺷﺪﻩ ﺑﺮﺍﯼ ﺗﻮﺍﺑـﻊ ﺳﻴﺴـﺘﻢ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺩﺭ‬ ‫ﻧﺘﻴﺠﻪ ﻣﻨﺎﺑﻊ ﺳﻴﺴﺘﻢ ﺑﻪ ﺷﺪﺕ ﻣﺼﺮﻑ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﺍﻓﺰﺍﻳﺶ ﻣﺼﺮﻑ ﻣﻨﺎﺑﻊ ﺑﺎﻋﺚ ﻛﺎﻫﺶ ﺳﺮﻋﺖ ﺩﺭﺳﺘﻲﻳـﺎﺑﻲ‬ ‫ﻣﻲﮔﺮﺩﺩ‪ .‬ﺩﺭ ﻋﻤﻞ ﺭﺍﻩﺣﻞﻫﺎﻱ ﺯﻳﺎﺩﻱ ﺑﺮﺍﻱ ﻛﺎﻫﺶ ﺍﻧﺪﺍﺯﻩﻱ ‪ BDD‬ﺍﺭﺍﻳﻪ ﺷﺪﻩ ﺍﺳﺖ]‪.[۷ ،۶‬‬ ‫ﻳﻜﻲ ﺩﻳﮕﺮ ﺍﺯ ﻣﻌﺎﻳﺐ ﭘﻴﻤﺎﻳﺶ ﻧﻤﺎﺩﻳﻦ ﺣﺎﻟﺘﻬﺎ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﻧﻤﻲﺗﻮﺍﻥ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻧﺘﺎﻳﺞ ﺁﻥ ﺑـﻪ ﺭﻓـﻊ ﺍﺷـﻜﺎﻝ‬ ‫ﻃﺮﺡ ﭘﺮﺩﺍﺧﺖ؛ ﺯﻳﺮﺍ ﺩﺭ ﺻﻮﺭﺕ ﺑﺮﻭﺯ ﺧﻄﺎ ﺑﺎ ﻛﻤﻚ ﺍﻳﻦ ﺭﻭﺵ ﻧﻤﻲﺗﻮﺍﻥ ﺭﺷﺘﻪ ﻭﺭﻭﺩﻳﻬﺎﻳﻲ ﺭﺍ ﻛـﻪ ﺳﻴﺴـﺘﻢ ﺭﺍ‬ ‫ﺑﻪ ﺁﻥ ﺣﺎﻟﺖ ﺧﻄﺎﺩﺍﺭ ﻣﻲﺭﺳﺎﻧﻨﺪ‪ ،‬ﺑﺪﺳﺖ ﺁﻭﺭﺩ‪.‬‬ ‫‪ -۷-۲‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ‬ ‫ﺭﻭﺵ ﺩﻳﮕﺮ ﺑﺮﺍﻱ ﭘﻴﻤﺎﻳﺶ ﺣﺎﻟﺘﻬﺎﻱ ﻧﻤﺎﺩﻳﻦ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺍﺳﺖ‪ ،‬ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺨـﺶ ‪-۲‬‬ ‫‪ ۵‬ﮔﻔﺘﻪ ﺷﺪ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯ ﻣﻨﻄﻘﻲ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﮔﻴﺖ ﻣﺪﺍﺭ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﺭﺍ ﺑﺎ ﻣﻘﺎﺩﻳﺮ ﺑـﻮﻟﻲ ﺻـﻔﺮ ﻭ‬ ‫ﻳﻚ ﺍﻧﺠﺎﻡ ﻣﻲ ﺩﻫﺪ‪ .‬ﺗﻔﺎﻭﺕ ﺷﺒﻴﻪﺳﺎﺯ ﻧﻤﺎﺩﻳﻦ ﻭ ﺷﺒﻴﻪﺳﺎﺯ ﻣﻨﻄﻘـﻲ ﺩﺭ ﺍﻳـﻦ ﺍﺳـﺖ ﻛـﻪ ﺩﺭ ﺷـﺒﻴﻪﺳـﺎﺯ ﻧﻤـﺎﺩﻳﻦ‬ ‫ﺣﺎﺻﻞ ﻣﺪﺍﺭ ﺑﻪ ﺻﻮﺭﺕ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﻣﺤﺎﺳﺒﻪ ﻣﻲﺷﻮﺩ ﻧﻪ ﻣﻘﺎﺩﻳﺮ ﺛﺎﺑﺖ ﺑﻮﻟﻲ‪ .‬ﺩﺭ ﺷﻜﻞ ‪ ۸-۲‬ﮔﻴﺖ ‪ OR‬ﺑـﻪ‬ ‫ﺩﻭ ﺻﻮﺭﺕ ﻣﻨﻄﻘﻲ ﻭ ﻧﻤﺎﺩﻳﻦ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﺷﺪﻩ ﺍﺳﺖ‪.‬‬ ‫ﺷﮑﻞ ‪ -۸-۲‬ﻣﻘﺎﻳﺴﻪ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﻭ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻨﻄﻘﯽ‬ ‫ﺩﺭ ﺳﻤﺖ ﭼﭗ ‪-‬ﻗﺴﻤﺖ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻣﻨﻄﻘﻲ‪ -‬ﺩﻭ ﻣﻘﺪﺍﺭ ﺛﺎﺑـﺖ ﺑـﻮﻟﻲ ﺑـﻪ ﻋﻨـﻮﺍﻥ ﻭﺭﻭﺩﻱ ﮔﻴـﺖ ﺑـﻪ ﺁﻥ ﻭﺍﺭﺩ‬ ‫ﻣﻲﺷﻮﺩ ﻭ ﺣﺎﺻﻞ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﺑﻮﻟﻲ ﺧﺎﺭﺝ ﻣﻲﺷﻮﺩ‪ .‬ﻭﻟﻲ ﺩﺭ ﺳـﻤﺖ ﺭﺍﺳـﺖ‪-‬ﻗﺴـﻤﺖ ﺷـﺒﻴﻪ‬ ‫ﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ‪ -‬ﻭﺭﻭﺩﻱ ﺑﻪ ﺻﻮﺭﺕ ﺩﻭ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ‪ b, a‬ﻭﺍﺭﺩ ﮔﻴﺖ ﻣﻲﺷﻮﺩ ﻭ ﭘﺲ ﺍﺯ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺧﺮﻭﺟﻲ ﺑﻪ‬ ‫ﺻﻮﺭﺕ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ‪ a+b‬ﻣﺤﺎﺳﺒﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪۲۸‬‬ ‫ﺍﻳﻦ ﺭﻭﺵ ﺍﺯ ﺩﻭ ﺟﻬﺖ ﺑﺴﻴﺎﺭ ﻗﺪﺭﺗﻤﻨﺪ ﺍﺳﺖ‪ -۱ :‬ﺩﺭ ﺍﻧﺘﻬﺎﻱ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺧﺮﻭﺟﻲ ﻛﻠﻲ ﻣﺪﺍﺭ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ‬ ‫ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ‪ ،‬ﻛﻪ ﺁﻥ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﺎ ﺗﻮﺻﻴﻒ ﺻﻮﺭﻱ ﻣﺪﺍﺭ ﻣﻘﺎﻳﺴﻪ ﻭ ﻣﺪﺍﺭ ﺭﺍ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻧﻤـﻮﺩ‪.‬‬ ‫ﻫﺮ ﭼﻨﺪ ﺑﻪ ﻋﻠﺖ ﭘﻴﭽﻴﺪﮔﻲ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺍﻳﻦ ﻋﻤﻞ ﺗﻨﻬﺎ ﺩﺭ ﻣﻮﺍﺭﺩﻱ ﻛﻪ ﻃـﺮﺡ ﺑﺴـﻴﺎﺭ ﻛﻮﭼـﻚ ﻣـﻲﺑﺎﺷـﺪ‪،‬‬ ‫ﺍﻣﻜﺎﻥﭘﺬﻳﺮ ﺍﺳﺖ‪ -۲ .‬ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺗﻮﺍﻧﺪ ﻧﻤﺎﻳﺎﻧﮕﺮ ِﺍﻋﻤﺎﻝ ﻣﻮﺍﺯﻱ ﺗﻌﺪﺍﺩ ﺯﻳﺎﺩﻱ ﺑﺮﺩﺍﺭ ﺗﺴﺖ ﺑﻪ ﻣـﺪﺍﺭ‬ ‫ﺗﺤﺖ ﺁﺯﻣﻮﻥ ﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﯼ ﻣﺜﺎﻝ ﺩﺭ ﺷﮑﻞ‪ ۸-۲‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤـﺎﺩﻳﻦ ﺑـﻪ ﺻـﻮﺭﺕ ﺿـﻤﻨﯽ ﭼﻬـﺎﺭ ﺑـﺮﺩﺍﺭ ﺗﺴـﺖ‬ ‫}‪ {۱،۰} ،{۰،۱} ،{۰،۰‬ﻭ }‪ {۱،۱‬ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻫﻢﺯﻣﺎﻥ ﺍﻋﻤﺎﻝ ﻣﻲﮐﻨﺪ‪.‬‬ ‫ﺩﺭ ﻧﺘﻴﺠﻪ ﺍﻳﻦ ﺭﻭﺵ ﺑﻪ ﻣﺎ ﺍﺟﺎﺯﻩ ﻣﻲﺩﻫﺪ ﮐﻪ ﺩﺭ ﻳﮏ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺭﻓﺘﺎﺭ ﻃﺮﺡ ﺭﺍ ﺑﺮﺍﯼ ﻳﮏ ﺣﺎﻟﺖ ﺧـﺎﺹ ﺑـﻪ‬ ‫ﻃﻮﺭ ﻫﻢﺯﻣﺎﻥ ﺩﺭﺍﺯﺍﻱ ﻫﻤﻪﻱ ﻭﺭﻭﺩﻳﻬﺎﯼ ﻣﻤﮑﻦ ﭘﻴﺪﺍ ﮐﻨﻴﻢ‪ .‬ﺍﻳﻦ ﺧﺼﻮﺻﻴﺖ ﺷﺒﻴﻪﺳﺎﺯﻫﺎﻱ ﻧﻤﺎﺩﻳﻦ ﺑﺴﻴﺎﺭ ﻗﺎﺑـﻞ‬ ‫ﺗﻮﺟﻪ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺯﻳﺮﺍ ﺑﻪ ﺁﻥ ﻗﺎﺑﻠﻴﺖ ﺗﺮﻛﻴﺐ ﺑﺎ ﺷﺒﻴﻪ ﺳﺎﺯﻫﺎﻱ ﻣﻨﻄﻘﻲ ﻣﻮﺟﻮﺩ ﺩﺭ ﻧﺮﻡ ﺍﻓﺰﺍﺭﻫﺎﻱ ﺗﺠﺎﺭﻱ ﻣﻮﺟـﻮﺩ‬ ‫ﺭﺍ ﺩﺍﺩﻩﺍﺳﺖ‪.‬‬ ‫‪ -۱-۷-۲‬ﺍﻟﮕﻮﺭﻳﺘﻤﻬﺎﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ‬ ‫ﺍﻳﺪﻩ ﺍﺻﻠﻲ ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺭﻭﺷﻬﺎﻱ ﺭﻳﺎﺿﻲ ﺑﺮﺍﻱ ﺟﺎﻳﮕﺰﻳﻨﻲ ﻣﻘﺎﺩﻳﺮ ﺑﺎ ﻧﻤﺎﺩﻫﺎﻱ ﺑـﻮﻟﯽ‪ ،‬ﺩﺭ‬ ‫ﻭﺭﻭﺩﻱ ﻣﺪﺍﺭ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻳﻜﻲ ﺍﺯ ﺍﻭﻟﻴﻦ ﺍﻓﺮﺍﺩﻱ ﻛﻪ ﺩﺭ ﺍﻳﻦ ﺯﻣﻴﻨﻪ ﻓﻌﺎﻟﻴﺖ ﻛﺮﺩﻩ ﺍﺳﺖ ‪ [۱] king‬ﻣﻲﺑﺎﺷـﺪ ﻛـﻪ ﺍﺯ‬ ‫ﺍﻳﻦ ﺭﻭﺵ ﺑﺮﺍﻱ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻧﺮﻡ ﺍﻓﺰﺍﺭﻫﺎ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮐﺮﺩ‪ .‬ﺩﺭ ﺳﺎﻝ ‪ [۱] Bryant ،۱۹۸۷‬ﺭﻭﺷـﻲ ﺑـﺮﺍﻱ ﺷـﺒﻴﻪ‪-‬‬ ‫ﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﻣﺪﺍﺭﻫﺎﻱ ‪ CMOS‬ﺍﺭﺍﻳﻪ ﻛﺮﺩ ﻛﻪ ﺩﺭ ﺁﻥ ﺍﺯ ‪ BDD‬ﻭ ﻣﺘﺪﻫﺎﻱ ﺭﻳﺎﺿﻲ ﺑـﺮﺍﻱ ﻧﻤـﺎﻳﺶ ﻣﻘـﺪﺍﺭ‬ ‫ﻣﻮﺟﻮﺩ ﺩﺭ ﻫﺮ ﮔﺮﻩ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﺪ‪.‬‬ ‫ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﻳﻚ ﻣﺪﺍﺭ ﻫﻤﮕﺎﻡ ﺑﺎ ﺍﺟﺮﺍﻱ ﻣﺘﻨﺎﻭﺏ ﻳﻚ ﺷـﺒﻴﻪﺳـﺎﺯﻱ ﻧﻤـﺎﺩﻳﻦ ﭘﻴﻤـﺎﻳﺶ‬ ‫ﻲ ﺩﻳﺠﻴﺘﺎﻝ ﺍﻧﺠﺎﻡ ﻣـﻲﺷـﻮﺩ‪ .‬ﺩﺭ ﻫـﺮ ﻣﺮﺣﻠـﻪ‬ ‫ﺖ ﻃﺮﺍﺣ ِ‬ ‫ﺢ ﮔﻴ ِ‬ ‫ﻒ ﺳﻄ ِ‬ ‫ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺗﻮﺻﻴ ِ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﻫﺮ ﻭﺭﻭﺩﻱ ﻭ ﻭﺿﻌﻴﺖﻫﺎﻱ ﺳﻴﺴﺘﻢ ﺑﺎ ﻳﻚ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﻣﺸﺨﺺ ﻣﻲ ﺷـﻮﺩ‪ .‬ﺍﻳـﻦ ﻋﺒـﺎﺭﺕ ﺑـﻮﻟﻲ‬ ‫ﻣﻲﺗﻮﺍﻧﺪ ﻳﻚ ﻋﺒﺎﺭﺕ ﺳﺎﺩﻩ ﻳﺎ ﭘﻴﭽﻴﺪﻩ ﻭ ﻳﺎ ﻳﻚ ﻣﻘﺪﺍﺭ ﺑﻮﻟﻲ ﺛﺎﺑﺖ ﺑﺎﺷﺪ‪ .‬ﺷﺒﻴﻪﺳﺎﺯ ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﻫـﺮ ﺳـﻴﮕﻨﺎﻝ‬ ‫‪۲۹‬‬ ‫ﻣﻮﺟﻮﺩ ﺩﺭ ﻗﺴﻤﺖ ﺗﺮﻛﻴﺒﻲ ﺷﺒﻜﻪ ﺭﺍ ﺑﺎ ﻛﻤﻚ ﻣﺘﺪﻫﺎﻱ ﺭﻳﺎﺿﻲ ﻣﺤﺎﺳﺒﻪ ﻣﻲﻛﻨـﺪ‪ .‬ﺑـﻪ ﺁﺳـﺎﻧﻲ ﻣـﻲﺗـﻮﺍﻥ ﺭﻓﺘـﺎﺭ‬ ‫ﻣﻌﺎﺩﻝ ﺍﻳﻦ ﮔﻮﻧﻪ ﺷﺒﻴﻪﺳﺎﺯﻫﺎ ﺭﺍ ﺑﺎ ﺷﺒﻴﻪﺳﺎﺯﻫﺎﻱ ﻣﻨﻄﻘﻲ‪ ،‬ﻣﺸﺎﻫﺪﻩ ﻛﺮﺩ‪.‬‬ ‫ﺩﺭ ﮔﺎﻡ ﺻﻔﺮ‪ ،‬ﺣﺎﻟﺖ ﻓﻌﻠﯽ ﺳﻴﺴﺘﻢ ﻣﻘﺪﺍﺭ ﭘﻴﺶﻓـﺮﺽ ‪ S 0‬ﻗـﺮﺍﺭ ﺩﺍﺩﻩ ﻭ ﻭﺭﻭﺩﻳﻬـﺎﯼ ﺑﺨـﺶ ﺗﺮﮐﻴﺒـﯽ ﻣـﺪﺍﺭ ﺑـﻪ‬ ‫ﺻﻮﺭﺕ ﻳﮏ ﻣﺘﻐﻴﺮ ﺑﻮﻟﯽ } ‪ IN @ 0 = {i1@ 0 , i2 @ 0 ,..., ir @ 0‬ﻣﻘﺪﺍﺭﺩﻫﯽ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﻣﻘـﺎﺩﻳﺮ ﺩﺭ ﮔـﺎﻡ ﺑﻌـﺪﯼ ﺑـﻪ‬ ‫ﺳﻴﺴﺘﻢ ﺍﻋﻤﺎﻝ ﻣﻲﺷﻮﺩ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯ ﺑﺎ ﮐﻤﮏ ﺁﻧﻬﺎ ﻣﻘﺎﺩﻳﺮ ﮔﺮﻩﻫﺎﯼ ﺩﺍﺧﻠﯽ ﺑﺨﺶ ﺗﺮﮐﻴﺒﯽ ﻣﺪﺍﺭ‪ ،‬ﺧﺮﻭﺟﯽ ﻣـﺪﺍﺭ ﻭ‬ ‫ﺣﺎﻟﺖ ﺑﻌﺪﯼ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻳﮏ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺑﺪﺳﺖﻣﻲﺁﻭﺭﺩ‪ .‬ﺑﺮﺍﯼ ﺍﻳﻨﮑﺎﺭ ﻳﮏ ﻋﺒﺎﺭﺕ ﺑﻮﻟﯽ ﺑـﺮﺍﯼ ﺧﺮﻭﺟـﯽ‬ ‫ﻫﺮ ﮔﻴﺖ ﺑﺮﺍﺳﺎﺱ ﻋﻤﻠﮑﺮﺩ ﺁﻥ ﮔﻴﺖ ﻣﺤﺎﺳﺒﻪ ﻣﻲﺷﻮﺩ‪ .‬ﮔﻴﺘﻬﺎ ﺑﻪ ﺗﺮﺗﻴﺐ ﻓﺎﺻﻠﻪ ﺍﺯ ﻭﺭﻭﺩﯼ ﻣﻮﺭﺩ ﻣﺤﺎﺳﺒﻪ ﻗـﺮﺍﺭ‬ ‫ﻣﻲﮔﻴﺮﻧﺪ‪ .‬ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻭﺭﻭﺩﻳﻬﺎﯼ ﺟﺪﻳﺪ ﻭ ﺣﺎﻟﺖ ﺟﺪﻳﺪ ﺳﻴﺴﺘﻢ ﺗﮑﺮﺍﺭ ﻣﻲﺷﻮﺩ‪ .‬ﺗﻮﺟﻪ ﮐﻨﻴـﺪ ﮐـﻪ‬ ‫ﺩﺭ ﻫﺮ ﻣﺮﺣﻠﻪ ﻣﺘﻐﻴﺮﻫﺎﯼ ﻭﺭﻭﺩﯼ ﺟﺪﻳﺪﯼ ﺑﻪ ﻋﻨﻮﺍﻥ ﻭﺭﻭﺩﯼ ﺍﻭﻟﻴﻪ ﺑﻪ ﺳﻴﺴﺘﻢ ﻭﺍﺭﺩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﻣﺜﺎﻝ ‪ :۶-۲‬ﺑﺮﺍﻱ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﻣﺪﺍﺭ ﺷﻤﺎﺭﻧﺪﻩﻱ ﻣﺜﺎﻝ ‪ ۲-۲‬ﺍﺑﺘﺪﺍ ﺣﺎﻟﺖ ﺍﻭﻟﻴـﻪ ﺳﻴﺴـﺘﻢ }‪ {000-1‬ﻗـﺮﺍﺭ‬ ‫ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺳﭙﺲ ﺩﻭ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ‪ co , ro‬ﺭﺍ ﺑﻪ ﺩﻭ ﻭﺭﻭﺩﻱ ﻣﺪﺍﺭ ﻣﻲﺩﻫـﻴﻢ‪ .‬ﺣـﺎﻝ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﻧﻤـﺎﺩﻳﻦ ﺑـﺮﺍﻱ‬ ‫ﻫﺮﻳﻚ ﺍﺯ ﮔﺮﻩﻫﺎﻱ ﻣﻮﺟﻮﺩ ﺩﺭ ﻣﺪﺍﺭ ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺷﻜﻞ ‪ ۷-۲‬ﺩﺍﺭﻳﻢ‪:‬‬ ‫‪20. ro co‬‬ ‫‪… 19. 0,‬‬ ‫‪1. 1, 2. 0 … 11. co‬‬ ‫ﺩﺭ ﭘﺎﻳﺎﻥ ﻣﺮﺣﻠﻪ ﺍﻭﻝ ﻭﺭﻭﺩﻱ ‪ flip-flop‬ﻫﺎ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺍﺳﺖ‪.‬‬ ‫‪, out1 = 0 , out 2 = 0 , up = 1‬‬ ‫‪out o = ro co‬‬ ‫ﺣﺎﻝ ﺍﻳﻦ ﻭﺭﻭﺩﻳﻬﺎ ﺑﻪ ﻋﻨﻮﺍﻥ ﺣﺎﻟﺖ ﻓﻌﻠﻲ ﺳﻴﺴﺘﻢ ﺩﺭ ﻣﺮﺣﻠﻪ ﺑﻌﺪﻱ ﺍﺳـﺘﻔﺎﺩﻩ ﻣـﻲﺷـﻮﺩ ﻭ ﺩﺭ ﻣﺮﺣﻠـﻪ ﺑﻌـﺪ ﺑـﻪ‬ ‫ﺳﻴﺴﺘﻢ ﻭﺭﻭﺩﻳﻬﺎﻱ ﻧﻤﺎﺩﻳﻦ ﺟﺪﻳﺪ ﻣﻲﺩﻫﻴﻢ‪ .‬ﺩﺭ ﻣﺮﺣﻠﻪ ﺑﻌﺪ ﺑﺎ ﻭﺭﻭﺩﻳﻬﺎﻱ ‪ c1,r1‬ﺩﺍﺭﻳﻢ‪.‬‬ ‫‪out o = ((ro , co ) ⊕ c1 )r1‬‬ ‫‪out1 = ro r1co c1‬‬ ‫‪out 2 = 0‬‬ ‫‪up = 1‬‬ ‫ﺗﻮﺟﻪ ﻛﻨﻴﺪ ﻛﻪ ﺩﺭ ﭘﺎﻳﺎﻥ ﻫﺮ ﻣﺮﺣﻠﻪ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﻳﻚ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ﺟﺪﻳـﺪ ﺑـﻪ ﻋﻨـﻮﺍﻥ ﻭﺭﻭﺩﻱ ﺑـﻪ ﺳﻴﺴـﺘﻢ ﻭﺍﺭﺩ‬ ‫‪۳۰‬‬ ‫ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺧﺮﻭﺟﻲ ﺳﻴﺴﺘﻢ ﺑﻌﺪ ﺍﺯ ‪ k‬ﻣﺮﺣﻠﻪ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﺗـﺎﺑﻌﻲ ﺍﺯ } ‪ {IN @ o ,....., IN @ k‬ﻣـﻲﺑﺎﺷـﺪ‪.‬‬ ‫ﻋﺒﺎﺭﺍﺕ ﺑﻮﻟﻲ ﻛﻪ ﺑﻪ ﻋﻨﻮﺍﻥ ﺣﺎﻟﺖ ﺳﻴﺴـﺘﻢ ﺩﺭ ﺁﻥ ﻣﺮﺣﻠـﻪ ﺍﺯ ﺷـﺒﻴﻪ ﺳـﺎﺯﻱ ﺑﺪﺳـﺖ ﻣـﻲﺁﻳـﺪ ﻧﻤﺎﻳـﺎﻧﮕﺮ ﺗﻤـﺎﻡ‬ ‫ﺣﺎﻟﺘﻬﺎﻳﻲ ﺍﺳﺖ ﻛﻪ ﺍﺯ ﺣﺎﻟﺖ ﺍﻭﻟﻴﻪ ﺑﺎ ‪ k‬ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺁﻧﻬﺎ ﺭﺳﻴﺪ‪ .‬ﺍﻳﻦ ﻋﺒﺎﺭﺕ ﺑﻪ ﺻـﻮﺭﺕ ﺿـﻤﻨﻲ‬ ‫ﺣﺎﻟﺖ ﺳﻴﺴﺘﻢ ﺭﺍ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻭﺭﻭﺩﻳﻬﺎﻱ ‪ k‬ﻣﺮﺣﻠﻪ ﮔﺬﺷﺘﻪ } ‪ {IN @ o ,...., IN @ k‬ﺑﻴﺎﻥ ﻣﻲﻛﻨﺪ‪ .‬ﺷﻜﻞ ‪ ۹-۲‬ﻣﺪﻝ‬ ‫ﺗﻜﺮﺍﺭﻱ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﻳﻚ ﻣﺪﺍﺭ ﺭﺍ ﻧﻤﺎﻳﺶ ﻣﻲﺩﻫﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۹-۲‬ﻣﺪﻝ ﺗﮑﺮﺍﺭﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ‬ ‫ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺧﻄﺎﻫﺎﻱ ﺳﻴﺴﺘﻢ ﺑﺎ ﺑﺮﺭﺳﻲ ﺗﺎﺑﻊ ﺑﻮﻟﻲ ‪ Out@k‬ﺩﺭ ﻫﺮ ﻣﺮﺣﻠﻪﻱ ﺍﺟﺮﺍﻱ ﺑﺮﻧﺎﻣﻪ ﺑﺪﺳﺖ ﻣـﻲﺁﻳـﺪ‪.‬‬ ‫ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﻳﻚ ﺗﺮﻛﻴﺐ ﻏﻴﺮ ﻣﺠﺎﺯ ﺍﺯ ﺧﺮﻭﺟﻴﻬﺎ ﻛﺸـﻒ ﻣـﻲﺷـﻮﺩ‪ ،‬ﻋﺒـﺎﺭﺕ ‪ Out@k‬ﻣـﻲﺗﻮﺍﻧـﺪ ﺗﻤـﺎﻡ ﺭﺷـﺘﻪ‬ ‫ﻭﺭﻭﺩﻳﻬﺎﻱ ﻣﻤﻜﻦ ﺭﺍ ﻛﻪ ﺑﺎﻋﺚ ﻣﻲﺷﻮﻧﺪ ﺳﻴﺴﺘﻢ ﺑﻪ ﺍﻳﻦ ﺣﺎﻟـﺖ ﻏﻴﺮﻣﺠـﺎﺯ ﺑﺮﺳـﺪ‪ ،‬ﻣﺸـﺨﺺ ﻣـﻲﻛﻨـﺪ‪ .‬ﺑـﺮﺍﻱ‬ ‫ﺗﻮﻟﻴﺪﻛﺮﺩﻥ ﻳﻚ ﺍﺯ ﺭﺷﺘﻪ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ ﻛﻪ ﺑﺘﻮﺍﻧﻨﺪ ﺍﻳﻦ ﺧﻄﺎ ﺭﺍ ﻧﺸـﺎﻥ ﺩﻫﻨـﺪ‪ .‬ﻛـﺎﻓﻲ ﺍﺳـﺖ ﻛـﻪ ﻣﺘﻐﻴﺮﻫـﺎﻱ‬ ‫ﻧﻤﺎﺩﻳﻦ ﺭﺍ ﺑﻪ ﮔﻮﻧﻪﺍﻱ ﺗﻌﻴﻴﻦ ﻛﻨﻴﻢ ﻛﻪ ﺩﺭ ﺷﺮﺍﻳﻂ ﺧﻄﺎ ﺻﺪﻕ ﻛﻨﻨﺪ‪ .‬ﺍﮔﺮ ﻓﺮﺽ ﻛﻨﻴﻢ ﺑﺮﺩﺍﺭ ﺧﺮﻭﺟﻲ ﺩﺭﺳﺖ ﺩﺭ‬ ‫ﺯﻣـــﺎﻥ ‪ k‬ﺑـــﺎ ﺑـــﺮﺩﺍﺭ ﺑـــﻮﻟﻲ ‪ C ∈ B p‬ﻧﻤـــﺎﻳﺶ ﺩﺍﺩﻩ ﺷــﻮﺩ ﻭ ﺗﻤـــﺎﻡ ﻣﻘـــﺎﺩﻳﺮ ﻭﺭﻭﺩﻱ ﻛـــﻪ ﺩﺭ ﻋﺒـــﺎﺭﺕ‬ ‫‪p‬‬ ‫) ‪ Err = ∧ (OUT@ k ,i = Ci‬ﺻﺪﻕ ﻛﻨﻨﺪ ﻗﺎﺑﻠﻴﺖ ﻛﺸﻒ ﺧﻄﺎﻱ ﺳﻴﺴﺘﻢ ﺭﺍ ﺩﺍﺭﻧﺪ‪.‬‬ ‫‪i =1‬‬ ‫‪ -۲-۷-۲‬ﻣﺸﻜﻼﺕ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ‬ ‫ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻨﻜﻪ ﺍﺯ ﻧﻈﺮ ﺗﺌﻮﺭﻱ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻣﻲﺗﻮﺍﻧﺪ ﺗﺎ ﺑﻴﻨﻬﺎﻳﺖ ﺍﻧﺠـﺎﻡ ﺷـﻮﺩ‪ ،‬ﻣﺤـﺪﻭﺩﻳﺖ ﺣﺎﻓﻈـﻪ ﺩﺭ ﺳﻴﺴـﺘﻢ‬ ‫ﺷﺒﻴﻪﺳﺎﺯ ﻣﺎﻧﻊ ﺍﺯ ﺑﺰﺭﮒ ﺷﺪﻥ ﺑﻴﺶ ﺍﺯ ﺣﺪ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﻣﻲﺷﻮﺩ ﻭ ﻫﻤﺎﻧﻨﺪ ﺍﻟﮕﻮﺭﻳﺘﻢ ﭘﻴﻤﺎﻳﺶ ﻧﻤـﺎﺩﻳﻦ ﺣﺎﻟﺘﻬـﺎ‬ ‫‪۳۱‬‬ ‫ﺑﺰﺭﮒ ﺷﺪﻥ ﮔﺮﺍﻑ ‪ BDD‬ﻣﺴﺎﻟﻪ ﺍﺻﻠﻲ ﺩﺭ ﺍﻳﻦ ﻧﻮﻉ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ﺭﻓﻊ ﺍﻳﻦ ﻣﺸـﻜﻞ ﺭﺍﻩﺣﻠﻬـﺎﻱ‬ ‫ﻓﺮﺍﻭﺍﻧﻲ ﻣﻄﺮﺡ ﺷﺪﻩ ﺍﺳﺖ ﺗﺎ ﺍﻧﺪﺍﺯﻩﻱ ‪ BDD‬ﺭﺍ ﺩﺭ ﻳﻚ ﺣﺪ ﻣﻌﻘﻮﻝ ﻧﮕﻬﺪﺍﺭﻧﺪ‪.‬‬ ‫ﺑﺮﺍﯼ ﻣﺜﺎﻝ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺭﻭﺷﻲ ﻛﻪ ﺗﻮﺳﻂ ‪ Wilson‬ﺍﺭﺍﻳﻪ ﺷﺪﻩﺍﺳﺖ‪ ،‬ﺍﺷﺎﺭﻩﮐﺮﺩ‪ .‬ﺩﺭ ﺍﻳـﻦ ﺭﻭﺵ ﺑـﺮﺍﯼ ﺍﻧـﺪﺍﺯﻩﻱ‬ ‫‪ BDD‬ﺣﺪ ﻗﺮﺍﺭﺩﺍﺩﻩﻣﻲﺷﻮﺩ‪ .‬ﺯﻣﺎﻧﻲ ﮐﻪ ﺍﻧﺪﺍﺯﻩﻱ ‪ BDD‬ﺑﻪ ﺍﻳﻦ ﻣﻘﺪﺍﺭ ﻣﯽﺭﺳﺪ‪ ،‬ﻳﻚ ﻳﺎ ﭼﻨﺪ ﻣﺘﻐﻴـﺮ ﻧﻤـﺎﺩﻳﻦ ﺑـﻪ‬ ‫ﺖ ﺩﻳﮕـﺮ ﺭﺍ‬ ‫ﺛﺎﺑﺘﻬﺎﻱ ﺑﻮﻟﻲ ﺗﺒﺪﻳﻞﻣﻲﺷﻮﻧﺪ ﻭ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﻣﻌﺎﺩﻝ ﺳﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭﮔﺎﻡ ﺑﻌﺪ ﺷﺒﻴﻪﺳﺎﺯ ﻣﻘﺪﺍﺭ ﺛﺎﺑـ ِ‬ ‫ﺑﻪ ﻣﺘﻐﻴﺮ ﻧﺴﺒﺖ ﻣﻲﺩﻫﺪ‪ ،‬ﺗﺎ ﺩﺭ ﺍﺯﺍﻱ ﻫﺮ ﺩﻭ ﻣﻘﺪﺍ ِﺭ ﻣﺘﻐﻴﺮ‪ ،‬ﻋﺒﺎﺭﺕ ﺧﺮﻭﺟﻲ ﺭﺍ ﺑﺪﺳﺖ ﺁﻭﺭﺩ‪.‬‬ ‫ﺭﻭﺵ ﺩﻳﮕﺮ ﻛﻪ ﺗﻮﺳﻂ ‪ Bergmann‬ﺍﺭﺍﻳﻪ ﺷﺪﻩ ﺍﺳﺖ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ ﻣﺎﺟﻮﻟﻬـﺎﻱ ﺳﻴﺴـﺘﻢ ﺍﺳـﺖ ﻳﻌﻨـﻲ ﺩﺭ ﺍﺑﺘـﺪﺍ‬ ‫ﺳﻴﺴﺘﻢ ﻣﺎﺟﻮﻝﺑﻨﺪﻱ ﻣﻲﺷﻮﺩ‪ ،‬ﺳﭙﺲ ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﺍﻧﺪﺍﺯﻩﻱ ‪ BDD‬ﻫﺎ ﺍﺯ ﺣﺪ ﺩﻟﺨﻮﺍﻩ ﺑﺰﺭﮔﺘـﺮ ﺷـﺪ‪ .‬ﻣﺎﺟﻮﻟﻬـﺎﻱ‬ ‫ﺩﻳﮕﺮ ﺳﻴﺴﺘﻢ ﺑﺮﺍﺳﺎﺱ ﺍﻳﻨﻜﻪ ﻛﺪﺍﻡ ﻗﺴﻤﺖ ﺍﺯ ﻓﻀﺎﻱ ﺣﺎﻟﺖ ﺑﺮﺭﺳﻲ ﻧﺸﺪﻩ ﺍﺳﺖ ﺍﻧﺘﺨﺎﺏ ﻣـﻲﺷـﻮﻧﺪ ﻭ ﺷـﺒﻴﻪ‪-‬‬ ‫ﺳﺎﺯﻱ ﺭﻭﻱ ﺁﻧﻬﺎ ﺍﻧﺠﺎﻡ ﻣﻲ ﺷﻮﺩ‪.‬‬ ‫ﻣﺸﻜﻞ ﺑﻌﺪﻱ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﻋﺪﻡ ﺍﺳﺘﻔﺎﺩﻩ ﺁﻥ ﺍﺯ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺑـﺎﻻﻱ ﺳﻴﺴـﺘﻢ ﻣﺎﻧﻨـﺪ ﺗﻮﺻـﻴﻒ ﺳـﻄﺢ‬ ‫ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺍﻃﻼﻋﺎﺕ ﻣﻲﺗﻮﺍﻥ ﺍﺯ ﺟﺎﻳﮕﺰﻳﻨﻲ ﻳﻚ ﻋﻤﻞ ﺳﻄﺢ ﺑﺎﻻ ﻣﺎﻧﻨـﺪ ﺟﻤـﻊ ﺩﻭ‬ ‫ﻋﺪﺩ ﺻﺤﻴﺢ ﺑﺎ ﺗﻌﺪﺍﺩ ﺯﻳﺎﺩﻱ ﮔﻴﺖ ﺟﻠﻮﮔﻴﺮﻱ ﻛﺮﺩ ﻭ ﺣﺠﻢ ‪ BDD‬ﺭﺍ ﺑﺎﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻣـﺪﻟﻬﺎﻱ ﻣﻌـﺎﺩﻝ ﻛـﻮﭼﻜﺘﺮ‬ ‫ﻛﺮﺩ ﮐﻪ ﺩﺭﻧﺘﻴﺠﻪ ﺳﺮﻋﺖ ﻣﺤﺎﺳﺒﺎﺕ ﺍﻓﺰﺍﻳﺶ ﻣﻲﻳﺎﺑﺪ‪.‬‬ ‫ﺣﺘﻲ ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻨﮕﻮﻧﻪ ﺗﻼﺷﻬﺎ ﻫﻨﻮﺯ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺑﻪ ﺁﻥ ﺩﺭﺟﻪ ﺍﺯ ﺍﻋﺘﺒﺎﺭ ﻧﺮﺳﻴﺪﻩ ﺍﺳـﺖ ﻛـﻪ ﺑـﻪ ﻋﻨـﻮﺍﻥ‬ ‫ﻦ ﺷﺒﻴﻪﺳﺎﺯﻫﺎﯼ ﻣﻨﻄﻘﻲ ﻣﻄﺮﺡ ﺷﻮﺩ‪ .‬ﻭﻟﯽ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻣﻲﺗﻮﺍﻧﺪ‬ ‫ﺷﺒﻴﻪﺳﺎ ِﺯ ﺟﺎﻳﮕﺰﻳ ِ‬ ‫ﺳﺮﻋﺖ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺭﺍ ﺍﻓﺰﺍﻳﺶ ﺩﻫﺪ ﻭ ﺑﺎﻋﺚ ﺷﻮﺩ ﺗﺎ ﺍﺯ ﻓﺸﺎﺭ ﺭﻭﻱ ﺗﻴﻢ ﻃﺮﺍﺣﻲ ﺑﻜﺎﻫـﺪ‬ ‫ﻭ ﺍﺯ ﻫﺪﺭﺭﻓﺘﻦ ﻣﻨﺎﺑﻊ ﻭ ﻭﻗﺖ ﺗﻴﻢ ﻃﺮﺍﺣﻲ ﺗﺎ ﺣﺪ ﻗﺎﺑﻞ ﻣﻼﺣﻈﻪﺍﻱ ﺟﻠﻮﮔﻴﺮﻱ ﻛﻨﺪ‪.‬‬ ‫ﻫﺴﺘﻪﻱ ﺍﺻﻠﻲ ﻛﺎﺭﻱ ﻛﻪ ﺩﺭ ﺍﻳﻦ ﭘﺎﻳﺎﻥ ﻧﺎﻣﻪ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ ﺟﺎﻳﮕﺰﻳﻨﻲ ‪ BDD‬ﺑﺎ ﻳـﻚ ﺩﻳـﺎﮔﺮﺍﻡ ﺗﺼـﻤﻴﻢﮔﻴـﺮﻱ‬ ‫ﺳﻄﺢ ﺑﺎﻻﺗﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺩﻳﺎﮔﺮﺍﻡ ﻣﻲﺗﻮﺍﻥ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺑﺎﻻﻳﻲ ﺍﺯ ﺳﻴﺴﺘﻢ ﺭﺍ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻛـﺮﺩ‬ ‫‪۳۲‬‬ ‫ﮐﻪ ﺩﺭ ﻧﺘﻴﺠﻪ ﺣﺠﻢ ﻣﻨﺎﺑﻊ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺗﻮﺳـﻂ ﻧـﺮﻡ ﺍﻓـﺰﺍﺭ ﺷـﺒﻴﻪﺳـﺎﺯ ﻛـﺎﻫﺶ ﻣـﻲﻳﺎﺑـﺪ‪ .‬ﻫﻤﭽﻨـﻴﻦ ﺳـﺮﻋﺖ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﻪ ﻋﻠﺖ ﺟﺎﻳﮕﺰﻳﻨﻲ ﺍﻋﻤﺎﻝ ﺳﻄﺢ ﺑﺎﻻﻳﻲ ﻣﺜﻞ ﺟﻤﻊ‪ ،‬ﺿﺮﺏ ﻭ ﺑﻪ ﺗﻮﺍﻥ ﺭﺳﺎﻧﺪﻥ ﺍﻋـﺪﺍﺩ ﺻـﺤﻴﺢ ﺑـﻪ‬ ‫ﺟﺎﻱ ﺍﻋﻤﺎﻝ ﺳﻄﺢ ﭘﺎﻳﻴﻨﻲ ﻣﺜﻞ ‪ OR, AND‬ﺍﻓﺰﺍﻳﺶ ﻣﻲﻳﺎﺑﺪ‪.‬‬ ‫‪۳۳‬‬ ‫‪WLDD -۳‬ﻫﺎ‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﻓﺼﻞ ﮔﺬﺷﺘﻪ ﮔﻔﺘﻪ ﺷﺪ‪ ،‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭﺩﻭﻳﻲ ‪ BDD‬ﻳﻚ ﻣﺪﻝ ﻣﻮﻓﻖ ﺑﺮﺍﻱ ﻛﺎﺭ ﺑﺎ ﺗﻮﺍﺑـﻊ‬ ‫ﺑﻮﻟﻲ ﺑﻪ ﺻﻮﺭﺕ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻟﻴﻜﻦ ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﻣﻄﺮﺡ ﺷﺪ ‪ BDD‬ﺑﻪ ﺩﻟﻴﻞ ﺭﺷﺪ ﻧﻤـﺎﻳﻲ ﺩﺭ ﻃﺮﺍﺣﻴﻬـﺎﻱ‬ ‫ﺑﺰﺭﮒ‪ ،‬ﺣﺠﻢ ﺯﻳﺎﺩﻱ ﺍﺯ ﻣﻨﺎﺑﻊ ﻭ ﺣﺎﻓﻈﻪ ﺳﻴﺴﺘﻢ ﺷﺒﻴﻪ ﺳﺎﺯ ﺭﺍ ﻫﺪﺭ ﻣﻲﺩﻫﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠـﻪ ﺍﻟﮕﻮﺭﻳﺘﻤﻬـﺎﻱ ﺑﺴـﻴﺎﺭﯼ‬ ‫ﺑﺮﺍﻱ ﻛﺎﻫﺶ ﺍﻧﺪﺍﺯﻩﻱ ‪ BDD‬ﺍﺭﺍﻳﻪ ﺷﺪﻩﺍﺳﺖ‪ .‬ﺍﺯ ﺳﻮﻱ ﺩﻳﮕﺮ ﻣﻬﻨﺪﺳﻴﻦ ﻃـﺮﺍﺡ ﺳـﻌﻲ ﻣـﻲﻛﻨـﺪ ﺗـﺎ ‪ BDD‬ﺑـﺎ‬ ‫ﺳﺎﺧﺘﺎﺭﻫﺎﻱ ﮐﺎﻣﻠﺘﺮﯼ ﺟﺎﻳﮕﺰﻳﻦ ﺷﻮﺩ]‪ ،[۸‬ﺩﺭ ﺍﻳﻦ ﺭﺍﻩ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼـﻤﻴﻢ ﺩﻳﮕـﺮﻱ ﻃﺮﺍﺣـﻲ ﺷـﺪﻩﺍﺳـﺖ‪ .‬ﺩﺭ‬ ‫ﺑﻌﻀﯽ ﻣﻮﺍﺭﺩ ﻣﺒﻨﺎﻱ ﺗﻐﻴﻴﺮ ﺳﺎﺧﺘﺎﺭ‪ ،‬ﺗﻐﻴﻴﺮ ﺗﺎﺑﻊ ﺗﺠﺰﻳﻪ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺍﺳﺖ ﻭ ﺩﺭ ﻣﻮﺍﺭﺩﯼ ﺩﻳﮕﺮ ﺑﺎﻻﺗﺮﺑﺮﺩﻥ ﺳﻄﺢ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﻳﺎ ﺣﺘﻲ ﺟﺎﻳﮕﺰﻳﻦ ﻛﺮﺩﻥ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺑﻮﻟﻲ ﻳﺎ ﮐﻠﻤﻪ ﺑﺮﺍﻱ ﺑﻬﻴﻨﻪ ﻛﺮﺩ ِﻥ ﺩﻳﺎﮔﺮﺍﻡ‪ ،‬ﺑﻪﻛﺎﺭ ﻣﻲﺭﻭﺩ‪ .‬ﺩﺭ ﺍﻳﻦ‬ ‫ﺑﺨﺶ ﭘﺎﻳﺎﻥ ﻧﺎﻣﻪ ﺳﻌﻲ ﻣﻲﺷﻮﺩ ﺗﺎ ﭼﻨﺪ ﺳﺎﺧﺘﺎﺭ ﺟﺎﻳﮕﺰﻳﻦ ‪ BDD‬ﻣﻌﺮﻓﻲ ﻭ ﺗﺤﻠﻴﻞ ﺷﻮﺩ ﺗﺎ ﺩﺭ ﺑﺨﺶ ﺑﻌﺪﻱ ﺑـﺎ‬ ‫ﻣﻌﺮﻓﻲ ﺳﺎﺧﺘﺎﺭ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺩﺭﺍﻳﻦ ﭘﺮﻭﮊﻩ‪ ،‬ﺑﻪ ﻣﻘﺎﻳﺴﻪ ﺁﻥ ﺑﺎ ﺳﺎﺧﺘﺎﺭﻫﺎﻱ ﻣﻄﺮﺡ ﺷﺪﻩ ﺩﺭ ﺍﻳﻦ ﺑﺨﺶ ﭘﺮﺩﺍﺧﺘﻪ‪-‬‬ ‫ﺷﻮﺩ‪.‬‬ ‫‪ -۱-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻋﻤﻠﻜﺮﺩﻱ )‪(Functional Decision Diagram‬‬ ‫ﺍﻭﻟﻴﻦ ﺩﻳﺎﮔﺮﺍﻣﻲ ﻛﻪ ﺩﺭ ﺍﻳﻦ ﺑﺨﺶ ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﺩ ‪ FDD‬ﻳﺎ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻋﻤﻠﻜﺮﺩﻱ ﻣﻲﺑﺎﺷـﺪ‪ ،‬ﻛـﻪ ﺳـﻄﺢ‬ ‫‪۳۴‬‬ ‫ﻛﺎﺭﻱ ﺁﻥ ﻣﺎﻧﻨﺪ ‪ BDD‬ﺩﺭ ﺳﻄﺢ ﮔﻴﺖ ﻣﻲﺑﺎﺷﺪ ﻭ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺭﺍ ﻣﺪﻝ ﻣﻲﻛﻨﺪ‪ ،‬ﻭﻟـﻲ ﺑـﻪ ﺟـﺎﻱ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ‬ ‫ﺭﺍﺑﻄﻪ ﺷﺎﻧﻮﻥ ﺑﺮﺍﻱ ﺗﺠﺰﻳﻪ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺍﺯ ﺑﺴﻂ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﻛﻨﺪ]‪.[۹‬‬ ‫‪ -۱-۱-۳‬ﺑﺴﻂ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ ﻳﺎ ﺩﺍﻭﻳﻮ ﻣﺜﺒﺖ )‪(Positive Davio‬‬ ‫ﺩﺭ ﺑﺴﻂ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ ﻫﺮ ﺗﺎﺑﻊ ﺑﻮﻟﻲ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﭼﻨﺪ ﺟﻤﻠﻪﺍﻱ ‪ XOR‬ﻧﻮﺷﺖ ‪:‬‬ ‫‪f ( x0 , x1 ,..., x n −1 ) = a 0 ⊕ a1 • x1 ⊕ a 2 • x1 ⊕ a3 • x1 • x 2‬‬ ‫‪⊕ ... ⊕ a 2n −1 • x1 • ... • x n −1‬‬ ‫‪2 n −1‬‬ ‫‪= ⊕ ai • π i‬‬ ‫‪i =0‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ‪:‬‬ ‫‪ : π i‬ﭘﻲ ﻧﺎﻡ ﺩﺍﺭﺩ ﻛﻪ ﻫﻢ ﺍﺭﺯ ﺟﻤﻠﻪﻱ ﺿﺮﺑﻲ ﺩﺭ ‪ SOP‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ : ai‬ﺿﺮﻳﺐ ﺟﻤﻠﻪﻱ ‪ π i‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫⊕ ‪ :‬ﻳﻚ ﺟﻤﻊ ﺑﻪ ﭘﻴﻤﺎﻧﻪ ﺩﻭ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺩﺭ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﯽ ﺑﻪ ﺻﻮﺭﺕ ‪ XOR‬ﺩﺭﻣﻲﺁﻳﺪ‪.‬‬ ‫ﺍﻳﻦ ﮔﻮﻧﻪ ﻧﻤﺎﻳﺶ ‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﺻﻔﺮ ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺯﻳﺮﺍ ﻣﺘﻐﻴﺮﻫﺎ ﻓﻘـﻂ ﺑـﻪ ﺻـﻮﺭﺕ ﻏﻴـﺮ ﻣﮑﻤـﻞ ﺧـﻮﺩ‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﺷﺪﻩﺍﻧﺪ ﻭ ﺍﺯ ﻣﻜﻤﻞ ﺁﻧﻬﺎ ﺍﺳﺘﻔﺎﺩﻩ ﻧﺸﺪﻩ ﺍﺳﺖ‪ .‬ﺛﺎﺑﺖ ﻣﻲﺷﻮﺩ ﻛﻪ ‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﺻـﻔﺮ ﻳـﻚ ﻧﻤـﺎﻳﺶ‬ ‫ﻳﻜﺘﺎ ﺍﺯ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ﺑﺴـﻂ ﺩﺍﺩﻥ ‪ RME‬ﻣﺤـﺪﻭﺩﻳﺖ ﺍﺳـﺘﻔﺎﺩﻩ ﻣﺴـﺘﻘﻴﻢ ﻣﺘﻐﻴﺮﻫـﺎ ﺭﺍ ﺣـﺬﻑ‬ ‫ﻣﻲﺷﻮﺩ ﻭ ﺩﺭﻧﺘﻴﺠﻪ ﺩﻭ ﺑﺴﻂ ﺑﺮﺍﻱ ‪ RME‬ﻭﺟﻮﺩ ﺩﺍﺭﺩ‪:‬‬ ‫‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﺛﺎﺑﺖ‪ :‬ﻫﺮ ﻣﺘﻐﻴﺮ ﻳﺎ ﺑﻪ ﺻﻮﺭﺕ ﻣﺴﺘﻘﻴﻢ ﻭ ﻳﺎ ﺑﻪ ﺻﻮﺭﺕ ﻣﻜﻤﻞ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺍﻣﺎ ﺍﺯ ﻫﺮ ﺩﻭ‬ ‫ﺑﻪ ﺻﻮﺭﺕ ﻫﻤﺰﻣﺎﻥ ﺍﺳﺘﻔﺎﺩﻩ ﻧﻤﻲﺷﻮﺩ‪ .‬ﺍﮔﺮ ﻳﻚ ﻋﺒﺎﺭﺕ ‪ n‬ﻣﺘﻐﻴﺮ ﺑـﻮﻟﻲ ﺩﺍﺷـﺘﻪ ﺑﺎﺷـﺪ ‪ RME ،2n‬ﻣﺘﻔـﺎﻭﺕ ﺑـﺎ‬ ‫ﻗﻄﺒﻴﺘﻬﺎﻱ ﮔﻮﻧﺎﮔﻮﻥ ﻗﺎﺑﻞ ﻃﺮﺍﺣﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺛﺎﺑﺖ ﻣﻲﺷﻮﺩ ﻛﻪ ‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﺛﺎﺑﺖ ﻧﻴﺰ ﻧﻤﺎﻳﺸـﻲ ﻳﻜﺘـﺎ ﺑـﺮﺍﻱ‬ ‫ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﻣﻲﺑﺎﺷﺪ]‪.[۹‬‬ ‫‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﻣﺮﻛﺐ‪ :‬ﺩﺭ ﺍﻳﻦ ﺑﺴﻂ ﻫﺮ ﻣﺘﻐﻴﺮ ﻫﻢ ﺑﻪ ﺻﻮﺭﺕ ﻣﺴﺘﻘﻴﻢ ﻭ ﻫﻢ ﺑـﻪ ﺻـﻮﺭﺕ ﻣﻜﻤـﻞ ﺍﺳـﺘﻔﺎﺩﻩ‬ ‫‪۳۵‬‬ ‫ﻣﻲﺷﻮﺩ‪ ،‬ﺑﻨﺎﺑﺮﺍﻳﻦ ‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﻣﺮﻛﺐ ﺑﺴﻴﺎﺭ ﮔﺴﺘﺮﺩﻩﺗﺮ ﺍﺯ ﺩﻭ ﺑﺴﻂ ﻗﺒﻠﻲ ﻣﻲ ﺑﺎﺷﺪ ﻭﻟﻲ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎ ﺑﺮﺍﻱ‬ ‫ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﻧﻤﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺑﺮﺍﻱ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻥ ﺑﺴﻂ ‪ RME‬ﺗﺒﺪﻳﻞ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ )‪ (RMT‬ﺭﻭﻱ ﻧﻤﺎﻳﺶ ‪ SOP‬ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺍﻋﻤﺎﻝ ﻣﻲﺷـﻮﺩ‪.‬‬ ‫ﺩﺭ ‪ RMT‬ﻫﺮ ﺿﺮﻳﺐ ﺩﺭ ﻧﻤﺎﻳﺶ ‪ SOP‬ﺑﺎ ﻳﻚ ﺗﺒﺪﻳﻞ ﺧﻄﻲ ﺑﻪ ﻳﻚ ﺿـﺮﻳﺐ ﺑﺴـﻂ ‪ RME‬ﺗﺒـﺪﻳﻞ ﻣـﻲﺷـﻮﺩ‪.‬‬ ‫ﻧﻜﺘﻪ ﻣﻨﻔﻲ ﺍﻳﻦ ﺭﻭﺵ ﭘﻴﭽﻴﺪﮔﻲ ﺁﻥ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺯﻳﺮﺍ ﺑﺮﺍﻱ ‪ n‬ﻣﺘﻐﻴﺮ ﺑﺎﻳﺪ ‪ 2n‬ﺿـﺮﻳﺐ ﻣﺤﺎﺳـﺒﻪ ﺷـﻮﺩ‪ ،‬ﺩﺭ ﻧﺘﻴﺠـﻪ‬ ‫ﻣﺤﺎﺳﺒﻪ ‪ RME‬ﺑﺮﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﺰﺭﮒ ﺍﻣﻜﺎﻥ ﭘﺬﻳﺮ ﻧﻴﺴﺖ‪.‬‬ ‫‪ -۲-۱-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪FDD‬‬ ‫ﺖ ﺩﻭ ﻣﻘﺪﺍﺭﻱ‪ ،‬ﺍﻋﻤﺎﻝ ﻛﻨﻴﻢ ﻳﻚ ﻧﻤﺎﻳﺶ ﺑﺎﺯﮔﺸﺘﻲ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ‬ ‫ﺍﮔﺮ ﺑﺴﻂ ﺷﺎﻧﻮﻥ ﺭﺍ ﺭﻭﻱ ‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﺛﺎﺑ ِ‬ ‫ﭼﻨﺪ ﻻﻳﻪﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ‪:‬‬ ‫) ‪Fn = Fn ( x1 , x2 ,..., xn‬‬ ‫‪shanon‬‬ ‫‪= F ( x = 0) ⊕ F ( x = 1) • x‬‬ ‫‪= F ( x = 0) ⊕ [ F ( x = 0) ⊕ F ( x = 1)] • x‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪x =1⊕ x‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫‪n‬‬ ‫*‬ ‫‪= Fn ( xn = 0) ⊕ Fn • xn‬‬ ‫ﻛﻪ ﺩﺭ ﺍﻳﻨﺠﺎ )‪ F ∗ (n‬ﻳﻚ ﻋﺒﺎﺭﺕ ﺍﺯ ‪ n-1‬ﻣﺘﻐﻴﺮ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺳﺎﺧﺘﺎﺭﻱ ﺷﺒﻴﻪ ‪ Fn-1‬ﺩﺍﺭﺩ‪.‬‬ ‫ﻣﺜــﺎﻝ ‪ :۱-۳‬ﺑــﺎ ﺍﺳــﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳــﻦ ﺍﻟﮕــﻮﺭﻳﺘﻢ ﺑﺎﺯﮔﺸــﺘﻲ ﻧﻤــﺎﻳﺶ ﭼﻨــﺪ ﻻﻳــﻪ ﻋﺒــﺎﺭﺕ ﭼﻬــﺎﺭ ﻣﺘﻐﻴــﺮﻱ‬ ‫‪ f = a • b • d + b • c • d + b • c • d‬ﺑﻪ ﺻﻮﺭﺕ ﺷﻜﻞ ﺷﻤﺎﺭﻩﻱ ‪ ۱-۳‬ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪.‬‬ ‫ﺷﮑﻞ ‪ -۱-۳‬ﺩﺭﺧﺖ ‪ FDD‬ﻣﻌﺎﺩﻝ ﺗﺎﺑﻊ ‪[۹] f = a • b • d + b • c • d + b • c • d‬‬ ‫ﺗﻮﺟﻪ ﻛﻨﻴﺪ ﻛﻪ ﺍﻳﻦ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎﻱ ‪ RME‬ﺑﺎ ﻗﻄﺒﻴﺖ ﺛﺎﺑﺖ ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﺗﻤﺎﻡ ﺿـﺮﺍﻳﺐ ﻧﻤـﺎﻳﺶ ﺩﺍﺩﻩ ﺷـﻮﻧﺪ‪،‬‬ ‫‪۳۶‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺣﺎﻝ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺭﻭﺷﻬﺎﻱ ﺣﺬﻑ ﺍﻓﺮﻭﻧﮕﻲ ﻣﻮﺟﻮﺩ ﺩﺭ ‪ ،FDD‬ﻧﻤﺎﻳﺶ ﻛﺎﻫﺶ ﻳﺎﻓﺘـﻪ ﺍﻳـﻦ ﺩﺭﺧـﺖ‬ ‫ﻣﻨﻄﻘﻲ ﻃﺮﺍﺣﻲ ﻣﻲﺷﻮﺩ‪:‬‬ ‫‪ -۱‬ﺗﻤﺎﻡ ﺯﻳﺮﺩﺭﺧﺘﻬﺎﻱ ﺍﻳﺰﻭﻣﻮﺭﻓﻴﮏ ﺑﺎ ﻫﻢ ﺍﺩﻏﺎﻡ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫‪ -۲‬ﺗﻤﺎﻡ ﮔﺮﻩﻫﺎﻳﻲ ﻛﻪ ﻓﺮﺯﻧﺪﺍﻥ ﺍﻳﺰﻭﻣﻮﺭﻓﻴﮏ ﺩﺍﺭﻧﺪ ﺣﺬﻑ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫ِﺍﻋﻤﺎﻝ ﺍﻳﻦ ﺩﻭ ﻗﺎﻋﺪﻩ ﺑﺮ ﺭﻭﻱ ﺩﺭﺧﺖ ﻣﺜﺎﻝ ‪ ،۱-۳‬ﺩﺭﺧﺖ ﺭﺍ ﺑﻪ ﮔﺮﺍﻑ ﺷﻜﻞ ‪ ۲-۳‬ﺗﺒﺪﻳﻞ ﻣﻲﻛﻨـﺪ‪ .‬ﺍﻳـﻦ ﻣـﺪﻝ‬ ‫ﻳﻚ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎ ﻭ ﺑﺴﻴﺎﺭ ﻛﺎﺭﺁﻣﺪ ﺑﺮﺍﻱ ﻳﻚ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﻣﻲ ﺑﺎﺷـﺪ‪ ،‬ﻛـﻪ ﺑـﻪ ﺁﻥ ‪ FDD‬ﻳـﺎ ﺩﻳـﺎﮔﺮﺍﻡ ﺗﺼـﻤﻴﻢ‬ ‫ﻋﻤﻠﻜﺮﺩﻱ ﮔﻔﺘﻪ ﻣﻲﺷﻮﺩ‪ ،‬ﺯﻳﺮﺍ ﻫﺮ ﮔﺮ ِﻩ ‪ FDD‬ﻧﻤﺎﻳﺎﻧﮕﺮ ﺍﻳﻦ ﻣﺴﺎﻟﻪ ﺍﺳﺖ ﻛﻪ ﺁﻳﺎ ﺟﻤﻠﻪﻱ ﭘﻲ ﺗﺎﺑﻊ ﺑﻮﻟﻲ ﺍﻋﻤـﺎﻝ‬ ‫ﻣﻲﺷﻮﺩ ﻳﺎ ﻧﻪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۲-۳‬ﮔﺮﺍﻑ ﮐﺎﻫﺶﻳﺎﻓﺘﻪ ﺩﺭﺧﺖ ﺷﮑﻞ ‪[۹] ۱-۳‬‬ ‫ﻣﺰﻳﺖ ‪ FDD‬ﺑﺮ ‪ BDD‬ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﺣﺘﻲ ﺍﮔﺮ ﺗﻌﺪﺍﺩ ﮔﺮﻩﻫﺎﻱ ﺍﻳﻦ ﺩﻭ ﻧﻤﺎﻳﺶ ﺩﺭ ﻳﻚ ﻋﺒـﺎﺭﺕ ﺑﺮﺍﺑـﺮ ﺑﺎﺷـﻨﺪ‬ ‫ﺗﻌﺪﺍﺩ ﻳﺎﻟﻬﺎﻳﻲ ﻛﻪ ﺩﺭ ‪ FDD‬ﺑﻪ ﻛﺎﺭ ﺑﺮﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺑﺴﻴﺎﺭ ﻛﻤﺘﺮ ﻣﻲﺑﺎﺷﺪ ]‪ [۹‬ﺯﻳﺮﺍ ﺗﻌـﺪﺍﺩ ﻳﺎﻟﻬـﺎ ﺑﺮﺍﺑـﺮ ﺑـﺎ ﺗﻌـﺪﺍﺩ‬ ‫ﺟﻤﻠﻪﻫﺎﻱ ﭘﻲ ‪ RME‬ﺩﻭ ﻣﻘﺪﺍﺭﻩ ﻛﺎﻫﺶ ﻳﺎﻓﺘﻪ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻣﺎ ﺍﻳﻦ ﺭﻭﺵ ﻣﺎﻧﻨﺪ ‪ BDD‬ﺑﻪ ﺷﺪﺕ ﻭﺍﺑﺴﺘﻪ ﺑﻪ ﺗﺮﺗﻴﺐ‬ ‫ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۲-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻋﻤﻠﻜﺮﺩﻱ ﻛﺮﻭﻧﻜﺮ )‪(KFDD‬‬ ‫‪ KFDD‬ﮔﺴﺘﺮﺵ ﻳﺎﻓﺘﻪ ‪ FDD‬ﻭ‪ BDD‬ﻣﻲﺑﺎﺷﺪ ﻭ ﺩﺭ ﻋﻴﻦ ﺣﺎﻝ ﺳﻌﻲ ﻣﻲﻛﻨﺪ ﺍﺯ ﻣﺰﺍﻳﺎﻱ ﺍﻳﻦ ﺩﻭ ﻧﻤـﺎﻳﺶ ﺑـﻪ‬ ‫ﻃﻮﺭ ﻫﻤﺰﻣﺎﻥ ﺍﺳﺘﻔﺎﺩﻩ ﮐﻨﺪ‪ .‬ﺩﺍﺩﻩ ﺳﺎﺧﺘﺎﺭ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﺍﺟﺎﺯﻩ ﻣﻲﺩﻫﺪ ﻛﻪ ﻧﻤﺎﻳﺶ ﺗﺎﺑﻊ ﺑـﺎ ﺗﻮﺟـﻪ‬ ‫‪۳۷‬‬ ‫ﺑﻪ ﺧﻮﺩ ﻣﺴﺎﻟﻪ ﺑﻬﻴﻨﻪ ﺳﺎﺯﻱ ﺷﻮﺩ‪ KFDD .‬ﺍﺟﺎﺯﻩ ﻣﻲﺩﻫﺪ ﺗﺎ ﺗﻮﺍﺑﻌﻲ ﻛﻪ ﻧﻤﺎﻳﺶ ‪ BDD‬ﻭ ‪ FDD‬ﺁﻧﻬـﺎ ﺍﻧـﺪﺍﺯﻩﻱ‬ ‫ﻧﻤﺎﻳﻲ ﺩﺍﺭﻧﺪ ﺑﻪ ﺻﻮﺭﺗﯽ ﺑﻬﻴﻨﻪ ﻧﻤﺎﻳﺶﺩﺍﺩﻩﺷﻮﻧﺪ]‪ .[۱۰‬ﻟﻴﮑﻦ ﺍﻧﺪﺍﺯﻩﻱ ﺍﻳﻦ ﻧﻤـﺎﻳﺶ ﻧﻴـﺰ ﻫﻤﺎﻧﻨـﺪ ‪BDD‬ﻭ ‪FDD‬‬ ‫ﺑﻪ ﺷﺪﺕ ﻭﺍﺑﺴﺘﻪ ﺑﻪ ﺗﺮﺗﻴﺐ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻟﺬﺍ ﺑﺮﺍﻱ ﺍﻳﻦ ﻣﺪﻝ ﻧﻴﺰ‪ ،‬ﺭﻭﺷﻬﺎﻱ ﺷﻬﻮﺩﯼ ﺑـﺮﺍﯼ ﺗﻌﻴـﻴﻦ ﺗﺮﺗﻴـﺐ‬ ‫ﻣﺘﻐﻴﺮﻫﺎ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱-۲-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪KFDD‬‬ ‫ﺩﺭ ‪ KFDD‬ﺍﺯ ﺳﻪ ﻋﺒﺎﺭﺕ ﺗﺠﺰﻳﻪ ﻣﺘﻔﺎﻭﺕ ﺑﺮﺍﻱ ﺗﺠﺰﻳﻪ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪:‬‬ ‫‪ -۱‬ﺷﺎﻧﻮﻥ )‪(S‬‬ ‫‪1‬‬ ‫‪0‬‬ ‫‪ -۲‬ﺩﺍﻭﻳﻮ ﻣﺜﺒﺖ )‪(pD‬‬ ‫‪2‬‬ ‫‪0‬‬ ‫‪ -۳‬ﺩﺍﻭﻳﻮ ﻣﻨﻔﻲ )‪(nD‬‬ ‫‪1‬‬ ‫‪0‬‬ ‫‪f = xi f i + xi f i‬‬ ‫‪f = f i + xi f i‬‬ ‫‪f = f i + xi f i‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ ‪ ( f i1 ) f i 0‬ﻧﻤﺎﻳﻨﺪﻩ ‪ cofactor‬ﺑﺎ ﻓﺮﺽ ‪ ( x=1 ) x=0‬ﻭ ‪ f i 2 = f i 0 ⊕ f i 1‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺑﻪ ﻫﺮﻳﻚ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻋﻀﻮ ﻣﺠﻤﻮﻋﻪ ‪ Xn‬ﻳﻚ ﻭ ﻓﻘﻂ ﻋﺒﺎﺭﺕ ﺗﺠﺰﻳـﻪ ﻣﺘﻨـﺎﻇﺮ ﺷـﺪﻩ ﺍﺳـﺖ‪ ،‬ﺍﻳـﻦ ﺗﻨـﺎﻇﺮ ﺩﺭ‬ ‫ﻟﻴﺴﺖ ﻧﻮﻉ ﺗﺠﺰﻳﻪ‪ (DTL) ٢٥‬ﺑﻴﺎﻥ ﺷﺪﻩ ﺍﺳﺖ‪DTL = {d1 , d 2 ,..., d n } .‬‬ ‫‪d i ∈ {S , pD, nD},‬‬ ‫ﻳﮏ ‪ KFDD‬ﺑﺮ ﺭﻭﯼ ﻣﺠﻤﻮﻋﻪﻱ ‪ n‬ﻣﺘﻐﻴﺮ ﺑﻮﻟﯽ ﺑﻪ ﺻﻮﺭﺕ ﻳﮏ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ‪ G‬ﻭ ﻳﮏ ﻟﻴﺴﺖ ﻧﻮﻉ ﺗﺠﺰﻳﻪ‬ ‫‪ d‬ﺗﻌﺮﻳﻒ ﻣﻲﺷﻮﺩ‪ .‬ﺑﺮﺍﯼ ﺗﺎﺑﻊ ‪ f G d : B n → B‬ﺩﺍﺭﻳﻢ‪:‬‬ ‫ ﺍﮔﺮ ‪ G‬ﺷﺎﻣﻞ ﻳﻚ ﮔﺮﻩ ﺻﻔﺮ ﻳﺎ ﻳﻚ ﺑﻮﺩ‪ G ،‬ﻣﻌﺎﺩﻝ ﺗﺎﺑﻊ ﺛﺎﺑﺖ ﺻﻔﺮ ﻳﺎ ﻳﻚ ﺍﺳﺖ‪.‬‬‫ ﺍﮔﺮ ﺭﻳﺸﻪ ‪ G‬ﺑﺮﭼﺴﺐ ‪ xi‬ﺩﺍﺷﺖ ﺁﻧﮕﺎﻩ ‪ KFDD ،G‬ﺗﺎﺑﻊ ﺯﻳﺮ ﺍﺳﺖ‪.‬‬‫‪di = S‬‬ ‫‪d i = pD‬‬ ‫‪d i = nD‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ ‪ f low , f high‬ﺩﻭ ﺯﻳﺮﺩﺭﺧﺘﻲ ﻫﺴﺘﻨﺪ ﻛﻪ ﮔﺮﻩ ﺑﻪ ﺁﻧﻬﺎ ﺍﺷﺎﺭﻩ ﻣﻲﻛﻨﺪ‪.‬‬ ‫‪Decomposition Type List 25‬‬ ‫‪۳۸‬‬ ‫‪ xi • f low ⊕ xi • f high‬‬ ‫‪‬‬ ‫‪ f low ⊕ xi • f high‬‬ ‫‪‬‬ ‫‪ f low ⊕ xi • f high‬‬ ‫ﻳﻚ ﮔﺮﻩ ﺩﺭ ‪ S-node ، FDD‬ﻧﺎﻡ ﺩﺍﺭﺩ ﺍﮔﺮ ﺑﺎ ﺭﺍﺑﻄﻪ ﺷﺎﻧﻮﻥ ﺑﺴﻂ ﺩﺍﺩﻩ ﺷﺪﻩ ﺑﺎﺷﺪ‪ .‬ﺍﮔـﺮ ﻳـﮏ ﮔـﺮﻩ ﺑـﺎ ﺗﺠﺰﻳـﻪ‬ ‫ﺩﺍﻭﻳﻮ ﺑﺴﻂ ﺩﺍﺩﻩ ﺷﺪﻩ ﺑﺎﺷﺪ‪ ،‬ﺑﻨﺎ ﺑﻪ ﻧﻮﻉ ﺁﻥ ‪ pD-node‬ﻳﺎ ‪ nD-Node‬ﻧﺎﻣﻴﺪﻩ ﻣـﻲﺷـﻮﺩ‪ .‬ﺑـﺎ ﺗﻮﺟـﻪ ﺑـﻪ ﺗﻌﺮﻳـﻒ‬ ‫‪ KFDD‬ﺗﺠﺰﻳﻪ ﻳﻜﺴﺎﻧﻲ ‪ di‬ﺑﺮﺍﻱ ﻻﻳﻪﻱ ‪ i‬ﺍﻡ ﮔﺮﺍﻑ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷـﻮﺩ‪ .‬ﻣـﻲﺗـﻮﺍﻥ ﻧﺘﻴﺠـﻪ ﮔﺮﻓـﺖ ﻛـﻪ ‪KFDD‬‬ ‫ﮔﺴﺘﺮﺵ ﻳﺎﻓﺘﻪ ‪ BDD‬ﻭ ‪ FDD‬ﺍﺳﺖ ﺯﻳﺮﺍ ﺍﮔﺮ ﺩﺭ ﺗﻤﺎﻡ ﻻﻳﻪﻫﺎ ﺗﺠﺰﻳﻪ ﺷﺎﻧﻮﻥ ﺍﺳﺘﻔﺎﺩﻩ ﺷـﻮﺩ ﺑـﻪ ‪ BDD‬ﻭ ﺍﮔـﺮ‬ ‫ﺗﺠﺰﻳﻪ ﺩﺍﻭﻳﻮ ﺍﺳﺘﻔﺎﺩﻩ ﺷﻮﺩ ﺑﻪ ‪ FDD‬ﻣﻲﺭﺳﻴﻢ‪ .‬ﺩﺭ ‪ KFDD‬ﺳﻪ ﻧﻮﻉ ﺧﻼﺻﻪﺳﺎﺯﻱ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪:‬‬ ‫ﻧﻮﻉ ‪ : I‬ﮔﺮﻩ ‪ v′‬ﻛﻪ ﺑﺎ ﮔﺮﻩ ‪ v‬ﻫﻢ ﺑﺮﭼﺴﺐ ﺍﺳﺖ ﻭ ﻫﺮ ﺩﻭ ﺯﻳﺮﺩﺭﺧﺘﻬﺎﻱ ﺍﻳﺰﻭﻣﻮﺭﻓﻴﮏ ﺩﺍﺭﻧﺪ‪ ،‬ﺣﺬﻑ ﻣﻲﺷﻮﺩ ﻭ‬ ‫ﻳﺎﻝ ﺍﺷﺎﺭﻩ ﻛﻨﻨﺪﻩ ﺑﻪ ‪ v′‬ﺑﻪ ‪ v‬ﻣﺘﺼﻞ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﻧﻮﻉ ‪ : S‬ﮔﺮﻩ ‪ v‬ﻛﻪ ﻫﺮ ﺩﻭ ﻳﺎﻝ ﺧﺮﻭﺟﻲ ﺁﻥ ﺑﻪ ﮔﺮﻩ ‪ v′‬ﺍﺷﺎﺭﻩ ﻣﻲﻛﻨﻨﺪ‪ ،‬ﺣﺬﻑ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﻧﻮﻉ ‪ : D‬ﮔﺮﻩ ‪ v‬ﻛﻪ ﻳﺎﻝ ‪ High‬ﺁﻥ ﺑﻪ ﺑﺮﮒ ﺻﻔﺮ ﺍﺷﺎﺭﻩ ﻣﻲﻛﻨﺪ‪ ،‬ﺣﺬﻑ ﻣﻲﺷﻮﺩ ﻭ ﻳﺎﻝ ﺍﺷﺎﺭﻩ ﻛﻨﻨـﺪﻩ ﺑـﻪ ﺁﻥ ﺑـﻪ‬ ‫ﮔﺮﻩ ‪ low‬ﻣﺘﺼﻞ ﻣﻲﺷﻮﺩ‪ .‬ﻫﻤﻪﻱ ﮔﺮﻩﻫﺎﻱ ﻣﻮﺟﻮﺩ ﺩﺭ ‪ FDD‬ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﺎ ﺭﻭﺵ ﺣﺬﻑ ﻧﻮﻉ ‪ I‬ﻣﻮﺭﺩ ﺑﺮﺭﺳـﻲ‬ ‫ﻗﺮﺍﺭ ﺩﺍﺩ‪ ،‬ﻟﻴﻜﻦ ﺣﺬﻑ ﻧﻮﻉ ‪ S‬ﻓﻘﻂ ﺑﺮﺍﻱ ‪ S-node‬ﻫﺎ ﻭ ﺣﺬﻑ ﻧﻮﻉ ‪ D‬ﻓﻘﻂ ﺑـﺮﺍﻱ ‪ D-node‬ﻫـﺎ ﻗﺎﺑـﻞ ﺍﻋﻤـﺎﻝ‬ ‫ﺍﺳﺖ‪.‬‬ ‫ﺑﺮﺍﻱ ﺑﺮﺭﺳﻲ ﻫﻢ ﺍﺭﺯﻱ ﺩﻭ ‪ KFDD‬ﺑﺎﻳﺪ‪ DTL‬ﺁﻧﻬﺎ ﺑﺎ ﻫﻢ ﻳﻜﻲ ﺑﺎﺷﺪ‪ ،‬ﺳﭙﺲ ﺑﺎ ﺍﻋﻤﺎﻝ ﺭﻭﺍﺑـﻂ ﻛـﺎﻫﺶ ﺩﻫﻨـﺪﻩ‬ ‫ﻭﻋﻜﺲ ﺁﻧﻬﺎ ﻳﻜﻲ ﻗﺎﺑﻞ ﺗﺒﺪﻳﻞ ﺑﻪ ﺩﻳﮕﺮﻱ ﺑﺎﺷﺪ‪ .‬ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻳﺎﻟﻬﺎﻱ ﻣﻜﻤﻞ‪ ،‬ﻫﻤﺎﻧﻨ ِﺪ ‪ ،BDD‬ﻣـﻲﺗـﻮﺍﻥ ﺍﻧـﺪﺍﺯﻩ‬ ‫‪ KFDD‬ﺭﺍ ‪ ۱۰‬ﺩﺭﺻﺪ ﻛﺎﻫﺶ ﺩﺍﺩ ]‪[۱۰‬‬ ‫ﺍﺛﺒﺎﺕ ﻣﻲﺷﻮﺩ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻗﻮﺍﻋﺪ ﻛﺎﻫﺶﺩﻫﻨﺪﻩ ﻣﻲﺗﻮﺍﻥ ﺍﺯ ‪ KFDD‬ﺑﻪ ﻳﻚ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎ ﺍﺯ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﺑـﻮﻟﻲ‬ ‫ﺭﺳﻴﺪ ]‪.[۱۰‬‬ ‫‪ -۳-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭﺩﻭﻳﻲ ﭼﻨﺪ ﭘﺎﻳﺎﻧﻪﺍﻱ )‪ (MTBDD‬ﻳﺎ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺟﺒﺮﻱ )‪. (ADD‬‬ ‫ﭘﺲ ﺍﺯ ﺍﻳﻨﻜﻪ ﻋﺒﺎﺭﺍﺕ ﺑﻮﻟﻲ ﺗﻮﺳﻂ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺷـﺪﻧﺪ‪ .‬ﮔـﺎﻡ ﺑﻌـﺪﻱ ﺩﺭ ﺧﻼﺻـﻪ ﻛـﺮﺩﻥ‬ ‫‪۳۹‬‬ ‫ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ‪ ،‬ﺍﺭﺍﻳﻪ ﻣﺪﻟﻲ ﺑﺮﺍﻱ ﺗﻮﺍﺑﻊ ﺑﺎ ﺩﺍﻣﻨﻪ ﺑﻮﻟﻲ ﻭ ﺑﺮﺩ ﻏﻴﺮﺑﻮﻟﻲ ﻣﺎﻧﻨـﺪ ﺍﻋـﺪﺍﺩ ﺻـﺤﻴﺢ ﻳـﺎ ﺣﻘﻴﻘـﻲ‬ ‫ﻣﻲﺑﺎﺷﺪ]‪ .[۱۴ ،۱۳ ، ۱۲، ۱۱‬ﺍﻳﻦ ﮔﻮﻧﻪ ﺗﻮﺍﺑﻊ‪ ،‬ﺗﻮﺍﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﻧﺪ ﻭ ﺑﺴﻴﺎﺭ ﻛﺎﺭﺍﺗﺮ ﺍﺯ ﺗﻮﺍﺑﻊ ﺑـﻮﻟﻲ‬ ‫ﻣﻌﻤﻮﻝ ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﻛﻪ ﺍﺯ ﺟﻤﻠﻪ ﻛﺎﺭﺑﺮﺩﻫﺎﻱ ﺍﻳﻦ ﮔﻮﻧﻪ ﺗﻮﺍﺑﻊ ﻛﺎﺭ ﺑﺎ ﻣﺎﺗﺮﻳﺲ ﻭ ﺗﺤﻠﻴﻞ ﺳﻴﺴـﺘﻢ ﺩﺭ ﺳـﻄﺢ ﻛﻠﻤـﻪ‬ ‫ﻣﻲﺑﺎﺷﺪ]‪ .[۱۵‬ﻳﻜـﻲ ﺍﺯ ﺍﻭﻟـﻴﻦ ﻣـﺪﻟﻬﺎ ﺑـﺮﺍﻱ ﺍﻳﻨﮕﻮﻧـﻪ ﺗﻮﺍﺑـﻊ ﻣـﺪﻝ ‪Multi Terminal Binary ) MTBDD‬‬ ‫‪ ( Decision Diagram‬ﻳﺎ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭﺩﻭﻳﻲ ﭼﻨﺪ ﭘﺎﻳﺎﻧﻪﺍﻱ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۱-۳-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪MTBDD‬‬ ‫ﺩﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ‪ MTBDD‬ﻓﺮﺽ ﻣﻲﺷﻮﺩ ﻛﻪ ﺗﺎﺑﻊ ‪ f‬ﺑﻪ ﺻﻮﺭﺕ ‪ f : B m → Z‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻛﻪ ﻳﻚ ﺑﺮﺩﺍﺭ ﺑـﻮﻟﻲ‬ ‫ﺑﺎ ﻃﻮﻝ ‪ m‬ﺭﺍ ﺑﻪ ﻳﻚ ﻋﺪﺩ ﺻﺤﻴﺢ ﻣﺘﻨﺎﻇﺮ ﻣﻲﻛﻨﺪ‪ .‬ﺗـﺎﺑﻊ ‪ f‬ﻓﻀـﺎﻱ ‪ B m‬ﺭﺍ ﺑـﻪ ‪ N‬ﻣﺠﻤﻮﻋـﻪﻱ } ‪{S1 , S 2 ,..., S n‬‬ ‫ﺍﻓﺮﺍﺯ ﻣﻲﻛﻨﺪ‪ ،‬ﺑﻪ ﺻﻮﺭﺗﻲ ﻛﻪ } ‪ . S i = {x f ( x) = ni‬ﺍﮔﺮ ‪ f i‬ﺗﺎﺑﻊ ﻣﺸﺨﺼـﻪ ‪ Si‬ﺑﺎﺷـﺪ‪ ،‬ﺁﻧﮕـﺎﻩ ‪ f‬ﻳـﻚ ﻧﻤـﺎﻳﺶ‬ ‫‪N‬‬ ‫ﻧﺮﻣﺎﻝ‪ ٢٦‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﮔﺮ )‪ f(x‬ﺑﻪ ﺻﻮﺭﺕ ‪ ∑ f i ( x ). n i‬ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩﺷﻮﺩ‪ BDD ،‬ﺑﻪ ﺻـﻮﺭﺕ ﺩﻳـﺎﮔﺮﺍﻣﻲ ﺑـﺎ‬ ‫‪i =1‬‬ ‫ﺍﻋﺪﺍﺩ ﺻﺤﻴﺢ ﺩﺭ ﺑﺮﮔﻬﺎ ﺩﺭ ﻣﻲﺁﻳﺪ ﻛﻪ ﺑﻪ ﺁﻥ ‪ MTBDD‬ﻣـﻲﮔـﻮﻳﻴﻢ‪ .‬ﻫـﺮ ﻋﻤﻠﮕـﺮ ﺭﻳﺎﺿـﻲ ⊗ ﻣـﻲﺗﻮﺍﻧـﺪ ﺩﺭ‬ ‫‪ MTBDD‬ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺷﻮﺩ‪:‬‬ ‫) ‪h( x ) = f ( x ) ⊗ g ( x‬‬ ‫‪N′‬‬ ‫‪N‬‬ ‫‪= ∑ f i ( x).ni ⊗∑ g j ( x).n′j‬‬ ‫‪i =1‬‬ ‫‪j =1‬‬ ‫‪N′‬‬ ‫‪N‬‬ ‫) ‪= ∑∑ f i ( x)g j ( x)(ni ⊗ n′j‬‬ ‫‪i =1 j =1‬‬ ‫‪f i ( x) g j ( x)nk′′‬‬ ‫∨‬ ‫‪N ′′‬‬ ‫∑=‬ ‫‪k =1 ni ⊗n j = nk′′‬‬ ‫ﺩﺭ ﻧﺘﻴﺠﻪ ﻳﻚ ﺍﻟﮕﻮﺭﻳﺘﻢ ﺑﺎﺯﮔﺸﺘﯽ ﻣﺸﺨﺺ ﺑﺮﺍﻱ ﻃﺮﺍﺣﻲ ‪ MTBDD‬ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ ﻛﻪ ‪:‬‬ ‫ ﺍﮔﺮ ‪ f‬ﺑﺮﮒ ﺑﻮﺩ‪ f ،‬ﺭﺍ ﺑﻪ ﻋﻨﻮﺍﻥ ﻋﻤﻠﻮﻧﺪ ﺍﻭﻝ ﻋﻤﻠﮕﺮ ⊗ ﺑﺎ ﻫﺮ ﺑﺮﮒ ‪ g‬ﺗﺮﻛﻴﺐ ﻛﻨﻴﺪ‪.‬‬‫ ﺍﮔﺮ ‪ g‬ﺑﺮﮒ ﺑﻮﺩ‪ g ،‬ﺭﺍ ﺑﻪ ﻋﻨﻮﺍﻥ ﻋﻤﻠﻮﻧﺪ ﺩﻭﻡ ﻋﻤﻠﮕﺮ ⊗ ﺑﺎ ﻫﺮ ﺑﺮﮒ ‪ f‬ﺗﺮﻛﻴﺐ ﻛﻨﻴﺪ‪.‬‬‫‪Normal form 26‬‬ ‫‪۴۰‬‬ ‫ ‪ MTBDD‬ﻋﺒﺎﺭﺕ ‪ f ⊗ g‬ﻭﺍﺑﺴﺘﻪ ﺑﻪ ﺭﺍﺑﻄﻪﻱ ﺑﻴﻦ ‪ xj , xi‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺭﻭﺵ ﺳﺎﺧﺖ ﺁﻥ ﺩﺭ ﺷـﻜﻞ ‪۳-۳‬‬‫ﻧﺸﺎﻥ ﺩﺍﺩﻩﺷﺪﻩﺍﺳﺖ‪.‬‬ ‫ﺷﮑﻞ ‪ MTBDD -۳-۳‬ﺗﺎﺑﻊ ‪f‬ﻭ ‪ g‬ﻭ ﺗﺮﮐﻴﺐ ﺁﻧﻬﺎ ﺑﺮ ﺍﺳﺎﺱ ﺭﺍﺑﻄﻪﻱ ‪xj , xi‬‬ ‫ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﺻﻞ ﺑﻪ ﺻﻮﺭﺕ ﻛﺎﻫﺶ ﻳﺎﻓﺘـﻪ ﻧﻤـﻲﺑﺎﺷـﺪ ﻭ ﺑﺎﻳـﺪ ﻣﺮﺣﻠـﻪ ﮐﻤﻴﻨـﻪ ﺳـﺎﺯﻱ ﺭﻭﻱ ﺁﻥ ﺍﻋﻤـﺎﻝ ﺷـﻮﺩ‪.‬‬ ‫ﺍﻟﮕﻮﺭﻳﺘﻢ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺩﻗﻴﻘﹰﺎ ﻣﺎﻧﻨﺪ ﺭﻭﺵ ﺑﺮﻳﺎﻧﺖ ]‪ [۵‬ﺑﺮﺍﻱ ﺧﻼﺻﻪ ﺳﺎﺯﻱ ‪ BDD‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺗﻮﺍﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﺁﺭﺍﻳﻪ ﺍﺯ ‪ BDD‬ﻫﺎ ﻧﻴﺰ ﻧﺸﺎﻥ ﺩﺍﺩ‪،‬ﮐﻪ ﻫﺮﻳﻚ ﺍﺯ ‪ BDD‬ﻫﺎ ﻧﻤﺎﻳﻨﺪﻩﻱ‬ ‫ﻳﻚ ﺑﻴﺖ ﺩﺭ ﻧﻤﺎﻳﺶ ﺩﻭﺩﻭﻳﻲ ﺣﺎﺻﻞ ﺗﺎﺑﻊ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻭﻟﻲ ﺍﻳﻦ ﺭﻭﺵ ﺑﺴﻴﺎﺭ ﻫﺰﻳﻨﻪﺑﺮ ﻭ ﭘﺮﺣﺠﻢ ﺍﺳﺖ‪.‬‬ ‫ﻣﺜﺎﻝ ‪ :۲-۳‬ﺗﺎﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ ‪ f ( z, y) = 8 − 20 z + 2 y + 4 zy‬ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺍﺳﺖ‪ ،‬ﺟﺪﻭﻝ ﺩﺭﺳـﺘﻲ ﻭ ﻧﻤـﺎﻳﺶ‬ ‫‪ MTBDD‬ﺍﻳﻦ ﺗﺎﺑﻊ ﺑﻪ ﺻﻮﺭﺕ ﺷﻜﻞ ‪ ۴-۳‬ﺩﺭ ﻣﻲﺁﻳﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۴-۳‬ﺟﺪﻭﻝ ﺩﺭﺳﺘﯽ ﻭ ‪ MTBDD‬ﺗﺎﺑﻊ ‪[۱۲] f ( z, y ) = 8 − 20 z + 2 y + 4 zy‬‬ ‫ﺍﻣﺎ ﺍﻳﻦ ﻣﺪﻝ ﻧﻴﺰ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﺗﻮﺍﺑﻊ ﺑﺎ ﺩﺍﻣﻨـﻪ ﻏﻴﺮﺑـﻮﻟﻲ ﻛـﺎﺭﺁﻳﻲ ﻧـﺪﺍﺭﺩ‪ ،‬ﺯﻳـﺮﺍ ﺑﺎﻳـﺪ ﻣﺘﻐﻴﺮﻫـﺎ ﺭﺍ ﺑـﻪ ﺻـﻮﺭﺕ‬ ‫ﻣﺠﻤﻮﻋﻪﺍﻱ ﺍﺯ ﺑﻴﺘﻬﺎﻱ ﻧﻤﺎﻳﺶ ﺩﻭﺩﻭﻳﻲ ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﺁﻧﻬﺎ ﺩﺭﺁﻭﺭﺩ‪ .‬ﻧﻜﺘﻪ ﻣﻨﻔﻲ ﺩﻳﮕﺮ ﺍﻳﻦ ﻧﻤﺎﻳﺶ ﺭﺷﺪ ﻧﻤـﺎﻳﻲ‬ ‫‪۴۱‬‬ ‫ﺁﻥ ﺑﺎ ﺍﻓﺰﺍﻳﺶ ﺗﻌﺪﺍﺩ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۴-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭﺩﻭﻳﻲ ﺑﺎ ﻳﺎﻟﻬﺎﻱ ﻭﺯﻥ ﺩﺍﺭ‪(EVBDD) ٢٧‬‬ ‫ﻫﻤﺎﻧﻄﻮﺭ ﻛﻪ ﺩﺭ ﺑﺨﺶ ﻗﺒﻠﻲ ﺩﻳﺪﻳﻢ ﺩﺭ ‪ MTBDD‬ﻣﻘﺎﺩﻳﺮ ﺻﺤﻴﺢ ﺑﻪ ﺑﺮﮔﻬﺎ ﻧﺴﺒﺖ ﺩﺍﺩﻩ ﻣﻲﺷﺪ ﻭ ﺑﺮﺍﻱ ﻳﺎﻟﻬﺎﻱ‬ ‫ﮔﺮﺍﻑ ﻭﺯﻧﻲ ﻗﺮﺍﺭ ﺩﺍﺩﻩ ﻧﻤﻲﺷﺪ‪ .‬ﺩﺭ ﺩﻳﺎﮔﺮﺍﻣﻲ ﻛﻪ ﺩﺭ ﺍﻳﻦ ﺑﺨﺶ ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﺩ ﺑﺎ ﻭﺯﻥﺩﺍﺭﻛـﺮﺩﻥ ﻳﺎﻟﻬـﺎ ﺳـﻌﻲ‬ ‫ﺷﺪﻩ ﺍﺳﺖ ﺗﺎ ﺍﻧﺪﺍﺯﻩ ﮔﺮﺍﻑ ﺭﺍ ﻛﺎﻫﺶ ﺩﻫﻨﺪ‪ .‬ﺯﻳﺮﺍ ﺑﺮﺍﻱ ﺧﻼﺻﻪ ﺷﺪﻥ ‪ MTBDD‬ﺑﺎﻳﺪ ﻛـﻪ ﮔـﺮﻩﻫـﺎ ﺍﺯ ﺳـﻤﺖ‬ ‫ﺑﺮﮒ ﺑﺎ ﻳﻜﺪﻳﮕﺮ ﺗﺮﻛﻴﺐ ﺷﻮﻧﺪ‪ .‬ﻭﻟﻲ ﺩﺭ ﺻﻮﺭﺕ ﻭﺟﻮﺩ ﻳﻚ ﺭﻳﺸﻪ ﺑﺎ ﺗﻌﺪﺍﺩ ﺯﻳﺎﺩﻱ ﮔﺮﻩ ﺑﺮﮒ ﺍﺣﺘﻤﺎﻝ ﺗﺮﻛﻴـﺐ‬ ‫ﺷﺪﻥ ﺑﺮﮔﻬﺎ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺯﻳﺮﺩﺭﺧﺘﻬﺎﯼ ﮔﺮﺍﻑ ﻛﺎﻫﺶ ﻣﻲﻳﺎﺑﺪ‪ .‬ﺑـﻪ ﻋﺒـﺎﺭﺕ ﺩﻳﮕـﺮ ﺗﻌـﺪﺍﺩ ﮔـﺮﻩﻫـﺎﻱ ﺑـﺮﮒ ﺩﺭ‬ ‫ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺗﺎﺑﻊ ﺑﻪ ﺗﻌﺪﺍﺩ ﻣﻘﺎﺩﻳﺮﻳﻜﻪ ﺗﺎﺑﻊ ‪ f‬ﻣﻲﺗﻮﺍﻧﺪ ﻛﺴﺐ ﻛﻨﺪ‪ ،‬ﺑﺎﻗﻲ ﻣﻲﻣﺎﻧـﺪ‪ .‬ﻭﻟـﻲ ﺍﮔـﺮ ﺑﺘـﻮﺍﻧﻴﻢ ﺗﻤـﺎﻡ‬ ‫ﮔﺮﻩﻫﺎﻱ ﺑﺮﮒ ﺭﺍ ﺑﺎ ﻫﻢ ﻳﻜﻲ ﻛﻨﻴﻢ ﺍﺣﺘﻤﺎﻝ ﭘﻴﺪﺍﻛﺮﺩﻥ ﺯﻳﺮﺩﺭﺧﺖ ﻣﻌﺎﺩﻝ ﺍﻓﺰﺍﻳﺶ ﻣـﻲﻳﺎﺑـﺪ ﻭ ﺩﻳـﺎﮔﺮﺍﻡ ﺗﺼـﻤﻴﻢ‬ ‫ﻛﻮﭼﻜﺘﺮ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱-۴-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪EVBDD‬‬ ‫ﺩﺭ ‪ EVBDD‬ﻫﻤﺎﻧﻨﺪ ‪ MTBDD‬ﺍﻳـﻦ ﻓـﺮﺽ ﻭﺟـﻮﺩ ﺩﺍﺭﺩ ﻛـﻪ ﺗـﺎﺑﻊ ‪ f‬ﺑـﻪ ﺻـﻮﺭﺕ ‪ f : B m → Z‬ﺗﻌﺮﻳـﻒ‬ ‫ﻣﻲﺷﻮﺩ‪ .‬ﺣﺎﻝ ﻳﻚ ‪ EVBDD‬ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺗﻌﺮﻳﻒ ﻣﻲﺷﻮﺩ]‪:[۱۳، ۱۷، ۱۶‬‬ ‫‪ EVBDD‬ﻳﻚ ﮔﺮﺍﻑ ﺟﻬﺖ ﺩﺍﺭ ﺑﺪﻭﻥ ﺩﻭﺭ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺗﺎﺑﻊ ‪ f‬ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻧﻤﺎﻳﺶ ﻣﻲﺩﻫﺪ‪:‬‬ ‫ ﺗﻨﻬﺎ ﻳﻚ ﮔﺮﻩ ﺑﺮﮒ‪ ،‬ﺩﺭ ﻻﻳﻪ ﺻﻔﺮ ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﻛﻪ ﺑﺮﭼﺴﺐ ﺻﻔﺮ ﺩﺍﺭﺩ ﻭ ﺑﺎ ﻧﻤﺎﻳﺶ ‪ 0‬ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬‫ ﻫﺮ ﮔﺮﻩ ﻏﻴﺮ ﺑﺮﮒ ﺩﺭ ﻻﻳﻪ ‪ k‬ﺍﻡ ﺑﺎ >‪ <k‬ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﮔﺮﻩ ﺩﺍﺭﺍﻱ ﺩﻭ ﻓﺮﺯﻧﺪ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻫﺮ ﻓﺮﺯﻧﺪ‬‫ﻣﻌﺎﺩﻝ ﻳﻜﻲ ﺍﺯ ﺩﻭ ﻣﻘﺪﺍﺭﻱ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻣﺘﻐﻴﺮ ‪ xk‬ﻣـﻲﺗﻮﺍﻧـﺪ ﺑﺪﺳـﺖ ﺑﻴـﺎﻭﺭﺩ ﻛـﻪ ﺍﻳـﻦ ﺩﻭ ﻓﺮﺯﻧـﺪ ﺧـﻮﺩ‬ ‫ﮔﺮﻩﻫﺎﻳﻲ ﺩﺭ ﻻﻳﻪ ‪ n , l‬ﻛﻮﭼﻜﺘﺮ ﺍﺯ ‪ k‬ﻣﻲﺑﺎﺷﻨﺪ‪.‬‬ ‫‪Edged Value Binary Decision Diagram 27‬‬ ‫‪۴۲‬‬ ‫ ﻳﺎﻝ ﺍﻭﻝ ﺑﺎ ﻳﻚ ﻣﻘﺪﺍﺭ ﺻﺤﻴﺢ ﻭﺯﻥﺩﻫﻲ ﺷﺪﻩ ﺍﺳﺖ ﻭ ﻭﺯﻥ ﻳﺎﻝ ﺩﻭﻡ ﻫﻤﻴﺸﻪ ﺻﻔﺮ ﻣﻲﺑﺎﺷﺪ‪.‬‬‫ ﮔﺮﻩ ﺭﻳﺸﻪ ﺩﺍﺭﺍﻱ ﺗﻨﻬﺎ ﻳﻚ ﻳﺎﻝ ﻭﺭﻭﺩﻱ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺑﺎ ﻳﻚ ﻣﻘﺪﺍﺭ ﺻﺤﻴﺢ ﻭﺯﻥﺩﻫﻲ ﺷﺪﻩ ﺍﺳﺖ‪.‬‬‫‪-‬‬ ‫ﻗﻮﺍﻋﺪﻱ ﺑﺮﺍﻱ ﻳﻜﺘﺎﻛﺮﺩﻥ ﺍﻳﻦ ﮔﺮﺍﻑ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ ﻛﻪ ﺩﻗﻴﻘﹰﺎ ﻣﻨﻄﺒﻖ ﺑﺮ ﺭﻭﺷﻬﺎﻱ ﺧﻼﺻـﻪﺳـﺎﺯﻱ ‪BDD‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۱‬ﺍﮔﺮ ﺩﻭ ﮔﺮﻩ ﻭ ﺯﻳﺮﺩﺭﺧﺘﻬﺎﻱ ﺁﻧﻬﺎ ﻳﻜﺴﺎﻥ ﺑﺎﺷﺪ ﻳﻜﻲ ﺍﺯ ﺁﻥ ﺩﻭ ﮔﺮﻩ ﺣﺬﻑ ﻣﻲﺷﻮﺩ ﻭ ﻳـﺎﻝ ﺍﺷـﺎﺭﻩ‬ ‫ﻛﻨﻨﺪﻩ ﺑﻪ ﺁﻥ‪ ،‬ﺑﻪ ﺩﻳﮕﺮﻱ ﻣﺘﺼﻞ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۲‬ﺑﺎ ﺣﺬﻑ ﮔﺮﻩﻫﺎﻳﻲ ﻛﻪ ﺩﻭ ﺯﻳﺮﺩﺭﺧﺖ ﺁﻧﻬﺎ ﻣﻌﺎﺩﻝ ﻣﻲﺑﺎﺷﺪ ﺍﻓﺰﻭﻧﮕﻲ ﺭﺍ ﺍﺯ ﺑﻴﻦ ﻣﻲﺑﺮﻳﻢ‪.‬‬ ‫ﺗﺎﺑﻊ ﺗﺠﺰﻳﻪ ‪ EVBDD‬ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻗﺎﺑﻞ ﺑﻴﺎﻥ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻛﻪ ﺑﺎ ﺍﺟﺮﺍﻱ ﻳﻚ ﺍﻟﮕﻮﺭﻳﺘﻢ ﺑﺎﺯﮔﺸﺘﻲ‪ ،‬ﻛﻞ ﺩﺭﺧـﺖ‬ ‫ﻗﺎﺑﻞ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪0‬‬ ‫‪1‬‬ ‫) ‪f i +1 = xi f i + xi ( f i + wi‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ ‪ f i 0‬ﺗﺎﺑﻊ ﺑﻴﺎﻥ ﺷﺪﻩ ﺩﺭ ﻳـﺎﻝ ﺍﻭﻝ ﮔـﺮﻩ‪ f i1 ،‬ﺗـﺎﺑﻊ ﺑﻴـﺎﻥ ﺷـﺪﻩ ﺩﺭ ﻳـﺎﻝ ﺩﻭﻡ ﮔـﺮﻩ ﻭ ‪ wi‬ﻭﺯﻥ ﻳـﺎﻝ ﺩﻭﻡ‬ ‫ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﻣﺜـــﺎﻝ ‪ :۳-۳‬ﺷـــﻜﻞ ﺷـــﻤﺎﺭﻩ ‪ ۵-۳‬ﻧﺸـــﺎﻥ ﺩﻫﻨـــﺪﻩﻱ ﺟـــﺪﻭﻝ ﺩﺭﺳـــﺘﻲ ﻭ ‪ EVBDD‬ﻳﻜﺘـــﺎﻱ ﺗـــﺎﺑﻊ‬ ‫‪ f ( x2 , x1 , x0 ) = 4 x2 + 2 x1 + x0‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۵-۳‬ﺟﺪﻭﻝ ﺩﺭﺳﺘﯽ ﻭ ‪ EVBDD‬ﺗﺎﺑﻊ ‪f ( x2 , x1 , x0 ) = 4 x2 + 2 x1 + x0‬‬ ‫‪۴۳‬‬ ‫‪ -۵-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺩﻭﺩﻭﻳﻲ ﻣﻤﺎﻥ‪BMD ٢٨‬‬ ‫ﺩﻭ ﺩﻳﺎﮔﺮﺍﻡ ﺳﻄﺢ ﻛﻠﻤﻪﺍﻱ ﻛﻪ ﺩﺭ ﺩﻭ ﺑﺨﺶ ﭘﻴﺶ ﺑﻴﺎﻥ ﺷﺪﻧﺪ‪ ،‬ﻫﺮ ﺩﻭ ﺑﺮﺍﺳﺎﺱ ﺗﻮﺍﺑﻊ ﺗﺠﺰﻳﻪﺍﻱ ﻫﺴﺘﻨﺪ ﻛﻪ ﺗـﺎﺑﻊ‬ ‫ﺭﺍ ﺑﻪ ﺩﻭ ﻗﺴﻤﺖ ﺗﻘﺴﻴﻢ ﻣﻲﻛﻨﻨﺪ‪ .‬ﻗﺴﻤﺖ ﺍﻭﻝ ﺗﺎﺑﻊ ﺭﺍ ﺑﺎ ﺷﺮﻁ ﺻﻔﺮﺑﻮﺩﻥ ‪ x‬ﻭ ﻗﺴـﻤﺖ ﺩﻭﻡ ﺗـﺎﺑﻊ ﺭﺍ ﺑـﺎ ﺷـﺮﻁ‬ ‫ﺗﻮﺍﺑﻊﺗﺠﺰﻳﻪ‪ pointwise‬ﻣﻲﮔﻮﻳﻨـﺪ‪ .‬ﻧـﻮﻉ ﺩﻳﮕـﺮ ﺗﻮﺍﺑـﻊ‬ ‫ﻳﻚ ﺑﻮﺩﻥ ‪ x‬ﻣﺤﺎﺳﺒﻪ ﻣﻲﻛﻨﺪ‪ .‬ﺑﻪ ﺍﻳﻦ ﻧﻮﻉ ﺗﻮﺍﺑﻊِﺗﺠﺰﻳﻪ‪ِ ،‬‬ ‫ﺗﺠﺰﻳﻪ‪ ،‬ﺗﻮﺍﺑﻊ ﺗﺠﺰﻳﻪﻱ ﻣﻤﺎﻥ ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺩﻭ ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ ﺍﺯ ﺗﺠﺰﻳﻪ ﺗﺎﺑﻊ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺗﻮﺍﺑﻊ ﺑـﻪ ﺻـﻮﺭﺕ‬ ‫‪-۱‬ﻋﺒﺎﺭﺗﯽ ﻛﻪ ﻣﻘﺪﺍﺭ ﺗﺎﺑﻊ ﺭﺍ ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ‪ x‬ﺻﻔﺮ ﺑﺎﺷﺪ ﻣﺤﺎﺳﺒﻪ ﻣﻲﻛﻨﺪ ﻭ‪ -۲‬ﻋﺒﺎﺭﺗﯽ ﮐﻪ ﺗﻐﻴﻴـﺮﺍﺕ ﺗـﺎﺑﻊ ﺭﺍ‬ ‫ﺑﺮﺍﺛﺮ ﻳﻚ ﺷﺪﻥ ‪ x‬ﺑﺪﺳﺖ ﻣﻲﺁﻭﺭﺩ‪ ،‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺳﺎﺩﻩﺗﺮﻳﻦ ﺩﻳﺎﮔﺮﺍﻣﻲ ﻛﻪ ﺍﺯ ﺍﻳﻦ ﺗﺎﺑﻊ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﻛﻨﺪ‪ FDD ،‬ﻣﻲ‪-‬‬ ‫ﺑﺎﺷﺪ ﻛﻪ ﺩﺭ ﺑﺨﺸﻬﺎﯼ ﻗﺒﻠﯽ ﺑﺮﺭﺳﯽ ﺷﺪ‪ .‬ﻭﻟﻲ ﺑﺮﺍﻱ ﺗﻮﺍﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ ﺳﺎﺩﻩﺗﺮﻳﻦ ﺩﻳﺎﮔﺮﺍﻡ‪ BMD ،‬ﻣﻲﺑﺎﺷﺪ]‪.[۱۲‬‬ ‫‪ -۱-۵-۳‬ﺗﺎﺑﻊ ﺗﺠﺰﻳﻪ ﻣﻤﺎﻥ‬ ‫ﺩﺭ ﻣﻘﺎﺑﻞ ﺑﺴﻂ ﻣﻌﺮﻭﻑ ﺷﺎﻧﻮﻥ ﺩﺭ ﺗﻮﺍﺑﻊ ﺑﻮﻟﻲ‪ ،‬ﺑﺮﺍﻱ ﺗﻮﺍﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ ﺑﺴﻂ ﺑﻮﻝ – ﺷﺎﻧﻮﻥ‪ ٢٩‬ﺍﺭﺍﻳﻪ ﺷـﺪﻩ ﺍﺳـﺖ‬ ‫ﻛﻪ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺁﻥ ﻣﻲﺗﻮﺍﻥ ﻋﺒﺎﺭﺕ ﺷﺒﻪ ﺑﻮﻟﻲ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻋﺒﺎﺭﺕ ﺟﺒﺮﻱ ﻣﻌﺎﺩﻝ ﺑﺪﺳـﺖ ﺁﻭﺭﺩ]‪ .[۱۲‬ﺍﺯ‬ ‫ﺁﻧﺠﺎ ﻛﻪ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻭﺭﻭﺩﻱ ﺩﺭ ﺗﻮﺍﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ‪ ،‬ﻣﺘﻐﻴﺮﻫﺎﻱ ﺑـﻮﻟﻲ ﻫﺴـﺘﻨﺪ ﻭ ﺗﻨﻬـﺎ ﺩﻭ ﻣﻘـﺪﺍﺭ ﺻـﻔﺮ ﻭ ﻳـﻚ ﺭﺍ‬ ‫ﮐﺴﺐ ﻣﻲﮐﻨﻨﺪ‪ ،‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺩﺭ ﺍﻳﻦ ﺑﺴﻂ )‪ (1-x‬ﺟﺎﻳﮕﺰﻳﻦ ﻧﻘﻴﺾ ﻣﺘﻐﻴﺮ ‪ x‬ﺩﺭ ﺑﺴﻂ ﺷﺎﻧﻮﻥ ﺷﺪﻩ ﺍﺳـﺖ‪ .‬ﻋﺒـﺎﺭﺕ‬ ‫ﺑﻮﻟﻪ ﺷﺎﻧﻮﻥ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻧﻮﺷﺖ‪:‬‬ ‫‪f = (1 − x). f x + x. f x‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ * ﻭ ‪ +‬ﻧﻤﺎﻳﻨﺪﻩﻱ ﺿﺮﺏ ﻭ ﺟﻤﻊ ﺟﺒﺮﯼ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ﻣﺤﺎﺳﺒﻪﻱ ﺗﺎﺑﻊ ﻣﻤﺎﻥ ﺭﺍﺑﻄﻪﻱ ﺷﺎﻧﻮﻥ – ﺑﻮﻝ‬ ‫ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺑﺎﺯﻧﻮﻳﺴﻲ ﻣﻲﺷﻮﺩ‪:‬‬ ‫) ‪f = f x + x.( f x − f x‬‬ ‫&‪= f x + x. f x‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ &‪ f x‬ﻣﻤﺎﻥ ﺧﻄﻲ ‪ f‬ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ‪ x‬ﻧﺎﻡ ﺩﺍﺭﺩ‪ .‬ﺩﻟﻴﻞ ﺍﻳﻦ ﻧﺎﻣﮕﺬﺍﺭﻱ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﺍﮔﺮ ‪ f‬ﻳﻚ ﺗـﺎﺑﻊ ﺧﻄـﻲ‬ ‫‪Binary Moment Diagram 28‬‬ ‫‪Boole-Shanon 29‬‬ ‫‪۴۴‬‬ ‫ﺍﺯ ‪ x‬ﺑﺎﺷﺪ‪ f x& ،‬ﺿﺮﻳﺐ ‪ x‬ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪ .‬ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ﺣﺎﺻﻞ ﺗﺎﺑﻊ ﻓﻘﻂ ﺑـﺮﺍﯼ ﺩﻭ ﻣﻘـﺪﺍﺭ ‪ x‬ﻣﺤﺎﺳـﺒﻪ ﻣـﻲﺷـﻮﺩ‪،‬‬ ‫ﻣﻲﺗﻮﺍﻥ ﺭﺍﺑﻄﻪﻱ ﺑﻴﻦ ﺁﻧﻬﺎ ﺭﺍ ﺧﻄﻲ ﻓﺮﺽ ﻧﻤﻮﺩ‪ f x .‬ﻣﻤﺎﻥ ﺛﺎﺑﺖ ‪ f‬ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺯﻳﺮﺍ ﺍﻳـﻦ ﻗﺴـﻤﺖ ﺗـﺎﺑﻊ ﺑـﺎ‬ ‫ﺗﻐﻴﻴﺮ ‪ x‬ﻫﻴﭻ ﺗﻐﻴﻴﺮﻱ ﻧﻤﻲﻛﻨﺪ‪ ،‬ﻭﻟﻲ &‪ f x‬ﺑﻪ ﺻﻮﺭﺕ ﺧﻄﻲ ﺗﻐﻴﻴﺮ ﻣﻲﻛﻨﺪ‪.‬‬ ‫ﺭﺍﺑﻄﻪﻱ ﻣﻤﺎﻥ ﺩﺭ ﺗﺎﺑﻊ ﺑﻮﻟﻲ ﺑﻪ ﺻﻮﺭﺕ ﺑﺴﻂ ﺭﻳﺪ – ﻣﺎﻟﺮ ) ‪ f = f x ⊕ x.( f x ⊕ f x‬ﺩﺭ ﻣﻲﺁﻳﺪ‪ ،‬ﻛـﻪ ﺩﺭ ‪FDD‬‬ ‫ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻗﺮﺍﺭ ﮔﺮﻓﺖ‪.‬‬ ‫‪ -۲-۵-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪BMD‬‬ ‫ﺑــﺎ ﺍﺳــﺘﻔﺎﺩﻩ ﺍﺯ ﺗــﺎﺑﻊ ﺗﺠﺰﻳــﻪ ﻣﻤــﺎﻥ‪ ،‬ﺑــﺮﺍﯼ ﻫــﺮ ﺗــﺎﺑﻊ ﺷــﺒﻪ ﺑــﻮﻟﻲ‪ ،‬ﻣــﻲﺗــﻮﺍﻥ ﻳــﻚ ﻧﻤــﺎﻳﺶ ﺟﺪﻳــﺪ‬ ‫‪ Fn = Fn ( x1 , x2 ,..., xn ) = Fn−1 + xn Fn*−1‬ﺑﺮﺍﻱ ﺁﻥ ﺗﺎﺑﻊ ﺑﺪﺳﺖ ﺁﻭﺭﺩ‪.‬‬ ‫ﻣﺜــــﺎﻝ‪ :۴-۳‬ﺑــــﺮﺍﻱ ﭘﻴــــﺎﺩﻩ ﺳــــﺎﺯﻱ ﺗــــﺎﺑﻊ ﻣﺜــــﺎﻝ ‪ ۲-۳‬ﻣــــﻲﺗــــﻮﺍﻧﻴﻢ ﺗــــﺎﺑﻊ ﺭﺍ ﺑــــﻪ ﺻــــﻮﺭﺕ‬ ‫‪f ( z, y ) = 8(1 − y )(1 − z ) − 12(1 − y ) z + 10 y (1 − z ) − 6 yz = 8 y 0 z 0 − 20 y1 z 0 + 2 y 1 z 0 + 4 y1 z 1‬‬ ‫ﺑﺴﻂ ﺩﻫﻴﻢ‪ .‬ﺍﻳﻦ ﺑﺴﻂ ﺗﻚ ﺟﻤﻠﻪﺍﻱ ‪ f‬ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ ﻛﻪ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺑﺴﻂ ﺷﻜﻞ ﻧﻤـﻮﺩﺍﺭ ‪ BMD‬ﺗـﺎﺑﻊ ‪f‬‬ ‫ﺑﻪ ﺻﻮﺭﺕ ﺷﻜﻞ‪ ۶-۳‬ﺩﺭ ﻣﻲﺁﻳﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ BMD -۶-۳‬ﺗﺎﺑﻊ ‪[۱۲] f ( z, y ) = 8 − 20 z + 2 y + 4 zy‬‬ ‫ﺗﻔﺎﻭﺕ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ ﻭ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﻣﻤﺎﻥ ﺩﺭ ﻃﺮﻳﻘﻪ ﻣﺤﺎﺳﺒﻪﻱ ﺗﺎﺑﻊ ﺑﺮﺍﻱ ﻳﻚ ﻭﺭﻭﺩﯼ ﺧﺎﺹ ﻣﻲﺑﺎﺷﺪ‬ ‫ﺩﺭ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ ﻛﺎﻓﻲ ﺍﺳﺖ ﻣﺴﻴﺮ ﻳﻜﺘﺎﻳﻲ ﻛﻪ ﺍﺯ ﺭﻳﺸﻪ ﺑﻪ ﻳﻜﻲ ﺍﺯ ﺑﺮﮔﻬﺎ ﺑﺮ ﻣﺒﻨـﺎﻱ ﻣﻘـﺎﺩﻳﺮ ﻣﺘﻐﻴﺮﻫـﺎﻱ‬ ‫ﻭﺭﻭﺩﻱ ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ‪ ،‬ﭘﻴﻤﺎﻳﺶ ﺷﻮﺩ ﻭ ﺑﺮﺍﺳﺎﺱ ﻧﻮﻉ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻣﻘﺪﺍﺭ ﺗﺎﺑﻊ ﻣﺤﺎﺳﺒﻪ ﮔﺮﺩﺩ‪ .‬ﺑـﺮﺍﻱ ﻣﺜـﺎﻝ‬ ‫‪۴۵‬‬ ‫ﺩﺭ ‪ MTBDD‬ﻣﻘﺪﺍﺭ ﺑﺮﮒ ﺍﻧﺘﻬﺎﻳﻲ ﻣﺴﻴﺮ ﺣﺎﺻﻞ ﺗﺎﺑﻊ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻳﻌﻨﻲ ﺍﮔﺮ ﺩﺭ ﺩﻳﺎﮔﺮﺍﻡ ‪ MTBDD‬ﺑﺮﺍﻱ ﮔـﺮﻩ ‪v‬‬ ‫ﻭ ﻣﻘﺪﺍﺭﺩﻫﻲ ﻣﺘﻐﻴﺮﻫﺎﻱ ‪: φ‬‬ ‫‪φ (var(v )) = 0‬‬ ‫‪φ (var(v)) = 1‬‬ ‫‪v is leaf‬‬ ‫) ‪val (v‬‬ ‫‪‬‬ ‫) ‪MTBDDeval (v, φ ) = MTBDDeval (lo (v ), φ‬‬ ‫) ‪MTBDDeval ( hi (v ), φ‬‬ ‫‪‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ )‪ Lo(v‬ﻓﺮﺯﻧﺪ ﺍﻭﻝ ﻭ )‪ Hi(v‬ﻓﺮﺯﻧﺪ ﺩﻭﻡ ﮔﺮﻩ ‪ v‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻟﻴﻜﻦ ﺩﺭ ﺩﻳـﺎﮔﺮﺍﻡ ﻣﻤـﺎﻥ ﻣﺤﺎﺳـﺒﻪ ﻣﻘـﺪﺍﺭ‬ ‫ﻳﻚ ﺗﺎﺑﻊ ﻧﻴﺎﺯﻣﻨﺪ ﮔﺬﺷﺘﻦ ﺍﺯ ﭼﻨﺪ ﻣﺴﻴﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﯼ ﻣﺜـﺎﻝ ﺑـﺮﺍﯼ ﺩﻳﺎﮔﺮﺍﻣﻬـﺎﯼ ﺍﺯ ﻧـﻮﻉ ‪ BMD‬ﻭ ﺩﺭ ﺍﺯﺍﻱ‬ ‫ﻣﻘﺪﺍﺭﺩﻫﻲ ﺑﻪ ﻣﺘﻐﻴﺮﻫﺎﻱ ‪ φ‬ﺩﺍﺭﻳﻢ ‪:‬‬ ‫‪v is leaf‬‬ ‫‪φ (var(v)) = 0‬‬ ‫‪φ (var(v)) = 1‬‬ ‫) ‪val (v‬‬ ‫‪‬‬ ‫) ‪BMDeval (v,φ ) =  BMDeval (lo(v), φ‬‬ ‫) ‪ BMDeval (lo(v), φ ) + BMDeval ( hi (v), φ‬‬ ‫‪‬‬ ‫‪ -۶-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭ ﺭﮔﻪ‪HDD ٣٠‬‬ ‫ﺩﺭ ﺣﺎﻟﺖ ﻛﻠﻲ ﺛﺎﺑﺖ ﻣﻲﺷﻮﺩ ﻛﻪ ﺍﻧﺪﺍﺯﻩﻱ ‪ BMD‬ﻫﻤﻴﺸﻪ ﺍﺯ ‪ MTBDD‬ﻛﻮﭼﻜﺘﺮ ﻧﻴﺴﺖ‪ .‬ﺣﺎﻟﺖ ﺑـﻮﻟﻲ ‪BMD‬‬ ‫ﻳﻌﻨﯽ ‪ FDD‬ﻭ ﺣﺎﻟﺖ ﺑﻮﻟﯽ ‪ BDD ،MTBDD‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﻲﺗﻮﺍﻥ ﺛﺎﺑﺖ ﻛﺮﺩ ﻛﻪ ‪ FDD‬ﻳـﻚ ‪ FDD‬ﺑﺮﺍﺑـﺮ ﺑـﺎ‬ ‫‪BDD‬ﺗــﺎﺑﻊ ﺍﻭﻟﻴــﻪ ﻣــﻲﺑﺎﺷــﺪ‪ .‬ﺑﻨــﺎﺑﺮﺍﻳﻦ ﺑــﺮﺍﻱ ﻫــﺮ ﺗــﺎﺑﻊ ‪ f‬ﻣــﻲﺗــﻮﺍﻥ ﻳــﻚ ﺗــﺎﺑﻊ ‪ f ′‬ﺗﻌﺮﻳــﻒ ﻛــﺮﺩ ﻛــﻪ‬ ‫‪ . BDD f ′ < FDD f‬ﺑﻨﺎﺑﺮﺍﻳﻦ ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ‪ KFDD‬ﺑﺮﺍﺳﺎﺱ ‪ BDD‬ﻭ ‪ FDD‬ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺍﺳﺖ ﻣﻌﺎﺩﻝ ﺁﻥ‬ ‫ﺑﺮﺍﻱ ‪ BMD‬ﻭ ‪ MTBDD‬ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﻭ ﺭﮔﻪ ﻧﺎﻡ ﺩﺍﺭﺩ‪.‬‬ ‫‪ -۱-۶-۳‬ﺗﺸﺎﺑﻪ ‪ MTBDD‬ﻭ ‪BMD‬‬ ‫ﻫﻤﺎﻥﻃﻮﺭ ﻛﻪ ﺩﺭ ﺑﺨﺶ ﻗﺒﻠﻲ ﮔﻔﺘﻪ ﺷﺪ‪ ،‬ﺗﺎﺑﻊ ﺗﺠﺰﻳﻪ ﻣﻤﺎﻥ ﺑـﻪ ﺻـﻮﺭﺕ ‪ f = f 0 + xf ′‬ﻣـﻲﺑﺎﺷـﺪ ﻛـﻪ ﺩﺭ ﺁﻥ‬ ‫‪ . f ′ = f1 − f 0‬ﺑﻴﻦ ﺍﻳﻦ ﺭﺍﺑﻄﻪ ﻭ ﻣﻌﻜﻮﺱ ﺑﺴﻂ ﺩﻳﺪ ﻣﺎﻟﺮ ﺍﺭﺗﺒﺎﻁ ﻧﺰﺩﻳﻜﻲ ﻭﺟﻮﺩ ﺩﺍﺭﺩ]‪ .[۱۸‬ﻣﺎﺗﺮﻳﺲ ﻣﻌﻜﻮﺱ‬ ‫‪Hybrid Decision Diagram 30‬‬ ‫‪۴۶‬‬ ‫ﺑﺴﻂ ﺭﻳﺪ ﻣﺎﻟﺮ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﺑﺎﺯﮔﺸﺘﻲ ﺯﻳﺮ ﺗﻌﺮﻳﻒ ﻣﻲﻛﻨﻨﺪ‪:‬‬ ‫‪ S‬‬ ‫‪S n =  n −1‬‬ ‫‪ − S n−1‬‬ ‫‪0 ‬‬ ‫‪‬‬ ‫‪S n −1 ‬‬ ‫ﻛﻪ ﻫﻤﺎﻧﻨﺪ ﻣﺎﺗﺮﻳﺲ ﻣﺪﻝ ‪ MTBDD‬ﻣﻲ ﺑﺎﺷـﺪ‪ .‬ﻓـﺮﺽ ﻛﻨﻴـﺪ ‪ I ∈ B n‬ﻧﻤـﺎﻳﺶ ﺑـﻮﻟﻲ ﻣﻘـﺪﺍﺭ ‪ i‬ﺑﺎﺷـﺪ‪ .‬ﺗـﺎﺑﻊ‬ ‫‪S0 = 1‬‬ ‫‪ f : B n → Z‬ﻣﻲﺗﻮﺍﻧﺪ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﺑﺮﺩﺍﺭ ﻛﻪ ‪ i‬ﺍﻣﻴﻦ ﻋﻨﺼﺮ ﺁﻥ ﺑﺮﺍﺑﺮ )‪ f(I‬ﺍﺳﺖ‪ ،‬ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩﺷـﻮﺩ‪ .‬ﺣـﺎﻝ‬ ‫ﺍﮔﺮ ﺍﻳﻦ ﺑﺮﺩﺍﺭ ﺭﺍ ﻧﻤﺎﻳﻨﺪﻩ ﺗﺎﺑﻊ ‪ f‬ﺑﺪﺍﻧﻴﻢ‪ .‬ﻣﻲﺗﻮﺍﻥ ﺗﺒﺪﻳﻞ ﻣﻌﻜﻮﺱ ﺑﺴﻂ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ ﺭﺍ ﺑﺎ ﺿﺮﺏ ﻣـﺎﺗﺮﻳﺲ ﺗﺒـﺪﻳﻞ‬ ‫ﺩﺭ ﺑﺮﺩﺍﺭ ﺑﺪﺳﺖ ﺑﻴﺎﻭﺭﻳﻢ ‪ . fˆ = S × f‬ﺑﺎ ﺍﺳﺘﻘﺮﺍ ﺛﺎﺑﺖ ﻣﻲﺷﻮﺩ ﻛﻪ ‪ MTBDD‬ﻫﺮ ﺗﺎﺑﻊ ﺑﺎ ‪ BMD‬ﻫﻤـﺎﻥ ﺗـﺎﺑﻊ‬ ‫ﺍﻳﺰﻭﻣﻮﺭﻓﻴﮏ ﻣﻲﺑﺎﺷﺪ]‪.[۱۸‬‬ ‫ﺗﻌﺮﻳﻒ‪ :‬ﺿﺮﺏ ﻛﺮﻭﻧﻜﺮ ﺩﻭ ﻣﺎﺗﺮﻳﺲ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺗﻌﺮﻳﻒ ﻣﻲﺷﻮﺩ‪:‬‬ ‫‪ a11 L a1m ‬‬ ‫‪ a11 B L a1m B ‬‬ ‫‪‬‬ ‫‪‬‬ ‫‪‬‬ ‫‪‬‬ ‫‪A⊗ B =  M O M ⊗ B =  M‬‬ ‫‪O‬‬ ‫‪M ‬‬ ‫‪a‬‬ ‫‪‬‬ ‫‪a B L a B‬‬ ‫‪nm ‬‬ ‫‪ n1 L a nm ‬‬ ‫‪ n1‬‬ ‫ﺣــﺎﻝ ﻣــﻲﺗــﻮﺍﻧﻴﻢ ﻣــﺎﺗﺮﻳﺲ ‪ n×n‬ﺗﺒ ـﺪﻳﻞ ﻣﻌﻜــﻮﺱ ﺭﻳــﺪ‪-‬ﻣــﺎﻟﺮ ﺭﺍ ﺑــﻪ ﺻــﻮﺭﺕ ﺣﺎﺻﻠﻀــﺮﺏ ﻛﺮﻭﻧﻜــﺮ ‪n‬‬ ‫ﻣﺎﺗﺮﻳﺲ‪۲*۲‬ﺗﺒﺪﻳﻞ ﻛﺮﺩ‪:‬‬ ‫‪0   1 0‬‬ ‫‪ 1 0‬‬ ‫‪ 1 0‬‬ ‫‪ = ‬‬ ‫‪ ⊗ S n −1 = ‬‬ ‫‪ ⊗ ... ⊗ ‬‬ ‫‪‬‬ ‫‪S n −1   − 1 1 ‬‬ ‫‪ −1 1‬‬ ‫‪ −1 1‬‬ ‫‪ S‬‬ ‫‪S n =  n −1‬‬ ‫‪ − S n−1‬‬ ‫ﺣﺎﻝ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺟﺎﻱ ﺗﺒﺪﻳﻞ ﻣﻌﻜﻮﺱ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ‪ ،‬ﺍﺯ ﻫﺮ ﻣﺎﺗﺮﻳﺲ ﺗﺒـﺪﻳﻞ ﺩﻳﮕـﺮﻱ ﻛـﻪ ﺍﺯ ﺿـﺮﺏ ﻛﺮﻭﻧﻜـﺮ ‪n‬‬ ‫ﻣﺎﺗﺮﻳﺲ ‪ ۲ِ *۲‬ﻏﻴﺮﺗﻜﻴﻦ‪ ،‬ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ ﺍﺳﺘﻔﺎﺩﻩ ﮐﺮﺩ‪ ،‬ﻛﻪ ﻣﺎﺗﺮﻳﺲ ﺭﻳﺪ‪-‬ﻣﺎﻟﺮ ﺩﺭﺟﻪ ‪ n‬ﻭ ﻣﺎﺗﺮﻳﺲ ﻭﺍﻟﺶ ﺍﺯ ﺍﻳـﻦ‬ ‫ﺗﺒﺪﻳﻠﻬﺎ ﻣﻲﺑﺎﺷﺪ]‪.[۱۸‬‬ ‫‪ -۲-۶-۳‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪HDD‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺨﺶ ﻗﺒﻞ ﮔﻔﺘﻪ ﺷﺪ‪ ،‬ﮐﻠﻴﻪﻱ ﺗﺒـﺪﻳﻠﻬﺎﻳﻲ ﮐـﻪ ﺑـﺎ ﺿـﺮﺏ ﻛﺮﻭﻧﻜـﺮ ‪ n‬ﻣـﺎﺗﺮﻳﺲ ﻳﻜﺴـﺎﻥ‪۲*۲‬‬ ‫ﺑﺪﺳﺖﻣﻲﺁﻳﺪ‪ ،‬ﻳﮏ ﻧﻤﺎﻳﺶ ﻳﮑﺘﺎ ﺍﺯ ﺗﻮﺍﺑﻊ ﺷﺒﻪﺑﻮﻟﯽ ﺗﻮﻟﻴﺪ ﻣﻲﮐﻨﻨﺪ‪ .‬ﺣﺎﻝ ﺍﮔﺮ ﺑﻪ ﺟـﺎﻱ ﻣﺎﺗﺮﻳﺴـﻬﺎﻱ ﻳﻜﺴـﺎﻥ ﺍﺯ‬ ‫ﻣﺎﺗﺮﻳﺴﻬﺎﻱ ﻣﺘﻔﺎﻭﺕ ﺍﺳﺘﻔﺎﺩﻩ ﺷﻮﺩ‪ ،‬ﻫﻨﻮﺯ ﻳﻚ ﺗﺒﺪﻳﻞ ﻳﻜﺘﺎ ﺑﺮﺍﻱ ﺗﺎﺑﻊ ﻣﻮﺭﺩﻧﻈﺮ ﺧﻮﺩ ﺑﺪﺳـﺖ ﺧﻮﺍﻫـﺪ ﺁﻣـﺪ‪ .‬ﺑـﺎ‬ ‫‪۴۷‬‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺭﻭﺵ ﻣﻲﺗﻮﺍﻥ ﺍﻧﺪﺍﺯﻩﻱ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺭﺍ ﺗﺎ ﺣﺪ ﺯﻳﺎﺩﻱ ﻛﺎﻫﺶ ﺩﺍﺩ‪ .‬ﺍﺯ ﺁﻧﺠﺎ ﻛـﻪ ﻫﻨـﻮﺯ ﻫـﻴﭻ‬ ‫ﺍﻟﮕﻮﺭﻳﺘﻢ ﻣﻜﺎﺷﻔﻪﺍﻱ ﺑﺮﺍﻱ ﺑﺪﺳﺖﺁﻭﺭﺩﻥ ﺗﺒﺪﻳﻞ ﻛﺮﻭﻧﻜﺮ ﺩﻭﺭﮔﻪ ﻭﺟﻮﺩ ﻧﺪﺍﺭﺩ‪ .‬ﺍﺯ ﺍﻟﮕﻮﺭﻳﺘﻤﻬـﺎ ﺣـﺮﻳﺺ ﺑـﺮﺍﻱ‬ ‫ﻛﻮﭼﻚﻛﺮﺩﻥ ﺍﻧﺪﺍﺯﻩﻱ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ ﺑﻪ ﺍﻳﻦ ﺻﻮﺭﺕ ﻛﻪ ﻣﺎﺗﺮﻳﺴﻬﺎﻱ ‪ ۲*۲‬ﺗﻨﻬﺎ ﺑـﺎ ﺍﻋﻀـﺎﻱ‬ ‫ﻣﺠﻤﻮﻋﻪ}‪ {0,1,−1‬ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ‪ ،‬ﺑﻨﺎﺑﺮﺍﻳﻦ ‪ ۶‬ﻣﺎﺗﺮﻳﺲ ﻗﺎﺑﻞ ﺑﺮﺭﺳﻲ ﻭﺟﻮﺩ ﺩﺍﺭﺩ‪ .‬ﺩﺭ ﻣﺮﺣﻠـﻪﻱ ﺍﺿـﺎﻓﻪ ﻛـﺮﺩ ِﻥ‬ ‫ﻳﻚ ﻣﺘﻐﻴﺮ ﺟﺪﻳﺪ‪ ،‬ﻫﻤﻪ ﺍﻳﻦ ‪ ۶‬ﻣﺎﺗﺮﻳﺲ ﺁﺯﻣﺎﻳﺶ ﻣﻲﺷﻮﺩ ﻭ ﻫﺮﻛﺪﺍﻡ ﻛﻪ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻛﻮﭼﻜﺘﺮﻱ ﺗﻮﻟﻴﺪ ﻛﺮﺩ‪،‬‬ ‫ﺩﺭ ﻣﺎﺗﺮﻳﺲ ﺗﺒﺪﻳﻞ‪ ،‬ﺿﺮﺏﻛﺮﻭﻧﻜﺮ ﻣﻲﺷﻮﺩ‪ .‬ﺩﻳﺎﮔﺮﺍﻡ ﺣﺎﺻﻞ ‪ HDD‬ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﺭﻭﺵ ﺣﺘﻲ ﺍﺯ ‪BDD‬‬ ‫ﻱ ﻛﻪ ﺑﺎ ﻛﻤﻚ ﺭﻭﺵ ﻣﺮﺗﺐ ﺳﺎﺯﻱ ﻣﺘﻐﻴﺮ ﺑﻪ ﺻﻮﺭﺕ ﭘﻮﻳﺎ ﺗﻮﻟﻴﺪ ﺷﺪﻩ ﺍﺳﺖ‪ ،‬ﺩﻳﺎﮔﺮﺍﻡ ﻛﻮﭼﻜﺘﺮﻱ ﻣﻲﺳﺎﺯﺩ‪.‬‬ ‫‪ -۷-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﻣﻤﺎﻥ ﺩﻭﺩﻭﻳﻲ ﺿﺮﺑﻲ )‪(*BMD‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺨﺶ ‪ EVBDD‬ﮔﻔﺘﻪ ﺷﺪ ﻗـﺮﺍﺭﺩﺍﺩﻥ ﻣﻘـﺎﺩﻳﺮ ﺻـﺤﻴﺢ ﺩﺭ ﺑﺮﮔﻬـﺎﻱ ﻳـﻚ ﺩﻳـﺎﮔﺮﺍﻡ ﻣـﺎﻧﻊ ﺍﺯ‬ ‫ﺧﻼﺻﻪ ﺷﺪﻥ ﺁﻥ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﻣﺴﺎﻟﻪ ﺩﺭ ﺩﻳﺎﮔﺮﺍﻡ ﻣﻤﺎﻥ ﺩﻭﺩﻭﻳﻲ ﻧﻴﺰ ﻭﺟﻮﺩ ﺩﺍﺭﺩ‪ .‬ﺩﺭ ﻧﺘﻴﺠـﻪ ﺑـﺮﺍﻱ ﺭﻓـﻊ ﺍﻳـﻦ‬ ‫ﻣﺸﻜﻞ ﻭ ﺟﻠﻮﮔﻴﺮﻱ ﺍﺯ ﺭﺷﺪ ﻧﻤﺎﻳﻲ ‪ BMD‬ﻧﻮﻉ ﺩﻳﮕﺮﻱ ﺍﺯ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺍﺳـﺖ ﻛـﻪ ﺩﺭ ﺁﻥ ﺍﺯ‬ ‫ﻳﺎﻟﻬﺎﻱ ﻭﺯﻧﺪﺍﺭ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱-۷-۳‬ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ‪*BMD‬‬ ‫ﻫﻤﺎﻧﻄﻮﺭ ﻛﻪ ﺩﺭ ﺑﺨﺶ ‪ BMD‬ﮔﻔﺘﻪ ﺷﺪ ‪ BMD‬ﻧﻪ ﺗﻨﻬﺎ ﺑﺮﺍﻱ ﺗﻮﺍﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ ﺑﻠﻜـﻪ ﺑـﺮﺍﻱ ﺗﻮﺍﺑـﻊ ﺧﻄـﻲ ﻧﻴـﺰ‬ ‫ﻛﺎﺭﺑﺮﺩ ﺩﺍﺭﺩ‪ ،‬ﺑﺮﺍﻱ ﺗﻌﻴﻴﻦ ﻣﻘﺪﺍﺭﯼ ﻛﻪ ﺩﺭ ﺑﺮﮒ ﺍﻧﺘﻬﺎﻳﻲ ﻫـﺮ ﻣﺴـﻴﺮ ‪ BMD‬ﻗـﺮﺍﺭ ﺩﺍﺭﺩ‪ ،‬ﺩﺭ ‪ *BMD‬ﺗﻤـﺎﻡ ﻭﺯﻥ‬ ‫ﻳﺎﻟﻬﺎﻱ ﻣﻮﺟﻮﺩ ﺩﺭ ﻣﺴﻴﺮ ﺩﺭ ﻫﻢ ﺿﺮﺏ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫ﺑــﺮﺍﻱ ﻣﺤﺎﺳــﺒﻪ ﺗــﺎﺑﻊ ‪) f‬ﻣﻌــﺎﺩﻝ ﻳــﺎﻟﻲ ﺑــﺎ ﻭﺯﻥ ‪ m‬ﻛــﻪ ﺑــﻪ ﮔــﺮﻩ ‪ v‬ﺍﺷــﺎﺭﻩ ﻣــﻲﻛﻨــﺪ( ﺍﺯ ﺭﺍﺑﻄــﻪﻱ‬ ‫))‪ f = m( f lo (v) + xf hi (v‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﻛﻪ ﺩﺭ ﺁﻥ )‪ f lo (v‬ﺗﺎﺑﻊ ﻣﻌﺎﺩﻝ ﻳﺎﻝ ﺍﻭﻝ ﮔـﺮﻩ ‪ v‬ﻭ )‪ f hi (v‬ﺗـﺎﺑﻊ‬ ‫ﻣﻌﺎﺩﻝ ﻳﺎﻝ ﺩﻭﻡ ﮔﺮﻩ ‪ v‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪۴۸‬‬ ‫ﻣﺜﺎﻝ ‪ :۵-۳‬ﺩﻭ ﻧﻤﻮﻧﻪ ﺍﺯ ‪ *BMD‬ﺗﺎﺑﻊ ‪ f ( x, y, z ) = 8 − 20z + 2 y + 4 yz + 12 x + 24xz + 15xy‬ﺩﺭ ﺷـﻜﻞ ‪-۳‬‬ ‫‪ ۷‬ﺭﺳﻢ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﻣﺸﺎﻫﺪﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺩﺭ ‪ BMD‬ﺣﻘﻴﻘﻲ ﺿﺮﺍﻳﺐ ﺭﻭﻱ ﻳﺎﻟﻬﺎ ﻣﻲﺗﻮﺍﻧﻨـﺪ ﻣﻘـﺪﺍﺭ‬ ‫ﻏﻴﺮﺻﺤﻴﺢ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ BMD -۷-۳‬ﺑﺎﺿﺮﺍﻳﺐ ﺻﺤﻴﺢ ﻭ ﺣﻘﻴﻘﻲ ﺗﺎﺑﻊ ‪f ( x, y, z ) = 8 − 20 z + 2 y + 4 yz + 12 x + 24 xz + 15xy‬‬ ‫ﺍﻳﻦ ﻧﮑﺘﻪ ﻗﺎﺑﻞ ﺗﻮﺟﻪ ﻣﻲﺑﺎﺷﺪ ﮐﻪ ‪ BMD‬ﺑﺎ ﺿﺮﺍﻳﺐ ﺻﺤﻴﺢ ﻓﻘﻂ ﺗﻮﺍﺑﻊ ﺻـﺤﻴﺢ ﺭﺍ ﻣـﻲﭘـﺬﻳﺮﺩ‪ .‬ﺩﺭ ﻋﺒﺎﺭﺗﻬـﺎﻱ‬ ‫‪ 2 y + 4 yz‬ﻭ ‪ 12 x + 24 xz‬ﻋﺒﺎﺭﺕ ‪ 1+2z‬ﻗﺎﺑﻞ ﻓﺎﻛﺘﻮﺭﮔﻴﺮﻱ ﻣﻲ ﺑﺎﺷﺪ‪ .‬ﻭﻟﻲ ‪ BMD‬ﻗﺎﺑﻠﻴﺖ ﻓﺎﻛﺘﻮﺭﮔﻴﺮﻱ ﺍﻳﻦ‬ ‫ﻋﺒﺎﺭﺕ ﺭﺍ ﻧﺪﺍﺭﺩ‪ .‬ﻭﻟﻲ ﺩﺭ ‪ *BMD‬ﺍﻳﻦ ﻋﻤﻞ ﻗﺎﺑﻞ ﺍﻧﺠﺎﻡ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ‪ *BMD‬ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﻳﻜﺴﺎﻧﻲ ﻭﺟـﻮﺩ‬ ‫ﻧﺪﺍﺭﺩ ﻭﻟﻲ ﺑﺎ ﮔﺬﺍﺷﺘﻦ ﻳﻚ ﺷﺮﻁ ﻣﻲﺗﻮﺍﻥ ﺁﻥ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎ ﺩﺭ ﺁﻭﺭﺩ‪ .‬ﺑﺮﺍﻱ ﻧﻤﻮﻧـﻪ ﺩﺭ ﻣﺜـﺎﻝ‬ ‫‪ ۵-۳‬ﺑﺮﺍﻱ ‪ BMD‬ﺍﻭﻝ ﺷﺮﻁ ﻳﻚ ﺑﻮﺩﻥ ﻭﺯﻥ ﻳﺎﻝ ﺍﻭﻝ ﻭ ﺑﺮﺍﻱ ‪ BMD‬ﺩﻭﻡ ﺷﺮﻁ ﺻﺤﻴﺢ ﺑﻮﺩﻥ ﺿﺮﺍﻳﺐ ﺑﺮﻗﺮﺍﺭ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ *BMD .‬ﻗﺎﺑﻠﻴﺖ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺗﻮﺍﺑﻊ ﺟﺒﺮﻱ ﺭﺍ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻭﻟﻲ ﺑـﻪ ﻣـﺎ ﺍﻣﻜـﺎﻥ ﭘﻴـﺎﺩﻩﺳـﺎﺯﻱ ﺗﻮﺍﺑـﻊ‬ ‫ﺟﺒﺮﻱ ﺑﺎ ﺗﻮﺍﻥ ﺑﺰﺭﮔﺘﺮ ﺍﺯ ﻳﻚ ﺭﺍ ﻧﻤﻲﺩﻫﺪ‪.‬‬ ‫‪ -۸-۳‬ﺩﻳﺎﮔﺮﺍﻡ ﻣﻤﺎﻥ ﺩﻭﺩﻭﻳﻲ ﺿﺮﺑﻲ ﻛﺮﺍﻧﻜﺮ ‪K * BMD‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺑﺮﺍﻱ ‪ FDD‬ﻳﻚ ﮔﺴﺘﺮﺵﻳﺎﻓﺘـﻪ ‪ KFDD‬ﺍﺭﺍﻳـﻪ ﺷـﺪ ﻣـﻲﺗـﻮﺍﻥ ﺑـﺮﺍﻱ ﻣـﺪﻝ ‪ BMD‬ﻧﻴـﺰ ﻣـﺪﻝ‬ ‫‪ K*BMD‬ﺭﺍ ﺍﺭﺍﻳﻪ ﻛﺮﺩ]‪ ،[۱۹‬ﺩﺭ ﺍﻳﻦ ﻣﺪﻝ ﻫﺮ ﻳﺎﻝ ﺑﺎ ﺩﻭ ﻣﻘﺪﺍﺭ ﻋﺮﺽﺍﺯﻣﺒﺪﺍ ﻭ ﺿﺮﻳﺐ ﻭﺯﻥﺩﻫـﻲ ﻣـﻲﺷـﻮﻧﺪ‪.‬‬ ‫ﻳﺎﻝ ﺍﺷﺎﺭﻩ ﻛﻨﻨﺪﻩ ﺑﻪ ﮔﺮﻩ ‪ v‬ﻛﻪ ﺳﺎﺯﻧﺪﻩﻱ ﺗﺎﺑﻊ ‪ f‬ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺑﻪ ﺻﻮﺭﺕ ‪ (a, m), f‬ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﻛـﻪ ‪m‬‬ ‫‪۴۹‬‬ ‫ﺿﺮﻳﺐ ﻭ‪ a‬ﻋﺮﺽﺍﺯﻣﺒﺪﺍ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻫﺮ ﮔﺮﻩ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺗﻮﺍﺑﻊ ﺗﺠﺰﻳﻪ ﺯﻳﺮ ﺑﻪ ﺩﻭ ﮔﺮﻩ ﺍﺷﺎﺭﻩ ﻣﻲﮐﻨﺪ‪.‬‬ ‫‪ -۱‬ﺗﺠﺰﻳﻪ ﺷﺎﻧﻮﻥ‪:‬‬ ‫))‪(a, m), f = a + m((1 − x) f lo (v) + xf hi (v‬‬ ‫‪ -۲‬ﺗﺠﺰﻳﻪ ﺩﺍﻭﻳﻮ ﻣﺜﺒﺖ‪(a, m), f = a + m( f lo (v) + xf hi (v)) :‬‬ ‫‪ -۳‬ﺗﺠﺰﻳﻪ ﺩﺍﻭﻳﻮ ﻣﻨﻔﻲ‪(a, m), f = a + m( f lo (v) + (1 − x) f hi (v)) :‬‬ ‫ﺑﺮﺍﻱ ﻳﻜﺘﺎﻛﺮﺩﻥ ﻧﻤﺎﻳﺶ ‪ K*BDD‬ﺷﺮﺍﻳﻂ ﺯﻳﺮ ﺍﻋﻤﺎﻝ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱‬ﺗﻨﻬﺎ ﻳﻚ ﮔﺮﻩ ﺑﺮﮒ ﺑﺎ ﻣﻘﺪﺍﺭ ﺻﻔﺮ ﺩﺭ ﮔﺮﺍﻑ ﻭﺟﻮﺩ ﺩﺍﺭﺩ‪.‬‬ ‫‪ -۲‬ﻳﺎﻝ ﺍﻭﻝ ﻫﺮ ﮔﺮﻩ ﺩﺍﺭﺍﻱ ﻋﺮﺽ ﺍﺯ ﻣﺒﺪﺍ ﺻﻔﺮ ﻭ ﺿﺮﻳﺐ ﻳﻚ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۳‬ﺍﮔﺮ ‪ f lo (v) = 0‬ﺑﺎﺷﺪ‪ ،‬ﺿﺮﻳﺐ ﻳﺎﻝ ﺩﻭﻡ ﻳﻚ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪ .‬ﺩﺭ ﺍﻳﻦ ﮔﻮﻧﻪ ﻣﻮﺍﺭﺩ ﺍﮔﺮ ﻳﺎﻝ ﺩﻭﻡ ﺑﻪ ﻳـﻚ ﺑـﺮﮒ‬ ‫ﺧﺘﻢ ﻣﻲﺷﺪ ﻋﺮﺽ ﺍﺯ ﻣﺒﺪﺍ ﻳﺎﻝ ﺑﺮﺍﺑﺮ ﺑﺎ ﻳﻚ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﻣﺜﺎﻝ ‪ :۶-۳‬ﺷﻜﻞ ﺷﻤﺎﺭﻩ ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ‪ K*BMD‬ﻋﺪﺩ ﺑﺎﻳﻨﺮﻱ ‪ x0 x1 x2 x3‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ K*BMD -۸-۳‬ﻋﺪﺩ ﺑﺎﻳﻨﺮﻱ ‪[۱۹] x0 x1 x2 x3‬‬ ‫‪ -۹-۳‬ﺟﻤﻊﺑﻨﺪﻱ ﻭ ﻣﻘﺎﻳﺴﻪ ‪WLDD‬ﻫﺎ‬ ‫ﺩﺭ ﺑﺨﺸﻬﺎﻱ ﻗﺒﻞ ﺩﻳﺎﮔﺮﺍﻡﻫﺎﻱ ﺗﺼﻤﻴﻢ ﻣﺘﻔﺎﻭﺗﻲ ﻣﻌﺮﻓـﻲ ﺷـﺪﻧﺪ‪ ،‬ﺗﻌـﺪﺍﺩﻱ ﺍﺯ ﺁﻧﻬـﺎ ﺩﺭ ﺳـﻄﺢ ﺑﻴـﺖ ﻫﺴـﺘﻨﺪ ﻭ‬ ‫ﺗﻌﺪﺍﺩﻱ ﺩﻳﮕﺮ ﺩﺭ ﺳﻄﺢ ﻛﻠﻤﻪ ﻧﻴﺰ ﻛﺎﺭﺁﻳﻲ ﺩﺍﺭﻧﺪ‪ .‬ﺑﻌﻀﻲ ﺍﺯ ﺁﻧﻬﺎ ﺗﻮﺍﺑﻊ ﺷﺒﻪ ﺑﻮﻟﻲ ﺭﺍ ﻣﺪﻝ ﻣـﻲﻛﻨﻨـﺪ ﻭ ﺗﻌـﺪﺍﺩﻱ‬ ‫ﺩﻳﮕﺮ ﻗﺎﺑﻠﻴﺖ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺗﻮﺍﺑﻊ ﺟﺒﺮﻱ ﺭﺍ ﻧﻴﺰ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺩﺭ ﻋﻤﻞ ‪ WLDD‬ﻫﺎ ﺩﺭ ﺍﺑﺰﺍﺭﻫﺎﻱ ﺩﺭﺳـﺘﻲ ﻳـﺎﺑﻲ‬ ‫‪۵۰‬‬ ‫]‪ [۲۰‬ﺩﺭ ﺑﺮﺭﺳﻲ ﻧﻤﺎﺩﻳﻦ ﻣﺪﻝ ]‪ [۲۱‬ﺍﺳﺘﻔﺎﺩﻩ ﺷﺪﻩﺍﻧﺪ‪ WLDD .‬ﻫﺎ ﺑﻪ ﻋﻨﻮﺍﻥ ﭘﻠﻲ ﺍﺭﺗﺒﺎﻃﻲ ﺑﻴﻦ ﺩﺭﺳﺘﻲﻳـﺎﺑﻲ ﺩﺭ‬ ‫ﺳﻄﻮﺡ ﺑﺎﻻ ﻭ ﺗﻮﺻﻴﻒ ﺩﺭ ﺳﻄﺢ ﮔﻴﺖ ﻣﺪﺍﺭ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﻪ ﺻﻮﺭﺗﻲ ﻛﻪ ﺗﻌﺪﺍﺩ ﺯﻳﺎﺩﻱ ﺍﺯ ﺗﻮﺻـﻴﻒ ﺳـﻄﺢ ﺑـﺎﻻﻱ‬ ‫‪ HDL‬ﻣﺪﺍﺭ ﺑﺮ ﺍﺛﺮ ﺗﺒﺪﻳﻞ ﺑﻪ ‪ WLDD‬ﺗﻐﻴﻴﺮ ﻧﻤﻲﻛﻨﺪ‪ .‬ﺑﺮﺍﻱ ﺑﺮﺭﺳﻲ ﻛﺎﺭﺍﻳﻲ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺳـﻄﺢ ﺑـﺎﻻﻱ ﻣﺨﺘﻠـﻒ‬ ‫ﺩﺭ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﻣﺘﻔﺎﻭﺕ ﻗﻀﻴﻪﻫﺎﻳﻲ ﻣﻌﺮﻓﻲ ﻭ ﺍﺛﺒﺎﺕ ﺷﺪﻩﺍﻧﺪ ﻛﻪ ﺑﺮﺍﻱ ﻧﻤﻮﻧﻪ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﻗﻀﻴﻪﻱ ﺯﻳﺮﺍﺷﺎﺭﻩ ﻛﺮﺩ‬ ‫]‪.[۲۰‬‬ ‫‪ n‬‬ ‫‪i =0  i ‬‬ ‫‪c‬‬ ‫ﻗﻀﻴﻪ ‪ BMD :۱-۳‬ﺗﺎﺑﻊ ‪ Xc‬ﺣﺪﺍﻛﺜﺮ ﺩﺍﺭﺍﻱ ‪ ∑  ‬ﮔﺮﻩ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺩﺭ ﺻـﻮﺭﺗﻲ ﻛـﻪ ﺗﺮﺗﻴـﺐ ﻣﺘﻐﻴﺮﻫـﺎ ﺭﺍ ﺑـﻪ‬ ‫ﺻﻮﺭﺕ ‪ x0 , x1 ,..., xn−2 , xn−1‬ﺑﮕﻴﺮﻳﻢ]‪.[۲۰‬‬ ‫ﺟﺪﻭﻝ ‪ ۱-۳‬ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﺍﻧﺪﺍﺯﻩﻱ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ ﺳﻄﺢ ﻛﻠﻤﻪ ﻣﺘﻔﺎﻭﺕ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺟﺒـﺮﻱ ﻣﻌﻤـﻮﻝ‬ ‫ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪cx‬‬ ‫‪x2‬‬ ‫‪x. y‬‬ ‫‪x+ y‬‬ ‫‪x‬‬ ‫‪exp‬‬ ‫‪exp‬‬ ‫‪exp‬‬ ‫‪exp‬‬ ‫‪exp‬‬ ‫‪MTBDD‬‬ ‫‪exp‬‬ ‫‪exp‬‬ ‫‪exp‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪EVBDD‬‬ ‫‪exp‬‬ ‫‪quad‬‬ ‫‪Quad‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪BMD,HDD‬‬ ‫‪Lin‬‬ ‫‪quad‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪*BMD‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪lin‬‬ ‫‪K*BMD‬‬ ‫ﺟﺪﻭﻝ ‪ -۱-۳‬ﺍﻧﺪﺍﺯﻩﻱ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ ﺳﻄﺢ ﻛﻠﻤﻪ ﻣﺘﻔﺎﻭﺕ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺟﺒﺮﻱ ﻣﻌﻤﻮﻝ]‪[۲۰‬‬ ‫‪۵۱‬‬ ‫‪ ٣١TED -۴‬ﻭ ‪CTED‬‬ ‫‪٣٢‬‬ ‫ﻫﻤﺎﻧﻄﻮﺭ ﻛﻪ ﺩﺭﻓﺼﻞ ﻗﺒﻠﻲ ﻣﺸﺎﻫﺪﻩ ﺷﺪ‪،‬ﺗﻤﺎﻡ ﺑﺴﻂﻫﺎﻱ ﻣﻮﺟﻮ ِﺩ ‪ BDD‬ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻧﺎﭼﺎﺭ ﺑﻪ ﺗﻘﺴـﻴﻢ‬ ‫ﻭﺭﻭﺩﻱ ﺑﻪ ﺑﻴﺘﻬﺎﻱ ﺗﺸﻜﻴﻞ ﺩﻫﻨﺪﻩﻱ ﺁﻥ ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﻳﻌﻨﻲ ﺍﮔﺮ ﺩﺭ ﻳـﻚ ﺳﻴﺴـﺘﻢ ﻣﺘﻐﻴـﺮ ‪ A‬ﻫﺸـﺖ ﺑﻴﺘـﻲ ﻭﺟـﻮﺩ‬ ‫ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‪ ،‬ﻣﺪﻟﻬﺎﻱ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴ ِﻢ ﺩﺭ ﺳﻄﺢ ﻛﻠﻤﻪ ﺁﻥ ﻣﺘﻐﻴﺮ ﺭﺍ ﺑﻪ ‪ ۸‬ﻣﺘﻐﻴﺮ ﺑﻴﺘﻲ ‪ A8 ,...., A2 , A1‬ﺗﻘﺴـﻴﻢ‬ ‫ﻣﻲﻛﻨﻨﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺍﺭﺗﻔﺎﻉ ﮔﺮﺍﻑ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺩﺭ ﺍﺯﺍﻱ ﻳﻚ ﻣﺘﻐﻴﺮ ‪ n‬ﺑﻴﺘـﻲ ﺑـﻪ ﺍﻧـﺪﺍﺯﻩ ‪ n‬ﺍﺿـﺎﻓﻪ ﻣـﻲﺷـﻮﺩ‪.‬‬ ‫ﻋﻼﻭﻩ ﺑﺮ ﺍﻓﺰﺍﻳﺶ ﺣﺠﻢ ﮔﺮﺍﻑ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ‪ ،‬ﺍﻳﻦ ﻣﺸﻜﻞ ﺑﺎﻋﺚ ﻣﻲﺷﻮﺩ ﻛﻪ ﺍﺑﺰﺍﺭﻫﺎﯼ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ ﻣﻮﺟـﻮﺩ‬ ‫ﻛﻪ ﺑﺮ ﭘﺎﻳﻪﻱ ﺍﻳﻨﮕﻮﻧﻪ ﺩﻳﺎﮔﺮﺍﻣﻬﺎ ﻃﺮﺍﺣﻲﺷﺪﻩﺍﻧﺪ‪ ،‬ﻧﺘﻮﺍﻧﻨﺪ ﺍﺯ ﺍﻃﻼﻋﺎﺕ ﺳﻄﺢ ﺑﺎﻻﻱ ﻣﻮﺟﻮﺩ ﺩﺭ ﺗﻮﺻـﻴﻒ ﺳـﻄﺢ‬ ‫ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺍﺳﺘﻔﺎﺩﻩ ﻛﻨﻨﺪ‪ .‬ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﺟﻤﻊ ﺩﻭ ﻣﺘﻐﻴﺮ ﻫﺸﺖ ﺑﻴﺘﻲ‪ ،‬ﻛﻪ ﺩﺭ ﺍﻳﻦ ﻣﺪﻟﻬﺎ ﺍﺑﺘﺪﺍ ﺍﻳﻦ ﻋﻤﻞ ﺑﻪ ﻋﺒـﺎﺭﺕ‬ ‫ﻣﻨﻄﻘﻲ ﺣﺎﺻﻞ ﺍﺯ ﺑﻴﺘﻬﺎﻱ ﺗﺸﻜﻴﻞﺩﻫﻨﺪﻩﻱ ﺩﻭ ﻣﺘﻐﻴﺮ ﺗﺒﺪﻳﻞ ﻣﻲﺷﻮﺩ ﺳﭙﺲ ﺩﻳﺎﮔﺮﺍﻡ ﺗﺼﻤﻴﻢ ﺑﺮﺍﺳﺎﺱ ﺁﻥ ﻋﺒﺎﺭﺕ‬ ‫ﻣﻨﻄﻘﯽ ﻃﺮﺍﺣﻲ ﻣﻲﺷﻮﺩ‪ .‬ﺣﺘﻲ ﺑﺎ ﻭﺟﻮﺩ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﻱ ﺗﺼﻤﻴﻢ ﺩﺭ ﺳﻄﺢ ﻛﻠﻤﻪ ﻣﺎﻧﻨﺪ ‪ MTBDD‬ﺗﻨﻬـﺎ ﺧﺮﻭﺟـﻲ‬ ‫ﺗﺎﺑﻊ ﻛﻪ ﻳﮏ ﻣﺘﻐﻴﺮ‪ ۹‬ﺑﻴﺘﻲ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺗﻘﺴﻴﻢ ﻧﻤﻲﮔـﺮﺩﺩ‪ .‬ﺍﺯ ﺳـﻮﻱ ﺩﻳﮕـﺮ ﺗﻼﺷـﻬﺎﻳﻲ ﻛـﻪ ﺑـﺮﺍﻱ ﻃﺮﺍﺣـﻲ ﺍﺑـﺰﺍﺭ‬ ‫ﻞ ﻗﺴـﻤﺖ ﻛﻨﺘﺮﻟـﻲ ﻣـﺪﺍﺭ ﺍﺯ ﻳﻜﺴـﻮ ]‪ [۲۲‬ﻭ‬ ‫ﺩﺭﺳﺘﻲ ﻳﺎﺑﻲ ﺩﺭ ﺳﻄﺢ ﻛﻠﻤﻪ ﺍﻧﺠﺎﻡ ﺷﺪﻩ ﺍﺳﺖ ﺩﺭ ﺩﻭ ﻣﺴﻴ ِﺮ ﻣﺴﺘﻘ ِ‬ ‫‪Tailor Expansion Diagram 31‬‬ ‫‪Conditional Tailor Expansion Diagram 32‬‬ ‫‪۵۲‬‬ ‫ﻗﺴﻤﺖ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺍﺯ ﺳﻮﻱ ﺩﻳﮕﺮ ﺑﻮﺩﻩ ﺍﺳﺖ]‪ .[۲۳‬ﻛﻪ ﺩﺭ ﻫﺮ ﻛـﺪﺍﻡ ﺍﺯ ﺍﻳـﻦ ﺩﻭﺑﺨـﺶ ﺑـﻪ ﺻـﻮﺭﺕ ﻣﺴـﺘﻘﻞ‪،‬‬ ‫ﭘﻴﺸﺮﻓﺘﻬﺎﻳﻲ ﺍﻧﺠﺎﻡ ﺷﺪﻩ ﺍﺳﺖ ﺍﺯﺟﻤﻠﻪ ﺭﻭﺷﻬﺎﻱ ﺍﺛﺒﺎﺕ ﺗﺌﻮﺭﻳﻚ ﻳﺎ ﺩﻭﺑﺎﺭﻩﻧﻮﻳﺴﻲ ﻣﺸﺨﺼﺎﺕ ﺑﺎ ﻛﻤﻚ ﺩﺭﺧﺖ‬ ‫‪ .Syntax‬ﺑﺎ ﻭﺟﻮﺩ ﺍﻳﻦ ﻫﻨﻮﺯ ﺗﻼﺵ ﺑﺮﺍﻱ ﺳﺎﺧﺖ ﻣﺪﻟﻲ ﻛﻪ ﺑﺘﻮﺍﻧﺪ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺭﺍ ﻛـﻪ ﺗﺮﻛﻴﺒـﻲ‬ ‫ﺍﺯ ﻳﻚ ﻗﺴﻤﺖ ﺳﻄﺢ ﻛﻠﻤﻪ )ﻣﺤﺎﺳﺒﺎﺗﻲ( ﻭ ﺳﻄﺢ ﺑﻴﺖ )ﻛﻨﺘﺮﻟﻲ( ﻣﻲﺑﺎﺷﺪ ﻣـﺪﻝ ﻛﻨـﺪ ﺑـﻪ ﻧﺘﻴﺠـﻪ ﻗﺎﺑـﻞ ﻗﺒـﻮﻟﻲ‬ ‫ﺩﺳﺖ ﻧﻴﺎﻓﺘﻪ ﺍﺳﺖ‪ .‬ﺩﺭ ﺍﻳﻦ ﻓﺼﻞ ﺍﺑﺘﺪﺍ ‪ TED‬ﻛﻪ ﻣﺪﻟﻲ ﺟﺪﻳﺪ ﺑﺎ ﺗﺎﺑﻊ ﺗﺠﺰﻳﻪﻱ ﺟﺪﻳﺪﻱ ﺑﺎﺷﺪ ﺍﺭﺍﻳﻪ ﻣـﻲﮔـﺮﺩﺩ‪.‬‬ ‫ﺳﭙﺲ ﺑﺴﻂ ﺍﻳﻦ ﻣﺪﻝ ﺑﺮﺍﻱ ﺩﺭ ﺑﺮﮔﺮﻓﺘﻦ ﻋﺒﺎﺭﺗﻬﺎﻱ ﻛﻨﺘﺮﻟﻲ ﺳﻄﺢ ﻛﻠﻤﻪ ﺑﻴﺎﻥ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫‪ -۱-۴‬ﺩﻳﺎﮔﺮﺍﻡ ﺑﺴﻂ ﺗﻴﻠﻮﺭ )‪(TED‬‬ ‫ﺍﺳﺎﺱ ﺍﻳﻦ ﻣﺪﻝ ﺗﺎﺑﻊِﺗﺠﺰﻳﻪ ﺟﺪﻳﺪﻱ ﻳﻌﻨﻲ ﺑﺴﻂ ﺗﻴﻠﻮﺭ ﻋﺒﺎﺭﺕ ﺳﻄﺢ ﻛﻠﻤﻪ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﻫـﺮ ﻣﺮﺣﻠـﻪ ﺗﺠﺰﻳـﻪ‪،‬‬ ‫ﻋﺒﺎﺭﺕ ﺑﺮﺍﺳﺎﺱ ﻳﻜﻲ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺁﻥ ﺑﺎ ﻛﻤﻚ ﺑﺴﻂ ﺗﻴﻠﻮﺭ ﺗﺠﺰﻳـﻪ ﻣـﻲﺷـﻮﺩ‪ TED .‬ﺣﺎﺻـﻞ ﺑـﻪ ﺍﺯﺍﻱ ﻳـﻚ‬ ‫ﺗﺮﺗﻴﺐ ﺧﺎﺹ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎ ﻳﻜﺘﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻓﺮﺽ ﺍﻭﻟﻴﻪ ﺑﺮﺍﻱ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﻣﺪﻝ ﻣﺸﺘﻖﭘﺬﻳﺮﻱ ﻋﺒﺎﺭﺕ ﻣﻮﺭﺩﻧﻈﺮ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ﺗﻤﺎﻡ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺳﻄﺢ ﺑﺎﻻ ﻛﻪ ﺩﺭ ﻣﺪﺍﺭﻫﺎﻱ ﻣﺠﺘﻤﻊ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﻧﺪ ﺩﺭ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺧـﻮﺩ‬ ‫ﺍﺯ ﺑﺴﻂ ﺗﻴﻠﻮﺭ ﺑﺎ ﺗﻌﺪﺍﺩ ﺟﻤﻠﻪ ﻣﺸﺨﺺ ﻭ ﻣﺤﺪﻭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﻛﻨﻨﺪ ﻭ ﻳﺎ ﺑﻪ ﺧﻮﺩﻱ ﺧﻮﺩ ﻣﺸﺘﻖﭘـﺬﻳﺮ ﻭﻣﺤـﺪﻭﺩ‬ ‫ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺍﻳﻦ ﻓﺮﺽ ﺑﺮﺍﻱ ﺗﻤﺎﻣﻲ ﻋﺒﺎﺭﺍﺕ ﺳﻄﺢ ﺑﺎﻻﻱ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺩﺭ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻛـﺎﺭﺁﻳﻲ‬ ‫ﺩﺍﺭﺩ‪ .‬ﺩﻟﻴﻞ ﻛﺎﺭﺁﻳﻲ ﻣﺪﻝ ‪ TED‬ﻓﺸﺮﺩﻩ ﺑﻮﺩﻥ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺁﻥ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺯﻳﺮﺍ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺍﺕ ﻣﻌﻤﻮﻝ ﻛﻪ ﺩﺭ ﺳﻄﺢ‬ ‫ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﻣﺎﻧﻨﺪ ‪ X.Y,X+Y‬ﻭ‪ X K‬ﺩﺍﺭﺍﯼ ﺭﺷﺪ ﺧﻄﻲ ﻣﺘﻨﺎﺳﺐ ﺑﺎ ﺗﻌﺪﺍﺩ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺑﺎﺷـﺪ‪.‬‬ ‫ﺩﺭ ﻭﺍﻗﻊ ﺍﻳﻦ ﻣﺪﻝ ﺗﻨﻬﺎ ﻣﺪﻝ ﻣﻮﺟﻮﺩ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻋﺒﺎﺭﺗﻬﺎﻱ ﻣﺤﺎﺳﺒﺎﺗﻲ ﺑﺎ ﺗﻮﺍﻥ ﺑـﺎﻻﺗﺮ ﺍﺯ ﺩﻭ ﺑـﺎ ﺭﺷـﺪ ﺧﻄـﻲ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﺯ ﺳﻮﻱ ﺩﻳﮕﺮ ﺯﻣﺎﻥ ﭘﺮﺩﺍﺯﻧـﺪﻩ ﻣـﻮﺭﺩ ﻧﻴـﺎﺯ ﺑـﺮﺍﻱ ﺳـﺎﺧﺖ ﺍﻳـﻦ ﻣـﺪﻝ ﺑـﺎ ‪ *BMD‬ﻗﺎﺑـﻞ ﻣﻘﺎﻳﺴـﻪ‬ ‫ﻣﻲﺑﺎﺷﺪ]‪[۲۴‬‬ ‫‪۵۳‬‬ ‫‪ -۱-۱-۴‬ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ‪TED‬‬ ‫ﺩﺭ ﻧﻤﺎﻳﺶ ‪ TED‬ﻳﻚ ﺗﺎﺑﻊ‪ ،‬ﺍﺯ ﺑﺴﻂ ﺗﻴﻠﻮﺭ ﺁﻥ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮔﺮﺩﺩ‪ .‬ﻓﺮﺽ ﺍﻭﻟﻴـﻪ ﺩﺭ ﺍﻳـﻦ ﺑﺨـﺶ ﺣﻘﻴﻘـﻲ ﺑـﻮﺩﻥ‬ ‫ﺩﺍﻣﻨﻪﻱ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻭﻟﻲ ﻣﻲﺗﻮﺍﻥ ﺍﺛﺒﺎﺕ ﮐﺮﺩ ﻛﻪ ﻓﺮﺽ ﺻﺤﻴﺢ ﺑﻮﺩﻥ ﺩﺍﻣﻨـﻪ ﺁﺳـﻴﺒﻲ ﺑـﻪ‬ ‫ﻣﺪﻝ ﻧﻤﻲﺭﺳﺎﻧﺪ‪.‬‬ ‫ﺍﮔﺮ )…‪ f(x,y,‬ﻳﻚ ﺗﺎﺑﻊ ﺣﻘﻴﻘﻲ‪ ،‬ﻣﺸﺘﻖﭘﺬﻳﺮ ﻭ ﻧﻤﺎﻳﺎﻧﮕﺮ ﻋﺒﺎﺭﺕ ﺟﺒﺮﻱ ‪ F‬ﺑﺎﺷﺪ‪ .‬ﺑـﺎ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ ﺑﺴـﻂ ﺗﻴﻠـﻮﺭ‬ ‫ﺑﺮﺣﺴﺐ ﻣﺘﻐﻴﺮ ‪ x‬ﺣﻮﻝ ﻧﻘﻄﻪ ‪ x0= 0‬ﺗﺎﺑﻊ ‪ f‬ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻧﻤﺎﻳﺶ ﺩﺍﺩ‪:‬‬ ‫‪f ( x ) = f (0) + xf ′(0) + 12 x 2 f ′′(0) + L‬‬ ‫ﻛﻪ ﺩﺭ ﺁﻥ ‪ f ′‬ﻭ ‪ f ′′‬ﺑﻪ ﺗﺮﺗﻴﺐ ﻣﺸﺘﻖ ﺍﻭﻝ ﻭ ﺩﻭﻡ ‪ f‬ﺑﺮ ﺣﺴﺐ ‪ x‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻫﺮ ﻛﺪﺍﻡ ﺍﺯ ﺍﻳـﻦ ﺗﻮﺍﺑـﻊ ﻣـﻲﺗﻮﺍﻧﻨـﺪ‬ ‫ﺑﺮﺣﺴﺐ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺑﺎﻗﻴﻤﺎﻧﺪﻩ ﺩﺭ ﻋﺒﺎﺭﺕ ﺁﻧﻬﺎ ﻭ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺑﺴﻂ ﺗﻴﻠﻮﺭ ﺗﺠﺰﻳﻪ ﺷﻮﻧﺪ‪.‬‬ ‫‪ TED‬ﻳﻚ ﮔﺮﺍﻑ ﺟﻬﺘﺪﺍﺭ ﻭ ﺑﺪﻭﻥﺩﻭﺭ ) ‪ (ϕ ,V , E , T‬ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻳﻚ ﻋﺒـﺎﺭﺕ ﺟﺒـﺮﻱ ﻣـﻲﺑﺎﺷـﺪ‪ ϕ .‬ﺗـﺎﺑﻊ‬ ‫ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﻋﺒﺎﺭﺕ ﻣﻲﺑﺎﺷﺪ‪ V .‬ﻣﺠﻤﻮﻋﻪ ﮔﺮﻩﻫﺎ ﻭ ‪ E‬ﻳﺎﻟﻬﺎﻱ ﻭﺯﻧﺪﺍﺭ ﻭ ﺟﻬﺘـﺪﺍﺭ ﻭ ‪ T‬ﻣﺠﻤﻮﻋـﻪﻱ ﺑﺮﮔﻬـﺎﻱ‬ ‫ﮔﺮﺍﻑ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺭﻳﺸﻪﻱ ﻳﮑﺘﺎﻱ ‪ TED‬ﻧﻤﺎﻳﺎﻧﮕﺮ ﺗﺎﺑﻊ ‪ ϕ‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻛـﻪ ﻳﺎﻟﻬـﺎﻱ ﺁﻥ ﺑـﻪ ﻣﺸـﺘﻘﻬﺎﻱ ﺗـﺎﺑﻊ ‪ ϕ‬ﺑـﺮ‬ ‫ﺣﺴﺐ ﻳﻜﻲ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻮﺟﻮﺩ ﺩﺭ ‪ ϕ‬ﻛﻪ ﺑﻪ ﺭﻳﺸﻪ ﻧﺴﺒﺖ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ ،‬ﺍﺷﺎﺭﻩ ﻣﻲﻛﻨﺪ‪.‬‬ ‫ﻫﺮ ﮔﺮﻩ ‪ v‬ﺑﺎ ﻳﻚ ﻣﺘﻐﻴﺮ )‪ var(v‬ﺑﺮﭼﺴﺐ ﺩﻫﻲ ﺷﺪﻩ ﺍﺳﺖ ﻛﻪ ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﻣﺘﻐﻴﺮﻱ ﻣـﻲﺑﺎﺷـﺪ‪ ،‬ﻛـﻪ ﻋﺒـﺎﺭﺕ‬ ‫ﻣﻌﺎﺩﻝ ﺁﻥ ﮔﺮﻩ ﺑﺮﺣﺴﺐ ﺁﻥ ﺗﺠﺰﻳﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺗﻌﺪﺍﺩ ﻳﺎﻟﻬﺎﻱ ﺧﺮﻭﺟ ِ‬ ‫ﻲ ﮔـﺮﻩ ‪ v‬ﻛـﻪ ﻧﻤﺎﻳﻨـﺪﻩ ﺗـﺎﺑﻊ ﺟﺒـﺮﻱ )‪g(x‬‬ ‫ﻣﻲﺑﺎﺷﺪ ﻭ ﺑﺎ ﻣﺘﻐﻴﺮ ‪ x‬ﺑﺮﭼﺴﺐﺩﻫﻲ ﺷﺪﻩﺍﺳﺖ‪ ،‬ﺑﺮﺍﺑﺮ ﺑﺎ ﺩﺭﺟﻪ ﺗﺎﺑﻊ )‪ g(x‬ﺑﺮﺣﺴﺐ ‪ x‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻫﺮ ﻛﺪﺍﻡ ﺍﺯ ﺍﻳﻦ‬ ‫ﮔﺮﻩﻫﺎ ﺑﻪ ﺗﺮﺗﻴﺐ ﻧﻤﺎﻳﻨﺪﻩ ﺗﻮﺍﺑﻊ)‪ g ′′(0), g ′(0) ، g(0‬ﻭ… ﺑﺮ ﺣﺴﺐ‪ x‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺗﻌﺪﺍﺩ ﻳﺎﻟﻬﺎﻱ ﺧﺮﻭﺟﻲ ﺑـﺮﺍﻱ‬ ‫ﮔﺮﻩ ﺑﺮﮒ‪ ،‬ﺻﻔﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﮔﺮﻩ ﻧﻤﺎﻳﺎﻧﮕﺮ ﻳﮏ ﻋﺪﺩ ﺛﺎﺑﺖ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺷﻜﻞ ‪ ۱-۴‬ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﺗﺠﺰﻳﻪ ﺗﺎﺑﻊ ‪f‬‬ ‫ﺑﺮﺣﺴﺐ ‪ x‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪۵۴‬‬ ‫ﺷﮑﻞ ‪ -۱-۴‬ﮔﺮﻩ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ ﺩﺭ ﮔﺮﺍﻑ ‪TED‬‬ ‫ﻣﺸﺘﻖ ‪k‬ﺍﻡ ﺗﺎﺑﻊ ﮔﺮﻩ‪ v‬ﺑﺮ ﺣﺴﺐ ﻣﺘﻐﻴﺮ )‪k ، var(v‬ﺍﻣﻴﻦ ﻓﺮﺯﻧﺪ ﮔـﺮﻩ ‪ v‬ﻧﺎﻣﻴـﺪﻩ ﻣـﻲﺷـﻮﺩ‪ ،‬ﺩﺭ ﻧﺘﻴﺠـﻪ ‪f(x=0) :‬‬ ‫ﺻﻔﺮﻣﻴﻦ ﻓﺮﺯﻧﺪ ﻭ )‪ f ′( x = 0‬ﺍﻭﻟﻴﻦ ﻓﺮﺯﻧﺪ ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﻧﺪ‪ .‬ﻳﺎﻝ ﺍﺷﺎﺭﻩﻛﻨﻨﺪﻩ ﺑﻪ ‪k‬ﺍﻣـﻴﻦ ﻓﺮﺯﻧـﺪ‪k ،‬ﺍﻣـﻴﻦ ﻳـﺎﻝ‬ ‫ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺷﻜﻞ ‪ ۲-۴‬ﻣﺜﺎﻟﻬﺎﻳﻲ ﺍﺯ ‪ TED‬ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﺜﺎﻟﻬـﺎ ﺿـﺮﺍﻳﺐ ﺟﻤﻌـﻲ ﻭ ﺿـﺮﺑﻲ ﺑـﺮ ﺭﻭﻱ‬ ‫ﻳﺎﻟﻬﺎﻱ ﮔﺮﺍﻑ ﻗﺮﺍﺭ ﮔﺮﻓﺘﻪﺍﻧﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ TED -۲-۴‬ﻣﻌﺎﺩﻝ ﺗﻮﺍﺑﻊ ‪ X 2‬ﻭ ) ‪( A + B )( A + 2C‬‬ ‫ﺳﺎﺧﺖ ﺩﻳﺎﮔﺮﺍﻡ ‪ TED‬ﺑﻪ ﺻﻮﺭﺕ ﺑﺎﺯﮔﺸﺘﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﻗﻮﺍﻋﺪﻱ ﺑﺮﺍﻱ ﺗﺮﻛﻴﺐ ﺩﻭ ﮔﺮﺍﻑ ﻋﺒﺎﺭﺕ ﺳﺎﺩﻩ‬ ‫ﻭ ﺗﺸﻜﻴﻞ ﻳﻚ ﻋﺒﺎﺭﺕ ﭘﻴﭽﻴﺪﻩﺗﺮ ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺩﺭ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ‪ TED‬ﺍﺯ ﻫﻤﺎﻥ ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ ﻣﻮﺟﻮﺩ ﺩﺭ‬ ‫‪ BDD‬ﻫﺎ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮔﺮﺩﺩ‪ .‬ﻟﻴﻜﻦ ‪ TED‬ﻗﻮﺍﻋﺪ ﺧﺎﺻﻲ ﺑﺮﺍﻱ ﻋﻤﻠﮕﺮﻫﺎﻱ ﺳﻄﺢ ﻛﻠﻤﻪﻱ ﺿﺮﺏ ﻭ ﺟﻤـﻊ ﺩﺍﺭﺩ‪.‬‬ ‫ﻋﻤﻠﮕﺮ ﺗﻔﺮﻳﻖ ﻧﻴﺰ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳﻦ ﺩﻭ ﻋﻤﻠﮕﺮ ﻗﺎﺑﻞ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪۵۵‬‬ ‫‪ -۲-۱-۴‬ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ )ﺑﺮﺍﻱ ﻋﻤﻠﮕﺮﻫﺎﻱ ﺿﺮﺏ ﻭ ﺟﻤﻊ(‬ ‫ﺍِﻋﻤﺎﻝ ﺍﻳﻦ ﻗﻮﺍﻋﺪ ﺍﺯ ﺭﻳﺸﻪ ﺩﻭ ‪ TED‬ﺍﻭﻟﻴﻪ ﺷﺮﻭﻉ ﻣﻲﺷﻮﺩ‪ ،‬ﺳـﭙﺲ ‪ TED‬ﺣﺎﺻـﻞ ﺑـﻪ ﺻـﻮﺭﺕ ﺑﺎﺯﮔﺸـﺘﻲ ﺍﺯ‬ ‫ﺍﻋﻤﺎﻝ ﻗﻮﺍﻋﺪ ﺿﺮﺏ ﻭ ﺟﻤﻊ ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﭘﺎﻳﺎﻥ ‪ TED‬ﺣﺎﺻﻞ ﻛﺎﻫﺶﻳﺎﻓﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﻣﻮﺭﺩ ﺍﻳﻦ ﻋﻤﻞ‬ ‫ﺩﺭ ﺑﺨﺶ ﺑﻌﺪﻱ ﺗﻮﺿﻴﺢ ﺩﺍﺩﻩ ﺧﻮﺍﻫﺪﺷﺪ‪.‬‬ ‫ﺍﮔﺮ ﺩﻭ ﮔﺮﻩ ‪ u‬ﻭ ‪ v‬ﺑﺎ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺗﺠﺰﻳﻪ ‪ var(u)=x‬ﻭ ‪ var(u)=y‬ﺑﺨﻮﺍﻫﻨـﺪ ﺑـﺎ ﻫـﻢ ﺗﺮﻛﻴـﺐ ﺷـﻮﻧﺪ ﻭ ﮔـﺮﻩ ‪q‬‬ ‫ﺣﺎﺻﻞ ﺷﻮﺩ‪ .‬ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﮔﻔﺘﻪ ﺷﺪ ﻣﺘﻐﻴﺮ )‪ var(q‬ﻳﻜﻲ ﺍﺯ ﺩﻭ ﻣﺘﻐﻴﺮ ‪ x‬ﻳﺎ ‪ y‬ﺧﻮﺍﻫـﺪ ﺑـﻮﺩ ﻛـﻪ ﺩﺍﺭﺍﻱ ﺩﺭﺟـﻪ‬ ‫ﺑﺎﻻﺗﺮﻱ ﺑﺎﺷﺪ‪ .‬ﻳﻌﻨﻲ ‪ var(q)=x‬ﺍﮔﺮ ‪ x ≥ y‬ﻭ ‪ var(q)=y‬ﺍﮔﺮ ‪ . y > x‬ﮔﺮﻩﻫﺎﻱ ‪ u‬ﻭ ‪ v‬ﻧﻤﺎﻳﻨـﺪﻩﻱ ﺩﻭ ﺗـﺎﺑﻊ ‪f‬‬ ‫ﻭ‪ g‬ﻭ ‪ h‬ﺗﺎﺑﻊ ﻣﺸﺨﺺ ﺷﺪﻩ ﺑﺎ ﮔﺮﻩ ‪ q‬ﻣﻲﺑﺎﺷﺪ‪ T.‬ﻧﻴﺰ ﻣﺠﻤﻮﻋﻪ ﮔـﺮﻩﻫـﺎﻱ ﺑـﺮﮒ ﻣـﻲﺑﺎﺷـﺪ ﻛـﻪ ) ‪val (v ∈ T‬‬ ‫ﻧﺸﺎﻥﺩﻫﻨﺪﻩ ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﮔﺮﻩ ‪ v‬ﺍﺳﺖ‪ ،‬ﺑﺎ ﻓﺮﺿﻴﺎﺕ ﺑﺎﻻ ﻗﻮﺍﻋﺪ ﺯﻳﺮ ﺑﺮﺍﻱ ﻋﻤﻠﮕﺮﻫـﺎﻱ ﺿـﺮﺏ ﻭ ﺟﻤـﻊ ﺑﺮﻗـﺮﺍﺭ‬ ‫ﻣﻲﺑﺎﺷﺪ‪:‬‬ ‫‪ -۱‬ﺍﮔﺮ ﻫﺮ ﺩﻭ ﮔﺮﻩ ﺑﺮﮒ ﺑﺎﺷﻨﺪ‪ ،‬ﻳﻌﻨﻲ ‪ . u, v ∈ T‬ﺁﻧﮕﺎﻩ ‪ q‬ﻳﻚ ﮔﺮﻩ ﺑﺮﮒ ﺍﺳﺖ ﻛﻪ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺳﺎﺧﺘﻪ‪-‬‬ ‫ﻣﻲﺷﻮﺩ‪:‬‬ ‫)‪ ADD : q ← (u + v) : val (q) = val (u ) + val (v‬‬ ‫‪‬‬ ‫)‪MULT : q ← (u.v) : val (q) = val (u ).val (v‬‬ ‫‪ -۲‬ﺣﺪﺍﻗﻞ ﻳﻜﻲ ﺍﺯ ﮔﺮﻩﻫﺎ ﻏﻴﺮ ﺑﺮﮒ ﺑﺎﺷﺪ‪:‬‬ ‫‪ -۱-۲‬ﺍﮔﺮ ﻫﺮ ﺩﻭ ﮔﺮﻩ ﻣﺘﻐﻴﺮ ﺗﺠﺰﻳﻪﻱ ﻳﻜﺴﺎﻧﻲ ﺩﺍﺷﺘﻪ ﺑﺎﺷﻨﺪ)‪ (x‬ﺩﺭ ﻧﺘﻴﺠﻪ ‪var(q)=x‬‬ ‫‪ADD : q ← (u + v) :‬‬ ‫) ‪h( x ) = f ( x ) + g ( x‬‬ ‫])‪= [ f (0) + xf ′(0)] + [ g (0) + xg ′(0‬‬ ‫])‪= [ f (0) + g (0)] + x[ f ′(0) + g ′(0‬‬ ‫‪MULT : q ← (u.v) :‬‬ ‫)‪h( x) = f ( x).g ( x‬‬ ‫])‪= [ f (0) + xf ′(0)].[ g (0) + xg ′(0‬‬ ‫])‪= [ f (0) g (0)] + x[ f ′(0) g (0) + g ′(0) f (0)] + x 2 [ f ′(0) g ′(0‬‬ ‫‪۵۶‬‬ ‫ﺩﺭ ﻧﺘﻴﺠﻪ ﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﮔﺮﻩ ‪ q‬ﺍﺯ ﺿﺮﺏ ﻓﺮﺯﻧﺪﻫﺎﻱ ﺻﻔﺮﻡ ﮔﺮﻩ ‪ u‬ﻭ‪ v‬ﺑﺪﺳﺖ ﻣﻲﺁﻳـﺪ‪ ،‬ﻓﺮﺯﻧـﺪ ﺍﻭﻝ ﮔـﺮﻩ ‪q‬‬ ‫ﺍﺯ ﺟﻤ ِ‬ ‫ﻊ ﺣﺎﺻﻠﻀﺮﺏ ﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﮔﺮﻩ ‪ u‬ﺑﺎ ﻓﺮﺯﻧﺪ ﺍﻭﻝ ﮔﺮﻩ ‪ v‬ﻭ ﺣﺎﺻﻠﻀﺮﺏ ﻓﺮﺯﻧﺪ ﺍﻭﻝ ﮔﺮﻩ ‪ u‬ﺑﺎ ﻓﺮﺯﻧﺪ‬ ‫ﺻﻔﺮﻡ ﮔﺮﻩ ‪ v‬ﻭ ﻓﺮﺯﻧﺪ ﺩﻭﻡ ﮔﺮﻩ ‪ q‬ﺍﺯ ﺣﺎﺻﻠﻀﺮﺏ ﻓﺮﺯﻧﺪﻫﺎﻱ ﺍﻭﻝ ﮔﺮﻩﻫﺎﯼ ‪u‬ﻭ‪ v‬ﺑﺪﺳﺖﻣﻲﺁﻳﺪ‪.‬‬ ‫‪ -۲-۲‬ﺍﮔــــﺮ ﺩﻭ ﮔــــﺮﻩ ﻣﺘﻐﻴﺮﻫــــﺎﻱ ﺗﺠﺰﻳــــﻪ ﻣﺘﻔــــﺎﻭﺗﻲ ﺩﺍﺷــــﺘﻪ ﺑﺎﺷــــﻨﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠــــﻪ‬ ‫))‪ . var(q)=max(var(v),var(u‬ﺩﺭ ﺍﻳﻨﺠﺎ ﻓﺮﺽ ﻣﻲﺷﻮﺩ )‪.ord(x)>ord(y‬‬ ‫‪ADD : q ← (u + v) :‬‬ ‫) ‪h( x ) = f ( x ) + g ( y‬‬ ‫) ‪= [ f ( x = 0) + xf ′( x = 0)] + g ( y‬‬ ‫)‪= [ f ( x = 0) + g ( y )] + xf ′(0‬‬ ‫ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ ﮔﺮﻩ ﺑﺎ ﺩﺭﺟﻪ ﻛﻤﺘﺮ ﺗﻨﻬﺎ ﺑﺎ ﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﮔﺮﻩ ﺑﺎ ﺩﺭﺟﻪ ﺑﺎﻻﺗﺮ ﺟﻤﻊ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪MULT : q ← (u.v) :‬‬ ‫) ‪h( x) = f ( x).g ( y‬‬ ‫) ‪= [ f ( x = 0) + xf ′( x = 0)].g ( y‬‬ ‫]) ‪= [ f ( x = 0) g ( y )] + x[ f ′( x = 0) g ( y‬‬ ‫ﻳﻌﻨﻲ ﻓﺮﺯﻧﺪﺍﻥ ﮔﺮﻩ ﺑﺎ ﺩﺭﺟﻪ ﺑﺎﻻﺗﺮ ﺩﺭ ﮔﺮﻩ ﺑﺎ ﺩﺭﺟﻪ ﭘﺎﻳﻴﻦﺗﺮ ﺿﺮﺏ ﻣﻲﺷﻮﻧﺪ ‪.‬‬ ‫ﺷﻜﻞ ‪ ۳-۴‬ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﺍﻋﻤﺎﻝ ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ ﺑﺮﺍﯼ ﺍﻳﺠﺎﺩ ﺗﺎﺑﻊ ) ‪ ( A + B)( A + 2C‬ﻣﻲﺑﺎﺷﺪ‪:‬‬ ‫ﺷﮑﻞ ‪ -۳-۴‬ﺳﺎﺧﺖ ﺗﺎﺑﻊ ) ‪ ( A + B )( A + 2C‬ﺑﺎ ﮐﻤﮏ ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ‬ ‫‪۵۷‬‬ ‫‪ TED -۳-۱-۴‬ﻛﺎﻫﺶ ﻳﺎﻓﺘﻪ‬ ‫ﺑﺮﺍﻱ ﺳﺎﺧﺖ ﻳﻚ ‪ TED‬ﻳﻜﺘﺎ ﺑﺮﺍﻱ ﻫﺮ ﻋﺒﺎﺭﺕ ﺍﺑﺘﺪﺍ ﺑﺎﻳﺪ ‪ TED‬ﻛﺎﻫﺶﻳﺎﺑﺪ‪ .‬ﺍﻳﻦ ﻋﻤـﻞ ﺑـﺎ ﺣـﺬﻑ ﮔـﺮﻩﻫـﺎﻱ‬ ‫ﺍﻓﺰﻭﻧﻪ ﻭ ﺗﺮﻛﻴﺐ ﺯﻳﺮ ﮔﺮﺍﻓﻬﺎﻱ ﺍﻳﺰﻭﻣﻮﺭﻓﻴﻚ ﺍﻧﺠﺎﻡ ﻣﻲﮔﺮﺩﺩ‪ .‬ﻳﻚ ﮔﺮﻩ ﺍﻓﺰﻭﻧﻪ ﻣﻲﺑﺎﺷﺪ ﺍﮔﺮ‪ -۱‬ﺗﻤﺎﻡ ﻳﺎﻟﻬـﺎﻱ ﺁﻥ‬ ‫ﺻﻔﺮ ﺑﺎﺷﻨﺪ‪ -۲.‬ﻓﻘﻂ ﺷﺎﻣﻞ ﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﺑﺎﺷﺪ ﺩﺭ ﺍﻳﻦ ﺩﻭﺣﺎﻟﺖ ﻣﻲﺗﻮﺍﻥ ﭘﺪﺭ ﮔﺮﻩ ﺭﺍ ﺑـﻪ ﻓﺮﺯﻧـﺪ ﺻـﻔﺮﻡ ﮔـﺮﻩ‬ ‫ﻣﺘﺼﻞ ﻛﺮﺩ ﻭ ﮔﺮﻩ ﺍﻓﺰﻭﻧﻪ ﺭﺍ ﺣﺬﻑ ﻛﺮﺩ‪.‬‬ ‫ﺩﻭ ﮔﺮﺍﻑ ‪ , G ′ , G, TED‬ﺍﻳﺰﻭﻣﻮﺭﻑ ﻫﺴﺘﻨﺪ‪ .‬ﺍﮔﺮ ﻳﻚ ﺗﻨﺎﻇﺮ ﻳﻚ ﺑﻪ ﻳﻚ ) ‪ ( σ‬ﺑـﻴﻦ ﺭﺍﺳـﻬﺎﻱ ‪ G‬ﻭ ﺭﺍﺳـﻬﺎﻱ‬ ‫‪ G ′‬ﻭﺟﻮﺩ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‪ .‬ﻳﻌﻨﻲ ﺑﺮﺍﻱ ﺭﺍﺱ ‪ v‬ﺩﺭ ﮔﺮﺍﻑ ‪ G‬ﺭﺍﺱ ‪ σ (v) = v ′‬ﺩﺭ ﮔﺮﺍﻑ ‪ G ′‬ﻭﺟﻮﺩ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‬ ‫ﻛــﻪ ‪ -۱‬ﻫــﺮ ﺩﻭﮔــﺮﻩ ‪v‬ﻭ ‪ v ′‬ﮔــﺮﻩ ﺑــﺮﮒ ﺑﺎﺷــﻨﺪ ﻭ )‪ -۲ . val (v) = val (v ′‬ﻫــﺮ ﺩﻭ ﺭﺍﺱ ﻏﻴــﺮ ﺑــﺮﮒ ﺑﺎﺷــﻨﺪ‬ ‫ﻭ )‪ var(v) = var(v ′‬ﻭ ﺑــﺮﺍﻱ ﺗﻤــﺎﻡ ‪ k‬ﻳــﺎﻝ ﻏﻴــﺮ ﺻــﻔﺮ ))‪σ (child (edge _ k (v))) = child (edge _ k (v ′‬‬ ‫ﺑﻪ ﺻﻮﺭﺗﻲ ﻛﻪ ﻳﺎﻟﻬﺎﻱ ﻣﺘﻨﺎﻇﺮ ﻭﺯﻥ ﻳﻜﺴﺎﻧﻲ ﺩﺍﺷﺘﻪ ﺑﺎﺷﻨﺪ‪.‬‬ ‫ﻳﻚ ‪ TED‬ﻛﺎﻫﺶ ﻳﺎﻓﺘﻪ ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ ﺍﮔﺮ ﻫﻴﭻ ﮔﺮﻩ ﺍﻓﺰﻭﻧﻪﺍﻱ ﻧﺪﺍﺷﺘﻪ ﺑﺎﺷﺪ ﻭ ﻫﻤﭽﻨﻴﻦ ﻫﻴﭻ ﺩﻭ ﮔـﺮﻩ ‪ v‬ﻭ ‪v ′‬‬ ‫ﻭﺟﻮﺩ ﻧﺪﺍﺷﺘﻪ ﺑﺎﺷﺪ‪ ،‬ﻛﻪ ﺯﻳﺮﮔﺮﺍﻓﻬﺎﻱ ‪v‬ﻭ ‪ v ′‬ﺍﻳﺰﻭﻣﻮﺭﻑ ﺑﺎﺷﻨﺪ‪.‬‬ ‫ﺷﺮﻁ ﺩﻳﮕﺮ ﻳﻜﺘﺎ ﺑﻮﺩﻥ ﮔﺮﺍﻑ ‪ TED‬ﻣﺮﺗﺐ‪ ٣٣‬ﺑﻮﺩﻥ ﺁﻥ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻳﻌﻨﻲ ﺩﺭ ﻫﺮ ﻣﺴﻴﺮ ﺭﻳﺸﻪ ﺑﻪ ﺑـﺮﮒ ﺩﺭ ﮔـﺮﺍﻑ‬ ‫‪ TED‬ﻣﺘﻐﻴﺮﻫﺎ ﺑﺎ ﻳﻚ ﺗﺮﺗﻴﺐ ﻳﻜﺴﺎﻥ ﻭﻓﻘﻂ ﻳﻜﺒﺎﺭ ﻇﺎﻫﺮ ﺷﻮﻧﺪ‪.‬‬ ‫ﺛﺎﺑﺖ ﻣﻲﺷﻮﺩ ﻛﻪ ﻳﻚ ‪ TED‬ﻛﺎﻫﺶ ﻳﺎﻓﺘﻪ ﻭ ﻣﺮﺗﺐ ﻳﻚ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺟﺒـﺮﻱ ﻣـﻲﺑﺎﺷـﺪ]‪.[۲۴‬‬ ‫ﺩﺭ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺧﻄﻲ ﺍﻧﺪﺍﺯﻩ ‪ TED‬ﺑﺎ ‪ *BMD‬ﻳﻜﺴﺎﻥ ﻣﻲﺑﺎﺷﺪ ﻳﻌﻨـﻲ ﺭﺷـﺪ ﻫـﺮ ﺩﻭ ﺁﻧﻬـﺎ ﺑـﻪ ﺻـﻮﺭﺕ ﺧﻄـﻲ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﻟﻴﻜﻦ ﺑﺮﺍﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﭼﻨﺪ ﺟﻤﻠﻪﺍﻱ ﺑﺎ ﺩﺭﺟﻪ ﺑﺰﺭﮔﺘﺮ ﺍﺯ ﺩﻭ )‪ (k ≥ 2‬ﻛﻪ ﺍﻧﺪﺍﺯﻩ ‪ *BMD‬ﺑـﺎ ) ‪O(n k‬‬ ‫)‪n‬ﺗﻌﺪﺍﺩ ﺑﻴﺖ ﻭﺭﻭﺩﻱ ( ﺭﺷﺪ ﻣﻲﻛﻨﺪ ‪ TED‬ﺭﺷﺪ ﺧﻄﻲ ﺩﺍﺭﺩ]‪.[۲۴‬‬ ‫‪ordered 33‬‬ ‫‪۵۸‬‬ ‫‪ -۴-۱-۴‬ﻧﻤﺎﻳﺶ ﺗﻮﺍﺑﻊ ﺑﻮﻟﻲ ﻭ ﺑﻮﻟﻲ‪-‬ﺟﺒﺮﻱ ﺑﺎ ﻛﻤﻚ ‪TED‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﮔﻔﺘﻪ ﺷﺪ ‪ TED‬ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻫﻤﺰﻣﺎﻥ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﻭ ﺟﺒﺮﻱ ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺍﺳـﺖ‪ .‬ﺗـﺎ ﺑﺤـﺎﻝ‬ ‫ﻧﺤﻮﻩﻱ ﻧﻤﺎﻳﺶ ﺗﻮﺍﺑﻊ ﻣﺸﺘﻖﭘﺬﻳﺮﺣﻘﻴﻘﻲ ﻣﻄﺮﺡ ﺷﺪ‪ .‬ﺑﺮﺍﻱ ﺍﻳﻨﻜﻪ ‪ TED‬ﻗﺎﺑﻠﻴﺖ ﻧﻤﺎﻳﺶ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺭﺍ ﻧﻴـﺰ‬ ‫ﺑﺪﺳﺖ ﺑﻴﺎﻭﺭﺩ‪ ،‬ﺍﺑﺘﺪﺍ ﺑﺎﻳﺪ ﻋﻤﻠﮕﺮﻫﺎﯼ ﺑﻮﻟﻲ ﺭﺍ ﺑﻪ ﮔﻮﻧﻪﺍﻱ ﺗﻐﻴﻴﺮ ﺩﻫﻴﻢ ﺗﺎ ﺑﺘﻮﺍﻥ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑـﻮﻟﻲ ﺭﺍﺑـﻪ ﺻـﻮﺭﺕ‬ ‫ﻳﻚ ﺗﺎﺑﻊ ﻣﺸﺘﻖﭘﺬﻳﺮ ﺣﻘﻴﻘﻲ ﺑﻴﺎﻥ ﻛﺮﺩ‪ .‬ﺑﺮﺍﻱ ﺍﻳﻨﻜﺎﺭ ﺍﺑﺘﺪﺍ ﺩﺍﻣﻨﻪﻱ ﺍﻳﻦ ﻋﺒﺎﺭﺗﻬﺎ ﺭﺍ ﻣﻘﺎﺩﻳﺮ }‪ {۰،۱‬ﻗﺮﺍﺭ ﻣﻲﺩﻫـﻴﻢ‪.‬‬ ‫ﺳﭙﺲ ﺗﻮﺍﺑﻊ ﺭﺍﺑﻪ ﮔﻮﻧﻪﺍﻱ ﺗﻐﻴﻴﺮ ﻣﻲﺩﻫﻴﻢ ﻛﻪ ﺑﺮﺩ }‪ {۰،۱‬ﺩﺍﺷﺘﻪ ﺑﺎﺷﻨﺪ ﻭ ﺍﺯ ﻗﻮﺍﻋﺪ ﺟﺒﺮ )*‪ R(+,‬ﺍﺳﺘﻔﺎﺩﻩ ﻛﻨﻨـﺪ‪.‬‬ ‫ﻫﻤﺎﻧﻨﺪ ‪ BMD‬ﻓﺮﻣﻮﻟﻬﺎﻱ ﺯﻳﺮ ﺑﺮﺍﻱ ﻣﺪﻝﻛﺮﺩﻥ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺩﺭ ‪ TED‬ﻃﺮﺍﺣﻲ ﺷﺪﻩ ﺍﻧﺪ ‪NOT ( x) = 1 − x‬‬ ‫‪ OR( x, y ) = x ∨ y = x + y − xy ، AND( x, y ) = x ∧ y = xy‬ﻭ ‪XOR( x, y ) = x ⊕ y = x + y − 2 xy‬‬ ‫ﺣﺎﻝ ﺗﻤﺎﻡ ﻣﺪﺍﺭﻫﺎﻳﻲ ﻛﻪ ﺗﻨﻬﺎ ﺷﺎﻣﻞ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﺑﺎ ﺍﻳﻦ ﺭﻭﺵ ﻗﺎﺑﻞ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻣﻲﺑﺎﺷﻨﺪ‪.‬‬ ‫ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﺗﻮﺍﺑﻊ ﺟﺒﺮﻱ‪-‬ﺑﻮﻟﻲ ﻧﻴﺰ ﻣﻲﺗﻮﺍﻥ ﺍﺯ ﻓﺮﻣﻮﻟﻬﺎﻱ ﺑﺎﻻ ﺑﺮﺍﻱ ﻣﺪﻝ ﻛﺮﺩﻥ ﻗﺴﻤﺖ ﺑـﻮﻟﻲ ﻣـﺪﺍﺭ ﺍﺳـﺘﻔﺎﺩﻩ‬ ‫ﻛﺮﺩ ﻭ ﺗﻨﻬﺎ ﻧﻜﺘﻪ ﻣﺒﻬﻢ ﺩﺭ ﺍﻳﻦ ﻧﻤﺎﻳﺶ ﻫﻨﮕﺎﻣﻲ ﺍﺳﺖ ﻛﻪ ﺑﺮ ﺍﺛﺮ ﻗﻮﺍﻋﺪ ﺟﺒﺮﻱ ﺑـﺮﺍﻱ ﻳﻜـﻲ ﺍﺯ ﻣﺘﻐﻴﺮﻫـﺎﻱ ﺑﻴﺘـﻲ‬ ‫ﺗﻮﺍﻥ ﺑﺰﺭﮔﺘﺮ ﺍﺯ ﺻﻔﺮ ﺗﻮﻟﻴﺪ ﺷﻮﺩ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﻮﺍﺭﺩ ﺍﺛﺒﺎﺕ ﻣﻲﺷﻮﺩ ﻛﻪ ﻛـﺎﻓﻲ ﺍﺳـﺖ ﺗﻤـﺎﻡ ‪ xk‬ﻫـﺎﻱ ﻣﻮﺟـﻮﺩ ﺩﺭ‬ ‫ﻋﺒﺎﺭﺕ ﺑﻪ ‪ x‬ﺗﺒﺪﻳﻞ ﺷﻮﺩ]‪ [۲۴‬ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﻗﺎﻋﺪﻩﻱ ﺿﺮﺏ ﺩﻭ ‪ TED‬ﺑﺮﺍﺳﺎﺱ ﻳﻚ ﻣﺘﻐﻴﺮ ﺑـﻮﻟﻲ ‪ x‬ﺑـﻪ ﺻـﻮﺭﺕ‬ ‫ﺯﻳﺮ ﺑﺎﺯﻧﻮﻳﺴﻲ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪MULT : q ← (u.v) :‬‬ ‫)‪h( x) = f ( x).g ( x‬‬ ‫])‪= [ f (0) + xf ′(0)].[ g (0) + xg ′(0‬‬ ‫])‪= [ f (0) g (0)] + x[ f ′(0) g (0) + g ′(0) f (0) + f ′(0) g ′(0‬‬ ‫‪ -۵-۱-۴‬ﻛﺎﺭﺑﺮﺩ‪ TED‬ﺩﺭ ﺩﺭﺳﺘﻲ ﻳﺎﺑﻲ‬ ‫ﺍﻭﻟﻴﻦ ﻛﺎﺭﺑﺮﺩ ‪ TED‬ﺩﺭ ﺩﺭﺳﺘﻲﻳﺎﺑﻲ‪ ،‬ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺁﻥ ﺩﺭ ﻭﺍﺭﺳﻲ ﻫﻢ ﺍﺭﺯﻱ ﺩﻭ ﻣﺪﺍﺭ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺷﻜﻞ ‪ ۴-۴‬ﻧﺸـﺎﻥ‬ ‫ﺩﻫﻨﺪﻩ ﻱ ﺩﻭﻣﺪﺍﺭ ﻣﻌﺎﺩﻝ ﺗﻮﺍﺑﻊ ‪ F1 = s1 ( A + B)( A − B) + (1 − s1 ) D‬ﻭ ) ‪F2 = s 2 D + (1 − s 2 )( A 2 − B 2‬‬ ‫‪۵۹‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ﺍﺛﺒﺎﺕ ﻫﻢ ﺍﺭﺯﻱ ﺍﻳﻦ ﺩﻭﻣﺪﺍﺭ ‪ TED‬ﻣﻌﺎﺩﻝ ﺁﻥ ﺩﻭ ﻃﺮﺍﺣﻲ ﻣـﻲﺷـﻮﺩ‪ .‬ﻫﻤﺎﻧﮕﻮﻧـﻪ ﻛـﻪ ﺩﺭ ‪TED‬‬ ‫ﻣﺸﺨﺺ ﻣﻲﺑﺎﺷﺪ ﺩﻭ ﻣﺘﻐﻴﺮ ‪ A,B‬ﺑﻪ ﮔﻮﻧﻪﺍﻱ ﺗﻘﺴﻴﻢ ﺷﺪﻩﺍﻧﺪ ﻛﻪ ‪ a k‬ﻭ ‪ bk‬ﺑﻪ ﺻﻮﺭﺕ ﻳـﻚ ﻣﺘﻐﻴـﺮ ﺑﻴﺘـﻲ ﻣﺠـﺰﺍ‬ ‫ﻧﻤﺎﻳﺶ ﺩﺍﺩﻩ ﺷﻮﺩ‪ .‬ﻳﻌﻨﻲ ‪ ، A = 2 k +1 Ahi + 2 k a k + Alo‬ﺳﭙﺲ ﺑﺮﺭﺳﻲ ﻣﻲﺷﻮﺩ ﻛﻪ ﺁﻳﺎ ‪ TED‬ﺍﻳـﻦ ﺩﻭ ﻣـﺪﺍﺭ‬ ‫ﺍﻳﺰﻭﻣﻮﺭﻑ ﻣﻲﺑﺎﺷﻨﺪ ﻳﺎ ﻧﻪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۴-۴‬ﻣﺪﺍﺭ ﻣﻌﺎﺩﻝ ﺗﻮﺍﺑﻊ ‪ F1 = s1 ( A + B )( A − B ) + (1 − s1 ) D‬ﻭ ) ‪ F2 = s 2 D + (1 − s 2 )( A 2 − B 2‬ﻭ ‪ TED‬ﻣﻌﺎﺩﻝ‬ ‫ﺍﻣﺮﻭﺯﻩ ‪ TED‬ﺑﺮﺍﻱ ﺑﻴﺎﻥ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺳﻄﺢ ﺑﺎﻻﻳﻲ ﻣﺎﻧﻨﺪ ‪ ،FFT‬ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﺳﻄﺢ ﺑﺎﻻ ﻭ ﻫﻤﭽﻨـﻴﻦ ﺩﺭ‬ ‫ﭘﺮﻭﺳﻪﻱ ﺳﺎﺧﺖ ﺳﻄﺢ ﺑﺎﻻﻱ ﻣﺪﺍﺭ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ]‪.[۲۵‬‬ ‫‪CTED -۲-۴‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺨﺶ ﻗﺒﻞ ﮔﻔﺘﻪ ﺷﺪ ‪ TED‬ﻗﺎﺑﻠﻴﺖ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎ ﻭﻓﺸﺮﺩﻩﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﻭ ﺟﺒـﺮﻱ ﺭﺍ ﺩﺍﺭﺍ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﻟﻴﻜﻦ ﻧﻘﻄﻪﻱ ﺿﻌﻒ ﺍﻳﻦ ﻣﺪﻝ ﺳﻄﺢ ﺑﻴﺖ ﺑﻮﺩﻥ ﻗﺴﻤﺖ ﻛﻨﺘﺮﻟﻲ ﺁﻥ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻳﻌﻨﻲ ﺍﮔﺮ ﺩﺭ ﺗﻮﺻـﻴﻒ‬ ‫ﺳﻴﺴﺘﻢ ﻋﺒﺎﺭﺕ ﻛﻨﺘﺮﻟﻲ ﺳﻄﺢ ﻛﻠﻤﻪ ﻭﺟﻮﺩ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ‪ ،‬ﺑﺎﻳﺪ ﺍﺑﺘﺪﺍ ﺑﻪ ﺳﻄﺢ ﮔﻴﺖ ﺑﺮﺩﻩﺷـﻮﺩ ﻭ ﺳـﭙﺲ ﻋﺒـﺎﺭﺕ‬ ‫ﺑﻮﻟﻲ ﻣﻌﺎﺩﻝ ﺁﻥ ﺭﺍ ﺩﺭ ‪ TED‬ﻣﺪﻝ ﺷﻮﺩ‪ .‬ﺩﺭ ﺍﻳﻦ ﺑﺨﺶ ﻳﻚ ﺑﺴﻂ ﺑﺮﺍﯼ ‪ TED‬ﺍﺭﺍﺋﻪ ﻣﻲﺷﻮﺩ ﻛـﻪ ﺑـﺎ ﻛﻤـﻚ ﺁﻥ‬ ‫ﻣﻲﺗﻮﺍﻥ ﻳﻚ ﻣﺪﻝ ﻓﺸﺮﺩﻩ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﻛﻨﺘﺮﻟﻲ ﺷﺎﻣﻞ ‪ if‬ﻭ ‪ case‬ﺍﺭﺍﻳﻪ ﻣﻲﺷﻮﺩ ﻛﻪ ﻧﻴـﺎﺯﻱ ﺑـﻪ ﺑﺴـﻂ ﻣﺘﻐﻴـﺮ‬ ‫ﺳﻄﺢ ﻛﻠﻤﻪ ﺑﻪ ﺑﻴﺘﻬﺎﻱ ﺗﺸﻜﻴﻞ ﺩﻫﻨﺪﻩﻱ ﺁﻥ ﻧﺪﺍﺭﺩ]‪.[۲۶‬‬ ‫‪۶۰‬‬ ‫‪ -۱-۲-۴‬ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ‪CTED‬‬ ‫ﺣﺎﺻﻞ ﻋﺒﺎﺭﺗﻬﺎﻳﻲ ﻛﻪ ﺷﺮﻭﻁ ﻃﺮﺍﺣﻲ ﺭﺍﻣﻲﺳﺎﺯﻧﺪ ﺑﻪ ﺻﻮﺭﺕ ﺑﻴﺘﻬﺎﻳﻲ ﻣﻲﺑﺎﺷﻨﺪ ﻛﻪ ﻣﻲﺗﻮﺍﻥ ﺁﻧﻬـﺎ ﺭﺍ ﺑـﺎ ﻛﻤـﻚ‬ ‫‪ TED‬ﺑﻮﻟﻲ ﻧﻤﺎﻳﺶ ﺩﺍﺩ‪ .‬ﭘﺲ ﺗﻨﻬﺎ ﻧﻜﺘﻪﺍﻱ ﻛﻪ ﺑﺮﺍﻱ ﺑﺴﻂ ‪ TED‬ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﺍﺿﺎﻓﻪ ﻛﺮﺩﻥ ﮔﺮﻩﻫﺎﻳﻲ ﻣـﻲﺑﺎﺷـﺪ‬ ‫ﻛﻪ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﺭﺍ ﺑﻪ ﻳﻚ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ﻣﺘﻨﺎﻇﺮ ﻣﻲﻛﻨﻨﺪ‪ .‬ﻣﻲﺗﻮﺍﻥ ﻧﺸﺎﻥ ﺩﺍﺩ ﻛﻪ ﻛﻠﻴﻪ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﻣﻘﺎﻳﺴـﻪﺍﻱ ﺭﺍ‬ ‫ﻣﻲﺗﻮﺍﻥ ﺑﺎ ﺩﻭ ﻋﻤﻠﮕﺮ '‪ '!= 0‬ﻭ '‪ ' < 0‬ﻭ ﻋﻤﻠﮕﺮﻫﺎﻱ ﺟﺒﺮ ﺑﻮﻝ ﻧﻤﺎﻳﺶ ﺩﺍﺩ‪.‬‬ ‫ﺷﻜﻞ‪ ۵-۴‬ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﻃﺮﻳﻘﻪ ﺑﺎﺯﻧﻮﻳﺴﻲ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﯽ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻳﻚ ﻣﻘﺪﺍﺭﺩﻫﻲ ﻣﺸـﺮﻭﻁ ﺑـﻪ ﻳـﻚ‬ ‫ﻣﺘﻐﻴﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﺑﺎﺯﻧﻮﻳﺴﯽ ﺩﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ‪ CTED‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫)‪if (C ) o1 = f1 ( x1 , x 2 ,...‬‬ ‫)‪o1 = f 2 ( x1 , x 2 ,...‬‬ ‫‪else‬‬ ‫)‪o1 = C * f1 ( x1 , x 2 ,...) + (1 − C ) f 2 ( x1 , x 2 ,...‬‬ ‫)‪= cf ( x1 , x 2 ,...‬‬ ‫‪a.‬‬ ‫‪b.‬‬ ‫ﺷﮑﻞ ‪ -۵-۴‬ﺑﺎﺯﻧﻮﻳﺴﯽ ﻳﮏ ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﺩﺭ ‪CTED‬‬ ‫ﺩﺭ ﻗﺴﻤﺖ ﺍﻭﻝ ﺷﺮﻁ ﺑﺎ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ‪ C‬ﻧﺸﺎﻥ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﻗﺴﻤﺖ ﺩﻭ ِﻡ ﺷﻜﻞ‪ ،‬ﺑﺎﺯﻧﻮﻳﺴﻲ ﻋﺒـﺎﺭﺕ ﻗﺴـﻤﺖ‬ ‫ﺍﻭﻝ ﻣﻲﺑﺎﺷﺪ‪ TED .‬ﻧﻤﻲﺗﻮﺍﻧﺪ ﺍﻳﻦ ﺑﺎﺯﻧﻮﻳﺴﻲ ﺭﺍ ﻣﺪﻝ ﻛﻨﺪ‪ .‬ﺑﺮﺍﻱ ﻣﺪﻝ ﻛﺮﺩﻥ ﺍﻳﻦ ﻋﺒﺎﺭﺗﻬﺎ ﺩﻭ ﮔﺮﻩ ﺍﺿﺎﻓﻲ '=!'‬ ‫ﻭ '<' ﺑﺮﺍﻱ ‪ TED‬ﺗﻌﺮﻳﻒ ﻣﻲﺷﻮﺩ ﻛﻪ ﮔﺮﻩﻫﺎﻱ ﺷﺮﻃﻲ ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺍﻳﻦ ﮔﺮﻩﻫﺎ ﺩﺍﺭﺍﯼ ﺩﻭ ﻓﺮﺯﻧﺪ ﻣﻲﺑﺎﺷﻨﺪ‬ ‫ﻛﻪ ﺧﻮﺩ ﺁﻧﻬﺎ ﻧﻴﺰ ‪ CTED‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﮔﺮﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﺍﻳﻦ ﮔـﺮﻩ ﻣﻌـﺎﺩﻝ ﻋﺒـﺎﺭﺕ )‪ cf 0 ( x1 , x 2 ,...‬ﻭ ﻓﺮﺯﻧـﺪ ﺩﻭﻡ‬ ‫ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﻋﺒﺎﺭﺕ )‪ cf1 ( x1 , x 2 ,...‬ﺑﺎﺷﺪ ﻭﺧﻮﺩ ﮔﺮﻩ ﺑﺎ ‪ r_op‬ﻛﻪ ﻳﻜـﻲ ﺍﺯ ﺩﻭ ﺣﺎﻟـﺖ '=!' ﻭ '<' ﻣـﻲﺑﺎﺷـﺪ‬ ‫ﺑﺮﭼﺴﺐﺩﻫﻲ ﺷﺪﻩ ﺑﺎﺷﺪ‪ .‬ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﺍﻳﻦ ﮔﺮﻩ ﺑـﻪ ﺻـﻮﺭﺕ )‪(cf1 ( x1 , x 2 ,...) r _ op 0) + cf 0 ( x1 , x 2 ,...‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺩﺭ ‪ CTED‬ﮔﺮﻩﻫﺎﻱ ﺑﺮﮒ ﻓﻘﻂ ﺷﺎﻣﻞ ﻳﻚ ﻭ ﺻﻔﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ‪ CTED‬ﻳﻚ ﺗﺮﺗﻴﺐ ﺟﺪﻳﺪ ﺑـﺮﺍﻱ ﻣﺘﻐﻴﺮﻫـﺎ‬ ‫ﻣﻌﺮﻓﻲ ﺷﻮﺩ‪ .‬ﺑﻪ ﺍﻳﻦ ﺻﻮﺭﺕ ﻛﻪ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻌﻤﻮﻟﻲ ﺩﺍﺭﺍﻱ ﺑﺎﻻﺗﺮﻳﻦ ﺩﺭﺟﻪ ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺳﭙﺲ ﮔﺮﻩﻫـﺎﻱ ﺷـﺮﻃﻲ‬ ‫‪۶۱‬‬ ‫ﻭ ﭘﺲ ﺍﺯ ﺁﻧﻬﺎ ﮔﺮﻩﻫﺎﻱ ﺑﺮﮒ ﺩﺍﺭﺍﻱ ﺩﺭﺟﻪﻫﺎﻱ ﺑﻌﺪﻱ ﻫﺴﺘﻨﺪ‪ .‬ﺑﺮﺍﻱ ﺳﺎﺧﺖ ﻋﺒﺎﺭﺕ ‪ f1 > 0‬ﻳـﺎ ‪ f1 != 0‬ﮔـﺮﻩ‬ ‫ﺷﺮﻃﻲ ﻣﻨﺎﺳﺐ ﺩﺭﺭﻳﺸﻪﻱ ‪ CTED‬ﻗﺮﺍﺭ ﺩﺍﺩﻩﻣﻲﺷﻮﺩ‪ ،‬ﺳﭙﺲ ﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﺁﻥ ﺑﻪ ﺑﺮﮒ ﺻﻔﺮ ﻭ ﻓﺮﺯﻧﺪ ﻳﻜـﻢ ﺁﻥ‬ ‫ﺑﻪ ‪ CTED‬ﻣﻌﺎﺩﻝ ﻋﺒﺎﺭﺕ ‪ f1‬ﻣﺘﺼﻞ ﻣﯽﺷﻮﺩ‪ .‬ﺑﺮﺍﻱ ﺳـﺎﺧﺖ ﺭﻭﺍﺑـﻂ ﻣﻨﻄﻘـﻲ ﺑـﻴﻦ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﺷـﺮﻃﻲ ﻣﺎﻧﻨـﺪ‬ ‫ﻋﻤﻠﮕﺮﻫﺎﻱ ﺑﻮﻟﻲ ﺭﻓﺘﺎﺭ ﻣﻲﺷﻮﺩ‪ ،‬ﻳﻌﻨﻲ‪c1 & &c 2 = c1 * c 2 , c1 || c 2 = c1 + c 2 − c1.c 2 , !c1 = 1 − c1 :‬‬ ‫‪ -۲-۲-۴‬ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ ‪CTED‬‬ ‫ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ‪ CTED‬ﺩﻭ ﮔﺮﻩ ﺷﺮﻃﻲ ﺑﻴﺸﺘﺮ ﺍﺯ ‪ TED‬ﺩﺍﺭﺩ‪ .‬ﺑﺮﺍﻱ ﺍﻳﻦ ﺩﻭ ﻋﻤﻠﮕﺮ ﻧﻴـﺰ ﻗﻮﺍﻋـﺪ ﺗﺮﻛﻴﺒـﻲ ﻃﺮﺍﺣـﻲ‬ ‫ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺍﺑﺘﺪﺍ ﺑﺮﺍﻱ ﻣﻘﺎﻳﺴﻪ ﺩﻭ ‪ CTED‬ﺑﺎ ﺭﻳﺸﻪﻫﺎﻱ ‪ u‬ﻭ‪ v‬ﻗﻮﺍﻋﺪ ﺗﻌﺮﻳﻒ ﻣﻲﺷﻮﺩ‪:‬‬ ‫‪ CTED‬ﺑﺎ ﺭﻳﺸﻪ ‪ v‬ﺍﺯ ‪ CTED‬ﺑﺎ ﺭﻳﺸﻪ ‪ u‬ﺑﺰﺭﮔﺘـﺮ ﺍﺳـﺖ‪ ،‬ﺍﮔـﺮ‪-۲ ord (var(v )) > ord (var(u )) -۱ :‬‬ ‫)) ‪ ord (var(v)) = ord (var(u‬ﻭ ﺗﻌﺪﺍﺩ ﻓﺮﺯﻧﺪﺍﻥ ‪ v‬ﺍﺯ ﺗﻌﺪﺍﺩ ﻓﺮﺯﻧﺪﺍﻥ ‪ u‬ﺑﻴﺸﺘﺮ ﺑﺎﺷـﺪ‪ -۳ .‬ﺩﺭﺟـﻪ ﻣﺘﻐﻴﺮﻫـﺎ ﻭ‬ ‫ﺗﻌﺪﺍﺩ ﻓﺮﺯﻧﺪﺍﻥ ﺩﻭﮔﺮﻩ ‪ u‬ﻭ ‪ v‬ﺑﺮﺍﺑﺮ ﺑﺎﺷﻨﺪ‪ ،‬ﻭﻟﻲ ﻳﻚ‪ k‬ﻭﺟﻮﺩ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ ﻛﻪ ﻓﺮﺯﻧﺪ ‪k‬ﺍﻡ ﮔـﺮﻩ ‪ v‬ﺍﺯ ﻓﺮﺯﻧـﺪ ‪k‬ﺍﻡ‬ ‫ﮔﺮﻩ ‪ u‬ﺑﺰﺭﮔﺘﺮ ﺑﺎﺷﺪ ﻭ ﻓﺮﺯﻧﺪﺍﻥ ﻗﺒﻠﯽ ﺩﻭ ﮔﺮﻩ ﺑﺎ ﻫﻢ ﺑﺮﺍﺑﺮ ﺑﺎﺷﻨﺪ‪.‬‬ ‫ﺣﺎﻝ ﻗﻮﺍﻋﺪ ﺯﻳﺮ ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ‪ v‬ﻳﻚ ﮔﺮﻩ ﺷﺮﻃﻲ ﻭ ‪ u‬ﻳﮏ ﮔﺮﻩ ﺩﻟﺨﻮﺍﻩ ﺑﺎﺷـﺪ‪ ،‬ﺑـﻪ ﻗﻮﺍﻋـﺪ ﺟﻤـﻊ ﻭ ﺿـﺮﺏ‬ ‫ﺍﺿﺎﻓﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱‬ﻗﺎﻋﺪﻩ ﺟﻤﻊ‪ :‬ﺍﮔﺮ ‪ CTED‬ﺑﺎ ﺭﻳﺸﻪ ‪ v‬ﺑﺰﺭﮔﺘـﺮ ﺍﺯ ‪ CTED‬ﺑـﺎ ﺭﻳﺸـﻪ ‪ u‬ﺑﺎﺷـﺪ‪) q .‬ﺭﻳﺸـﻪﻱ ‪CTED‬‬ ‫ﺣﺎﺻﻞ( ﮔﺮﻫﻲ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻓﺮﺯﻧﺪ ﺻﻔﺮﺍﻡ ﺁﻥ ﺣﺎﺻﻞ ﺟﻤﻊ ﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﮔـﺮﻩ ‪ v‬ﻭ ﮔـﺮﻩ ‪ u‬ﺧﻮﺍﻫـﺪ‬ ‫ﺑﻮﺩ ﻭ ﻓﺮﺯﻧﺪ ﺍﻭﻝ ﺁﻥ ﻓﺮﺯﻧﺪ ﺍﻭﻝ ﮔﺮﻩ ‪.v‬‬ ‫‪ -۲‬ﻗﺎﻋﺪﻩ ﺿﺮﺏ‪ :‬ﺍﮔﺮ ‪ CTED‬ﺑﺎ ﺭﻳﺸﻪ ‪ v‬ﺑﺰﺭﮔﺘﺮ ﺍﺯ ‪ CTED‬ﺑﺎ ﺭﻳﺸﻪ ‪ u‬ﺑﺎﺷﺪ‪ q ،‬ﻫﻤﺎﻥ ‪ v‬ﺧﻮﺍﻫـﺪ ﺑـﻮﺩ‬ ‫ﻛﻪ ﻓﺮﺯﻧﺪﺍﻥ ﺁﻥ ﺩﺭ ‪ u‬ﺿﺮﺏ ﺷﺪﻩﺍﻧﺪ‪ .‬ﺩﺭﺻﻮﺭﺗﻲ ﻛﻪ ‪ CTED‬ﺑﺎ ﺭﻳﺸﻪ ‪ u‬ﺑﺰﺭﮔﺘﺮ ﺍﺯ ‪ CTED‬ﺑﺎ ﺭﻳﺸـﻪ‬ ‫‪ v‬ﺑﺎﺷﺪ‪ ،‬ﻃﺮﻳﻘﻪ ﻣﺤﺎﺳﺒﻪ ﺑﻪ ﻫﻤﺎﻥ ﺭﻭﺵ ﻗﺒﻠﻲ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪.‬‬ ‫‪۶۲‬‬ ‫ﻳﻚ ‪ CTED‬ﻧﺮﻣﺎﻝ ﻣﻲﺑﺎﺷﺪ ﺍﮔﺮ ﻭ ﻓﻘﻂ ﺍﮔﺮ ﮔﺮﻩﻫﺎﻱ ﺑﺮﮒ ﺁﻥ ﻓﻘﻂ ‪ 0‬ﻭ‪ 1‬ﻭ ﻭﺯﻥ ﺭﻭﻱ ﻳﺎﻟﻬﺎﻱ ﻫﺮ ﮔﺮﻩ ﻧﺴﺒﺖ‬ ‫ﺑﻪ ﻫﻢ ﺍﻭﻝ ﺑﺎﺷﻨﺪ‪ .‬ﻳﻌﻨﻲ ﺩﺭ ﻓﺮﺁﻳﻨﺪ ﻧﺮﻣﺎﻝ ﺳﺎﺯﻱ ‪ CTED‬ﺏ‪.‬ﻡ ﻡ ﺿﺮﺍﻳﺐ ﻳﺎﻟﻬﺎﻱ ﻳﮏ ﮔﺮﻩ ﮔﺮﻓﺘﻪ ﻣـﻲﺷـﻮﺩ ﻭ‬ ‫ﺩﺭ ﺿﺮﻳﺐ ﻳﺎﻝ ﻭﺍﺭﺩ ﺷﻮﻧﺪﻩ ﺑﻪ ﮔﺮﻩ ﺿﺮﺏ ﻣﻲﮔﺮﺩﺩ‪ .‬ﺩﺭ ‪ CTED‬ﻳﻚ ﺍﺳﺘﺜﻨﺎ ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﻭ ﺁﻥ ﺣﺬﻑ ﺿـﺮﻳﺐ‬ ‫ﻳﺎﻝ ﻓﺮﺯﻧﺪ ﺍﻭﻝ ﮔﺮﻩ ﺷﺮﻃﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺯﻳﺮﺍ ﺍﮔﺮ ‪ f 0‬ﺗﺎﺑﻊ ﻓﺮﺯﻧﺪ ﺻﻔﺮﻡ ﮔﺮﻩ ﻭ ‪ f1‬ﺗﺎﺑﻊ ﻓﺮﺯﻧﺪ ﻳﻜﻢ ﮔﺮﻩ ﺑﺎﺷﺪ ﻭ‬ ‫)‪ c‬ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ( ﺍﺛﺒﺎﺕ ﻣﻲﺷﻮﺩ ﮐﻪ ﻣﻲﺗﻮﺍﻥ ﺛﺎﺑﺖ ‪ c‬ﺭﺍ ﺣﺬﻑ ﻛﺮﺩ‪:‬‬ ‫‪( f1 r _ op 0) + f 0 = (c * f 2 r _ op 0) + f 0 = ( f 2 r _ op 0) + f 0‬‬ ‫ﺛﺎﺑﺖ ﻣﻲﺷﻮﺩ ﻛﻪ ﻳﻚ ‪ TED‬ﻛﺎﻫﺶ ﻳﺎﻓﺘﻪ ﻭ ﻧﺮﻣﺎﻝ ﻳﻚ ﻧﻤﺎﻳﺶ ﻳﻜﺘﺎ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺗﻬﺎﯼ ﺟﺒـﺮﻱ‪-‬ﺑـﻮﻟﻲ–ﺷـﺮﻃﻲ‬ ‫ﻣﻲﺑﺎﺷﺪ]‪.[۲۶‬‬ ‫‪۶۳‬‬ ‫‪ -۵‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﭘﺮﻭﮊﻩ‬ ‫ﺩﺭ ﺍﻳﻦ ﻓﺼﻞ ﺑﻪ ﺗﻮﺿﻴﺢ ﭘﻴﺎﺩﻩﺳﺎﺯﻳﻬﺎﻳﻲ ﻛﻪ ﺑﺮﺍﺳﺎﺱ ﻣﺪﻟﻬﺎﻱ ﺍﺭﺍﺋﻪ ﺷﺪﻩ ﺩﺭ ﻓﺼﻠﻬﺎﻱ ﻗﺒﻞ ﺍﻧﺠـﺎﻡ ﺷـﺪﻩ ﺍﺳـﺖ‬ ‫ﭘﺮﺩﺍﺧﺘﻪﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺑﺨﺶ ‪ ۱-۵‬ﺑﻪ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺷﺒﻴﻪﺳﺎﺯ ﺳﻄﺢ ﮔﻴﺖ ﻣﺪﺍﺭﻫﺎ ﭘﺮﺩﺍﺧﺘﻪ ﻣﻲﺷﻮﺩ ﻛـﻪ ﺑـﻪ ﻋﻨـﻮﺍﻥ‬ ‫ﺵ ﭘﻴﺎﺩﻩﺳـﺎﺯ ِ‬ ‫ﭘﺎﻳﻪ ﺍﺻﻠﻲ ﺩﺭ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﻧﻬﺎﻳﻲ ﻣﺪﻝ ﺟﺪﻳﺪ ﺍﺳﺘﻔﺎﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺩﺭ ﺑﺨﺶ ‪ ۲-۵‬ﺭﻭ ِ‬ ‫ﻱ ‪،CTED‬‬ ‫ﺑﺮﺍﻱ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺗﻮﺻﻴﻒ ﻣﺪﺍﺭ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺍﺭﺍﻳﻪ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺗﻮﺻﻴﻒ ﻣـﻮﺭﺩ ﺑﺮﺭﺳـﻲ ﺑﺎﻳـﺪ‬ ‫ﺩﺍﺭﺍﻱ ﺍﻟﮕﻮﻱ ﺧﺎﺻﻲ ﺑﺎﺷﺪ ﻛﻪ ﺩﺍﺭﺍﯼ ﺷﺒﺎﻫﺘﻬﺎﯼ ﺑﺴﻴﺎﺭﻱ ﺑﻪ ﺯﺑﺎﻥ ﺗﻮﺻﻴﻒ ﺳـﺨﺖ ﺍﻓـﺰﺍﺭ ‪ Verilog‬ﺭﻓﺘـﺎﺭﻱ‪،‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺗﻮﺻﻴﻒ ﺗﻌﺪﺍﺩﻱ ﺑﻠﻮﻙ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﻗﺮﺍﺭ ﺩﺍﺭﺩ ﻛﻪ ﺑﻪ ﺻﻮﺭﺕ ﻫﻢﺭﻭﻧﺪ ﺑﺎ ﻫﻢ‬ ‫ﺍﺟﺮﺍ ﻣﻲ ﮔﺮﺩﻧﺪ‪ .‬ﺷﺒﻴﻪﺳﺎﺯ ﭘﻴﺎﺩﻩﺳﺎﺯﻱﺷﺪﻩ ﺑﺮﺍﻱ ﻫﺮ ﻳﻚ ﺍﺯ ﺑﻠﻮﻛﻬﺎﻱ ﺗﻮﺻـﻴﻒ ﺳـﻄﺢ ﺍﻧﺘﻘـﺎﻝ ﺛﺒـﺎﺕ‪CTED ،‬‬ ‫ﺧﺮﻭﺟﻴﻬﺎ ﺭﺍ ﺑﺮﺣﺴﺐ ﻭﺭﻭﺩﻳﻬﺎ ﺑﺪﺳﺖ ﻣﻲﺁﻭﺭﺩ‪ .‬ﺳﭙﺲ ﺍﻳﻦ ﺑﻠﻮﻛﻬﺎ ﺑﺮﺣﺴﺐ ﻓﺎﺻﻠﻪ ﺗـﺎ ﻭﺭﻭﺩﻱ ﻣـﺪﺍﺭ ﻣﺮﺗـﺐ‬ ‫ﻣﻲﺷﻮﻧﺪ ﻭ ﻭﺭﻭﺩﻳﻬﺎ ﺑﻪ ﺻﻮﺭﺕ ﻧﻤﺎﺩﻳﻦ ﺑﻪ ﺑﻠﻮﻛﻬﺎ ﺍﺭﺳﺎﻝ ﻣﻲﺷﻮﺩ ﻭ ﺧﺮﻭﺟﻲ ﻧﻤﺎﺩﻳﻦ ﻫﺮ ﺑﻠﻮﻙ ﺑﺎ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ‬ ‫‪ CTED‬ﺧﺮﻭﺟﻴﻬﺎ ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ‪ .‬ﺩﺭ ﺗﻮﺻﻴﻒ ﻛﻠﻲ ﺳﻴﺴﺘﻢ ﻣﻲﺗﻮﺍﻧﻴﻢ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎﻳﻲ ﺑﺎ ﻧـﺎﻡ ‪ register‬ﺍﺳـﺘﻔﺎﺩﻩ‬ ‫ﻛﻨﻴﻢ‪ ،‬ﻛﻪ ﺩﺭ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻧﻬﺎﻳﻲ ﺑﺎ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﺟﺎﻳﮕﺰﻳﻦ ﻣﻲﺷﻮﻧﺪ ﺍﻳﻦ ﻣﺘﻐﻴﺮﻫﺎ ﻗﺎﺑﻠﻴﺖ ﺫﺧﻴﺮﻩ ﺣﺎﻟﺖ ﻓﻌﻠـﻲ‬ ‫ﺳﻴﺴﺘﻢ ﺭﺍ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷﻨﺪ ﻭ ﺑﻪ ﻋﻨﻮﺍﻥ ﺧﺮﻭﺟﻲ ﻭ ﻭﺭﻭﺩﻱ ﺛﺎﻧﻮﻳﻪ ﺳﻴﺴﺘﻢ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﻧﺪ‪.‬‬ ‫‪۶۴‬‬ ‫‪ -۱-۵‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺷﺒﻴﻪﺳﺎﺯ ﻣﻨﻄﻘﻲ ﻭ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﺳﻄﺢ ﮔﻴﺖ‬ ‫ﺩﺭﺍﻳﻦ ﻗﺴﻤﺖ ﻳﻚ ﺷﺒﻴﻪ ﺳﺎﺯ ﻣﻨﻄﻘﻲ ﺑﺮﺍﻱ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﮔﻴﺖ ﻃﺮﺍﺣﻲ ﻣﻲﺷـﻮﺩ‪ .‬ﺍﻳـﻦ ﺷـﺒﻴﻪ ﺳـﺎﺯ ﻗﺎﺑﻠﻴـﺖ‬ ‫ﭘﺬﻳﺮﺵ ﮔﻴﺘﻬﺎﻱ ‪ NAND,AND,OR,XOR,NOR,NOT‬ﻭ ‪ XNOR‬ﺭﺍ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷـﺪ ﻭ ﺑـﻪ ﻋﻨـﻮﺍﻥ ﻋﻨﺼـﺮ‬ ‫ﺣﺎﻓﻈﻪ ﺍﺯ ‪ DFF‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﻓﺎﻳﻞ ﻭﺭﻭﺩﻱ ﺍﻳﻦ ﺷﺒﻴﻪ ﺳﺎﺯ ﺍﺑﺘﺪﺍ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺳﻴﺴﺘﻢ ﺗﻌﺮﻳﻒ ﻣـﻲﺷـﻮﻧﺪ‪.‬‬ ‫ﺳﭙﺲ ﺩﺭ ﺧﻂ ﺑﻌﺪﻱ ﺧﺮﻭﺟﻴﻬﺎﻱ ﺳﻴﺴﺘﻢ ﻭ ﺩﺭ ﺧﻂ ﺑﻌﺪﻱ ﺳﻴﻤﻬﺎﻱ ﻣﻴﺎﻧﻲ ﺗﻌﺮﻳﻒ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺳﭙﺲ ﮔﻴﺘﻬﺎ ﺑـﻪ‬ ‫ﺻﻮﺭﺕ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ﻧﺎﻡ ﮔﻴﺖ ﻭ ﺩﺍﺧﻞ ﭘﺮﺍﻧﺘﺰ ﺑﻪ ﺗﺮﺗﻴﺐ ﺧﺮﻭﺟﻲ ﻭ ﻭﺭﻭﺩﻳﻬﺎﻱ ﮔﻴﺖ ﻣﻌﺮﻓـﻲ ﻣـﻲﺷـﻮﻧﺪ‪ .‬ﺩﺭ‬ ‫ﺍﻳﻦ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺧﺮﻭﺟﻲ ﻫﺮﮔﻴﺖ‪ ،‬ﺑﻪ ﻋﻨﻮﺍﻥ ﻧﺎﻡ ﮔﻴـﺖ ﺍﺳـﺘﻔﺎﺩﻩ ﻣـﻲﺷـﻮﺩ‪ .‬ﻫـﺮ ﮔﻴـﺖ ﺑـﺎ ﺩﻭ ﺍﺷـﺎﺭﻩﮔـﺮ ﺑـﻪ‬ ‫ﻭﺭﻭﺩﻳﻬﺎﻱ ﺧﻮﺩ ﺍﺷﺎﺭﻩ ﻣﻲﮐﻨﺪ‪ .‬ﺩﺭ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﭘﺲ ﺍﺯ ﺁﻧﻜﻪ ﺗﻤﺎﻣﻲ ﮔﻴﺘﻬﺎ ﺩﺭ ﻟﻴﺴـﺖ ﮔﻴﺘﻬـﺎ ﺗﻌﺮﻳـﻒ ﺷـﺪﻧﺪ ﻭ‬ ‫ﻭﺭﻭﺩﻱ ﻭ ﺧﺮﻭﺟﻲ ﺁﻧﻬﺎ ﻣﺸﺨﺺ ﺷﺪ‪ ،‬ﺑﺮﺍﺳﺎﺱ ﻓﺎﺻﻠﻪ ﺗﺎ ﻭﺭﻭﺩﻱ ﻣﺮﺗﺐ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺗﻮﺟﻪ ﻛﻨﻴﺪ ﻛـﻪ ﺧﺮﻭﺟـﻲ‬ ‫‪ DFF‬ﻧﻴﺰ ﺑﻪ ﻋﻨﻮﺍﻥ ﻭﺭﻭﺩﻱ ﺛﺎﻧﻮﻳﻪ ﺳﻴﺴﺘﻢ ﺩﺭ ﻧﻈﺮ ﮔﺮﻓﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺍﺳـﺎﺱ ﻣﺮﺗـﺐ ﺷـﺪﻥ ﮔﻴﺘﻬـﺎ ﺑـﺪﻳﻦ ﮔﻮﻧـﻪ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻛﻪ ﺍﺑﺘﺪﺍ ﺑﻪ ﻭﺭﻭﺩﻳﻬﺎ ﺩﺭﺟﻪ ﺻﻔﺮ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺳـﭙﺲ ﺑـﻪ ﺻـﻮﺭﺕ ﺗﻜـﺮﺍﺭﻱ ﺗﻤـﺎﻡ ﮔﻴﺘﻬـﺎ ﺑﺮﺭﺳـﻲ‬ ‫ﻣﻲﺷﻮﻧﺪ ﻭ ﺩﺭﺟﻪ ﺧﺮﻭﺟﻲ ﮔﻴﺘﻲ ﻛﻪ ﺗﻤﺎﻡ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺁﻥ ﺩﺭﺟﻪﺑﻨﺪﻱ ﺷـﺪﻩﺍﺳـﺖ‪ ،‬ﺑﺮﺍﺑـﺮ ﺑـﺎ ﻣـﺎﻛﺰﻳﻤﻢ ﺩﺭﺟـﻪ‬ ‫ﻭﺭﻭﺩﻳﻬﺎﯼ ﮔﻴﺖ ﺑﻌﻼﻭﻩ ﻳﻚ ﻗﺮﺍﺭ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﺩﺭ ﺍﻳﻦ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺑﻪ ﺻﻮﺭﺕ ﻣﺒﺘﻨﻲ ﺑـﺮ ﺭﻭﻳـﺪﺍﺩ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺑﺪﻳﻦ ﺻﻮﺭﺕ ﻛﻪ ﻳﻚ ﻟﻴﺴﺖ ﺍﺯ ﺭﻭﻳﺪﺍﺩﻫﺎﻳﻲ ﻛﻪ ﺩﺭ ﻃﻮﻝ ﺯﻣﺎﻥ ﺍﺗﻔﺎﻕ ﻣﻲﺍﻓﺘﻨـﺪ‪ ،‬ﺳـﺎﺧﺘﻪ ﻣـﻲﺷـﻮﺩ‪.‬‬ ‫ﺍﻭﻟﻴﻦ ﺭﻭﻳﺪﺍﺩ ﺑﺮﺍﺳﺎﺱ ﺯﻣﺎﻥ ﺍﻧﺘﺨﺎﺏ ﻣﻲﺷﻮﺩ‪ ،‬ﺳﭙﺲ ﺗﻤﺎﻡ ﮔﻴﺘﻬﺎﻳﻲ ﻛﻪ ﺍﻳـﻦ ﺭﻭﻳـﺪﺍﺩ ﺩﺭ ﻭﺭﻭﺩﻱ ﺁﻧﻬـﺎ ﺍﺗﻔـﺎﻕ‬ ‫ﻣﻲﺍﻓﺘﺪ ﺑﺮ ﺍﺳﺎﺱ ﻧﻮﻉ ﮔﻴﺖ ﻭ ﻣﻘﺪﺍﺭ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺁﻥ ﺗﺤﻠﻴﻞ ﻣﻲﺷﻮﻧﺪ ﻭ ﻧﺘﻴﺠﻪﻱ ﺁﻥ ﺑﻪ ﺻـﻮﺭﺕ ﻳـﻚ ﺭﻭﻳـﺪﺍﺩ‬ ‫ﺟﺪﻳﺪ ﺩﺭ ﺧﺮﻭﺟﻲ ﮔﻴﺖ ﻣﺸﺨﺺ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﺭﻭﻳﺪﺍﺩ ﻫﻤﺮﺍﻩ ﺑﺎ ﺯﻣﺎﻥ ﺍﺗﻔﺎﻕ ﺁﻥ ﻛﻪ ﻭﺍﺑﺴﺘﻪ ﺑـﻪ ﺗـﺎﺧﻴﺮ ﮔﻴـﺖ‬ ‫ﻣﻲﺑﺎﺷﺪ ﺩﺭ ﻟﻴﺴﺖ ﺭﻭﻳﺪﺍﺩﻫﺎ ﺍﺿﺎﻓﻪ ﻣﻲﮔﺮﺩﺩ‪ .‬ﺭﻭﻳﺪﺍﺩﻫﺎ ﺩﺭ ﻟﻴﺴﺖ ﺑﺮﺣﺴﺐ ﺯﻣﺎﻥ ﻣﺮﺗﺐ ﺷﺪﻩﺍﻧﺪ‪ ،‬ﺩﺭ ﺻـﻮﺭﺗﻲ‬ ‫ﻛﻪ ﺩﻭﻳﺎ ﭼﻨﺪ ﺭﻭﻳﺪﺍﺩ ﺩﺭ ﻳﻚ ﺯﻣﺎﻥ ﻭﺍﺣﺪ ﻭﺍﻗﻊ ﺷﻮﻧﺪ ﺗﺮﺗﻴﺐ ﺍﺟﺮﺍ ﻭﺍﺑﺴﺘﻪ ﺑﻪ ﺩﺭﺟﻪ ﺳـﻴﻤﻲ ﻣـﻲﺑﺎﺷـﺪ ﻛـﻪ ﺁﻥ‬ ‫ﺭﻭﻳﺪﺍﺩ ﺭﻭﻱ ﺁﻥ ﺍﺗﻔﺎﻕ ﻣﻲﺍﻓﺘﺪ‪ .‬ﺩﺭﺣﻘﻴﻘﺖ ﺩﺭ ﺍﻳﻦ ﮔﻮﻧﻪ ﻣﻮﺍﻗﻊ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯ ﺍﺯ ﻣﻔﻬﻮﻡ ﺯﻣـﺎﻥ ‪ δ‬ﻛـﻪ ﺩﺭ ﺯﺑﺎﻧﻬـﺎﻱ‬ ‫‪۶۵‬‬ ‫ﺗﻮﺻﻴﻒ ﺳﺨﺖ ﺍﻓﺰﺍﺭ ﻣﺎﻧﻨﺪ ‪ VHDL‬ﻣﻄﺮﺡ ﺷﺪﻩ ﺍﺳﺖ‪ ،‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﻛﻨﺪ‪.‬‬ ‫ﺩﺭ ﺍﺩﺍﻣﻪ ﺑﺎ ﺍﻓﺰﻭﺩﻥ ﺟﺪﻭﻝ ﺩﺭﺳﺘﻲ ﻧﻤﺎﺩﻳﻦ ﻫﺮ ﮔﻴﺖ ﺑﻪ ﻣﺮﺣﻠﻪ ﺗﺤﻠﻴﻞ ﺧﺮﻭﺟﻲ ﮔﻴﺘﻬـﺎ ﺷـﺒﻴﻪﺳـﺎﺯ ﻣﻨﻄﻘـﻲ ﺑـﻪ‬ ‫ﺷﺒﻴﻪﺳﺎﺯ ﻧﻤﺎﺩﻳﻦ ﺗﺒﺪﻳﻞ ﻣﻲﺷﻮﺩ‪ .‬ﺑﺮﺍﻱ ﺍﻳﻨﻜﺎﺭ ﺩﺭ ﻣﺮﺣﻠﻪ ﻣﺤﺎﺳﺒﻪﻱ ﺧﺮﻭﺟﻲ ﻫﺮ ﮔﻴﺖ ﺑﺮ ﺣﺴـﺐ ﻭﺭﻭﺩﻳﻬـﺎﻱ‬ ‫ﺁﻥ ﺑﻪ ﺟﺎﻱ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺟﺪﻭﻝ ﺩﺭﺳﺘﻲ ﻛﻪ ﻓﻘﻂ ﻣﻘﺎﺩﻳﺮ ﺛﺎﺑﺖ ﺑﻮﻟﻲ ﺭﺍ ﺩﺭﻳﺎﻓﺖ ﻣﻲﻛﻨﺪ‪ ،‬ﺍﻳﻦ ﺟﺪﻭﻝ ﺩﺭﺳﺘﻲ ﻛـﻪ‬ ‫ﺑﺮﺣﺴﺐ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻧﻤﺎﺩﻳﻦ ﻭ ﺛﺎﺑﺘﻬﺎﯼ ﺑﻮﻟﻲ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ‪ .‬ﺩﺭ ﺍﻳـﻦ ﺟـﺪﻭﻝ ﺭﻭﺷـﻬﺎﻱ‬ ‫ﺧﻼﺻﻪﺳﺎﺯﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺑﺎ ﺷﺮﺍﻳﻂ ﺧﺎﺹ ﻧﻴﺰ ﻣﺪﻧﻈﺮ ﻗﺮﺍﺭ ﮔﺮﻓﺘﻪ ﺷـﺪﻩ ﺍﺳـﺖ‪ .‬ﺑـﺮﺍﻱ ﻣﺜـﺎﻝ ﺩﺭ ﺟـﺪﻭﻝ‬ ‫ﺩﺭﺳﺘﻲ ﻧﻤﺎﺩﻳﻦ ‪ XOR‬ﺣﺎﺻﻞ ‪ XOR‬ﻳﻚ ﻣﺘﻐﻴﺮ ﺑﺎ ﺧﻮﺩﺵ ﻫﻤﻴﺸﻪ ﺻـﻔﺮ ﻭ ﺣﺎﺻـﻞ ‪ XOR‬ﺁﻥ ﺑـﺎ ﻧﻘـﻴﺾ‬ ‫ﺧﻮﺩ ﻫﻤﻴﺸﻪ ﻳﻚ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪ ،‬ﻳﺎ ﺩﺭ ﺣﺎﻟﺖ ﻧﻤﺎﺩﻳﻦ‪-‬ﻣﻨﻄﻘﯽ ﺣﺎﺻﻞ ‪ XOR‬ﻳﻚ ﻣﺘﻐﻴﺮ ﺑﺎ ﻳﻚ‪ ،‬ﺑﺮﺍﺑﺮ ﺑﺎ ﻧﻘـﻴﺾ‬ ‫ﺁﻥ ﻣﺘﻐﻴﺮ ﻭ ﺣﺎﺻﻞ ‪ XOR‬ﺁﻥ ﺑﺎ ﺻﻔﺮ‪ ،‬ﺧﻮﺩ ﻣﺘﻐﻴﺮ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪.‬‬ ‫ﻣﺜﺎﻝ‪ :۱-۵‬ﮐﺪ ﺯﻳﺮ ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﻳﻚ ﻣﺪﺍﺭﺳﺎﺩﻩ ﺩﺭ ﺳﻄﺢ ﮔﻴﺖ ﺑﺎ ﺍﻟﮕﻮﯼ ﻣﺨﺼﻮﺹ ﺍﻳﻦ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫;)‪Input(a, b‬‬ ‫;)‪Output(c‬‬ ‫;)‪Wire(d‬‬ ‫;)‪Xor(d, a, b‬‬ ‫;)‪And(c, d, a‬‬ ‫ﺣﺎﻝ ﺑﻪ ﻣﺪﺍﺭ ﺑﺎﻻ ﻟﻴﺴﺖ ﺭﻭﻳﺪﺍﺩﻫﺎﻱ ﺯﻳﺮ ﺍﻋﻤﺎﻝ ﻣﻲﺷﻮﺩ ﻭ ﻧﺘﻴﺠﻪ ﺧﺮﻭﺟﻲ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪.‬‬ ‫;)‪a(@0: 1,@2: 0‬‬ ‫;)‪b(@0: 1,@3: B‬‬ ‫‪d: @0 = 0, @2 = 1, @3 = B‬‬ ‫‪c: @0 = 0, @2 = 0‬‬ ‫‪ -۲-۵‬ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺷﺒﻴﻪﺳﺎﺯ ﻧﻤﺎﺩﻳﻦ ﺩﺭ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ‬ ‫ﺑﺮﺍﻱ ﺳﺎﺩﻩﺷﺪﻥ ﻋﻤﻞ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻓﺮﺽ ﻣﻲﺷﻮﺩ ﻛﻪ ﺩﺭ ﻣﺪﺍﺭ ﺗﺮﺗﻴﺒﻲ ﻣﺎ ﻓﻘﻂ ﻳﻚ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﻭﺟـﻮﺩ ﺩﺍﺭﺩ‪،‬‬ ‫ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺑﺎﻻﻱ ﻣﺪﺍﺭ ﺑﻪ ﺻﻮﺭﺕ ﺗﻌﺪﺍﺩﻱ ﺑﻠﻮﻙ ‪ always‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺑﻪ ﺻﻮﺭﺕ ﻫﻢ ﺭﻭﻧﺪ ﺑﺎ ﻳﻜـﺪﻳﮕﺮ‬ ‫ﻭﻇﻴﻔﻪﻱ ﺗﺸﻜﻴﻞ ﻗﺴﻤﺖ ﺗﺮﻛﻴﺒﻲ ﻣﺪﺍﺭ ﺭﺍ ﺩﺍﺭﻧﺪ‪ .‬ﻫﺮ ﻛﺪﺍﻡ ﺍﺯ ﺑﻠﻮﻛﻬﺎﻱ ‪ always‬ﺷﺎﻣﻞ ﻳـﻚ ﺳـﺮﻱ ﺩﺳـﺘﻮﺭﺍﺕ‬ ‫ﺗﺮﺗﻴﺒﻲ ﻣﻲﺑﺎﺷﻨﺪ ﻛﻪ ﺑﺮﺍﻱ ﻣﺤﺎﺳﺒﻪ ﺧﺮﻭﺟﻲ ﺑﻠﻮﻙ ﺑﻪ ﺗﺮﺗﻴﺐ ﻗﺮﺍﺭ ﮔﺮﻓﺘﻦ ﺩﺭ ﺑﻠﻮﮎ ﺍﺟﺮﺍ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺍﻟﮕﻮﻳﻲ ﻛﻪ‬ ‫‪۶۶‬‬ ‫ﺩﺭ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﺑﻪ ﻋﻨﻮﺍﻥ ﺍﻟﮕﻮﻱ ﻣﻌﺮﻓﻲ ﻳﻚ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺑﻪ ﺷـﺒﻴﻪ ﺳـﺎﺯ ﺍﺳـﺘﻔﺎﺩﻩ ﺷـﺪﻩ ﺍﺳـﺖ‬ ‫ﻫﻤﺎﻧﻨﺪ ﺯﺑﺎﻧﻬﺎﻱ ﺗﻮﺻﻴﻒ ﺳﺨﺖ ﺍﻓﺰﺍﺭ ‪ VHDL‬ﻭ ‪ Verilog‬ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺗﻨﻬﺎ ﺍﺯ ﻧﻈﺮ ‪ syntax‬ﺗﻔﺎﻭﺗﻬﺎﻳﻲ ﻭﺟﻮﺩ‬ ‫ﺩﺍﺭﺩ‪ .‬ﻛﻪ ﺩﺭ ﺍﺑﺘﺪﺍ ﺍﻳﻦ ﺍﻟﮕﻮ ﺷﺮﺡ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۱‬ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒﺎﺕ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻓﺎﻳﻞ ﺑﺎ ﭘﺴﻮﻧﺪ ‪ cir‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۲‬ﺩﺭ ﺧﻂ ﺍﻭﻝ ﺍﻳﻦ ﻓﺎﻳﻞ ﻭﺭﻭﺩﻳﻬﺎ ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺧﻂ ﺍﺑﺘﺪﺍ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ INPUT‬ﻗﺮﺍﺭ ﺩﺍﺭﺩ ﻭ‬ ‫ﺩﺭ ﺍﺩﺍﻣﻪ ﺩﺭ ﺩﺍﺧﻞ ﭘﺮﺍﻧﺘﺰ ﻭﺭﻭﺩﻳﻬﺎ ﻭﺗﻌﺪﺍﺩ ﺑﻴﺘﻬﺎﯼ ﺗﺸﮑﻴﻞ ﺩﻫﻨﺪﻩﻱ ﺁﻥ ﻛﻪ ﺩﺭﻭﻥ ﻳﻚ ﻗﻼﺏ ﻗـﺮﺍﺭ ﮔﺮﻓﺘـﻪ‬ ‫ﺍﺳﺖ‪ ،‬ﺍﺭﺍﻳﻪ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫‪ -۳‬ﺩﺭ ﺧﻂ ﺩﻭﻡ ﺧﺮﻭﺟﻴﻬﺎﻱ ﻣﺪﺍﺭ ﻫﻤﺎﻧﻨﺪ ﻭﺭﻭﺩﻳﻬﺎ ﻣﻌﺮﻓﻲ ﻣﻲ ﺷﻮﺩ‪ ،‬ﻭﻟﻲ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ﺍﻳﻦ ﺧﻂ ‪OUTPUT‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۴‬ﺩﺭ ﺧﻂ ﺑﻌﺪ ﻋﻨﺎﺻﺮ ﺣﺎﻓﻈﻪ ﺑﺎ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ register‬ﻣﺼﺮﻓﻲ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫‪ -۵‬ﺩﺭ ﺍﺩﺍﻣﻪ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴﺎﻧﻲ ﺳﻴﺴﺘﻢ ﻣﻌﺮﻓﻲ ﻣﻲ ﺷﻮﻧﺪ‪ ،‬ﺍﻳﻦ ﻣﺘﻐﻴﺮﻫـﺎ ﻛـﻪ ﻣﻌـﺎﺩﻝ ‪ variable‬ﻫـﺎ ﺩﺭ ‪VHDL‬‬ ‫ﻣﻲﺑﺎﺷﻨﺪ ﺑﺎ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ Wire‬ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫‪ -۶‬ﺩﺭ ﺑﺎﻗﻴﻤﺎﻧﺪﻩﻱ ﻓﺎﻳﻞ ﺑﻠﻮﻛﻬﺎﻱ ‪ always‬ﻛﻪ ﻣﻌﺎﺩﻝ ﺑﻠﻮﻛﻬـﺎﯼ ‪ process‬ﺩﺭ ‪ VHDL‬ﻭ ﺑﻠﻮﻛﻬـﺎﻱ‪always‬‬ ‫ﺩﺭ ‪ Verilog‬ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﻧﺪ‪ .‬ﻃﺮﻳﻘﻪ ﺗﻌﺮﻳﻒ ﺍﻳﻦ ﺑﻠﻮﻛﻬﺎ ﺑﻪ ﺍﻳﻦ ﺻﻮﺭﺕ ﻣﻲﺑﺎﺷـﺪ ﻛـﻪ ﺍﺑﺘـﺪﺍ‬ ‫ﻛﻠﻤﻪﻱ ﻛﻠﻴﺪﻱ ‪ Always‬ﺁﻭﺭﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺳﭙﺲ ﺁﺩﺭﺱ ﻭ ﻧﺎﻡ ﻓﺎﻳﻞ ﻣﺸﺨﺺﻛﻨﻨﺪﻩﻱ ﺑﻠـﻮﻙ ‪ always‬ﻭ‬ ‫ﺩﺭ ﺍﺩﺍﻣﻪ ﻟﻴﺴﺖ ﻭﺭﻭﺩﻳﻬﺎ ﻭ ﺧﺮﻭﺟﻴﻬﺎﻱ ﺑﻠﻮﻙ ‪ always‬ﺑﻴﺎﻥ ﻣﻲﺷﻮﺩ‪ .‬ﺳﺎﺧﺘﺎﺭ ﻓﺎﻳـﻞ ‪ always‬ﺩﺭ ﺍﺩﺍﻣـﻪ‬ ‫ﺍﺭﺍﺋﻪ ﺧﻮﺍﻫﺪ ﺷﺪ‪.‬‬ ‫‪ -۱-۲-۵‬ﺳﺎﺧﺖ ﻳﻚ ﻟﻴﺴﺖ ﮔﺮﻩﻫﺎﻱ ﺳﻴﺴﺘﻢ‬ ‫ﺍﻭﻟﻴﻦ ﮔﺎﻡ ﺩﺭ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺷﺒﻴﻪ ﺳﺎﺯ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﺍﻳﺠﺎﺩ ﻳﻚ ﻟﻴﺴﺖ )‪ (cunwire‬ﺍﺯ ﮔﺮﻩﻫﺎ ﻳﺎ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻮﺟـﻮﺩ‬ ‫ﺩﺭ ﺑﻠﻮﻙ ﺍﺻﻠﻲ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺍﻋﻀﺎ ﺍﻳﻦ ﻟﻴﺴﺖ ﻣـﻲﺗﻮﺍﻧﻨـﺪ ﻳﻜـﻲ ﺍﺯ ﺍﻧـﻮﺍﻉ ﻭﺭﻭﺩﻱ‪ ،‬ﺧﺮﻭﺟـﻲ‪ ،‬ﺳـﻴﻢ ﻳـﺎ‬ ‫‪۶۷‬‬ ‫ﺭﺟﻴﺴﺘﺮ ﺑﺎﺷﻨﺪ‪ .‬ﻫﺮ ﻛﺪﺍﻡ ﺍﺯ ﺍﻳﻦ ﺍﻧﻮﺍﻉ ﺩﺍﺭﺍﻱ ﻣﺸﺨﺼﺎﺗﻲ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺑﺎﻳﺪ ﺩﺭ ﻟﻴﺴﺖ ﻣﻮﺭﺩ ﻧﻈﺮ ﮔﻨﺠﺎﻧﺪﻩ ﺷـﻮﺩ‬ ‫ﻟﺬﺍ ﻳﻚ ﻛﻼﺱ ﺑﺎ ﻧﺎﻡ ‪ Node‬ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﺩ ﻛﻪ ﻧﻤﺎﻳﻨﺪﻩﻱ ﻫﺮ ﻳﻚ ﺍﺯ ﺍﻳﻦ ﮔﺮﻩﻫﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺩﺍﺧﻞ ﻛـﻼﺱ‬ ‫‪ Node‬ﺑﺮﺍﻱ ﻫﺮ ﻛﺪﺍﻡ ﺍﺯ ﻣﺸﺨﺼﻪﻫﺎ‪ ،‬ﻳﻚ ﻣﺘﻐﻴﺮ ﻧﺴﺒﺖ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺍﻭﻟﻴﻦ ﻣﺘﻐﻴﺮ ﻧﺎﻡ ﮔﺮﻩ ﻣـﻲﺑﺎﺷـﺪ ﺍﻳـﻦ‬ ‫ﻣﺘﻐﻴﺮ ﺍﺯ ﻧﻮﻉ ﺭﺷﺘﻪ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﺘﻐﻴﺮ ﺩﻭﻡ ﻣﻘﺪﺍﺭ ﮔﺮﻩ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﺍﻳﻦ ﻣﻘﺪﺍﺭ ﻣﻲﺗﻮﺍﻧـﺪ ﻳـﻚ‬ ‫ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﻳﺎ ﻣﺘﻐﻴﺮ ﻳﺎ ﺣﺘﻲ ﻳﻚ ﻋﺒﺎﺭﺕ ﺟﺒﺮﻱ – ﺑﻮﻟﻲ ﺑﺎﺷﺪ‪ .‬ﻣﺘﻐﻴﺮ ﺑﻌﺪﻱ ﻧﻮﻉ ﮔﺮﻩ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺑﻪ ﻫﺮ ﻳـﻚ ﺍﺯ‬ ‫ﺍﻧﻮﺍﻉ ﮔﺮﻩ ﻳﻚ ﻣﻘﺪﺍﺭ ﺻﺤﻴﺢ ﺧﺎﺹ ﻧﺴﺒﺖ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﻭﻇﻴﻔﻪ ﻣﺘﻐﻴﺮ ‪ degree‬ﻣﺸﺨﺺ ﻛﺮﺩﻥ ﻓﺎﺻـﻠﻪ ﺍﻳـﻦ‬ ‫ﮔﺮﻩ ﺗﺎ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ ﺍﻳﻦ ﻣﻘﺪﺍﺭ ﺑﺮﺍﻱ ﮔﺮﻩﻫﺎﻱ ﻧﻮﻉ ﻭﺭﻭﺩﻱ ﻭ ﺭﺟﻴﺴﺘﺮ ﻣﺴﺎﻭﻱ ﺻﻔﺮ ﻣﻲﺑﺎﺷـﺪ‪،‬‬ ‫ﺩﺭ ﺁﻏﺎﺯ ﺑﺮﺍﻱ ﮔﺮﻩﻫﺎﻱ ﺧﺮﻭﺟﻲ ﻭ ﺳﻴﻤﻬﺎﯼ ﻣﻴﺎﻧﯽ ﺍﻳﻦ ﻣﻘﺪﺍﺭ ‪ -۱‬ﻓـﺮﺽ ﻣـﻲﺷـﻮﺩ‪ .‬ﺁﺧـﺮﻳﻦ ﻣﺘﻐﻴـﺮ ﻛـﻼﺱ‬ ‫‪ Node‬ﻣﺘﻐﻴﺮ ‪ assigned‬ﺍﺯ ﻧﻮﻉ ﺑﻮﻝ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﺑﺮﺍﻱ ﮔﺮﻩﻫﺎﻱ ﺍﺯ ﻧﻮﻉ ﺭﺟﻴﺴﺘﺮ ﻭ ﺳﻴﻢ ﻭ ﺧﺮﻭﺟـﻲ‬ ‫ﻛﺎﺭﺍﻳﻲ ﺩﺍﺭﺩ ﻭ ﻣﺸﺨﺺ ﻣﻲﻛﻨﺪ ﻛﻪ ﺁﻳﺎ ﺍﻳﻦ ﮔﺮﻩﻫﺎ ﺑﻪ ﻋﻨﻮﺍﻥ ﺧﺮﻭﺟﻲ ﻳﻚ ﺑﻠﻮﻙ ‪ always‬ﻣﻌﺮﻓﻲ ﺷﺪﻩﺍﻧﺪ ﻳـﺎ‬ ‫ﻧﻪ ‪ .‬ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﻛﻤﻚ ﻣﻲﻛﻨﺪ ﺷﺒﻴﻪﺳﺎﺯ ﻣﺎﻧﻊ ﻣﻘﺪﺍﺭﺩﻫﻲ ﻣﺠﺪﺩ ﻳﻚ ﮔﺮﻩ ﺑﺸﻮﺩ‪.‬‬ ‫‪ -۲-۲-۵‬ﺳﺎﺧﺖ ﻟﻴﺴﺖ ﺑﻠﻮﻛﻬﺎﻱ ‪always‬‬ ‫ﺩﺭ ﮔﺎﻡ ﺑﻌﺪﻱ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻳﻚ ﻟﻴﺴﺖ ﺍﺯ ﺑﻠﻮﻛﻬﺎﻱ‬ ‫‪ always‬ﺗﻌﺮﻳـﻒ ﺷـﺪﻩ‪ ،‬ﺩﺭ ﺣﺎﻓﻈـﻪﻱ ﺷـﺒﻴﻪﺳـﺎﺯ ﺳـﺎﺧﺘﻪ‬ ‫ِ‬ ‫ﻣﻲﺷﻮﺩ‪ .‬ﺍﻋﻀﺎ ﺍﻳﻦ ﻟﻴﺴﺖ ﻣﺸﺨﺼﺎﺕ ﻫﺮ ﻳﻚ ﺍﺯ ‪ always‬ﻫﺎ ﺭﺍ ﺩﺭ ﺧﻮﺩ ﺫﺧﻴﺮﻩ ﻣﻲﻛﻨﻨﺪ‪ .‬ﺍﻳﻦ ﺍﻋﻀﺎ ﺑﺎ ﻛﻼﺱ‬ ‫‪ ALWAYSNODE‬ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﻛﻼﺱ ﻧﻴﺰ ﻣﺘﻐﻴﺮ ﻫﺎﻳﻲ ﺑﺮﺍﻱ ﺗﻮﺻـﻴﻒ ﻣﺸﺨﺼـﺎﺕ ﺑﻠﻮﻛﻬـﺎﻱ‬ ‫‪ always‬ﻗﺮﺍﺭ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﻣﺘﻐﻴﺮ ‪ filename‬ﻧﺎﻡ ﻭ ﻣﺴﻴﺮ ﻓﺎﻳﻞ ﺗﻮﺻـﻴﻒ ﻛﻨﻨـﺪﻩﻱ ﺑﻠـﻮﻙ ‪ always‬ﺭﺍ ﺩﺭ‬ ‫ﺧﻮﺩ ﺫﺧﻴﺮﻩ ﻣﻲﻛﻨﺪ‪ .‬ﺳﻪ ﻣﺘﻐﻴﺮ ﺩﻳﮕﺮ ﺑﻪ ﺻﻮﺭﺕ ﻟﻴﺴﺖ ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﻛﻪ ﻳﻜﻲ ﺍﺯ ﺁﻧﻬـﺎ ﺑـﻪ ﻭﺭﻭﺩﻳﻬـﺎﻱ ﺑﻠـﻮﻙ ﺩﺭ‬ ‫ﻟﻴﺴﺖ ‪ cunwires‬ﺍﺷﺎﺭﻩ ﻣﻲﻛﻨﺪ‪ .‬ﻟﻴﺴﺖ ﺩﻭﻡ ﺍﺷﺎﺭﻩﮔﺮﻫﺎﻳﻲ ﺑﻪ ﺧﺮﻭﺟﻴﻬﺎﻱ ﺑﻠﻮﻙ ﺭﺍ ﺫﺧﻴﺮﻩ ﻣﻲﻛﻨـﺪ ﻭ ﺍﻋﻀـﺎﺀ‬ ‫ﻟﻴﺴﺖ ﺳﻮﻡ ‪CTED‬ﻫﺎﯼ ﻃﺮﺍﺣﯽ ﺷﺪﻩ ﺑﺮﺍﯼ ﺑﻠﻮﻙ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﺘﻐﻴﺮ ﭘﺎﻳﺎﻧﯽ ﻣﺘﻐﻴﺮ ‪ place‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻓﺎﺻـﻠﻪﻱ‬ ‫ﺑﻠﻮﻙ ﺭﺍ ﺍﺯ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺳﻴﺴﺘﻢ ﺫﺧﻴﺮﻩ ﻣﻲﻛﻨﺪ‪ ،‬ﻛﺎﺭﺑﺮﺩ ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﺩﺭ ﻣﺮﺗﺐ ﮐﺮﺩﻥ ﺑﻠﻮﻛﻬﺎﻱ ‪ always‬ﻣﻲﺑﺎﺷـﺪ‬ ‫‪۶۸‬‬ ‫ﻛﻪ ﺑﺮﺍﻱ ﺗﺮﺗﻴﺐ ﺍﺟﺮﺍﻱ ﺁﻥ ﺩﺭ ﺣﻴﻦ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﺍﻫﻤﻴﺖ ﺯﻳـﺎﺩﻱ ﺩﺍﺭﺩ‪ .‬ﺩﺭ ﻫﻨﮕـﺎﻣﻲ ﻛـﻪ ﻟﻴﺴـﺖ ﺧﺮﻭﺟﻴﻬـﺎﻱ‬ ‫ﻼ ﻣﻘـﺪﺍﺭﺩﻫﻲ ﻧﺸـﺪﻩ ﺑﺎﺷـﺪ‪ ،‬ﻳﻌﻨـﻲ ﻣﺘﻐﻴـﺮ‬ ‫ﻛﻼﺱ ﺳﺎﺧﺘﻪ ﻣﻲﺷـﻮﺩ‪ ،‬ﺩﺭ ﺻـﻮﺭﺗﻲ ﻛـﻪ ﻳﻜـﻲ ﺍﺯ ﺧﺮﻭﺟﻴﻬـﺎ ﻗـﺒ ﹰ‬ ‫‪ Assigned‬ﺁﻥ ﺩﺭﺳﺖ ﺑﺎﺷﺪ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﻗﻄﻊ ﻣﻲﺷﻮﺩ ﺯﻳﺮﺍ ﻳﻚ ﮔﺮﻩ ﺩﻭﺑﺎﺭ ﻣﻘﺪﺍﺭﺩﻫﻲ ﺷـﺪﻩ ﺍﺳـﺖ‪ .‬ﭘـﺲ ﺍﺯ‬ ‫ﺗﺸﻜﻴﻞ ﻟﻴﺴﺖ ﻭﺭﻭﺩﻱ ﻭ ﺧﺮﻭﺟﻲ ﺑﻠﻮﻙ ﺑﺎ ﻛﻤﻚ ﺗﺎﺑﻊ ‪TED ،createalways‬ﻫﺎﻱ ﺁﻥ ﺑﻠﻮﻙ ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۳-۲-۵‬ﺳﺎﺧﺖ ‪ TED‬ﺑﻠﻮﻛﻬﺎﻱ‪always‬‬ ‫ﺍﻳﻦ ﻗﺴﻤﺖ ﺍﺯ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﺑﻪ ﻭﺳﻴﻠﻪ ﺗـﺎﺑﻊ ‪ createalways‬ﺍﻧﺠـﺎﻡ ﻣـﻲﮔـﺮﺩﺩ‪ .‬ﺩﺭ ﺍﻳـﻦ ﻣﺮﺣﻠـﻪ ﺷـﺒﻴﻪﺳـﺎﺯﻱ‬ ‫ﺑﻠﻮﻛﻬﺎﻱ ‪ always‬ﻛﻪ ﺑﻪ ﻣﻌﻨﺎﻱ ﻗﺴﻤﺖ ﺳﻄﺢ ﺑﺎﻻ ﻭ ﺗﺮﺗﻴﺒﻲ ﻃﺮﺡ ﻣﻲﺑﺎﺷﻨﺪ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﺑﻠﻮﻛﻬﺎﻱ ‪always‬‬ ‫ﺑﻪ ﺻﻮﺭﺕ ﻓﺎﻳﻠﻬﺎﻳﻲ ﺑﺎ ﻓﺮﻣﺖ ﻣﺸﺨﺺ ﺑﻪ ﺳﻴﺴﺘﻢ ﺩﺍﺩﻩ ﻣﻲﺷﻮﻧﺪ ﻭ ﺩﺭ ﺍﻧﺘﻬﺎ ﺗﻤﺎﻡ ﺧﺮﻭﺟﻴﻬﺎﻱ ﺍﻳـﻦ ﺑﻠـﻮﻙ ﺑـﻪ‬ ‫ﺻﻮﺭﺕ ﻳﻚ ﻟﻴﺴﺖ ﺍﺯ ‪TED‬ﻫﺎ ﻣﺸﺨﺺ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺍﻳﻦ ﺑﻠﻮﻛﻬﺎ ﻣﺘﺸﻜﻞ ﺍﺯ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺟﺒﺮﻱ‪ ،‬ﺑـﻮﻟﻲ‪ ،‬ﺟﺒـﺮﻱ‪-‬‬ ‫ﺑﻮﻟﻲ ﻭ ﺷﺮﻃﻲ ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﻛﻪ ﺑﺎ ﺍﺟﺮﺍﯼ ﺗﺮﺗﻴﺒﻲ ﺁﻧﻬﺎ ﺧﺮﻭﺟﻲ ﻣﻮﺭﺩ ﻧﻈﺮ ﺑﻪ ﺩﺳﺖ ﺧﻮﺍﻫﺪ ﺁﻣﺪ‪.‬‬ ‫‪ -۱-۳-۲-۵‬ﺍﻟﮕﻮﻱ ﻓﺎﻳﻠﻬﺎﻱ ‪:always‬‬ ‫ﻓﺎﻳﻠﻬﺎﻱ ‪ always‬ﺑﺎﻳﺪ ﭼﻨﺪ ﺍﻟﮕﻮﻱ ﺧﺎﺹ ﺭﺍ ﺭﻋﺎﻳﺖ ﻛﻨﻨﺪ ﻛﻪ ﺑﻪ ﻃﻮﺭ ﺧﻼﺻﻪ ﻣﻲﺗﻮﺍﻥ ﺁﻧﻬﺎ ﺭﺍ ﺑﺎ ﻗﻮﺍﻋـﺪ ﺯﻳـﺮ‬ ‫ﻣﻄﺮﺡ ﻛﺮﺩ‪:‬‬ ‫‪ -۱‬ﺍﻭﻟﻴﻦ ﺧﻂ ﺍﻳﻦ ﻓﺎﻳﻞ ﺑﺎﻳﺪ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ ALWAYS‬ﺑﺎﺷﺪ‪.‬‬ ‫‪ -۲‬ﺩﺭ ﺧﻄﻮﻁ ﺑﻌﺪﻱ ﺑﻪ ﺗﺮﺗﻴﺐ ﻭﺭﻭﺩﻱ‪ ،‬ﺧﺮﻭﺟﻲ ﻭ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺩﺍﺧﻠﻲ ﺑﻠﻮﻙ ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺑﺎﺷـﻨﺪ ﻳﻌﻨـﻲ‬ ‫ﺧﻂ ﺗﻌﺮﻳﻒ ﻛﻨﻨﺪﻩ ﺁﻧﻬﺎ ﺩﺭ ﻓﺎﻳﻞ‪،‬ﻣﺘﻨﺎﺳﺐ ﺑﺎ ﻧﻮﻉ ﺁﻥ‪ ،‬ﺑﻪ ﺗﺮﺗﻴﺐ ﺑﺎ ﻛﻠﻤﻪﻫﺎﻱ ﻛﻠﻴـﺪﻱ ‪Output ، Input‬‬ ‫ﻭ ‪ Wire‬ﺷﺮﻭﻉ ﺷﺪﻩ ﺑﺎﺷﻨﺪ‪ .‬ﭘﺲ ﺍﺯ ﺁﻥ ﭘﺮﺍﻧﺘﺰ ﺑﺎﺯﻣﻲﺷﻮﺩ ﻭ ﺩﺭ ﺁﻥ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣـﻮﺭﺩ ﻧﻈـﺮ ﺑـﺎﺣﺮﻭﻑ ﻭ‬ ‫ﺍﻋﺪﺍﺩ ﻣﺸﺨﺺ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺑﻌﺪ ﺍﺯ ﻫﺮ ﻣﺘﻐﻴﺮ ﺍﻧﺪﺍﺯﻩﻱ ﺁﻥ‪ ،‬ﮐﻪ ﻣﺸﺨﺼﻪ ﺑﻴﺖ ﻳﺎ ﮐﻠﻤﻪ ﺑﻮﺩﻥ ﺁﻥ ﻣﻲﺑﺎﺷـﺪ‬ ‫ﺩﺭﻭﻥ ﻗﻼﺏ ﻗﺮﺍﺭ ﺩﺍﺭﺩ‪ .‬ﺍﮔﺮ ﻣﺘﻐﻴﺮﻱ ﺍﻧﺪﺍﺯﻩ ﻧﺪﺍﺷﺘﻪ ﺑﺎﺷﺪ ﺑﻪ ﺻﻮﺭﺕ ﺑﻴﺖ ﺩﺭ ﻧﻈﺮ ﮔﺮﻓﺘﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪۶۹‬‬ ‫‪ -۳‬ﭘﺲ ﺍﺯ ﺁﻥ ﺩﺭ ﻓﺎﻳﻞ ﻋﺒﺎﺭﺍﺕ ﺳﺎﺯﻧﺪﻩﻱ ﺧﺮﻭﺟﻴﻬﺎ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ‪ .‬ﺩﺭ ﺍﻟﮕﻮﻱ ﺍﻳـﻦ ﻋﺒـﺎﺭﺍﺕ ﺍﺑﺘـﺪﺍ ﻣﺘﻐﻴـﺮ‬ ‫ﺣﺎﺻﻞ ﻋﺒﺎﺭﺕ ﺳﭙﺲ ﻛﺎﺭﺍﻛﺘﺮ "=" ﻭ ﺩﺭ ﺍﺩﺍﻣﻪ ﻋﺒﺎﺭﺕ ﺳﺎﺯﻧﺪﻩ ﺑﻪ ﺻﻮﺭﺕ ﻳﮏ ﻋﺒﺎﺭﺕ ﺟﺒﺮﯼ‪ ،‬ﺑـﻮﻟﯽ‬ ‫ﻳﺎ ﺟﺒﺮﯼ‪-‬ﺑﻮﻟﯽ ﺑﻴﺎﻥ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﻋﺒﺎﺭﺗﻬﺎﯼ ﺟﺒﺮﯼ ﻋﻤﻠﮕﺮﻫـﺎﯼ ﻣﺠـﺎﺯ ﺷـﺎﻣﻞ ﺑـﻪﺗـﻮﺍﻥ ﺭﺳـﺎﻧﺪﻥ"^"‪،‬‬ ‫ﺟﻤﻊ "‪ ،"+‬ﺿـﺮﺏ"*"‪ ،‬ﺗﻔﺮﻳـﻖ "‪ "-‬ﻭ ﻗﺮﻳﻨـﻪ "‪ "-‬ﻭ ﺩﺭ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﺑـﻮﻟﯽ ﻋﻤﻠﮕﺮﻫـﺎﻱ ﻣﺠـﺎﺯ ﺷـﺎﻣﻞ‪:‬‬ ‫‪ `@` XOR ،`|`OR ، `&`AND‬ﻭ‪ `~`NOT‬ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺩﺭ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﺟﺒـﺮﻱ‪-‬ﺑـﻮﻟﻲ ﺗﺮﻛﻴـﺐ ﺍﻳـﻦ‬ ‫ﻋﻤﻠﮕﺮﻫﺎ ﻣﺠﺎﺯ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺷﺒﻴﻪ ﺳﺎﺯ ﺍﻭﻟﻮﻳﺖﺑﻨﺪﻱ ﻋﺒﺎﺭﺍﺕ ﻣﻮﺭﺩ ﺗﻮﺟﻪ ﻗﺮﺍﺭﮔﺮﻓﺘـﻪﺷـﺪﻩﺍﺳـﺖ‪.‬‬ ‫ﻭﻟﻲ ﺩﺭ ﻧﻬﺎﻳﺖ ﭘﺮﺍﻧﺘﺰ ﺑﻨﺪﻱ ﻣﻨﺎﺳﺐ ﭘﻴﺸﻨﻬﺎﺩ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫‪ -۴‬ﺩﺭ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﺍﺑﺘﺪﺍ ﺷﺮﻁ ﺩﺭ ﻳﻚ ﺧﻂ ﻛﻪ ﺍﺑﺘﺪﺍﻱ ﺁﻥ ﺑﺎ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ IF‬ﻣﺸﺨﺺ ﺷـﺪﻩ ﺍﺳـﺖ‬ ‫ﺗﻌﺮﻳﻒ ﻣﻲﮔﺮﺩﺩ‪ ،‬ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﺑﺎﻳﺪ ﺩﺭﻭﻥ ﭘﺮﺍﻧﺘﺰ ﻗﺮﺍﺭ ﮔﻴﺮﺩ‪ .‬ﺑﺮﺍﻱ ﺍﺭﺗﺒﺎﻁ ﻣﻨﻄﻘﻲ ﺑﻴﻦ ﭼﻨـﺪ ﺷـﺮﻁ‬ ‫ﺍﺯ ﻫﻤﺎﻥ ﻋﻤﻠﮕﺮﻫﺎﻱ ﻣﺠﺎﺯ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮔﺮﺩﺩ‪ .‬ﻋﻤﻠﮕﺮﻫﺎﻱ ﻣﺠﺎﺯ ﺩﺭ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷـﺮﻃﻲ‬ ‫ﺷﺎﻣﻞ ‪ :‬ﺗﺴﺎﻭﻱ ﺩﻭ ﻋﺒﺎﺭﺕ`==` ‪ ،‬ﻋﺪﻡ ﺗﺴﺎﻭﻱ ﺩﻭ ﻋﺒﺎﺭﺕ `=!` ﻛﻮﭼﻜﺘﺮ `<` ﻛﻮﭼﻜﺘﺮ ﻣﺴﺎﻭﻱ`=<`‬ ‫‪ ،‬ﺑﺰﺭﮔﺘﺮ> ﻭ ﺑﺰﺭﮔﺘﺮ ﻣﺴﺎﻭﻱ`=>` ﻣﻲﺑﺎﺷﺪ‪ .‬ﭘﺲ ﺍﺯ ﺗﻌﺮﻳﻒ ﺷـﺮﻁ ﻋﺒﺎﺭﺗﻬـﺎﻳﻲ ﻛـﻪ ﺑـﻪ ﺍﺯﺍﻱ ﺩﺭﺳـﺖ‬ ‫ﺑﻮﺩﻥ ﺍﻳﻦ ﺷﺮﻁ ﺑﺮﻗﺮﺍﺭ ﻣﻲﺑﺎﺷﻨﺪ ﺩﺭ ﻓﺎﻳﻞ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﻧﺪ ﺩﺭ ﺻـﻮﺭﺕ ﻟـﺰﻭﻡ ﻛﻠﻤـﻪ ﻛﻠﻴـﺪﻱ‪ ELSE‬ﺩﺭ‬ ‫ﺧﻄﻲ ﻧﻮﺷﺘﻪ ﺷﺪﻩ ﻭ ﭘﺲ ﺍﺯ ﺁﻥ ﻋﺒﺎﺭﺗﻬﺎﻱ ﻛﻪ ﺩﺭﺻﻮﺭﺕ ﺑﺮﻗﺮﺍﺭ ﻧﺒﻮﺩﻥ ﺷﺮﻁ‪ IF‬ﺍﺟﺮﺍ ﻣﻲﺷﻮﻧﺪ‪ ،‬ﻗـﺮﺍﺭ‬ ‫ﻣﻲﮔﻴﺮﻧﺪ‪ .‬ﻣﺤﺪﻭﺩﻩﻱ ﻫﺮ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﺑﺎ ﻛﻠﻤﻪﻱ ﻛﻠﻴﺪﻱ ‪ ENDIF‬ﻣﺸﺨﺺ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳـﻦ ﻋﺒـﺎﺭﺕ‬ ‫ﺩﺭ ﺻﻮﺭﺕ ﻭﺟﻮﺩ ‪ ELSE‬ﻧﻴﺰ ﺍﻟﺰﺍﻣﻲ ﻣﻲﺑﺎﺷﺪ ﺍﻳﻦ ﺷﺒﻴﻪﺳﺎﺯ ﻗﺎﺑﻠﻴﺖ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ‪ IF‬ﻫﺎﻱ ﺗﻮﺩﺭ ﺗـﻮ ﺭﺍ‬ ‫ﻧﻴﺰ ﺩﺭ ﺍﺧﺘﻴﺎﺭ ﻛﺎﺭﺑﺮﻱ ﻣﻲﮔﺬﺍﺭﺩ‪.‬‬ ‫‪ -۲-۳-۲-۵‬ﺣﺬﻑ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ‬ ‫ﺩﺭﮔﺎﻡ ﺍﻭﻝ ﺷﺒﻴﻪ ﺳﺎﺯ ﺳﻌﻲ ﻣﻲﻛﻨﺪ ﺑﺎ ﺣﺬﻑ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﺷـﺮﻃﻲ ﺑﻠـﻮﻙ ‪ always‬ﺭﺍﺑـﻪ ﺻـﻮﺭﺕ ﻳـﻚ ﺳـﺮﻱ‬ ‫ﻋﺒﺎﺭﺍﺕ ﻣﺤﺎﺳﺒﻪﺍﻱ ﺩﺭ ﺑﻴﺎﻭﺭﺩ‪ ،‬ﻛﻪ ﺑﻪ ﺻﻮﺭﺕ ﺗﺮﺗﻴﺒﻲ ﺍﺟﺮﺍ ﻣﻲﮔﺮﺩﻧﺪ ﺍﻳﻦ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺟﺪﻳـﺪ ﺩﺭ ﻳـﻚ ﻓﺎﻳـﻞ ﺑـﺎ‬ ‫‪۷۰‬‬ ‫ﭘﺴﻮﻧﺪ ‪ nof‬ﺫﺧﻴﺮﻩ ﻣﻲﺷﻮﺩ‪ .‬ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺍﻳﻦ ﮔﺎﻡ ﺑﺎ ﮐﻤﮏ ﺗﺎﺑﻊ ‪ ifelimination‬ﺍﻧﺠﺎﻡ ﻣﻲﺷـﻮﺩ‪ .‬ﺩﺭ ﺍﻳـﻦ ﺗـﺎﺑﻊ‬ ‫ﻓﺎﻳﻞ ﻭﺭﻭﺩﻱ ﺗﺎ ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﺑﻪ ﻛﻠﻤﻪﻱ ﻛﻠﻴﺪﻱ ‪ IF‬ﻧﺮﺳﻴﺪﻩ ﺍﺳﺖ‪ ،‬ﺩﺭ ﻓﺎﻳﻞ ﺧﺮﻭﺟﻲ ﻛﭙﻲ ﻣﻲﺷـﻮﺩ ﻭ ﻫﻨﮕـﺎﻣﻲ‬ ‫ﻛﻪ ﺑﻪ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ IF‬ﺭﺳﻴﺪ‪ .‬ﺗﺎﺑﻊ ‪ Ifstruct‬ﺻﺪﺍ ﺯﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﻭﻇﻴﻔﻪﻱ ﺍﻳﻦ ﺗﺎﺑﻊ ﻗﺮﺍﺭ ﺩﺍﺩﻥ ﺷﺮﻁ ﺑﻪ ﻋﻨـﻮﺍﻥ‬ ‫ﻱ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺗﺎﺑﻊ ﺍﺑﺘﺪﺍ ﻳﻚ ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﯽ ﺑﻪ ﻋﻨﻮﺍﻥ ﻧﻤﺎﻳﻨـﺪﻩﻱ ﺷـﺮﻁ‬ ‫ﺕ ﻣﺤﺎﺳﺒﻪﺍ ِ‬ ‫ﺟﺰﻳﻲ ﺍﺯ ﻋﺒﺎﺭ ِ‬ ‫ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ‪ ،‬ﺳﭙﺲ ﺗﺎﺑﻊ ‪ ifcom‬ﺻﺪﺍ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺗﺎﺑﻊ ‪ ifcom‬ﺍﺑﺘﺪﺍ ﺑﻪ ﻛﻤﻚ ﺗﺎﺑﻊ ‪ unaryrem‬ﻋﻤﻠﮕﺮﻫﺎﻱ‬ ‫ﻱ ﻣﺘﻐﻴ ِﺮ ﺟـﺎﻳﮕﺰﻳﻦ ﺷـﺮﻁ ﺑﺪﺳـﺖ ﻣـﻲﺁﻳـﺪ‪.‬‬ ‫‪ unary‬ﺑﻪ ﻣﻌﺎﺩﻝ ﺑﺎﻳﻨﺮﯼ ﺗﺒﺪﻳﻞ ﻣﻲﺷﻮﺩ‪ .‬ﺳﭙﺲ ﻋﺒﺎﺭﺕ ﻣﺤﺎﺳﺒﻪ ِ‬ ‫ﻳﻌﻨﻲ ﺍﺑﺘﺪﺍ ﺷﺮﻁ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺗﺸﻜﻴﻞ ﺷﺪﻩ ﺍﺯ ﭼﻨﺪ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﺗﺒﺪﻳﻞ ﻣﻲﻛﻨـﺪ‪ .‬ﺳـﭙﺲ‬ ‫ﺑﻪ ﻫﺮ ﻳﻚ ﺍﺯ ﺍﻳﻦ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﻳﻚ ﻣﺘﻐﻴﺮ ‪ wirex‬ﻧﺴﺒﺖ ﻣﻲﺩﻫـﺪ ﻭ ﻋﺒـﺎﺭﺕ ﺷـﺮﻃﻲ ﺭﺍ ﺑـﻪ ﻳﻜـﻲ ﺍﺯ ﺩﻭ‬ ‫ﺣﺎﻟﺖ '‪ ' f wirex != 0‬ﻳﺎ '‪ ' f wirex < 0‬ﺩﺭﻣﻲﺁﻭﺭﺩ‪ .‬ﺳـﭙﺲ ﺩﺭﻓﺎﻳـﻞ ﺧﺮﻭﺟـﻲ ﺑﻨﺎﺑـﻪ ﺍﻳﻨﻜـﻪ ﻋﺒـﺎﺭﺕ ﺷـﺮﻃﻲ ﺑـﻪ‬ ‫ﻛﺪﺍﻣﻴﻚ ﺍﺯ ﺍﻳﻦ ﺩﻭﺣﺎﻟﺖ ﺩﺭﺁﻣﺪﻩ ﺑﺎﺷﺪ‪ ،‬ﻋﺒﺎﺭﺕ ‪ wirex# f wirex‬ﻳﺎ ‪ wirex < f wirex‬ﻧﻮﺷﺘﻪ ﻣـﻲﺷـﻮﺩ‪ .‬ﭘـﺲ ﺍﺯ‬ ‫ﻗﺮﺍﺭﺩﺍﺩﻥ ﻋﺒﺎﺭﺗﻬﺎﻱ ﻣﻌﺎﺩﻝ‪ ،‬ﺷﺮﻁ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴـﺎﻧﯽ ﺟـﺎﻳﮕﺰﻳﻦ ﻋﺒﺎﺭﺗﻬـﺎﻱ‬ ‫ﺷﺮﻃﻲ )‪wirex‬ﻫﺎ( ﺩﺭ ﻓﺎﻳﻞ ﺧﺮﻭﺟﻲ ﺫﺧﻴﺮﻩ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺩﺭ ﻓﺎﻳﻞ ﺧﺮﻭﺟﻲ ﺗﻌـﺪﺍﺩﻱ ﻣﺘﻐﻴﺮﻫـﺎﻱ ﻣﻴـﺎﻧﯽ‬ ‫ﺟﺎﻳﮕﺰﻳﻦ ﻋﺒﺎﺭﺗﻬﺎﯼ ﺷﺮﻃﻲ ﻣﻘﺪﺍﺭﺩﻫﻲ ﺷﺪﻩﺍﻧﺪ ﻭ ﺳﭙﺲ ﻛـﻞ ﺷـﺮﻁ ﺑـﻪ ﺻـﻮﺭﺕ ﻳـﻚ ﻋﺒـﺎﺭﺕ ﺑـﻮﻟﻲ ﺍﺯ ﺁﻥ‬ ‫ﻣﺘﻐﻴﺮﻫﺎ ﺑﻴﺎﻥ ﻣﻲﺷﻮﺩ‪ .‬ﺳﭙﺲ ﺩﺭ ﺗﺎﺑﻊ ‪ ، ifstruct‬ﻣﺘﻐﻴﺮ ﺷﺮﻁ ﺑﻪ ﻋﻨﻮﺍﻥ ﻳﻚ ﻓـﺎﻛﺘﻮﺭ ﺩﺭ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﻣﺤﺎﺳـﺒﺎﺗﻲ‬ ‫ﺩﺍﺧﻞ ﺑﺨﺶ ‪ IF‬ﻭ ﻧﻘﻴﺾ ﺁﻥ ﺩﺭ ﻋﺒﺎﺭﺗﻬﺎﻱ ﻣﺤﺎﺳﺒﺎﺗﻲ ﺩﺍﺧﻞ ﺑﺨﺶ ‪ And ،ELSE‬ﻣﻲﺷﻮﺩ‪ .‬ﺷﻜﻞ ‪ ۱-۵‬ﻧﺸـﺎﻥ‬ ‫ﺩﻫﻨﺪﻩﻱ ﺍﻳﻦ ﺗﻐﻴﻴﺮﺍﺕ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫;‪wire1 > c - d‬‬ ‫;‪wire2# d – 1‬‬ ‫;‪wire3 = wire1 & ~wire2‬‬ ‫;‪a = wire3 & b + ~wire3 & d‬‬ ‫))‪If ((c > d) & (d == 1‬‬ ‫;‪a = b‬‬ ‫‪Else‬‬ ‫;‪a = d‬‬ ‫;‪Endif‬‬ ‫ﺷﮑﻞ ‪ -۱-۵‬ﮐﺪ ﻳﮏ ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﻭ ﻣﻌﺎﺩﻝ ﺁﻥ‬ ‫‪۷۱‬‬ ‫ﻟﻴﻜﻦ ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﻣﺎ ‪IF‬ﻫﺎﻱ ﺗﻮﺩﺭ ﺗﻮ ﺩﺍﺷﺘﻪ ﺑﺎﺷﻴﻢ‪ ،‬ﺍﻳﻦ ﻓﺎﻛﺘﻮﺭ ﺑﺎﻳﺪ ﺷﺎﻣﻞ ﻓﺎﻛﺘﻮﺭ ‪ IF‬ﺧﺎﺭﺟﻲ ﻧﻴـﺰ ﺑﺎﺷـﺪ‪.‬‬ ‫ﭘﺲ ﺑﻪ ﺗﺎﺑﻊ ‪ ifstruct‬ﻳﻚ ﻣﺘﻐﻴﺮ ‪ factor‬ﺍﺭﺳﺎﻝ ﻣﻲﮔﺮﺩﺩ ﻛـﻪ ﻧﻤﺎﻳـﺎﻧﮕﺮ ‪factor‬ﺣﺎﺻـﻞ ﺍﺯ ‪ IF‬ﻫـﺎﻱ ﺧـﺎﺭﺟﻲ‬ ‫ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺩﺭ ﻫﺮ ‪ IF‬ﺑﺎﻳﺪ ﺩﺭ ﻓﺎﻛﺘﻮﺭ ﺟﺪﻳﺪ ‪ AND‬ﺷﻮﺩ)ﺷﻜﻞ ‪.(۲-۵‬‬ ‫)‪If (wire1‬‬ ‫)‪If (wire2‬‬ ‫;‪a = b‬‬ ‫‪Else‬‬ ‫;‪a = d‬‬ ‫;‪Endif‬‬ ‫;‪Endif‬‬ ‫;‪a = wire1 & wire2 & b + wire1 & ~wire2 & d‬‬ ‫ﺷﮑﻞ ‪ -۲-۵‬ﮐﺪ ﻳﮏ ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﺗﻮﺩﺭﺗﻮ ﻭ ﻣﻌﺎﺩﻝ ﺁﻥ‬ ‫ﺣﺎﻝ ﺍﮔﺮ ﻳﻜﻲ ﻣﺘﻐﻴﺮ ﻫﻢ ﺩﺭﺑﻠﻮﻙ ‪ IF‬ﻭ ﻫﻢ ﺩﺭ ﺑﻠﻮﻙ ‪ ELSE‬ﻣﻘﺪﺍﺭﺩﻫﻲ ﺷـﻮﺩ ﻣـﻲﺗـﻮﺍﻥ ﺁﻥ ﺭﺍ ﺑـﻪ ﺻـﻮﺭﺕ‬ ‫ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ‪ x = c & f T + (~ c) & f f‬ﺩﺭ ﺁﻭﺭﺩ‪ .‬ﻭﻟﻲ ﻣﺸﻜﻞ ﺍﻳﻦ ﺭﻭﺵ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﻣﻤﻜﻦ ﺍﺳﺖ ﻛـﺪﻱ‬ ‫ﻣﺎﻧﻨﺪ ﺷﻜﻞ ‪ ۳-۵‬ﺩﺍﺷﺘﻪ ﺑﺎﺷﻴﻢ‪ .‬ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ ﻧﻤﯽﺗﻮﺍﻥ ﺑﺮﺍﯼ ‪ c‬ﻭ ‪ a‬ﻳﮏ ﻋﺒﺎﺭﺕ ﻳﮑﺘﺎ ﺗﺸﮑﻴﻞ ﺩﺍﺩ‪ ،‬ﭘـﺲ ﻳـﻚ‬ ‫ﻟﻴﺴﺖ ﻃﺮﺍﺣﻲ ﻣﻲﺷﻮﺩ ﻛﻪ ﺩﺭﺁﻥ ﻣﺘﻐﻴﺮﻫﺎﻳﻲ ﻛﻪ ﺗﺎﻛﻨﻮﻥ ﻣﻘﺪﺍﺭ ﺩﻫﻲ ﺷﺪﻩﺍﻧﺪ ﻗﺮﺍﺭ ﺩﺍﺩﻩﻣﻲﺷـﻮﺩ‪ .‬ﺩﺭ ﺍﺩﺍﻣـﻪ ﺍﮔـﺮ‬ ‫ﻣﺘﻐﻴﺮﻱ ﻣﻘﺪﺍﺭﺩﻫﻲ ﺷﺪﻩ ﺑﻮﺩﻩ ﺍﺳﺖ‪ ،‬ﺣﺎﻝ ﺑﺎ ﻓﺮﻣﻮﻝ ‪ x = x + c & f T‬ﻣﻘﺪﺍﺭﺩﻫﻲ ﻣﻲﺷﻮﺩ‪.‬‬ ‫;‪a = wire1 & b‬‬ ‫;‪c = wire1 & d‬‬ ‫;‪c = c + ~wire1 & f‬‬ ‫; ‪a = a + (~wire1) & c‬‬ ‫)‪If (wire1‬‬ ‫;‪a = b‬‬ ‫;‪c = d‬‬ ‫‪Else‬‬ ‫;‪c = f‬‬ ‫;‪a = c‬‬ ‫;‪Endif‬‬ ‫ﺷﮑﻞ ‪ -۳-۵‬ﻋﺒﺎﺭﺕ ﺷﺮﻃﯽ ﺑﺎ ﻣﻘﺪﺍﺭ ﺩﻫﯽ ﺿﺮﺑﺪﺭﯼ‬ ‫ﻣﺸﻜﻞ ﺑﻌﺪﻱ ﺍﻳﻦ ﺭﻭﺵ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﻣﻤﻜﻦ ﺍﺳﺖ ﻣﺘﻐﻴـﺮﺩﺭ ﻳﻜـﻲ ﺍﺯ ﺑﻠﻮﻛﻬـﺎﻱ ‪ IF‬ﻳـﺎ‪ ELSE‬ﻣﻘـﺪﺍﺭ ﺩﻫـﻲ‬ ‫ﻧﺸﻮﺩ‪ ،‬ﻭﻟﻲ ﺍﻳـﻦ ﻣﺘﻐﻴـﺮ ﻗﺒـﻞ ﺍﺯ ﺑﻠـﻮﻙ ‪ IF‬ﻣﻘـﺪﺍﺭ ﺩﻫـﻲ ﺷـﺪﻩ ﺑﺎﺷـﺪ ﺑـﺮﺍﻱ ﺣـﺬﻑ ﺍﻳـﻦ ﻣﺸـﻜﻞ ﺩﺭ ﺗـﺎﺑﻊ‬ ‫‪ ifelimination‬ﺗﻤﺎﻡ ﻣﺘﻐﻴﺮﻫﺎﻳﻲ ﻛﻪ ﻗﺒﻞ ﺍﺯ ﻳﻚ ﺑﻠﻮﻙ ‪ IF‬ﻣﻘـﺪﺍﺭ ﺩﻫـﻲ ﺷـﺪﻩﺍﻧـﺪ ﺩﺭ ﻟﻴﺴـﺖ ‪ result‬ﺭﻳﺨﺘـﻪ‬ ‫ﻣـــﻲﺷـــﻮﺩ ﻭ ﻫﻨﮕـــﺎﻣﻲ ﻛـــﻪ ﺗـــﺎﺑﻊ ‪ ifstruct‬ﺑـــﺎ ﻣﻘـــﺪﺍﺭ ﺩﻫـــﻲ ﺁﻥ ﻣﺘﻐﻴـــﺮ ﻣﻮﺍﺟـــﻪ ﻣـــﻲﺷـــﻮﺩ‪،‬‬ ‫‪۷۲‬‬ ‫ﻋﺒﺎﺭﺕ ‪ x = (~ c) & x + c & f T‬ﺭﺍ ﺟﺎﻳﮕﺰﻳﻦ ﺁﻥ ﻣﻲﻛﻨﺪ‪.‬‬ ‫ﺩﺭ ﺗﺎﺑﻊ ‪ ifcom‬ﺗﻤﺎﻡ ﻣﺘﻐﻴﺮﻫﺎﻳﻲ ﻛﻪ ﺑﻪ ﻋﻨﻮﺍﻥ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﺑﺮﻧﺎﻣﻪ ﺍﺳﺘﻔﺎﺩﻩ ﺷﺪﻩﺍﺳﺖ ﻫﻤﺮﺍﻩ ﺑﺎ ﻋﻤﮕﺮﺷـﺎﻥ‬ ‫ﺩﺭ ﻟﻴﺴﺖ ‪ ifwires‬ﺭﻳﺨﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺩﻟﻴﻞ ﺍﻳﻦ ﺍﻣﺮ ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﻣﻘﺪﺍﺭﺩﻫﻲ ﺍﻳﻦ ﻣﺘﻐﻴﺮﻫـﺎ ﻣﻴـﺎﻧﻲ ﺑـﺎ ﻣﺘﻐﻴﺮﻫـﺎﻱ‬ ‫ﺩﻳﮕﺮ ﺗﻔﺎﻭﺕ ﺩﺍﺭﺩ‪ .‬ﺗﻤﺎﻡ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴﺎﻧﻲ ﻧﻤﺎﻳﻨﺪﻩ ﺷﺮﻃﻬﺎ ﻧﻴﺰ ﺑﻪ ‪ wire‬ﻫﺎﻱ ﻛﺪ ﺍﺿﺎﻓﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪precompile -۳-۳-۲-۵‬‬ ‫ﻫﺪﻑ ﺍﺯ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺗﺒﺪﻳﻞ ﻓﺎﻳﻞ ﺣﺎﺻﻞ ﺍﺯ ﻣﺮﺣﻠﻪ ﻗﺒﻞ )‪ (nof‬ﺑﻪ ﻓﺎﻳﻠﻲ )‪ (ntl‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺩﺭ ﺁﻥ ﻋﻤﻠﮕﺮﻫﺎﻱ‬ ‫ﺑﻮﻟﻲ ﻋﺒﺎﺭﺗﻬﺎ ﺑﻪ ﻣﻌﺎﺩﻝ ﺟﺒﺮﻱ ﺧﻮﺩ ﻭ ﺗﻤﺎﻣﻲ ﻋﺒﺎﺭﺗﻬﺎ ﺑﻪ ﺻـﻮﺭﺕ ﻋﺒﺎﺭﺗﻬـﺎﻳﻲ ﺩﻭﺗـﺎﻳﻲ ﺑـﺎ ﻋﻤﻠﮕـﺮ `‪ `+‬ﻭ `*`‬ ‫ﺗﺒﺪﻳﻞ ﺷﺪﻩﺍﻧﺪ‪ .‬ﺩﺭ ﺣﻘﻴﻘﺖ ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﮔﺮﺍﻑ ﻣﺴﻴﺮﺩﺍﺩﻩ ﻫﺮ ﻋﺒﺎﺭﺕ ﺑﻪ ﺩﺳﺖ ﻣﻲﺁﻳﺪ‪ .‬ﻫﺮ ﭼﻨﺪ ﺍﻳﻦ ﻣﺮﺣﻠـﻪ‬ ‫ﻗﺎﺑﻠﻴﺖ ﺍﺟﺮﺍ ﻣﻮﺍﺯﻱ ﺑﺎ ﻗﺴﻤﺖ ﺑﻌﺪ ﺭﺍ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻟﻴﻜﻦ ﻓﺎﻳﻞ ﺣﺎﺻﻞ ﺍﺯ ﺍﺟﺮﺍﻱ ﺍﻳﻦ ﻗﺴﻤﺖ‪ ،‬ﺑﺮﺭﺳﻲ ﻧﺤـﻮﻩ‬ ‫ﻋﻤﻠﻜﺮﺩ ﺷﺒﻴﻪﺳﺎﺯ ﺭﺍ ﺁﺳﺎﻥ ﻣﻲﺳﺎﺯﺩ ﻭ ﺍﺯ ﺳﻮﻱ ﺩﻳﮕﺮ ﺑﺎﻋﺚ ﻣﻲﺷﻮﺩ ﻛﻪ ﻫﺮ ﻛﺪﺍﻡ ﺍﺯ ﺍﻳﻦ ﺩﻭ ﻣﺮﺣﻠﻪ ﺑـﺎ ﺣﺠـﻢ‬ ‫ﺣﺎﻓﻈﻪ ﻛﻤﺘﺮﻱ ﺍﺟﺮﺍ ﺷﻮﻧﺪ‪ .‬ﺯﻳﺮﺍ ﻫﺮ ﻛﺪﺍﻡ ﺍﺯ ﺍﻳﻦ ﻣﺮﺍﺣﻞ ﺩﺍﺭﺍﻱ ﺗﻮﺍﺑﻊ ﺑﺎﺯﮔﺸﺘﻲ ﻣـﻲﺑﺎﺷـﻨﺪ ﻛـﻪ ﺗﺮﻛﻴـﺐ ﺍﻳـﻦ‬ ‫ﺩﻭﻣﺮﺣﻠﻪ ﺑﺎ ﻫﻢ ﻧﻴﺎﺯﻣﻨﺪ ﺣﺎﻓﻈﻪ ﭘﺸﺘﻪ ﺑﺎ ﺣﺠﻢ ﺑﺎﻻﻳﻲ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺩﺭﺍﻳﻦ ﻗﺴﻤﺖ ﺍﺑﺘﺪﺍ ﺗﺎﺑﻊ ‪ compile‬ﻓﺎﻳﻞ ‪ nof‬ﺭﺍ ﺧﻂ ﺑﻪ ﺧﻂ ﻣﻲﺧﻮﺍﻧﺪ‪ ،‬ﺩﺭ ﺧﻂ ﺗﻌﺮﻳﻒ ﻭﺭﻭﺩﻳﻬﺎ‪ ،‬ﻣﺘﻐﻴـﺮ ﻫـﺮ‬ ‫ﻭﺭﻭﺩﻱ ﺭﺍ ﺩﺭ ﻟﻴﺴﺖ ‪ inputs‬ﻗﺮﺍﺭ ﻣﻲﺩﻫﺪ ﻭ ﺍﮔﺮ ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﺍﻧﺪﺍﺯﻩﻱ ﻣﺸﺨﺼﻲ ﻧﺪﺍﺷﺖ ﺩﺭﻓﺎﻳـﻞ ﺧﺮﻭﺟـﻲ ﺑـﺎ‬ ‫ﺍﻧﺪﺍﺯﻩﻱ ﻳﻚ ﻣﺸﺨﺺ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺧﻂ ﺗﻌﺮﻳﻒ ﺧﺮﻭﺟﻴﻬﺎ ﻧﻴﺰ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺧﺮﻭﺟﻲ ﺍﻧﺪﺍﺯﻩﺩﻫـﻲ ﻭ ﺑـﻪ ﻟﻴﺴـﺖ‬ ‫‪ outputs‬ﺍﺿﺎﻓﻪ ﻣﻲﺷﻮﻧﺪ‪ .‬ﺩﺭ ﺧﻂ ﺗﻌﺮﻳﻒ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺩﺍﺧﻠﻲ ﺍﻳﻦ ﻣﺘﻐﻴﺮﻫﺎ ﺑﻪ ﻟﻴﺴـﺘﻬﺎﻱ ‪ wires‬ﻭ ‪mainwires‬‬ ‫ﺍﺿﺎﻓﻪ ﻣﻲﺷﻮﻧﺪ‪ .‬ﭘﺲ ﺍﺯ ﺍﻳﻦ ﺧﻄﻮﻁ ﺑﻪ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺳﺎﺯﻧﺪﻩﻱ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺭﺳﻴﻢ‪ ،‬ﺗﺎﺑﻊ ‪ compile‬ﺍﺑﺘﺪﺍ ﺧﻂ ﺭﺍ ﺑﻪ‬ ‫ﻣﺘﻐﻴﺮ ﻣﻘﺪﺍﺭﺩﻫﻲ ﺷﻮﻧﺪﻩ ﻭ ﻋﺒﺎﺭﺕ ﻣﻘﺪﺍﺭﺩﻫﻲ ﺗﻘﺴﻴﻢ ﻣﻲﮐﻨﺪ‪ .‬ﺳﭙﺲ ﻋﺒﺎﺭﺕ ﺳﻤﺖ ﺭﺍﺳﺖ ﺑـﻪ ﺗـﺎﺑﻊ ‪precom‬‬ ‫ﺍﺭﺳﺎﻝ ﻣﻲﺷﻮﺩ‪ .‬ﺗﺎﺑﻊ ‪ precom‬ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺗﺎﺑﻊ ‪ logicom‬ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑـﻮﻟﻲ ﺭﺍ ﺑـﺎ ﻋﺒﺎﺭﺗﻬـﺎﻱ ﺟﺒـﺮﻱ ﻣﻌـﺎﺩﻝ‬ ‫ﺟﺎﻳﮕﺰﻳﻦ ﻣﻲﮐﻨﺪ ﻭ ﺳﭙﺲ ﻋﻤﻠﮕﺮﻫﺎﻱ ﺟﺒﺮﻱ ﺗﻔﺎﺿـﻞ `‪ `-‬ﻭ ﺗـﻮﺍﻥ `^` ﺭﺍ ﺑـﻪ ﻣﻌـﺎﺩﻝ ﺁﻧﻬـﺎ ﺩﺭ ﺟﺒـﺮ )*‪R(+,‬‬ ‫‪۷۳‬‬ ‫ﺗﺒﺪﻳﻞ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﺗﺎﺑﻊ ‪ logicom‬ﺧﻂ ﺍﺯ ﺍﻭﻝ ﺗﺎ ﺑﻪ ﺁﺧﺮ ﺑﺮﺭﺳﻲ ﻣﻲﺷﻮﺩ ﻭ ﺍﮔﺮ ﺑﻪ ﻋﻤﻠﮕﺮﻫﺎﻱ `&`‪`@`،`|` ،‬‬ ‫ﺑﺮﺧﻮﺭﺩ ﻛﺮﺩ‪ ،‬ﻋﻤﻠﻮﻧﺪﻫﺎﯼ ﺁﻥ ﺭﺍ ﺑﺎ ﻛﻤﻚ ﺗﻮﺍﺑﻊ ‪ findnextop‬ﻭ ‪ findlastop‬ﺑﺪﺳـﺖ ﻣـﻲﺁﻭﺭﺩ‪ .‬ﺩﺭ ﭘﺎﻳـﺎﻥ ﺑـﺎ‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻓﺮﻣﻮﻟﻬﺎﻱ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺩﺭ ‪ TED‬ﻋﺒﺎﺭﺗﻬﺎﻱ ﺑﻮﻟﻲ ﺑﻪ ﻋﺒﺎﺭﺕ ﺟﺒﺮﻱ ﻣﻌﺎﺩﻝ ﺗﺒﺪﻳﻞ ﻣﻲﺷﻮﻧﺪ‪.‬‬ ‫ﺗﺎﺑﻊ ‪ precom‬ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ ﺍﺯ ﺗﺎﺑﻊ ‪ logicom‬ﺭﺍﻣﻮﺭﺩ ﺑﺮﺭﺳﻲ ﻗﺮﺍﺭ ﺩﺍﺩﻩ‪ ،‬ﺍﮔﺮ ﺑﺎ ﻋﻤﮕـﺮ ﻗﺮﻳﻨـﻪ `‪ `-‬ﺑﺮﺧـﻮﺭﺩ‬ ‫ﻛﺮﺩ ﻣﻌﺎﺩﻝ ﺁﻥ ﻳﻌﻨﻲ '‪ '*− 1‬ﺭﺍ ﻗﺮﺍﺭ ﻣﻲﺩﻫﺪ ﻭ ﻫﻤﭽﻨـﻴﻦ ﻋﻤﻠﮕـﺮ ﺗﻔﺎﺿـﻞ `‪ `-‬ﺭﺍ ﺑـﺎ ﻣﻌـﺎﺩﻝ ﺁﻥ ﻳﻌﻨـﻲ `‪`+-‬‬ ‫ﺟﺎﻳﮕﺰﻳﻦ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﭘﺎﻳﺎﻥ ﺑﻪ ﺗﻮﺍﻥ ‪ n‬ﺭﺳﺎﻧﺪﻥ ﻳﻚ ﻋﺒﺎﺭﺕ ﺭﺍﺑـﻪ ﺣﺎﺻـﻞ ﺿـﺮﺏ ‪ n‬ﻋﺒـﺎﺭﺕ ﻣﺘـﻮﺍﻟﻲ ﺗﺒـﺪﻳﻞ‬ ‫ﻣﻲﻛﻨﺪ‪ .‬ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ ﺍﺯ ﺍﻳﻦ ﺗﺎﺑﻊ ﻳﻚ ﻋﺒﺎﺭﺕ ﺷﺎﻣﻞ ﻋﻤﻠﮕﺮ ﻫﺎﻱ`‪ `+‬ﻭ`*` ‪ ،‬ﺍﻋﺪﺍﺩ ﺻﺤﻴﺢ‪ ،‬ﻣﺘﻐﻴـﺮ‪ ،‬ﭘﺮﺍﻧﺘـﺰ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻛﻪ ﺑﻪ ﺗﺎﺑﻊ ‪ compile‬ﺑﺎﺯﮔﺮﺩﺍﻧﺪﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺳﭙﺲ ﺗﺎﺑﻊ ‪ compile‬ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ ﺭﺍ ﺑﻪ ﺗﺎﺑﻊ ‪ createtree‬ﺍﺭﺳﺎﻝ ﻣﻲﻛﻨﺪ‪ ،‬ﺩﺭ ﺍﻳﻦ ﺗﺎﺑﻊ ﮔﺮﺍﻑ ﻣﺴـﻴﺮ ﺩﺍﺩﻩﻱ‬ ‫ﻋﺒﺎﺭﺕ ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺗـﺎﺑﻊ ‪ createtree‬ﺍﺑﺘـﺪﺍ ﺍﮔـﺮ ﺩﻭ ﻃـﺮﻑ ﻋﺒـﺎﺭﺕ ﭘﺮﺍﻧﺘـﺰ ﺑﺎﺷـﺪ‪ ،‬ﺑـﺎ ﻛﻤـﻚ ﺗـﺎﺑﻊ‬ ‫‪ removeparenthesis‬ﺍﻳﻦ ﭘﺮﺍﻧﺘﺰﻫﺎ ﺣﺬﻑ ﻣﻲﺷﻮﺩ‪ .‬ﺳﭙﺲ ﺑﻪ ﺩﻟﻴﻞ ﺍﻳﻨﻜﻪ ﺍﻭﻟﻮﻳﺖ ﺿﺮﺏ ﺍﺯ ﺟﻤﻊ ﺑﺎﻻﺗﺮ ﺍﺳﺖ‬ ‫ﺍﺑﺘﺪﺍ ﺳﻌﻲ ﻣﻲﺷﻮﺩ ﻛﻪ ﺗﺎﺑﻊ ﺑﺮﺍﺳﺎﺱ ﻋﻤﻠﮕﺮ ﺟﻤﻊ‪ ،‬ﺗﻘﺴﻴﻢ ﺷﻮﺩ‪ .‬ﻭﻟﻲ ﺍﮔﺮ ﻋﻤﻠﮕـﺮ ﺟﻤـﻊ ﭘﻴـﺪﺍ ﻧﺸـﺪ‪ ،‬ﺍﻭﻟـﻴﻦ‬ ‫ﻋﻤﻠﮕﺮ ﺿﺮﺏ‪ ،‬ﻋﺒﺎﺭﺕ ﺭﺍ ﺗﻘﺴﻴﻢ ﻣﻲﻛﻨﺪ‪ .‬ﺗﻮﺟﻪ ﻛﻨﻴﺪ ﻛﻪ ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ ﺍﺯ ﺗﺎﺑﻊ ‪ precom‬ﭘﺮﺍﻧﺘﺰ ﺑﻨـﺪﻱ ﺷـﺪﻩ‬ ‫ﺍﺳﺖ ﻭ ﺗﺎﺑﻊ ‪ createtree‬ﺗﻘﺴﻴﻢ ﻋﺒﺎﺭﺕ ﺭﺍ ﺑﺮ ﺍﺳﺎﺱ ﭘﺮﺍﻧﺘﺰﺑﻨﺪﻱ ﺗﺎﺑﻊ ﺍﻧﺠﺎﻡ ﻣﻲﺩﻫﺪ‪ .‬ﺩﺭ ﻣﻮﺍﺭﺩﻱ ﻛـﻪ ﻋﺒـﺎﺭﺕ‬ ‫ﻣﺤﺎﺳﺒﻪﺍﻱ ﺗﻨﻬﺎ ﻳﻚ ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﻳﺎ ﻳﻚ ﻣﺘﻐﻴﺮ ﺑﺎﺷﺪ ﺗﺎﺑﻊ ﺁﻥ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﺣﺎﺻﻠﻀﺮﺏ ﻋﺪﺩ ﻳﻚ ﺑﺎ ﺁﻥ ﻣﺘﻐﻴـﺮ‬ ‫ﻳﺎ ﻋﺪﺩ ﺻﺤﻴﺢ ﺩﺭ ﻧﻈﺮ ﻣﻲﮔﻴﺮﺩ‪.‬ﭘﺲ ﺍﺯ ﭘﻴﺪﺍ ﻛﺮﺩﻥ ﻋﻤﻠﮕﺮ ﺗﻘﺴﻴﻢ ﻛﻨﻨـﺪﻩﻱ ﻋﺒـﺎﺭﺕ‪ ،‬ﻋﺒـﺎﺭﺕ ﺑـﻪ ﺩﻭ ﻗﺴـﻤﺖ‬ ‫‪ d1temp‬ﻭ ‪ d2temp‬ﺗﻘﺴﻴﻢ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺳﭙﺲ ﺍﻳﻦ ﺩﻭ ﻋﺒﺎﺭﺕ ﺑﻪ ﺗﻮﺍﺑﻊ ‪ findoutput, findinput‬ﻭ‪ findwire‬ﺍﺭﺳﺎﻝ ﻣﻲﺷـﻮﻧﺪ‪ ،‬ﺍﻳـﻦ ﺗﻮﺍﺑـﻊ ﺑﺮﺭﺳـﯽ‬ ‫ﻣﻲﮐﻨﻨﺪ ﮐﻪ ﺁﻳﺎ ﻋﺒﺎﺭﺕ ﺍﺭﺳﺎﻟﯽ ﻳﻚ ﻭﺭﻭﺩﻱ‪ ،‬ﺧﺮﻭﺟﻲ ﻳﺎ ﻳﻚ ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﻲ ﺍﺻـﻠﻲ ﺍﺳـﺖ ﻳـﺎ ﻧـﻪ‪ .‬ﺩﺭ ﺣﻘﻴﻘـﺖ‬ ‫ﻛﺎﺭﺑﺮﺩ ﺍﺻﻠﻲ ﻟﻴﺴﺘﻬﺎﻱ ‪ mainwires, inputs‬ﻭ‪ outputs‬ﺩﺭ ﺍﻳﻦ ﺗﻮﺍﺑﻊ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﻗﺴﻤﺖ ﺣﺬﻑ ﻋﺒﺎﺭﺗﻬـﺎﻱ‬ ‫‪۷۴‬‬ ‫ﺷﺮﻃﻲ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻧﻤﺎﻳﻨﺪﻩﻱ ﺷﺮﻃﻬﺎ ﻧﻴﺰ ﺩﺭ ‪ mainwires‬ﺍﺿﺎﻓﻪ ﺷﺪﻩﺍﻧﺪ‪ ،‬ﻋﻠﺖ ﺍﻳﻦ ﻣﻮﺿﻮﻉ ﺍﻳﻦ ﺍﺳﺖ ﮐـﻪ ﺩﺭ‬ ‫ﺻﻮﺭﺗﻲ ﻛﻪ ﻋﺒﺎﺭﺕ ﺑﻪ ﻳﻚ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﺭﺳﻴﺪ ﺍﺯ ﻣﺘﻐﻴﺮ ﻣﺘﻨﺎﺳـﺐ ﺑـﺎ ﺁﻥ ﺍﺳـﺘﻔﺎﺩﻩ ﻛﻨـﺪ‪ .‬ﺩﺭ ﺍﺩﺍﻣـﻪ ﺑﺮﺭﺳـﻲ‬ ‫ﻣﻲﺷﻮﺩ ﻛﻪ ﻋﺒﺎﺭﺗﻬﺎﻱ ‪ d1temp‬ﻭ ‪ d2temp‬ﻋﺪﺩ ﺻﺤﻴﺢ ﻫﺴﺘﻨﺪ ﻳﺎ ﻧﻪ‪ .‬ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﻳﻜـﻲ ﺍﺯ ﺍﻳـﻦ ﺷـﺮﻭﻁ‬ ‫ﺑﺮﻗﺮﺍﺭ ﺑﻮﺩ‪ .‬ﻣﻲﺗﻮﺍﻥ ﺍﺯ ﻫﻤﻴﻦ ﻋﺒﺎﺭﺗﻬﺎ ﺑﺮﺍﻱ ﺗﺸﻜﻴﻞ ﻳﻚ ﻗﺴﻤﺖ ﺍﺯ ﻋﺒﺎﺭﺕ ﺣﺎﺻـﻞ ﺍﺳـﺘﻔﺎﺩﻩ ﻛـﺮﺩ‪ .‬ﻟـﻴﻜﻦ ﺩﺭ‬ ‫ﺻﻮﺭﺗﻲ ﻛﻪ ﺗﻤﺎﻡ ﺍﻳﻦ ﺷﺮﺍﻳﻂ ﺑﺮﻗﺮﺍﺭ ﻧﺒﺎﺷﻨﺪ‪ .‬ﻳﻚ ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﻲ ﺗﻌﺮﻳﻒ ﻭ ﺑﻪ ﻟﻴﺴﺖ ‪ wires‬ﺍﺿـﺎﻓﻪ ﻣـﻲﺷـﻮﺩ‪.‬‬ ‫ﺳﭙﺲ ﺑﺮﺍﯼ ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﻲ ﺗﺎﺑﻊ ‪ createtree‬ﻭ ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﺁﻥ ﺑﻪ ﺻﻮﺭﺕ ﺑﺎﺯﮔﺸﺘﻲ ﺻﺪﺍ ﺯﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ‬ ‫ﭘﺎﻳﺎﻥ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﻋﺒﺎﺭﺕ ﺍﺻـﻠﻲ ﺑـﻪ ﺻـﻮﺭﺕ `)ﻗﺴـﻤﺖ ﺩﻭﻡ‪،‬ﻗﺴـﻤﺖ ﺍﻭﻝ(ﻋﻤﻠﮕـﺮ` ﺩﺭﻓﺎﻳـﻞ‬ ‫ﺧﺮﻭﺟﻲ ﻧﻮﺷﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺷﮑﻞ ‪ ۴-۵‬ﻳﮏ ﻣﺜﺎﻝ ﺍﺯ ﻓﺮﺁﻳﻨﺪ ﺗﺎﺑﻊ ‪ compile‬ﻣﻲﺑﺎﺷﺪ‪:‬‬ ‫ﻋﺒﺎﺭﺕ ﭘﺲ ﺍﺯ ﺗﺎﺑﻊ ‪:logiccom‬‬ ‫ﻋﺒﺎﺭﺕ ﺍﻭﻟﻴﻪ‪:‬‬ ‫;‪a = wire1 & wire2 & b & 1‬‬ ‫;‪a = wire1*wire2*b*1‬‬ ‫ﻋﺒﺎﺭﺕ ﻧﻬﺎﻳﻲ‪:‬‬ ‫;)‪*(wire4, b, 1‬‬ ‫;)‪*(wire3, wire2, wire4‬‬ ‫;)‪*(a, wire1, wire3‬‬ ‫ﺷﮑﻞ ‪ -۴-۵‬ﻓﺮﺁﻳﻨﺪ ﺗﺎﺑﻊ ‪ compile‬ﺑﺮﺍﯼ ﻳﮏ ﻋﺒﺎﺭﺕ‬ ‫ﺩﺭ ﭘﺎﻳﺎﻥ ﺍﻳﻦ ﻣﺮﺍﺣﻞ ﻳﻚ ﻓﺎﻳﻞ ﺑﺎ ﭘﺴﻮﻧﺪ ‪ tmp‬ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ ﻛﻪ ﺷـﺎﻣﻞ ﺗﻤـﺎﻡ ﺍﻃﻼﻋـﺎﺕ ﻣﻮﺟـﻮﺩ ﺩﺭ ﻓﺎﻳـﻞ‬ ‫ﻧﻬﺎﻳﻲ ﻣﺮﺣﻠﻪ ‪ precompile‬ﺟﺰ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴﺎﻧﻲ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺑﻠﻮﻙ ‪ ،always‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﭘﺲ ﺍﺯ ﺍﻳﻦ ﻣﺮﺣﻠﻪ‬ ‫ﻓﺎﻳﻞ ‪ tmp‬ﺩﻭﺑﺎﺭﻩ ﺧﻮﺍﻧﺪﻩ ﻣﻲﺷﻮﺩ ﻭ ﭘﺲ ﺍﺯ ﺧﻂ ﻣﻌﺮﻓﻲ ﺧﺮﻭﺟﻴﻬﺎﻱ ﺑﻠـﻮﻙ ﺍﺑﺘـﺪﺍ ﺧﻄـﻲ ﺑـﺎ ﻛﻠﻤـﻪ ﻛﻠﻴـﺪﻱ‬ ‫‪ IFWIRE‬ﺍﺿﺎﻓﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺍﻳﻦ ﺧﻂ ﺗﻤﺎﻡ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴﺎﻧﻲ ﻧﻤﺎﻳﻨﺪﻩﻱ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﻣﻌﺮﻓﻲ ﻣﻲﺷـﻮﻧﺪ‪،‬‬ ‫ﭘﺲ ﺍﺯ ﺁﻧﻬﺎ ﻋﻤﻠﮕﺮ ﻣﻘﺎﻳﺴﻪﺍﻱ ﺁﻧﻬﺎ ﻛﻪ ﺷﺎﻣﻞ `‪ `<` ،`#‬ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺩﺭﻭﻥ ﻗﻼﺏ ﻗﺮﺍﺭ ﺩﺍﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﻋﻠﺖ ﺍﻳﻦ ﺍﻣﺮ‬ ‫ﺍﻳﻦ ﺍﺳﺖ ﻛﻪ ﺩﺭ ﻛﻞ ﻓﺎﻳﻞ ﺧﺮﻭﺟﻲ ﻃﺮﻳﻘﻪ ﻣﺤﺎﺳﺒﻪ ﻋﺒﺎﺭﺗﻬﺎﯼ ﺷﺮﻃﯽ ﺑﻪ ﺻﻮﺭﺕ ﮔﺮﺍﻑﻣﺴـﻴﺮﺩﺍﺩﻩ ﺑﻴـﺎﻥ ﺷـﺪﻩ‬ ‫ﺍﺳﺖ‪ ،‬ﻟﻴﮑﻦ ﻋﻤﻠﮕﺮﯼ ﮐﻪ ﺑﻪ ﻭﺳﻴﻠﻪ ﺁﻥ ﺣﺎﺻﻞ ﻋﺒﺎﺭﺕ ﺑﺎ ﺻﻔﺮ ﻣﻘﺎﻳﺴﻪ ﻣﻲﺷﻮﺩ‪ ،‬ﺑﻴﺎﻥ ﻧﺸﺪﻩ ﺍﺳﺖ‪ .‬ﺩﺭ ﺍﺩﺍﻣﻪ ﺑـﺎ‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻟﻴﺴﺖ ‪ wires‬ﺧﻄﻲ ﺑﺎ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ WIRE‬ﺍﺿﺎﻓﻪ ﻣﻲﺷﻮﺩ ﻛﻪ ﺩﺭ ﺁﻥ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴـﺎﻧﻲ ﻭ ﺍﺻـﻠﻲ‬ ‫ﺑﻠﻮﻙ ‪ ALWAYS‬ﻭ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺟﺪﻳﺪ ﺣﺎﺻﻞ ﺍﺯ ﭘﺮﺩﺍﺯﺵﺍﻭﻟﻴﻪﻱ ﺳﻴﺴـﺘﻢ ﻫﻤـﺮﺍﻩ ﺑـﺎ ﺍﻧـﺪﺍﺯﻩﻱ ﺁﻧﻬـﺎ ﺩﺭ ﺁﻥ‬ ‫‪۷۵‬‬ ‫ﻣﺸﺨﺺ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﭘﺎﻳﺎﻥ‪ ،‬ﺍﺩﺍﻣﻪﻱ ﻓﺎﻳﻞ ﺩﺭ ﻓﺎﻳﻞ ‪ nt1‬ﻛﭙﻲ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪ -۴-۳-۲-۵‬ﺩﺭﺧﺘﻬﺎﻱ‪:TED‬‬ ‫ﺩﺭ ﺍﺑﺘﺪﺍﻱ ﺍﻳﻦ ﺑﺨﺶ ﺍﺑﺘﺪﺍ ﺗﻮﺿﻴﺤﻲ ﺩﺭ ﻣﻮﺭﺩ ﺳﺎﺧﺘﻤﺎﻥ ﺩﺍﺩﻩ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺑﺮﺍﻱ ﻧﮕﻬﺪﺍﺭﻱ ﮔﺮﻩﻫـﺎﻱ ﮔـﺮﺍﻑ‬ ‫‪ TED‬ﺩﺍﺩﻩ ﺧﻮﺍﻫﺪ ﺷﺪ‪ .‬ﺳﭙﺲ ﺩﺭ ﺍﺩﺍﻣﻪ ﻃﺮﻳﻘﻪ ﺳﺎﺧﺖ ﺍﻳﻦ ﺩﺭﺧﺘﻬﺎ ﺍﺭﺍﻳﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺍﺯ ﺁﻧﺠـﺎ ﻛـﻪ ﮔـﺮﺍﻑ ‪TED‬‬ ‫ﺩﺭ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﺑﺮﺍﻱ ﻭﺍﺭﺳﻲ ﻫﻢ ﺍﺭﺯﻱ ﺍﺳﺘﻔﺎﺩﻩ ﻧﻤﻲﺷﻮﺩ‪ ،‬ﻟﺰﻭﻣﻲ ﺑﻪ ﻳﻜﺘﺎ ﻛﺮﺩﻥ ﺁﻥ ﻭﺟﻮﺩ ﻧﺪﺍﺭﺩ ﻭ ﺩﺭ ﻧﺘﻴﺠـﻪ ﺍﺯ‬ ‫ﺳﺎﺧﺘﻤﺎﻥ ﺩﺍﺩﻩ ﺳﺎﺩﻩﺗﺮﻱ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻭ ﺫﺧﻴﺮﻩ ﺳﺎﺯﻱ ﺁﻥ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫ﺳﺎﺧﺘﻤﺎﻥ ﺩﺍﺩﻩﻱ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺑﺮﺍﻱ ﮔﺮﻩﻫﺎﻱ ‪ :TED‬ﺩﺭ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﺍﺯ ﻛﻼﺱ ‪ TEDNODE‬ﺑﺮﺍﻱ ﻧﻤـﺎﻳﺶ‬ ‫ﮔﺮﻩﻫﺎﻱ ‪ TED‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺎﻻ ﺍﺷﺎﺭﻩ ﺷﺪ ﺑﻪ ﺩﻟﻴﻞ ﺍﻳﻨﻜﻪ ﮔﺮﺍﻓﻬﺎﻱ ‪ TED‬ﺩﺭ ﺍﻳﻦ ﭘﺮﻭﮊﻩ‬ ‫ﺑﺮﺍﻱ ﻭﺍﺭﺳﻲ ﻫﻢ ﺍﺭﺯﻱ ﺍﺳﺘﻔﺎﺩﻩ ﻧﻤﻲﺷﻮﻧﺪ‪ ،‬ﺳﺎﺧﺘﻤﺎﻥ ﺩﺍﺩﻩﻱ ﺳﺎﺩﻩﺗﺮﻱ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﺁﻥ ﺑـﻪ ﻛـﺎﺭ ﻣـﻲﺭﻭﺩ‪ .‬ﺩﺭ‬ ‫ﻧﺘﻴﺠﻪ‪ ،‬ﺑﻪ ﺍﺯﺍﻱ ﺗﺠﺰﻳﻪ ﻋﺒﺎﺭﺕ ﺑﻪ ﺗﻤﺎﻣﻲ ﺿﺮﺍﻳﺐ ﺑﺴﻂ ﺗﻴﻠﻮﺭ ﺁﻥ ﻋﺒﺎﺭﺕ ﺑﺮ ﺍﺳﺎﺱ ﻣﺘﻐﻴﺮ ‪ X‬ﻓﻘﻂ ﺑﻪ ﺩﻭ ﺑﺨﺶ‬ ‫ﺗﻘﺴﻴﻢ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻟﺒﺘﻪ ﺑﺨﺶ ﺩﻭﻡ ﻣﻤﻜﻦ ﺍﺳﺖ ﺑﺎﺯ ﻫﻢ ﺷﺎﻣﻞ ﻣﺘﻐﻴﺮ ‪ X‬ﺑﺎﺷﺪ‪ ،‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺗﺎ ﻫﻨﮕﺎﻣﻲ ﻛـﻪ ﻋﺒـﺎﺭﺕ‬ ‫ﺩﺍﺭﺍﻱ ﻣﺘﻐﻴﺮ ‪ X‬ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺑﺮ ﻣﺒﻨﺎﻱ ﻫﻤﺎﻥ ﻣﺘﻐﻴﺮ ﺗﺠﺰﻳﻪ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﻣﺰﻳﺖ ﺍﻳﻦ ﺭﻭﺵ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﮔـﺮﻩﻫـﺎﻳﻲ‬ ‫ﺑﺎ ﺩﻭ ﺍﺷﺎﺭﻩﮔﺮ ﺑﻪ ﻓﺮﺯﻧﺪﻫﺎﻱ ﺧﻮﺩ ﻣﻲﺑﺎﺷﻨﺪ‪ .‬ﺍﮔﺮ ﺍﺯ ﭘﻴﺎﺩﻩ ﺳﺎﺯﻱ ﻣﺴﺘﻘﻴﻢ ﮔﺮﻩﻫـﺎﻱ ‪ TED‬ﺍﺳـﺘﻔﺎﺩﻩ ﻣـﻲﺷـﺪ ‪،‬‬ ‫ﺗﻌﺪﺍﺩ ﻓﺮﺯﻧﺪﺍﻥ ﻫﺮ ﮔﺮﻩ ﻭﺍﺑﺴﺘﻪ ﺑﻪ ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﺁﻥ ﻣﺘﻐﻴﺮ ﺑﻮﺩ‪ .‬ﻟﺬﺍ ﺑﺎﻳﺪ ﺍﺯ ﺳﺎﺧﺘﻤﺎﻥ ﺩﺍﺩﻩﻫﺎﻳﻲ ﺑـﺎ ﻃـﻮﻝ ﭘﻮﻳـﺎ‬ ‫ﻣﺎﻧﻨﺪ ﻟﻴﺴﺖ‪ ،‬ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻓﺮﺯﻧﺪﺍﻥ ﻫﺮ ﮔﺮﻩ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﺪ ﺍﺯ ﺟﻤﻠﻪﻱ ﺍﻳﻦ ﺳـﺎﺧﺘﻤﺎﻥ ﺩﺍﺩﻩﻫـﺎ ﻣـﻲﺗـﻮﺍﻥ ﺑـﻪ‬ ‫ﻟﻴﺴﺖﭘﻴﻮﻧﺪﯼ ﻳﺎ ﻧﻤﺎﻳﺶ ﺩﺭﺧﺖ ﺑﻪ ﺻﻮﺭﺕ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﭼﭗ – ﺑﺮﺍﺩﺭ ﺳﻤﺖ ﺭﺍﺳﺖ‪ ٣٤‬ﺍﺷـﺎﺭﻩ ﻛـﺮﺩ‪ .‬ﺩﺭ ﺍﻳـﻦ‬ ‫ﺭﻭﺵ ﻫﺮ ﮔﺮﻩ ﺑﻪ ﺩﻭ ﮔﺮﻩ ﺩﻳﮕﺮ ﺍﺷﺎﺭﻩ ﻣﻲﻛﻨﺪ‪ ،‬ﻛﻪ ﻳﻜﻲ ﺍﺯ ﺁﻧﻬﺎ ﻓﺮﺯﻧـﺪ ﺳـﻤﺖ ﭼـﭗ ﺧـﻮﺩ ﻭ ﺩﻳﮕـﺮﻱ ﺑـﺮﺍﺩﺭ‬ ‫ﺳﻤﺖ ﺭﺍﺳﺖ ﺁﻥ ﮔﺮﻩ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻟﻴﻜﻦ ﺍﻳﻦ ﺳﺎﺧﺘﻤﺎﻥ ﺩﺍﺩﻩ ﺩﺍﺭﺍﻱ ﭘﻴﭽﻴﺪﮔﻲ ﻣﺤﺎﺳـﺒﺎﺗﻲ ﻭ ﭘﻴـﺎﺩﻩﺳـﺎﺯﻱ ﺑـﺎﻻﻳﻲ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﻪ ﮔﻮﻧﻪﺍﻱ ﻛﻪ ﺍﻋﻤﺎﻝ ﻗﺎﻋﺪﻩﻱ ﺗﺮﻛﻴﺐ ﺿﺮﺏ ﺩﺭ ﺁﻥ‪ ،‬ﻣﺴﺘﻠﺰﻡ ﻓﺮﺍﺧـﻮﺍﻧﯽ ﺗـﺎﺑﻊ ﺿـﺮﺏ ﺑـﻪ ﺻـﻮﺭﺕ‬ ‫‪leftmost child-right sibling 34‬‬ ‫‪۷۶‬‬ ‫ﺑﺎﺯﮔﺸﺘﻲ ﺑﻪ ﺩﻓﻌﺎﺕ ﺑﺴﻴﺎﺭ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺑﺎﻋﺚ ﺑﺰﺭﮒ ﺷﺪﻥ ﺣﺠﻢ ﺣﺎﻓﻈـﻪ ﭘﺸـﺘﻪ ﻣـﻲﺷـﻮﺩ ‪ .‬ﺍﺯ ﺳـﻮﻱ ﺩﻳﮕـﺮ‬ ‫ﺑﺮﺭﺳﻲ ﻛﺎﺭﻛﺮﺩ ﺷﺒﻴﻪﺳﺎﺯ ﻭ ﺗﻌﻤﻴﻢ ﻣﺪﻝ ‪ TED‬ﺑﺮﺍﻱ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻥ ﮔـﺮﺍﻑ ﺟﺮﻳـﺎﻥ ﺩﺍﺩﻩ ﮐـﻪ ﺩﺭ ﭘﻴـﺎﺩﻩﺳـﺎﺯﯼ‬ ‫ﻧﻬﺎﻳﻲ ﺳﺨﺖﺍﻓﺰﺍﺭ ﮐﺎﺭﺁﻳﯽ ﺩﺍﺭﺩ‪ ،‬ﺩﺭ ﺍﻳﻦ ﻣﺪﻝ ﺁﺳﺎﻥﺗﺮ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﻛﻼﺱ ‪ TEDNODE‬ﻋﻼﻭﻩ ﺑﺮ ﺩﻭ ﺍﺷﺎﺭﻩﮔﺮ ﺑﻪ ﺯﻳﺮﮔﺮﺍﻓﻬﺎﻱ ﺳﻤﺖ ﭼـﭗ ﻭ ﺭﺍﺳـﺖ ﺧـﻮﺩ ﺩﺍﺭﺍﻱ ﭼﻨﺪﻋﻀـﻮ‬ ‫ﺩﻳﮕﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻋﻀﻮ ﺍﻭﻝ ‪ expression‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺍﺯ ﻧﻮﻉ ﺭﺷﺘﻪ ﺍﺳﺖ‪ .‬ﻭﻇﻴﻔﻪﻱ ﺍﻳﻦ ﺭﺷـﺘﻪ ﺫﺧﻴـﺮﻩ ﻋﺒـﺎﺭﺕ‬ ‫ﻣﻌﺎﺩﻝ ﺗﺎﺑﻊ ﺁﻥ ﮔﺮﻩ ﺑﻪ ﺍﺯﺍﻱ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳـﻦ ﻗﺴـﻤﺖ ﺍﺯ ‪ TEDNODE‬ﻓﻘـﻂ ﺑـﺮﺍﻱ ﻣﺮﺣﻠـﻪ‬ ‫‪ debug‬ﻭ ﺑﺮﺭﺳﻲ ﺩﺭﺳﺘﻲ ﻛﺎﺭﻛﺮﺩ ﺑﺮﻧﺎﻣﻪ ﻛﺎﺭﺁﻳﻲ ﺩﺍﺭﺩ ﻭ ﺩﺭ ﻣﺮﺣﻠﻪ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻧﻬﺎﻳﻲ ﻣﻲﺗﻮﺍﻧﺪ ﺣﺬﻑ ﮔﺮﺩﺩ‪.‬‬ ‫ﺍﺯ ﺁﻧﺠﺎ ﻛﻪ ﺩﺭ ﺷﺒﻴﻪ ﺳﺎﺯﻱ ﻧﻤﺎﺩﻳﻦ ﻧﻴﺎﺯﻱ ﺑﻪ ﻳﻜﺘﺎ ﺑﻮﺩﻥ ﻧﻤﺎﻳﺶ ‪ TED‬ﻧﻤﻲﺑﺎﺷﺪ‪ ،‬ﻟﺰﻭﻣﻲ ﺑﻪ ﻛﺎﻫﺶﻳﺎﻓﺘﻪ ﺑـﻮﺩﻥ‬ ‫ﺳﺎﺧﺘﻤﺎﻥﺩﺍﺩﻩﻱ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﺩﺭ ﺍﻳﻦ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻧﻤﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠـﻪ ﺩﺭ ﺍﻳـﻦ ﭘﻴـﺎﺩﻩﺳـﺎﺯﻱ ﺩﺭ ﺍﺯﺍﻱ ﮔـﺮﺍﻑ‬ ‫‪ TED‬ﺍﺯ ﺩﺭﺧﺖ ﺩﻭﺩﻭﻳﻲ ‪ TED‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﮔﺮﺩﺩ‪ .‬ﮐﻪ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻳـﻦ ﺩﺭﺧـﺖ ﻧﻴـﺎﺯﻱ ﺑـﻪ ﻭﺯﻥﺩﺍﺭ ﻛـﺮﺩﻥ‬ ‫ﻳﺎﻟﻬﺎﻱ ﮔﺮﺍﻑ ﻧﻤﻲﺑﺎﺷﺪ ﻭ ﺍﻋﺪﺍﺩ ﺛﺎﺑﺖ ﻓﻘﻂ ﺩﺭ ﮔـﺮﻩ ﺑـﺮﮒ ﺩﺭﺧـﺖ ﻗـﺮﺍﺭ ﻣـﻲﮔﻴﺮﻧـﺪ‪ .‬ﺩﺭ ﻧﺘﻴﺠـﻪ ﺩﺭ ﻛـﻼﺱ‬ ‫‪ TEDNODE‬ﻧﻴﺎﺯﻱ ﺑﻪ ﺍﻓﺰﻭﺩﻥ ﺩﻭﻣﻘﺪﺍﺭ ﻧﻤﺎﻳﻨﺪﻩﻱ ﻭﺯﻥ ﺭﻭﻱ ﻳﺎﻟﻬـﺎ ﻧﻤـﻲﺑﺎﺷـﺪ‪ .‬ﻳﻜـﻲ ﺩﻳﮕـﺮ ﺍﺯ ﻣﺘﻐﻴﺮﻫـﺎﻱ‬ ‫ﻛﻼﺱ ‪ TEDNODE‬ﻣﺘﻐﻴﺮ ‪ size‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﺗﻌﺪﺍﺩ ﺑﻴﺖ ﺧﺮﻭﺟﻲ ﺍﻳﻦ ﮔﺮﻩ ﺭﺍ ﻧﺸـﺎﻥ ﻣـﻲﺩﻫـﺪ‪ ،‬ﺍﻳـﻦ‬ ‫ﻣﻘﺪﺍﺭ ﺑﺮﺍﻱ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺑﻮﻟﻲ ﻳﻚ ﻭ ﺑﺮﺍﻱ ﻛﻠﻤﺎﺕ ‪ ۸‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﺘﻐﻴﺮ ﺑﻌﺪﻱ ﻛﻪ ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﻣﺘﻐﻴﺮ ﺗﺠﺰﻳﻪ ﮔـﺮﻩ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻣﺘﻐﻴﺮ ‪ order‬ﺍﺯ ﻧﻮﻉ ﻋﺪﺩ ﺻﺤﻴﺢ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﻳﻚ ﻓﺎﻳﻞ ‪ ntl‬ﺑﺮﺍﻱ ﺳﺎﺧﺖ ﺩﺭﺧﺘﻬﺎﻱ ‪TED‬‬ ‫ﺻﺪﺍ ﺯﺩﻩ ﻣﻲﺷﻮﺩ‪ .‬ﮔﺮﻩﻫﺎﻱ ﻭﺭﻭﺩﻱ ﺑﻪ ﻋﻨﻮﺍﻥ ‪ TED‬ﻫﺎﻱ ﺍﻭﻟﻴﻪ ﺑﺎ ﺩﺭﺧﺘﻲ ﻛﻪ ﻓﺮﺯﻧـﺪ ﺳـﻤﺖ ﭼـﭗ ﺁﻥ ﺻـﻔﺮ‬ ‫ﻭﻓﺮﺯﻧﺪ ﺳﻤﺖ ﺭﺍﺳﺖ ﺁﻥ ﻳﻚ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺍﺩﺍﻣﻪ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴﺎﻧﻲ ﻧﻤﺎﻳﻨﺪﻩ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷـﺮﻃﻲ‬ ‫ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﻧﺪ ﻛﻪ ﻃﺮﻳﻘﻪ ﺳﺎﺧﺖ ﺩﺭﺧﺖ ﺁﻧﻬﺎ ﺩﺭ ﺑﺨﺶ ﺑﻌﺪﻱ ﺑﻪ ﻃﻮﺭ ﻣﻔﺼﻞ ﺗﻮﺿﻴﺢ ﺩﺍﺩﻩ ﺧﻮﺍﻫﺪ ﺷـﺪ ‪ .‬ﺑـﻪ‬ ‫ﺍﻳﻦ ‪TED‬ﻫﺎﻱ ﺍﻭﻟﻴﻪ ﻳـﻚ ﺷـﻤﺎﺭﻩ ﻣﻨﺤﺼـﺮ ﺑـﻪ ﻓـﺮﺩ ﺩﺍﺩﻩ ﻣـﻲﺷـﻮﺩ‪ ،‬ﺩﺭ ﻧﺘﻴﺠـﻪ ﺍﮔـﺮ ﺩﺭ ﻣﺘﻐﻴـﺮ ‪ order‬ﻳـﻚ‬ ‫‪ TEDNODE‬ﻣﻘﺪﺍﺭ ‪ k‬ﺭﻳﺨﺘﻪ ﺷﻮﺩ ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﺍﻳﻦ ﻣﻮﺿﻮﻉ ﻣﻲﺑﺎﺷـﺪﻛﻪ ﻣﺘﻐﻴـﺮ ﺗﺠﺰﻳـﻪ ﺍﻳـﻦ ﮔـﺮﻩ ‪k‬ﺍﻣـﻴﻦ‬ ‫‪۷۷‬‬ ‫ﻭﺭﻭﺩﻱ ﻳﺎ ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﻲ ﺟﺎﻳﮕﺰﻳﻦ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﮔﺮ ﻣﻘﺪﺍﺭ ﻣﺘﻐﻴﺮ ‪ order‬ﺑﺮﺍﺑﺮ ﺻﻔﺮ ﺑﺎﺷﺪ‪ ،‬ﻳﻌﻨﻲ ﺍﻳﻦ‬ ‫ﮔﺮﻩ ﻳﻚ ﺑﺮﮒﻭ ﻧﻤﺎﻳﻨﺪﻩﻱ ﻳﻚ ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻣﺘﻐﻴﺮ ﺩﻳﮕﺮ ‪ type‬ﺍﺯ ﻧﻮﻉ ﮐﺎﺭﺍﮐﺘﺮ ﻣﻲﺑﺎﺷـﺪ‪ ،‬ﺍﻳـﻦ ﻣﺘﻐﻴـﺮ‬ ‫ﻲ ﻳﮏ ﻣﺘﻐﻴﺮ ﻳﺎ ﻣﺤﺎﺳﺒﻪ ﻳﻚ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﻣﺸﺨﺺ ﻣﻲﻛﻨﺪ ﮐﻪ ﺍﻳﻦ ‪ TED‬ﺑﺮﺍﯼ ﻣﻘﺪﺍﺭﺩﻫ ِ‬ ‫ﻊ ‪ createalways‬ﺧﻄﻮﻁ ﻓﺎﻳـﻞ ﻣﻴـﺎﻧﻲ ‪ ntl‬ﺭﺍ ﺧـﻂ ﺑـﻪ‬ ‫ﻃﺮﻳﻘﻪ ﺳﺎﺧﺖ ﺩﺭﺧﺘﻬﺎﻱ ‪ :TED‬ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠﻪ‪ ،‬ﺗﺎﺑ ِ‬ ‫ﺧﻂ ﻣﻲﺧﻮﺍﻧﺪ‪ .‬ﺍﮔﺮ ﺧﻂ ﺧﻮﺍﻧﺪﻩ ﺷﺪﻩ ﺑﺎ ﻛﻠﻤﻪﻱ ﻛﻠﻴﺪﻱ ‪ INPUT‬ﺷﺮﻭﻉ ﺷﺪ‪ ،‬ﺑﻪ ﻣﻌﻨﻲ ﺍﻳﻦ ﺍﺳﺖ ﻛـﻪ ﻣﻘـﺎﺩﻳﺮ‬ ‫ﺍﻳﻦ ﻣﺘﻐﻴﺮﻫﺎ ﺍﺯ ﺧﺎﺭﺝ ﺑﻪ ﺑﻠﻮﻙ ‪ always‬ﺍﻋﻤﺎﻝ ﻣﻲﺷﻮﺩ‪ .‬ﭘﺲ ﺍﻭﻟﻴﻦ ﺩﺭﺧﺘﻬـﺎﻱ ‪ TED‬ﺩﺭ ﻟﻴﺴـﺖ ‪TED‬ﻫـﺎﻱ‬ ‫ﺑﻠﻮﻙ ‪ TED ،always‬ﻣﻌﺎﺩﻝ ﻭﺭﻭﺩﻳﻬﺎ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻛﻪ ﺑﺎ ﺍﻳﻦ ﺧﺼﻮﺻﻴﺖ ﻛﻪ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﭼـﭗ ﺁﻧﻬـﺎ ﺻـﻔﺮ ﻭ‬ ‫ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﺭﺍﺳﺖ ﺁﻧﻬﺎ ﻳﻚ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺳﺎﺧﺘﻪ ﻣﻲﺷﻮﺩ ﻭ ﺑﻪ ﺗﺮﺗﻴﺒﻲ ﻛﻪ ﺩﺭ ﺧـﻂ ‪ INPUT‬ﻣﻌﺮﻓـﻲ ﺷـﺪﻩﺍﻧـﺪ‬ ‫ﺩﺭﺟﻪﺩﻫﻲ ﻣﻲﺷﻮﻧﺪ‪ ،‬ﻳﻌﻨﻲ ﺍﻭﻟﻴﻦ ﻣﺘﻐﻴﺮ ﺗﻌﺮﻳﻒ ﺷﺪﻩ ﺩﺭ ﺧﻂ ﺑﻪ ﻋﻨﻮﺍﻥ ﻣﺘﻐﻴﺮ ﺑﺎ ﭘﺎﻳﻴﻦﺗﺮﻳﻦ ﺩﺭﺟﻪ ﻳﻌﻨـﻲ ﻳـﻚ‬ ‫ﻣﻘﺪﺍﺭﺩﻫﻲ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺧﻂ ﺑﻌﺪﻱ ﻓﺎﻳﻞ ‪ .ntl‬ﺧﻄﻲ ﺑﺎ ﻛﻠﻤﻪ ﻛﻠﻴﺪﻱ ‪ ifwire‬ﻗﺮﺍﺭ ﺩﺍﺭﺩ ﻛﻪ ﻣﻌﺮﻓـﻲ ﻣﺘﻐﻴﺮﻫـﺎﻱ‬ ‫ﻣﻴﺎﻧﻲ ﺟﺎﻳﮕﺰﻳﻦ ﺷـﺮﻃﻬﺎ ﻭ ﻋﻤﻠﮕـﺮ ﺍﻋﻤـﺎﻝ ﺷـﻮﻧﺪﻩ ﺭﻭﻱ ﻋﺒـﺎﺭﺕ ﺁﻥ ' ‪ `#‬ﻳـﺎ ’<‘ ﺭﺍ ﺑـﺮ ﻋﻬـﺪﻩ ﺩﺍﺭﺩ‪ .‬ﺗـﺎﺑﻊ‬ ‫‪ createalways‬ﺩﺭ ﻫﻨﮕﺎﻡ ﻣﻮﺍﺟﻬﻪ ﺑﺎ ﺍﻳﻦ ﺧﻂ ﺑﺮﺍﻱ ﻫﺮ ﻳﻚ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎ ﺩﻭ ﺩﺭﺧﺖ ‪ TED‬ﺍﻳﺠﺎﺩ ﻣﻲﻛﻨـﺪ‪ ،‬ﻛـﻪ‬ ‫ﺩﺭﺧﺖ ﺍﻭﻝ ﻣﺘﻐﻴﺮ ﺭﺍ ﻛﺎﻣ ﹰ‬ ‫ﻼ ﻣﺸﺎﺑﻪ ﻳﻚ ﻭﺭﻭﺩﻱ ﺑﺮﺍﻱ ﺳﻴﺴﺘﻢ ﻣﻌﺮﻓﻲ ﻣﻲﻛﻨﺪ‪ .‬ﻛـﺎﺭﺑﺮﺩ ﺍﻳـﻦ ‪ TED‬ﺩﺭ ﺳـﺎﺧﺖ‬ ‫‪TED‬ﻫﺎﻳﻲ ﻣﻲﺑﺎﺷﺪ ﮐﻪ ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﺩﺭ ﻣﺤﺎﺳﺒﻪ ﺁﻧﻬﺎ ﺑﻪ ﻛﺎﺭ ﺑﺮﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺩﺭ ‪ TED‬ﺩﻭﻡ ﻣﺘﻐﻴﺮ ﺑـﻪ ﺻـﻮﺭﺕ‬ ‫ﻳﻚ ﺧﺮﻭﺟﻲ ﻣﻌﺮﻓﻲ ﻣﻲﺷﻮﺩ‪ ،‬ﺍﻳﻦ ‪ TED‬ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﻃﺮﻳﻘﻪ ﻣﺤﺎﺳﺒﻪﻱ ﺍﻳـﻦ ﻣﺘﻐﻴـﺮ ﺑﺮﺍﺳـﺎﺱ ﻭﺭﻭﺩﻳﻬـﺎﻱ‬ ‫ﺳﻴﺴﺘﻢ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪ .‬ﺧﻂ ﺑﻌﺪﻱ ﺩﺭ ﻓﺎﻳﻞ ‪ ntl‬ﺧﻂ ‪ output‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ﻫـﺮ ﻳـﻚ ﺍﺯ ﺍﻳـﻦ ﺧﺮﻭﺟﻴﻬـﺎ ﻳـﻚ‬ ‫‪ TED‬ﺧﺎﻟﻲ ﺑﻪ ﻟﻴﺴﺖ ﺍﺿﺎﻓﻪ ﻣﻲﺷﻮﺩ‪ ،‬ﺑﻪ ﻣﺘﻐﻴﺮ ‪ order‬ﺍﻳﻦ ﮔﺮﻩ ﻣﻘﺪﺍﺭ ‪ -۱‬ﻧﺴـﺒﺖ ﺩﺍﺩﻩ ﻣـﻲﺷـﻮﺩ ﻛـﻪ ﻧﺸـﺎﻥ‬ ‫ﻣﻲﺩﻫﺪ ﻛﻪ ﺍﻳﻦ ‪ TED‬ﻫﻨﻮﺯ ﻣﻘﺪﺍﺭﺩﻫﻲ ﻧﺸﺪﻩ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺧـﻂ ﺑﻌـﺪﻱ ﻓﺎﻳـﻞ ‪ ntl‬ﻗﺴـﻤﺖ ‪ wire‬ﻗـﺮﺍﺭ ﺩﺍﺭﺩ‪،‬‬ ‫ﻒ‬ ‫ﻁ ﺗﻌﺮﻳـ ِ‬ ‫ﺑﺮﺍﻱ ‪ wire‬ﻫﺎ ﻧﻴﺰ ‪TED‬ﻫﺎﻳﻲ ﻣﺎﻧﻨﺪ ﻗﺴﻤﺖ ‪ output‬ﺩﺭ ﻟﻴﺴﺖ ﻗﺮﺍﺭ ﺩﺍﺩﻩ ﻣﻲﺷﻮﻧﺪ‪ .‬ﭘـﺲ ﺍﺯ ﺧﻄـﻮ ِ‬ ‫ﻣﺘﻐﻴﺮﻫﺎ‪ ،‬ﻣﻘﺪﺍﺭﺩﻫﻲ ‪wire‬ﻫﺎ ﺑﺮﺍﺳﺎﺱ ﻭﺭﻭﺩﻳﻬﺎ ﻗﺮﺍﺭ ﺩﺍﺭﻧﺪ ﻛﻪ ﺩﺭ ﻗﺴﻤﺖ ‪ precompile‬ﺑﻪ ﺻﻮﺭﺕ ﻋﺒﺎﺭﺗﻬـﺎﻱ‬ ‫‪۷۸‬‬ ‫ﺑﺎ ﻋﻤﻠﮕﺮﻫﺎﯼ ﺩﻭﺩﻭﻳﻲ ﺩﺭﺁﻣﺪﻩﺍﻧﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﻫﺮ ﺧﻂ ﺑﻪ ﭼﻬـﺎﺭ ﻗﺴـﻤﺖ ﻣـﻲﺷـﻮﺩ‪ -۱ :‬ﻋﻤﻠﮕـﺮ ﻣـﻮﺭﺩ‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﻛﻪ ﻳﻜﻲ ﺍﺯ ﺩﻭ ﻋﻤﻠﮕﺮ ’‪ ‘+‬ﻭ ’*‘ ﻣﻲﺑﺎﺷﺪ‪ -۲ ،‬ﺧﺮﻭﺟـﻲ ﻋﺒـﺎﺭﺕ ﺑـﺎﻳﻨﺮﻱ ‪ -۳‬ﻋﻤﻠﻮﻧـﺪﺍﻭﻝ ﻋﻤﻠﮕـﺮ‬ ‫ﺑﺎﻳﻨﺮﻱ ‪ -۴‬ﻋﻤﻠﻮﻧﺪ ﺩﻭﻡ ﻋﻤﻠﮕﺮ ﺑﺎﻳﻨﺮﻱ‪ .‬ﻫﺮ ﻳﻚ ﺍﺯ ﺍﻳﻦ ﺩﻭ ﻋﻤﻠﻮﻧ ِﺪ ﻋﻤﻠﮕﺮ ﺑـﺎﻳﻨﺮﻱ ﻣـﻲﺗﻮﺍﻧـﺪ ﻣﻘـﺪﺍﺭ ﺛﺎﺑـﺖ‬ ‫ﺑﺎﺷﺪ‪ ،‬ﺩﺭ ﺍﻳﻦ ﺻﻮﺭﺕ ﻳﻚ ‪ TED‬ﺟﺪﻳﺪ ﻛﻪ ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩﻱ ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﻣﻲﺑﺎﺷﺪ ﺑﻪ ﻟﻴﺴﺖ ﺍﺿـﺎﻓﻪ ﻣـﻲ ﺷـﻮﺩ‪.‬‬ ‫ﺳﭙﺲ ﺗﺎﺑﻊ ‪ combine‬ﺑﺎ ﻋﻤﻠﮕﺮ ﻭ ﺁﺩﺭﺱ ‪ TED‬ﻋﻤﻠﻮﻧﺪﻫﺎ ﻭ ﺻﺪﺍ ﺯﺩﻩ ﻣﻲﺷﻮﺩ ﺣﺎﺻﻞ ﺍﻳﻦ ﺗﺎﺑﻊ ﻳـﻚ ‪TED‬‬ ‫ﺧﻮﺍﻫﺪ ﺑﻮﺩ ﻛﻪ ﺟﺎﻳﮕﺰﻳﻦ ‪ TED‬ﺧﺮﻭﺟﻲ ﻋﺒﺎﺭﺕ ﺩﺭ ﻟﻴﺴﺖ ‪TED‬ﻫﺎ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫ﺗــﺎﺑﻊ ‪ Combine‬ﻭﻇﻴﻔــﻪﻱ ﺍﻋﻤــﺎﻝ ﻗﻮﺍﻋــﺪ ﺗﺮﻛﻴــﺐ ‪- TED‬ﺑﺮﺍﺳــﺎﺱ ﻋﻤﻠﮕــﺮ ﺑــﺎﻳﻨﺮﻱ‪ -‬ﺑــﺮ ﺭﻭﻱ ﺩﻭ ‪TED‬‬ ‫ﻋﻤﻠﻮﻧﺪﻫﺎﻱ ﺁﻥ‪ ،‬ﺑﺮﺍﻱ ﺳﺎﺧﺖ ‪ TED‬ﺣﺎﺻﻞ ﺭﺍ ﺑﺮ ﻋﻬﺪﻩ ﺩﺍﺭﺩ‪ .‬ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ ﺩﺭ ﭘﻴـﺎﺩﻩﺳـﺎﺯﯼ ﺗﻔﺎﻭﺗﻬـﺎﻳﻲ ﺑـﺎ‬ ‫ﻗﻮﺍﻋﺪ ﺗﺮﮐﻴﺐ ﺍﺻﻠ ِ‬ ‫ﻲ ‪ TED‬ﺩﺍﺭﻧﺪ‪ ،‬ﺍﻳﻦ ﺗﻔﺎﻭﺕ ﺍﺯ ﻳﻜﺘﺎ ﻧﺒﻮﺩﻥ ﺩﺭﺧﺘﻬﺎﻱ ‪ TED‬ﺩﺭ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻧﺎﺷﻲ ﻣﻲﺷـﻮﺩ‪،‬‬ ‫ﺑﻪ ﻃﻮﺭﻱ ﻛﻠﻲ ﻗﻮﺍﻋﺪ ﺗﺮﻛﻴﺐ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺗﻌﺮﻳﻒ ﻛﺮﺩ‪:‬‬ ‫ﺍﮔﺮ ‪ i1‬ﻭ ‪TED ، i2‬ﻫﺎﻱ ﺩﻭ ﻋﻤﻠﻮﻧﺪ ﻋﻤﻠﮕﺮ ‪ op‬ﺑﺎﺷﻨﺪ‪ .‬ﺑﺮﺍﻱ ’‪ op= ‘+‬ﺩﺍﺭﻳﻢ‪:‬‬ ‫‪ -۱‬ﺍﮔﺮ ﻣﺮﺗﺒﻪ ‪ il‬ﻭ ‪ i2‬ﻣﺴﺎﻭﻱ ﺻﻔﺮ ﺑﺎﺷﺪ‪ TED ،‬ﺣﺎﺻﻞ ﺣﺎﺻﻠﺠﻤﻊ ﻣﻘﺪﺍﺭ ﺍﻳﻦ ﺩﻭ ‪ TED‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۲‬ﺍﮔﺮ ﻣﺮﺗﺒﻪ ‪ i1‬ﻭ ‪ i2‬ﻣﺴﺎﻭﻱ ﻭ ﻣﺨﺎﻟﻒ ﺻﻔﺮ ﺑﺎﺷﻨﺪ‪ TED ،‬ﺣﺎﺻﻞ ﺩﺍﺭﺍﻱ ﻣﺮﺗﺒﻪ ﻣﺸﺘﺮﻙ ﻣﻲﺑﺎﺷﺪ ﻭ ﻓﺮﺯﻧـﺪ‬ ‫ﺳﻤﺖ ﭼﭗ ﺁﻥ ﺣﺎﺻﻠﺠﻤﻊ ﻓﺮﺯﻧﺪﻫﺎﻱ ﺳﻤﺖ ﭼﭗ ‪ i1‬ﻭ ‪ i2‬ﻭ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﺭﺍﺳﺖ ﺁﻥ ﺣﺎﺻﻠﺠﻤﻊ ﻓﺮﺯﻧﺪﻫﺎﻱ‬ ‫ﺳﻤﺖ ﺭﺍﺳﺖ ‪ i1‬ﻭ ‪ i2‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪ -۳‬ﺍﮔﺮ ﻣﺮﺗﺒﻪ ‪ i1‬ﻭ ‪ i2‬ﻣﺘﻔﺎﻭﺕ ﻭ ﺑﺮﺍﻱ ﻣﺜﺎﻝ ) ‪ ord (i1 ) > ord (i2‬ﺑﺎﺷﺪ‪ TED .‬ﺣﺎﺻﻞ ﺩﺍﺭﺍﻱ ﻣﺮﺗﺒﻪ ) ‪ord (i1‬‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﻛﻪ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﭼﭗ ﺁﻥ ﺣﺎﺻﻠﺠﻤﻊ ‪ i2‬ﻭ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﭼﭗ ‪ i1‬ﻣﻲ ﺑﺎﺷﺪ ﻭ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﺭﺍﺳـﺖ‬ ‫ﺣﺎﺻﻞ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﺭﺍﺳﺖ ‪ i1‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺑﺮﺍﻱ ’*‘ = ‪ op‬ﺩﺍﺭﻳﻢ‪:‬‬ ‫‪ -۱‬ﺍﮔﺮ ﻣﺮﺗﺒﻪ ‪ i1 , i2‬ﻣﺴﺎﻭﻱ ﺻﻔﺮ ﺑﺎﺷﻨﺪ‪ TED ،‬ﺣﺎﺻﻞ ﺣﺎﺻﻠﻀﺮﺏ ﻣﻘﺪﺍﺭ ﺍﻳﻦ ﺩﻭ ‪ TED‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪۷۹‬‬ ‫‪ -۲‬ﺍﮔﺮ ﻣﺮﺗﺒﻪ ‪ i1‬ﻭ ‪ i2‬ﻣﺴﺎﻭﻱ ﻭ ﻣﺨﺎﻟﻒ ﺻﻔﺮ ﺑﺎﺷﻨﺪ‪ TED ،‬ﺣﺎﺻﻞ ﺑﻪ ﺻﻮﺭﺕ ﺷﻜﻞ ‪ ۵-۵‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۵-۵‬ﺷﮑﻞ ﻣﻌﺎﺩﻝ ﻗﺎﻋﺪﻩ ﺩﻭﻡ ﺗﺮﮐﻴﺐ ﺿﺮﺏ‬ ‫‪ -۳‬ﺍﮔﺮ ﻣﺮﺗﺒـﻪ ‪ i1‬ﻭ ‪ i2‬ﻣﺘﻔـﺎﻭﺕ ﻭ ﺑـﺮﺍﻱ ﻣﺜـﺎﻝ ) ‪ ord (i1 ) > ord (i2‬ﺑﺎﺷـﺪ‪ TED ،‬ﺣﺎﺻـﻞ ﺩﺍﺭﺍﻱ ﻣﺮﺗﺒـﻪﻱ‬ ‫) ‪ ord (i1‬ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻛﻪ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﭼﭗ ﺁﻥ ﺣﺎﺻﻠﻀﺮﺏ ﻓﺮﺯﻧـﺪ ﺳـﻤﺖ ﭼـﭗ ‪ i1‬ﺩﺭ ‪ i2‬ﻭ ﻓﺮﺯﻧـﺪ ﺳـﻤﺖ‬ ‫ﺭﺍﺳﺖ ﺁﻥ ﺣﺎﺻﻠﻀﺮﺏ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﺭﺍﺳﺖ ‪ i1‬ﺩﺭ ‪ i2‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﭘﺲ ﺍﺯ ﺳﺎﺧﺖ ‪ TED‬ﺩﺭ ﺗـﺎﺑﻊ ‪، combine‬‬ ‫ﺑﺎ ﻛﻤﻚ ﺗﺎﺑﻊ ‪ remorexn‬ﺗﻤﺎﻡ ﻗﺴﻤﺘﻬﺎﻳﻲ ﺍﺯ ﺩﺭﺧﺖ ﻛﻪ ﻳﻚ ﻣﻘﺪﺍﺭ ﺑﻮﻟﻲ ﺑـﻪ ﺗـﻮﺍﻥ ﺑﺰﺭﮔﺘـﺮ ﺍﺯ ﺻـﻔﺮ ﺭﺳـﻴﺪﻩ‬ ‫ﺍﺳﺖ ﺣﺬﻑ ﻣﻲﺷﻮﺩ ﻭ ﺑﻪ ﺟﺎﻱ ﺁﻥ ﻣﺘﻐﻴﺮ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﺑﺪﻭﻥ ﺗﻮﺍﻥ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ‪ .‬ﺑﻪ ﺍﻳـﻦ ﺻـﻮﺭﺕ ﻛـﻪ ﺍﮔـﺮ‬ ‫ﻣﺘﻐﻴﺮ ﺗﺠﺰﻳﻪ ﻳﻚ ﮔﺮﻩ ﻣﻘﺪﺍﺭﻱ ﺑﻮﻟﻲ ﺑﻮﺩ ﻭ ﻓﺮﺯﻧﺪ ﺳﻤﺖ ﺭﺍﺳﺖ ﺁﻥ ﻫﻢ ﻫﻤﺎﻥ ﻣﺘﻐﻴﺮ ﺗﺠﺰﻳﻪ ﺭﺍ ﺩﺍﺷـﺖ ﻓﺮﺯﻧـﺪ‬ ‫ﺳﻤﺖ ﺭﺍﺳﺖ ﺭﺍ ﺑﻪ ﻣﺠﻤﻮﻉ ﻓﺮﺯﻧﺪﻫﺎﻱ ﺁﻥ ﺗﺒﺪﻳﻞ ﻣﻲﻛﻨﺪ‪ .‬ﺷﻜﻞ ‪ ۶-۵‬ﻧﺸﺎﻥ ﺩﻫﻨﺪﻩ ﺍﻳﻦ ﻋﻤﻞ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺷﮑﻞ ‪ -۶-۵‬ﺣﺬﻑ ﺗﻮﺍﻥ ﺑﻴﺸﺘﺮ ﺍﺯ ﻳﮏ ﺑﺮﺍﯼ ﻣﺘﻐﻴﺮﻫﺎﯼ ﺑﻮﻟﯽ‬ ‫ﺩﺭ ﭘﺎﻳﺎﻥ ﺗﺤﻠﻴﻞ ﺗﻤﺎﻡ ‪TED‬ﻫﺎﻱ ﻣﻴﺎﻧﻲ ﺑﺎ ﻛﻤﻚ ﺗﺎﺑﻊ ‪ clearwires‬ﺣﺬﻑ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﺗﺎﺑﻊ ‪ TED‬ﺍﻭﻟﻲ ﺭﺍ ﻛﻪ‬ ‫ﺑﺮﺍﻱ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴﺎﻧﻲ ﻣﻌﺎﺩﻝ ﺷﺮﻃﻬﺎ ﺳﺎﺧﺘﻪ ﺷﺪﻩ ﺍﺳﺖ‪ ،‬ﻧﻴﺰ ﺣﺬﻑ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﭘﺎﻳﺎﻥ ﺍﻳﻦ ﻗﺴﻤﺖ ﻳﻚ ﻟﻴﺴـﺖ‬ ‫ﺍﺯ ‪TED‬ﻫﺎﻱ ﺑﻠﻮﻙ ‪ always‬ﺑﻪ ﺗﺎﺑﻊ ﺍﺻﻠﻲ ﻓﺮﺳﺘﺎﺩﻩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪۸۰‬‬ ‫‪ -۴-۲-۵‬ﻣﺮﺗﺐ ﻛﺮﺩﻥ ﺑﻠﻮﻛﻬﺎﻱ ‪always‬‬ ‫ﭘﺲ ﺍﺯ ﺗﺸﻜﻴﻞ ﻟﻴﺴﺖ ‪ always‬ﺑﺎﻳﺪ ﺁﻧﻬﺎ ﺭﺍ ﺑﻪ ﺗﺮﺗﻴﺐ ﺍﺯ ﻭﺭﻭﺩﻱ ﺑـﻪ ﺧﺮﻭﺟـﻲ ﻣﺮﺗـﺐ ﻛـﺮﺩ‪ ،‬ﺍﻳـﻦ ﻣﺮﺗـﺐ‬ ‫ﺳﺎﺯﻱ ﺑﻪ ﻛﻤﻚ ﺗﺎﺑﻊ ‪ sortalways‬ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﻋﻤﻠﻜﺮﺩ ﺍﻳﻦ ﺗﺎﺑﻊ ﻣﺎﻧﻨﺪ ﻣﺮﺗـﺐ ﺳـﺎﺯﻱ ﮔﻴﺘﻬـﺎ ﺩﺭ ﻗﺴـﻤﺖ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﺩﺭ ﺳﻄﺢ ﮔﻴﺖ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﺗﺎﺑﻊ‪ ،‬ﻟﻴﺴﺖ ‪ always‬ﻫﺎ ﺟﺴﺘﺠﻮ ﻣﻲﺷـﻮﺩ ﻭ ﺑﻠـﻮﻛﻲ ﻛـﻪ ﻫﻨـﻮﺯ‬ ‫ﻣﺮﺗﺒﻪ ﺁﻥ ﻣﺸﺨﺺ ﻧﺸﺪﻩ ﺍﺳﺖ ﻣﻮﺭﺩ ﺑﺮﺭﺳﻲ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ‪ .‬ﺍﮔﺮ ﻟﻴﺴـﺖ ﮔـﺮﻩﻫـﺎﻱ ﻣﻮﺟـﻮﺩ ﺩﺭ ﻭﺭﻭﺩﻱ ﺍﻳـﻦ‬ ‫ﺑﻠﻮﻙ ﻫﻤﻪ ﻣﺮﺗﺒﻪ ﺑﻨﺪﻱ ﺷﺪﻩ ﺑﺎﺷﻨﺪ‪ ،‬ﺩﺭﺟﻪ ﺑﻠﻮﻙ ﻭ ﺗﻤﺎﻡ ﺧﺮﻭﺟﻲﻫﺎﻱ ﺁﻥ ﻣﺴﺎﻭﻱ ﻣﺎﻛﺰﻳﻤﻢ ﺩﺭﺟـﻪ ﻭﺭﻭﺩﻳﻬـﺎ‬ ‫ﺑﻪ ﻋﻼﻭﻩ ﻳﻚ ﻗﺮﺍﺭ ﺩﺍﺩﻩﻣﻲﺷﻮﺩ‪ .‬ﺍﻟﺒﺘﻪ ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﺧﺮﻭﺟﻲ ﺑﻠﻮﻙ ﻳﻚ ﺭﺟﻴﺴﺘﺮ ﺑﺎﺷﺪ‪ ،‬ﺩﺭﺟﻪ ﺁﻥ ﺻﻔﺮ ﺑﺎﻗﻲ‬ ‫ﻣﻲﻣﺎﻧﺪ‪ .‬ﺩﺭ ﻫﺮ ﻣﺮﺣﻠﻪ ﺟﺴﺘﺠﻮﻱ ﻟﻴﺴﺖ ‪ always‬ﻫﺎ ﺑﺎﻳﺪ ﺣﺪﺍﻗﻞ ﻳﻜﻲ ﺍﺯ ﺍﻳﻦ ﺑﻠﻮﻛﻬﺎ ﻣﺮﺗﺒﻪ ﺑﻨﺪﻱ ﺷـﻮﻧﺪ‪ .‬ﺩﺭ‬ ‫ﺻﻮﺭﺗﻲ ﻛﻪ ﺩﺭ ﻳﻚ ﻣﺮﺣﻠﻪ ﻫﻴﭻ ﺑﻠﻮﻛﻲ ﺩﺭﺟﻪﺑﻨﺪﻱ ﻧﺸﻮﺩ‪ ،‬ﺗﻤﺎﻡ ﺑﻠﻮﻛﻬﺎ ﻣﺮﺗﺒﻪﺑﻨـﺪﻱ ﺷـﺪﻩﺍﻧـﺪ ﻳـﺎ ﺩﺭ ﻃﺮﺍﺣـﻲ‬ ‫ﻣﺪﺍﺭ ﺍﺷﻜﺎﻟﻲ ﻭﺟﻮﺩ ﺩﺍﺭﺩ‪.‬‬ ‫‪ -۵-۲-۵‬ﺷﺒﻴﻪﺳﺎﺯﻱ ﻣﺪﺍﺭ‬ ‫ﺩﺭ ﭘﺎﻳﺎﻥ ﻣﺮﺣﻠﻪ ﻗﺒﻞ‪ ،‬ﺳﻴﺴﺘﻢ ﺗﻮﺻﻴﻒﺷﺪﻩ‪ ،‬ﻗﺎﺑﻠﻴﺖ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺭﺍ ﭘﻴﺪﺍ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﻣﻘـﺪﺍﺭ ﺍﻭﻟﻴـﻪﻱ‬ ‫ﻭﺭﻭﺩﻳﻬﺎ ﻭ ﺣﺎﻟﺖ ﻓﻌﻠﻲ ﺳﻴﺴﺘﻢ ﻣﺸﺨﺺ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﻋﻤﻞ ﺑﺎ ﻗﺮﺍﺭﺩﺍﺩﻥ ﻣﻘﺪﺍﺭ ﻳـﺎ ﻣﺘﻐﻴـﺮ ﻧﻤـﺎﺩﻳﻦ ﻳـﺎ ﺣﺘـﻲ‬ ‫ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﺁﻥ ﻭﺭﻭﺩﻱ ﺩﺭ ﻣﺘﻐﻴﺮ ‪ value‬ﺁﻥ ﮔﺮﻩ‪ ،‬ﺩﺭ ﻟﻴﺴﺖ ‪ cunwires‬ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺳﭙﺲ ﺷﺒﻴﻪﺳﺎﺯ ﺑﻠﻮﻛﻬﺎﻱ ‪ always‬ﺭﺍ ﺑﻪ ﺗﺮﺗﻴﺐ ﻣﺮﺗﺒﻪ ﺑﺎ ﺗﺎﺑﻊ ‪ evaluate‬ﺻـﺪﺍ ﻣـﻲﺯﻧـﺪ‪ .‬ﺗـﺎﺑﻊ ‪ evaluate‬ﺑـﺎ‬ ‫ﻛﻤﻚ ﻟﻴﺴﺖ ‪ TED‬ﻫﺎﻱ ﺑﻠﻮﻙ ‪ always‬ﻣﻘﺪﺍﺭ ﺗﻚﺗﻚ ﮔﺮﻩﻫﺎﻳﻲ ﻛـﻪ ‪ TED‬ﺁﻧﻬـﺎ ﺩﺭ ﻟﻴﺴـﺖ ﻗـﺮﺍﺭﺩﺍﺭﺩ ﺭﺍ‬ ‫ﻣﺤﺎﺳﺒﻪ ﻣﻲﻛﻨﺪ‪ .‬ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﺩﺭ ﺑﺨـﺶ ﭘﻴـﺎﺩﻩﺳـﺎﺯﻱ ﺑﻠﻮﻛﻬـﺎﻱ ‪ always‬ﮔﻔﺘـﻪ ﺷـﺪ‪ .‬ﺍﻳـﻦ ‪TED‬ﻫـﺎ ﺍﺑﺘـﺪﺍ‬ ‫ﻭﺭﻭﺩﻳﻬﺎﻱ ﻣﺪﺍﺭ‪ ،‬ﺳﭙﺲ ﻣﺘﻐﻴﺮﻫﺎﻱ ﻣﻴﺎﻧﻲ ﺟﺎﻳﮕﺰﻳﻦ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﻭ ﺩﺭ ﭘﺎﻳﺎﻥ ﺧﺮﻭﺟﻴﻬﺎﻱ ﻣﺪﺍﺭ ﻣﻲﺑﺎﺷـﻨﺪ‪.‬‬ ‫ﺩﺭ ﻧﺘﻴﺠﻪ ﺍﻳﻦ ﺗﺎﺑﻊ ﺍﺑﺘﺪﺍ ﻣﻘﺪﺍﺭ ﻣﺘﻐﻴﺮ ‪ expression‬ﺭﺍ ﺑﺮﺍﻱ ‪TED‬ﻫﺎﻱ ﻭﺭﻭﺩﻱ‪ ،‬ﻣﺴﺎﻭﻱ ﻣﻘﺪﺍﺭﻱ ﻗﺮﺍﺭ ﻣﻲﺩﻫﺪ‬ ‫ﻛﻪ ﻟﻴﺴﺖ ‪ cunwire‬ﺑﺮﺍﻱ ﺁﻥ ﻭﺭﻭﺩﻱ ﻗﺮﺍﺭﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﺳﭙﺲ ﻧﻮﺑـﺖ ﺑـﻪ ﻣﺘﻐﻴـﺮﻫـﺎﻱ ﻣﻴـﺎﻧﻲ ﺟـﺎﻳﮕﺰﻳﻨﻲ‬ ‫‪۸۱‬‬ ‫ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﻣﻲﺭﺳﺪ‪ .‬ﺍﻳﻦ ‪ TED‬ﻫﺎ ﺑﻪ ﺻﻮﺭﺕ ﺑﺎﺯﮔﺸﺘﻲ ﺑﺎ ﻋﺒﺎﺭﺕ ﺑﺎﺯﮔﺸﺘﻲ ﺯﻳﺮ ﻣﺤﺎﺳﺒﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪if v is leaf‬‬ ‫‪else‬‬ ‫)‪val (v‬‬ ‫‪TEDeval (v) = ‬‬ ‫))‪TEDeval (lo(v)) + var(v).TEDeval (hi (v‬‬ ‫ﺩﺭ ﻫﺮ ﻣﺮﺣﻠﻪ ﻣﺤﺎﺳﺒﻪ ‪ TED‬ﺍﻣﻜﺎﻥ ﺩﺍﺭﺩ ﻛﻪ )‪ var (v‬ﻛﻪ ﻳﻜﻲ ﺍﺯ ﻭﺭﻭﺩﻳﻬـﺎﻱ ﺑﻠـﻮﻙ ‪ always‬ﻣـﻲﺑﺎﺷـﺪ‪،‬‬ ‫ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﻳﺎ ﻳﻚ ﻋﺒﺎﺭﺕ ﺟﺒﺮﻱ ﺑﻪ ﻋﻨﻮﺍﻥ ‪ experession‬ﺧﻮﺩ ﺫﺧﻴﺮﻩ ﻛﺮﺩﻩ ﺑﺎﺷﺪ ﺩﺭ ﻧﺘﻴﺠﻪ ﻋﻤﻞ ﺿﺮﺏ ﺑـﺎ‬ ‫ﻛﻤﻚ ﺗﺎﺑﻊ ‪ mult‬ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﺗﺎﺑﻊ ﻣﻲﺗﻮﺍﻧﺪ ﺩﻭ ﻋﺒﺎﺭﺕ ﻛﻪ ﺑﻪ ﺻﻮﺭﺕ ﻣﺠﻤﻮﻉ ﭼﻨـﺪ ﻋﺒـﺎﺭﺕ ﺿـﺮﺑﻲ‬ ‫ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﺟﻤﻠﻪ‪-‬ﺟﻤﻠﻪ ﺩﺭﻫﻢ ﺿﺮﺏ ﻛﻨﺪ ﻭ ﻧﺘﻴﺠﻪ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﻣﺠﻤﻮﻉ ﺣﺎﺻﻠﻀﺮﺏ ﺑﺮﮔﺮﺩﺍﻧـﺪ‪ .‬ﺑـﺮﺍﻱ‬ ‫ﺳﺎﺩﻩ ﺷﺪﻥ ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ‪ ،‬ﺍﺯ ﺩﻭ ﺗﺎﺑﻊ ‪ expand‬ﻭ ‪ expardplus‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺩﺭ ﺗـﺎﺑﻊ ‪ expand‬ﻳـﻚ‬ ‫ﻋﺒﺎﺭﺕ ﺿﺮﺑﻲ ﺧﻼﺻﻪ ﻣﻲﺷﻮﺩ ﻭ ﺗﻤﺎﻣﻲ ﻣﻘـﺎﺩﻳﺮ ﺛﺎﺑـﺖ ﺁﻥ ﺑـﻪ ﺻـﻮﺭﺕ ﻳـﻚ ﺿـﺮﻳﺐ ﺩﺭﻣـﻲﺁﻳـﺪ‪ .‬ﺩﺭ ﺗـﺎﺑﻊ‬ ‫‪ expandplus‬ﻣﺠﻤﻮﻉ ﺣﺎﺻﻠﻀﺮﺏ ﺧﻼﺻﻪ ﻣﻲﺷﻮﺩ‪ ،‬ﻳﻌﻨﻲ ﺗﻤﺎﻡ ﺟﻤﻠﻪﻫﺎﻱ ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﺟﻤﻊ ﺯﺩﻩ ﻣﻲﺷﻮﺩ ﻭ‬ ‫ﺑﻪ ﺻﻮﺭﺕ ﻳﻚ ﺟﻤﻠﻪ ﻣﺸﺘﺮﻙ ﺩﺭ ﺍﻧﺘﻬﺎﻱ ﺟﻤﻼﺕ ﺩﻳﮕﺮ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ‪.‬‬ ‫ﺗﺎﺑﻊ ‪ evaluate‬ﺑﺎ ﻳﻚ ﭘﺎﺭﺍﻣﺘﺮ ﻛﺎﺭﺍﻛﺘﺮ ﺻﺪﺍ ﺯﺩﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺍﻳﻦ ﻛﺎﺭﺍﻛﺘﺮ ﺑـﻪ ﺗـﺎﺑﻊ ﻛﻤـﻚ ﻣـﻲﻛﻨـﺪ ﺗـﺎ ﻃﺮﻳﻘـﻪ‬ ‫ﻣﺤﺎﺳﺒﻪ ﻭ ﻧﻮﻉ ﺧﺮﻭﺟﻲ ‪ TED‬ﺭﺍ ﺑﺪﺳﺖ ﺑﻴﺎﻭﺭﺩ‪ .‬ﺍﻳﻦ ﭘﺎﺭﺍﻣﺘﺮ ﻣـﻲﺗﻮﺍﻧـﺪ ﻣﻘـﺎﺩﻳﺮ "=" ‪ "#" ،‬ﻭ "<" ﺭﺍ ﻛﺴـﺐ‬ ‫ﻛﻨﺪ‪ .‬ﻫﻨﮕﺎﻣﻲ ﻛﻪ ﻳﻚ ‪ TED‬ﺑﺎ ﻣﻘﺪﺍﺭ "=" ﺻﺪﺍ ﺯﺩﻩ ﻣﻲﺷﻮﺩ‪ TED ،‬ﺑﻪ ﺻﻮﺭﺕ ﻣﻌﻤـﻮﻝ ﻣﺤﺎﺳـﺒﻪ ﺷـﺪﻩ ﻭ ﺩﺭ‬ ‫‪ expression‬ﺣﺎﺻﻞ ﺭﻳﺨﺘﻪ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ‪ TED‬ﺑﺎ ﻣﻘﺪﺍﺭ "‪ "#‬ﻣﺤﺎﺳﺒﻪ ﺷﻮﺩ‪ ،‬ﻣﻘﺪﺍﺭ ﺣﺎﺻﻞ ﺍﺯ ‪ TED‬ﺑﺎ ﺻﻔﺮ ﻣﻘﺎﻳﺴﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺍﮔـﺮ ﺍﻳـﻦ‬ ‫ﻣﻘﺪﺍﺭ ﻣﺴﺎﻭﯼ ﺻﻔﺮ ﺑﻮﺩ‪ ،‬ﻣﻘﺪﺍﺭ ‪ expression‬ﺑﺮﺍﺑﺮ ﺻﻔﺮ ﻭ ﺩﺭ ﻏﻴﺮ ﺍﻳﻦ ﺻﻮﺭﺕ ﺑﺮﺍﺑـﺮ ﻳـﮏ ﺧﻮﺍﻫـﺪ ﺑـﻮﺩ‪ .‬ﺩﺭ‬ ‫ﻣﻮﺍﻗﻌﯽ ﮐﻪ ﭘﺎﺭﺍﻣﺘﺮ ﺍﺭﺳﺎﻝﺷﺪﻩ ﻣﻘﺪﺍﺭ "<" ﺭﺍ ﺩﺍﺷﺘﻪﺑﺎﺷﺪ‪ ،‬ﺩﺭ ﺻـﻮﺭﺗﯽ ﮐـﻪ ﺣﺎﺻـﻞ ﻣﺤﺎﺳـﺒﻪ ‪ TED‬ﺍﺯ ﺻـﻔﺮ‬ ‫ﻛﻮﭼﻜﺘﺮ ﺑﻮﺩ ﺧﺮﻭﺟﯽ ﻳﻚ ﻭ ﺩﺭ ﻏﻴﺮ ﺍﻳﻦ ﺻﻮﺭﺕ ﺻـﻔﺮ ﺧﻮﺍﻫـﺪ ﺑـﻮﺩ‪ .‬ﺍﻳـﻦ ﭘﺎﺭﺍﻣﺘﺮﻫـﺎ ﻛﻤـﻚ ﻣـﻲﻛﻨـﺪ ﺗـﺎ‬ ‫ﻣﺘﻐﻴﺮﻫﺎﻱ ﺟﺎﻳﮕﺰﻳﻦ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﻣﺤﺎﺳﺒﻪ ﺷﻮﻧﺪ‪ .‬ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﻣﺘﻐﻴﺮ ﺗﺠﺰﻳﻪ ﻳـﻚ ﮔـﺮﻩ ﺍﺯ ﮔـﺮﺍﻑ ‪TED‬‬ ‫ﻳﻜﻲ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎﻱ ﺟﺎﻳﮕﺰﻳﻦ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﺑﺎﺷﺪ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯ ﺑﺮﺍﻱ ﺟﻠـﻮﮔﻴﺮﻱ ﺍﺯ ﺑـﺰﺭﮒ ﺷـﺪﻥ‪ ،‬ﺑـﻲﺍﻧـﺪﺍﺯﻩﻱ‬ ‫‪۸۲‬‬ ‫ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ ‪ experession‬ﻣﻌﺎﺩﻝ ﺁﻥ ﻣﺘﻐﻴﺮ ﺭﺍ ﺑﺮﺭﺳﻲ ﻣﻲﻛﻨﺪ‪ ،‬ﺍﮔﺮ ﻣﻘﺪﺍﺭ ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﺻﻔﺮ ﻳﺎ ﻳـﻚ ﺑـﻮﺩ‪ ،‬ﺍﺯ‬ ‫ﻣﻘﺪﺍﺭ ﺁﻥ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﻏﻴﺮ ﺍﻳﻨﺼﻮﺭﺕ ﻧﺎﻡ ﺁﻥ ﺭﺍ ﺩﺭ ﻋﺒﺎﺭﺕ ﺣﺎﺻﻞ ‪ TED‬ﺟﺎﻳﮕﺰﻳﻦ ﻣﻲﻛﻨﺪ‪ .‬ﺩﺭ ﭘﺎﻳـﺎﻥ‬ ‫ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺣﺎﺻﻞ ﺧﺮﻭﺟﻲ ﻫﺎﻱ ﺑﻠﻮﻙ ‪ always‬ﺩﺭ ﻗﺴﻤﺖ ‪ value‬ﻟﻴﺴﺖ ‪ cunwire‬ﺭﻳﺨﺘﻪ ﻣﻲﺷﻮﺩ ﺗﺎ ﺑـﻪ‬ ‫ﻋﻨﻮﺍﻥ ﺣﺎﻟﺖ ﺑﻌﺪﻱ ﺧﺮﻭﺟﻲ ﻳﺎ ﻭﺭﻭﺩﻱ ﻳﻚ ﺑﻠﻮﻙ ‪ always‬ﺩﻳﮕﺮ ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻗﺮﺍﺭ ﮔﻴﺮﺩ‪.‬‬ ‫‪ -۳-۵‬ﺗﺴﺖ ﺷﺒﻴﻪ ﺳﺎﺯ‬ ‫ﺑﺮﺍﻱ ﺁﺯﻣﺎﻳﺶ ﻋﻤﻠﻜﺮﺩ ﺷﺒﻴﻪﺳﺎﺯ‪ ،‬ﺩﻭ ﻣﺪﺍﺭ ﺳﺎﺩﻩ ﻭ ﻳﻚ ﺭﻳﺰﭘﺮﺩﺍﺯﻧﺪﻩﻱ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ ﻣﻮﺭﺩ ﺑﺮﺭﺳﻲ ﻗـﺮﺍﺭ ﺧﻮﺍﻫﻨـﺪ‬ ‫ﮔﺮﻓﺖ ﻭ ﺩﺭ ﻫﺮ ﻣﻮﺭﺩ ﻧﺘﺎﻳﺞ ﺍﻋﻤﺎﻝ ﻳﻚ ﻳﺎ ﭼﻨﺪ ﻭﺭﻭﺩﻱ ﺑﺮﺭﺳﻲ ﺧﻮﺍﻫﺪ ﺷﺪ‪.‬‬ ‫‪ -۱-۳-۵‬ﻣﺪﺍﺭ ﺑﺎ ﻗﺴﻤﺖ ﻛﻨﺘﺮﻟﻲ ﺑﻮﻟﻲ ﻭ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺟﺒﺮﻱ‬ ‫ﺑﻪ ﻋﻨﻮﺍﻥ ﺍﻭﻟﻴﻦ ﻣﺪﺍﺭ ﻳﻚ ‪ ALU‬ﺑﺴﻴﺎﺭ ﺳﺎﺩﻩ ﺑﺎ ‪ ۴‬ﺩﺳﺘﻮﺭ ﻭ ‪ ۲‬ﺑﻴﺖ ﻛﻨﺘﺮﻟﻲ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺷﺪﻩﺍﺳـﺖ‪ .‬ﻗﺴـﻤﺘﻬﺎﻳﻲ‬ ‫ﺍﺯ ﻛﺪ ﺑﻪ ﺻﻮﺭﺗﻲ ﺗﻐﻴﻴﺮ ﻳﺎﻓﺘﻪﺍﻧﺪ ﺗﺎ ﺑﺮﺍﻱ ﺑﺮﺭﺳﻲ ﻧﻜﺎﺕ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺷﺪﻩ ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯ ﻣﻤﻜﻦ ﮔـﺮﺩﺩ‪ .‬ﺍﺯ ﺟﻤﻠـﻪ‬ ‫ﺑﻪ ﺗﻮﺍﻥ ﺭﺳﺎﻧﺪﻥ ﻳﻚ ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ ﻭ ﻳﺎ ﺍﻋﻤﺎﻝ ﺑﻮﻟﻲ ﺯﺍﻳﺪ ﺩﺭ ﻗﺴﻤﺖ ﻛﻨﺘﺮﻟﻲ ﻣﺪﺍﺭ‪ .‬ﺗﻮﺻﻴﻒ ﺳﻄﺢ ‪ RTL‬ﻣـﺪﺍﺭ‬ ‫‪ ALU‬ﺷﺎﻣﻞ ﻳﻚ ﺑﻠﻮﻙ ‪ always‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﻛﺪ ﺑﻠﻮﻙ ‪ always‬ﻣﺪﺍﺭ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻧﻮﺷﺘﻪﺷﺪﻩﺍﺳﺖ‪:‬‬ ‫‪always‬‬ ‫;)]‪input(a[8], b[8], f[1], g[1‬‬ ‫;)]‪output(h[8], c[8], d[8‬‬ ‫;)]‪wire(i[1‬‬ ‫;‪i = ~g @ f‬‬ ‫;‪d = (g^5)*a‬‬ ‫;‪c = a‬‬ ‫))‪if ((f & g == 1) | (i == 1‬‬ ‫)‪if (f == 1‬‬ ‫;‪h = a + b‬‬ ‫‪else‬‬ ‫;‪h = a‬‬ ‫;‪endif‬‬ ‫‪else‬‬ ‫;‪d = c‬‬ ‫)‪if (g == 1‬‬ ‫;‪h = a - b‬‬ ‫‪else‬‬ ‫;‪h = b‬‬ ‫;‪endif‬‬ ‫‪۸۳‬‬ ‫;‪endif‬‬ ‫ﭘﺲ ﺍﺯ ﺣﺬﻑ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﺩﺭ ﺑﻠﻮﻙ ‪ always‬ﻛﺪ ‪ nof‬ﺣﺎﺻﻞ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪:‬‬ ‫‪ALWAYS‬‬ ‫;)]‪INPUT(A[8],B[8],F[1],G[1‬‬ ‫;)]‪OUTPUT(H[8],C[8],D[8‬‬ ‫;)]‪WIRE(I[1‬‬ ‫;‪I=~G@F‬‬ ‫;‪D=(G^5)*A‬‬ ‫;‪C=A‬‬ ‫;)‪WIRE100002#(F&G)-(1‬‬ ‫;)‪WIRE100003#(I)-(1‬‬ ‫;))‪WIRE100001=(~(WIRE100002)|~(WIRE100003‬‬ ‫;)‪WIRE100005#(F)-(1‬‬ ‫;)‪WIRE100004=~(WIRE100005‬‬ ‫;))‪H=(1&WIRE100001&WIRE100004&(A+B‬‬ ‫‪H=(~(1&WIRE100001&~(WIRE100004))&(H)+‬‬ ‫;)))‪(1&WIRE100001&~(WIRE100004)&(A‬‬ ‫;)))‪D=(~(1&~(WIRE100001))&(D)+(1&~(WIRE100001)&(C‬‬ ‫;)‪WIRE100007#(G)-(1‬‬ ‫;)‪WIRE100006=~(WIRE100007‬‬ ‫‪H=(~(1&~(WIRE100001)&WIRE100006)&(H)+‬‬ ‫;)))‪(1&~(WIRE100001)&WIRE100006&(A-B‬‬ ‫‪H=(~(1&~(WIRE100001)&~(WIRE100006))&(H)+‬‬ ‫;)))‪(1&~(WIRE100001)&~(WIRE100006)&(B‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﻣﺸﺎﻫﺪﻩ ﻣﻲﺷﻮﺩ‪ ،‬ﺗﻌﺪﺍﺩﻱ ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﻲ ﻭﻇﻴﻔﻪ ﺑﺮﺭﺳﻲ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷـﺮﻃﻲ ﻣﻮﺟـﻮﺩ ﺩﺭ ﺷـﺮﻃﻬﺎﻱ‬ ‫ﺗﻮﺻﻴﻒ ﺭﺍ ﺑﺮ ﻋﻬﺪﻩ ﺩﺍﺭﻧﺪ‪ ،‬ﻛﻪ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﺑﻪ ﮔﻮﻧﻪﺍﻱ ﺑﺎﺯﻧﻮﻳﺴﻲ ﺷﺪﻩ ﺍﺳﺖ ﺗﺎ ﺑﺘﻮﺍﻥ ﺁﻥ ﺭﺍ ﺑـﺎ ﺩﻭ ﻋﻤﻠﮕـﺮ‬ ‫'‪ '!= 0‬ﻭ ‪ < 0‬ﻧﻤﺎﻳﺶ ﺩﺍﺩ ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﺑﻪ ﺟﺎﻱ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ‪ f&g == 1‬ﻣﺘﻐﻴـﺮ ﻣﻴـﺎﻧﻲ ‪ WIRE100002‬ﺑـﻪ‬ ‫ﺻﻮﺭﺕ )‪ WIRE100002#(F&G)-(1‬ﺗﻌﺮﻳﻒ ﺷﺪﻩﺍﺳـﺖ‪ .‬ﺩﺭ ﻋﺒﺎﺭﺗﻬـﺎﻳﻲ ﻛـﻪ ﻣﻘـﺪﺍﺭﺩﻫﻲ ﺑـﻪ ﻳـﻚ ﻣﺘﻐﻴـﺮ‬ ‫ﻣﺸﺮﻭﻁ ﺑﻪ ﺩﺭﺳﺖ ﺑﻮﺩﻥ ﺍﻳﻦ ﻋﺒﺎﺭﺕ ﺷﺮﻃﻲ ﻣﻲﺑﺎﺷـﺪ‪ ،‬ﻧﻘـﻴﺾ ‪ WIRE100002‬ﺩﺭ ﺁﻥ ﻣﻘـﺪﺍﺭ ﺩﻫـﻲ ‪AND‬‬ ‫ﺷﺪﻩﺍﺳﺖ‪ .‬ﭘﺲ ﺍﺯ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ﺳﺎﺧﺖ ﻓﺎﻳﻞ ‪ ntl‬ﻛﻪ ﺷﺎﻣﻞ ﻣﻌﺎﺩﻝ ﺗﻮﺻﻴﻒ ﺑﺎ ﻋﻤﻠﮕﺮﻫﺎﻱ ﺩﻭﺩﻭﻳﻲ ﻣـﻲﺑﺎﺷـﺪ‪،‬‬ ‫ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﭘﺎﻳﺎﻥ ﺍﻳﻦ ﻣﺮﺣﻠﻪ ‪ ۹۲‬ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﻲ ﺩﺭ ﻣﺪﺍﺭ ﺍﺿﺎﻓﻪ ﻣﻲﺷـﻮﺩ ﻗﺴـﻤﺘﻲ ﺍﺯ ﻛـﺪ ﺣﺎﺻـﻞ ﺑـﺮﺍﻱ‬ ‫ﻣﺤﺎﺳﺒﻪ ‪ i‬ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻣﻲﺑﺎﺷﺪ‪:‬‬ ‫;)‪*(WIRE100009,-1,G‬‬ ‫;)‪+(WIRE100008,1,WIRE100009‬‬ ‫;)‪*(WIRE100012,-1,2‬‬ ‫;)‪*(WIRE100015,-1,G‬‬ ‫;)‪+(WIRE100014,1,WIRE100015‬‬ ‫;)‪*(WIRE100013,WIRE100014,F‬‬ ‫;)‪*(WIRE100011,WIRE100012,WIRE100013‬‬ ‫‪۸۴‬‬ ‫;)‪+(WIRE100010,F,WIRE100011‬‬ ‫;)‪+(I,WIRE100008,WIRE100010‬‬ ‫ﺣﺎﻝ ﺑﺮﺍﻱ ﺷﺒﻴﻪﺳﺎﺯﻱ‪ ،‬ﻣﻘﺎﺩﻳﺮ ﺯﻳﺮ ﺑﻪ ﺷﺒﻴﻪﺳﺎﺯ ﺍﻋﻤﺎﻝ ﻣﻲﺷﻮﺩ‪ F = 0 ، B = B ،A = A :‬ﻭ‪.G = 0‬‬ ‫ﺧﺮﻭﺟﻲ ﺷﺒﻴﻪﺳﺎﺯ ﺍﺑﺘﺪﺍ ﺯﻣﺎﻥ ﺳﺎﺧﺖ ‪ TED‬ﺭﺍ ﺑﻴﺎﻥ ﻣﻲﻛﻨﺪ‪ .‬ﺷﺒﻴﻪﺳﺎﺯ ﺭﻭﻱ ﻳﻚ ﻛـﺎﻣﭙﻴﻮﺗﺮ ﺑـﺎ ﭘﺮﺩﺍﺯﻧـﺪﻩ ‪P4‬‬ ‫‪ 2GHZ‬ﺑﺎ ‪ 256MB‬ﺣﺎﻓﻈﻪ ﻭ ﺳﻴﺴﺘﻢ ﻋﺎﻣﻞ ‪ ، Windows XP‬ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻣﺤـﻴﻂ ﺑﺮﻧﺎﻣـﻪﻧﻮﻳﺴـﻲ ‪Visual‬‬ ‫‪ Studion .net‬ﻭ ﺩﺭ ﺣﺎﻟﺖ ‪ Debug‬ﺍﺟﺮﺍ ﺷﺪﻩ ﺍﺳﺖ‪ .‬ﻧﺘﺎﻳﺞ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻣﻲﺑﺎﺷﺪ‪:‬‬ ‫‪Program takes‬‬ ‫‪0 seconds.‬‬ ‫‪A = A = A‬‬ ‫‪B = B = B‬‬ ‫‪F = F = 0‬‬ ‫‪G = G = 0‬‬ ‫‪WIRE100002 # (-1+G*F) = 1‬‬ ‫‪WIRE100003 # (F*(-1)+G*(-1+F*2)) = 0‬‬ ‫‪WIRE100005 # (-1+F) = 1‬‬ ‫‪WIRE100007 # (-1+G) = 1‬‬ ‫‪H = ((((A+B)+WIRE100003*WIRE100002*B*(-2))+‬‬ ‫‪WIRE100005*(B*(1)+WIRE100003*WIRE100002*B))+‬‬ ‫‪WIRE100007*(WIRE100003*WIRE100002*(A*(-1)+B*2)+‬‬ ‫))))‪WIRE100005*WIRE100003*WIRE100002*(B+WIRE100002*B*(-1‬‬ ‫‪= B*-1+B+A‬‬ ‫‪C = A = A‬‬ ‫‪D = (G*A+WIRE100003*WIRE100002*(A+G*A*(-1))) = 0‬‬ ‫ﺩﺭ ﺧﻂ ﺍﻭﻝ ﻧﺘﺎﻳﺞ ﺯﻣﺎﻥ ﺍﺟﺮﺍﻱ ﺑﺮﻧﺎﻣﻪ ﺑﺮﺍﻱ ﺳﺎﺧﺖ ﮔﺮﺍﻑ ‪ TED‬ﺑﻴﺎﻥ ﻣـﻲﺷـﻮﺩ‪ .‬ﺩﺭ ﺧﻄـﻮﻁ ﺑﻌـﺪﻱ ﻧﺘـﺎﻳﺞ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﺎ ﺍﻟﮕﻮﻱ ﺯﻳﺮ ﻧﻮﺷﺘﻪ ﻣﻲﺷﻮﺩ‪ .‬ﺍﺑﺘﺪﺍ ﻧﺎﻡ ﻣﺘﻐﻴﺮ‪ ،‬ﺳﭙﺲ ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﺁﻥ ﻭ ﺩﺭ ﺍﺩﺍﻣﻪ ﻣﻘﺪﺍﺭ ﺍﻳﻦ ﻣﺘﻐﻴﺮ‬ ‫ﺩﺭ ﭘﺎﻳﺎﻥ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ‪ .‬ﺑﺎ ﺍﻳﻦ ﻣﻘﺪﺍﺭﺩﻫﻲ ﺍﻭﻟﻴﻪ ﻣﺘﻐﻴﺮﻫﺎ ﺩﺭ ﻛﺪ ﺍﺻﻠﻲ ﻣﻘﺪﺍﺭ ‪ H‬ﺑﺮﺍﺑﺮ ﺑﺎ ‪ A‬ﺧﻮﺍﻫـﺪ‬ ‫ﺑﻮﺩ‪ .‬ﺧﺮﻭﺟﻲ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﺮﺍﻱ ﺍﻳﻦ ﻣﻘﺎﺩﻳﺮ ﺍﻭﻟﻴﻪ ‪ B*-1+B+A‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻣﻌﺎﺩﻝ ‪ A‬ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺣﺎﻟﺖ ﺩﻭﻡ‬ ‫ﻣﻘﺎﺩﻳﺮ ﺍﻭﻟﻴﻪ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺩﺭ ﻧﻈﺮ ﻣﻲﮔﻴﺮﻳﻢ‪ F = 1 ، B = B ، A = A‬ﻭ‪.G = 0‬‬ ‫ﺣﺎﺻﻞ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪:‬‬ ‫‪Program takes‬‬ ‫‪0 seconds.‬‬ ‫‪A = A = A‬‬ ‫‪B = B = B‬‬ ‫‪F = 1 = 1‬‬ ‫‪G = 0 = 0‬‬ ‫‪WIRE100002 # (-1+G*F) = 1‬‬ ‫‪۸۵‬‬ ‫‪WIRE100003 # (F*(-1)+G*(-1+F*2)) = 1‬‬ ‫‪WIRE100005 # (-1+F) = 0‬‬ ‫‪WIRE100007 # (-1+G) = 1‬‬ ‫‪H = ((((A+B)+WIRE100003*WIRE100002*B*(-2))+‬‬ ‫‪WIRE100005*(B*(-1)+WIRE100003*WIRE100002*B))+‬‬ ‫‪WIRE100007*(WIRE100003*WIRE100002*(A*(-1)+B*2)+‬‬ ‫))))‪WIRE100005*WIRE100003*WIRE100002*(B+WIRE100002*B*(-1‬‬ ‫‪= B*2+A*-1+B*-2+B+A‬‬ ‫‪C = A = A‬‬ ‫‪D = (G*A+WIRE100003*WIRE100002*(A+G*A*(-1))) = A‬‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﻛﻪ ﻣﺸﺎﻫﺪﻩ ﻣﻲﺷﻮﺩ ﺩﺭ ﺍﻳﻦ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻣﻘـﺪﺍﺭ ﺧﺮﻭﺟـﻲ ‪ H‬ﺑﺮﺍﺑـﺮ ﺑـﺎ ‪B*2+A*-1+B*-2+B+A‬‬ ‫ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻣﻌﺎﺩﻝ ﻣﻘﺪﺍﺭ ‪ B‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺑﺎ ﻓﺮﺽ ‪ F=1‬ﻭ ‪ G=0‬ﺗﻄﺎﺑﻖ ﺩﺍﺭﺩ‪.‬‬ ‫ﺍﻳﻦ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﺮﺍﻱ ﻣﻘﺎﺩﻳﺮ ﺍﻭﻟﻴﻪ ﺯﻳﺮ ﻧﻴﺰ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺷﺪﻩ ﺍﺳﺖ ﻭ ‪ H‬ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺑﺪﺳﺖ ﻣﻲﺁﻳﺪ‪.‬‬ ‫‪A = A, B = B‬‬ ‫‪F = 0, G = 1‬‬ ‫‪H = B+B*-1+B*-2+B+A‬‬ ‫ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ ﻣﻘﺪﺍﺭ ﻣﺘﻐﻴﺮ ‪ H‬ﺑﺮﺍﺑﺮ ﺑﺎ ‪ A-B‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪A = A, B = B‬‬ ‫‪F = 1, G = 1‬‬ ‫‪H = B+A‬‬ ‫‪ -۲-۳-۵‬ﻣﺪﺍﺭ ﺑﺎ ﻗﺴﻤﺖ ﻛﻨﺘﺮﻟﻲ ﻭ ﻣﺴﻴﺮ ﺩﺍﺩﻩ ﺳﻄﺢ ﻛﻠﻤﻪ‬ ‫ﺑﻪ ﻋﻨﻮﺍﻥ ﺩﻭﻣﻴﻦ ﻣﺪﺍﺭ ﻳﻚ ﺳﻴﺴﺘﻢ ﺑﺎ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﺳﻄﺢ ﻛﻠﻤﻪ ﻣـﻲﺑﺎﺷـﺪ‪ .‬ﺗﻮﺻـﻴﻒ ﺳـﻄﺢ ‪ RTL‬ﻣـﺪﺍﺭ‬ ‫ﺷﺎﻣﻞ ﻳﻚ ﺑﻠﻮﻙ ‪ always‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺑﺮﺍﻱ ﺑﺮﺭﺳﻲ ﻋﻤﻠﮕﺮﻫﺎﻱ ﺷﺮﻃﻲ ﺩﺭ ﺍﻳﻦ ﻛﺪ ﺍﺯ ﺗﻤـﺎﻡ ﺁﻧﻬـﺎ ﺩﺭ ﺗﻮﺻـﻴﻒ‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﺷﺪﻩﺍﺳﺖ‪ .‬ﻛﺪ ﺑﻠﻮﻙ ‪ always‬ﻣﺪﺍﺭ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﻧﻮﺷﺘﻪﺷﺪﻩﺍﺳﺖ‪:‬‬ ‫‪always‬‬ ‫;)]‪input(a[8], b[8], f[1], g[1‬‬ ‫;)]‪output(h[8], c[8‬‬ ‫;)]‪wire(d[8], m[8], e[8], i[1‬‬ ‫;‪i = ~g @ f‬‬ ‫;‪d = (g^5)*a‬‬ ‫;‪m = a - d‬‬ ‫;)‪e = d * -(m + b‬‬ ‫;‪c = a‬‬ ‫))‪if (((a * b) + b != d) & (i == 1‬‬ ‫;‪i = g | f‬‬ ‫))‪if ((e > d) | (m <= b‬‬ ‫;‪h = -(d) + 2 * m‬‬ ‫‪else‬‬ ‫;‪h = m‬‬ ‫;‪endif‬‬ ‫‪۸۶‬‬ else d = e; if ((c < d) | (m == e)) h = m + e * d; else h = e - d; endif; endif; :‫ ﺣﺎﺻﻞ ﺑﻪ ﺻﻮﺭﺕ ﺯﻳﺮ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‬nof ‫ ﻛﺪ‬always ‫ﭘﺲ ﺍﺯ ﺣﺬﻑ ﻋﺒﺎﺭﺗﻬﺎﻱ ﺷﺮﻃﻲ ﺩﺭ ﺑﻠﻮﻙ‬ ALWAYS INPUT(A[8],B[8],F[1],G[1]); OUTPUT(H[8],C[8]); WIRE(D[8],M[8],E[8],I[1]); I=~G@F; D=(G^5)*A; M=A-D; E=D*-(M+B); C=A; WIRE100002#((A*B)+B)-(D); WIRE100003#(I)-(1); WIRE100001=((WIRE100002)&~(WIRE100003)); I=(~(1&WIRE100001)&(I)+(1&WIRE100001&(G|F))); WIRE100005<(D)-(E); WIRE100006<(M)-(B)-1; WIRE100004=((WIRE100005)|(WIRE100006)); H=(1&WIRE100001&WIRE100004&(-(D)+2*M)); H=(~(1&WIRE100001&~(WIRE100004))&(H)+ (1&WIRE100001&~(WIRE100004)&(M))); D=(~(1&~(WIRE100001))&(D)+(1&~(WIRE100001)&(E))); WIRE100008<(C)-(D); WIRE100009#(M)-(E); WIRE100007=((WIRE100008)|~(WIRE100009)); H=(~(1&~(WIRE100001)&WIRE100007)&(H)+ (1&~(WIRE100001)&WIRE100007&(M+E*D))); H=(~(1&~(WIRE100001)&~(WIRE100007))&(H)+ (1&~(WIRE100001)&~(WIRE100007)&(E-D))); -‫ ﺍﺑﺘﺪﺍ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﻪ ﺻﻮﺭﺕ ﭘﺎﺭﺍﻣﺘﺮﻱ ﺍﻧﺠـﺎﻡ ﻣـﻲ‬،‫ﺣﺎﻝ ﺍﻳﻦ ﺳﻴﺴﺘﻢ ﺑﺎ ﺷﺮﺍﻳﻂ ﺍﻭﻟﻴﻪ ﻣﺘﻔﺎﻭﺕ ﺑﺮﺭﺳﻲ ﻣﻲﺷﻮﺩ‬ :‫ﺷﻮﺩ‬ A = A = A B = B = B F = F = F G = G = G WIRE100002 # (B*(1+A)+G*A*(-1)) = G*A*-1+B*A+B WIRE100003 # (F*(-1)+G*(-1+F*2)) = G*F*2+G*-1+F*-1 WIRE100005 < G*(A+B*A) = G*B*A+G*A WIRE100006 < (((-1+A)+B*(-1))+G*A*(-1)) = G*A*-1+B*-1+A+-1 WIRE100008 < (((A+G*B*A)+WIRE100002*G*(A*(-1)+B*A*(-1)))+ WIRE100003*WIRE100002*G*(A+B*A)) = WIRE100003*WIRE100002*G*B*A+ WIRE100003*WIRE100002*G*A+ ۸۷ ‫‪WIRE100002*G*B*A*-1+WIRE100002*G*A*-1+G*B*A+A‬‬ ‫‪WIRE100009 # (A+G*(A*(-1)+B*A)) = G*B*A+G*A*-1+A‬‬ ‫ﺩﺭ ﮔﺎﻡ ﺑﻌﺪﻱ ﺷﺒﻴﻪﺳﺎﺯﻱ ﻳﻚ ﻋﺒﺎﺭﺕ ﺟﺎﻳﮕﺰﻳﻦ ﻳﻜﻲ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎ ﻣﻲﺷﻮﺩ‪:‬‬ ‫‪A= C+D, B = 0‬‬ ‫‪Program takes‬‬ ‫‪1 seconds.‬‬ ‫‪A = C+D = C+D‬‬ ‫‪B = 0 = 0‬‬ ‫‪F = F = F‬‬ ‫‪G = G = G‬‬ ‫‪WIRE100002 # (B*(1+A)+G*A*(-1)) = G*C*-1+G*D*-1‬‬ ‫‪WIRE100003 # (F*(-1)+G*(-1+F*2)) = G*F*2+G*-1+F*-1‬‬ ‫‪WIRE100005 < G*(A+B*A) = G*C+G*D‬‬ ‫‪WIRE100006 < (((-1+A)+B*(-1))+G*A*(-1)) = G*C*-1+G*D*-1+C+D+-1‬‬ ‫‪WIRE100008 < (((A+G*B*A)+WIRE100002*G*(A*(-1)+B*A*(-1)))+‬‬ ‫))‪WIRE100003*WIRE100002*G*(A+B*A‬‬ ‫‪= WIRE100003*WIRE100002*G*C+‬‬ ‫‪WIRE100003*WIRE100002*G*D+‬‬ ‫‪WIRE100002*G*C*-1+WIRE100002*G*D*-1+C+D‬‬ ‫‪WIRE100009 # (A+G*(A*(-1)+B*A)) = G*C*-1+G*D*-1+C+D‬‬ ‫‪C = A = C+D‬‬ ‫ﺩﺭ ﭘﺎﻳﺎﻥ ﺩﺭ ﺍﺯﺍﻱ ﻫﺮ ﻳﻚ ﺍﺯ ﻣﺘﻐﻴﺮﻫﺎ ﻳﻚ ﻣﻘﺪﺍﺭ ﺛﺎﺑﺖ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ‪:‬‬ ‫‪A = 10 B= 15 F = 0 G = 1‬‬ ‫‪A = 10 = 10‬‬ ‫‪B = 15 = 15‬‬ ‫‪F = 0 = 0‬‬ ‫‪G = 1 = 1‬‬ ‫‪WIRE100002 # (B*(1+A)+G*A*(-1)) = 1‬‬ ‫‪WIRE100003 # (F*(-1)+G*(-1+F*2)) = 1‬‬ ‫‪WIRE100005 < G*(A+B*A) = 0‬‬ ‫‪WIRE100006 < (((-1+A)+B*(-1))+G*A*(-1)) = 1‬‬ ‫‪WIRE100008 < (((A+G*B*A)+WIRE100002*G*(A*(-1)+B*A*(-1)))+‬‬ ‫))‪WIRE100003*WIRE100002*G*(A+B*A‬‬ ‫‪= 0‬‬ ‫‪WIRE100009 # (A+G*(A*(-1)+B*A)) = 1‬‬ ‫‪H = 0‬‬ ‫‪C = A = 10‬‬ ‫ﺗﻮﺟﻪ ﻛﻨﻴﺪ ﻛﻪ ﺩﺭ ﺍﻳﻦ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺑﻪ ﻋﻠﺖ ﺑﺰﺭﮒ ﺑﻮﺩﻥ ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﻣﺘﻐﻴﺮ ‪ H‬ﺍﺯ ﺑﻴﺎﻥ ﺁﻥ ﭼﺸﻢﭘﻮﺷﻲ ﺷﺪﻩ‪-‬‬ ‫ﺍﺳﺖ‪.‬‬ ‫‪ -۳-۳-۵‬ﭘﺮﺩﺍﺯﻧﺪﻩﻱ ‪Parwan‬‬ ‫ﺩﺭ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﺍﺯ ﭘﺮﺩﺍﺯﻧﺪﻩﻱ ‪ parwan‬ﻛﻪ ﺗﻮﺳﻂ ﮔﺮﻭﻩ ﺩﻛﺘﺮ ﻧﻮﺍﺑﻲ ﻃﺮﺍﺣﻲ ﻭ ﭘﻴﺎﺩﻩﺳـﺎﺯﻱ ﺷـﺪﻩ‪ ،‬ﺑـﻪ ﻋﻨـﻮﺍﻥ‬ ‫ﻣﺪﺍﺭ ﺍﺳﺘﺎﻧﺪﺍﺭﺩﻱ ﻛﻪ ﺷﺒﻴﻪﺳﺎﺯﻱ ﺭﻭﻱ ﺁﻥ ﺍﻧﺠﺎﻡ ﺧﻮﺍﻫـﺪ ﺷـﺪ ﺍﺳـﺘﻔﺎﺩﻩ ﺷـﺪﻩ ﺍﺳـﺖ]‪ .[۲۷‬ﻣـﺪﻝ ﻭ ﻛـﺪ ﺍﻳـﻦ‬ ‫‪۸۸‬‬ ‫ﭘﺮﺩﺍﺯﻧﺪﻩ ﺩﺭ ﻣﺮﺟﻊ ]‪ [۲۷‬ﺍﺭﺍﺋﻪ ﺷﺪﻩ ﺍﺳﺖ ﻭ ﺩﺭ ﺍﻳﻦ ﭘﺎﻳﺎﻥﻧﺎﻣﻪ ﺗﻨﻬﺎ ﺑﻪ ﺫﻛﺮ ﻳﻚ ﺗﻌﺮﻳﻒ ﻛﻠﻲ ﺍﺯ ﺍﻳـﻦ ﭘﺮﺩﺍﺯﻧـﺪﻩ‬ ‫ﺍﻛﺘﻔﺎ ﻣﻲﺷﻮﺩ‪ .‬ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺍﻭﻟﻴﻦ ﭘﺮﺩﺍﺯﻧﺪﻩﻱ ﻛﻤﻚ ﺁﻣﻮﺯﺷﻲ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻳﻚ ﻣﺠﻤﻮﻋـﻪ ﺩﺳـﺘﻮﺭﺍﺕ‪ ٣٥‬ﺑﺴـﻴﺎﺭ‬ ‫ﺳﺎﺩﻩ ﺩﺍﺭﺩ ﻭ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺩﺭ ﻣﺮﻛﺰ ﻣﻴﻜﺮﻭ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﺩﺍﻧﺸﮕﺎﻩ ﻣﺎﺳﺎﭼﻮﺳﺖ ﺳﺎﺧﺘﻪ ﺷﺪﻩ ﺍﺳﺖ‪ ،‬ﻛﻪ ﺑـﻪ ﺩﻟﻴـﻞ‬ ‫ﺳﺎﺩﮔﻲ ﺳﺎﺧﺘﺎﺭ ﺣﺘﻲ ﺩﺭ ﺗﺮﺍﺷﻪ ﺳﺎﺧﺘﻪ ﺷﺪﻩ ﺍﺟﺰﺍﻱ ﭘﺮﺩﺍﺯﻧﺪﻩ ﻗﺎﺑﻞ ﺗﻔﻜﻴﻚ ﻣﻲﺑﺎﺷﺪ]‪.[۲۷‬‬ ‫‪ Parwan‬ﻳﻚ ﭘﺮﺩﺍﺯﻧﺪﻩ ﻱ ﻫﺸﺖ ﺑﻴﺘﻲ ﺑﺎ ﻓﻀﺎﻱ ﺁﺩﺭﺱ ‪ ۱۲‬ﺑﻴﺘﻲ ﻣﻲﺑﺎﺷﺪ‪ .‬ﻓﻀﺎﻱ ﺣﺎﻓﻈـﻪ ‪ 4096‬ﺑـﺎﻳﺘﻲ ﺑـﻪ‬ ‫‪ 16‬ﺻﻔﺤﻪ‪ ٣٦‬ﺗﻘﺴﻴﻢ ﺷﺪﻩ ﺍﺳﺖ ﻛﻪ ﻫﺮ ﻛﺪﺍﻡ ﺑﺎ ﻳـﻚ ﺑﺎﻳـﺖ ﻗﺎﺑـﻞ ﺁﺩﺭﺱ ﺩﻫـﻲ ﻣـﻲﺑﺎﺷـﻨﺪ‪ .‬ﺩﺭ ﺑـﺎﺱ ﺁﺩﺭﺱ‬ ‫ﭘﺮﺩﺍﺯﻧﺪﻩﻱ ‪ parwan‬ﭼﻬﺎﺭ ﺑﻴﺖ ﺳﻤﺖ ﭼﭗ ﺻـﻔﺤﻪ ﻭ ‪ ۸‬ﺑﻴـﺖ ﺑﻌـﺪﻱ ‪ offset‬ﺁﺩﺭﺱ ﺣﺎﻓﻈـﻪ ﺭﺍ ﻣﺸـﺨﺺ‬ ‫ﻣﻲﻛﻨﻨﺪ‪.‬‬ ‫ﺩﺳﺘﻮﺭﺍﺕ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺑﻪ ﮔﺮﻭﻫﻬﺎﻱ ﺣﺴﺎﺑﻲ ‪،‬ﻣﻨﻄﻘﻲ ﻭ ﭘﺮﺵ ﻗﺎﺑﻞ ﺗﻘﺴﻴﻢ ﻣـﻲﺑﺎﺷـﺪ ‪ .‬ﺍﻳـﻦ ﭘﺮﺩﺍﺯﻧـﺪﻩ ﺩﺍﺭﺍﻱ‬ ‫ﻳﻚ ﻭﺭﻭﺩﻱ ﻭﻗﻔﻪ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺭﺍ ‪ reset‬ﻣﻲﻛﻨﺪ‪ .‬ﺍﻳـﻦ ﭘﺮﺩﺍﺯﻧـﺪﻩ ﻗﺎﺑﻠﻴـﺖ ﺁﺩﺭﺱﺩﻫـﻲ ﺑـﻪ ﺩﻭ ﺭﻭﺵ‬ ‫ﻣﺴﺘﻘﻴﻢ‪ ٣٧‬ﻭ ﻏﻴﺮ ﻣﺴﺘﻘﻴﻢ‪ ٣٨‬ﺭﺍ ﺩﺍﺭﺍ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺁﻥ ﺗﻌﺪﺍﺩ ﺩﺳـﺘﻮﺭﺍﺕ ﺍﻳـﻦ ﭘﺮﺩﺍﺯﻧـﺪﻩ ﺑـﻪ ‪ ۲۳‬ﺩﺳـﺘﻮﺭ‬ ‫ﻣﻲﺭﺳﺪ‪ .‬ﺭﺟﻴﺴﺘﺮ ﺍﺻﻠﻲ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺍﻧﺒﺎﺷﺘﮕﺮ ﺁﻥ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺩﺍﺭﺍﻱ ‪ ۴‬ﺭﺟﻴﺴﺘﺮ ﭘﺮﭼﻢ‪ ٣٩‬ﺑﻪ ﻧﺎﻣﻬـﺎﻱ‬ ‫‪ (zero) z ، (carry) c ، (overflow) v‬ﻭ ‪ (negetive) n‬ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺩﺳﺘﻮﺭﻫﺎﯼ ‪ sta‬ﻭ‪ lda‬ﺩﺭ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﻭﻇﻴﻔﻪ ﺑﺎﺭﮔﺬﺍﺭﻱ ﻭ ﺫﺧﻴﺮﻩ ﺍﻧﺒﺎﺷﺘﮕﺮ ﺭﺍ ﺩﺭ ﻳـﻚ ﺧﺎﻧـﻪﻱ ﺣﺎﻓﻈـﻪ ﺑـﺮ‬ ‫ﻋﻬﺪﻩ ﺩﺍﺭﻧﺪ‪ .‬ﺩﺳﺘﻮﺭﺍﺕ ﺣﺴﺎﺑﻲ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺷﺎﻣﻞ ﺩﺳﺘﻮﺭﺍﺕ ‪ Sub ، Add‬ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﻳﻚ ﻣﻘﺪﺍﺭ ﺍﺯ ﻛـﻞ‬ ‫ﻓﻀﺎﻱ ﺣﺎﻓﻈﻪ ﺭﺍ ﺑﻪ ﻋﻨﻮﺍﻥ ﻋﻤﻠﻮﻧﺪ ﺩﻭﻡ ﺧﻮﺩ ﻣﻌﺮﻓﻲ ﻣﻲﻛﻨﻨﺪ‪ .‬ﻋﻤﻠﮕﺮ ﻣﻨﻄﻘﻲ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ‪ AND‬ﻣـﻲﺑﺎﺷـﺪ‬ ‫ﻛﻪ ﻛﺎﺭﻛﺮﺩﻱ ﻣﺎﻧﻨﺪ ﺩﺳﺘﻮﺭﺍﺕ ﺣﺴﺎﺑﻲ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺩﺍﺭﺩ‪ .‬ﺩﺳﺘﻮﺭ ﺩﻳﮕﺮ ﭘﺮﺩﺍﺯﻧﺪﻩ ‪ jsr‬ﻣـﻲﺑﺎﺷـﺪ ﻛـﻪ ﻭﻇﻴﻔـﻪﻱ ﺁﻥ‬ ‫‪instruction set 35‬‬ ‫‪page 36‬‬ ‫‪direct 37‬‬ ‫‪indirect 38‬‬ ‫‪flag 39‬‬ ‫‪۸۹‬‬ ‫ﺻﺪﺍ ﻛﺮﺩﻥ ﻳﻚ ﺯﻳﺮ ﺭﻭﻳﻪ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻳﻦ ﺩﺳﺘﻮﺭ ﺍﺑﺘـﺪﺍ ﻣﻘـﺪﺍﺭ ﻓﻌﻠـﻲ ‪ pc‬ﺭﺍ ﺩﺭ ﺣﺎﻓﻈـﻪﻱ ﻣﺸـﺨﺺ ﺷـﺪﻩ ﺩﺭ‬ ‫ﺩﺳﺘﻮﺭ ‪ (tos) jsr‬ﻣﻲﺭﻳﺰﺩ ﻭ ‪ pc‬ﺭﺍ ﺑﻪ ﺣﺎﻓﻈﻪ ﺑﻌﺪﻱ ﻳﻌﻨﻲ ‪ tos+l‬ﻣﻲﺑﺮﺩ‪.‬‬ ‫ﺩﺳﺘﻮﺭﺍﺕ ﭘﺮﺷﻲ ﺩﺭ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺑﻪ ﺩﻭ ﻗﺴﻤﺖ ﺷﺮﻃﻲ ﻭ ﻏﻴﺮﺷﺮﻃﻲ ﺗﻘﺴﻴﻢ ﻣﻲﺷﻮﻧﺪ‪ ،‬ﺩﺭ ﻗﺴﻤﺖ ﻏﻴﺮﺷﺮﻃﻲ‬ ‫ﺩﺳﺘﻮﺭ ‪ JMP‬ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﻛﻪ ﺁﺩﺭﺱ ﻋﻤﻞ ﭘﺮﺵ ﺭﺍ ﺑﻪ ﺻﻮﺭﺕ ﻣﺴﺘﻘﻴﻢ ﻳـﺎ ﻏﻴـﺮ ﻣﺴـﺘﻘﻴﻢ ﺩﺭﻳﺎﻓـﺖ ﻣـﻲﻛﻨـﺪ‪.‬‬ ‫ﺩﺳﺘﻮﺭﺍﺕ ﭘﺮﺷﻬﺎﻱ ﺷﺮﻃﻲ ﺷﺎﻣﻞ ‪ BRA-n , BRA-z , BRA-c‬ﻭ ‪ BRA-v‬ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﻛﻪ ﺩﺭ ﺻـﻮﺭﺕ ﻳـﻚ‬ ‫ﺑﻮﺩﻥ ﺭﺟﻴﺴﺘﺮ ﭘﺮﭼﻢ ﻣﻮﺭﺩ ﻧﻈﺮ ﻋﻤﻞ ﭘﺮﺵ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺳﺘﻮﺭﺍﺕ ﺑﻌﺪﻱ ﺳﻴﺴﺘﻢ ﺷﺎﻣﻞ ﺩﺳـﺘﻮﺭﺍﺕ ﺑـﺪﻭﻥ‬ ‫ﺁﺩﺭﺱﺩﻫﻲ ﻣﻲﺑﺎﺷﺪ‪ :‬ﺍﺯ ﺟﻤﻠﻪ ‪ CLA‬ﻛﻪ ﺍﻧﺒﺎﺷﺘﮕﺮ ﺭﺍ ﺻﻔﺮ ﻣﻲﻛﻨﺪ‪ CMA .‬ﻛﻪ ﺍﻧﺒﺎﺷﺘﮕﺮ ﺭﺍ ﻧﻘـﻴﺾ ﻣـﻲﻛﻨـﺪ‪.‬‬ ‫‪ CMC‬ﻛﻪ ﺭﺟﻴﺴﺘﺮ ﭘﺮﭼﻢ ‪ c‬ﺭﺍ ﻧﻘﻴﺾ ﻣﻲﻛﻨﺪ‪ NOP .‬ﻛﻪ ﻫﻴﭻ ﻋﻤﻠﻲ ﺍﻧﺠﺎﻡ ﻧﻤﻲﺷﻮﺩ ﻭ ﺩﺳﺘﻮﺭﺍﺕ ﺷﻴﻔﺖ ﺑﻪ‬ ‫ﭼﭗ ﻭ ﺭﺍﺳﺖ ‪ .SHR , SHL‬ﺟﺪﻭﻝ ‪ ۱-۵‬ﺧﻼﺻﻪ ﺩﺳﺘﻮﺭﺍﺕ ﻭ ﻧﺤﻮﻱ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺁﻥ ﺭﺍ ﻧﺸﺎﻥ ﻣﻲﺩﻫﺪ‪.‬‬ ‫ﺑﻴﺘﻬﺎﯼ ‪ ۰‬ﺗﺎ ‪Opcode ۳‬‬ ‫ﺑﻴﺖ ﻧﺤﻮﻩﻱ ﺁﺩﺭﺱﺩﻫﯽ‬ ‫ﺑﻴﺘﻬﺎﯼ ‪Opcode‬‬ ‫ﻓﻀﺎﯼ ﺁﺩﺭﺱﺩﻫﯽ‬ ‫ﺗﻌﺪﺍﺩ ﺑﻴﺖ ﺁﺩﺭﺱ‬ ‫ﺁﺩﺭﺱ ﺻﻔﺤﻪ‬ ‫‪۱/۰‬‬ ‫‪۰۰۰‬‬ ‫ﮐﻞ ﺣﺎﻓﻈﻪ‬ ‫‪۱۲‬‬ ‫‪LDA loc‬‬ ‫ﺁﺩﺭﺱ ﺻﻔﺤﻪ‬ ‫‪۱/۰‬‬ ‫‪۰۰۱‬‬ ‫ﮐﻞ ﺣﺎﻓﻈﻪ‬ ‫‪۱۲‬‬ ‫‪AND loc‬‬ ‫ﺁﺩﺭﺱ ﺻﻔﺤﻪ‬ ‫‪۱/۰‬‬ ‫‪۰۱۰‬‬ ‫ﮐﻞ ﺣﺎﻓﻈﻪ‬ ‫‪۱۲‬‬ ‫‪ADD loc‬‬ ‫ﺁﺩﺭﺱ ﺻﻔﺤﻪ‬ ‫‪۱/۰‬‬ ‫‪۰۱۱‬‬ ‫ﮐﻞ ﺣﺎﻓﻈﻪ‬ ‫‪۱۲‬‬ ‫‪SUB loc‬‬ ‫ﺁﺩﺭﺱ ﺻﻔﺤﻪ‬ ‫‪۱/۰‬‬ ‫‪۱۰۰‬‬ ‫ﮐﻞ ﺣﺎﻓﻈﻪ‬ ‫‪۱۲‬‬ ‫‪JMP loc‬‬ ‫ﺁﺩﺭﺱ ﺻﻔﺤﻪ‬ ‫‪۱/۰‬‬ ‫‪۱۰۱‬‬ ‫ﮐﻞ ﺣﺎﻓﻈﻪ‬ ‫‪۱۲‬‬ ‫‪STA loc‬‬ ‫‪---‬‬ ‫‪-‬‬ ‫‪۱۱۰‬‬ ‫ﺻﻔﺤﻪ ﻓﻌﻠﯽ‬ ‫‪۸‬‬ ‫‪JSR loc‬‬ ‫‪۱۰۰۰‬‬ ‫‪۱‬‬ ‫‪۱۱۱‬‬ ‫ﺻﻔﺤﻪ ﻓﻌﻠﯽ‬ ‫‪۸‬‬ ‫‪BRA_V addr‬‬ ‫‪۰۱۰۰‬‬ ‫‪۱‬‬ ‫‪۱۱۱‬‬ ‫ﺻﻔﺤﻪ ﻓﻌﻠﯽ‬ ‫‪۸‬‬ ‫‪BRA_C addr‬‬ ‫‪۰۰۱۰‬‬ ‫‪۱‬‬ ‫‪۱۱۱‬‬ ‫ﺻﻔﺤﻪ ﻓﻌﻠﯽ‬ ‫‪۸‬‬ ‫‪BRA_Z addr‬‬ ‫‪۰۰۰۱‬‬ ‫‪۱‬‬ ‫‪۱۱۱‬‬ ‫ﺻﻔﺤﻪ ﻓﻌﻠﯽ‬ ‫‪۸‬‬ ‫‪BRA_N addr‬‬ ‫‪۰۰۰۰‬‬ ‫‪۰‬‬ ‫‪۱۱۱‬‬ ‫‪-‬‬ ‫‪-‬‬ ‫‪NOP‬‬ ‫‪۰۰۰۱‬‬ ‫‪۰‬‬ ‫‪۱۱۱‬‬ ‫‪-‬‬ ‫‪-‬‬ ‫‪CLA‬‬ ‫‪۰۰۱۰‬‬ ‫‪۰‬‬ ‫‪۱۱۱‬‬ ‫‪-‬‬ ‫‪-‬‬ ‫‪CMA‬‬ ‫‪۰۱۰۰‬‬ ‫‪۰‬‬ ‫‪۱۱۱‬‬ ‫‪-‬‬ ‫‪-‬‬ ‫‪CMC‬‬ ‫‪۱۰۰۰‬‬ ‫‪۰‬‬ ‫‪۱۱۱‬‬ ‫‪-‬‬ ‫‪-‬‬ ‫‪ASL‬‬ ‫‪۱۰۰۱‬‬ ‫‪۰‬‬ ‫‪۱۱۱‬‬ ‫‪-‬‬ ‫‪-‬‬ ‫‪ASR‬‬ ‫ﺟﺪﻭﻝ ‪ ۱-۵‬ﻣﺠﻤﻮﻋﻪ ﺩﺳﺘﻮﺭﺍﺕ ﭘﺮﺩﺍﺯﻧﺪﻩ ‪[۲۷] parwan‬‬ ‫ﺳﺎﺧﺘﺎﺭ ﺩﺳﺘﻮﺭﺍﺗﻲ ﻛﻪ ﺑﺎ ﻣﻘﺎﺩﻳﺮ ﻣﻮﺟﻮﺩ ﺩﺭ ﺣﺎﻓﻈﻪ ﻛﺎﺭ ﻣﻲﻛﻨﺪ ﺩﻭ ﺑﺎﻳﺘﯽ ﻣﻲﺑﺎﺷـﺪ ﮐـﻪ ﺑﺎﻳـﺖ ﺩﻭﻡ ﺁﻥ ‪offset‬‬ ‫ﻣﺤﻞ ﺣﺎﻓﻈﻪ ﺭﺍ ﻣﺸﺨﺺ ﻣﻲﮐﻨﺪ‪ .‬ﺩﺳﺘﻮﺭﺍﺗﻲ ﻛﻪ ﺍﺣﺘﻴﺎﺟﻲ ﺑﻪ ﺩﺳﺘﺮﺳﻲ ﺑﻪ ﻣﻘﺎﺩﻳﺮ ﻣﻮﺟﻮﺩ ﺩﺭ ﺣﺎﻓﻈـﻪ ﻧﺪﺍﺭﻧـﺪ‪،‬‬ ‫‪۹۰‬‬ ‫ﺗﻚ ﺑﺎﻳﺘﻲ ﻣﻲﺑﺎﺷﻨﺪ‪ Opcode .‬ﺩﺳﺘﻮﺭﺍﺕ ﻣﻮﺟﻮﺩ ﺩﺭ ‪ parwan‬ﺑﻪ ﺻﻮﺭﺕ ﻛﻠﻲ ‪ ۴‬ﺑﻴﺘﻲ ﻣﻲﺑﺎﺷﺪ ﻛﻪ ﺍﮔﺮ ﺍﻳـﻦ‬ ‫ﭼﻬﺎﺭ ﺑﻴﺖ ﻣﻘﺪﺍﺭ ‪ 1110‬ﺭﺍ ﺑﺪﺳﺖ ﺑﻴﺎﻭﺭﻧﺪ ﻧﺸﺎﻧﻪﻱ ﺩﺳﺘﻮﺭﺍﺕ ﺗﻚ ﺑﺎﻳﺘﻲ ﻣﻲﺑﺎﺷـﻨﺪ‪ ،‬ﻛـﻪ ﺑـﺎ ﻛﻤـﻚ ‪ ۴‬ﺑﻴـﺖ‬ ‫ﺑﻌﺪﻱ ﺍﻳﻦ ﺩﺳﺘﻮﺭ ﻣﺸﺨﺺ ﻣﻲﺷﻮﺩ‪ .‬ﺩﺭ ﺻﻮﺭﺗﻲ ﻛﻪ ﻣﻘـﺪﺍﺭ ‪ 1111 Opcode‬ﺑﺎﺷـﺪ ﺩﺳـﺘﻮﺭ ﭘـﺮﺵ ﺷـﺮﻃﻲ‬ ‫ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﺯ ﺁﻧﺠﺎ ﮐﻪ ﺩﺭ ﺍﻳﻦ ﺩﺳﺘﻮﺭﺍﺕ ﭘﺮﺵ ﻓﻘﻂ ﺩﺭ ﺩﺍﺧﻞ ﺻﻔﺤﻪ ﻓﻌﻠﻲ ﺍﻣﻜﺎﻥ ﭘﺬﻳﺮ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺑﺎﻳـﺖ ﺑﻌـﺪﻱ‬ ‫‪ offset‬ﺁﺩﺭﺱ ﺣﺎﻓﻈﻪ ﺭﺍ ﺩﺭ ﺍﺧﺘﻴﺎﺭ ﭘﺮﺩﺍﺯﻧﺪﻩ ﻗﺮﺍﺭ ﻣﻲﺩﻫﺪ‪ .‬ﺑﻘﻴﻪ ﺩﺳﺘﻮﺭﺍﺕ ﺩﺍﺭﺍﻱ ﻓﻀﺎﻱ ﺁﺩﺭﺱ ﺗﻤﺎﻡ ﺣﺎﻓﻈـﻪ‬ ‫ﻣﻲﺑﺎﺷﻨﺪ‪ ،‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺩﺭ ﺑﺎﻳﺖ ﺍﻭﻝ ﺩﺳﺘﻮﺭ ﭘﺲ ﺍﺯ ‪ ۴‬ﺑﻴﺖ ‪ opcode‬ﺁﺩﺭﺱ ﺻﻔﺤﻪ ﺣﺎﻓﻈﻪ ﻗﺮﺍﺭﺩﺍﺭﺩ ‪ ،‬ﺗﻮﺻﻴﻒ‬ ‫ﺭﻓﺘﺎﺭﻱ ﭘﺮﺩﺍﺯﻧﺪﻩ ‪ parwan‬ﻛﻪ ﺑﻪ ﻭﺳﻴﻠﻪﻱ ﺯﺑﺎﻥ ﺗﻮﺻﻴﻒ ﺳﺨﺖﺍﻓﺰﺍﺭ ‪ VHDL‬ﺑﻴﺎﻥ ﺷﺪﻩﺍﺳـﺖ ﺩﺭ ﭘﻴﻮﺳـﺖ‬ ‫ﺍﻟﻒ ﻗﺮﺍﺭﺩﺍﺭﺩ‪ .‬ﺑﺮﺍﻱ ﺍﻋﻤﺎﻝ ﺍﻳﻦ ﺗﻮﺻﻴﻒ ﺑﻪ ﺷﺒﻴﻪﺳﺎﺯ ﺑﺎﻳﺪ ﺍﻟﮕﻮﻱ ﺁﻥ ﺭﺍ ﺑـﻪ ﺻـﻮﺭﺕ ﭘﻴﻮﺳـﺖ ﺏ ﺩﺭﺁﻭﺭﺩ ﺗـﺎ‬ ‫ﺑﺘﻮﺍﻥ ﺍﺯ ﺁﻥ ﺑﻪ ﻋﻨﻮﺍﻥ ﻭﺭﻭﺩﻱ ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯ ﺍﺳﺘﻔﺎﺩﻩ ﻛﺮﺩ‪ .‬ﻫﻤﺎﻧﮕﻮﻧـﻪ ﮐـﻪ ﻣﺸـﺎﻫﺪﻩﻣـﻲﺷـﻮﺩ‪ ،‬ﺑﻠـﻮﮎ ‪always‬‬ ‫ﺣﺎﺻﻞ ﺭﺟﻴﺴﺘﺮﻫﺎﯼ ﻣﻮﺟﻮﺩ ﺩﺭ ﺗﻮﺻـﻴﻒ ﺭﻓﺘـﺎﺭﯼ ﺯﺑـﺎﻥ ‪ VHDL‬ﺭﺍ ﺑـﻪ ﺻـﻮﺭﺕ ﻭﺭﻭﺩﻳﻬـﺎ ﻭ ﺧﺮﻭﺟﻴﻬـﺎﯼ‬ ‫ﻣﺴﺘﻘﻞ ﺩﺭ ﻧﻈﺮ ﮔﺮﻓﺘﻪﺍﺳﺖ ﮐﻪ ﺩﺭ ﻓﺎﻳﻞ ‪ cir‬ﺍﻳﻦ ﺩﻭ ﺑﻪ ﻳﮏ ﮔﺮﻩ ﺩﺭ ﻟﻴﺴﺖ ‪ cunwire‬ﺍﺷـﺎﺭﻩ ﻣـﻲﮐﻨﻨـﺪ‪ .‬ﺑـﺮﺍﯼ‬ ‫ﻣﺜﺎﻝ ‪ curac‬ﺩﺭ ﻭﺭﻭﺩﻳﻬﺎ ﻧﺸﺎﻥﺩﻫﻨﺪﻩﻱ ﺭﺟﻴﺴﺘﺮ ﺍﻧﺒﺎﺷﺘﮕﺮ ﺩﺭ ﺣﺎﻟـﺖ ﻓﻌﻠـﯽ ﻭ ‪ nextac‬ﺩﺭ ﺧﺮﻭﺟﻴﻬـﺎ ﻧﺸـﺎﻥ‪-‬‬ ‫ﺩﻫﻨﺪﻩﻱ ﻣﻘﺪﺍﺭ ﺑﻌﺪﯼ ﺭﺟﻴﺴﺘﺮ ﺍﻧﺒﺎﺷﺘﮕﺮ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﺯ ﺁﻧﺠـﺎ ﮐـﻪ ﺷـﺒﻴﻪﺳـﺎﺯﯼ ﺑـﺮﺍﯼ ﺗﻮﺻـﻴﻒ ﺭﻓﺘـﺎﺭﯼ ﺯﺑـﺎﻥ‬ ‫‪ VHDL‬ﺑﻪ ﺻﻮﺭﺕ ﻣﺒﺘﻨﻲ ﺑﺮ ﺭﻭﻳﺪﺍﺩ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺍﺯ ﺩﺳﺘﻮﺭﺍﺗﯽ ﻣﺜﻞ ‪ wait‬ﺩﺭ ﺍﻳﻦ ﺗﻮﺻﻴﻒ ﺍﺳﺘﻔﺎﺩﻩﺷﺪﻩﺍﺳﺖ‪ ،‬ﮐﻪ‬ ‫ﺩﺭ ﻣﻮﺍﺭﺩﯼ ﮐﻪ ﺩﺳﺘﺮﺳﯽ ﺑﻪ ﺣﺎﻓﻈﻪ ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﮐﺎﺭﺍﻳﻲ ﺩﺍﺭﺩ‪ .‬ﺍﻳﻦ ﻗﺎﺑﻠﻴﺖ ﺩﺭ ﺷﺒﻴﻪﺳﺎﺯ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺷﺪﻩ ﻭﺟﻮﺩ‬ ‫ﻧﺪﺍﺭﺩ ﺯﻳﺮﺍ ﺍﻳﻦ ﺷﺒﻴﻪ ﺳﺎﺯ ﻣﺒﺘﻨﯽ ﺑﺮ ﭼﺮﺧﻪ ﻣﻲﺑﺎﺷﺪ ﻭ ﺩﺭ ﻧﺘﻴﺠﻪ ﺩﺭ ﻣﻮﺍﺭﺩﯼ ﮐﻪ ﮐﺎﺭ ﺑﺎ ﺣﺎﻓﻈﻪ ﻣﻮﺭﺩﻧﻴﺎﺯ ﺑﺎﺷـﺪ‪،‬‬ ‫ﺍﻳﻦ ﻋﻤﻞ ﺍﻧﺠﺎﻡﺷﺪﻩ ﻓﺮﺽ ﻣﻲﺷﻮﺩ‪ .‬ﺑﺮﺍﯼ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﻣﻮﺍﺭﺩﯼ ﮐﻪ ﺍﺣﺘﻴﺎﺝ ﺑﻪ ﺗﻘﺴﻴﻢ ﻳﮏ ﻣﺘﻐﻴﺮ ﺑﻪ ﭼﻨﺪ ﻣﺘﻐﻴـﺮ‬ ‫ﺩﻳﮕﺮ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﺍﻳﻦ ﻣﺘﻐﻴﺮ ﺑﻪ ﺻﻮﺭﺕ ﭼﻨﺪ ﻣﺘﻐﻴﺮ ﺑﻪ ﺑﻠـﻮﮎ ﺍﺭﺳـﺎﻝ ﻣـﻲﺷـﻮﺩ‪ .‬ﺑـﺮﺍﯼ ﻣﺜـﺎﻝ ﻣﺘﻐﻴـﺮ ‪ Byte1‬ﺩﺭ‬ ‫ﺗﻮﺻﻴﻒ ﺭﻓﺘﺎﺭﯼ ﺯﺑﺎﻥ ‪ VHDL‬ﮐﻪ ﻧﻤﺎﻳﻨﺪﻩﻱ ﮐﻞ ﺑﺎﻳﺖ ﺷﺎﻣﻞ ‪ Opcode‬ﻭ ﺁﺩﺭﺱ ﺻﻔﺤﻪ ﻭ ﻧﺤـﻮﻩﻱ ﺁﺩﺭﺱ‪-‬‬ ‫ﺩﻫﯽ ﻣﻲﺑﺎﺷﺪ ﺩﺭ ﺑﻠﻮﮎ ‪ always‬ﺑـﻪ ﺻـﻮﺭﺕ ‪ ۳‬ﻣﺘﻐﻴـﺮ ‪ opc‬ﻧﻤﺎﻳﻨـﺪﻩﻱ ‪ DIbit ،Opcode‬ﻧﻤﺎﻳﻨـﺪﻩ ﻧﺤـﻮﻩﻱ‬ ‫‪۹۱‬‬ ‫ﺁﺩﺭﺱﺩﻫﯽ ﻭ ‪ lowbit‬ﻧﻤﺎﻳﻨﺪﻩﻱ ﻗﺴﻤﺖﭘﺎﻳﺎﻧﯽ ‪ Byte1‬ﻧﻤﺎﻳﺶﺩﺍﺩﻩﺷﺪﻩﺍﺳﺖ‪.‬‬ ‫ﻓﺎﻳﻞ ‪ nof‬ﺍﻳﻦ ﺗﻮﺻﻴﻒ ﺩﺭ ﭘﻴﻮﺳﺖ ﭖ ﺍﺭﺍﻳﻪ ﺷﺪﻩﺍﺳﺖ‪ ،‬ﺩﺭ ﺍﻳﻦ ﻓﺎﻳﻞ ﺍﺯ ‪ ۵۶‬ﮔﺮﻩ ﻣﻴﺎﻧﯽ ﺟﺪﻳـﺪ ﺍﺳـﺘﻔﺎﺩﻩﺷـﺪﻩ‪-‬‬ ‫ﺍﺳﺖ‪ .‬ﻧﺘﻴﺠﻪﻱ ﺷﺒﻴﻪﺳﺎﺯﯼ ﭘﺲ ﺍﺯ ﻣﺮﺣﻠﻪﻱ ‪ precompile‬ﻳﮏ ﻓﺎﻳﻞ ﺑـﻪ ﻃـﻮﻝ ‪۱۶۱۳‬ﺧـﻂ ﻣـﻲﺑﺎﺷـﺪ‪ ،‬ﮐـﻪ ﺍﺯ‬ ‫‪ ۱۵۵۳‬ﻣﺘﻐﻴﺮ ﻣﻴﺎﻧﯽ ﺩﺭ ﺁﻥ ﺍﺳﺘﻔﺎﺩﻩﺷﺪﻩﺍﺳﺖ‪ .‬ﺍﻳﻦ ﻣﻘﺪﺍﺭ ﻣﻲﺗﻮﺍﻧﺪ ﺗﻘﺮﻳﺐ ﺧﻮﺑﯽ ﺑﺮﺍﯼ ﺗﻌـﺪﺍﺩ ﮔـﺮﻩﻫـﺎﯼ ‪TED‬‬ ‫ﺣﺎﺻﻞ ﺑﺎﺷﺪ‪ .‬ﺍﺯ ﺁﻧﺠﺎ ﮐﻪ ﺩﺭ ﻓﺼﻞ ﻗﺒﻞ ﮔﻔﺘﻪﺷﺪ‪ .‬ﺩﺭ ﺍﻳﻦ ﭘﻴﺎﺩﻩﺳـﺎﺯﯼ ﺑـﺮﺍﯼ ﺑﺮﺭﺳـﯽ ﭘﻴﺸـﺮﻓﺖ ﺷـﺒﻴﻪﺳـﺎﺯ ﺍﺯ‬ ‫ﻣﺘﻐﻴﺮﻫﺎﯼ ﺭﺷﺘﻪ ﺑﺮﺍﯼ ﻧﻤﺎﻳﺶ ﻋﺒﺎﺭﺕ ﻣﻌﺎﺩﻝ ﻫﺮ ﮔﺮﻩ ﺍﺳﺘﻔﺎﺩﻩﺷﺪﻩﺍﺳﺖ‪ ،‬ﺩﺭ ﻧﺘﻴﺠﻪ ﺣﺠـﻢ ﺣﺎﻓﻈـﻪ ﻣـﻮﺭﺩ ﻧﻴـﺎﺯ‬ ‫ﺑﺮﺍﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﺍﻳﻦ ﭘﺮﺩﺍﺯﻧﺪﻩ ﺑﺴﻴﺎﺭ ﻗﺎﺑﻞ ﺗﻮﺟﻪ ﺧﻮﺍﻫﺪ ﺑﻮﺩ‪ .‬ﺳﻴﺴﺘﻤﯽ ﮐﻪ ﺍﻳﻦ ﺷﺒﻴﻪﺳﺎﺯ ﺭﻭﯼ ﺁﻥ ﺍﺟﺮﺍ ﺷـﺪﻩ‪-‬‬ ‫ﺍﺳﺖ‪ ،‬ﺑﻪ ﺩﻟﻴﻞ ﺩﺍﺷﺘﻦ ﺣﺎﻓﻈﻪﻱ ﻣﺸﺘﺮﮎ ﺑﺎ ﮐﺎﺭﺕ ﮔﺮﺍﻓﻴﮑﯽ ﺗﻮﺍﻧﺎﻳﻲ ﺍﺟـﺮﺍﯼ ﺍﻳـﻦ ﺷـﺒﻴﻪﺳـﺎﺯﯼ ﺭﺍ ﻧـﺪﺍﺭﺩ‪ .‬ﺩﺭ‬ ‫ﻧﺘﻴﺠﻪ ﻧﺮﻡﺍﻓﺰﺍﺭ ﺷﺒﻴﻪﺳﺎﺯ ﺑﻪ ﺻﻮﺭﺕ ‪ release‬ﺑﺮ ﺭﻭﯼ ﻳﮏ ﮐﺎﻣﭙﻴﻮﺗﺮﻗﺎﺑﻞ ﺣﻤـﻞ ﺑـﺎ ﭘﺮﺩﺍﺯﻧـﺪﻩﻱ ‪ِPentium M‬‬ ‫‪ 1.5 GHz‬ﺑﺎ ‪ 512MB‬ﺣﺎﻓﻈﻪ ﺍﺟﺮﺍ ﺷﺪ‪ .‬ﺯﻣﺎﻥ ﺳﺎﺧﺖ ‪TED‬ﻫﺎﯼ ﻣﻌﺎﺩﻝ ﺗﻮﺻﻴﻒ ﭘﺮﺩﺍﺯﻧﺪﻩ ‪ ۳۶‬ﺛﺎﻧﻴﻪ ﺑﺪﺳـﺖ‪-‬‬ ‫ﺁﻣﺪ ﻭ ﺣﺎﻓﻈﻪﻱ ﻣﺎﮐﺰﻳﻤﻢ ﻣﻮﺭﺩ ﻧﻴﺎﺯ ‪ 450MB‬ﻣﻲﺑﺎﺷﺪ‪ .‬ﺍﻟﺒﺘﻪ ﺩﺭ ﺻﻮﺭﺕ ﺣﺬﻑ ﻗﺴﻤﺖ ﻣﺤﺎﺳﺒﻪﻱ ﺭﺷﺘﻪﻫـﺎﯼ‬ ‫ﻣﻌﺎﺩﻝ ﻣﻲﺗﻮﺍﻥ ﺍﻳﻦ ﺣﺠﻢ ﺣﺎﻓﻈﻪ ﺭﺍ ﺗﺎ ‪ %۹۰‬ﻭ ﺯﻣﺎﻥ ﺁﻥ ﺭﺍ ﺗﺎ ‪ %۵۰‬ﮐﺎﻫﺶﺩﺍﺩ‪ .‬ﺯﻣﺎﻥ ﻫﺮ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ‬ ‫ﺑﻪ ﻃﻮﺭ ﻣﺘﻮﺳﻂ ‪ ۲‬ﺗﺎ ‪ ۵‬ﺛﺎﻧﻴﻪ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪۹۲‬‬ ‫‪ -۶‬ﻧﺘﻴﺠﻪﮔﻴﺮﯼ ﻭ ﭘﻴﺸﻨﻬﺎﺩﺍﺕ ﺁﻳﻨﺪﻩ‬ ‫ﻫﻤﺎﻧﮕﻮﻧﻪ ﮐﻪ ﺩﺭ ﻓﺼﻠﻬﺎﯼ ﺍﻭﻟﻴﻪ ﮔﻔﺘﻪﺷﺪ‪ ،‬ﺍﻣﺮﻭﺯﻩ ﺩﺭﺳﺘﯽﻳﺎﺑﻲ ﮔﻠﻮﮔﺎﻩ ﻣﺴﻴﺮ ﺳﺎﺧﺖ ﻭ ﭘﻴﺎﺩﻩﺳـﺎﺯﯼ ﻣـﺪﺍﺭﻫﺎﯼ‬ ‫ﻣﺠﺘﻤﻊ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﮐﻪ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻨﻄﻘﯽ ﺗﻨﻬﺎ ﺍﺑﺰﺍﺭ ﮐﺎﺭﺑﺮﺩﯼ ﺑﺮﺍﯼ ﻏﻠﺒﻪ ﺑﺮ ﺍﻳـﻦ ﻣﺴـﺎﻟﻪ ﺩﺭ ﺻـﻨﻌﺖ ﻣـﻲﺑﺎﺷـﺪ‪.‬‬ ‫ﻟﻴﮑﻦ ﺑﻪ ﺩﻟﻴﻞ ﮐﺎﺳﺘﻴﻬﺎﻳﻲ ﮐﻪ ﺍﺑﺰﺍﺭﻫﺎﯼ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻣﻨﻄﻘﯽ ﺍﻣﺮﻭﺯ ﺑﺎ ﺁﻥ ﺩﺳﺖ ﺑﻪ ﮔﺮﻳﺒـﺎﻥ ﻫﺴـﺘﻨﺪ ﻣﺎﻧﻨـﺪ ﻋـﺪﻡ‬ ‫ﭘﻮﺷﺶ ﺗﻤﺎﻡ ﻓﻀﺎﯼ ﺣﺎﻟﺖ ﺳﻴﺴﺘﻢ‪ ،‬ﻃﺮﺍﺣﯽ ﻭ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺩﺳﺘﯽ ﻭ ﻫﺰﻳﻨﻪﺑﺮ ﺑﺮﺩﺍﺭﻫﺎﯼ ﺗﺴﺖ ‪،‬ﺍﺟـﺮﺍﯼ ﺯﻣـﺎﻧﺒﺮ‬ ‫ﺷﺒﻴﻪﺳﺎﺯﯼ ﺭﻭﯼ ﺳﻴﺴﺘﻢ ﺷﺒﻴﻪﺳﺎﺯ ﻭ ﺗﺤﻠﻴﻞ ﺩﺳﺘﯽ ﺧﺮﻭﺟﯽ ﺑﺎﻋﺚ ﺷﺪﻩﺍﺳﺖ ﺗﺎ ﻳﮏ ﻣﻴﻞ ﺷﺪﻳﺪ ﺑﺮﺍﯼ ﻃﺮﺍﺣﯽ‬ ‫ﻭ ﺳﺎﺧﺖ ﺍﺑﺰﺍﺭﻫﺎﯼ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﺟﺪﻳﺪ ﻭ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻟﮕﻮﺭﻳﺘﻤﻬـﺎﯼ ﺟﺪﻳـﺪ ﺩﺭ ﺑـﻴﻦ ﻣﻬﻨﺪﺳـﻴﻦ ﻭ ﻃﺮﺍﺣـﺎﻥ‬ ‫ﺍﻳﺠﺎﺩ ﺷﻮﺩ‪ .‬ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺷﺮﺍﻳﻂ ﻣﻮﺟﻮﺩ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﮔﺎﻡ ﺑﻌﺪﯼ ﺩﺭ ﺻﻨﻌﺖ ﺩﺭﺳﺘﯽﻳﺎﺑﯽ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺍﺑﺰﺍﺭﻱ ﮐﻪ ﺩﺭ ﺍﻳﻦ ﭘﺮﻭﮊﻩ ﻃﺮﺍﺣﯽ ﻭ ﭘﻴﺎﺩﻩﺳﺎﺯﯼ ﺷﺪﻩﺍﺳﺖ‪ ،‬ﻭﻇﻴﻔﻪﻱ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ‬ ‫ﺛﺒﺎﺕ ﻳﮏ ﺳﻴﺴﺘﻢ ﺭﺍ ﺑﺮﻋﻬﺪﻩ ﺩﺍﺭﺩ‪ ،‬ﮐﻪ ﻳﮏ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺑﺎﻻ ﺑﻪ ﺻﻮﺭﺕ ﺍﻟﮕﻮﯼ ﺗﻮﺻﻴﻒﺷﺪﻩ ﺩﺭ ﻓﺼﻞ ﻗﺒـﻞ‬ ‫ﺩﺭﻳﺎﻓﺖ ﻣﻲﮐﻨﺪ‪ .‬ﺳﭙﺲ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺑﻬﻴﻨﻪﺳﺎﺯﯼﺷﺪﻩ ﻣﺪﻝ ﺟﺪﻳﺪ ‪ CTED‬ﺁﻥ ﺗﻮﺻﻴﻒ ﺭﺍ ﺑﻪ ﻣﺪﻝ ﻗﺎﺑﻞ ﺷـﺒﻴﻪ‪-‬‬ ‫ﺳﺎﺯﯼ ﺩﺭ ﮐﺎﻣﭙﻴﻮﺗﺮ ﺗﺒﺪﻳﻞ ﻣﻲﮐﻨﺪ‪ .‬ﺳﭙﺲ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻭﺭﻭﺩﻳﻬﺎﻱ ﺷﺒﻴﻪﺳـﺎﺯﯼ ﮐـﻪ ﺗﻮﺳـﻂ ﮐـﺎﺭﺑﺮ ﺩﺭ ﺍﺧﺘﻴـﺎﺭ‬ ‫ﺳﻴﺴﺘﻢ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ‪ ،‬ﻣﺪﻝ ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺷﻮﺩ‪.‬‬ ‫‪۹۳‬‬ ‫ﺍﻳﻦ ﺍﺑﺰﺍﺭ ﺑﻪ ﮐﺎﺭﺑﺮ ﻗﺎﺑﻠﻴﺖ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺗﻮﺻﻴﻒ ﺳﻄﺢ ﺑﺎﻻ ﻣﺎﻧﻨﺪ ﺳﻄﺢ ﺍﻧﺘﻘﺎﻝ ﺛﺒـﺎﺕ ﺭﺍ ﻣـﯽﺩﻫـﺪ‪ ،‬ﮐـﻪ ﺩﺭ ﺍﻳـﻦ‬ ‫ﺗﻮﺻﻴﻒ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻋﺒﺎﺭﺗﻬﺎﯼ ﺟﺒﺮﯼ‪ ،‬ﺑﻮﻟﯽ‪ ،‬ﺟﺒﺮﯼ‪-‬ﺑﻮﻟﯽ ﻭ ﺣﺘﯽ ﻋﺒﺎﺭﺍﺕ ﺷﺮﻃﯽ ﺩﺭ ﺳﻄﺢ ﮐﻠﻤﻪ ﺭﺍ ﻣﻲﺩﻫـﺪ‪،‬‬ ‫ﺍﻳﻦ ﺍﺑﺰﺍﺭ ﭘﺲ ﺍﺯ ﺑﺪﺳﺖﺁﻭﺭﺩﻥ ‪ CTED‬ﺗﻐﻴﻴﺮﻳﺎﻓﺘﻪﻱ ﻣﻌﺎﺩﻝ ﺍﻳﻦ ﻃﺮﺡ ﺑﺎ ﺍﺳـﺘﻔﺎﺩﻩ ﺍﺯ ﻭﺭﻭﺩﻳﻬـﺎﯼ ﻧﻤـﺎﺩﻳﻦ ﮐـﻪ‬ ‫ﺗﻮﺳﻂ ﮐﺎﺭﺑﺮ ﺩﺭ ﺍﺧﺘﻴﺎﺭ ﺷﺒﻴﻪﺳﺎﺯ ﻗﺮﺍﺭﻣﻲﮔﻴﺮﺩ‪ ،‬ﺷﺒﻴﻪﺳﺎﺯﯼ ﻧﻤﺎﺩﻳﻦ ﺑﺮ ﺭﻭﯼ ﻣﺪﻝ ﺍﻧﺠﺎﻡ ﻣﻲﺷﻮﺩ‪ .‬ﻣﺸـﮑﻞ ﺍﻳـﻦ‬ ‫ﻣﺪﻝ ﻫﻤﺎﻧﻨﺪ ﺩﻳﮕﺮ ﺭﻭﺷﻬﺎﯼ ﻣﺒﺘﻨﯽ ﺑﺮ ﺩﻳﺎﮔﺮﺍﻣﻬﺎﯼ ﺗﺼﻤﻴﻢ ﺍﻧﻔﺠـﺎﺭ ﺣﺎﻟﺘﻬـﺎ ﻭ ﺍﻧﺠـﺎﻡ ﻋﻤﻠﻴـﺎﺕ ﺯﻳـﺎﺩ ﺑـﺮ ﺭﻭﯼ‬ ‫ﻋﺒﺎﺭﺗﻬﺎﯼ ﻧﻤﺎﺩﻳﻦ ﻣﻲﺑﺎﺷﺪ ﮐﻪ ﻧﺘﻴﺠﻪﻱ ﺁﻥ ﻣﺼﺮﻑ ﺑﻴﺶ ﺍﺯ ﺍﻧﺪﺍﺯﻩﻱ ﺣﺎﻓﻈﻪﻱ ﺳﻴﺴﺘﻢ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫ﺑﺮﺍﻱ ﺗﻮﺳﻌﻪ ﻭ ﻛﺎﺭﺑﺮﺩﻱ ﻛﺮﺩﻥ ﺍﻳﻦ ﺷﺒﻴﻪ ﺳﺎﺯ ﺩﻭ ﭘﻴﺸﻨﻬﺎﺩ ﻛﻠﻲ ﻣﻄﺮﺡ ﻣﻲﮔﺮﺩﺩ‪.‬‬ ‫ ﺍﻭﻟﻴﻦ ﮔﺎﻡ ‪ userfrendly‬ﻛﺮﺩﻥ ﻣﺤﻴﻂ ﺷﺒﻴﻪ ﺳﺎﺯ ﻭ ﺍﺭﺗﻘﺎﺀ ﺍﻟﮕﻮﻱ ﻭﺭﻭﺩﻱ ﺷﺒﻴﻪ ﺳﺎﺯ ﺑﻪ ﮔﻮﻧـﻪﺍﻱ ﻣـﻲﺑﺎﺷـﺪ‬‫ﻛﻪ ﺷﺒﻴﻪﺳﺎﺯ ﺑﺘﻮﺍﻧﺪ ﺍﺯ ﺯﺑﺎﻧﻬﺎﻱ ﺍﺳـﺘﺎﻧﺪﺍﺭﺩ ﺗﻮﺻـﻴﻒ ﺳـﺨﺖﺍﻓـﺰﺍﺭ ﻣﺎﻧﻨـﺪ ‪ Verilog ، VHDL‬ﻭ ﻳـﺎ ﺣﺘـﻲ‬ ‫‪ SystemC‬ﺍﺳﺘﻔﺎﺩﻩ ﻛﻨﺪ‪ .‬ﺍﻳﻦ ﮔﺎﻡ ﻣﻲﺗﻮﺍﻧﺪ ﺩﺭ ﻗﺎﻟﺐ ﻳﻚ ﭘﺮﻭﮊﻩﻱ ﻛﺎﺭﺷﻨﺎﺳﻲ ﻣﻄﺮﺡ ﺷﻮﺩ‪ .‬ﺍﻟﺒﺘـﻪ ﺍﺯ ﺁﻧﺠـﺎ ﻛـﻪ‬ ‫ﺍﻳﻦ ﻋﻤﻞ ﻧﻴﺎﺯﻣﻨﺪ ﺁﺷﻨﺎﻳﻲ ﺩﻗﻴﻖ ﻃﺮﺍﺡ ﺑﺎ ﺍﻟﮕـﻮﻱ ﺯﺑﺎﻧﻬـﺎ‪ ،‬ﻛﺎﻣﭙﺎﻳﻠﺮﻫـﺎ ﻭ ﻧﻈﺮﻳـﻪ ﺯﺑﺎﻧﻬـﺎ ﻭ ﻣﺎﺷـﻴﻨﻬﺎ ﻣـﻲﺑﺎﺷـﺪ‪،‬‬ ‫ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﺁﻥ ﺗﻮﺳﻂ ﻳﻚ ﺩﺍﻧﺸﺠﻮﻱ ﻣﻬﻨﺪﺳﻲ ﻧﺮﻡﺍﻓﺰﺍﺭ ﭘﻴﺸﻨﻬﺎﺩ ﻣﻲﺷﻮﺩ‪.‬‬ ‫ ﮔﺎﻡ ﺑﻌﺪﻱ ﻳﺎ ﺍﺻﻠﻲ ﺗﺮﻳﻦ ﮔﺎﻡ ﻛﻪ ﺩﺭ ﻃﻮﻝ ﭘﺮﻭﮊﻩ ﻣﺤـﺪﻭﺩﻳﺘﻬﺎﻱ ﺯﻳـﺎﺩﻱ ﺩﺭ ﭘﻴـﺎﺩﻩﺳـﺎﺯﻱ ﺍﻳﺠـﺎﺩ ﻣـﻲﻛـﺮﺩ‬‫ﻣﺤﺪﻭﺩ ﺑﻮﺩﻥ ﺟﺒﺮ ‪ TED‬ﻫﺎ ﺑﻪ ﺩﻭ ﻋﻤﻠﮕﺮ ﺟﻤﻊ ﻭ ﺿﺮﺏ ﻣﻲﺑﺎﺷﺪ‪ .‬ﺩﺭ ﺍﻳـﻦ ﮔـﺎﻡ ﺍﺿـﺎﻓﻪ ﻛـﺮﺩﻥ ﺩﻭ ﻋﻤﻠﮕـﺮ‬ ‫ﺗﻘﺴﻴﻢ ﻭ ﻣﺤﺎﺳﺒﻪ ﺑﺎﻗﻴﻤﺎﻧﺪﻩ ﺑﻪ‪ TED‬ﺑﺎﻋﺚ ﻣﻲﺷﻮﺩ ﺗﺎ ﺑﻪ ‪ TED‬ﻗﺎﺑﻠﻴﺘﻬﺎﻱ ﺯﻳﺎﺩﻱ ﺍﺯ ﺟﻤﻠﻪ ﺑﺮﺩﺍﺷـﺘﻦ ﺑﺨـﺶ‬ ‫ﺧﺎﺻﻲ ﺍﺯ ﻳﻚ ﻣﻘﺪﺍﺭ‪ ،‬ﺷﻴﻔﺖ ﺑﻪ ﺭﺍﺳﺖ ﻭ ﻳﺎ ﺣﺘﻲ ﺩﺭ ﻧﻈﺮ ﮔﺮﻓﺘﻦ ﻃﻮﻝ ﻋﻤﻠﻮﻧﺪ ﻳـﻚ ﻋﻤﻠﮕـﺮ ﺩﺭ ﻣﺤﺎﺳـﺒﻪﻱ‬ ‫ﻧﺘﻴﺠﻪﻱ ﺁﻥ‪ ،‬ﺍﺿﺎﻓﻪ ﺷﻮﺩ‪.‬‬ ‫ﺩﺭ ﺍﻳﻦ ﺣﺎﻟﺖ ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﻧﺴﺒﺖ ﺩﺍﺩﻥ ﺑﻴﺘﻬﺎﻱ ﺳﻪ ﺗﺎ ﭘﻨﺞ ﻣﺘﻐﻴﺮ ﻫﺸﺖ ﺑﻴﺘـﻲ ‪ A‬ﺑـﻪ ﻣﺘﻐﻴـﺮ ﺳـﻪ ﺑﻴﺘـﻲ ‪ B‬ﺑـﻪ‬ ‫ﺻﻮﺭﺕ ﻋﺒﺎﺭﺕ ﺟﺒﺮﻱ ‪ B = ( A%2 5 ) / 2 2‬ﻗﺎﺑﻞ ﭘﻴﺎﺩﻩﺳﺎﺯﻱ ﻣﻲﺑﺎﺷﺪ‪ ،‬ﻛﻪ ﺩﺭ ﺁﻥ ‪ %‬ﻋﻤﻠﮕﺮ ﺑﺎﻗﻴﻤﺎﻧﺪﻩ ﻣﻲﺑﺎﺷﺪ‪.‬‬ ‫‪۹۴‬‬ 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J., Kalla P., Zeng Z., Rouzeyre B., “Taylor Expansion Diagram: A Compact Representation with Application to Symboic Verification”, Design Automation and Test in Europe, March 2002, PP. 285-289. [25] Kalla P., Ciesielski M., Boutillon E., Martin E., "High-Level Design Verification Using Taylor Expansion Diagram: First Results", IEEE International High Level Design Validation and Test Workshop (HLDVT), 2002, PP. 13-17. [26] Gharebaghi A. M., Hessabi S., Eshghi M. R., "High-Level Symbolic Simulation Using Integer Equations", Canadian Conference on Electrical and Computer Engineering (CCECE), Niagara Falls, May 2004. [27] Navabi Z., "VHDL Analysis and Modeling of Digital Systems", Second Edition, McGraw-Hill, 1998. ۹۶ ‫ﭘﻴﻮﺳﺘﻬﺎ‬ ‫ﭘﻴﻮﺳﺖ ﺍﻟﻒ‬ VHDL ‫ ﺑﻪ ﺯﺑﺎﻥ‬parwan ‫ﮐﺪ ﺳﻄﺢ ﺭﻓﺘﺎﺭﯼ ﭘﺮﺩﺍﺯﻧﺪﻩﻱ‬ LIBRARY cmos; USE cmos.basic_utilities.ALL; -LIBRARY par_library; USE par_library.par_utilites.ALL; USE par_library.par_parameters.ALL; -ENTITY par_central_processing_unit IS GENERIC(read_high_time, read_low_time, write_high_time, write_low_time : TIME := 2US; cycle_time: TIME := 4US); PORT(clk: IN qit;intrrupt: IN qit; read_mem, write_mem: OUT qit; Databus:INOUT wired_byte BUS := "ZZZZZZZZ"; adbus:OUT twelve); END par_centeral_processing_unit; --ARCHITECTURE behavioral OF par_central_processing_unit IS SIGNAL ac_out: byte; SIGNAL pc_out: twelve; BEGIN PROCESS VARIBALE pc: twelve; VARIBALE ac, byte1, byte2: byte; VARIBALE v, c, z, n: qit; VARIBALE temp: qit_vector(9 DOWNTO 0); BEGIN IF interrupt = '1' THEN pc := zero_12; WAIT FOR cycle_time; ELSE –no interrupt adbus <= pc; read_mem <= '1'; WAIT FOR read_high_time; byte1 := byte(databus); read_mem <= '0'; WAIT FOR read_low_time; pc := inc(pc); IF byte1(7 DOWNTO 4) = single_byte_instructions THEN CASE byte1(3 DOWNTO 0) IS WHEN cla=> ac := zero_8; WHEN cma=> ac := NOT ac; IF ac = zero_8 THEN z := 1;END IF; n := ac(7); WHEN cmc=> ۹۷ c := NOT c; WHEN asl=> c := ac(7); ac := ac(6 DOWNTO 0)&'0'; IF ac = zero_8 THEN z := 1;END IF; n := ac(7); IF c /= n THEN v := 1;END IF; WHEN asr=> ac := '0' & ac(7 DOWNTO 1); IF ac = zero_8 THEN z := 1;END IF; n := ac(7); WHEN OTHERS => NULL; END CASE; ELSE –-two-byte instructions adbus <= pc; read_mem <= '1'; WAIT FOR read_high_time; byte2 := byte(databus); read_mem <= '0'; WAIT FOR read_low_time; pc := inc(pc); IF byte1(7 DOWNTO 5) = jsr THEN databus <= wired_byte(pc(7 DOWNTO 0)); adbus(7 DOWNTO 0) <= byte2; write_mem <= '1'; WAIT FOR write_high_time; write_mem <= '0'; WAIT FOR write_low_time; Databus <= 'ZZZZZZZZ'; pc(7 DOWNTO 0) := inc(byte2); ELSEIF byte1(7 DOWNTO 4) = bra THEN IF (byte1(3) = '1' AND v ='1') OR (byte1(2) = '1' AND c ='1') OR (byte1(1) = '1' AND z ='1') OR (byte1(0) = '1' AND n ='1') THEN pc(7 DOWNTO 0) := byte2; END IF: ELSE IF byte1(4) = indirect THEN adbus(11 DOWNTO 8) <= byte1(3 DOWNTO 0); adbus(7 DOWNTO 0) <= byte2; read_mem <= '1'; WAIT FOR read_high_time; byte2 := byte(databus); read_mem <= '0'; WAIT FOR read_low_time; END IF; IF byte1(7 DOWNTO 5) = jmp THEN pc := byte1(3 DOWNTO 0) & byte2; ELSEIF byte1(7 DOWNTO 5) = sta THEN adbus <= byte1(3 DOWNTO 0) & byte2; databus <= wired_byte(ac); write_mem <= '1'; WAIT FOR write_high_time; write_mem <= '0'; WAIT FOR write_low_time; ۹۸ Databus <= "ZZZZZZZZ"; ELSE –read operand for lda, and, add, sub adbus(11 DOWNTO 8) <= byte1(3 DOWNTO 0); adbus(7 DOWNTO 0) <= byte2; read_mem <= '1'; WAIT FOR read_high_time; CASE byte1(7 DOWNTO 5) IS WHEN lda=> ac := byte(databus); WHEN and=> ac := ac AND byte(databus); WHEN add=> temp := add_cv(ac, byte(databus), c); ac := temp(7 DOWNTO 0); c := temp(8); v := temp(9); WHEN sub=> temp := sub_cv(ac, byte(databus), c); ac := temp(7 DOWNTO 0); c := temp(8); v := temp(9); WHEN OTHERS=> NULL; END CASE; IF ac = zero_8 THEN z:= '1'; END IF; N = ac(7); read_mem <= '0'; WAIT FOR read_low_time; END IF; END IF; END IF; END IF; END PROCESS; END behavioral; ۹۹ ‫ﭘﻴﻮﺳﺖ ﺏ‬ :‫ ﻣﻄﺎﺑﻖ ﺑﺎ ﺍﻟﮕﻮﯼ ﺷﺒﻴﻪﺳﺎﺯ‬parwan ‫ ﭘﺮﺩﺍﺯﻧﺪﻩﻱ‬always ‫ﮐﺪ ﺑﻠﻮﮎ‬ always input(interrupt[1], curpc[12], databuslow[4], databusdi[1], databusop[3], addbus[12], curac[8], curz[1], curc[1], curn[1], curv[1], curdatabus[8]); output(nextpc[12], nextac[8], nextz[1], nextc[1], nextn[1], nextv[1], nextdatabus[8]); wire(read_mem[1], write_mem[1], opc[3], DIbit[1], lowbits[4], byte2[8]); if (interrupt == 1) nextpc = 0; else addbus = curpc; read_mem = 1; opc = databusop; DIbit = databusdi; lowbits = databuslow; read_mem = 0; nextpc = curpc + 1; if ((opc == 7) & (DIbit == 0)) if(lowbits == 1) nextac = 0; endif; if(lowbits == 2) nextac = -curac - 1; if (nextac == 0) nextz = 1; else nextz = 0; endif; if (nextac < 0) nextn = 1; else nextn = 0; endif; endif; if(lowbits == 4) nextc = ~curc; endif; if(lowbits == 8) nextac = curac * 2; if (nextac > 128) nextc = 1; else nextc = 0; endif; if (nextac == 0) nextz = 1; else nextz = 0; endif; ۱۰۰ if (nextac < 0) nextn = 1; else nextn = 0; endif; endif; else addbus = curpc; read_mem = 1; byte2 = databusop * (2 ^ 4)+ databusdi * (2 ^ 3) + databuslow; read_mem = 0; nextpc = curpc + 1; if(lowbits == 6) nextdatabus = curpc; addbus = byte2; write_mem = 1; write_mem = 0; nextpc = byte2 + 1; else if((opc == 7) & (DIbit == 1)) if (((lowbits == 8) & (curv == 1)) | ((lowbits == 4) & (curc == 1)) | ((lowbits == 2) & (curz == 1)) | ((lowbits == 1) & (curn == 1))) nextpc = byte2; endif; else if(DIbit == 1) addbus = lowbits * (2 ^ 8) + byte2; read_mem = 1; byte2 = curdatabus; read_mem = 0; endif; if(opc == 4) nextpc = lowbits * (2 ^ 8) + byte2; else if(opc == 5) addbus = lowbits * (2 ^ 8) + byte2; nextdatabus = curac; write_mem = 1; write_mem = 0; else addbus = lowbits * (2 ^ 8) + byte2; read_mem = 1; read_mem = 0; if(opc == 0) nextac = curdatabus; endif; if(opc == 1) nextac = curac & curdatabus; endif; if(opc == 2) nextac = curac + curdatabus; endif; if(opc == 3) nextac = curac - curdatabus; ۱۰۱ endif; if (nextac > 128) nextc = 1; else nextc = 0; endif; if (nextac == 0) nextz = 1; else nextz = 0; endif; if (nextac < 0) nextn = 1; else nextn = 0; endif; endif; endif; endif; endif; endif; endif; ۱۰۲ ‫ﭘﻴﻮﺳﺖ ﭖ‬ :parwan ‫ ﭘﺮﺩﺍﺯﻧﺪﻩﻱ‬nof ‫ﮐﺪ ﻓﺎﻳﻞ‬ ALWAYS INPUT(INTERRUPT[1],CURPC[12],DATABUSLOW[4],DATABUSDI[1],DATABUSOP[ 3],ADDBUS[12],CURAC[8],CURZ[1],CURC[1],CURN[1],CURV[1],CURDATABUS[ 8]); OUTPUT(NEXTPC[12],NEXTAC[8],NEXTZ[1],NEXTC[1],NEXTN[1],NEXTV[1],NE XTDATABUS[8]); WIRE(READ_MEM[1],WRITE_MEM[1],OPC[3],DIBIT[1],LOWBITS[4],BYTE2[8]) ; WIRE100002#(INTERRUPT)-(1); WIRE100001=~(WIRE100002); NEXTPC=(1&WIRE100001&(0)); ADDBUS=(1&~(WIRE100001)&(CURPC)); READ_MEM=(1&~(WIRE100001)&(1)); OPC=(1&~(WIRE100001)&(DATABUSOP)); DIBIT=(1&~(WIRE100001)&(DATABUSDI)); LOWBITS=(1&~(WIRE100001)&(DATABUSLOW)); READ_MEM=(~(1&~(WIRE100001))&(READ_MEM)+(1&~(WIRE100001)&(0))); NEXTPC=(~(1&~(WIRE100001))&(NEXTPC)+(1&~(WIRE100001)&(CURPC+1))); WIRE100004#(OPC)-(7); WIRE100005#(DIBIT)-(0); WIRE100003=(~(WIRE100004)&~(WIRE100005)); WIRE100007#(LOWBITS)-(1); WIRE100006=~(WIRE100007); NEXTAC=(1&~(WIRE100001)&WIRE100003&WIRE100006&(0)); WIRE100009#(LOWBITS)-(2); WIRE100008=~(WIRE100009); NEXTAC=(~(1&~(WIRE100001)&WIRE100003&WIRE100008)&(NEXTAC)+(1&~(WIR E100001)&WIRE100003&WIRE100008&(-CURAC-1))); WIRE100011#(NEXTAC)-(0); WIRE100010=~(WIRE100011); NEXTZ=(1&~(WIRE100001)&WIRE100003&WIRE100008&WIRE100010&(1)); NEXTZ=(~(1&~(WIRE100001)&WIRE100003&WIRE100008&~(WIRE100010))&(NEX TZ)+(1&~(WIRE100001)&WIRE100003&WIRE100008&~(WIRE100010)&(0))); WIRE100013<(NEXTAC)-(0); WIRE100012=(WIRE100013); NEXTN=(1&~(WIRE100001)&WIRE100003&WIRE100008&WIRE100012&(1)); NEXTN=(~(1&~(WIRE100001)&WIRE100003&WIRE100008&~(WIRE100012))&(NEX TN)+(1&~(WIRE100001)&WIRE100003&WIRE100008&~(WIRE100012)&(0))); WIRE100015#(LOWBITS)-(4); WIRE100014=~(WIRE100015); NEXTC=(1&~(WIRE100001)&WIRE100003&WIRE100014&(~CURC)); WIRE100017#(LOWBITS)-(8); WIRE100016=~(WIRE100017); NEXTAC=(~(1&~(WIRE100001)&WIRE100003&WIRE100016)&(NEXTAC)+(1&~(WIR E100001)&WIRE100003&WIRE100016&(CURAC*2))); WIRE100019<(128)-(NEXTAC); WIRE100018=(WIRE100019); NEXTC=(~(1&~(WIRE100001)&WIRE100003&WIRE100016&WIRE100018)&(NEXTC) +(1&~(WIRE100001)&WIRE100003&WIRE100016&WIRE100018&(1))); NEXTC=(~(1&~(WIRE100001)&WIRE100003&WIRE100016&~(WIRE100018))&(NEX ۱۰۳ TC)+(1&~(WIRE100001)&WIRE100003&WIRE100016&~(WIRE100018)&(0))); WIRE100021#(NEXTAC)-(0); WIRE100020=~(WIRE100021); NEXTZ=(~(1&~(WIRE100001)&WIRE100003&WIRE100016&WIRE100020)&(NEXTZ) +(1&~(WIRE100001)&WIRE100003&WIRE100016&WIRE100020&(1))); NEXTZ=(~(1&~(WIRE100001)&WIRE100003&WIRE100016&~(WIRE100020))&(NEX TZ)+(1&~(WIRE100001)&WIRE100003&WIRE100016&~(WIRE100020)&(0))); WIRE100023<(NEXTAC)-(0); WIRE100022=(WIRE100023); NEXTN=(~(1&~(WIRE100001)&WIRE100003&WIRE100016&WIRE100022)&(NEXTN) +(1&~(WIRE100001)&WIRE100003&WIRE100016&WIRE100022&(1))); NEXTN=(~(1&~(WIRE100001)&WIRE100003&WIRE100016&~(WIRE100022))&(NEX TN)+(1&~(WIRE100001)&WIRE100003&WIRE100016&~(WIRE100022)&(0))); ADDBUS=(~(1&~(WIRE100001)&~(WIRE100003))&(ADDBUS)+(1&~(WIRE100001) &~(WIRE100003)&(CURPC))); READ_MEM=(~(1&~(WIRE100001)&~(WIRE100003))&(READ_MEM)+(1&~(WIRE100 001)&~(WIRE100003)&(1))); BYTE2=(1&~(WIRE100001)&~(WIRE100003)&(DATABUSOP*(2^4)+DATABUSDI*(2 ^3)+DATABUSLOW)); READ_MEM=(~(1&~(WIRE100001)&~(WIRE100003))&(READ_MEM)+(1&~(WIRE100 001)&~(WIRE100003)&(0))); NEXTPC=(~(1&~(WIRE100001)&~(WIRE100003))&(NEXTPC)+(1&~(WIRE100001) &~(WIRE100003)&(CURPC+1))); WIRE100025#(LOWBITS)-(6); WIRE100024=~(WIRE100025); NEXTDATABUS=(1&~(WIRE100001)&~(WIRE100003)&WIRE100024&(CURPC)); ADDBUS=(~(1&~(WIRE100001)&~(WIRE100003)&WIRE100024)&(ADDBUS)+(1&~( WIRE100001)&~(WIRE100003)&WIRE100024&(BYTE2))); WRITE_MEM=(1&~(WIRE100001)&~(WIRE100003)&WIRE100024&(1)); WRITE_MEM=(~(1&~(WIRE100001)&~(WIRE100003)&WIRE100024)&(WRITE_MEM) +(1&~(WIRE100001)&~(WIRE100003)&WIRE100024&(0))); NEXTPC=(~(1&~(WIRE100001)&~(WIRE100003)&WIRE100024)&(NEXTPC)+(1&~( WIRE100001)&~(WIRE100003)&WIRE100024&(BYTE2+1))); WIRE100027#(OPC)-(7); WIRE100028#(DIBIT)-(1); WIRE100026=(~(WIRE100027)&~(WIRE100028)); WIRE100030#(LOWBITS)-(8); WIRE100031#(CURV)-(1); WIRE100032#(LOWBITS)-(4); WIRE100033#(CURC)-(1); WIRE100034#(LOWBITS)-(2); WIRE100035#(CURZ)-(1); WIRE100036#(LOWBITS)-(1); WIRE100037#(CURN)-(1); WIRE100029=((~(WIRE100030)&~(WIRE100031))|(~(WIRE100032)&~(WIRE100 033))|(~(WIRE100034)&~(WIRE100035))|(~(WIRE100036)&~(WIRE100037))) ; NEXTPC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&WIRE100026&W IRE100029)&(NEXTPC)+(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&W IRE100026&WIRE100029&(BYTE2))); WIRE100039#(DIBIT)-(1); WIRE100038=~(WIRE100039); ADDBUS=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&WIRE100038)&(ADDBUS)+(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024 )&~(WIRE100026)&WIRE100038&(LOWBITS*(2^8)+BYTE2))); READ_MEM=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE1000 ۱۰۴ 26)&WIRE100038)&(READ_MEM)+(1&~(WIRE100001)&~(WIRE100003)&~(WIRE10 0024)&~(WIRE100026)&WIRE100038&(1))); BYTE2=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026) &WIRE100038)&(BYTE2)+(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)& ~(WIRE100026)&WIRE100038&(CURDATABUS))); READ_MEM=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE1000 26)&WIRE100038)&(READ_MEM)+(1&~(WIRE100001)&~(WIRE100003)&~(WIRE10 0024)&~(WIRE100026)&WIRE100038&(0))); WIRE100041#(OPC)-(4); WIRE100040=~(WIRE100041); NEXTPC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&WIRE100040)&(NEXTPC)+(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024 )&~(WIRE100026)&WIRE100040&(LOWBITS*(2^8)+BYTE2))); WIRE100043#(OPC)-(5); WIRE100042=~(WIRE100043); ADDBUS=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&~(WIRE100040)&WIRE100042)&(ADDBUS)+(1&~(WIRE100001)&~(WIRE100003 )&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&WIRE100042&(LOWBITS*(2 ^8)+BYTE2))); NEXTDATABUS=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE1 00026)&~(WIRE100040)&WIRE100042)&(NEXTDATABUS)+(1&~(WIRE100001)&~( WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&WIRE100042&( CURAC))); WRITE_MEM=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100 026)&~(WIRE100040)&WIRE100042)&(WRITE_MEM)+(1&~(WIRE100001)&~(WIRE 100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&WIRE100042&(1))) ; WRITE_MEM=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100 026)&~(WIRE100040)&WIRE100042)&(WRITE_MEM)+(1&~(WIRE100001)&~(WIRE 100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&WIRE100042&(0))) ; ADDBUS=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&~(WIRE100040)&~(WIRE100042))&(ADDBUS)+(1&~(WIRE100001)&~(WIRE100 003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE100042)&(LOWB ITS*(2^8)+BYTE2))); READ_MEM=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE1000 26)&~(WIRE100040)&~(WIRE100042))&(READ_MEM)+(1&~(WIRE100001)&~(WIR E100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE100042)&( 1))); READ_MEM=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE1000 26)&~(WIRE100040)&~(WIRE100042))&(READ_MEM)+(1&~(WIRE100001)&~(WIR E100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE100042)&( 0))); WIRE100045#(OPC)-(0); WIRE100044=~(WIRE100045); NEXTAC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&~(WIRE100040)&~(WIRE100042)&WIRE100044)&(NEXTAC)+(1&~(WIRE100001 )&~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE10 0042)&WIRE100044&(CURDATABUS))); WIRE100047#(OPC)-(1); WIRE100046=~(WIRE100047); NEXTAC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&~(WIRE100040)&~(WIRE100042)&WIRE100046)&(NEXTAC)+(1&~(WIRE100001 )&~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE10 0042)&WIRE100046&(CURAC&CURDATABUS))); WIRE100049#(OPC)-(2); ۱۰۵ WIRE100048=~(WIRE100049); NEXTAC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&~(WIRE100040)&~(WIRE100042)&WIRE100048)&(NEXTAC)+(1&~(WIRE100001 )&~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE10 0042)&WIRE100048&(CURAC+CURDATABUS))); WIRE100051#(OPC)-(3); WIRE100050=~(WIRE100051); NEXTAC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026 )&~(WIRE100040)&~(WIRE100042)&WIRE100050)&(NEXTAC)+(1&~(WIRE100001 )&~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE10 0042)&WIRE100050&(CURAC-CURDATABUS))); WIRE100053<(128)-(NEXTAC); WIRE100052=(WIRE100053); NEXTC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026) &~(WIRE100040)&~(WIRE100042)&WIRE100052)&(NEXTC)+(1&~(WIRE100001)& ~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE1000 42)&WIRE100052&(1))); NEXTC=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026) &~(WIRE100040)&~(WIRE100042)&~(WIRE100052))&(NEXTC)+(1&~(WIRE10000 1)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE1 00042)&~(WIRE100052)&(0))); WIRE100055#(NEXTAC)-(0); WIRE100054=~(WIRE100055); NEXTZ=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026) &~(WIRE100040)&~(WIRE100042)&WIRE100054)&(NEXTZ)+(1&~(WIRE100001)& ~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE1000 42)&WIRE100054&(1))); NEXTZ=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026) &~(WIRE100040)&~(WIRE100042)&~(WIRE100054))&(NEXTZ)+(1&~(WIRE10000 1)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE1 00042)&~(WIRE100054)&(0))); WIRE100057<(NEXTAC)-(0); WIRE100056=(WIRE100057); NEXTN=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026) &~(WIRE100040)&~(WIRE100042)&WIRE100056)&(NEXTN)+(1&~(WIRE100001)& ~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE1000 42)&WIRE100056&(1))); NEXTN=(~(1&~(WIRE100001)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026) &~(WIRE100040)&~(WIRE100042)&~(WIRE100056))&(NEXTN)+(1&~(WIRE10000 1)&~(WIRE100003)&~(WIRE100024)&~(WIRE100026)&~(WIRE100040)&~(WIRE1 00042)&~(WIRE100056)&(0))); ۱۰۶ Abstract: Symbolic simulation combines simulation and symbolic methods to find a new way for design verification. This method uses gate-level specification of design, and adds the X value to normal 0 and 1 Boolean constants. This makes the simuation more powerful, but the main disadvantage of this method is not using the high-level descriptions used in RTL or higher level of abstraction. This thesis presents a new method for RTL or higher-level symbolic simulation using bit arrays and integer data structures. Keywords: 1- Symbolic Simulation 2- RTL 3- Verification ۱۰۷ Sharif University of Technology Department of Computer Engineering M.S.C. Thesis RTL Symbolic Simulation Saeed Mirzaeian Supervisor: Dr. Shahin Hessabi Advisor: Dr. Hamid Sarbazi Azad Summer 2004 ۱

Symbolic Simulation at Register Transfer Level Thesis

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