ECL: Emitter-Coupled Logic Gate Design & Performance

Emitter-Coupled Logic (ECL) University of Connecticut 115 The ECL Advantage n n n n All of the BJT-based logic gates discussed so far use the transistors as saturated switches. In addition, operation of the RTL, DTL, and TTL gates involves relatively large voltage swings on the p-n junctions. ECL gates are inherently FASTER than the other BJT-based logic gates because the transistors stay forward active and the voltage swings are small. The fastest commercially-available logic gates are made with ECL at the present time: sub-nanosecond propagation delays make possible off-chip data rates approaching 1 GHz. University of Connecticut 116 Basic ECL Current Switch VCC n RC RC VINV VIN VNINV QR QI VE n VREF n RE -VEE University of Connecticut n The ECL current switch acts like a differential amplifier with a fixed reference voltage at the base of QR. If VIN > VREF, QI conducts and VINV goes low. QR cuts off, and VNINV goes high. If VIN < VREF, QR conducts and VNINV goes low. QI cuts off and VINV goes high. The current in RE, and hence the power dissipation, are nearly constant. 117 Basic ECL: Choice of VREF VCC n RC VIN VE ≈ RC VINV With a high input, VIN = VCC , VNINV QR QI n VREF QR can be held off as long as VBE 2 ≤ VE RE n VREF can thus be chosen as -VEE VREF = University of Connecticut 118 Basic ECL: Conduction of QR VCC n RC VIN VE = RC VINV VNINV QR QI n VREF VE -VEE To maintain a symmetric cut-off situation, we design so that VBEI = RE University of Connecticut With a low input, and QI off, n VOL = This may be achieved through the choice of RC , but then QR is near saturation! 119 Improved ECL Gate RCI RCR VINV VIN n QR QI VNINV VREF n VE RO n n RE RO n -VEE Emitter followers have been added at the output. The fan-out is improved. The speed is improved. QR conducts safely in the forward active region. The outputs are referenced to ground for better noise immunity. Motorola ECL I, or MECL I, was the first standard family of ECL gates and utilized the basic design shown here, with a -5.2V supply and a fixed reference voltage. University of Connecticut 120 Motorola ECL I: VTC RCI 270Ω Approximate analysis: RCI 300Ω QBN VNOR V A QBO QIA VB QR QIB VREF VE RO 2kΩ RE 1.24kΩ βF = 50 VBEA = 0.75V VREF = -1.175V - 5.2V RO 2kΩ VOR Assuming a transition width of 0.1V at the input, VIL = VIH = If we neglect the base currents flowing through RCI and RCR: VOL = VOH = Hence University of Connecticut VOL + VOH ≈ 2 121 Motorola ECL I: Dissipation RCI 270Ω With QR conducting, RCR 300Ω QBN VNOR V A QBO QIA VB QR QIB VREF PL = VOR VE RO 2kΩ RE 1.24kΩ βF = 50 VBEA = 0.75V VREF = -1.175V RO 2kΩ With QIA or QIB conducting, - 5.2V PH = NOTE: PH and PL are defined with respect to the noninverting output. University of Connecticut 122 ECL: Temperature Effects n For a fixed level of current, the forward voltage across a PN junction decreases with increasing temperature dV = fixed dT current Experimental values are approximately -2mV / oC n n VOL and VOH therefore move toward ground as the temperature increases With a fixed VREF , ECL malfunctions for T > 60 oC. ECL II uses a temperature-compensated bias driver. University of Connecticut 123 ECL: Temperature Effects n Temperature dependence of VOH: dVOH dT n Temperature dependence of VOL: VOL = dVOL = dT n To stay centered between VOH and VOL, VREF should increase approximately 1.5mV/ oC. University of Connecticut 124 Temperature-Compensated Bias Driver for ECL II n RBH QB DL1 to VREF DL2 RBE The temperature-compensated bias driver keeps VREF roughly centered between VOH and VOL: VREF ≈ dVREF ≈ dT RBL -VEE n University of Connecticut This approach is not entirely satisfactory because there may be temperature variations within the system. 125 Standard ECL Gates VCC1 = GND VCC2 = GND RCI RCR QBO VOR QB VA QIA VB RO QIB QR RE -VEE = - 5.2V 10k III RBH QBN VNOR II DL1 DL2 RBE RBL RO RE 1.18 RCI 0.29 RCR 0.30 RB RO 2.0 RBH 0.30 RBL 2.3 RBE 2.0 P (mW) 20 tP (ns) 4 0.78 0.365 0.22 0.100 0.245 0.112 50 50 0.91 0.35 1.96 5.0 2.0 6.1 60 25 1 2 All resistors are in kilohms. The ECL II, ECL 10k, and ECL III families all use the same circuit design and voltage supplies. The differences: resistor values and transistor device designs yield differences in power / speed performance. University of Connecticut 126 60 4 50 3 40 30 2 20 1 10 0 0 0 0.1 0.2 propagation delay (ns) power dissipation (mW) Standard ECL Performance t P ∝ RC 1 P∝ RC PDP ∝ RC RC 0.3 RC (kΩ) For a particular BJT design, the PDP is independent of RC. University of Connecticut 127 Switching Speed of ECL n For ECL, the switching speed is limited by the charging of parasitic capacitances through finite resistors, internal to the gate. External RC time constants tend to be unimportant. n CBC and CP are the important capacitances. n RC is the important resistance. n ECL is very fast due to: • the small logic swing • the avoidance of saturated operation in transistors • The use of a low-impedance emitter follower to drive the load. University of Connecticut 128 Switching Speed of ECL n RC Consider the turn-off of QI in a two-input gate. At the collector of QI : QBN VCI ( t ) = VNOR VA n Solving for VCI (t)=VCI (0) / 2, family RC ECL II 295Ω ECL 10k 232Ω ECL III 106Ω ECL 100k 150Ω University of Connecticut QIA VB QIB tP = CBC 4 pF 3 pF 3 pF 1.5 pF tP (calc.) 4.1 ns 2.4 ns 1.1 ns 0.78 ns tP (meas.) 4.0 ns 2.0 ns 1.0 ns 0.75 ns 129 ECL 100k n n n n n Vintage 1985 Oxide-isolated transistors, similar to those used in 74F TTL, reduce the parasitic capacitances and improve switching speed. A reduced supply voltage (4.5V vs 5.2V) reduces dissipation. Improved temperature compensation makes VOH, VOL, and VREF almost independent of temperature (< 0.1mV/ oC for all) A current source, driven by a second voltage reference, minimizes voltage supply sensitivity. ∆VOL = −0.25 (ECL 10k) ∆VEE University of Connecticut ∆VOL = −0.01 (ECL 100k) ∆VEE 130 ECL 100k VCC1 = GND n VCC2 = GND RCI RCR 500Ω 500Ω VNOR RC QBN DL1 QBO 500Ω n VOR VA QIA VB DL2 QIB QR VREF1 = -1.2V VREF1 is designed to be independent of temperature and supply voltage. VREF2 is independent of temperature but varies with VEE such that VREF 2 − (−VEE ) = constant QE RE 300Ω -VEE = -4.5V University of Connecticut I EE = constant VREF2 = -3.2V n DL1 and D L2 provide output voltage T compensation 131 ECL 100k Consider a low output at VOR , with QR and DL2 conducting: I1 = VCC1 = GND VCC2 = GND R VNOR QBN I1 I2 R R QBO DL2 VOR IEE I2 = I EE = VOL = University of Connecticut 132 ECL 100k Consider a high output at VOR, with QI and DL1 conducting: I2 = VCC1 = GND VCC2 = GND R VNOR I1 I2 DL1 QBN R R QBO VOR IEE I1 = I EE = VOH = University of Connecticut 133 ECL 100K Bias Driver RBH 900Ω VREF1 is compensated for variations in T and VEE : R1 2kΩ VREF 1 = QB1 R2 3.1kΩ VREF1 QB2 I CB 3 ≈ QB3 VREF2 QSH R 900Ω RE1 1kΩ RX DL QSI QS2 RE2 100Ω -VEE = -4.5V University of Connecticut VREF 1 = The circuit is designed such that IES2 has a positive temperature coefficient, which cancels the negative coefficient for VBEA. 134 ECL 100K Bias Driver RBH 900Ω VREF2 is T compensated: R1 2kΩ VREF 2 = QB1 R2 3.1kΩ VREF1 QB2 VREF 2 = QB3 VREF2 QSH R 900Ω RE1 1kΩ RX DL QS1 QS2 RE2 100Ω -VEE = -4.5V University of Connecticut The temperature compensation is the same as for VREF1. Also, VREF2 varies directly with -VEE , so that VREF2 - ( -VEE ) is fixed. The shunt regulator QSH guarantees fixed currents in QS1 , QS2 , and QB3. 135 ECL Applications and Trends n n n n Si ECL gates are important for high data rate applications, such as vector architecture supercomputers. Massively parallel processor (MPP) and Symmetric Multiprocessing (SMP) architectures will continue to bring CMOS and BiCMOS into the supercomputer arena at the expense of ECL. Nonetheless, ECL is projected to hold a significant market share among Si digital IC’s until at least 2005 A.D. New materials and devices, such as GaAs/AlGaAs and Si/SiGe heterojunction bipolar transistors, may create a rebirth of ECL by boosting switching speeds to a new plateau (> 1 GHz). University of Connecticut 136

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