Studies in Systems, Decision and Control 37
Saleem Mohammed Ridha Taha
Reversible
Logic Synthesis
Methodologies
with Application to
Quantum Computing
Studies in Systems, Decision and Control
Volume 37
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Saleem Mohammed Ridha Taha
Reversible Logic Synthesis
Methodologies
with Application to Quantum
Computing
123
Saleem Mohammed Ridha Taha
Electrical Engineering Department, College
of Engineering
University of Baghdad
Baghdad
Iraq
ISSN 2198-4182
ISSN 2198-4190 (electronic)
Studies in Systems, Decision and Control
ISBN 978-3-319-23478-6
ISBN 978-3-319-23479-3 (eBook)
DOI 10.1007/978-3-319-23479-3
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Preface
Traditional technologies are increasingly beginning to suffer from the increasing
miniaturization and the exponential growth of the number of transistors in integrated circuits. The high rate of power consumption and the emergence of quantum
effects for highly dense integrated circuits are the biggest problems in system design
today and will be in the future. Reversible logic provides an alternative to face the
upcoming challenges. One of the main benefits that reversible logic brings about is
theoretically zero power dissipation. In order to reduce power consumption,
physical processes have to be logically reversible. Every future technology will
have to use reversible logic circuits in order to reduce power consumption. In the
area of quantum computation and low-power design, very promising results have
already been obtained today. Nevertheless, research on reversible logic is still at the
beginning stage.
This book provides several novel contributions to reversible logic synthesis.
Twelve reversible logic synthesis methodologies are presented for the first time in a
single literature. Evaluations for the comparative advantages and disadvantages
of these methodologies are also provided. Reversible sequential logic circuits are
discussed, with new designs of reversible sequential elements.
The tendency of current technologies is towards the nanoscale. Therefore, there
is a need to incorporate the physical quantum mechanical effects that are
unavoidable in the nanoscales. Representations and operations in quantum computing that use theorems of reversible computing and reversible structures to
compute functionalities using quantum logic are introduced. Applications of
wavelet and multiwavelet transformations to quantum computing structures are
discussed. New techniques to implement the Daubechies wavelets and multiwavelets using quantum circuits are proposed.
Finally, highlights of novel contributions that are presented in this book and the
future directions of research are provided.
In this context, the contributions to this book provide a good starting point. It is
hoped that this book will help to spur further research in the field of reversible and
quantum computations. In fact researchers in academia or industry and graduate
v
vi
Preface
students, who work in this field, will be interested in this book. Books that are
concerned with reversible synthesis of logic functions are rare. Therefore, there is a
need to publish books in this field. The first book [1] presented for the first time
comprehensive and systematic methods of reversible logic synthesis. It is hoped
that this book will be more valuable, because 12 methods of reversible logic
synthesis are introduced here, while only five are in Ref. [1]. Also, for the first time
the sequential reversible logic circuitries are discussed in a book.
This book opens the door to a new interesting and ambitious world of reversible
and quantum computing research. It presents the state of the art, with some new
proposals.
Baghdad
January 2015
Saleem Mohammed Ridha Taha
Reference
1. A.N. Al-Rabadi, Reversible Logic Synthesis: From Fundamentals to Quantum Computing
(Springer-Verlag, 2004)
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 What This Book Is About . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Major Contributions of This Book . . . . . . . . . . . . . . . . . . . .
1.5 Overview of the Book Chapters . . . . . . . . . . . . . . . . . . . . . .
1.6 Overall Message of the Book . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
2
2
3
3
4
4
2
Fundamentals of Reversible Logic . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Basic Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Reversible Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Feynman Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Toffoli Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Fredkin Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Reversible Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Overview of Reversible Logic Synthesis Methods . . . . . . . . . .
2.6 The Elimination of Garbage in Binary Reversible Circuits . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
8
9
9
11
11
12
12
14
15
3
Methods of Reversible Logic Synthesis. . . . . . . . . . . . . . . . . . . . .
3.1 Reversible Expansions and Reversible
Spectral Transforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
Reversible Ternary Shannon
and Davio Expansions . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
Reversible Shannon Spectral Transforms . . . . . . . . . .
3.1.3
Reversible Davio Spectral Transforms . . . . . . . . . . . .
17
17
19
21
23
vii
viii
Contents
3.2
The Elimination of Garbage in Ternary
Reversible Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Reversible Decision Trees (RDTs) . . . . . . . . . . . . . . . . . . . .
3.4 Reversible Decision Diagrams (RDDs) . . . . . . . . . . . . . . . . .
3.5 Reversible Lattice Circuits . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Symmetric and Non-symmetric Functions . . . . . . . . .
3.5.2
Two-Dimensional Lattice Circuits . . . . . . . . . . . . . . .
3.5.3
Three-Dimensional Lattice Circuits . . . . . . . . . . . . . .
3.5.4
Algorithms for Realizing the Shannon/Davio
Expansions of Ternary Functions
into 3D Lattice Circuits . . . . . . . . . . . . . . . . . . . . . .
3.5.5
Complete Example for the Implementation
of Ternary Functions Using 3D Lattice Circuits . . . . .
3.5.6
New Minimal Realization Method
for 3D Lattice Circuits. . . . . . . . . . . . . . . . . . . . . . .
3.5.7
Lattice Circuit Synthesis Using ISID . . . . . . . . . . . . .
3.5.8
The Creation of Reversible Lattice Structures . . . . . . .
3.5.9
3D Ternary Davio Reversible Lattice Structures . . . . .
3.6 Reversible Fast Transform Circuits . . . . . . . . . . . . . . . . . . . .
3.7 Group-Theoretic Representations. . . . . . . . . . . . . . . . . . . . . .
3.8 Reversible Reconstructability Analysis Circuits. . . . . . . . . . . .
3.8.1
Ternary MRA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2
Reversible MRA (RMRA) . . . . . . . . . . . . . . . . . . . .
3.9 Reversible Programmable Gate Array (RPGA) . . . . . . . . . . . .
3.9.1
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2
(2 * 2) Net Structures and RPGAs . . . . . . . . . . . . . .
3.9.3
The New Reversible Gate (SALEEM) . . . . . . . . . . . .
3.9.4
Novel Design of RPGA Based on the SALEEM
Reversible Gate . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Reversible Cascade Circuits . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Spectral-Based Synthesis Method . . . . . . . . . . . . . . . . . . . . .
3.12 Transformation-Based Network Synthesis
of Fredkin-Toffoli Cascade Gates . . . . . . . . . . . . . . . . . . . . .
3.13 Heuristic Algorithm for Reversible Logic Synthesis. . . . . . . . .
3.14 Constructive Synthesis of Reversible Circuits
by NOT and (n − 1)-CNOT Gates . . . . . . . . . . . . . . . . . . . .
3.15 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Evaluation of the Reversible Logic Synthesis Methodologies . . . . .
4.1 NPN-Classification of Logic Functions . . . . . . . . . . . . . . . . .
4.2 New Evaluation Procedure of Reversible
Synthesis Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
29
31
32
34
35
37
43
48
55
60
60
64
69
78
81
83
86
87
87
88
89
89
94
95
99
102
104
109
109
111
111
112
Contents
Comparison Between the Various Reversible
Synthesis Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
4.3
116
116
117
Reversible Sequential Logic Circuits . . . . . . . . . . . . . . . . . . . . . .
5.1 Reversible Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1
Reversible RS Flip Flop . . . . . . . . . . . . . . . . . . . . .
5.1.2
Reversible Clocked RS Flip Flop . . . . . . . . . . . . . . .
5.1.3
Reversible D Flip Flop . . . . . . . . . . . . . . . . . . . . . .
5.1.4
Reversible JK Flip Flop. . . . . . . . . . . . . . . . . . . . . .
5.1.5
Reversible T Flip Flop . . . . . . . . . . . . . . . . . . . . . .
5.1.6
Reversible Master-Slave Flip Flop. . . . . . . . . . . . . . .
5.1.7
The Superiority of Using the SALEEM Gate
in Reversible Flip Flops Design . . . . . . . . . . . . . . . .
5.2 Complex Reversible Sequential Circuits. . . . . . . . . . . . . . . . .
5.3 Novel Reversible Sequential Elements . . . . . . . . . . . . . . . . . .
5.3.1
New Design of Reversible T Flip Flop . . . . . . . . . . .
5.3.2
New Design of Reversible D Flip Flop . . . . . . . . . . .
5.3.3
New Design of Reversible JK Flip Flop . . . . . . . . . .
5.3.4
New Design of Reversible Master-Slave
Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5
Evaluation of the New Reversible Flip Flops . . . . . . .
5.4 Multiple-Valued Reversible Sequential Circuits. . . . . . . . . . . .
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
132
133
133
134
6
Quantum Logic Circuits and Quantum Computing . . . . . . . . . . .
6.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Quantum Bits and Superposition. . . . . . . . . . . . . . . . . . . . . .
6.3 Qubit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Quantum Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Quantum Logic Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Synthesis of Quantum Logic Circuits . . . . . . . . . . . . . . . . . .
6.7 Binary Quantum Decision Trees and Diagrams . . . . . . . . . . . .
6.8 Fundamentals of Ternary Quantum Computing . . . . . . . . . . . .
6.9 Quantum Computing for the Reversible Structures . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
135
137
138
139
141
144
145
146
148
149
7
Wavelets and Multiwavelets Implementation Using
Quantum Computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Quantum Circuits for Perfect Shuffle
Permutation Matrices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
119
119
120
121
122
123
124
125
126
126
129
129
130
130
153
153
154
x
Contents
7.3
8
Quantum Wavelet Algorithms. . . . . . . . . . . . . . . . . . . . . . . .
7.3.1
Wavelet Pyramidal and Packet Algorithms . . . . . . . . .
7.3.2
Daubechies D(4) Wavelet Factorization . . . . . . . . . . .
7.4 Quantum Implementation of Daubechies
D(4) Wavelet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Quantum Implementation of Daubechies
D(4) Multiwavelet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1
Computation of Discrete Multiwavelet Transform . . . .
7.5.2
Computation of Inverse Discrete
Multiwavelet Transform. . . . . . . . . . . . . . . . . . . . . .
7.5.3
A New Quantum Implementation of Daubechies
D(4) Multiwavelet Transform . . . . . . . . . . . . . . . . . .
7.5.4
A New Quantum Implementation of Inverse
Daubechies D(4) Multiwavelet Transform . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
156
157
158
167
170
Conclusions and Future Researches . . . . . . . . . . . . . . . . . . . . . . .
8.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Promising Areas of Further Researches . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171
171
173
174
160
161
162
163
163
Abbreviations
1-RPL
3D
3DTDRL
BDD
CCW
CIN
CNOT
CRA
D
DD
DMWT
DT
ESOP
EXOR
GBFM
GF
GGS
IDMWT
K-map
MRA
NCTSF
nD
pD
PUS
Qubit
RDD
RDDT
RDT
RGBFM
RMRA
RPGA
1-Reduced Post Literal
Three-Dimensional
Three-Dimensional Ternary Davio Reversible Lattice
Binary Decision Diagram
Counter Clock Wise
Common Indices Nodes
Controlled NOT
Conventional Reconstructability Analysis
Davio expansion
Decision Diagram
Discrete Multiwavelet Transform
Decision Tree
EXOR Sum-Of-Product
Exclusive-OR
Generalized Basis Functions Matrix
Galois Field
Gate–Garbage–Sum
Inverse DMWT
Karnough map
Modified Reconstructability Analysis
NOT, CNOT, Toffoli, Swap, Fredkin reversible gates
Negative Davio
Positive Davio
Positive Unate Symmetric
Quantum bit
Reversible Decision Diagram
Reversible Davio Decision Tree
Reversible Decision Tree
Reversible GBFM
Reversible MRA
Reversible Programmable Gate Array
xi
xii
RSGBFM
RSPP
S
S/D
SBDD
SPP
T.M.
ULM
Abbreviations
Reversible Shannon GBFM
Rational SPP
Shannon expansion
Shannon/Davio
Shared BDD
Size Power-consumption Product
Transform Matrix
Universal Logic Modules
Symbols
ð4Þ
D2n
Q2n
P4
P2n
ji
y
^
_
\
Daubechies fourth-order wavelet kernel of dimension 2n
Downshift Permutation matrix
Qubit Swap gate
Perfect Shuffle Permutation matrices
Vector representing a quantum state
Tensor product
Modulo 2 addition
Adjoint
Equivalence
Logical AND operator
Logical OR operator
Intersection operation
xiii
Chapter 1
Introduction
In this chapter, some of the background of the body of research upon which this
book builds is outlined (Sect. 1.1), description (Sect. 1.2) and motivation (Sect. 1.3)
of the topic of this book are explained, the major contributions of this book are
summarized (Sect. 1.4), a brief overview of the contents of the later chapters is
given (Sect. 1.5), and the overall message of the book is highlighted (Sect. 1.6).
1.1
Background
Interest in reversible logic started when Landauer in 1961 [1] proved that traditional
binary irreversible gates lead to power dissipation in a circuit regardless of
implementation. Each bit of information that is lost, generates KT ln(2) Joules of
heat energy, where K is Boltzmann’s constant (≈1.380658 × 10−23 J/K) and T the
absolute temperature (Kelvins) at which computation is performed. For room
temperature T the amount of dissipating heat is small (i.e. 2.9 × 10−21 J), but not
negligible [2–4]. Bennett in 1973 showed that for power not to be dissipated in an
arbitrary circuit, it is necessary that this circuit be built from reversible gates. The
importance of Bennett’s theorem lies in the technological necessity that every future
technology will have to use reversible gates in order to reduce power loss [5, 6].
Reversible circuits are those circuits that do not lose information and reversible
computation in a system can be performed only when the system comprises of
reversible gates. These circuits can generate unique output vector from each input
vector, and vice versa, that is, there is a one-to-one mapping (a permutation)
between input and output vectors [7, 8].
Hardware development truly took off in 1948, when the transistor was developed. Computer hardware has grown in power at an amazing pace ever since, so
much so that the growth was codified by Gordan Moore in 1965 in what has come
to be known as Moore’s law. This law states that since the invention of the transistor the number of transistors per chip roughly doubled every 18–24 months,
which means an increase in the computing power of computers [9]. This increase in
computing power is due primarily to the continuing miniaturization of the elements
of which computers are made, resulting in more and more elementary gates per unit
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_1
1
2
1
Introduction
area with higher and higher clock frequency, accompanied by less and less energy
dissipation per elementary computing event [10]. Amazingly, Moore’s law has
approximately held true in the decades since the 1960s. With the size of a single
transistor constantly shrinking according to Moore’s law, it is expected to reach the
atomic scale in a few years, where the postulates of quantum mechanics replace the
laws of classic physics. The transition to quantum computing will unlock capabilities that a conventional classic computer is inherently incapable of.
The anticipated failure of Moore’s law is around the year 2020. However, it is
hoped that quantum computing will play an important role in building more
compact and less power consuming computers. In addition to this fact, and because
all quantum computer building blocks should be reversible, reversible computing
will be greatly utilized in the future design of regular, compact, and universal
structures [11, 12].
1.2
What This Book Is About
This book is a detailed study of the various reversible logic synthesis methodologies. Making new developments to some of these methods is introduced. Also, an
evaluation of the implementation of the reversible structures is shown.
Reversible logic plays an important role in quantum computing. One of the goals
of this book is to show the application of reversible logic in quantum computing.
A new implementation of Wavelet and Multiwavelet transforms using quantum
computing is performed for this purpose.
1.3
Motivation
Aside from pure academic interest, the study of reversible computing can be
motivated in a fairly strong way, in terms of the long-term goals of society in
general and the field of computer science in particular.
A relatively small improvement in the speed and power of computers facilitates
progress in virtually every industry. It is in society’s interest that computer technology continue to improve rapidly for as long as possible. Quantum computing is
the upcoming revolution in computation. Since quantum computing must be
reversible, the first step towards the implementation of quantum computing is to
find methods for reversible computing.
Reversible logic is an emerging research area. It has attracted significant
attention in recent years. It has applications in quantum computing, nanotechnology, low power CMOS, and optical computing. Reversible technologies and the
synthesis of reversible networks are potentially very promising areas of study with
regard to further technological advances [13].
1.4 Major Contributions of This Book
1.4
3
Major Contributions of This Book
The primary novel, original contributions of this book are the following:
• Chapter 3 gathers together and presents in an organized form a variety of
twelve known reversible logic synthesis methods. This is the first that such
listing of reversible synthesis techniques is collected in a single literature.
In this chapter the following contributions are achieved.
– a new rule which is a correction to the rule in [12] is introduced for the
elimination of garbage outputs in ternary reversible circuits (Sect. 3.2).
– new algorithms for realizing the Shannon, Davio, and hybrid expansions of
ternary functions into 3D lattice circuits are introduced (Sect. 3.5.4).
– a new optimization method for lattice circuit synthesis is presented (Sect. 3.
5.6).
– two new rules for the realization of symmetrical binary and ternary functions
in reversible lattice circuits are shown (Sect. 3.5.8).
– a new algorithm is introduced for three-dimensional synthesis of ternary
Davio reversible lattice logic circuits (Sect. 3.5.9).
– a new reversible gate (SALEEM) with three versions I, II, and III is invented
(Sect. 3.9.3).
– a novel design of Reversible Programmable Gate Array (RPGA) based on
the new (SALEEM) reversible gate is presented (Sect. 3.9.4).
– a new minimization rule for constructive synthesis of reversible circuits is
given (Sect. 3.14).
• Chapter 4 introduces a new procedure for evaluation of the reversible synthesis
techniques introduced in Chap. 3.
• Chapter 5 presents the design of new reversible sequential logic circuits based
on the new (SALEEM) reversible gate.
• Chapter 7 does novel decomposition methods of Wavelet and Multiwavelet
transformations and their implementations using quantum computing
techniques.
That completes the summary of the major contributions of the book. This list
will be revisited once again in Chap. 8.
1.5
Overview of the Book Chapters
The body of this book contains eight chapters. These chapters evolve gradually
from basics towards the contributions. This chapter provides the overall introduction to the subject of reversible and quantum computing. The contents of the
various chapters of this book are summarized here.
4
1
Introduction
Chapter 2 introduces the fundamentals of reversible logic. Reversible logic gates
and certain definitions are described. Guidelines for reversible logic synthesis are
given. An overview of reversible logic synthesis methods is introduced with their
classifications.
Chapter 3 describes and analyzes in detail the well-known reversible logic synthesis methodologies. New ideas for reversible logic synthesis are proposed and
discussed in this chapter.
Chapter 4 presents an evaluation of the reversible logic synthesis methodologies
that have been described in the previous chapter. This evaluation is conducted on
different symmetric and non-symmetric logic functions. A proposed evaluation
scheme is presented, as well.
Chapter 5 introduces the synthesis of the reversible sequential logic circuits. New
reversible sequential circuits are proposed and compared with the currently known
circuits.
Chapter 6 presents the quantum circuits for the reversible structures.
Representations and operations in quantum computing that uses theorems of
reversible computing and reversible structures from previous chapters to compute
functionalities using quantum logic are introduced.
Chapter 7 discusses some potential applications of Wavelets and Multiwavelets to
quantum computing structures described in the previous chapter. New techniques to
implement the Daubechies Wavelets and Multiwavelets using quantum computing
are presented.
Chapter 8 summarizes the major contributions achieved in the book, and points out
the main areas where future work is needed.
1.6
Overall Message of the Book
The overall message of this book is that (1) reversible logic synthesis techniques are
not very different from or more difficult than ordinary logic synthesis techniques,
and (2) they will definitely be a necessary part of the long-term future of computing,
because energy loss is an important consideration in digital circuit design.
It is hoped that this book will help to spur further research in the field of
reversible and quantum computing. In fact this work is only one possible beginning,
it opens the door for an interesting and ambitious world of computing.
References
1. R. Landauer, Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5
(3), 183–191 (1961)
2. D. Maslov, Reversible logic synthesis, Ph.D. thesis, The Faculty of Computer Science, The
University of New Brunswick, Canada, 2003
References
5
3. G.W. Dueck, D. Maslov, Reversible function synthesis with minimum garbage outputs, in
Proceedings of the 6th International Symposium on Representations and Methodology of
Future Computing Technologies (RM 2003), Trier, Germany, pp. 154–161, March 2003
4. D. Maslov, G.W. Dueck, Garbage in reversible designs of multiple output functions, in
Proceedings of the 6th International Symposium on Representations and Methodology of
Future Computing Technologies (RM 2003), Trier, Germany, pp. 162–170, March 2003
5. A.T.S. Bashaga, Three-dimensional synthesis of ternary reversible lattice logic circuits, M.Sc.
thesis, Department of Electrical Engineering, College of Engineering, University of Baghdad,
2007
6. C.H. Bennett, Logical reversibility of computation. IBM J. Res. Dev. 17, 525–532 (1973)
7. H. Thapliyal, S. Kotiyal, M.B. Srinivas, Novel BCD adders and their reversible logic
implementation for IEEE 754r format, in Proceedings of the IEEE 19th International
Conference on VLSI Design (VLSID’06), Hyderabad, India, pp. 387–392, 4–7 January, 2006
8. M. Lukac, M. Pivtoraiko, A. Mishchenko, M. Perkowski, Automated synthesis of generalized
reversible cascades using genetic algorithms, in 5th International Workshop on Boolean
Problems, Freiburg, Germany, pp. 33–45, 19–20 September, 2002
9. S. Imre, F. Balazs, Quantum Computing and Communications: An Engineering Approach.
Wiley, New York, 2005
10. P. Vitanyi, Time, space, and energy in reversible computing, in ACM International
Conference on Computing Frontiers (CF’05), Ischia, Italy, 4–6 May, 2005
11. A.N. Al-Rabadi, New classes of Kronecker-based reversible decision trees and their
group-theoretic representation, in Proceedings of the International Workshop on Spectral
Methods and Multirate Signal Processing (SMMSP), Vienna, Austria, pp. 233–243, 11–12
September, 2004
12. A.N. Al-Rabadi, Reversible Logic Synthesis: from Fundamentals to Quantum Computing.
Springer, Berlin, 2004
13. D. Maslov, G.W. Dueck, D.M. Miller, Synthesis of Fredkin-Toffoli reversible networks. IEEE
Trans. Very Large Scale Integr. VLSI Syst. 13(6), 765–769 (2005)
Chapter 2
Fundamentals of Reversible Logic
This chapter is devoted to the basic information and definitions required to travel
around the reversible logic world safely. First, some preliminary concepts of
reversible logic are introduced in Sect. 2.1. Basic and important definitions in
reversible logic are explained in Sect. 2.2. Next the three most commonly used
reversible gates of Feynman, Toffoli and Fredkin are presented in Sect. 2.3. The
following Sect. 2.4 introduces interesting heuristics for reversible logic synthesis.
Literature review of reversible logic synthesis methods is given in Sect. 2.5. As in
everyday life everything has its price. The price of reversibility is the “garbage”
outputs which are not allowed in quantum computing and have to be eliminated as
explained in Sect. 2.6.
2.1
Preliminaries
Reversible computing is the path to future computing technologies, which all
happen to use reversible logic. In addition, reversible computing will become
mandatory because of the necessity to decrease power consumption.
Reversible logic circuits have the same number of inputs and outputs, and have
one-to-one mapping between vectors of inputs and outputs; thus the vector of input
states can be always reconstructed from the vector of output states [1].
Consequently, a computation is reversible, if it is always possible to uniquely
recover the input, given the output. Each gate can be made reversible by adding
some additional input and output wires if necessary [2].
Two constraints for reversible logic synthesis are: (1) feedback is not allowed,
and (2) fan-out is not allowed (i.e., fan-out = 1). A gate with k inputs and k outputs
is called a k*k gate. Several reversible gates have been proposed over the last
decades.
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_2
7
8
2.2
2 Fundamentals of Reversible Logic
Basic Definitions
In this section some important factors in reversible logic are explained. The main
object in reversible logic theory is the reversible function, which is defined as
follows.
Definition 2.1 The function f(x1, x2 … xn) of n Boolean variables is called
reversible if:
1. the number of outputs is equal to the number of inputs.
2. any input pattern maps to a unique output pattern.
In other words, the output of a reversible function is a permutation of the set of
its input [3, 4].
For an (n, k) function, i.e. function with n-input k-output, it is necessary to add
inputs and/or outputs to make it reversible. This leads to the following definition.
Definition 2.2 “Garbage” is the number of outputs added to make an (n, k)
function reversible. While the word “constant inputs” is used to denote the preset
value inputs that were added to an (n, k) function to make it reversible. The constant
inputs are known as ancilla inputs.
The relation between garbage outputs and constant inputs is [3, 4]
input þ constant input ¼ output þ garbage
As with reversible gates, a reversible circuit has the same number of input and
output wires; the reversible circuit with n inputs is called an n × n circuit, or a
circuit on n wires. More generally, Fig. 2.1 illustrates the general reversible circuit
of temporary storage [5, 6]. The top n–k lines transfer n–k signals Y to the corresponding wires on the other side of the circuit. The bottom k wires enter as the
input value X and emerge as the output value f(X). These wires usually serve as an
essential workspace for computing f(X). This circuit is said to compute f(X) using
n–k lines of temporary storage. This leads to the following definition.
n–1
Y
n–1
.
.
k
k–1
.
.
X
1
0
Reversible
circuit
.
.
Y
k
k-1
.
.
f(X)
0
Fig. 2.1 Reversible circuit with n–k wires Y of temporary storage [5]
2.2 Basic Definitions
9
Definition 2.3 Temporary storage channels of reversible circuits are the redundant
input–output line–pairs.
Other commonly used notations in reversible logic are explained as follows.
Definition 2.4 The size of a reversible gate is a natural number which shows the
number of its inputs (outputs).
Definition 2.5 Balanced circuits are circuits for which each output value appears a
number of times which is equal to the number of times that each of the other output
values appears.
For example, in balanced binary logic the circuit has half of minterms with value
1. While in balanced ternary logic one third of minterms have value 0, one third
have value 1 and one third have value 2.
Definition 2.6 Conservative circuits are circuits that have the same number of
values in inputs and outputs, i.e. a conservative circuit preserves the number of
logic values in all combinations.
In the next section it will be obvious that, while the (k, k) reversible gates: Wire
(Buffer), Inverter, Swap, and Fredkin are balanced and conservative, other
reversible gates: Feynman, and Toffoli are balanced but not conservative.
2.3
Reversible Logic Gates
Reversible circuits have functionality outputs and “garbage” outputs that are needed
only to achieve reversibility. Figure 2.2 shows some of the binary (k, k) reversible
gates that are commonly used in the synthesis of reversible logic circuits. While
Wire (Buffer), Not, and Swap gates (Fig. 2.2a, b, and c, respectively) are naturally
reversible, others are not, and thus “garbage” outputs have to be added.
Fredkin gate [7] together with Toffoli [8] and Feynman [9] gates belong to the
most often discussed in reversible and quantum literature, the following
sub-sections concentrate on the description of these gates.
2.3.1
Feynman Gate
The 2*2 Feynman gate (Fig. 2.2d), also called controlled-not (CNOT) or “quantum
EXOR”, realizes functions
P¼ A
Q ¼ AB
10
2 Fundamentals of Reversible Logic
(a)
A
(b)
A
(c)
A
(d)
A
B
A
P
B
A
B
Q
A
(e)
(f)
Q
R
P
P
A
B
Q
C
R
A
B
Q
(g)
C
R
A
P
B
C
Fig. 2.2 Binary reversible gates: a. (1,1) Wire, b. (1,1) Inverter, c. (2,2) Swap, d. (2,2) Feynman
gate, e. (3,3) Toffoli gate, f. (3,3) Fredkin gate, g. The simplified notation of the Fredkin gate
where A and B are the inputs, while P and Q are the outputs. The truth table of the
Feynman gate is as follows:
AB
PQ
00
01
10
11
00
01
11
10
this is why it is called
When A = 0 then Q = B, and when A = 1 then Q = B
controlled not. With B = 0 Feynman gate is used as a fan-out gate or a copying gate
(P = A and Q = A).
2.3 Reversible Logic Gates
2.3.2
11
Toffoli Gate
The 3*3 Toffoli gate (Fig. 2.2e) is also known as 3*3 Feynman gate or
controlled-controlled-not. It is described by the following equations:
P ¼ A,
Q ¼ B,
R ¼ AB C:
The truth table of the Toffoli gate is as follows:
ABC
PQR
000
001
010
011
100
101
110
111
000
001
010
011
100
101
111
110
this
From the truth table, it can be seen that when A and B equal one then R = C,
is why this gate is called controlled-controlled-not, because it has two control inputs
A and B to invert the third input C. Toffoli gate is an example of two—through
gates, because two of its inputs are given to the output.
2.3.3
Fredkin Gate
The 3*3 Fredkin gate (Fig. 2.2f) is also called controlled SWAP (CSWAP). It is
described by the following equations:
8
<P ¼ A
Q ¼ C if A ¼ 1 else B
:
R ¼ B if A ¼ 1 else C
8
<P ¼ A
or,
Q ¼ B AB AC
:
R ¼ C AB AC
In terms of classical logic this gate is just two multiplexers in a flipped (permuted) way from the same control input A. Figure 2.2g shows the simplified
notation of the Fredkin gate, while its truth table is shown below:
12
2 Fundamentals of Reversible Logic
ABC
PQR
000
001
010
011
100
101
110
111
000
001
010
011
100
110
101
111
The 3*3 Fredkin gate is a permutation gate, it permutes the data inputs of its two
multiplexers under control of the control input of these multiplexers. This control
input is also an output from the Fredkin gate. Fredkin gates are called one—through
gates, which means that gates in which one input variable is also an output.
2.4
Reversible Logic Synthesis
The real challenge in system design today, and in the future, is to design reliable
systems that consume as little power as possible and in which the signals are
processed and transmitted at very high signal integrity. Logically reversible devices
have to be used in order to reduce (theoretically eliminate) power consumption [10].
Heuristics for smart method of reversible logic synthesis are the following [1, 11]:
•
•
•
•
•
•
•
Do not create many outputs of gates and sub circuits.
These outputs are reused as inputs to other gates.
A good synthesis method minimizes the number of garbage signals.
The total number of constants at inputs of the gates is kept as low as possible.
If two copies of a signal are required, a copying circuit (Feynman gate) is used.
The resulting circuit is acyclic which means that there can be no loops.
The method must be generally applicable.
Since fan-out is not permitted, and assuming an appropriate technology, then a
reversible logic circuit can realize the inverse specification simply by applying the
gates in the reverse order. Hence, synthesis can be carried out from the inputs
toward the outputs or from the outputs toward the inputs.
2.5
Overview of Reversible Logic Synthesis Methods
Here, the basic classifications with brief descriptions of reversible synthesis
methods are done.
2.5 Overview of Reversible Logic Synthesis Methods
13
1. Composition methods [4, 12, 13]. The main idea is the use of small and well
known reversible gates in composing a reversible block. A network is then
synthesized by applying a conventional logic synthesis procedure.
2. Decomposition methods [4, 10, 14]. Decomposition methods can be considered as a top-down reduction of the function from its outputs to its inputs.
A function is decomposed into several functions which are realized as separate
reversible networks. There are several models of decomposition:
Ashenhurst-Curtis (AC) decomposition, Modified Reconstructability Analysis
(MRA), Bi-decomposition (BD), etc.
The composition and decomposition methods can be multilevel, as well as they
form a very general and powerful tool of logic synthesis [3].
3. EXOR logic based methods [4–6, 12, 13, 15–18]. These methods depend
mainly on the use of Toffoli gates. The Toffoli gate uses the EXOR operation in its
definition. The usage of the EXOR operation allows heuristic synthesis, as well as
it is very hard to analyze. Thus only heuristic approaches currently work [3].
4. Genetic algorithms [10, 19, 20]. The general idea behind genetic algorithms is
emulation of the evolution process. Evolutionary methods can be a good fit for the
minimization of the general case of incompletely specified functions. This is
important in order to realize smallest functional forms using the reversible structures. The genetic algorithm minimizer utilizes the Darwinian evolution, as well
Lamarckian and Baldwinian evolutions to minimize the logic functions. These
genetic algorithms have a lot offormulations and their actual implementations may
vary. Their main weakness is their extremely bad scaleability [3].
5. Search methods [12]. The idea of circuit design is to take a circuit and start
expanding and reducing it with maintaining its output functionality unchanged.
After a certain number of such operations, a more compact circuit may be
obtained. This technique is very expensive to use, since the size of the search
space grows exponentially with an increase in the depth of the search.
6. Group—theoretic methods [21]. The group Sn of all permutations of n elements
(objects) is a permutation group of order n!, where each of the n! group operators
(permutations) is a group element. General k-cycle group representations for
reversible circuits made of serial-interconnected and parallel-interconnected
reversible primitives are done by performing the appropriate step-by-step permutations of each stage of the reversible circuit. One of the weaknesses of this
approach is its need for a reversible specification.
7. Synthesis of regular structures such as nets [1, 10, 22], lattices [10, 11, 23],
and RPGAs [10, 22]. The idea behind these methods is to realize symmetric
reversible functions in a regular structure of reversible gates. By a regular
structure it is understood that a logic circuit and its physical layout structure
being an array of identical cells regularly connected. Such methods have a high
amount of garbage which is considered as a weakness of these methods.
8. Spectral techniques [24]. In these techniques a composition approach is
applied and its spectral complexity is calculated. A spectral technique is used to
find the best gate to be added in terms of gates (NOT, CNOT, Toffoli) and adds
14
2 Fundamentals of Reversible Logic
the gate in a cascade-like manner. The output function is required to appear as a
set of actual outputs, or their negations. Good results are obtained for small size
reversible functions. A post processing process to simplify the network is used.
The weaknesses of the method are: it scales badly, and requires a reversible
specification [3].
9. Exhaustive search [5, 6]. Here, all optimal networks for 3 input reversible
functions are found by matching all the minimal Toffoli gate networks (networks made of NOT, CNOT, Toffoli gates) with all reversible functions of 3
variables. It also considered minimal networks for 3 input reversible functions
with Toffoli gate networks and SWAP gates. While the algorithm to synthesize
optimal circuits scales better than its counterparts for irreversible computation,
it is still limited by an exponentially growing search space.
10. Binary Decision Diagram (BDD) based methods [21, 23, 25, 26]. A Boolean
function can be represented by BDD. A BDD is a directed acyclic graph where
Shannon decomposition is often carried out in each node. In these methods
BDDs are used to solve the quantified problem formulation. All minimal networks are found and the best one with respect to circuit complexity (cost) can
be chosen, thus leading to cheaper realizations.
2.6
The Elimination of Garbage in Binary Reversible
Circuits
In reversible logic circuits, where number of inputs is equal to the number of outputs,
reversibility of computation has been achieved at the cost of introducing the constant
inputs and garbage outputs (information that are not needed for the computation)
Forward circuit
Mirror circuit
x1
y1
x1
x2
y2
x2
.
.
.
F
-1
F
.
.
.
xn
.
.
yn
0
.
xn
yn
“spy” circuit
Fig. 2.3 The reversible circuit and its reversible mirror to eliminate garbage
2.6 The Elimination of Garbage in Binary Reversible Circuits
15
[4, 12]. To eliminate the garbage outputs, for avoiding energy loss due to garbage
accumulation, it is important to construct the inverse of the circuit. This is achieved
by taking the outputs of the reversible circuit and producing from them “inversely”
the inputs. This is important especially in quantum computing where garbage is not
allowed. Figure 2.3 shows reversible circuit called “forward” (the block on the left),
and its reversible inverse, called “mirror”, (the block on the right).
Each reversible gate realizes a reversible function. That is, for each input pattern
a unique output pattern, i.e. a one-to-one mapping, exists. Thus, calculating the
inverse of the function F for an output pattern is essentially the same operation as
propagating this pattern backwards through the circuit. Hence, if the cascade of n
reversible gates G = g0 g1 … gn−1 realizes a reversible function F, then the reverse
cascade G = gn−1 gn−2 … g0 realizes the inverse function F−1. The forward circuit is
composed by using reversible gates, while the mirror circuit is composed by
replacing each gate in the forward circuit by its inverse. It has been shown [10] that
each of Fredkin, Toffoli, and Feynman gates is the inverse of itself. To measure the
state of the hidden functions within the total network of the forward reversible part
and the inverse reversible part, the “spy” circuit is used. The “spy” circuit is
Feynman gate which is used as a copier by setting the value of the control input to
value “0”. The disadvantage of this approach of eliminating garbage signals is that
it causes the duplication of the circuit’s delay and the count of gates [11, 27].
References
1. M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song,
A. Al-Rabadi, L. Jozwiak, A. Coppola and B. Massey, Regular realization of symmetric
functions using reversible logic, in Proceedings of EUROMICRO Symposium on Digital
Systems Design (Euro-Micro’01),Warsaw, Poland, pp. 245–252, September 2001
2. P. Kaye, R. Laflamme, M. Mosca, An Introduction to Quantum Computing. Oxford University
Press Inc.,Oxford, 2007
3. D. Maslov, Reversible logic synthesis, Ph.D. thesis, The Faculty of Computer Science, The
University of New Brunswick, Canada, 2003
4. D. Maslov, G.W. Dueck, Garbage in reversible designs of multiple output functions, in
Proceedings of the 6th International Symposium on Representations and Methodology of
Future Computing Technologies (RM 2003), Trier, Germany, pp. 162–170, March 2003
5. V.V. Shende, A.K. Prasad, I.L. Markov, J.P. Hayes, Reversible logic circuit synthesis, in
Proceedings of the International Conference on Computer Aided Design (ICCAD 2002), San
Jose, California, USA, pp. 125–132, 10–14 November, 2002
6. V.V. Shende, A.K. Prasad, I.L. Markov, J.P. Hayes, Synthesis of reversible logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), 710–722 (2003)
7. E. Fredkin, T. Toffoli, Conservative logic, Int. J. Theor. Phys. 21(¾), 219–253 (1982)
8. T. Toffoli, Reversible computing, Technical Memo MIT/LCS/TM-151, MIT Lab. for
Computer Science (1980). (Also, in Automata, Languages and Programming, (eds.) by W. de
Bakker, J. van Leeuwen (Springer-Verlag, 1980), pp. 632–644.)
9. R.P. Feynman, Quantum mechanical computers. Opt. News 11(2), 11–20 (1985)
10. A.N. Al-Rabadi, Reversible Logic synthesis: From Fundamentals to Quantum Computing.
Springer, Berlin, 2004
16
2 Fundamentals of Reversible Logic
11. A.T.S. Bashaga, Three-dimensional synthesis of ternary reversible lattice logic circuits, M.Sc.
thesis, Department of Electrical Engineering, College of Engineering, University of Baghdad,
2007
12. G.W. Dueck, D. Maslov, Reversible function synthesis with minimum garbage outputs, in
Proceedings of the 6th International Symposium on Representations and Methodology of
Future Computing Technologies (RM 2003), Trier, Germany, pp. 154–161, March 2003
13. D.M. Miller, D. Maslov, G.W. Dueck, A transformation based algorithm for reversible logic
synthesis, in Proceedings of the Design Automation Conference, DAC 2003, Anaheim,
California, USA, pp. 318–323, 2–6 June, 2003
14. M. Perkowski, L. Jozwiak, P. Kerntopf, A. Mishchenko, A. Al-Rabadi, A. Coppola, A. Buller,
X. Song, M. Khan, S. Yanushkevich, V. Shmerko, A general decomposition for reversible
logic, in Proceedings of the 5th International Workshop on Applications of Reed-Muller
Expansion in Circuit Design (Reed-Muller’01), Starkville, Mississippi, USA, pp. 119–138,
10–11 August, 2001
15. D. Maslov, G.W. Dueck, D.M. Miller, Synthesis of Fredkin-Toffoli reversible networks. IEEE
Trans. Very Large Scale Integr. VLSI Syst. 13(6), 765–769 (2005)
16. G.W. Dueck, D. Maslov, D.M. Miller, Transformation-based synthesis of networks of
Toffoli/Fredkin gates, in IEEE Canadian Conference on Electrical and Computer
Engineering, CCECE 2003, Montreal, Canada, May 2003
17. D. Maslov, G.W. Dueck, D.M. Miller, Fredkin/Toffoli templates for reversible logic synthesis,
in Proceedings of the International Conference on Computer-Aided Design (ICCAD 2003),
San Jose, California, USA, 9–13 November, 2003
18. G. Yang, F. Xie, X. Song, W.N.N. Hung, M.A. Perkowski, A constructive algorithm for
reversible logic synthesis, WCCI – 2006
19. M. Lukac, M. Pivtoraiko, A. Mishchenko, M. Perkowski, Automated synthesis of generalized
reversible cascades using genetic algorithms, in 5th International Workshop on Boolean
Problems, Freiburg, Germany, pp. 33–45, 19–20 September, 2002
20. M. Lukac, M. Perkowski, H. Goi, M. Pivtoraiko, C.H. Yu, K. Chung, H. Jee, B. Kim, Y. Kim,
Evolutionary approach to quantum and reversible circuits synthesis. Artif. Intell. Rev. 20(3–4),
361–417 (2003)
21. A.N. Al-Rabadi, New classes of Kronecker-based reversible decision trees and their
group-theoretic representation, in Proceedings of the International Workshop on Spectral
Methods and Multirate Signal Processing (SMMSP), Vienna, Austria, pp. 233–243,
September 11–12, 2004
22. M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song,
A. Al-Rabadi, L. Jozwiak, A. Coppola, B. Massey, Regularity and symmetry as a base for
efficient realization of reversible logic circuits, in Proceedings of IWLS’01, Lake Tahoe,
California, USA, pp. 90–95, 12–15 June, 2001
23. A.N. Al-Rabadi, Spectral techniques in the reversible logic circuit synthesis of switching
functions, in Proceedings of the International Workshop on Spectral Methods and Multirate
Signal Processing (SMMSP), Vienna, Austria, pp. 271–279, 11–12 September, 2004
24. D.M. Miller, Spectral and two-place decomposition techniques in reversible logic, in
Proceedings of the IEEE Midwest Symposium on Circuits and Systems (MWSCAS 02),
II 493–II 496, August 2002
25. P. Kerntopf, A new heuristic algorithm for reversible logic synthesis, in Proceedings of the
41st Annual Conference on Design Automation (DAC 2004), California, USA, pp. 834–837,
7–11 June, 2004
26. R. Wille, H.M. Le, G.W. Dueck, D. Groβe, Quantified synthesis of reversible logic, in Design,
Automation and Test in Europe (DATE 08), pp. 1015–1020, 2008
27. A.B. Khlopotine, M. Perkowski, P. Kerntopf, Reversible logic synthesis by iterative
compositions, in International Workshop on Logic Synthesis, 2002
Chapter 3
Methods of Reversible Logic Synthesis
The synthesis of reversible circuits differs substantially from synthesis using traditional irreversible gates. A circuit is said to be reversible if there is a bijective
mapping of the input assignments into the output assignments. So, it is assumed that
the number of outputs in a reversible circuit (or gate) is the same as the number of
inputs. In addition, the fan-outs and feedback loops are not allowed. Thus, logic
design of reversible circuits is a new and challenging task. This chapter is devoted
to the synthesis techniques of reversible logic circuits. It describes the well-known
twelve reversible logic synthesis methods. These methods are not found in a single
literature. In this Chapter, new ideas for reversible logic synthesis are proposed, as
well. First the reversible Shannon and Davio expansions and spectral transforms
according to the applied notations in the literature are presented in (Sect. 3.1). Next,
in (Sect. 3.2) the elimination of garbage in ternary reversible circuits is introduced.
Different synthesis approaches of reversible circuits are discussed in (Sects. 3.3–
3.14). New ideas and improvements to already exist methods are introduced in
(Sects. 3.2, 3.5, 3.9 and 3.14). Summary of the chapter is presented in (Sect. 3.15).
3.1
Reversible Expansions and Reversible Spectral
Transforms
The Shannon’s expansion theorem states that: (Any Boolean function f(x1, x2 …
xn) can be written in the form
f(x1 ; x2 . . .; xn Þ ¼ x1 fð0; x2 . . .; xn Þ þ x1 f ð1; x2 . . .; xn Þ
This expansion can be done in terms of the n variables) [1].
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_3
17
18
3 Methods of Reversible Logic Synthesis
The term f(0, x2 …, xn) is called the cofactor (residue) of f with respect to x1 ; it is
denoted in shorthand notation as f x1 : Similarly, the term f(1, x2 …, xn) is called the
cofactor of f with respect to x1 ; written f x1 : The function can then be expressed in
terms of these cofactors [2]:
f ¼ x1 f x1 þ x1 f x1
The complexity of the logic expression may vary, depending on which variable,
xi , is used. Shannon’s expansion can be made in terms of more than one variable.
The cofactors f x1 and f x1 are called the negative and positive cofactors,
respectively, of f with respect to variable x1. They are denoted as f 0 and f 1 , where
f 0 ¼ fð0; x2 . . .; xn Þ and f 1 ¼ f(1; x2 . . .; xn Þ: The exclusive sum (EXOR) of the
negative and positive cofactors is denoted as f 2 , where
f 2 ¼ f 0 f 1:
Reed-Muller based normal forms are based on three basic functional expansions:
Shannon (S), positive Davio (pD), and negative Davio (nD) expansions, which are
given below, respectively [3, 4]:
f(x1 ; x2 . . .; xn Þ ¼ x1 f 0 ðx1 ; x2 . . .; xn Þ x1 f 1 ðx1 ; x2 . . .; xn Þ
1 0 f0
¼ ½ x1 x1 0 1 f1
ð3:1Þ
f(x1 ; x2 . . .; xn Þ ¼ 1 f 0 ðx1 ; x2 . . .; xn Þ x1 f 2 ðx1 ; x2 . . .; xn Þ
1 0 f0
¼ ½ 1 x1 1 1 f1
ð3:2Þ
f(x1 ; x2 . . .; xn Þ ¼ 1 f 1 ðx1 ; x2 . . .; xn Þ x1 f 2 ðx1 ; x2 . . .; xn Þ
0 1 f0
¼ ½ 1 x1 1 1 f1
ð3:3Þ
All operations in the above equations are performed using Boolean algebra, i.e.,
⊕ is Boolean EXOR, and · is Boolean multiplication.
The Galois field (GF) algebraic structure is a fundamental algebraic structure in
the theory of algebras. Galois field proved to possess desired properties in many
circuit applications such as testing, communications, and signal processing.
Figure 3.1 shows GF addition and multiplication for binary GF(2) and ternary GF
(3) radices.
3.1 Reversible Expansions and Reversible Spectral Transforms
(a)
+ 0 1
0 0 1
1 1 0
(c)
(b)
+
* 0 1
0 0 0
1 0 1
19
(d)
0
1
2
*
0
1
2
0 0
1 1
2 2
1
2
0
2
0
1
0
1
2
0
0
0
0
1
2
0
2
1
Fig. 3.1 Galois field addition and multiplication tables, a GF(2) addition, b GF(2) multiplication,
c GF(3) addition, d GF(3) multiplication
3.1.1
Reversible Ternary Shannon and Davio Expansions
A literal is a function of a single variable. There are various literals to choose from
but the simplest is the 1-Reduced Post Literal (1-RPL) [3], it is defined as:
i
x¼1
iff x ¼ i
else i x ¼ 0
ð3:4Þ
For example, 0x, 1x, 2x are the zero, first, and second polarities of the 1-RPL,
respectively. Also, the ternary shifts of variable x are defined as: x with no shift, x′
with one shift and x″ with two shifts (i.e., x = x + 0, x′ = x + 1, and x″ = x + 2,
respectively), and x can take any value in the set {0, 1, 2}.
The fundamental Shannon expansions over GF(3) for a ternary function with
respect to the variable x as [5–8]:
f ð xÞ ¼ 0 x f 0 þ 1 x f 1 þ 2 x f 2
ð3:5Þ
where f0 = f(x = 0), f1 = f(x = 1), and f2 = f(x = 2), are the cofactors of the function
f(x).
Using the addition and multiplication over GF(3), and the axioms of GF(3), it
can be shown that the ternary 1-RPLs, which are defined in Eq. (3.4), are related to
the powers of shifts of variables over GF(3) as follows:
x ¼ 2ðxÞ2 þ 1
ð3:6Þ
x ¼ 2ðx0 Þ þ 2ðx0 Þ
ð3:7Þ
x ¼ 2ðx00 Þ þ x00
ð3:8Þ
x ¼ 2ð xÞ 2 þ 2ð xÞ
ð3:9Þ
1
x ¼ 2ðx0 Þ þ x0
ð3:10Þ
1
x ¼ 2ðx00 Þ þ 1
ð3:11Þ
0
0
2
0
1
2
2
2
20
3 Methods of Reversible Logic Synthesis
x ¼ 2ðxÞ2 þ x
ð3:12Þ
x ¼ 2ðx0 Þ þ 1
ð3:13Þ
x ¼ 2ðx00 Þ þ 2ðx00 Þ
ð3:14Þ
2
2
2
2
2
After the substitution of Eqs. (3.6) through (3.14) in Eq. (3.5), and after the
minimization of the terms according to the axioms of Galois field, the following
Equations are obtained:
f ¼ 1 f 0 þ x ð2f 1 þ f 2 Þ þ 2ðxÞ2 ðf 0 þ f 1 þ f 2 Þ
ð3:15Þ
f ¼ 1 f 2 þ x0 ð2f 0 þ f 1 Þ þ 2ðx0 Þ ðf 0 þ f 1 þ f 2 Þ
ð3:16Þ
f ¼ 1 f 1 þ x00 ð2f 2 þ f 0 Þ þ 2ðx00 Þ ðf 0 þ f 1 þ f 2 Þ
ð3:17Þ
2
2
Equations (3.5) and (3.15)–(3.17) are the fundamental ternary Shannon and
Davio expansions (decompositions) for single variable, respectively. These
Equations can be rewritten in the following matrix-based forms, respectively:
!
F¼
f ¼ BS ½S~
0
x
!
f ¼ BD0 ½D0 ~
F¼ 1
!
f ¼ BD1 ½D1 ~
F¼ 1
!
f ¼ BD2 ½D2 ~
F¼ 1
2
1 0
1
x 2x 4 0 1
0 0
32 3
f0
0
0 54 f 1 5
1
f2
ð3:18Þ
2
1
x2 4 0
2
32 3
0
f0
1 54 f 1 5
2
f2
ð3:19Þ
x
0
2
2
x0
2
0
ðx0 Þ2 4 2
2
0
1
2
32 3
1
f0
0 54 f 1 5
2
f2
ð3:20Þ
x00
2
0
00 2 4 1
ðx Þ
2
1
0
2
32 3
f0
0
2 54 f 1 5
2
f2
ð3:21Þ
!
where BS and [S] are Shannon basis function vector and Shannon spectral
!
transform matrix, respectively, BD0 and [D0] are Davio0 basis function vector and
!
!
Davio0 spectral transform matrix, respectively; similarly, BD1 , [D1], BD2 , and [D2]
but for Davio1 and Davio2, respectively, and ~
F is the truth vector of a function f.
Equations (3.18)–(3.21) are expansions for a single variable. Yet, these expansions can be recursively generated for arbitrary number of variables using the
Kronecker (tensor) product (Eq. 3.37).
3.1 Reversible Expansions and Reversible Spectral Transforms
3.1.2
21
Reversible Shannon Spectral Transforms
Definition 3.1 The matrix that is constructed from the permutations of many basis
functions of the same type of the corresponding spectral transform is called
Generalized Basis Functions Matrix (GBFM) [3, 5, 6].
Definition 3.2 From the total space of the all possible GBFMs, the matrices that
produce reversible expansions are called Reversible Generalized Basis Function
Matrices (RGBFM) [3, 5, 6].
A necessary and sufficient condition to generate the reversible ternary Shannon
expansions is that the order of the permuted basis functions in the GBFM should
satisfy the following constraint: in any given row or column the elements in that
row or column are different than the elements in the adjacent positions of the other
rows or columns.
Equation
is the
2 0(3.18)
3 ternary Shannon transform over GF(3). One possible
1
2
x x x
GBFM is 4 0 x 2 x 1 x 5.
2
x 1x 0x
Yet the upper GBFM is not reversible; it does not produce a reversible expansion. The following GBFM is one possible Reversible Shannon GBFM (RSGBFM)
that leads to a reversible expansion:
20
x
4 1x
2
x
3
x
0 5
x
1
x
1
2
x
2
x
0
x
The reversibility constraint, mentioned above, can be illustrated by means of
tables as follows:
The ternary Shannon expansion over GF(3)
22
x
~
f ¼ 4 1x
0
x
0
x
2
x
1
x
32
1
x
0 54 0
x
2
0
x
1
0
1
0
32 3 2 3
f r0
0
f0
0 54 f 1 5 ¼ 4 f r1 5
f2
f r2
1
ð3:22Þ
is reversible as shown in Table 3.1.
It is obvious from Table 3.1, that due to the uniqueness in 1–RPL selection, the
result function values (i.e., cofactors f0, f1, and f2) for different 1–RPL values are
always distinct. The same method carries out for any configuration that reflects
RGBFM for any Galois radix [5, 6].
22
3 Methods of Reversible Logic Synthesis
Table 3.1 Reversibility
proof of Eq. (3.22)
1 − RPL
0
x
Function
Equation (3.22): f =
Equation (3.22): f =
Equation (3.22): f =
f1
f2
f0
1
x
2
f2
f0
f1
f0
f1
f2
x
The reversible Shannon expansions for ternary GF(3) using all possible permutations of the RGBFM of the Shannon transform matrix
2
1
40
0
3
0
05
1
0
1
0
are
20
x
~
f ¼ 4 1x
2
x
20
x
~
f ¼ 4 2x
1
x
21
x
~
f ¼ 4 0x
2
x
22
x
~
f ¼ 4 0x
1
x
21
x
~
f ¼ 4 2x
0
x
22
x
~
f ¼ 4 1x
0
x
1
32
1
x
0 54 0
x
1
0
x
0
1
0
32 3 2 3
f r0
f0
0
0 54 f 1 5 ¼ 4 f r1 5
f2
f r2
1
ð3:23Þ
32
1
x
1 54 0
x
0
0
x
0
1
0
32 3 2 3
f r0
f0
0
0 54 f 1 5 ¼ 4 f r1 5
f2
f r2
1
ð3:24Þ
32
1
x
2 54 0
x
1
0
x
0
1
0
32 3 2 3
0
f0
f r0
0 54 f 1 5 ¼ 4 f r1 5
1
f2
f r2
ð3:25Þ
32
1
x
2 54 0
x
0
0
x
0
1
0
32 3 2 3
0
f0
f r0
0 54 f 1 5 ¼ 4 f r1 5
1
f2
f r2
ð3:26Þ
32
1
x
1 54 0
x
2
0
x
0
1
0
32 3 2 3
f r0
f0
0
0 54 f 1 5 ¼ 4 f r1 5
f2
f r2
1
ð3:27Þ
32
1
x
0 54 0
x
2
0
x
0
1
0
32 3 2 3
f r0
f0
0
0 54 f 1 5 ¼ 4 f r1 5
f2
f r2
1
ð3:28Þ
x
2
x
0
x
2
1
x
0
x
2
x
2
2
x
1
x
0
x
0
0
x
1
x
2
x
1
2
x
0
x
1
x
0
0
1
x
2
x
1
x
Reversible circuits for the synthesis of Eqs. (3.23)–(3.28) were shown in [3, 6]
using (3, 3) multiplexers which are also called ternary Fredkin gates. These gates
are shown in Fig. 3.2 that realizes Eq. (3.25), as an example, where all inputs {x, f0,
f1, f2} and outputs {x, fr0, fr1, fr2} can have any of the ternary values {0, 1, 2}. The
process of forward permutation of cofactors is illustrated at the outputs of the
ternary reversible Shannon primitives in Fig. 3.2.
3.1 Reversible Expansions and Reversible Spectral Transforms
fr0 = 0x f2 + 1x f0 + 2x f1
x
fr1 = 0x f0 + 1x f1 + 2x f2
23
fr2 = 0x f1 + 1x f2 + 2x f0
0 1 2
0 1 2
0 1 2
f0
f1
f2
x
Fig. 3.2 Logic circuit realization of the reversible expansion in Eq. (3.25)
fr0
(a)
(b)
fr1
x
x
0
f0
1
0
fr0
fr1
x
x
1
0
1
f1
f0
0
1
f1
Fig. 3.3 Logic circuit realizations of reversible binary Shannon primitives: a for Eq. (3.29), and
b for Eq. (3.30)
In binary logic there are only two reversible Shannon gates as follows:
x
~
f¼
x
x
x
x
~
f¼
x
x
x
1 0
0 1
1 0
0 1
f0
f1
f0
f1
¼
¼
f r0
f r1
f r0
f r1
ð3:29Þ
ð3:30Þ
Figure 3.3 shows the logic circuit realizations of Eqs. (3.29) and (3.30).
3.1.3
Reversible Davio Spectral Transforms
Using Eqs. (3.23)–(3.28), reversible Davio expansions have been derived in [3].
This is done as follows: for one possible ternary reversible Shannon expansion such
that of Eq. (3.23), for example, the reversible Davio expansion is produced using
the same method that was utilized for deriving Eq. (3.19) from Eq. (3.18) using
Eqs. (3.4) and (3.6)–(3.14). There exist for Eq. (3.23) three Davio types for each
24
3 Methods of Reversible Logic Synthesis
row of the RSGBFM. The following are the D20—type expansions
for the first row,
3
0
x 1x 2x
second row, and third row of the RSGBFM 4 1 x 2 x 0 x 5, respectively (where
2
x 0x 1x
the subscripts indicate the orderings of the literals kx in the RSGBFM in Eq. (3.23),
and D0 indicates reversible Davio expansion of type D0):
f 012D0 ¼ 1 f 0 þ x ð2f 1 þ f 2 Þ þ ðxÞ2 ð2f 0 þ 2f 1 þ 2f 2 Þ
32 3
2
f0
1 0 0
6
76 7
2
¼ 1 x x 4 0 2 1 54 f 1 5 ¼ f r0D0
2
2
2
f2
f 120D0 ¼ 1 f 2 þ x ð2f 0 þ f 1 Þ þ ðxÞ2 ð2f 0 þ 2f 1 þ 2f 2 Þ
32 3
2
f0
0 0 1
6
76 7
2
¼ 1 x x 4 2 1 0 54 f 1 5 ¼ f r1D0
2 2 2
f2
f 201D0 ¼ 1 f 1 þ x ð2f 2 þ f 0 Þ þ ðxÞ2 ð2f 0 þ 2f 1 þ 2f 2 Þ
2
32 3
f0
0 1 0
6
76 7
2
¼ 1 x x 4 1 0 2 54 f 1 5 ¼ f r2D0
2
2
2
ð3:31Þ
ð3:32Þ
ð3:33Þ
f2
The above Davio0 expansions are reversible. Reversibility can be shown by
utilizing the identities in Eqs. (3.6), (3.9), and (3.12) to rewrite Eqs. (3.31)–(3.33) as
follows:
f 012D0 ¼ 1 þ 2x2 f 0 þ 2x þ 2x2 f 1 þ x þ 2x2 f 2
¼ 0 x f 0 þ 1 x f 1 þ 2 x f 2 ¼ f r0;D0
f 120D0 ¼ 1 þ 2x2 f 2 þ 2x þ 2x2 f 0 þ x þ 2x2 f 1
¼ 1 x f 0 þ 2 x f 1 þ 0 x f 2 ¼ f r1;D0
f 201D0 ¼ 1 þ 2x2 f 1 þ 2x þ 2x2 f 2 þ x þ 2x2 f 0
¼ 2 x f 0 þ 0 x f 1 þ 1 x f 2 ¼ f r2;D0
ð3:34Þ
ð3:35Þ
ð3:36Þ
By using results from Eq. (3.23), this shows the reversibility in Eqs. (3.34)–
(3.36).
The transform matrices in Eqs. (3.23)–(3.28) and (3.34)–(3.36) are produced for
higher dimensions using the Kronecker (tensor) product defined for a transform
matrix [M] as follows:
3.1 Reversible Expansions and Reversible Spectral Transforms
2
a
4b
c
d
e
f
25
2
3
3
a½M d½M g½M
g
h 5 ½M ¼ 4 b½M e½M h½M 5
c½M f½M i½M
i
ð3:37Þ
To produce one form of the reversible Davio0–type functional expansion, there
are three choices of the transform matrix as shown below.
1. If the transform matrix in Eq. (3.31) is chosen to produce the corresponding
reversible ternary Davio0 expansion, then:
2
1
! 4
f D0 ¼ 1
1
x
2þx
1þx
32
1
x2
1 þ x þ x2 5 4 0
2
1 þ 2x þ x2
32 3 2 3
f r0
0 0
f0
2 1 54 f 1 5 ¼ 4 f r1 5
2 2
f2
f r2
ð3:38Þ
Proof of Eq. (3.38)
2
a
4d
g
b
e
h
32
c
1
f 54 0
i
2
0
2
2
3 20
0
x
1 5 ¼ 4 1x
2
2
x
3
x
0 5
x
1
x
1
2
x
2
x
0
x
ð3:39Þ
After using Eqs. (3.6), (3.9), and (3.12); Eq. (3.39) becomes,
2
a þ 2c
4 d þ 2f
g þ 2i
2b þ 2c
2e þ 2f
2h þ 2i
3 2
b þ 2c
1 þ 2x2
4
5
e þ 2f ¼ 2x þ 2x2
h þ 2i
x þ 2x2
2x þ 2x2
x þ 2x2
1 þ 2x2
3
x þ 2x2
1 þ 2x2 5
2x þ 2x2
ð3:40Þ
From Eq. (3.40), the followings are obtained:
a ¼ 1; b ¼ x; c ¼ x2 ; d ¼ 1; e ¼ 2 þ x;
f ¼ 1 þ x þ x2 ; g ¼ 1; h ¼ 1 þ x; i ¼ 1 þ 2x þ x2
After substituting the above values of the terms a, b …, i in Eq. (3.39), it
becomes
2
1
41
1
x
2þx
1þx
32
1
x2
1 þ x þ x2 54 0
2
1 þ 2x þ x2
3 20
0 0
x
2 1 5 ¼ 4 1x
2
2 2
x
1
x
2
x
0
x
3
x
0 5
x
1
x
2
The substitution of Eq. (3.41) in Eq. (3.23) yields Eq. (3.38).
Q.E.D.
ð3:41Þ
26
3 Methods of Reversible Logic Synthesis
2. If the transform matrix in Eq. (3.32) is chosen, then:
2
1
! 4
f D0 ¼ 1
1
32
0
1 þ x 1 þ 2x þ x2
54 2
x
x2
2
2 þ x 1 þ x þ x2
0
1
2
32 3 2 3
f r0
1
f0
0 54 f 1 5 ¼ 4 f r1 5
f2
f r2
2
ð3:42Þ
The proof of Eq. (3.42) is similar to that of Eq. (3.38).
3. If the transform matrix in Eq. (3.33) is chosen, then:
2
1
! 4
f D0 ¼ 1
1
32
0
2 þ x 1 þ x þ x2
1 þ x 1 þ 2x þ x2 54 1
2
x
x2
1
0
2
32 3 2 3
f r0
0
f0
2 54 f 1 5 ¼ 4 f r1 5
f2
f r2
2
ð3:43Þ
The proof of Eq. (3.43) is similar to that of Eq. (3.38).
3.2
The Elimination of Garbage in Ternary Reversible
Circuits
The process of the elimination of output garbage in ternary reversible circuits follow
exactly the same methodology used for binary circuits (discussed in Sect. 2.6), by
cascading the forward and the inverse circuits.
Here, a new rule is proposed for the elimination of output garbage in ternary
reversible circuits which is a correction to the rule in [3].
The elimination of garbage for ternary reversible Shannon circuits (Eqs. 3.23–
3.28) is done as follows:
20
3
x 1x 2x
1. Considering Eq. (3.23), the RSGBFM matrix is 4 1 x 2 x 0 x 5 and the fol2
x 0x 1x
lowings are obtained:
f r0 ¼ 0 x f 0 þ 1 x f 1 þ 2 x f 2
f r1 ¼ 1 x f 0 þ 2 x f 1 þ 0 x f 2
f r2 ¼ 2 x f 0 þ 0 x f 1 þ 1 x f 2
Accordingly;
(a) if x = 0, then fr0 = f0, fr1 = f2, fr2 = f1
(b) if x = 1, then fr0 = f1, fr1 = f0, fr2 = f2
(c) if x = 2, then fr0 = f2, fr1 = f1, fr2 = f0
The circuit realization of Fig. 3.4 shows that, the elimination of garbage for
Eq. (3.23) is achieved by combining the ternary reversible forward Shannon
circuit with the ternary reversible inverse Shannon circuit.
3.2 The Elimination of Garbage in Ternary Reversible Circuits
Forward circuit
27
Inverse circuit
x
x
0
1
2
f0
0
1
2
f1
0
1
2
f2
0
1
2
fr0
0
1
2
fr1
0
1
2
fr2
f0
f1
f2
x
Fig. 3.4 The elimination of garbage for ternary Shannon gate of Eq. (3.23)
20
x
2. Considering Eq. (3.24), the RSGBFM matrix is 4 2 x
1
x
lowings are obtained:
1
x
0
x
2
x
3
x
1 5 and the folx
0
x
2
f r0 ¼ 0 x f 0 þ 1 x f 1 þ 2 x f 2
f r1 ¼ 2 x f 0 þ 0 x f 1 þ 1 x f 2
f r2 ¼ 1 x f 0 þ 2 x f 1 þ 0 x f 2
Accordingly;
(a) if x = 0, then fr0 = f0, fr1 = f1, fr2 = f2
(b) if x = 1, then fr0 = f1, fr1 = f2, fr2 = f0
(c) if x = 2, then fr0 = f2, fr1 = f0, fr2 = f1
Figure 3.5 shows that, in order to eliminate the output garbage for Eq. (3.24), the
outputs of the forward circuit (fr1 and fr2) should be swapped before their
application to the inverse circuit. Also, the outputs of the inverse circuit (f1 and
f2) are swapped.
21
3
x 2x 0x
3. Considering Eq. (3.25), the RSGBFM matrix is 4 0 x 1 x 2 x 5 and by
2
x 0x 1x
following exactly the same methodology used above in items 1 and 2, the result is
that; in order to eliminate garbage, swapping is required between the outputs of
the forward circuit (fr0 and fr2) as well as between the outputs of the inverse
circuit (f0 and f2).
28
3 Methods of Reversible Logic Synthesis
x
Forward circuit
f0
0
1
2
f1
f2
0
1
2
0
1
2
Inverse circuit
x
0
1
2
f0
fr0
fr1
0
1
2
0
1
2
fr2
f1
f2
x
Fig. 3.5 The elimination of garbage for ternary Shannon gate of Eq. (3.24)
22
3
x 0x 1x
4. Considering Eq. (3.26), the RSGBFM matrix is 4 0 x 1 x 2 x 5, the elimination
1
x 2x 0x
of garbage is achieved by direct combining of the
and3 inverse circuits.
2 1 forward
x 2x 0x
5. Considering Eq. (3.27), the RSGBFM matrix is 4 2 x 0 x 1 x 5, the elimination
0
x 1x 2x
of garbage is achieved by direct combining of the
and3 inverse circuits.
2 2 forward
x 0x 1x
6. Considering Eq. (3.28), the RSGBFM matrix is 4 1 x 2 x 0 x 5, the elimination
0
x 1x 2x
of garbage requires swapping between the outputs of the forward circuit (fr0 and
fr1), as well as between the outputs of the inverse circuit (f0 and f1).
The results of the above six cases, lead to introduce the following new rule for
eliminating garbage in ternary reversible Shannon circuits.
Rule: (For eliminating garbage in ternary reversible Shannon circuits, test the
RSGBFM square matrix. If the entries of the matrix aij = aji, then direct combining
is possible between the forward and the inverse circuits. However, if aij ≠ aji, then
permutation (swapping) is required between the two outputs of the forward circuit,
that correspond to the unequal literals around the RSGBFM diagonal. Also, similar
permutation is required at the outputs of the inverse circuit).
In fact, the above new rule is a correction to that in [3], which states that for the
all six Eqs. (3.23)–(3.28) direct combining is sufficient for eliminating garbage.
3.2 The Elimination of Garbage in Ternary Reversible Circuits
(b)
(a)
a b
0 0
0 1
0 2
1 0
1 1
1 2
2 0
2 1
2 2
c d
0 0
0 1
0 2
1 1
1 2
1 0
2 2
2 0
2 1
29
(d)
(c)
c d a b
0 0 0 0
0 1 0 1
0 2 0 2
1 1 1 0
1 2 1 1
1 0 1 2
2 2 2 0
2 0 2 1
2 1 2 2
a
c
c
a
b
d
d
b
(e)
a
c
a
b
d
b
Fig. 3.6 Ternary reversible Feynman gate: a truth table for forward gate, b truth table for inverse
gate, c forward circuit, d inverse circuit, and e the elimination of garbage
However, it is proved here that, the circuits of Eqs. (3.24, 3.25, and 3.28) require
permutations; while those of Eqs. (3.23, 3.26, and 3.27) do not.
Figure 3.6 illustrates the elimination of garbage for ternary reversible Feynman
gate. Here, the inverse circuit should be constructed from two cascaded Feynman
gates (Fig. 3.6d). This is another correction to that in [3], which states that the
inverse circuit consists of a single Feynman gate.
3.3
Reversible Decision Trees (RDTs)
For one variable (one level), Fig. 3.7 represents the Shannon and Davio expansions
over GF(2), while Fig. 3.8 shows the basic S, D0, D1, and D2, ternary expansions.
In binary and ternary decision trees it is possible to have expansions that are mixed
of Shannon for certain variables and Davio for the other variables, see Fig. 3.9.
The Kronecker recursion defined in Eq. (3.37) is used for the reversible generation of the RGBFMs for functions of several input variables. This is shown as
follows [5, 6]:
!
!
f rn 1 ¼ ½½RGBFMrn rn ½½T:M:rn rn Frn 1
ð3:44Þ
where n is the number of variables, r is the logic radix, RGBFM is any reversible
generalized basis function matrix, and T.M. is the corresponding transform matrix.
For a two-variable third radix Galois logic, Eq. (3.44) becomes:
(a)
(b)
S
x
(c)
pD
x
1
nD
x
1
x
Fig. 3.7 Binary expansions: a Shannon, b positive Davio, and c negative Davio
30
3 Methods of Reversible Logic Synthesis
(a)
0
(b)
S
1
x
2
x
x
1
Equation (3.18)
(c)
D0
x2
x
(d)
D1
( )2
1
Equation (3.19)
D2
(
)2
b
2
1
Equation (3.20)
Equation (3.21)
Fig. 3.8 Ternary expansions: a Shannon, b Davio0, c Davio1, and d Davio2
(a)
0
1
a
S
0
b
(b)
S
1
b
2
a
a
b
0
b
1
b
1
D0
S
2
2
D1
b 1
b
b2
1
(a )2
a
D2
S
b (b ) 2 0 b
1
b
S
2
b
0
b
1
b
Fig. 3.9 Shannon/Davio (S/D) trees: a with three Shannon nodes and one Davio0 node, and
b with two Shannon nodes, one Davio1 and one Davio2 nodes
!
!
f 91 ¼ ½ ½RGBFM99 ½½T:M:99 F91
ð3:45Þ
For example, the generation of RDTs for binary logic functions of two variables
(a and b) for the case of reversible Shannon DTs is as follows.
2
f r0
3
6 f 7 a a f a0
1 0
1 0
f b0
b b
6 r1 7
~
f¼6 7¼
4 f r2 5
0 1
0 1
a a
f a1
f b1
b b
f r3
32
32
3
2 1 0 0 0
ab ab a
b ab
f a0b0
76
6
7
6 ab ab
ab ab
7
76 0 1 0 0 76 f a0b1 7
6
¼6
7
6
7
7
6
4 a
b ab a
b ab 54 0 0 1 0 54 f a1b0 5
f a1b1
0 0 0 1
ab a
b ab a
b
ð3:46Þ
Figure 3.10 shows the RDT synthesis for Eq. (3.46), where function inputs are
values in the leaves, input control variables a and b control the (2, 1) multiplexers’
outputs (i.e., (2, 1) internal nodes) and propagate through each level to the RDT
outputs, and basis functions are located on the internal interconnects (edges) where
—for variable of value 0 (i.e., a or b), and ··· for variable of value 1 (i.e., a or b).
If one multiplies each leaf value, going left-to-right, with all possible bottom-up
paths (i.e., from the leaves to the roots) and add them over Galois field
3.3 Reversible Decision Trees (RDTs)
fr0
fr1
31
fr2
fr3
a
a
b
b
fa0b0
fa0b1
fa1b0
fa1b1
Fig. 3.10 Multiplexer-based (6, 6) reversible Shannon decision tree (RSDT) for Eq. (3.46)
Table 3.2 Reversibility proof of the RSDT in Fig. 3.10
Input vector
Output vector
a = 0, b = 0, fa0b0, fa0b1, fa1b0, fa1b1
a = 0, b = 1, fa0b0, fa0b1, fa1b0, fa1b1
a = 1, b = 0, fa0b0, fa0b1, fa1b0, fa1b1
a = 1, b = 1, fa0b0, fa0b1, fa1b0, fa1b1
a = 0, b = 0, fr0 = fa0b0, fr1 = fa0b1, fr2 = fa1b0, fr3 = fa1b1
a = 0, b = 1, fr0 = fa0b1, fr1 = fa0b0, fr2 = fa1b1, fr3 = fa1b0
a = 1, b = 0, fr0 = fa1b0, fr1 = fa1b1, fr2 = fa0b0, fr3 = fa0b1
a = 1, b = 1, fr0 = fa1b1, fr1 = fa1b0, fr2 = fa0b1, fr3 = fa0b0
(using Fig. 3.1) then the outputs (fr0, …, fr3) are obtained, respectively. The (6, 6)
reversible Shannon decision tree (RSDT) in Fig. 3.10 is a multi-input multi-output
type of DTs, where Table 3.2 shows the proof of reversibility of such structure for
all possible values of the control inputs a and b.
It has been proved in [5] the followings:
1. There exist (n!) reversible Shannon DTs (RSDTs) over GF(n).
2. There exist (n2) reversible Davio DTs (RDDTs) of all types per reversible
Shannon DT, and a total of (n2 n!) for all possible reversible Shannon DTs.
The RDTs have big cost when implemented in hardware due to the fact that it
requires relatively large number of internal gates to realize such trees. This can be a
big disadvantage when considering such structures for the reversible synthesis of
logic circuits. However, the RDTs provide the notion of data structure reversibility
for the reversible implementation and manipulation of logic functions.
3.4
Reversible Decision Diagrams (RDDs)
Binary decision diagrams for representing Boolean functions were designed by
Akers in 1978 [9]. A decision diagram (DD) is a fundamental data structure that is
used extensively to represent and manipulate logic functions. A decision diagram
32
3 Methods of Reversible Logic Synthesis
over the set Xn:= {x1, x2 …, xn} is a rooted directed acyclic graph G = (V, E) with
vertex (node) set V containing two types of vertices, non-terminal and terminal (or
leaf) vertices, and E is the set of edges. A non-terminal vertex is labeled with a
variable from Xn, called the decision (or control) variable for vertex, and has
exactly two successors (in the case of binary) denoted by low and high. All nodes
with label xi are denoted as level i. A terminal vertex is labeled with a 0 or 1 (in the
case of binary) and has no successors. The size of a decision diagram is given by its
number of non-terminal nodes.
Decision diagrams are generated from a function by successive application of
expansions and reduction rules, until constant nodes are reached, and depending on
the type of expansion used in the nodes (being Shannon, positive Davio or negative
Davio). Binary decision diagrams (BDDs) are formed if only Shannon expansions
are used in nodes. If instead of Shannon expansions, the positive Davio or negative
Davio expansions are used in nodes then Functional Decision Diagrams (FDDs) are
generated.
Reversible decision diagrams (RDDs) have been created using two methods [6]:
1. direct synthesis from classical decision diagrams by using (a) reversible gates
and (b) the careful and optimal use of outputs from a level to the next in order to
minimize the number of gates and garbage lines used, and
2. the use of the classical rules for obtaining the corresponding RDDs from their
corresponding RDTs; these rules are: (1) join all of the isomorphic nodes, and
(2) remove all of the redundant nodes.
The following is an example illustrating the creation of a reversible binary
decision diagram (RBDD), using method 1, to realize the Boolean function
F ¼ ab þ bc þ ac, as shown in Fig. 3.11. In Fig. 3.11c, the binary reversible
Shannon primitives, also known as Fredkin gates, are used in the internal nodes.
Each node contains two multiplexers for reversibility, one to produce the output of
the node and the other to give garbage. In Fig. 3.11c, the desired output function is
denoted as F and the garbage outputs (that are necessary only for reversibility) are
denoted as G1–G5.
3.5
Reversible Lattice Circuits
Lattice diagrams are data structures that describe both regular geometry of connections, and logic of a circuit [10]. A regular structure describes a logic circuit and
its physical layout structure as being an array of identical cells regularly connected,
or a structure composed of few, regularly connected, structures of this type, called
planes [11]. Regularly connected means that every cell (except of boundary cells) is
connected to its k neighbors, so that there is no routing and all connections are short
and of equal length which will reduce the total length of the wires used for connections and consequently denser devices and signal delay decreases.
3.5 Reversible Lattice Circuits
33
(a)
(b)
F
F=a b + b c + a c
a
a
S
1
0
0
b
b
b+b c
0
1
bc+c
S
1
0
0
c
c
0
c
1
F
a
0
1
1
0
0
0
1
0
1
1
G3
1
0
1
a
1
0
1
G4
0
1
G1
c
1
S
0
(c)
b
0
1
G2
S
S
1
0
0
c
1
b
G5
0
1
0
0
1
0
1
0
1
c
1
Fig. 3.11 Reversible DD: a method for creation the Shannon BDD for the Boolean function F,
b BDD for F, and c RBDD for F
Lattice circuits represent an important class of regular circuits that allow for local
interconnections, predictable timing, fault localization, and self-repair. In addition,
three-dimensional lattice circuits can be potentially well suited for future 3D
technologies, such as nanotechnologies, where the intrinsic physical delay of the
irregular and lengthy interconnections limits the device performance [4].
34
3.5.1
3 Methods of Reversible Logic Synthesis
Symmetric and Non-symmetric Functions
One method to characterize a symmetry that might exist in a logic function is using
symmetry indices Si [12]. A symmetry index (Si) has superscript i equals to the
count of the number of “1” values in the states of variables in the corresponding cell
in a Karnough map (K-map) as in Table 3.3a. The K-map in Table 3.3b represents a
three variable symmetric function, because the values of a specific symmetry index
are equal for the whole map (S0 is equal to 1, S1 is equal to 1, S2 is equal to 0, and
S3 is equal to 0).
A function which is not symmetric can be made symmetric by repeating its
variables. This method of variable repetition transforms the values of K-map cells
which make the function non-symmetric into don’t care which make the function
symmetric. The K-map in Table 3.3c represents a non-symmetric function that has
conflicting values in the same symmetry indices, which is S1. The function can be
made symmetric by repeating variable a as in Table 3.3d.
Definition 3.3 A single index symmetric function, denoted as Sk(x1 … xn) has
value 1 when exactly k of its n inputs are equal to 1, and exactly (n − k) of its
remaining inputs are 0 [3, 12].
Definition 3.4 The elementary symmetric functions of n variables are:
S0 ¼ x1 x2 . . .xn ;
S1 ¼ x1 x2 . . .xn þ x1 x2 . . .xn
þ þ x1 x2 . . .xn . . .;
and
S ¼ x1 x2 . . .xn :
n
Table 3.3 (a) K-map of a 4 variable function showing the symmetry indices, (b) K-map of a 3
variable symmetric function, (c) Non-symmetric function with conflicting values, (d) Function in
(c) being made symmetric by repeating variable a
(a)
(b)
cd
ab
bc
00
01
11
10
00
0
S
1
S
2
S
1
S
0
S 1 S 1 S 0 S1 1
01
S1
S2
S3
S2
1
S1 1 S2 0 S3 0 S2 0
11
2
S
3
S
4
S
3
S
10
1
2
3
S2
S
S
S
a
bc
a
01
11
0
1
2
10
(d)
bc
aa
(c)
00
00
01
11
0
1
2
10
00
S 1 S 1 S 0 S1 1
00
01
11
10
01
S1 - S2 - S3 - S2 -
0
1
2
1
0
S 1 S 1 S 0 S 1
11
S2 0 S3 0 S4 0 S3 0
1
S1 0 S2 0 S3 0 S2 0
10
S1 - S2 - S3 - S2 -
3.5 Reversible Lattice Circuits
Fig. 3.12 The ternary
natural-encoded map of the
ternary symmetry indices
35
c
ab
0
1
2
0,0
00 S
1,0
S
S0,1
01 S1,0
S2,0
S1,1
02 S0,1
S1,1
S0,2
10 S1,0
S2,0
S1,1
11 S2,0
S3,0
S2,1
12 S1,1
S2,1
S1,2
20 S0,1
S1,1
S1,2
21 S1,1
S2,1
S1,2
22 S0,2
S1,2
S0,3
Thus, for a Boolean function of three variables, the following sets of symmetry
indices are obtained: S0 ¼ fabcg; S1 ¼ fabc; abc; abcg; S2 ¼ fabc; abc; abcg and
S3 ¼ fabcg. An arbitrary n-variable symmetric function f is uniquely represented
P
by elementary symmetric functions S0, S1 …, Sn as follows: f ¼ i2A Si ¼ SA ,
where A 2 f0; 1; . . .ng:
Symmetry indices are also generalized to include the ternary case as is shown in
Fig. 3.12. Here, the symmetry index Si,j counts the number of ones and twos in each
cell [3], where i represents the number of ones in the natural-encoded cell indices of
the ternary map, while j represents the number of twos.
3.5.2
Two-Dimensional Lattice Circuits
A lattice is a set of regularly placed gates locally interconnected to form a grid.
Each node (gate) in a 2D lattice has a control signal propagating from left-to-right
and two data inputs and two outputs (i.e., four neighbors) as in Fig. 3.13. Symmetry
indices are the sets of all possible paths from leaves to the root of a lattice circuit.
The concept of lattice circuits for switching functions involves three components
[3]:
1. Expansion of a function, that corresponds to the initial node (root) in the lattice,
which creates several successor nodes of the expanded node.
2. Joining (collapsing) of several nodes of a decision tree’s level to a single node,
which is the reverse operation of the expansion process.
3. Regular geometry to which the nodes are mapped that guides which nodes of
the level are to be joined.
36
3 Methods of Reversible Logic Synthesis
F = S0,1,2,4(a, b, c, d)
a
0
0
0
1
1
0
b
1
Initial node (root)
1
1
0
0
1
c
0
1 0
1 0
1
d
0
1 0
1 0
S0(a,b,c,d) S1(a,b,c,d) S2(a,b,c,d)
1 0
S3(a,b,c,d)
4-neighbor internal node
1
S4(a,b,c,d)
1
0
Terminal node (leaf)
Fig. 3.13 Two-dimensional lattice structure for a function of four variables
Figure 3.14 shows the joining rules to create lattice diagrams, for Shannon (S),
positive Davio (pD) and negative Davio (nD) expansions in nodes. The left side is
the case before joining non-isomorphic nodes, while the right side shows the situation after joining nodes [10].
Definition 3.5 The function that is generated by joining two nodes (sub-functions)
in a lattice circuit is called the joined function. The function that is generated in
nodes other than the joining nodes, to preserve the functionality in the lattice circuit,
is called the correction function [4].
The construction of the lattice circuit in Fig. 3.13 implements the following:
(1) top-to-bottom expansion, and (2) left-to-right joining [i.e., left-to-right propagation of the corresponding correction functions in Fig. 3.14b, c)]. In the case of
joining two Shannon expansion nodes, no a correction function is needed
(Fig. 3.14a), due to the fact that all of the Shannon cofactors are disjoint (i.e., no
overlap). If each leaf value, from left to right, is multiplied with all possible
bottom-up paths (from the leaves to the root) and adding them over Boolean algebra
then the function of the circuit (in the root) is obtained.
It has been shown (in Sect. 3.5.1) that every non-symmetric function can be
made symmetric by repeating its variables. Therefore, since a single variable corresponds to a single level in the lattice circuit, repeating variables produces a
repetition of levels in a lattice circuit.
In general, three main factors control the size of a lattice circuit that realizes
non-symmetric functions [12]:
1. expansion types that are used in the internal nodes,
2. order of variables upon which functions are expanded in each level of the lattice,
3. the choice of repeated variables.
Of course, the number of repetitions of variables and the number of nodes will
depend much on the variable ordering. Every order of variables leads to a solution.
3.5 Reversible Lattice Circuits
(a)
f
37
g
f
RULE(S, S)
a
a
a
a
f0
f1
g0
g1
a
a
a f1
f0
adjacent nodes
(b)
f
1
1
f2
f0
RULE (pD, pD)
a
g0
a
a
a g0
g1
joined function
g
a
g
f
g
1
g2
a
a f2
f0
adjacent nodes
1
a
f2
a g0
g0
g2
joined function correction function
RULE (nD, nD)
(c)
f
g
f
1
a
1
a
f1
f2
g1
g2
adjacent nodes
g
1
f1
a
a f2
1
a g1
a
f2
g1
g2
joined function correction function
Fig. 3.14 Joining rules to create lattice diagrams, a for Shannon expansion, b for positive Davio
expansion, and c for negative Davio expansion
If the function is symmetric and complete, it is realized with a lattice of arbitrary
order of variables without repetitions [10].
3.5.3
Three-Dimensional Lattice Circuits
The concept of two-dimensional lattice circuits that was presented in the previous
Sect. 3.5.2 can be generalized to include the case of three-dimensional lattice
circuits. Regular lattices can be realized in the 3D space for the third Galois radix.
Higher dimensionality lattices (for radices higher than three) can be implemented in
3D space but on the expense of losing the full regularity. This is because the circuit
realization for the ternary case produces a fully regular structure in 3D (all interconnections are of the same length). Realizing the higher dimensionality lattices in
lower dimensionality space is possible but with the expense of regularity; the
lattices will not be fully regular due to the uneven length of the interconnections
between nodes [3, 4].
38
3 Methods of Reversible Logic Synthesis
Because our physical space is three-dimensional, lattice circuits, as a geometrical
concept, can be realized in solid material, with all the interconnections between the
cells are of the same length, only for Galois radix two (2D space) or Galois radix
three (3D space). Thus, the ternary lattice circuits have structures that can make the
best use of three-dimensional space.
A very important property of lattice circuits is the high regularity, which is
useful in many applications of fault-related issues: (1) fault diagnosis (testing),
(2) fault localization, and (3) fault self-repair. Other advantages concerning the 3D
lattice circuits include: (a) no need for 3D layout routing and placement, analogously to the 2D case, and (b) regularity lead to ease of manufacturability. The 3D
lattice circuits can be especially well suited for future 3D based technologies, where
the intrinsic physical delay of the irregular and lengthy interconnections limits the
device performance in the form of high power consumption and high delay in the
interconnects especially at high frequencies [4].
Figure 3.15 illustrates a fully regular lattice structure in three dimensions. Such
lattices represent 3D 6-neighbour lattice structures. Each cell in the 3D lattice
represents a 3-to-1 multiplexer.
In 3D space, each control variable spreads in a plane to control the corresponding nodes, these planes are represented using the dotted triangles in Fig. 3.15.
Since the 3D lattice structures exist in 3D space, a geometrical reference of coordinate system is needed to be systematic in the realization of the corresponding
logic circuit. The right-hand rule of Cartesian coordinate system is adopted. Each
dimension corresponds to a value of the corresponding control variable; value 0 of
the control variable propagates along the x-axis, value 1 propagates along the
y-axis, and value 2 along the z-axis. Each node is denoted in the lattice structure by
their 3D Cartesian coordinates; the tuple{x, y, z}. Symmetry indices Si,j are also
shown in Fig. 3.15.
Analogously to the binary case, fully symmetric ternary functions do not need
any joining operations to repeat variables. Non-symmetric ternary functions cannot
be realized in a 3D lattice circuit without repeating variables [9]. In general, for nth
radix it is sufficient to join n nodes in n-dimensional space to obtain the corresponding lattice structure. For the binary it was sufficient to join two nodes, while in
the ternary it is sufficient to join three nodes to form the corresponding 3D lattice
structure [3].
To produce the repetition of variables for an arbitrary non-symmetric ternary
function, joining operators are needed to: (1) join the corresponding nodes in 3D
space, and (2) produce the corresponding correction functions in order to preserve
the output functionality of the 3D lattice circuit. Figure 3.16 represents such joining
for 3D lattice circuits, where three nodes: A, B and C are joining (super-imposing)
their nodes Ax, By and Cz, respectively, to form the super-imposed node J. The set
of nodes {Ax, Ay, Az } are the cofactors of the node A. The set of nodes {Bx, By,
Bz} are the cofactors of the node B. The set of nodes {Cx, Cy, Cz} are the cofactors
of the node C.
The nodes Ax, Bx and Cx are the cofactors of their corresponding nodes along
the x-axis. While, the nodes Ay, By, Cy and Az, Bz, Cz are the cofactors along the
3.5 Reversible Lattice Circuits
z
39
n(0,0,3)
S0,3
2
1
y
0
2
x
n(0,0,2)
c
1
c
n(0,1,2)
S1,2
c
0
c
2
n(1,0,2)
2
b
0,2
n(0,0,1)
S
n(0,1,1)
1
2
0
c
b
1
n(1,0,1)
c
c
2
n(1,0,0)
c
0
n(2,0,0) c
0
c
2
S
1
2
a
1
b
S2,1
2
b
c
n(1,1,1)
1
a
b
a
0
S
2
a
n(0,2,1)
c
c
1,1
c
b
0,1
c
0
n(0,0,0)
n(2,0,1)
1
b
b
2
0
c
0
c
b
n(1,0,0)
1
c
n(0,1,0)
0
b
c
n(1,1,0)
1
b
c
c
c S3,0
n(0,2,0)
n(0,3,0)
2,0
S
n(1,2,0)
b
1
c
S1,0
n(2,1,0)
S0,0
n(3,0,0)
Fig. 3.15 3D Shannon lattice structure
y-axis and the z-axis, respectively. The edge values between two nodes along the
three axes are assigned the values shown in Table 3.4 of variable {a}.
Definition 3.6 The joining node J is formed by joining (super-imposing) three
cofactors of three different nodes A, B, and C. The three cofactors are the x-axis
cofactor of the first node A, the y-axis cofactor of the second node B, and the z-axis
cofactor of the third node C; that is Ax, By, and Cz, respectively.
Definition 3.7 After joining, the correction functions D and E should be the x-axis
cofactor of node B and the y-axis cofactor of node C, respectively; for simple
derivation of these correction functions.
Theorem 3.1 For a lattice circuit with all ternary Shannon nodes, the following is
the possible joining rule:
40
3 Methods of Reversible Logic Synthesis
z
Az
2
1
y
Bz
A
0
Ay
x
B
By
Ax
Cz
Bx
C
J
Cy
Cx
( Before
joining )
Az
D
Bz
Jz
B
J
Jy
C
E
A
Ay
Jx
Cx
( After joining )
Fig. 3.16 General 3D lattice circuit for three joining nodes (Ax, By, Cz) and a single joined node J
J ¼ 0 a Ax þ 1 a By þ 2 a Cz
ð3:47Þ
The joined three cofactors become the corresponding three cofactors of the
joining node J, and no correction functions are needed.
Proof Referring to Fig. 3.16 and Table 3.4, the following sets of equations before
and after joining the three nodes Ax, By, and Cz are obtained:
3.5 Reversible Lattice Circuits
Table 3.4 The edge values
of the 3D lattices
41
Expansion
Edge value
x-axis
y-axis
z-axis
Shannon
Davio0
Davio1
Davio2
0
1
2
a
1
1
1
a
a
a′
a″
a
a2
(a′)2
(a″)2
Before joining the nodes:
A ¼ 0 a Ax þ 1 a Ay þ 2 a Az
ð3:48Þ
B ¼ 0 a Bx þ 1 a By þ 2 a Bz
ð3:49Þ
C ¼ 0 a Cx þ 1 a Cy þ 2 a Cz
ð3:50Þ
A ¼ 0 a J þ 1 a Ay þ 2 a Az
ð3:51Þ
B ¼ 0 a D þ 1 a J þ 2 a Bz
ð3:52Þ
C ¼ 0 a Cx þ 1 a E þ 2 a J
ð3:53Þ
After joining the nodes:
where D and E are the correction functions and J is the joining (super-imposed)
node in Fig. 3.16. The fundamental Shannon decomposition over GF(3) for a
ternary function J with a single variable is
J ¼ 0 a Jx þ 1 a Jy þ 2 a Jz
ð3:54Þ
By equalizing Eqs. (3.48)–(3.50) to Eqs. (3.51)–(3.53), respectively, and
applying Eq. (3.54) the following results are obtained: D = Bx, E = Cy, Jx = Ax,
Jy = By, Jz = Cz. Therefore,
J ¼ 0 a Ax þ 1 a By þ 2 a Cz
Q.E.D.
Definition 3.8 The joining rule of any ternary Shannon decomposition does not
need any correction function, due to the fact that all of the Shannon cofactors are
disjoint (i.e., no overlap).
Theorem 3.2 For a lattice circuit with all ternary Davio0 (D0) nodes, the following
is the possible set of joining rule, and correction functions, respectively:
42
3 Methods of Reversible Logic Synthesis
J ¼ Ax
ð3:55Þ
D ¼ 2a Ax þ Bx þ a By
ð3:56Þ
E ¼ 2a Ax þ Cy þ a Cz
ð3:57Þ
Proof Referring to Fig. 3.16 and Table 3.4, the following sets of equations before
and after joining the three nodes Ax, By, and Cz are obtained:
Before joining the nodes:
A ¼ Ax þ a Ay þ a2 Az
ð3:58Þ
B ¼ Bx þ a By þ a2 Bz
ð3:59Þ
C ¼ Cx þ a Cy þ a2 Cz
ð3:60Þ
A ¼ J þ a Ay þ a2 Az
ð3:61Þ
B ¼ D þ a J þ a2 B z
ð3:62Þ
C ¼ C x þ a E þ a2 J
ð3:63Þ
After joining the nodes:
By following the same procedure that was used in the proof of Theorem 3.1, the
following results are obtained:
– Equalizing Eqs. (3.58) and (3.61) yields: J = Ax
– Equalizing Eqs. (3.59) and (3.62) yields: D + a Ax = Bx + a By.
Therefore, D = 2a Ax + Bx + a By
– Equalizing Eqs. (3.60) and (3.63) yields: a E + a2 Ax = a Cy + a2 Cz.
Therefore, E = 2a Ax + Cy + a Cz
Q.E.D.
Definition 3.9 The function of the joining node J of any ternary Davio0 (D0)
decomposition is the same function of the x-axis cofactor Ax. Therefore,
J ¼ Ax
¼ 1 Jx þ a Jy þ a2 Jz
ð3:64Þ
Theorem 3.3 For a lattice circuit with all ternary Davio1 (D1) nodes, the following
is the possible set of joining rule, and correction functions, respectively:
3.5 Reversible Lattice Circuits
43
J ¼ Ax
ð3:65Þ
D ¼ 2a0 Ax þ Bx þ a0 By
ð3:66Þ
E ¼ 2a0 Ax þ Cy þ a0 Cz
ð3:67Þ
Proof The proof of Theorem 3.3 follows the same methodology that is used to
prove Theorem 3.2.
Theorem 3.4 For a lattice circuit with all ternary Davio2 (D2) nodes, the following
is the possible set of joining rule, and correction functions, respectively:
J ¼ Ax
ð3:68Þ
D ¼ 2a00 Ax þ Bx þ a00 By
ð3:69Þ
E ¼ 2a00 Ax þ Cy þ a00 Cz
ð3:70Þ
Proof The proof of Theorem 3.4 follows the same methodology that is used to
prove Theorem 3.2.
If the ternary function is symmetric then there is no need to repeat variable(s) to
realize the function in 3D lattice circuit, otherwise there is a need to repeat variable
(s) and thus the need to use Theorems (3.1)–(3.4).
3.5.4
Algorithms for Realizing the Shannon/Davio
Expansions of Ternary Functions into 3D Lattice
Circuits
3.5.4.1
An Algorithm for the Shannon Expansion
Table 3.5 shows an algorithm for realizing Shannon expansion of ternary functions
in 3D lattice circuits using the joining method that was proposed in Theorem 3.1.
This algorithm is a modified version to that given in [3, 8], it produces simpler
circuits.
The algorithm is developed as follows: in the octant (sub-space) that corresponds
to the positive x-axis, positive y-axis, and positive z-axis expand the nodes in-to-out
and join the cofactors.
The following sections are new algorithms for various types of expansions.
44
3 Methods of Reversible Logic Synthesis
Table 3.5 An algorithm for realizing ternary Shannon expansion of ternary functions in 3D lattice
circuits
{ for i = j = k = 0
Utilizing equation (3.5) Expand n(i, j, k) into n(i+1, j, k) , n(i, j+1, k) , n(i, j, k+1)
if all nodes are constants
then go to 4
else (
1.
Utilizing equation (3.5)
i = i ++: Expand n(i, j, k) into n(i+1, j, k) , n(i, j+1, k) , n(i, j, k+1)
j = j ++: Expand n(i, j, k) into n(i+1, j, k) , n(i, j+1, k) , n(i, j, k+1)
k = k ++: Expand n(i, j, k) into n(i+1, j, k) , n(i, j+1, k) , n(i, j, k+1)
if all nodes are constants with no conflicting values in the
common indices nodes (CINs)
then go to 4
else go to 2
2.
if all the CINs are constants with no conflicting values
then go to 3
else ( Utilizing equation (3.47)
Join nodes with common indices
if three nodes exist
then ( apply equation (3.47) )
else ( set the non-existing nodes to zero
apply equation (3.47) )
)
go to 3
3.5 Reversible Lattice Circuits
3.
45
for each non-constant node ( Utilizing equation (3.5)
// for x, y, and z as general positional indices that can be
expressed in terms of i, j, and k, respectively //.
Expand n(x, y, z) into n(x+1, y, z) , n(x, y+1, z) , n(x, y, z+1)
)
if all nodes are constants with no conflicting values in the CINs
then go to 4
else go to 1 )
4.
3.5.4.2
end }
An Algorithm for the Davio0 Expansion
Table 3.6 shows an algorithm for realizing ternary Davio0 expansion of ternary
functions in 3D lattice circuits using the joining method that was proposed in
Theorem 3.2. This algorithm is developed in a similar manner to that of Table 3.5.
However, the joining of the cofactors is made counter clock wise (CCW). Similar
algorithms can be developed for other Davio expansions (e.g. Davio1 and Davio2 in
Theorems 3.3 and 3.4) as well.
3.5.4.3
New Algorithms for the Shannon/Davio Hybrid Expansions
As mentioned in Sect. 3.5.2, the expansion types that are used in the realization of
the internal nodes have important effects on the size of a lattice circuit. Thus, in this
Section new algorithms are proposed to use hybrid expansions (i.e., two different
types of expansions) rather than using a single type of expansion for the entire 3D
lattice circuit (as in Sects. 3.5.4.1 and 3.5.4.2). The idea is to use a certain type of
expansion to realize the initial node (the root) only. While the successive node
expansions are all of a different type. The following equations are required to
convert expansions from Davio0 to Shannon:
1 ¼ 0x þ 1x þ 2x
ð3:71Þ
x ¼ 1x þ 2 2x
ð3:72Þ
46
3 Methods of Reversible Logic Synthesis
Table 3.6 An algorithm for realizing ternary Davio0 expansion of ternary functions in 3D lattice
circuits
3.5 Reversible Lattice Circuits
47
ðxÞ2 ¼ 1 x þ 2 x
ð3:73Þ
While the Eqs. (3.6), (3.9) and (3.12) are used to convert expansions from
Shannon to Davio0.
To convert expansions from Davio1 to Shannon, the following equations are
used:
1 ¼ 0x þ 1x þ 2x
ð3:74Þ
x0 ¼ 0 x þ 2 1 x
ð3:75Þ
ðx0 Þ2 ¼ 0 x þ 1 x
ð3:76Þ
While the Eqs. (3.7), (3.10) and (3.13) are used to convert expansions from
Shannon to Davio1.
To convert expansions from Davio2 to Shannon, the following equations are
used:
1 ¼ 0x þ 1x þ 2x
ð3:77Þ
x00 ¼ 2 x þ 2 0 x
ð3:78Þ
ðx00 Þ2 ¼ 0 x þ 2 x
ð3:79Þ
While the Eqs. (3.8), (3.11) and (3.14) are used to convert expansions from
Shannon to Davio2.
48
3 Methods of Reversible Logic Synthesis
Table 3.7 New algorithm for realizing ternary S/D0 expansion of ternary functions in 3D lattice
circuits
{ for i = j = k = 0
Utilizing equation (3.5) Expand n(i, j, k) into n(i+1, j, k) , n(i, j+1, k) , n(i, j, k+1)
if all nodes are constants
then go to 4
else ( Utilizing equations (3.6), (3.9) and (3.12)
convert all nodes to Davio0 expansion form
go to 1
1.
.........
2.
.........
3.
.........
4.
end }
The same items in Table 3.6
Table 3.7 shows a new algorithm for realizing ternary Shannon/Davio0 (S/D0)
expansion of ternary functions in 3D lattice circuits. Here, the Shannon expansion is
used to realize the root node, while the Davio0 expansion is used to realize the other
nodes of the 3D lattice circuit.
Table 3.8 shows a new algorithm for realizing ternary Davio0/Shannon (D0/S)
expansion of ternary functions in 3D lattice circuits. In this hybrid expansion, the
Davio0 expansion is used to realize the root node, while the Shannon expansion is
used in realizing the other nodes of the 3D lattice circuit.
By following the same methodology that is used in Tables (3.7) and (3.8),
algorithms for hybrid expansions S/D1, S/D2, D1/S, and D2/S can be proposed.
3.5.5
Complete Example for the Implementation of Ternary
Functions Using 3D Lattice Circuits
For the following non-symmetric ternary function F in Table 3.9, utilizing the
algorithms for expansions and the joining rules given in the previous sections, the
following 3D lattice circuits are obtained.
(a) Realization of F using Shannon expansion
The function F in Table 3.9 is written as:
F ¼ 0a 0b þ 2 0a 1b þ 2 0a 2b þ 1a 2b
þ 2a 0b þ 2 2a 1b þ 2 2a 2b
ð3:80Þ
3.5 Reversible Lattice Circuits
49
Table 3.8 New algorithm for realizing ternary D0/S expansion of ternary functions in 3D lattice
circuits
{ for i = j = k = 0
Utilizing equation (3.15) Expand n(i, j, k) into n(i+1, j, k) , n(i, j+1, k) , n(i, j, k+1)
if all nodes are constants
then go to 4
else ( Utilizing equations (3.71), (3.72) and (3.73)
convert all nodes to Shannon expansion form
1
go to 1
.........
2
.........
3
.........
4
end }
The same items in Table 3.5
Table 3.9 Ternary map for
the function F
a
0
1
2
2
2
1
0
0
1
2
1
2
2
Figure 3.17 shows the different steps that are applied to obtain the 3D lattice
circuit in Fig. 3.18.
Step 1: Expanding nodes.
Expand the non-symmetric function F in the root node (0, 0, 0) according to
Eq. (3.5), as follows:
F0 ¼ Fða ¼ 0Þ ¼ 0 b þ 2 1 b þ 2 2 b into node ð1; 0; 0Þ;
F1 ¼ Fða ¼ 1Þ ¼ 2 b into node ð0; 1; 0Þ;
F2 ¼ Fða ¼ 2Þ ¼ 0 b þ 2 1 b þ 2 2 b into node ð0; 0; 1Þ:
For simplicity, the nodes in Fig. 3.17 are enumerated. So, the above nodes (1, 0, 0),
(0, 1, 0) and (0, 0, 1) are the nodes 1, 2 and 3, respectively, in Fig. 3.17. The three
nodes are not constant value.
50
3 Methods of Reversible Logic Synthesis
z
12
18
2
1
2
y
2
b
b
0
21
x
2
b
0
b
10
1
6, 10
b
11
b
0
2
0
1
3
a
b
2
b
0
1
b
9
b
2
20
b
15
1
2
a
b
2
a
0
1
8
b
b
7
1
0
1
b
1
5, 7
5
0
b
b
14
b
13
4
Fig. 3.17 3D Shannon lattice circuit for the realization of the function F
z
2
2
1
2
y
1
0
2
0
x
0
2
2
F
2
1
0
1
1
2
0
1
0
17
16
F
19
9, 11
1
0
1
0
Fig. 3.18 3D Shannon lattice circuit for the realization of the non-symmetric function F
3.5 Reversible Lattice Circuits
51
Step 2: Expanding nodes.
Expand the lattice circuit nodes that result from step 1, as follows:
node 1 into: node 4 of value 1, node 5 of value 2, node 6 of value 2
node 2 into: node 7 of value 0, node 8 of value 0, node 9 of value 1
node 3 into: node 10 of value 1, node 11 of value 2, node 12 of value 2
Conflicting values occur in the common indices nodes (CINs) as:
9 6¼ 11; 6 6¼ 10
and
5 6¼ 7:
Step 3: Joining nodes.
As a result from step 2, join the cofactors of the CINs according to Eq. (3.47) as
follows:
Joining nodes 9 and 11
Joining nodes 6 and 10
Joining nodes 5 and 7
Ax = 0 (not exist)
By = 2 (node 11)
Cz = 1 (node 9)
node (9, 11): J = 2 1b + 2b
Ax = 1 (node 10)
By = 0 (not exist)
Cz = 2 (node 6)
node (6, 10): J = 0b + 2 2b
Ax = 0 (node 7)
By = 2 (node 5)
Cz = 0 (not exist)
node (5, 7): J = 2 1b
Step 4: Expanding nodes.
Expand the lattice circuit nodes that result from step 3, as follows:
node (5, 7) into: node 13 of value 0, node 14 of value 2, node 15 of value 0
node(9, 11)into: node 16 of value 0, node 17 of value 2, node 18 of value 1
node(6, 10)into: node 19 of value 1, node 20 of value 0, node 21 of value 2
Step 5: End.
The synthesis is completed, since all the nodes that result from step 4 are
constants with no conflicting values in the CINs, as: 15 = 16 = 20 (all of value 0).
Therefore, the node (15, 16, 20) or node (1, 1, 1) is a leaf node of value 0. All other
nodes of constant values are leaf nodes. Figure 3.18 represents the final 3D
Shannon lattice circuit for realization of non-symmetric function F in Table 3.9. It is
obvious that the variable b is necessary to be repeated in order to realize F. The
circuit contains seven nodes, and ten leaves. Three of the leaves are of value 0, three
leaves are of value 1 and four leaves are of value 2.
(b) Realization of F using Davio0expansion
Equation (3.80) is converted from Shannon form to Davio0 form by using the
Eqs. (3.6), (3.9) and (3.12). It becomes
52
3 Methods of Reversible Logic Synthesis
F ¼ 1 þ a þ 2 a b þ 2 a b2 þ a 2 þ 2 a 2 b þ b2 þ 2 a 2 b2
ð3:81Þ
The different steps applied to obtain the 3D lattice circuit in Fig. 3.19 are as
follows (with the nodes enumerated as in Fig. 3.17):
F = 1 + a + 2 a b + 2 a b2 + a2 + 2 a2 b + b2 + 2 a2 b2
Step 1 : Expanding nodes
CINs:
5
≠
node 2 :1+2b+2b2
2
Step 2 : Expanding 1 b
a2
a
1 :1+b2
node
nodes
1
b
1 b
b
1
4 :1 5 :0
6 :1 7 :1 8 :2 9 :2
7 ,
11
,
5 and
7
9 =
Step 3 : Joining nodes
Ax =
7 =1
By =
5 =0
6 =
node 3 :1+2b+2b2
2
10
b
:1 11
b2
:2 12
:2
10
Cz = 0 (not exist)
According to Equations (3.55), (3.56) and (3.57), the followings are obtained
node
5,7
: J=1
node
4 : D = 1 + 2b
Step 4 : Expanding node
22
Where, node
22
4 : 1 + 2b
1
b
b2
:1
13
:2
19
:0
is the node n(3, 0, 0) not shown in Fig.3.17, while all other
nodes are as shown in Fig.3.17.
Step 5 : End
The 3D Davio0 lattice circuit for the realization of the non-symmetric function F
is shown in Fig. 3.19. The circuit contains five nodes and eight leaves. One leaf is
of value 0, three leaves are of value 1, and four leaves are of value 2.
By following the same procedure in realizing F using Davio0, it is possible to
make realizations of F using Davio1 and Davio2. The following is the realization of
F using the hybrid (S/D0) expansion.
3.5 Reversible Lattice Circuits
53
(c) Realization of F using S/D0 expansions
F = 0a 0b + 2 0a 1b + 2 0a 2b + 1a 2b + 2a 0b + 2 2a 1b + 2 2a 2b
0
Step 1 : Expanding (S)
0
1
a
1
2
2
a
2
a
0
: b +2 1b +2 2b
1
: b +2 b +2 b
2
: b
1
: 1 + b2
2
: 2 b2 + b
3
: 1 + b2
1
b
3
Step 2 : Conversion to
(D0) using Equations
(3.6),(3.9) and (3.12).
Step 3 : Expanding (D0) 1 b b2
4 :1
CINs:
5
5 :0
7 ,
=
9
Step 4 : Joining
6 :1
6
=
and
11
1
b
b2
7 :0
8
:1
9 :2
,
9
≠
11
10
10
:1
b2
11
:0
12
:1
Ax = 0 (not exist)
By =
11
Cz =
9
=0
= 2
According to Equations (3.55), (3.56) and (3.57), the followings are obtained:
node
9,11
: J =0
node
10
: D = 1
node
8
: E=1+ 2b
Step 5: Expanding node
8
:
14
Where, node
23
1+2b
1
b
:1
23
b2
:2
17
:0
is the node n(0, 3, 0) not shown in Fig.3.17, while all other nodes are as
shown in Fig.3.17.
Step 6: End
The 3D (S/D0) hybrid expansions lattice circuit for the realization of the
non-symmetric function F is shown in Fig. 3.20. The circuit contains five nodes and
eight leaves. Three leaves are of value 0, four leaves are of value 1, and one leaf is
of value 2.
54
3 Methods of Reversible Logic Synthesis
z
v2
b2
v
y
b
b
1
1
a2
x
b2
2
1
b
b
b
1
a
1
b2
a
b
b
b
b
1
Fig. 3.19 3D Davio0 lattice circuit for the realization of the function F
Similarly, the other hybrid expansions lattice circuits for the realization of F are
synthesized. The results of all the expansion types’ lattice circuits to realize F are
summarized in Table 3.10.
When considering power consumption, the value “0” represents ground and thus
does not need to be supplied from a power supply (i.e., theoretically needs zero
power), in contrast to value “1” and value “2” that are obtained from a power
supply and thus consume power. However, the power consumed for the value “2” is
twice that of the value “1”. If the power consumed for the value “1” is considered as
one unit, and that consumed for the value “2” as two units, then Table 3.10 can be
derived for the size (number of gates) and power-consumption comparison between
the different types of lattice realizations. The product of the size with the
power-consumption will be considered as an important factor for best choice
z
b2
y
b
x
b
1
2
b
1
0
1
b
b2
a
2
a
a
a
1
b
b2
b
1
b
Fig. 3.20 3D (S/D0) lattice circuit for the realization of the function F
b
b
3.5 Reversible Lattice Circuits
55
Table 3.10 Size/power-consumption based comparison between the lattice realizations for the
non-symmetric function F
Parameter
Number of internal nodes
(size)
Number of leaves
Number of 0-valued leaves
Number of 1-valued leaves
Number of 2-valued leaves
Units of power-consumption
SPP
Order of best (optimal)
choices
Type of expansion
S
D0 D1 D2
S/D0
S/D1
S/D2
D0/
S
D1/
S
D2/
S
7
5
5
3
5
7
5
6
5
3
10
3
3
4
11
77
8
8
1
3
4
11
55
5
8
1
2
5
12
60
6
6
3
0
3
6
18
2
8
3
4
1
6
30
3
11
4
3
4
11
77
8
8
1
1
6
13
65
7
9
1
3
5
13
78
9
8
1
4
3
10
50
4
6
3
2
1
4
12
1
(optimal selection) of the type of expansion. Here, the size power- consumption
product (SPP) factor is presented as a new method for optimal selection of the type
of expansion. The (SPP) factor should be as minimal as possible to obtain a small
size circuit with minimum power consumption. It is obvious, from Table 3.10 that
the best optimal choice to realize the circuit is the hybrid (D2/S) expansion. That
clarifies the importance of the new hybrid expansions introduced in this book.
3.5.6
New Minimal Realization Method
for 3D Lattice Circuits
In the previous Sect. (3.5.5), it was seen how the type of expansion used in the
internal nodes had effect on the size of the lattice. Another important factor that
controls the size of the lattice is the order of control variables. In the example of
Sect. (3.5.5), the function F is a function of two variables (a and b). The variable a
was first applied to synthesize the lattice circuit. However, if the variable b is
applied first, the size of the lattice may be changed. Thus the synthesis is repeated
with variable b is applied first. The new results are shown in Table 3.11 under the
column b, as well as the previous results of Table 3.10 under the column a. It is
noticed that, the new order of the variables give better results (i.e., smaller values of
SPP) in the expansion types of D0, D1, S/D1, S/D2, and D0/S.
In Table 3.11, for each type of expansion there are two values of SPP, one in the
column a and the other in the column b. The larger value of SPP is denoted as
SPP1, while the smaller value as SPP2. The rational value of SPP is denoted RSPP
and defined as:
5
8
1
3
4
11
55
1.22
5
8
2
3
3
9
45
7
10
3
3
4
11
77
1
Number of nodes (size)
Number of leaves
Number of 0-valued leaves
Number of 1-valued leaves
Number of 2-valued leaves
Units of power-consumption
SPP
RSPP
7
10
3
3
4
11
77
Type of expansion
S
D0
a
b
a
b
Parameter
5
8
1
2
5
12
60
1.2
D1
a
5
8
1
4
3
10
50
b
3
6
3
0
3
6
18
1
D2
a
3
6
3
0
3
6
18
b
5
8
3
4
1
6
30
2.8
7
11
3
4
4
12
84
S/D0
a
b
7
11
4
3
4
11
77
1.4
5
8
1
3
4
11
55
S/D1
a
b
Table 3.11 Results of 3D lattice circuit realizations of F with different order of the control variables
5
8
1
1
6
13
65
≅1
8
13
7
4
2
8
64
S/D2
a
b
6
9
1
3
5
13
78
2.6
5
8
3
4
1
6
30
D0/S
a
b
5
8
1
4
3
10
50
1.2
6
9
2
4
3
10
60
D1/S
a
b
3
6
3
2
1
4
12
3.3
4
8
2
2
4
10
40
D2/S
a
b
56
3 Methods of Reversible Logic Synthesis
3.5 Reversible Lattice Circuits
57
RSPP ¼ SPP1=SPP2:
It is seen from Table 3.11 that for the values of RSPP less than 1.25, the two
lattice circuits (case a and case b) are approximately equivalent.
According to all of the above notes, the following is a new method for minimal
realization of 3D lattice circuits.
New method for minimal realization of 3D lattice circuits
For a ternary function F of two variables a and b; let N1 be the number of the
function terms containing the variable a only, and let N2 be the number of
terms containing the variable b only.
1. If the function is symmetric, then whichever is the order of control
variables and the types of expansion (decomposition) in internal nodes,
equivalent lattice circuits will be obtained.
2. For non-symmetric functions:
(a) If Shannon decomposition is used (N1 = N2 = 0, in this case), then
whichever is the order of the control variables, equivalent lattice circuits will be obtained (i.e., RSPP = 1).
(b) If one of the Davio decompositions (D0, or D1, or D2) is used, then
apply the following guidelines:
• If N1 = N2 = 0, then whichever is the order of the control variables,
equivalent lattice circuits will be obtained (i.e., RSPP = 1).
• If N1 > 0 and N2 = 0, then starting with the control variable
(a) gives minimum SPP value (i.e., RSPP > 1.25).
• If N2 > 0 and N1 = 0, then starting with the control variable
(b) gives minimum SPP value (i.e., RSPP > 1.25).
• If N1 > 0 and N2 > 0, then whichever is the order of the control
variables, approximately equivalent lattice circuits will be obtained
(i.e., RSPP < 1.25).
c. If hybrid S/D or D/S decompositions are used, then the RSPP value
should be determined for each case and then deciding the order of the
control variables.
To test the above method, it will be applied to the function F of Table 3.11. At
first, the four forms of F (i.e., S, D0, D1 and D2) are written,
58
3 Methods of Reversible Logic Synthesis
FS ¼ 0 a 0 b þ 2 0 a 1 b þ 2 0 a 2 b þ 1 a 2 b þ 2 a 0 b þ 2 2 a 1 b þ 2 2 a 2 b
FD0 ¼ 1 þ a þ 2 a b þ 2 a b2 þ a2 þ 2 a2 b þ b2 þ 2 a2 b2
FD1 ¼ 2 þ 2ða0 Þ ðb0 Þ þ ða0 Þ b0 þ a0 ðb0 Þ þ 2 a0 b0 þ ða0 Þ þ 2 a0 þ ðb0 Þ þ b0
2
2
2
2
2
2
FD2 ¼ 2ða00 Þ ðb00 Þ þ 2ða00 Þ þ 2ðb00 Þ þ 2 b00
2
•
•
•
•
2
2
2
For (FS): N1 = N2 = 0, and RSPP = 1.
For (FD0): N1 = 2, N2 = 1, and RSPP < 1.25.
For (FD1): N1 = 2, N2 = 2, and RSPP < 1.25.
For (FD2): N1 = 1, N2 = 2, and RSPP < 1.25.
Another example to show other cases of the new optimization method (that are
not appeared in the above example) is to consider the non-symmetric ternary
function G in Table 3.12.
Table 3.13 shows the results of 3D lattice circuit realizations of G with different
order of the control variables.
The four forms of G are written below:
GS ¼ 2 0 a 0 b þ 0 a 1 b þ 0 a 2 b þ 2 1 a 0 b þ 1 a 1 b þ 1 a 2 b þ 2 2 a 0 b þ 2 2 a 1 b þ 2 2 a 2 b
GD0 ¼ 2 þ a b2 þ 2 a2 b2 þ 2 b2
GD1 ¼ 2 þ 2 ða0 Þ ðb0 Þ þ 2 ða0 Þ b0 þ 2ða0 Þ
2
2
2
2
GD2 ¼ 1 þ 2ða00 Þ ðb00 Þ þ ða00 Þ b00 þ 2 a00 ðb00 Þ þ a00 b00 þ 2 ða00 Þ þ 2 a00 þ 2 ðb00 Þ þ b00
2
•
•
•
•
2
2
2
2
2
For (GS): N1 = N2 = 0, and RSPP = 1.
For (GD0): N1 = 0, N2 = 1, RSPP > 1.25 with b applied first.
For (GD1): N1 = 1, N2 = 0, RSPP > 1.25 with a applied first.
For (GD2): N1 = 2, N2 = 2, and RSPP < 1.25.
The new minimal realization method can be generalized for functions with more
than two variables, by considering the most two dominant variables of the function
as a and b in the minimal realization method, while the other variables are regarded
as constants. Then repeat for the next two dominant variables, and so on.
Table 3.12 Ternary map for
the function G
b
a
0
0
1
2
2
1
1
1
2
1
1
2
2
2
2
6
10
6
1
3
7
42
3
2
5
1
1
3
7
14
7
10
1
4
5
14
98
1
Number of nodes (size)
Number of leaves
Number of 0-valued leaves
Number of 1-valued leaves
Number of 2-valued leaves
Units of power-consumption
SPP
RSPP
7
10
1
4
5
14
98
Type of expansion
S
D0
a
b
a
b
Parameter
2
5
1
0
4
8
16
3
D1
a
6
10
6
0
4
8
48
b
8
13
4
5
4
13
104
1
D2
a
8
13
4
5
4
13
104
b
4
8
2
1
5
11
44
1.13
5
10
3
4
3
10
50
S/D0
a
b
4
8
1
3
4
11
44
1.1
4
8
3
0
5
10
40
S/D1
a
b
Table 3.13 Results of 3D lattice circuit realizations of G with different order of the control variables
3
6
0
3
3
9
27
1.1
3
6
0
2
4
10
30
S/D2
a
b
7
10
3
4
3
10
70
≅6
2
5
2
0
3
6
12
D0/S
a
b
2
5
2
0
3
6
12
5
6
9
3
2
4
10
60
D1/S
a
b
6
7
9
10
3
3
2
4
4
3
10 10
60 70
1.166
D2/S
a
b
3.5 Reversible Lattice Circuits
59
60
3.5.7
3 Methods of Reversible Logic Synthesis
Lattice Circuit Synthesis Using ISID
In many cases, it is needed to repeat variables so many times (in order to realize
non-symmetric functions) that will result in a big size lattice circuit. Hence, it is
possible that the circuit does not fit the specified area (or volume in the case of 3D
lattice circuits). In such cases, it is required to re-route interconnects between the
internal nodes of the lattice circuit in a way such that the structure will ultimately fit
into the specified layout space [12]. However, this process has a disadvantage of
causing interconnects between cells to be of different lengths, and consequently the
lattice circuit will lose one of its important features; all interconnects are of equal
length. Moreover, that will increase the delay and power consumed of the circuit.
About 40–50 % or more of the total delay associated with a circuit is caused by the
delay of interconnects. The idea of maintaining interconnects of equal length for a
large size lattice circuit that does not fit specific layout boundaries can be achieved
using Iterative Symmetry Indices Decomposition (ISID) instead of repeating variables. The ISID method is applied only if repeating variables will force the lattice
circuit to grow out of the layout boundaries.
In the ISID method, the non-symmetric function is decomposed into a symmetric
part superimposed with an error part [3, 12]. The error part can be alternatively
named as the correction part. The original function is equal to the EXOR () or the
Equivalence () of the two decomposed functions. Then the symmetric part is
synthesized using a lattice circuit. If the synthesis fits layout boundaries then the
error function is synthesized. Otherwise, either a single decomposition of the
symmetric or error sub-functions is performed (serial-mode), or a
multi-decomposition on all symmetric and error sub-functions is performed
(parallel-mode). This procedure is repeated until the synthesis fits the layout
boundaries.
Figure 3.21 illustrates the realization of a binary non-symmetric function F using
—ISID Shannon lattice circuit. While Fig. 3.22 shows the realization of F using
—ISID Shannon lattice circuit.
The same idea of 2D-ISID can be used for 3D-ISID by using the algebraic
equations over GF(3) to decompose the corresponding ternary maps.
3.5.8
The Creation of Reversible Lattice Structures
A general procedure for the construction of a reversible Shannon lattice circuit over
nth radix logic is as follows [3, 6]:
Synthesis stage:
1. Utilizing a reversible Shannon primitive (from Sect. 3.1.2), assign the
multi-valued map of the function that is needed to be realized in the reversible
lattice circuit for one output of the reversible Shannon primitive in the first level,
and assign don’t care maps for the rest of the primitive outputs at the first level.
3.5 Reversible Lattice Circuits
61
c
ab
0
1
0
00 0 S
1 S1
01 0 S1
0 S2
11 0 S2
0 S3
10 1 S1
1 S2
c
F
c
ab
0
1
ab
00
0
0 S
1
1 S
01
1 S1
11
10
0
1
00
0
0 S
0 S1
1 S2
01
1 S1
1 S2
1 S2
0 S3
11
1 S2
0
1 S1
1 S2
10
0 S1
0 S2
F1
S3
F2
F
F2
F1
a
0
1
b
0
1
0
1
c
0
S0
1
0
0
S1
1
1
0
S2
0
1
S3
0
Fig. 3.21 ⊕—ISID Shannon lattice circuit [3]
Also assign don’t care maps to the garbage outputs of the primitives in each
level of the reversible lattice structure.
2. Following the output-to-input paths and using the reverse of the method of
permutation of cofactors from Sect. 3.1.2 (e.g., constructing inputs from outputs
in Fig. 3.2 for instance), construct new maps at the input of the reversible
62
3 Methods of Reversible Logic Synthesis
c
ab
0
1
0
00 0 S
1 S1
01 0 S1
0 S2
11 0 S2
0 S3
1
1 S2
10 1 S
c
F
c
ab
0
1
ab
00
0
0 S
1
1 S
01
1 S1
11
10
0
1
00
0
1 S
1
S1
1 S2
01
0 S1
0
S2
1 S2
0 S3
11
0 S2
1
S3
1 S1
1 S2
10
1 S1
1
S2
F1
F2
F
F2
F1
a
0
1
b
0
1
0
1
c
0
S0
1
0
0
S1
1
1
S2
0
1
S3
1
0
Fig. 3.22 ⊗—ISID Shannon lattice circuit [3]
Shannon primitive by permuting the output cofactors (in the output maps) that
correspond to the expansion variable in the first level. Thus, the contents of the
input maps will result from the permutation of the values of the cofactors in
maps at the output of the same reversible Shannon primitives at the first level.
3. Going from top-to-bottom and left-to-right in the reversible lattice circuit, repeat
step 2 for each expansion variable in each level until the reach of maps at the
3.5 Reversible Lattice Circuits
63
bottom of the reversible lattice circuit having only a constant value from the set
{0, 1, 2}.
Analysis stage: An opposite process to the synthesis.
4. Following the input-to-output paths of the reversible Shannon primitives at the
last level of the reversible lattice structure, going from inputs-to-outputs, and
using the forward method of permutation of cofactors from Sect. 3.1.2, construct
new maps at the output of the reversible Shannon primitives by permuting the
input cofactors (in the input maps) that correspond to the expansion variable in
the last level.
5. Going from bottom-to-top and right-to-left of the reversible lattice structure,
repeat step 4 for each expansion variable in each level until one reaches completely specified maps, in all wires throughout the reversible lattice structure
from bottom-to-top and right-to-left, with no don’t cares.
The following example illustrates the concept of reversible lattice structure.
Example 3.1 Figures 3.23 and 3.24 illustrate the synthesis and analysis stages,
respectively, for realizing the Boolean function F using reversible lattice circuit (the
(−) sign indicates don’t care). The garbage outputs (that are necessary only for
reversibility) are denoted as G1–G5.
The function in Example 3.1 is totally symmetric, and it is realized without
variable repetition. But, that is not always the case in reversible lattice synthesis. In
some cases, there is a need to repeat variables in realizing reversible lattice synthesis of symmetric binary functions. In previous literatures there are no methods to
decide in which cases there is a need to repeat variables. The following is a new rule
for the realization of symmetrical binary functions in reversible lattice circuits. (To
realize a binary symmetric function of n variables using reversible lattice circuits
and without the need to repeat variables, it is necessary that the symmetry indices
of the function S1, S2… Sn−1are all of the same value.)
For example, the function F in Fig. 3.23, is a function of three variables with the
symmetry indices S1 = S2 = 1. Therefore, the conditions in the above rule are
satisfied, and consequently the lattice circuit was realized without the need to repeat
variables.
Example 3.2 Figure 3.25 illustrates the creation of the reversible ternary lattice
circuit for the ternary function (T) using the reversible Shannon gate from Fig. 3.5.
In some cases, there is a need to repeat variables when realizing symmetric
ternary functions using reversible lattice circuits. The following is a new rule for the
realization of symmetrical ternary functions in reversible lattice circuits:
(To realize a ternary symmetric function of n variables using reversible lattice
circuits and without the need to repeat variables, it is necessary that the symmetry
indices of the function (Si,j) are all of the same value, for i and j = 0, 1, …, n − 1).
The reason of assigning these symmetry indices, in both rules of the binary and
ternary cases, is that these symmetry indices of the function will be exist in the CIN
nodes and they should be of equal values to avoid the need to repeat variables.
64
3 Methods of Reversible Logic Synthesis
bc
a
bc
00 01 11 10
0 0
1
1
1
1 1
1
0
1
a
F
00 01 11 10
0 -
-
-
-
1 -
-
-
-
G3
a
a
0
1
0
1
G2
G4
-
-
-
-
0
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
0
1
-
-
-
-
0
1
0
1
b
b
0
1
0
1
G1
G5
-
-
-
-
0
1
-
-
-
-
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
-
-
-
-
-
-
-
0
-
-
-
-
-
1
-
-
-
-
CINs
c
0
1
0
1
0
1
0
1
0
1
0
c
1
0
-
-
-
-
1
-
-
-
-
-
1
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
1
-
-
-
-
-
-
1
-
-
0
-
Fig. 3.23 The synthesis stage of realizing 2D binary reversible lattice structure for the function F
in Example 3.1
3.5.9
3D Ternary Davio Reversible Lattice Structures
In this sub-Section, a new algorithm is introduced for 3D synthesis of ternary Davio
reversible lattice (3DTDRL) logic circuits. In Table 3.6, an algorithm for realizing
ternary Davio0 expansion of ternary functions in 3D lattice circuits is presented.
That algorithm as well as the ideas of constructing reversible lattice circuits
(described in Sect. 3.5.8) are combined together to develop the new algorithm.
The three Davio0 expansion Eqs. (3.31, 3.32, and 3.33) are rewritten below,
respectively, for an expansion variable (a) of a function F to be synthesized in a 3D
reversible lattice circuit.
3.5 Reversible Lattice Circuits
65
bc
bc
a
00 01 11 10
0 0
1
1
1
1 1
1
0
1
a
F
00 01 11 10
0 1
1
0
1
1 0
1
1
1 G3
a
a
0
1
0
1
G2
G4
1
1
1
0
0
1
1
1
1
1
0 1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
0 1
1
0
1
1
0
1
0
1
0
1
b
b
0
1
G1
G5
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
0
c
0
1
0
1
0
1
0
0
1
1
0
c
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Fig. 3.24 The analysis stage of realizing 2D binary reversible lattice structure for the function F in
Example 3.1
f r0 ¼ 1 f 0 þ að2 f 1 þ f 2 Þ þ a2 ð2 f 0 þ 2 f 1 þ 2 f 2 Þ
ð3:82Þ
f r1 ¼ 1 f 2 þ að2 f 0 þ f 1 Þ þ a2 ð2 f 0 þ 2 f 1 þ 2 f 2 Þ
ð3:83Þ
f r2 ¼ 1 f 1 þ að2 f 2 þ f 0 Þ þ a2 ð2f 0 þ 2 f 1 þ 2 f 2 Þ
ð3:84Þ
The x-axis cofactor of fr0 is denoted as (fr0)x, while (fr0)y and (fr0)z represent the
y-axis and z-axis cofactors of fr0, respectively. From Eq. (3.82), it is obtained that:
ðf r0 Þx ¼ f 0
ðf r0 Þy ¼ 2 f 1 þ f 2
ðf r0 Þz ¼ 2 f 0 þ 2 f 1 þ 2 f 2
66
3 Methods of Reversible Logic Synthesis
b
a
G4
1
2
2
1
0
0
1
2
0
1
2
b
2
1
0
2
a
0
1
2
0
1
2
0
T
1
2
1
2
b
2
0
2
1
a
0
1
2
a
G1
G2
G3
1 0 2
1 0 2
1 0 2
2 1 0
2 1 0
2 1 0
0 1 2
0 1 2
0 1 2
G5
1
1
2
2
0
2
0
1
2
2
1
0
a
0 2 1
0 2 1
0 2 1
1 2 0
1 2 0
1 2 0
2 1 2
2 1 2
2 1 2
G6
G7
G8
2 0 1
2 0 1
2 0 1
2 2 1
2 2 1
2 2 1
1 2 2
1 2 2
1 2 2
b
b
1 1 1
1 1 1
1 1 1
0 0 0
0 0 0
0 0 0
2 2 2
2 2 2
2 2 2
0 0 0
0 0 0
0 0 0
1 1 1
1 1 1
1 1 1
2 2 2
2 2 2
2 2 2
2 2 2
2 2 2
2 2 2
2 2 2
2 2 2
2 2 2
1 1 1
1 1 1
1 1 1
Fig. 3.25 The synthesis and analysis stages for the realization of the ternary function (T) in
Example 3.2 [3]
Using the GF(3) addition, described in Fig. 3.1c, then:
f 1 ¼ ðf r0 Þx þ ðf r0 Þy þ ðf r0 Þz
and;
f 2 ¼ ðf r0 Þx þ 2ðf r0 Þy þ ðf r0 Þz ¼ f 1 þ ðf r0 Þy
It is clear, from Eqs. (3.82)–(3.84) that:
f r0 ða ¼ 0Þ ¼ f 0 ;
f r1 ða ¼ 0Þ ¼ f 2 ;
f r0 ða ¼ 1Þ ¼ f 1 ;
f r1 ða ¼ 1Þ ¼ f 0 ;
f r0 ða ¼ 2Þ ¼ f 2
f r1 ða ¼ 2Þ ¼ f 1
f r2 ða ¼ 0Þ ¼ f 1 ;
f r2 ða ¼ 1Þ ¼ f 2 ;
f r2 ða ¼ 2Þ ¼ f 0
From the above equations, the design of the root node of the 3D reversible lattice
is accomplished as shown in Fig. 3.26. In order to be uniform, each node of the
3DTDRL structure has the same internal connection of Fig. 3.26b. Each node to be
expanded has the same position at the output of each primitive for every level, in
Fig. 3.26b the position of the function to be expanded is in the middle and the
cofactors are organized as shown. For simplicity, the 3DTDRL circuits described in
this sub-Section are all drawn using the irreversible vertex (node) in Fig. 3.26a, but
the internal connection is as in Fig. 3.26b.
The following is the new algorithm to obtain the 3DTDRL structure.
3.5 Reversible Lattice Circuits
(a)
67
(b)
2f0+2f1+2f2
z
v2
F
v2
v
2f1+f2
1
1
Fz
v
x
f0
y
Garbage
F
Garbage
fr1
fr0
fr2
a
a
f2
f0
f1
Fy =2f1+f2
Fx = f0
Fz = 2f0+2f1+2f2
Fig. 3.26 a Irreversible Davio0 3D node, b reversible Davio0 3D node
Synthesis stage:
1. According to the algorithm in Table 3.6, set i = j = k = 0. n(i,j,k) represents the root
node (map of the function), that map is one of the three outputs of the ternary
reversible Davio primitive, the other two output maps of the primitive will be
assigned don’t care. Following the output-to-input paths of the reversible Davio
primitive and using the reverse of the method of permutation of cofactors, new
maps will be constructed at the input of the reversible Davio primitive by permuting the output cofactors (in the output maps) that correspond to the expansion
variable in the three dimensional space. The map in the x-direction represents the
case when the expansion variable is of value 0 (i.e., f0). The map in the
y-direction represents the GF(3) addition of the case when the expansion variable
is of value 2 with twice of the case when the expansion variable is of value 1 (i.e.,
2f1 + f2). The map in the z-direction represents twice of GF(3) additions of the
three cases of values 0, 1, and 2 of the expansion variable (i.e., 2f0 + 2f1 + 2f2).
The new input maps will be represented by nodes according to the control
variable as follows: n(i+1,j,k) for the map in the x-direction and n(i, j+1, k) for the
map in the y-direction and n(i,j,k+1) for the map in the z-direction (this represents
the first level of the 3DTDRL). If all maps are constants then go to 5 else go to 2.
2. Increment i, j, and k; each of these new nodes will be treated as the root node by
taking the map that is represented by that node and assigning it to one of the
outputs of the reversible Davio primitive, but that output should have the same
position as that of the root node. The other two outputs are assigned don’t care.
Then by following the output-to-input paths of the primitive and assigning
68
3 Methods of Reversible Logic Synthesis
nodes according to the next expansion variable for the new maps (this will be
followed for all the successive levels). Now, if all nodes (maps) are constants
with non-conflicting values in the common indices nodes (CINs) then go to 5,
else go to 3.
3. This step is the same as step 2 for 3D Ternary Lattice (3DTL) circuits’ algorithm
in Table 3.6.
ifall the CINs are constants with non-conflicting values
then go to 4
else (Utilizing Equations (3.55), (3.56) and (3.57)
Join nodes with common indices
if three nodes exist
then (apply Equations (3.55), (3.56) and (3.57) to join CCW
starting with nodes n(i, j, k) , then nodes n(i+1, j-1, k) , then
nodes n(i+1, j, k-1))
else(set the non-existing nodes to zero
apply Equations (3.55), (3.56) and (3.57) to join CCW starting with
nodes n(i, j, k) , then nodes n(i+1, j-1, k) , then nodes n(i+1, j, k-1))
)
go to 4
4.
for each non-constant node (Utilizing Equation (3.15)
// for x, y, and z as general positional indices that can be expressed in
terms of i, j, and k, respectively //.
Expand n(x, y, z) into n(x+1, y, z) , n(x, y+1, z) , n(x, y, z+1)
)
if all nodes are constants with no conflicting values in the CINs
then go to 5
else go to 2
5. End.
3.5 Reversible Lattice Circuits
69
Analysis stage:
6. Going from out-to-in and using the method of permuting cofactors for all of the
gates throughout the lattice until all maps contain care values with no don’t care.
(Note: In this algorithm, the analysis stage can be achieved within the synthesis
stage).
Example 3.3 (3DTDRL) for a symmetrical function.
The 3DTDRL is implemented for a symmetrical function F of three variables as
in Fig. 3.27, which shows the exact steps and the content of the maps at each level
of the lattice for the synthesis and analysis stages.
Figure 3.28 shows the 3DTDRL circuit realization of the symmetrical function
F. The circuit contains four nodes and eight leaves, but in [13] the same function F
is realized using 3D ternary Shannon reversible lattice with ten nodes and ten
leaves. That shows the importance of the new 3DTDRL method.
3.6
Reversible Fast Transform Circuits
Spectral methods have also been used to synthesize reversible fast transform circuits [6].
The spectral transform S (or the vector of spectral coefficients) for n variables is
defined as follows:
!n
F
ð3:85Þ
S ¼ ½M½~
where [M] is the transform matrix, [~
F] is the truth vector of function f, and Sn is the
vector of spectral coefficients for n variables. For example, performing the same
method used for obtaining Eqs. (3.31)–(3.33), similar Equations for reversible
Davio of types D1 and D2 can be obtained. The vectors of spectral coefficients for
reversible Davio expansions of type D0, D1, and D2 are obtained as follows:
2
1
!
S1012;D0 ¼ 4 0
2
0
2
2
3
32 3 2
f0
0
f0
5
2f 1 þ f 2
1 54 f 1 5 ¼ 4
2
f2
2f 0 þ 2f 1 þ 2f 2
ð3:86Þ
2
0
!
S1120;D0 ¼ 4 2
2
0
1
2
3
32 3 2
f2
f0
1
5
2f 0 þ f 1
0 54 f 1 5 ¼ 4
f2
2f 0 þ 2f 1 þ 2f 2
2
ð3:87Þ
2
0
!
1
S201;D0 ¼ 4 1
2
1
0
2
3
32 3 2
f1
f0
0
5
2f 2 þ f 0
2 54 f 1 5 ¼ 4
f2
2f 0 þ 2f 1 þ 2f 2
2
ð3:88Þ
70
3 Methods of Reversible Logic Synthesis
F
n(0, 0, 0)
Garbage
a
0 2 1 2 2 2 1 2 0
Garbage
bc
00 01 02 10 11 12 20 21 22
0
0 0 0 0 1 2 0 2 1
0 1 2 1 0 2 2 2 2
0 0 0 0 1 2 0 2 1
1
0 1 2 1 0 2 2 2 2
0 2 1 2 2 2 1 2 0
0 1 2 1 0 2 2 2 2
2
0 2 1 2 2 2 1 2 0
0 0 0 0 1 2 0 2 1
a
a
f2 f0 f1
f0 f1 f2
f0
f1 f2 f0
f1
f2
0 1 2 1 0 2 2 2 2
0 2 1 2 2 2 1 2 0
0 1 2 1 0 2 2 2 2
0 2 1 2 2 2 1 2 0
0 1 2 1 0 2 2 2 2
0 2 1 2 2 2 1 2 0
f2
f1
f1
2f1+f2
f0
2f1+f2
2f0+2f1+2f2
0 0 0 0 1 2 0 2 1
0 0 0 0 0 0 0 0 0
0 1 2 1 2 0 2 0 1
0 0 0 0 1 2 0 2 1
0 0 0 0 0 0 0 0 0
0 1 2 1 2 0 2 0 1
0 0 0 0 1 2 0 2 1
0 0 0 0 0 0 0 0 0
0 1 2 1 2 0 2 0 1
n(1, 0, 0)
n(0, 0, 1)
n(0, 1, 0)
Fig. 3.27 The synthesis and analysis stages of the symmetrical function F in Example 3.3
3.6 Reversible Fast Transform Circuits
71
Garbage
n(1, 0, 0)
Garbage
0 2 1 0 0 0 0 1 2
0 0 0 0 1 2 0 2 1
0 1 2 0 2 1 0 0 0
0 2 1 0 0 0 0 1 2
0 0 0 0 1 2 0 2 1
0 1 2 0 2 1 0 0 0
0 2 1 0 0 0 0 1 2
0 0 0 0 1 2 0 2 1
0 1 2 0 2 1 0 0 0
b
b
f0
f1
f2
0 1 2 0 1 2 0 1 2
0 2 1 0 2 1 0 2 1
0 1 2 0 1 2 0 1 2
0 2 1 0 2 1 0 2 1
0 1 2 0 1 2 0 1 2
0 2 1 0 2 1 0 2 1
f2
f1
f1
2f1+f2
f0
2f1+f2
2f0+2f1+2f2
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1 2 0 1 2 0 1 2
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1 2 0 1 2 0 1 2
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1 2 0 1 2 0 1 2
n(2, 0, 0)
n(1, 0, 1)
n(1, 1, 0)
Fig. 3.27 (continued)
72
3 Methods of Reversible Logic Synthesis
Garbage
n(0, 1, 0)
Garbage
2 0 1 0 1 2 1 2 0
0 1 2 1 2 0 2 0 1
1 2 0 2 0 1 0 1 2
2 0 1 0 1 2 1 2 0
0 1 2 1 2 0 2 0 1
1 2 0 2 0 1 0 1 2
2 0 1 0 1 2 1 2 0
0 1 2 1 2 0 2 0 1
1 2 0 2 0 1 0 1 2
b
b
f0
f1
f2
1 2 0 1 2 0 1 2 0
2 0 1 2 0 1 2 0 1
1 2 0 1 2 0 1 2 0
2 0 1 2 0 1 2 0 1
1 2 0 1 2 0 1 2 0
2 0 1 2 0 1 2 0 1
f2
f1
f1
2f1+f2
f0
2f1+f2
2f0+2f1+2f2
0 1 2 0 1 2 0 1 2
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 1 2 0 1 2 0 1 2
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 1 2 0 1 2 0 1 2
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
n(1, 1, 0)
n(0, 1, 1)
n(0, 2, 0)
Fig. 3.27 (continued)
3.6 Reversible Fast Transform Circuits
73
Garbage
n(1, 1, 0)
Garbage
2 0 1 2 0 1 2 0 1
0 1 2 0 1 2 0 1 2
1 2 0 1 2 0 1 2 0
2 0 1 2 0 1 2 0 1
0 1 2 0 1 2 0 1 2
1 2 0 1 2 0 1 2 0
2 0 1 2 0 1 2 0 1
0 1 2 0 1 2 0 1 2
1 2 0 1 2 0 1 2 0
c
c
f0
f1
f2
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
f2
f1
f1
2f1+f2
f0
2f1+f2
2f0+2f1+2f2
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
n(2, 1, 0)
n(1, 1, 1)
n(1, 2, 0)
Fig. 3.27 (continued)
74
3 Methods of Reversible Logic Synthesis
Fig. 3.28 The 3DTDRL
circuit of the symmetrical
function F in Example 3.3
n(0,0,1)
n(0,1,1)
n(1,0,1)
a2
b2 F
a
n(1,1,1) b2
n(0,1,0)
1 n(0,0,0) c2
n(1,0,0) b
1
b
1
n(2,0,0)
n(0,2,0)
b
n(1,2,0)
c
c
1
b
a
n(1,1,0)
n(2,1,0)
2
0
!
S1012;D1 ¼ 4 2
2
0
1
2
3
32 3 2
f2
f0
1
5
2f 0 þ f 1
0 54 f 1 5 ¼ 4
f2
2f 0 þ 2f 1 þ 2f 2
2
ð3:89Þ
2
0
!
S1120;D1 ¼ 4 1
2
1
0
2
3
32 3 2
f1
f0
0
5
2f 2 þ f 0
2 54 f 1 5 ¼ 4
f2
2f 0 þ 2f 1 þ 2f 2
2
ð3:90Þ
2
1
!
S1201;D1 ¼ 4 0
2
0
2
2
3
32 3 2
f0
0
f0
5
2f 1 þ f 2
1 54 f 1 5 ¼ 4
2
f2
2f 0 þ 2f 1 þ 2f 2
ð3:91Þ
2
0
!
S1012;D2 ¼ 4 1
2
1
0
2
3
32 3 2
f1
0
f0
5
2f 2 þ f 0
2 54 f 1 5 ¼ 4
2
f2
2f 0 þ 2f 1 þ 2f 2
ð3:92Þ
2
1
!
S1120;D2 ¼ 4 0
2
0
2
2
3
32 3 2
f0
f0
0
5
2f 1 þ f 2
1 54 f 1 5 ¼ 4
f2
2f 0 þ 2f 1 þ 2f 2
2
ð3:93Þ
2
0
!
S1201;D2 ¼ 4 2
2
0
1
2
3
32 3 2
f2
f0
1
5
2f 0 þ f 1
0 54 f 1 5 ¼ 4
f2
2f 0 þ 2f 1 þ 2f 2
2
ð3:94Þ
From Eqs. (3.86)–(3.94), it is noted that:
! ! !
S1012;D0 ¼ S1201;D1 ¼ S1120;D2
ð3:95Þ
! ! !
S1120;D0 ¼ S1012;D1 ¼ S1201;D2
ð3:96Þ
3.6 Reversible Fast Transform Circuits
75
! ! !
S1201;D0 ¼ S1120;D1 ¼ S1012;D2
ð3:97Þ
Utilizing Eqs. (3.95)–(3.97), Fig. 3.29 shows all of the (3, 3) reversible kernels
for Eqs. (3.86)–(3.94), respectively, where dashed lines indicate multiplications by
2, and addition operation over GF(3) is used at the intersects of end lines. The three
inputs to each of the three circuits are {f0, f1, f2}, and output vectors from three
! !
!
circuits are: S1012;D0 , S1120;D0 , and S1201;D0 , respectively.
Families of fast permutation transform circuits for the reversible Shannon
expansions are created as follows:
Referring to Eq. (3.23)
2
f 012;S ¼ 0 x f 0 þ 1 x f 1 þ 2 x f 2 ¼
2
¼
0
x
1
x
2
1 0
0
0
6
x 40 1
0 0
x
32
1
2
x
f0
3
76 7
0 54 f 1 5
1
f2
f 120;S ¼ 1 x f 0 þ 2 x f 1 þ 0 x f 2 ¼
¼
2
0 0
6
1
2
x x x 41 0
0 1
012
3
6 7
x 4 f1 5
f2
2
0
f0
1
1
x
32
2
0
x
f0
3
f0
3
6 7
x 4 f1 5
f2
76 7
0 54 f 1 5
0
f2
120
201
f0
f0
f0
f2
f0
f1
f1
2f1+f2
f1
2f0+f1
f1
2f2+f0
f2
2f0+2f1+2f2 f2
Kernel 1:
Equation (3.86)
2f0+2f1+2f2 f2
Kernel 2:
Equation (3.87)
Fig. 3.29 (3, 3) Reversible kernels for Eqs. (3.86)–(3.88)
2f0+2f1+2f2
Kernel 3:
Equation (3.88)
76
3 Methods of Reversible Logic Synthesis
2
f 201;S ¼ 2 x f 0 þ 0 x f 1 þ 1 x f 2 ¼
2
¼
0
x
1
x
2
0 1
6
x 40 0
1 0
2
0
x
32
0
x
f0
3
1
f0
3
6 7
x 4 f1 5
f2
76 7
1 54 f 1 5
0
f2
2
1 0
!
1
S012;S ¼ 4 0 1
0 0
32 3 2 3
f0
0
f0
0 54 f 1 5 ¼ 4 f 1 5
1
f2
f2
ð3:98Þ
2
0 0
!
S1120;S ¼ 4 1 0
0 1
32 3 2 3
f2
f0
1
0 54 f 1 5 ¼ 4 f 0 5
f2
f1
0
ð3:99Þ
2
0 1
!
S1201;S ¼ 4 0 0
1 0
32 3 2 3
f1
f0
0
1 54 f 1 5 ¼ 4 f 2 5
f2
f0
0
ð3:100Þ
Figure 3.30 illustrates the (3, 3) reversible kernels for Eqs. (3.98)–(3.100). The
three inputs to each of the three circuits are (f0, f1, f2), and output vectors from three
! !
!
circuits are: S1012;S , S1120;S , and S1201;S , respectively.
Figures 3.31 and 3.32 illustrate the use of the reversible kernels in the realization
of reversible Shannon expansions in Eqs. (3.23) and (3.24), respectively. While
Fig. 3.33 shows the realization of reversible Davio expansion, Eq. (3.38). Universal
logic modules (ULMs) can be used in these realizations. Figures 3.34, 3.35, 3.36,
3.37 show different types of ULMs circuits [3].
Fig. 3.30 Reversible kernels for Eqs. (3.98)–(3.100)
3.6 Reversible Fast Transform Circuits
fr0 = 0x f0 + 1x f1 + 2x f2
77
fr1 = 0x f2 + 1x f0 + 2x f1
fr2 = 0x f1 + 1x f2 + 2x f0
x
x
kernel 1
kernel 2
kernel 3
f0 f1 f2
f0 f1 f2
f0 f1 f2
Fig. 3.31 Logic circuit realization of the reversible Shannon expansion in Eq. (3.23)
fr0 = 0x f0 + 1x f1 + 2x f2
fr1 = 0x f1 + 1x f2 + 2x f0
fr2 = 0x f2 + 1x f0 + 2x f1
x
x
kernel 1
kernel 3
kernel 2
f0 f1 f2
f0 f1 f2
f0 f1 f2
Fig. 3.32 Logic circuit realization of the reversible Shannon expansion in Eq. (3.24)
fr0 = 1·f0 + x·(2f1 + f2)
fr1 = 1·f2 + x(2f0 + f1)
2
+ x (2f0+2f1+2f2)
1
x
x2
fr2 = 1·f1 + x(2f2 + f0)
2
+ x2(2f0+2f1+2f2)
+ x (2f0+2f1+2f2)
1
x2
x
1
x2
x
x
x
kernel 1
f0
kernel 2
f1
f2
f0
kernel 3
f1
f2
f0
Fig. 3.33 Logic circuit realization of the Davio expansion in Eq. (3.38)
f1
f2
78
3 Methods of Reversible Logic Synthesis
x
0
x
f0
1
x
f1
2
x
f2
Fig. 3.34 ULM of ternary Shannon over GF(3) [3]
(c)
(b)
(a)
x
x
x
1
f0
1
1
f2
f1
2f0+f1
2( ) 2
2f2+f0
2( ) 2
x
2f1+f2
2(x)2
f0+f1+f2
f0+f1+f2
f0+f1+f2
Fig. 3.35 ULMs of Davio over GF(3): a D0, b D1, and c D2 [3]
1
·
fi
x
+1
·
+
f
+1
2
·
fj
fk
·
Fig. 3.36 ULM for all ternary Davio expansions over GF(3) [3]
3.7
Group-Theoretic Representations
A finite group G is a set of finite number of elements together with a binary
operation (called the group operation) satisfying the properties of (1) closure,
(2) association, (3) identity, and (4) inverse [5]. Group-theoretic compact representation of the reversible primitives can be considered as a cascading of group
3.7 Group-Theoretic Representations
79
0
x
1
·
x
x`
1
x
fi
x``
2
x
fj
+
·
f
·
2
·
fk
Fig. 3.37 Ternary S/D ULM over GF(3) [3]
representations of individual serially-interconnected reversible primitives.
Figure 3.38 shows the 2-cycle (transposition) group representations of several
important classes of GF(2) (i.e., binary) reversible gates. Each 1-digit decimal
number within each of the number strings between parentheses in Fig. 3.38 represents the corresponding group-represented input row and output row for each
binary truth table of the reversible primitives.
General k-cycle group representations for reversible circuits made of
serial-interconnected and parallel-interconnected reversible primitives are done by
performing the appropriate step-by-step permutations of each stage of the reversible
circuit [5].
Example 3.4 Using the 2-cycle group representations in Fig. 3.38, the following are
group representations of various reversible circuits:
(a) Stage 1: Feynman gate (23); Stage 2: SWAP gate (12); interconnect: Serial.
Group representation: 3-cycle group element (123).
a
c
(23)
e
a b
c d
f
0 0
0 0 0 0
01
0 1 1 0
11
1 0 0 1
(12)
(123)
e f
(b) Stage 1: SWAP gate (12); Stage 2: Feynman gate (23); interconnect: Serial.
Group representation: 3-cycle group element (132).
a
c
(12)
(23)
(132)
e
a b
c d
f
0 0
0 0 0 0
e f
0 1
1 0
1 1
1 1
1 1
1 0
80
3 Methods of Reversible Logic Synthesis
(a)
(b)
(c)
(d)
Input
Output MSB
MSB
MSB
LSB
LSB
LSB
(01)
(67)
(23)
(12)
Input
Output
0
1
Input
Output
Input
Output
Input
Output
1
0
00
01
10
11
00
01
11
10
000
001
010
011
100
101
110
111
000
001
010
011
100
101
111
110
00
01
10
11
00
10
01
11
f 0 f1 x f1r0 f1r1 x
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 1 0 1
1 0 0 1 0 0
1 0 1 0 1 1
1 1 0 1 1 0
1 1 1 1 1 1
f1r0
(e)
f1r1
x
x
0
1
f0
0
1
f1
x x 1 0 f
f
=
f
x x 0 1 f
Input order {f0,f1,x} and Output order {f1r0,f1r1,x}: (35)
f =
(f)
f 0 f1 x f2r0 f2r1 x
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 1 0 0
0 1 1 0 1 1
1 0 0 0 1 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1
f2r0
f2r1
x
x
0
1
f1
0
1
f0
x x 1 0 f
f
=
f
x x 0 1 f
Input order {f0,f1,x} and Output order {f2r0,f2r1,x}: (24)
f =
Fig. 3.38 Group-theoretic representations for important reversible primitives: a NOT gate,
b Feynman gate, c Toffoli gate, d SWAP gate, e reversible GF(2) Shannon 1 (Fredkin 1) gate, and
f reversible GF(2) Shannon 2 (Fredkin 2) gate [5]
3.7 Group-Theoretic Representations
81
(c) Stage 1: Operator (map) (123); Stage 2: Operator (map) (24); interconnect:
Serial. Group representation: 4-cycle group element (1423) (567).
a
(123)
c
d
e
f
(24)
g
h
i
(1423) (567)
abc def ghi
000 000 000
001 010 100
010 011 011
100 100
010
(d) Stage 1: NOT gate (01) in parallel with Feynman gate (23); Stage 2: Toffoli
gate (67); interconnect: Serial. Group representation: (04) (15) (2637).
(01)
a
g
d
e
c
h
f
(23)
i
(67)
abc def ghi
000 100 100
001 101 101
010 111 110
100 000 000
101 001 001
110 011 011
111 010 010
(04) (15) (2637)
3.8
Reversible Reconstructability Analysis Circuits
Reconstructability Analysis (RA) is an important decomposition (partitioning)
technique. There are two types of (RA) [3]: Conventional RA (CRA) and
Modified RA (MRA). Lossless decomposition means to obtain the simplest
decomposed model from data without the loss of any information (i.e., error = 0),
while decomposition with losses means to obtain the simplest decomposed model
from data with an acceptable amount of error. Figure 3.39 illustrates decomposed
structures using both CRA and MRA decompositions, respectively for the logic
function: F = x1x2 + x1x3.
CRA decomposition is illustrated in the upper part of Fig. 3.39, while 1-MRA
and 0-MRA decompositions are illustrated in the middle and lower parts of
Fig. 3.39, respectively. In Fig. 3.39, while CRA decomposes for all values of
Boolean functions, MRA decomposes for an arbitrarily chosen value of the Boolean
functions. The MRA decomposition for the Boolean function being equal either to
“1” (that is 1-MRA) or to “0” (that is 0-MRA).
As can be observed from Fig. 3.39, 1-MRA and 0-MRA decomposition yields
much simpler logic circuit than the corresponding CRA decomposition. Also,
82
3 Methods of Reversible Logic Synthesis
Original Function
x1 x2 x3 F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Simplest CRA Model
x1 x2 f1 x1 x3 f2 x2 x3 f3
0 0 0 0 0 0 0 0 0
0 1 0 0 1 0 0 1 1 0 - 1 0 - 1 0 1 1 1 1 1 1 1 1 -
2
0
0
1
1
x3 f3’
0 0
1 1
0 1
1 1
f1
x1
x2
f2
F
x3
f3
x1 x2 f1 : x1 x3 f2 : x2 x3 f3
Simplest 1-MRA
x1 f2’
0 0
1 1
Simplest CRA Circuit Model
Simplest 1-MRA Circuit
x1
f2’
x2
F
f3’
x3
x1 f2’ : x2 x3 f3’
Simplest 0-MRA
Simplest 0-MRA Circuit
x2
x1 x2 f1”
0 0 0
0 1 0
1 0 0
1 1 1
x1 x3 f2”
0 0 0
0 1 0
1 0 0
1 1 1
f1”
F
x1
x3
f2”
x1 x2 f1” : x1 x3 f2”
Fig. 3.39 CRA versus 1-MRA versus 0-MRA decompositions for the Boolean function
F = x1x2 + x1x3
0-MRA produces more complex decomposed structure than 1-MRA. In addition,
the resulting decomposed structures from MRA are directly realizable in
Boolean-based circuits, while the resulting decomposed structures from CRA are
not directly realizable in Boolean circuits. As can be observed that while the output
block in CRA decomposition is the set-theoretic intersection operation (\), the
output block in 1-MRA and 0-MRA decompositions are the Boolean AND and OR
operation, respectively, which are directly realizable.
It has been proved (in [3]) that MRA decomposition is superior to CRA, BD
(Bi-decomposition), and AC (Ashenhurst-Curtis) decompositions.
3.8 Reversible Reconstructability Analysis Circuits
3.8.1
83
Ternary MRA
The procedure for the ternary MRA intersection algorithm is as follows:
1. Partition the ternary truth table into sub-tables, each contains only single
functional value.
2. Perform CRA on all sub-tables.
3. CRA decompositions are expanded to include the full set of variable and
function values, and these expanded decompositions are then intersected to yield
the original table.
Example 3.5 The ternary MRA intersection algorithm for the following ternary
map is as follows [3]:
3
1 x2
00
01
02
10
11
12
20
21
22
0
0
1
1
0
0
1
0
1
2
1
0
1
1
0
0
1
2
1
2
2
0
0
1
2
2
1
0
0
0
Step 1: Decompose the ternary map of the function into three separate tables each
for a single function value. This will produce the following three sub-tables T0, T1,
and T2.
Value "0"
000
Value "1"
010
Value "2"
102
112
221
120
200
210
T1
T0
84
3 Methods of Reversible Logic Synthesis
Step 2: Perform CRA for each sub-table.
Step 2a: Considering T0 sub-table:
From T0 the following three sub-tables T01, T02, and T03 are derived.
x1 x2
00
01
10
11
20
21
x 2 x3
00
01
02
12
10
11
22
x1 x3
00
01
02
10
11
20
22
The merging of T01 with T02 yields T012. While the merging of T01 with T03 and
T02 with T03 yield T013 and T023, respectively. All the tuples (cubes) of T012,
should be exist in T0, otherwise the T012 cannot decompose the function. The same
thing is applied for T013 and T023. These three sub-tables (T012, T013, and T023)
are shown below.
x1 x2 x3
0 0 0
0 0 1
0 0 2
0 1 2
0 1 0
0 1 1
1 0 0
1 0 1
1 0 2
1 1 2
1 1 0
1 1 1
2 0 0
2 0 1
2 0 2
2 1 2
2 1 0
2 1 1
2 2 2
Exist in T0
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Yes
No
Yes
Yes
No
No
Yes
x1 x2 x3
0 0 0
0 0 1
0 0 2
0 1 0
0 1 1
0 1 2
1 0 0
1 0 1
1 1 0
1 1 1
2 0 0
2 0 2
2 1 0
2 1 2
2 2 0
2 2 2
Exist in T0
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
T013
x1 x2 x3
0 0 0
0 1 0
0 0 1
0 1 1
0 0 2
0 1 2
0 2 2
1 0 0
1 1 0
1 0 1
1 1 1
2 0 0
2 1 0
2 0 2
2 1 2
2 2 2
Exist in T0
Yes
No
Yes
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
T023
T012
It is clear that, the 0-MRA decomposition cannot decompose the function.
3.8 Reversible Reconstructability Analysis Circuits
85
Step 2b: By applying the same procedure in (Step 2a) on sub-table T1, the 1-MRA
decomposition of T1 is as follows:
x 1 x2
0 1
0 2
1 2
2 1
T11
:
x2 x 3
1 0
1 1
2 0
2 1
2 2
T12
Step 2c: The 2-MRA decomposition of T2 is as follows:
x 1 x3 :
1 2
2 1
2 0
T23
x2 x 3
0 2
1 2
0 1
2 0
2 1
T22
Step 3: The intersection algorithm
Step 3a: Select the two simplest error-free decomposed models. In this particular
example, these are 1-MRA and 2-MRA decompositions. MRA thus gives the
decomposition model of T11: T12: T23: T22 from which the original function can
be reconstructed as follows.
Step 3b: Note that, for tables T11 and T12, the MRA decomposition is for the value
“1” of the logic function. Therefore, the existence of the tuples in the decomposed
model implies that the function has value “1” for those tuples, and the
non-existence of the tuples in the decomposed model implies that the function does
not have value “1” but “0” or “2” for the non-appearing tuples. This is shown in
Tables 1 and 2, respectively. Similarly, for tables T23 and T22, the MRA
decomposition is for the value “2” of the logic function, and Tables 3 and 4 are
derived from them, respectively.
Table 1
1 x2 F1
0 0 0,2
0 2 1,0,2
1 0 0,2
Table 2
x2 x3 F2
0 0 0,2
0,2
0 2 0,2
1 0 1,0,2
Table 3
x1 x3 F3
0 0 0,1
0 1 0,1
0 2 0,1
1 0 0,1
1 2 1,0,2
1 2
0,2
1 2
2,0,1
2 1 1,0,2
2 1
1,0,2
2 1
2,0,1
:
:
Table 4
x2 x3 F4
0 0 0,1
0 1 2,0,1
0 2 2,0,1
1 0 0,1
1 2
2 0
2 1
2,0,1
2,0,1
2,0,1
86
3 Methods of Reversible Logic Synthesis
x1
F1
Table 1
x2
F5
F2
Table 2
x3
F
x1
F3
Table 3
x3
F6
F4
Table 4
x2
Fig. 3.40 The resulting decomposed structure by applying the ternary MRA decomposition
Step 3c: Tables 1, 2, 3, and 4 are used to obtain the block diagram in Fig. 3.40,
where the following equations govern the outputs of the levels in the circuit:
F ¼ F5 \ F6 ;
F5 ¼ F1 \ F2 ;
F6 ¼ F3 \ F4
where F1, F2, F3, and F4 are given by Tables 1, 2, 3, and 4, respectively.
The intermediate sub-functions, F5 and F6 are shown in the following maps,
respectively.
x3
x1 x 2
x3
00
01
02
10
11
12
20
21
22
0
0,2
1
1
0,2
0,2
1
0,2
1
0,2
1
0,2
1
1
0,2
0,2
1
0,2
1
0,2
2
0,2
0,2
1
0,2
0,2
1
0,2
0,2
0,2
F5 = F1
F2
x 1 x2
00
01
02
10
11
12
20
21
22
0
0,1
0,1
0,1
0,1
0,1
0,1
0,1
0,1
2
1
0,1
0,1
0,1
0,1
0,1
0,1
2
0,1
2
2
0,1
0,1
0,1
2
2
0,1
0,1
0,1
0,1
F6 = F3
F4
The logic function in Example 3.5 is non-decomposable using CRA. Consequently,
the ternary MRA is superior to CRA, analogously to the binary case.
3.8.2
Reversible MRA (RMRA)
Reversible gates can be used for the construction of RMRA circuits. The synthesis
of the 1-MRA circuit of Fig. 3.39 is done with the reversible circuit in Fig. 3.41,
where blocks B1, B2 and B3 are the reversible gates WIRE (BUFFER), OR and
Toffoli, respectively. The RMRA produces garbage (G1, G2 and G3) in the outputs,
3.8 Reversible Reconstructability Analysis Circuits
87
B1
B3
x1
f2’= x1
G2
BUFFER
Toffoli
gate
0
F
x2
x3
0
1
f3’= (x2+x3)
0
1
G1
G3
1
x2
OR - gate
B2
Fig. 3.41 Reversible (5, 5) Boolean circuit that implements the 1-MRA circuit of Fig. 3.39
and this output garbage has to be eliminated when the quantum counterpart of
RMRA is created.
The disadvantage of RMRA is that it creates big garbage, and thus the elimination of garbage in RMRA structures is done by using the reversible mirror image
circuit of the forward reversible circuit.
3.9
Reversible Programmable Gate Array (RPGA)
RPGA based on regular structure to realize binary functions in reversible logic is
introduced in [3, 14]. This structure, called a 2 * 2 Net structure, allows for
efficient realization of symmetric functions. A regular structure means a logic circuit and its physical layout structure being an array of identical cells regularly
connected, or a structure composed of few, regularly connected, structures of this
type, called planes. By regularly connected, it is understood that every cell (except
of boundary cells) is connected to its k neighbors.
3.9.1
Definitions
There is a subset of Boolean expressions, that are specified as sum-of-products, in
which every variable is either negated or not negated, but not both [11, 14].
88
3 Methods of Reversible Logic Synthesis
Definition 3.10 The variable that stands non-negated (positive) throughout the
expression is called a positive polarity variable. Variable that stands always in
negated (negative) form is called a negative polarity variable.
Definition 3.11 Unate function is a function expressed only using AND and OR
operators (for instance Sum-of-Products) in which every variable has either positive
or negative polarity, but not both.
For example, the function f = a b + b c is unate and has polarity: a = negative,
b = positive, c = positive. Function g = a b + a b is not unate.
Definition 3.12 Totally symmetric function that has value 1 when exactly k of its
n inputs are equal one and exactly n − k remaining inputs are equal 0, is called a
single-index symmetric function and denoted by Sk(x1, x2, …, xn). Analogously,
S{i,j,k} denotes the function that is one when i, j, or k of its variables are equal one.
Every symmetric function can be written as SI(x1, x2… xn), where I is any subset of
the set of indices {0, 1, 2… n}. It can be also easily checked that [11, 14]:
SI1 ðx1 ; x2 ; . . .; xn Þ AND SI2 ðx1 ; x2 ; . . .; xn Þ ¼ SI1intersectionI2 ðx1 ; x2 ; . . .; xn Þ
SI1 ðx1 ; x2 ; . . .; xn Þ OR SI2 ðx1 ; x2 ; . . .; xn Þ ¼ SI1unionI2 ðx1 ; x2 ; . . .; xn Þ
SI1 ðx1 ; x2 ; . . .; xn Þ EXOR SI2 ðx1 ; x2 ; . . .; xn Þ ¼ SI1symmetricdifferenceI2 ðx1 ; x2 ; . . .; xn Þ
Because the single index functions are disjoint then the OR of them is the same
as the EXOR of them (i.e., this is based on the Boolean law:
A þ B ¼ A B AB, and when A and B are disjoint functions: then AB = 0 and
thus A þ B ¼ A B ). Therefore,
Si ðx1 ; x2 ; . . .; xn Þ EXOR Sj ðx1 ; x2 ; . . .; xn Þ ¼ Si ðx1 ; x2 ; . . .; xn Þ
OR Sj ðx1 ; x2 ; . . .; xn Þ ¼ Si;j ðx1 ; x2 ; . . .; xn Þ:
3.9.2
(2 * 2) Net Structures and RPGAs
The basic idea of reversible Net structures [3] made up of (2, 2) reversible gates is
based on regular planes as shown in Fig. 3.42. The regular structure of RPGA has
two regular planes (Fig. 3.42). The first plane from left is planar, regular and
algorithmically created (it is also called the triangular plane). It consists of
OR/AND (MAX/MIN) combination cells to realize all positive unate symmetric
functions (PUS) of its input variables. The second plane is just a sequence of
columns of Feynman gates that converts these PUS functions to arbitrary symmetric
functions at the bottom. Every output function is realized as an EXOR of PUS
functions.
3.9 Reversible Programmable Gate Array (RPGA)
First plane
Second plane
C
A
B
MAX(A,B)
=A+B
89
MAX(A,B,C)
=(A+B)+C
1,2,3
=S
(A,B,C)
MIN(A,B)
= A*B
C(A+B)
0
0
S1,2,3
Feynman
gate
S1,2,3
Feynman
gate
2,3
S (A,B,C)
=(A*B)+C(A+B)
MIN(A,B,C)
3
=(A*B)*C=S (A,B,C)
S
Feynman
gate
S3
S1,2
S2,3
2,3
Feynman
gate
S3
S2
Arbitrary symmetric functions
Fig. 3.42 Realization of 3-input 2-output function S1;2 ðA, B, CÞ; S2 ðA, B, CÞ in RPGA
3.9.3
The New Reversible Gate (SALEEM)
Reversible (3, 3) gates, that are universal in two arguments, can be used for the
construction of the RPGA. A new reversible (3, 3) gate, called SALEEM, is
designed in this work to implement the AND/OR cells of the RPGA. It is universal
in two arguments. It consists of a Toffoli gate and two Feynman gates connected in
three different ways (versions), called SALEEM-I, II and III, as shown in Fig. 3.43
(the Toffoli and Feynman gates are denoted as T and F, respectively). The truth
tables of the SALEEM gate are shown in Table 3.14, from which it is clear that the
SALEEM gate is balanced but not conservative. Note that, the SALEEM reversible
gate can be called here as reversible logic module (RLM).
The SALEEM gate is universal in two arguments (variables), as is proved in
Table 3.15.
The production of cofactors for the (3, 3) SALEEM reversible gate is shown in
Table 3.16.
3.9.4
Novel Design of RPGA Based on the SALEEM
Reversible Gate
The SALEEM gate is required to achieve the AND and OR operations when it is
used to implement the cells in the first plane of the RPGA, while it is required to
achieve the EXOR and copy operations when it is used to implement the cells in the
second plane. From Tables 3.15 and 3.16, it is clear that; when the input c = 0, the
SALEEM-I, II and III gates can achieve the AND and OR operations. Thus, any
one of these three gates can be used to implement the cells in the first plane. For the
second plane, the SALEEM-II (with the input B = 0) and the SALEEM-III (with the
90
3 Methods of Reversible Logic Synthesis
(a)
(b)
(c)
Fig. 3.43 The three versions of SALEEM reversible gate, a SALEEM-I, b SALEEM-II, and
c SALEEM-III
Table 3.14 The truth tables of the SALEEM gate
Inputs
A
B
C
Outputs of SALEEM versions
SALEEM-I
SALEEM-II
P
Q
R
P
Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
1
0
R
SALEEM-III
P
Q
R
0
1
0
1
0
1
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
input A = 0) can be used to implement the cells in this plane. For the circuit
regularity, the same type of SALEEM gates is used in both planes of the RPGA.
The choice is made to use the SALEEM-II gates for the implementation of the cells
for the whole RPGA circuit. The notations for the SALEEM-II gates used in the
first and the second planes are shown in Fig. 3.44. The realization of 4-input
3-output function in RPGA using the SALEEM-II reversible gate is shown in
Fig. 3.45.
C=1
C=0
C=0
C=1
R ¼ AB
P ¼ A þ B; Q ¼ AB;
B=0
B=1
P ¼ A C; Q ¼ C; R ¼ C
B=0
B=1
Q ¼ A C; R ¼ A C
P ¼ C;
R ¼ AB
P ¼ A þ B; Q ¼ AB;
A=0
A=1
P ¼ B C; Q ¼ B C; R ¼ C
Q ¼ C; R ¼ B C
P ¼ C;
A=0
A=1
P ¼ A; Q ¼ A þ B; R ¼ AB
B=0
B=1
P ¼ A; Q ¼ A C; R ¼ C
R¼AC
P ¼ A; Q ¼ C;
P ¼ A; Q ¼ A þ B; R ¼ AB
C=1
C=0
A=0
A=1
P ¼ A þ B; Q ¼ B; R ¼ AB
P ¼ A þ B; Q ¼ B; R ¼ AB
P ¼ A C; Q ¼ 0; R ¼ C
Q ¼ 1; R ¼ A C
P ¼ C;
P ¼ B C; Q ¼ B; R ¼ C
Q ¼ B; R ¼ B C
P ¼ C;
SALEEM-III
Inputs
Outputs
P ¼ 0; Q ¼ B C; R ¼ C
R¼BC
P ¼ 1; Q ¼ C;
SALEEM-II
Inputs
Outputs
Outputs
SALEEM-I
Inputs
Table 3.15 Proof of universality of the SALEEM gate in two arguments
3.9 Reversible Programmable Gate Array (RPGA)
91
92
3 Methods of Reversible Logic Synthesis
Table 3.16 Demonstration of the number of cofactors for the (3, 3) SALEEM reversible gate
SALEEM-I (11 cofactors)
SALEEM-II (11 cofactors)
SALEEM-III (11 cofactors)
Pð0; B; CÞ ¼ B C
Pð1; B; CÞ ¼ C
Pð0; B; CÞ ¼ 0
Pð1; B; CÞ ¼ 1
Pð0; B; CÞ ¼ B C
Pð1; B; CÞ ¼ C
PðA; 0; CÞ ¼ A C
PðA; B; 0Þ ¼ A þ B
PðA; 0; CÞ ¼ A
Qð0; B; CÞ ¼ B C
Qð1; B; CÞ ¼ C
PðA; 0; CÞ ¼ A C
PðA; B; 0Þ ¼ A þ B
PðA; B; 1Þ ¼ A þ B
Qð1; B; CÞ ¼ C
QðA; 1; CÞ ¼ A C
QðA; B; 0Þ ¼ AB
QðA; B; 1Þ ¼ AB
RðA; B; 0Þ ¼ AB
RðA; B; 1Þ ¼ AB
(a)
QðA; 0; CÞ ¼ A C
QðA; B; 0Þ ¼ A þ B
QðA; B; 1Þ ¼ A þ B
Rð0; B; CÞ ¼ C
PðA; B; 1Þ ¼ A þ B
Qð0; B; CÞ ¼ B
QðA; 0; CÞ ¼ 0
QðA; 1; CÞ ¼ 1
Rð0; B; CÞ ¼ C
RðA; B; 0Þ ¼ AB
RðA; B; 0Þ ¼ AB
RðA; B; 1Þ ¼ AB
RðA; B; 1Þ ¼ AB
(b)
Fig. 3.44 The notations for the SALEEM-II gates (hexagon cells), a used in the first RPGA plane,
b used in the second RPGA plane
It is clear from Fig. 3.45, that horizontal outputs from the first plane PUS
functions are EXOR-ed in the second plane to create arbitrary symmetric functions
at the bottom. The additional garbage outputs of the SALEEM-II gates (hexagon
cells) in the first plane must be forwarded to the primary outputs of the first plane,
and can be used in the same way as the horizontal outputs to realize some
non-symmetric functions in the second plane with no repeated variables. The following example should clarify this fact.
Example 3.6 The RPGA method is to be used to realize the non-symmetric
function:
f ¼ abc þ abc þ abd þ abc:
3.9 Reversible Programmable Gate Array (RPGA)
b
a
a
1
c
(a + b)
(a + b) d
(a + b+ c)
(a + b +c)
2
93
S
3
Second plane
1, 2 ,3 ,4
S1, 2, 3, 4
0
0
0
c(a +b) 0
ab
d(a+b+c)
ab
4
(ab+ac+bc)
(ab+ac+bc)
0
S1, 2, 3, 4
S1
9
S2, 3, 4
5
0
0
abc
abc
6
S
S2, 3, 4
S1
0
7
S1, 2 S1
3, 4
S
10
3,4
S3, 4
0
8
0
S4
First plane
S4
abcd
S 1,2,4 S1,2 S1,3,4
Fig. 3.45 Realization of 4-input 3-output function S1;2 ða,b,c,dÞ; S1;2;4 ða,b,c,dÞ; S1;3;4 ða,b,c,dÞ in
RPGA
The K-map of the function f can be obtained by EXORing the two K-maps of
functions S1,2,3,4 and (ab + ac + bc), as shown below.
cd
ab
cd
00 01 11 10
1 1
01 1 1
ab
=
f
cd
00 01 11 10
00
1 1 1
01 1 1 1 1
11 1 1 1 1
S1,2,3,4
ab
00 01 11 10
00
01
1 1
11 1 1 1 1
10
1 1
(ab + ac + bc)
Referring to Fig. 3.45, the function f can be realized by EXORing the first PUS
function horizontal output of the first plane with the additional garbage output of
cell 5.
The RPGA technique presented in this work is superior to previous types in [3,
14], because the same type of gates is used in the implementation of the two
RPGA’s planes.
94
3.10
3 Methods of Reversible Logic Synthesis
Reversible Cascade Circuits
This method includes the cascade generation of reversible terms. The primary
inputs of function F are the input variables (a1, a2… an) for each stage of the circuit.
These stages are connected in cascade [3]. Each stage is designed to realize one
term of the function F using Feynman or Toffoli gate. Thus, the function F should
be written in the ESOP (EXOR sum-of-products) form. The following example
shows the reversible synthesis using the reversible cascades.
Example 3.7 Figure 3.46 shows the use of the reversible cascades method to
synthesize the function F ¼ 1 a b ab. This expression can be minimized to
F ¼ ab.
Figure 3.46a shows the reversible cascades composed of three stages of two
Feynman gates in the first two stages and a Toffoli gate at the third stage.
Figure 3.46b shows an equivalent reversible cascade circuit made only of Toffoli
gate as a result of minimization.
The good property of this method compared to other reversible logic synthesis
methods, is that it creates at most one constant input and no garbage outputs (see
Fig. 3.47). The same topological structure can be applied to a Galois field of any
(a)
(b)
a
a
a
a
·
·
b
b
b
b
1
F
0
F
Fig. 3.46 Reversible cascades for the realization of the function F in Example 3.7: a for the
original function, and b for the minimized function; (a bubble means an inverter) [3]
Inputs
a1
a2
.
.
an
Constant
a1
a2
.
.
an
Outputs = Inputs
Function
Fig. 3.47 Reversible cascades have no output garbage on average
3.10
Reversible Cascade Circuits
95
(a)
(b)
b
b
b
·
b
·
c
c
c
0
f
GF(3)
GF(3)
GF(3)
c
0
f
GF(3)
Fig. 3.48 Reversible cascade for the realization of the function f in Example 3.8: a for the original
function, and b for the minimized function f = b″c′ [3]
radix. The only difference is that reversible multiple-valued gates have to be used
and the constant in the bottom layer can be either of any value within the radix
instead of just being of values “0” or “1” for radix two [3].
Example 3.8 Figure 3.48a shows the synthesis, using reversible cascades, of the
ternary logic function: f = b′ +GF(3) c′ +GF(3) b′c. The minimal form of f can be
obtained as follows:
f ¼ b0 þGFð3Þ c0 þGFð3Þ b0 c ¼ b0 1 þGFð3Þ c þGFð3Þ c0 ¼ b0 c0 þGFð3Þ c0
¼ c0 1 þGFð3Þ b0 ¼ b00 c0
Examples 3.7 and 3.8 show clearly the need to minimize the expression before it
is realized in a reversible cascade circuit. If the structure produces only the output
function and the inputs as outputs, then there is no garbage in the output of the
structure. Consequently, outputs of a reversible circuit that are generated by
propagating the inputs through the reversible circuit are not considered as garbage.
Hence, the reversible cascade circuit has no output garbage on average.
3.11
Spectral-Based Synthesis Method
This method was suggested in [15], it is a reversible function synthesis that starts
with a reversible specification only. A spectral technique is used to find the best
gate to be added in terms of gates [NOT, CNOT, Toffoli 3 (with 3 inputs), and
Toffoli 4 (with 4 inputs)] and adds the gate in a cascade-like manner. The output
function is required to appear as a set of actual outputs or their negations. A post
processing process to simplify the network is used.
96
3 Methods of Reversible Logic Synthesis
A completely-specified Boolean function f (x1, …xn) is defined by a column
vector of 2n (0’s and 1’s) denoted F. The Rademacher-Walsh spectrum of the
function is given by
R ¼ Tn F
where the transform matrix Tn is a Hadamard matrix defined as
T0 ¼ ½1
"
Tp1
Tp ¼
Tp1
Tp1
#
Tp1
It has been shown [15] that one simple measure of function complexity is given
by
"
#
n
2X
1
1
1
n 2n n2
Cðf Þ ¼
kvkð r v Þ 2
2
2
v¼0
where ∥v∥ is the number of 1’s in the binary expansion of v. The complexity metric
used in this method is:
Dðf Þ ¼ n 2n NZðRÞ þ CðfÞ
where NZ(R) is the number of zero coefficients in R.
The synthesis method first transforms each function to the spectral domain
giving the spectra Ri, 1 ≤ i ≤ n.
Procedure
(a) Examine the effect of each of the n(n − 1) possible FEY(x; y) gates (where x is
the control line and y is the target of the Feynman gate) and select the gate that
results in the maximum positive change in D(fi) for the variable it affects.
(b) If no gate is identified in (a), examine the effect of each of the n (n − 1)(n − 2)/
2 possible TOF3(x, y; z) gates (where x and y are the control lines and z is the
target) each with the four possible negation patterns for x, y and select the gate
and negation pattern that results in the maximum positive change in D(fi) for
the variable it affects.
(c) If no gate is identified in (b), examine the effect of each of the n(n − 1)(n − 2)
(n − 3)/6 possible TOF4(w, x, y; z) gates each with the eight possible negation
patterns for w, x, y (the control lines) and select the gate and negation pattern
that results in the maximum positive change in D(fi) for the variable it affects.
(d) If no gate is identified in (c), the procedure terminates in error. Otherwise,
go to (a).
3.11
Spectral-Based Synthesis Method
97
The above procedure is applied iteratively until the problem has been reduced to
a set of n spectra each representing a unique variable or its complement. Each
complemented variable requires a NOT gate be applied. The final result is a
sequence of reversible logic gates which when applied in order transforms each of
the initial n spectra to the spectrum of a unique variable. The method thus synthesizes the circuit from the outputs back to the inputs.
Example 3.9 This example shows the realization of a Fredkin gate using two
Feynman gates and a Toffoli gate.
Specification: [ 0, 1, 2, 3, 4, 6, 5, 7] (corresponds to Table 3.17).
Here, n = 3 and therefore,
2
1
61
6
61
6
61
3
T ¼6
61
6
61
6
41
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1 7
7
1 7
7
1 7
7
1 7
7
1 7
7
1 5
1
From Table 3.17, the following functions are obtained:
2 3
0
607
6 7
607
6 7
607
0
7
F1 ð=a Þ ¼ 6
6 1 7;
6 7
617
6 7
415
1
Table 3.17 Fredkin gate
specification
2 3
0
607
6 7
617
6 7
617
0
7
F2 ð=b Þ ¼ 6
6 0 7;
6 7
617
6 7
405
1
2 3
0
617
6 7
607
6 7
617
0
7
F3 ð=c Þ ¼ 6
607
6 7
607
6 7
415
1
Inputs
Outputs
abc
000
001
010
011
100
101
110
111
a′b′c′
000
001
010
011
100
110
101
111
98
3 Methods of Reversible Logic Synthesis
The spectrum R = T3 F for each of the above functions (F1, F2 and F3) are as
follows:
3
4
6 0 7
7
6
6 0 7
7
6
6 0 7
7
R1 ¼ 6
6 4 7;
7
6
6 0 7
7
6
4 0 5
0
2
But, C(f) = (1/2) [24 − (1/2)
and C(F3) = 6. Consequently,
3
4
6 2 7
7
6
6 2 7
7
6
6 0 7
7
R2 ¼ 6
6 0 7;
7
6
6 2 7
7
6
4 2 5
0
2
3
4
6 2 7
7
6
6 2 7
7
6
6 0 7
7
R3 ¼ 6
6 0 7
7
6
6 2 7
7
6
4 2 5
0
2
P7
2
v¼0 kvk (rv) ]. Therefore, C(F1) = 8, C(F2) = 6
DðF1 Þ ¼ 3 8 6 þ 8 ¼ 152;
DðF3 Þ ¼ 3 8 3 þ 6 ¼ 78:
DðF2 Þ ¼ 3 8 3 þ 6 ¼ 78;
Applying step (a) of the above procedure yields:
1. For FEY(b; c): D(F3′ = c″ = b′ ⊕ c′) = 152
2. For FEY(a; c): D(F3′ = c″ = a′ ⊕ c′) = 78
3. For FEY(a; b): D(F2′ = b″ = a′ ⊕ b′) = 78
4. For FEY(c; b): D(F2′ = b″ = c′ ⊕ b′) = 152
5. For FEY(b; a): D(F1′ = a″ = b′ ⊕ a′) = 104
6. For FEY(c; a): D(F1′ = a″ = c′ ⊕ a′) = 78
The gates that result in the maximum positive change in D(Fi) for the variable
they affect are gates 1 and 4. Let gate 1 is selected, and then step (a) is repeated with
F3′(=c″) is used instead of F3(=c′). The following results are obtained:
1. For FEY(a; b): D(F2′ = b″ = a′ ⊕ b′) = 76
2. For FEY(c; b): D(F2′ = b″ = c″ ⊕ b′) = 76
3. For FEY(b; a): D(F1′ = a″ = b′ ⊕ a′) = 103
4. For FEY(c; a): D(F1′ = a″ = c″ ⊕ a′) = 148
Since no gate is identified, then step (b) is applied. The following results are
obtained:
1. For TOF3(a, b; c): D(F3″ = c″′ = a′ b′ ⊕ c″) = 76
2. For TOF3(a, c; b): D(F2′ = b″ = a′ c″ ⊕ b′) = 148
3. For TOF3(b, c; a): D(F1′ = a″ = b′ c″ ⊕ a′) = 77
The gate that results in the maximum positive change in D(Fi) for the variable it
affects is gate 2 (i.e., TOF3(a, c; b). Therefore, step (a) is applied using F2′(=b″)
instead of F2(=b′). The following results are obtained:
3.11
Spectral-Based Synthesis Method
99
1. For FEY(b; c): D(F3″ = c″′ = b″ ⊕ c″) = 152
2. For FEY(a; c): D(F3″ = c″′ = a′ ⊕ c″) = 144
3. For FEY(a; b): D(F2″ = b″′ = a′ ⊕ b″) = 148
4. For FEY(c; b): D(F2″ = b″′ = c″ ⊕ b″) = 148
5. For FEY(b; a): D(F1′ = a″ = b″ ⊕ a′) = 148
6. For FEY(c; a): D(F1′ = a″ = c″ ⊕ a′) = 148
Finally, gate 1 [i.e., FEY(b; c)] is selected and the synthesis procedure is ended,
because the problem is reduced to a set of 3 spectra each representing a unique
variable as follows:
a b
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
c
0
1
0
1
0
1
0
1
Circuit: FEY(b; c) TOF3(a, c; b) FEY(b; c).
3.12
Transformation-Based Network Synthesis
of Fredkin-Toffoli Cascade Gates
The synthesis algorithm of this method is a two-stage algorithm. First, a circuit is
constructed in a number of steps by inspecting the truth table of a reversible
function. The concept of a template is used in the second stage of the algorithm to
simplify the circuit found in the first stage. The basis for a template is a network
with m gates that realizes the identity function. If a sequence in the network to be
synthesized matches more than half of a template, then a transformation that
reduces the gate count can be applied [16–20].
Definition 3.13 For the set of domain variables {x1, x2… xn} the generalized
Toffoli gate has the form TOF(C; T), where C = {xi1, …, xik}, T = {xj} and
C \ T = ;. It maps the Boolean pattern (x1, x2 … xn) to (x1, x2, …, xj−1, xj ⊕ xi1xi2
… xik, xj+1, …, xn).
Definition 3.14 For the set of domain variables {x1, x2 … xn} the generalized
Fredkin gate has the form FRE(C; T), where C = {xi1, …, xik}, T = {xj, x‘ } and
C \ T = ;. It maps the Boolean pattern (x1, x2, …, xn) to {x1, x2, …, xj−1, x‘ , xj+1,
…, x‘1 , xj, x‘ þ 1 , …, xn) iff xi1xi2 … xik = 1.
100
3 Methods of Reversible Logic Synthesis
In other words, the generalized Fredkin gate interchanges bits xj and x‘ if and
only if corresponding product equals 1.
For both gate types, C will be called the control set and T will be called the
target set [17, 19, 20].
Toffoli gate networks (networks made of gates NOT, CNOT (Feynman), and
Toffoli) are denoted (NCT). NCT plus SWAP gates are denoted (NCTS); adding
Fredkin gates, then the group is denoted as (NCTSF). A NOT gate is the special
case of a Toffoli gate with no control inputs [i.e. TOF(; T)]. Likewise, a SWAP gate
is the special case of a Fredkin gate with no control inputs [i.e., FRE(; T)] [19]. The
set of generalized Toffoli and generalized Fredkin gates will be called the
Fredkin-Toffoli family.
Before describing the two algorithms of this method, it should be noted that the
function to be realized is given by a truth table, which has input patterns (a1 …, an)
on the left side and output patterns (b1 …, bn) on the right side. The input patterns
are arranged in lexicographical order.
The basic (unidirectional) algorithm:
The basic algorithm starts with an empty circuit (the identity function). At every
step of the synthesis algorithm some gates from the Fredkin-Toffoli family are
added to the end of the circuit (i.e., starting from the output).
Step 0. Take the narrowest gates and arrange them in a cascade so that they
bring the first output pattern in the truth table to the first input pattern. After adding
the gates to the cascade, update the output part of the table.
Step S (1 ≤ S ≤ 2n − 2). Without influencing the patterns of the lower order that
were put at their desired places in the previous steps of the algorithm, use the least
number of the narrowest gates to bring the output pattern to the form of correspondent input pattern.
Step 2n − 1. When all the 2n − 1 of previous patterns are in places, the last
patterns will automatically be correct [17, 20].
The bidirectional algorithm:
The basic algorithm worked from the output to input by adding the gates in one
direction starting from the end of desired cascade and ending at its beginning.
While in the bidirectional algorithm the network is constructed from the two ends
simultaneously by growing the number of gates from the two sides. The idea of the
two algorithms is the same: (applying the gates to match input with output part of
the truth table to each other by assuring that at each step of calculation there is at
least one pattern at its place). It makes sense that such a bidirectional algorithm on
average will be converged faster [20]. For each row of the truth table in order from
(0, 0, …, 0), it either transforms the output pattern to the input as described in the
unidirectional algorithm, or it performs the match by reordering rows of the truth
table, whichever requires less gates. If both require the same number of gates, the
gates identified in the unidirectional approach are used [17].
Table 3.18 refers to the basic (unidirectional) approach, and Table 3.19 illustrates the bidirectional algorithm. Each column in the tables shows the change of the
output part of the truth table as the gates from the previous steps are applied. The
3.12
Transformation-Based Network Synthesis of Fredkin-Toffoli Cascade Gates
101
Table 3.18 An example of the basic (unidirectional) synthesis algorithm
Input
abc
Output
000
111
001
001
010
000
011
100
100
010
101
101
110
011
111
110
Apply gates
S0
S1
S2
S3
S4
S5
S6
000
110
111
011
101
010
100
001
TOF
(;a)
TOF
(;b)
TOF
(;c)
000
001
011
111
110
101
100
010
FRE
(;b, c)
TOF
(c; a)
000
001
010
110
111
101
100
011
TOF
(b; c)
000
001
010
011
111
101
100
110
FRE
(b; a, c)
000
001
010
011
100
110
111
101
TOF
(a; c)
TOF
(a; b)
000
001
010
011
100
101
111
110
FRE
(a; b, c)
000
001
010
011
100
101
110
111
TOF
(a, b; c)
Table 3.19 Bidirectional synthesis algorithm of the example in Table 3.18
Input
abc
Output
000
111
001
001
010
000
011
100
100
010
101
101
110
011
111
110
Apply gates
S0
S1
S2
S3
S4
S5
S6
000
100
111
001
011
110
010
101
→
TOF
(;b)
000
001
111
100
110
011
010
101
←
FRE
(;a, c)
000
001
010
101
110
011
111
100
→
TOF
(b; a)
000
001
010
011
110
101
111
100
←
FRE
(c; a, b)
000
001
010
011
100
111
101
110
←
TOF
(a; b)
000
001
010
011
100
101
111
110
←
TOF
(a, c; b)
000
001
010
011
100
101
110
111
←
TOF
(a, b; c)
arrows in Table 3.19 indicate the direction of gate assignment (beginning of the
cascade → , or the end of the cascade ←). The resulting circuit of the unidirectional
algorithm has 11 gates (illustrated in Fig. 3.49a). The cascade of the bidirectional
algorithm consists of 7 gates, and the circuit is shown in Fig. 3.49b. The way that
the gates are drawn in Fig. 3.49 is a convention which is not related to the way the
gates are implemented.
Template simplification:
The circuits produced by the algorithms as described thus far frequently have gate
sequences that can be reduced. Template driven reduction methods have been
implemented. The idea of a template is to replace a sequence of gates with an
equivalent shorter sequence [19]. A template consists of a sequence of gates to be
102
3 Methods of Reversible Logic Synthesis
(a)
a
b
c
(b) a
b
c
Fig. 3.49 Circuits of the example: a in Table 3.18, b in Table 3.19
matched and the sequence of gates to be substituted when a match is found.
Templates with Toffoli gates only are described in [18]. Some templates with
Fredkin gates are introduced in [19], however, they are restricted to three inputs. All
templates with less than six gates are enumerated and classified in [16, 17, 20].
There are some disadvantages of this approach [21]:
1. Only algorithms for NCTSF library (set of gates) have been developed.
2. Simplifications of the circuits based on recognizing template may require a lot of
iterations. It is because, after each usage of a template, new template matches
may appear.
3. In some cases, the constructed circuits are far from optimal. It is because
transformations corresponding to the sequence of gates in an optimal circuit do
not yield a match of subsequent pairs of input and output assignments according
to the lexicographical order.
3.13
Heuristic Algorithm for Reversible Logic Synthesis
This is an incremental approach presented in [21], which uses shared binary
decision diagrams (SBDDs) for the representation of reversible functions (instead
of truth tables) and for measuring their complexity. Reversible gates are selected,
one at a time, based on the complexity of the reminder logic. A variety of reversible
gates have been proposed in the literature. However, the most widely used gates are
defined as follows:
1 1 NOT: a0 ¼ 1 a;
2 2 CNOT: a0 ¼ a; b0 ¼ a b;
3 3 Toffoli: a0 ¼ a; b0 ¼ b; c0 ¼ c ab;
2 2 SWAP: a0 ¼ b; b0 ¼ a;
3 3 Fredkin: a0 ¼ a; b0 ¼ b ab ac; c0 ¼ c ab ac:
3.13
Heuristic Algorithm for Reversible Logic Synthesis
103
where, a′, b′ and c′ are outputs of the gates; and a, b and c are their inputs. Each of
these gates is invertible (i.e., equal to its own inverse). Thus the equations for the
functions describing dependence of inputs on outputs (inverse mapping) have the
same form as the equations given above (after exchanging a, b, c with a′, b′, c′,
respectively). For each non-invertible gate it is possible to determine sets of
equations defining both forward and inverse mappings induced by the gate [21].
Definition 3.15 The complexity measure D(f) of an n * n reversible function f is
equal to D(f) = s(f) − n, where s(f) denotes the number of non-terminal nodes in the
reduced ordered SBDD of f with complemented edges. Thus, D(identity
function) = 0.
The algorithm:
In Fig. 3.50, the scheme of one basic step of the synthesis algorithm is shown. Let
G1 is the first (from the left side) gate of the circuit. The transformed n * n
reversible function fT (the reminder function) can be represented in the form of a
reduced ordered SBDD with complemented edges. The transformation shown in
Fig. 3.50 is iterated until D(f) equals 0.
The function f1(1)(y1, …, yn), …, fn(1)(y1, …, yn) are derived by substituting
x1 = g1(y1, …, yn), …, xn = gn(y1, …, yn) in the functions: f1(x1, …, xn), …, fn(x1,
…, xn).
In every step of the algorithm all gates are examined and for each of them SBDD
fT is constructed. Next, gates for which the size of the transformed function is
minimal are selected. If there is more than one such gate, then proceeding further
with all of them is required. The algorithm always terminated with the circuit
realizing the given function. Usually, more than one circuit was found. Thus, it is
possible to select the circuits having the minimal cost (gate count) for a given
reversible function. Such optimization is done on the global scale, in contrast to the
local decisions of the algorithms presented in the previous section. Also, this
approach works with arbitrary libraries of gates.
Example 3.10 Let f be a 3 * 3 reversible function defined as follows:
f 1ð0Þ ¼ ab bc ac
f 2ð0Þ ¼ a b ab bc ac
f 3ð0Þ ¼ b c
x1
.
.
xn
G1
y1
.
.
yn
f
T
f1(1) (y1, …, yn)
.
(y1, …, yn) .
fn(1) (y1, …, yn)
Fig. 3.50 A general scheme of one step of the algorithm
f1(x1, …, xn)
.
.
fn(x1, …, xn)
104
3 Methods of Reversible Logic Synthesis
a
b
c
Fig. 3.51 Circuit realization for the function in Example 3.10
If G1 is the CNOT gate with the control input being b and the target c. Thus,
according to the fact that this gate is invertible, the followings are obtained:
a ¼ a0
b ¼ b0
c ¼ c 0 b0 ;
these expressions are substituted for a, b, c into the expressions defining the
function f:
f 1ð1Þ ¼ ab bc ac ¼ b0 b0 c0 a0 c0
f 2ð1Þ ¼ a b ab bc ac ¼ a0 b0 c0 a0 c0
f 3ð1Þ ¼ b c ¼ c0
Similarly, transformations for the next gates shown in Fig. 3.51 are made (in the
order from left to right). For simplicity, the new variables after each transformation
are denoted using the same characters as for the previous names of variables (i.e.,
after each iteration a, b, c are used instead of a′, b′, c′). The transformed functions
are as follows:
f 1ð2Þ ¼ a b bc
f 1ð3Þ ¼ a b
f 1ð4Þ ¼ a
f 1ð5Þ ¼ a
f 2ð2Þ ¼ a bc
f 2ð3Þ ¼ a
f 2ð4Þ ¼ a b
f 2ð5Þ ¼ b
f 3ð2Þ ¼ c
f 3ð3Þ ¼ c
f 3ð4Þ ¼ c
f 3ð5Þ ¼ c
The SBDDs for these functions are presented in Fig. 3.52. The sequence of D
(f)’s is non-increasing: 5, 4, 2, 1, 1, 0 for the Fig. 3.52a–f, respectively (Fig. 3.52f
represents the identity function).
3.14
Constructive Synthesis of Reversible Circuits
by NOT and (n − 1)-CNOT Gates
A constructive synthesis algorithm for any n-bit (n > 2) reversible function is
presented in [22]. Such functions can be constructed by NOT and (n − 1)-CNOT
gates. Given any n-bit reversible function, there are N distinct input patterns different from their corresponding outputs, where N ≤ 2n. This function can be
realized by at most 2n · N (n − 1)-CNOT gates and 4n2 · N NOT gates.
3.14
Constructive Synthesis of Reversible Circuits …
(a)
(b)
(c)
(d)
(e)
(f)
Fig. 3.52 SBDDs for the functions calculated in Example 3.10
105
106
3 Methods of Reversible Logic Synthesis
Definition 3.16 A (n − 1)-CNOT is a n × n gate. It leaves (n − 1) inputs
unchanged, and inverts the other input iff all the (n − 1) inputs are 1 [23, 24]. This
gate is a generalized Toffoli gate.
The algorithm:
Step 1: Consider the truth table of the given binary reversible circuit f, each output
bit has 2n values, compare them with the input value, if the number of different
values is bigger than 2n−1, connect a NOT gate to this bit. After dealing with all
bits, count the changed vectors, if the number of the changed vectors is less than
that of the original circuit, then in step 2 decompose the reversible circuit dealt by
NOT gates. Otherwise, decompose the original reversible circuit.
Step 2: Write the reversible circuit in a product of cycles form. For every cycle (d1,
d2, …, dk), calculate the number ri of different bits between di and di+1, i = 1, 2, …,
k where dk+1 = d1. Let rj be the maximal number. Decompose the reversible circuit
by breaking the mapping relation from dj to dj+1 without increasing the number of
different bits between adjacent vectors.
ðd1 ; d2 ; . . .; dk Þ ¼ dj1 ; dj dj1 ; dj þ 1 ; dj þ 2 ; . . .; dj2
ð3:101Þ
Recursively repeating this process, the reversible circuit is decomposed to 2-cycles
(i.e., the use of the well-known result in group theory “any k-cycle can be factored
into a product of 2-cycles” [5]).
Step 3: Decompose every 2-cycle by NOT and (n − 1)-CNOT gates using the
following guidelines.
1. If between two n-dimensional vectors u and s, there is only one bit Bj different,
and q same bits are zeros. These zero bits are Bi1, …, Biq. Then,
ðu; sÞ ¼ Ni1 Niq Cj Niq Ni1
where N denotes NOT gate and C denotes (n − 1)-CNOT gate.
2. If two n-dimension vectors u and s have k bits different, then there is an ordered
set M = {d1, d2, …, dk+1} such that d1 = u, dk+1 = s and for any i, 1 ≤ i < k + 1,
there is only one bit different between di and di+1, and
ðu; sÞ ¼ ðd1 ; d2 Þðd2 ; d3 Þ. . .ðdk ; dk þ 1 Þðdk ; dk1 Þ. . .ðd2 ; d1 Þ
3. In order to make the number of NOT gates as small as possible, the following
two rules are used for constructing the ordered set M.
• If the number of 1’s in the vector u is more than that in s, then d1 = u, dk
+1 = s. Else, d1 = s, dk+1 = u.
• In the different bits between u and s, change the zero bit to one first, then
change one bit to zero bit.
3.14
Constructive Synthesis of Reversible Circuits …
Table 3.20 The ordered set
M of u and s
107
P1
P2
P3
P4
P5
Encode
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
d1 = s
d2
d3
d4
d5 = u
For example, if u ¼ h0; 1; 0; 0; 0i; s ¼ h0; 0; 1; 1; 1i, then k = 4, d1 = s, d5 = u
and, d2, d3, d4 are given in Table 3.20.
4. Remove pairs of adjacent NOT gates in the same wire when possible.
A new rule
If there exist two or more (dj) values (in step 2), then the following new rule should
be applied for minimal circuit synthesis.
(If there exist two or more (dj) values, then apply Eq. (3.101) for each (dj) and
calculate the sum of (rj) values for each case. The choice that yields a circuit with
minimal number of gates is that of minimal sum of (rj) values).
Example 3.11 It is given a binary reversible circuit f which has a truth table as
shown in Table 3.21.
Therefore, f = (a1, a8, a4, a7, a2, a3).
Step 1. The outputs P1, P2 and P3 have no over 23−1 = 4 different values with
inputs B1, B2 and B3, respectively. Thus, the input reversible circuit f is
considered without the need to cascade NOT gates after f.
Step 2. r1 = 3, r2 = 1, r3 = 2, r4 = 3, r5 = 2, r6 = 1.
There exist two dj values a1 and a7. The application of Eq. (3.101) to the first
case of dj values yields:
ð a1 ; a8 ; a4 ; a 7 ; a 2 ; a3 Þ ¼ ð a3 ; a1 Þ ð a3 ; a8 ; a4 ; a7 ; a2 Þ
The sum of the (ri) values = 1 + 2 + 1 + 2 + 3 + 2 = 11.
Table 3.21 A binary
reversible circuit f
Input
B2
B1
B3
Encoding
Output
P1
P2
P3
Encoding
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
a1
a2
a3
a4
a5
a6
a7
a8
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
a8
a3
a1
a7
a5
a6
a2
a4
0
0
1
1
0
0
1
1
1
1
0
1
0
0
0
1
108
3 Methods of Reversible Logic Synthesis
Now, Eq. (3.101) is applied to the second case of dj values giving:
ð a1 ; a8 ; a4 ; a 7 ; a 2 ; a3 Þ ¼ ð a4 ; a7 Þ ð a4 ; a2 ; a3 ; a1 ; a8 Þ
The sum of the (ri) values = 2 + 1 + 2 + 1 + 3 + 1 = 10.
According to the new rule, the second case will give the minimal circuit, and
consequently it is chosen to complete the design (the first case will give a circuit of
6 NOT and 9 (n − 1)-CNOT gates, while the second case as will be shown later
gives a circuit of 4 NOT and 7 (n − 1)-CNOT gates. That clarifies the importance of
the new rule). Now, repeat the process to decompose the reversible circuit to
2-cycles.
ð a4 ; a2 ; a 3 ; a 1 ; a8 Þ ¼ ð a3 ; a1 Þ ð a3 ; a8 ; a4 ; a2 Þ
ð a3 ; a 8 ; a 4 ; a2 Þ ¼ ð a4 ; a2 Þ ð a4 ; a3 ; a8 Þ
ða4 ; a3 ; a8 Þ ¼ ða4 ; a3 Þða4 ; a8 Þ
Therefore,
f ¼ ða1 ; a8 ; a4 ; a7 ; a2 ; a3 Þ ¼ ða4 ; a7 Þða3 ; a1 Þða4 ; a2 Þða4 ; a3 Þða4 ; a8 Þ
Step 3. By applying the four guidelines, the followings are obtained:
a 4 ¼ 1 1 0 ¼ d1 ¼ s
a 8 ¼ 1 1 1 ¼ d2
a 7 ¼ 0 1 1 ¼ d3 ¼ u
Therefore,
ða4 ; a7 Þ ¼ ða4 ; a8 Þða8 ; a7 Þða8 ; a4 Þ ¼ C3 C1 C3
ða3 ; a1 Þ ¼ N1 N3 C2 N1 N3
ða4 ; a2 Þ ¼ N3 C2 N3
ða4 ; a3 Þ ¼ N3 C1 N3
ð a4 ; a8 Þ ¼ C 3
Consequently,
f ¼ C3 C1 C3 N1 N3 C2 N1 C2 C1 N3 C3 :
The synthesis process is finished, and f is decomposed into the product of 4 NOT
gates and 7 (n − 1)-CNOT gates, shown in Fig. 3.53.
3.15
Summary
109
B1
P1
B2
P2
B3
P3
Fig. 3.53 Decomposed circuit for f
3.15
Summary
This chapter has introduced the most twelve well-known and popular reversible
logic synthesis methodologies. These are: RDTs, RDDs, lattice circuits, fast
transform circuits, group-theoretic representations, RMRA, RPGA, cascade circuits, spectral-based synthesis, transformation-based synthesis using
Fredkin-Toffoli gates, heuristic algorithm based on SBDDs, and constructive synthesis by NOT and (n − 1)-CNOT gates. Each of these methods has its own idea,
concepts, and applications. In other words, they perform logic synthesis of reversible circuits but with different flavors. Also, synthesis of ternary in addition to
binary functions are made. However, synthesis of multi-valued functions can
similarly be made. The following chapter introduces an evaluation of the implementation of logic functions using the various types of reversible logic structures
and methods that have been introduced in this chapter.
References
1. S. Brown, Z. Vranesic, Fundamentals of Digital Logic with VHDL Design (The McGraw–Hill
Companies Inc., Singapore, 2000)
2. P.K. Chan, S. Mourad, Digital Design Using Field Programmable Gate Arrays (PTR Prentice
Hall, New Jersey, 1994)
3. A.N. Al-Rabadi, Reversible Logic Synthesis: From Fundamentals to Quantum Computing
(Springer, Berlin, 2004)
4. A.N. Al-Rabadi, Three-dimensional Lattice Logic Circuits, Part I: Fundamentals, vol. 18, no.
1 (Facta Universitatis, University of Nis, Yugoslavia, April 2005), pp. 1–13
5. A.N. Al-Rabadi, New classes of Kronecker-based reversible decision trees and their
group-theoretic representation, in Proceedings of the International Workshop on Spectral
Methods and Multirate Signal Processing (SMMSP), Vienna, Austria, pp. 233–243, 11–12
Sept 2004
6. A.N. Al-Rabadi, Spectral techniques in the reversible logic circuit synthesis of switching
functions, in Proceedings of the International Workshop on Spectral Methods and Multirate
Signal Processing (SMMSP), Vienna, Austria, pp. 271–279, 11–12 Sept 2004
7. S.E. Lyshevski, Three dimensional multi-valued design in nanoscale integrated circuits, in
Proceedings of the IEEE 35th International Symposium on Multiple-Valued Logic
(ISMVL’05), 2005
8. A.N. Al-Rabadi, Three-Dimensional Lattice Logic Circuits, Part II: Formal Methods, vol. 18,
no. 1 (Facta Universitatis, University of Nis, Yugoslavia, April 2005), pp. 15–28
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3 Methods of Reversible Logic Synthesis
9. P. Dziarzanskii, V.P. Shmerko, S.N. Yanushkevich, Representation of logical circuits by linear
decision diagrams with extension to nanostructures. Autom. Remote Control 65(6), 920–937
(2004)
10. M.A. Perkowski, M. Chrzanowska-Jeske, Y. Xu, Lattice diagrams using Reed-Muller logic, in
Proceedings of RM’97, Oxford University, U.K., pp. 85–102, 19–20 Sept 1997
11. M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song, A.
Al-Rabadi, L. Jozwiak, A. Coppola, B. Massey, Regular realization of symmetric functions
using reversible logic, in Proceedings of EUROMICRO Symposium on Digital Systems Design
(Euro-Micro’01), Warsaw, Poland, pp. 245–252, Sept 2001
12. A.N. Al-Rabadi, Three-Dimensional Lattice Logic Circuits, Part III: Solving 3D Volume
Congestion Problem, vol. 18, no. 1 (Facta Universitatis, University of Nis, Yugoslavia, April
2005), pp. 29–43
13. A.T.S. Bashaga, Three-dimensional synthesis of ternary reversible lattice logic circuits. M.Sc.
Thesis, Department of Electrical Engineering, College of Engineering, University of Baghdad,
2007
14. M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song, A.
Al-Rabadi, L. Jozwiak, A. Coppola, B. Massey, Regularity and symmetry as a base for
efficient realization of reversible logic circuits, in Proceedings of IWLS’01, pp. 90–95, Lake
Tahoe, California, USA, 12–15 June 2001
15. D.M. Miller, Spectral and two-place decomposition techniques in reversible logic, in
Proceedings of the IEEE Midwest Symposium on Circuits and Systems (MWSCAS 02), II 493–
II 496, Aug 2002
16. D. Maslov, Reversible logic synthesis. Ph.D. Thesis, The Faculty of Computer Science, The
University of New Brunswick, Canada, 2003
17. D. Maslov, G.W. Dueck, D.M. Miller, Synthesis of Fredkin-Toffoli reversible networks. IEEE
Trans. Very Large Scale Integr. VLSI Syst. 13(6), 765–769 (2005)
18. D.M. Miller, D. Maslov, G.W. Dueck, A transformation based algorithm for reversible logic
synthesis, in Proceedings of the Design Automation Conference, DAC 2003, Anaheim,
California, USA, pp. 318–323, 2–6 June 2003
19. G.W. Dueck, D. Maslov, D.M. Miller, Transformation-based synthesis of networks of
Toffoli/Fredkin gates, in IEEE Canadian Conference on Electrical and Computer
Engineering, CCECE 2003, Montreal, Canada, May 2003
20. D. Maslov, G.W. Dueck, D.M. Miller, Fredkin/Toffoli templates for reversible logic synthesis,
in Proceedings of the International Conference on Computer-Aided Design (ICCAD 2003),
San Jose, California, USA, 9–13 Nov 2003
21. P. Kerntopf, A new heuristic algorithm for reversible logic synthesis, in Proceedings of the
41st annual Conference on Design Automation (DAC 2004), California, USA, pp. 834–837,
7–11 June 2004
22. G. Yang, F. Xie, X. Song, W.N.N. Hung, M.A. Perkowski, A constructive algorithm for
reversible logic synthesis, WCCI-2006. Web.cecs.pdx.edu/*whung/papers/WCCI-2006
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Jose, California, USA, pp. 125–132, 10–14 Nov 2002
24. V.V. Shende, A.K. Prasad, I.L. Markov, J.P. Hayes, Synthesis of reversible logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), 710–722 (2003)
Chapter 4
Evaluation of the Reversible Logic
Synthesis Methodologies
This chapter introduces an evaluation of the implementation of the reversible
structures that have been presented in Chap. 3 to realize logic functions. This
evaluation gives an important first look to some of the weaknesses, strengths, and
properties of the previously introduced reversible structures.
The remainder of this chapter is organized as follows. Section 4.1 summarizes
the idea of the NPN-classification of logic functions. Next a new procedure, based
on the number of gates and garbage outputs of the circuit, to evaluate the used
reversible synthesis method is introduced in Sect. 4.2. Section 4.3 explains the
advantages and disadvantages of each of the various reversible logic synthesis
methodologies given as a comparison table. Summary of the chapter is presented in
Sect. 4.4.
4.1
NPN-Classification of Logic Functions
There exist classification methods to cluster logic functions into families of functions. Two important operations that produce equivalence classes of logic functions
are negation and permutation. Accordingly, the NPN-classification will result. An
NPN-Equivalence class represents a family of identical functions obtained by the
operations of negation or permutation of one or more variables, and also negation of
function [1]. Table 4.1 lists 3-variable Boolean functions, for the non-degenerate
classes (i.e., the classes depending on all three variables). For example, the set of
all possible Boolean functions that are included in class 1 in Table 4.1 for the
representative function: F ¼ x1 x2 þ x2 x3 þ x1 x3 is fF1 ¼ x1 x2 þ x2 x3 þ x1 x3 ;
F2 ¼ x1 x2 þ x2 x3 þ x1 x3 ; F3 ¼ x1 x2 þ x2 x3 þ x1 x3 ; F4 ¼ x1 x2 þ x2 x3 þ x1 x3 ;
F5 ¼ x1 x2 þ x2 x3 þ x1 x3 ; F6 ¼ x1 x2 þ x2 x3 þ x1 x3 ; F7 ¼ x1 x2 þ x2 x3 þ x1 x3 ,
and F8 ¼ x1 x2 þ x2 x3 þ x1 x3 g, which encompasses a total of eight functions.
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_4
111
112
4 Evaluation of the Reversible Logic Synthesis Methodologies
Table 4.1 NPN-equivalence classes for non-degenerate Boolean functions of three binary
variables [1]
NPN class
Representative function
Number of functions
1
2
3
4
5
6
7
8
9
10
F ¼ x1 x2 þ x2 x3 þ x1 x3
F ¼ x1 x2 x3
F ¼ x1 þ x2 þ x3
F ¼ x1 ðx2 þ x3 Þ
F ¼ x1 x2 x3 þ x1 x2 x3
F ¼ x1 x2 x3 þ x1 x2 þ x1 x3
F ¼ x1 ðx2 x3 þ x2 x3 Þ
F ¼ x1 x2 þ x2 x3 þ x1 x3
F ¼ x1 x2 x3 þ x1 x2 x3 þ x1 x2 x3
F ¼ x1 x2 x3 þ x2 x3
8
2
16
48
8
24
24
24
16
48
4.2
New Evaluation Procedure of Reversible
Synthesis Methods
Traditional design methods use the number of gates as complexity measure. In
reversible logic there is one more factor, which is more important than the number
of gates used, namely the number of garbage outputs. In some cases garbage is
unavoidable. For example, a single output function of n variables will require at
least n − 1 garbage outputs, since the reversibility necessitates an equal number of
outputs and inputs.
In [2] an example is given to illustrate the importance of minimizing the garbage
outputs. It is that: if there is a 5-input 3-output function to be realized in a reversible
method on a 7 qubit (quantum bit) quantum computer, but the design requires 7
additional garbage outputs, resulting in a 10-input 10-output reversible function.
Therefore, that computer will not be able to implement this design. Hence, in case
of choosing between increase of the garbage and increase of the number of gates to
be used in a reversible implementation, the preference should be given to the design
method delivering the minimum garbage.
To characterize garbage in the outputs, the following criterion is to be considered. This criterion is: (If the structure produces only the output function and the
inputs as outputs, then there is no garbage in the output of the structure. Otherwise,
there is garbage in the output of the forward reversible circuit and there is a need
to create the reversible inverse circuit to eliminate the garbage). Consequently,
outputs of a reversible circuit that are generated by propagating the inputs through
the reversible circuit are not considered as garbage.
Example 4.1 Table 4.2 shows the results of synthesizing the Boolean function
f = ab + bc + ac, which is the representative of class 1 for NPN classification of
4.2 New Evaluation Procedure of Reversible …
113
Table 4.2 Results of applying the reversible synthesis methods to the symmetric Boolean
function f in Example 4.1
1
2
3
4
5
6
7
8
9
10
11
12
Synthesis method
Number of garbage
Number of gates
GGS
RDT
RDD
Lattice circuits
Fast transform
Group-theoretic
RMRA
RPGA
Reversible cascade
Spectral method
Transformation method
Heuristic algorithm
Constructive algorithm
7
4
6
4
1
4
4
0
2
2
2
2
7
4
6
8
2
5
3
3
7
3
5
13
21
12
18
16
4
13
11
3
11
7
9
17
Boolean functions (see Table 4.1) that encompass eight Boolean functions, using
reversible synthesis methods introduced in the previous chapter. A new evaluation
procedure of the reversible synthesis methods in Table 4.2 is presented here. It
depends on the number of gates and the number of garbage outputs of the reversible
circuit. Of course, the synthesis method that produces circuits with the lowest count
of reversible gates as well as the lowest number of garbage outputs is the best
choice. As mentioned above, the preference should be given to the case of minimum garbage. So, it is suggested to calculate the sum of the number of gates with
twice the number of garbage outputs. This sum is denoted as GGS
(Gate-Garbage-Sum) factor. The synthesis method that yields the minimal value of
GGS is the best choice. It is clear from Table 4.2 that the reversible cascade method
Table 4.3 Results of applying the reversible synthesis methods to the non-symmetric Boolean
function (g) in Example 4.2
1
2
3
4
5
6
7
8
9
10
11
12
Synthesis method
Number of garbage
Number of gates
GGS
RDT
RDD
Lattice circuits
Fast transform
Group-theoretic
RMRA
RPGA
Reversible cascade
Spectral method
Transformation method
Heuristic algorithm
Constructive algorithm
7
3
7
3
2
1
8
1
–
3
–
–
7
3
7
6
2
2
6
3
–
5
–
–
21
9
21
12
6
4
22
5
–
11
–
–
114
4 Evaluation of the Reversible Logic Synthesis Methodologies
Table 4.4 Advantages and disadvantages of various reversible logic synthesis methods
1
Type
Reversible decision
trees (RDTs)
2
Reversible decision
diagrams (RDDs)
3
Reversible lattices
4
Reversible fast
transform circuits
(RFTCs)
5
Group-theoretic
representations
6
Reversible
modified
reconstructability
analysis (RMRA)
7
Reversible
programmable gate
array (RPGA)
Advantages
1. Regularity
2. Methodological
3. Applied for incompletely
specified functions
4. Good for multi-output functions
1. Exhibit certain regularities
2. Methodological
3. Applied for incompletely
specified functions
4. Good for multi-output functions
5. Many types of RDDs exist from
which minimal size reversible
structure could be found
1. Regularity
2. Methodological
3. Applied for incompletely
specified functions
1. Regularity
2. Methodological
3. Applied for incompletely
specified functions
4. Good for multi-output functions
1. Can be expanded to incompletely
specified functions,
2. Can be created for efficient
realization of multiple-input
multiple-output (MIMO)
functions (circuits),
3. Many types of Group-theoretic
circuits exist from which minimal
size reversible structure could be
found,
4. Can produce a comparative small
size reversible circuit
1. Can produce a comparative small
size reversible circuit
2. Methodological
1. Good for multi-output functions
2. Can be extended to incompletely
specified functions
3. Uses symmetry
Disadvantages
1. Produces garbage
2. For functions with many
inputs, RDTs can be
exponential in size
1. Produces garbage
2. For functions with many
inputs, RDDs can be
exponential in size
1. Produces garbage
2. For functions with many
inputs, lattices can be
exponential in size
3. Inefficient for
multi-output functions
1. Produces garbage
2. For functions with many
inputs, RFTCs can be
exponential in size
1. Produces garbage
2. Not methodological and
depends on search
3. Need for a reversible
specification
1. Produces garbage
2. Inefficient for
multi-output functions
3. Does not realize ESOP
forms
4. Inefficient for
incompletely specified
functions
1. Produces garbage
2. Inefficient for strongly
non-symmetric functions
(continued)
4.2 New Evaluation Procedure of Reversible …
115
Table 4.4 (continued)
Type
Reversible cascades
Advantages
1. Good for multi-output functions
2. Can be extended to incompletely
specified functions
3. No garbage is produced on
average
4. Good for quantum circuits
9
Reversible spectral
method
1. Methodological
2. Good for multi-output functions
10
Reversible
Transformation
method
1. Methodological
2. Good for multi-output functions
3. Produce minimal garbage outputs
4. It can handle incompletely
specified functions
11
Reversible heuristic
algorithm
1. Methodological
2. Good for multi-output functions
3. Work with arbitrary libraries of
gates
4. Produce several circuits for a
given function
12
Reversible
constructive
algorithm
1. Methodological
2. Good for multi-output functions
8
Disadvantages
1. Not methodological and
depends on search
2. Has a single constant
garbage at the input
3. For functions with many
inputs, cascades can be
exponential in size
1. Produces garbage
2. Inefficient for
non-symmetric functions
3. Not applied for
incompletely specified
functions
4. It scales badly
5. Requires a reversible
specification
6. only applied for (NCTF)
library of gates
1. Inefficient for strongly
non-symmetric functions
2. For functions with many
inputs, the circuit can be
exponential in size
3. Only applied for
(NCTSF) library of gates
4. Simplification of the
circuits based on
recognizing templates,
which may require a lot
of iterations
1. Produces garbage
2. Inefficient for
non-symmetric functions
3. Not applied for
incompletely specified
functions
4. Selecting reversible gates
based on searching for
minimal complexity
1. Produces garbage
2. Inefficient for
non-symmetric functions
3. Not applied for
incompletely specified
functions
4. It scales badly
5. Only applied for
(NCT) library of gates
116
4 Evaluation of the Reversible Logic Synthesis Methodologies
gives the lowest value of GGS. It synthesizes the network of Example 4.1 with 3
gates only and with no garbage output.
Example 4.2 The function f in Example 4.1 is a symmetric function. In this
example, the realization of a non-symmetric Boolean function g = ab + ac using the
same methods used in Example 4.1 is to be considered. The Boolean function g is
the representative of class 4 for the NPN classification of Boolean functions (see
Table 4.1) that encompass 48 Boolean functions. Table 4.3 illustrates the results of
applying the synthesis methods to the function g. It is clear that the RMRA
(Reversible Modified Reconstructability Analysis) synthesis method has the lowest
value of GGS, and consequently it gives the minimal circuit, which consists of two
gates and one garbage output. The three synthesis methods (spectral method,
heuristic algorithm and constructive algorithm) are inefficient for non-symmetric
functions.
4.3
Comparison Between the Various Reversible
Synthesis Methodologies
Some of the introduced reversible synthesis methods possess certain advantages
over the other methods, and vice versa. Table 4.4 shows some properties that have
been observed so far when synthesizing reversibly the logic functions. For example,
it can be observed (from Table 4.4) that RPGA is very suitable for multi-output
functions. Also, as the reversible synthesis using reversible cascades does not
produce garbage in the outputs on average, it has been shown that this type of
synthesis is very well suited for quantum computing as will be shown in the
quantum logic circuits introduced in Chap. 6.
4.4
Summary
This chapter has introduced an evaluation of the various implementations of the
reversible structures that have been presented in Chap. 3. This evaluation produces
an important first look to some of the weaknesses, strengths, and properties of the
previously introduced reversible structures. The reversible circuits are highly
optimized in terms of number of gates and garbage outputs.
Chapter 6 will introduce the physical quantum operational notation and quantum
circuits that would be used to construct the counterparts of the reversible structures
from Chap. 3.
Next chapter will introduce the synthesis of the reversible sequential logic circuits (the other type of reversible logic circuits).
References
117
References
1. A.N. Al-Rabadi, Reversible Logic Synthesis: From Fundamentals to Quantum Computing
(Springer, Berlin, 2004)
2. D. Maslov, G.W. Dueck, Garbage in reversible designs of multiple output functions, in
Proceedings of the 6th International Symposium on Representations and Methodology of
Future Computing Technologies (RM 2003), Trier, Germany, pp. 162–170, 2003
Chapter 5
Reversible Sequential Logic Circuits
Recent work has begun to investigate the advantages of using reversible logic for
the design of circuits. The majority of work, however, has limited itself to combinational logic. Researchers are recently beginning to suggest possibilities for
sequential implementations [1]. As far as it can be discovered (due to the survey of
literature) the first work to design reversible sequential circuits is in 2005 [2].
In order to lie down the foundations of reversible sequential logic circuits, the
design of various flip flops (Sect. 5.1) with practical examples of some complex
reversible sequential circuits (Sect. 5.2) are provided within this chapter. Novel
optimal designs of reversible sequential elements are introduced in Sect. 5.3. The
idea of a recent work to synthesize multiple-valued reversible sequential circuits is
given in Sect. 5.4. Summary of the chapter is presented in Sect. 5.5.
5.1
Reversible Flip Flops
Reversible logic synthesis of sequential logic differs from combinational logic in
that the output of the logic device is dependent not only on the present inputs to the
device, but also on past inputs, i.e., the output of a sequential logic device depends
on its present internal state and the present inputs. The design of complex system
will require sequential circuits based on flip flops. The flip flops that are synthesized
using reversible logic are RS flip flop, JK flip flop, D flip flop, T flip flop, and
Master slave flip flop. Thus all the pulse as well as edge triggered flip flops are
synthesized using reversible logic. The circuits are highly optimized in terms of
number of gates and garbage outputs. The modularization approach (i.e., synthesizing small circuits and thereafter using them to construct bigger circuits) is used
for designing the optimal reversible flip flops. The reversible gates used to design
the reversible flip flops are AND, NAND, NOR, NOT and Copying. The SALEEM
gate (Sect. 3.9.3) is chosen to propose designs of the reversible flip flops, because it
can fulfill all the above logic operations (see Table 3.15).
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_5
119
120
5 Reversible Sequential Logic Circuits
5.1.1
Reversible RS Flip Flop
Figure 5.1 shows the RS flip flop designed from conventional irreversible gates.
Figure 5.2 shows the RS flip flop designed from the reversible equivalent gates. The
SALEEM-II gate acts here as a NOR gate. The circuit in Fig. 5.2 will be a common
unit in all of the following reversible flip flops. It is evaluated in terms of number of
reversible gates used and garbage outputs produced.
R
Q
S
Fig. 5.1 Conventional RS flip flop
SALEEM-II
R
1
S
1
A
P
B
Q
C
R
A
P
B
Q
C
R
SALEEM-II
Fig. 5.2 Proposed reversible RS flip flop
5.1 Reversible Flip Flops
121
Table 5.1 Evaluation of the proposed reversible RS flip flop
Proposed circuit
Existing circuit [2]
Number of gates
Number of garbage outputs
2
4
2
4
Table 5.1 shows the evaluation of the proposed reversible RS flip flop compared
with the circuit in [2]. In [2] all types of flip flops are designed using three different
types of reversible gates (Fredkin gate, Feynman gate, and New gate).
5.1.2
Reversible Clocked RS Flip Flop
Figure 5.3 shows the clocked RS flip flop designed from conventional irreversible
gates. Figure 5.4 shows the clocked RS flip flop designed from the reversible
equivalent gates. The proposed circuit of the flip flop is evaluated in terms of
number of reversible gates used and garbage outputs produced.
R
Q
CP
(Clock Pulses)
S
Fig. 5.3 Conventional clocked RS flip flop
SALEEM-II
A
P
R
B
Q
0
C
R
A
P
S
B
Q
0
C
R
R
Circuit
in
CP
SALEEM-II
Fig. 5.4 Proposed reversible clocked RS flip flop
S
Fig.5.2
122
5 Reversible Sequential Logic Circuits
Table 5.2 Evaluation of the proposed reversible clocked RS flip flop
Proposed circuit
Existing circuit [2]
Number of gates
Number of garbage outputs
4
6
5
8
Table 5.2 shows the evaluation of the proposed reversible clocked RS flip flop.
5.1.3
Reversible D Flip Flop
In the D flip flop, the D input goes directly to the S input and its complement is
applied as an R input. Figure 5.5 shows the D flip flop designed from irreversible
gates. Figure 5.6 shows the D flip flop designed from the reversible equivalent
gates.
The proposed circuit of the D flip flop is evaluated in terms of number of
reversible gates used and garbage outputs produced. Table 5.3 shows the evaluation
of the proposed reversible D flip flop.
R
Q
CP
D
S
Fig. 5.5 Conventional D flip flop
SALEEM-II
Feynman
A
P
B
Q
0
C
R
CP
A
P
B
Q
C
R
–
1
D
D
0
CP
CP
D.CP
SALEEM-II
Fig. 5.6 Proposed reversible D flip flop
R
–
Circuit
in
S
Fig.5.2
–
5.1 Reversible Flip Flops
123
Table 5.3 Evaluation of the proposed reversible D flip flop
Proposed circuit
Existing circuit [2]
5.1.4
Number of gates
Number of garbage outputs
5
7
5
8
Reversible JK Flip Flop
A JK flip flop can be considered as a refinement of the RS flip flop since the
indeterminate state (S = 1 and R = 1) of the RS type is defined in the JK type.
The JK flip flop switches to its complement state when both J and K inputs are high
(logic 1) simultaneously. Figure 5.7 shows the JK flip flop designed from conventional irreversible gates. Figure 5.8 shows the JK flip flop designed from the
reversible equivalent gates.
R
K
Q
CP
J
S
Fig. 5.7 Conventional JK flip flop
SALEEM-II
J
0
A
P
B
Q
A
P
R
B
Q
C
R
A
P
B
Q
C
R
C
CP
SALEEM-II
J.CP
0
CP
A
P
K
B
Q
0
C
R
SALEEM-II
S
CP
Circuit
in
K.CP
0
SALEEM-II
Fig. 5.8 Proposed reversible JK flip flop
R
Fig.5.2
124
5 Reversible Sequential Logic Circuits
Table 5.4 Evaluation of the proposed reversible JK flip flop
Proposed circuit
Existing circuit [2]
Number of gates
Number of garbage outputs
6
10
7
12
Table 5.4 shows the evaluation of the proposed reversible JK flip flop.
5.1.5
Reversible T Flip Flop
If both the J and K inputs of the JK flip flop are tied together, then the T flip flop is
obtained. Figure 5.9 shows the T flip flop designed from conventional irreversible
gates. Figure 5.10 shows the T flip flop designed from the reversible equivalent
gates. Table 5.5 shows the evaluation of the proposed reversible T flip flop.
R
T
Q
CP
S
Fig. 5.9 Conventional T flip flop
SALEEM-II
CP
A
P
T
B
Q
0
C
R
SALEEM-II
CP.T
CP.T
0
A
P
B
Q
C
R
A
P
B
Q
C
R
S
Circuit
in
0
Feynman
CP.T
0
SALEEM-II
Fig. 5.10 Proposed reversible T flip flop
R
Fig.5.2
5.1 Reversible Flip Flops
125
Table 5.5 Evaluation of the proposed reversible T flip flop
Proposed circuit
Existing circuit [2]
5.1.6
Number of gates
Number of garbage outputs
6
10
6
12
Reversible Master-Slave Flip Flop
A master-slave flip flop is constructed from two separate flip flops in which one
circuit serves as a master and the other as a slave [2]. Figure 5.11 shows the
conventional master–slave JK flip flop. Figure 5.12 shows the reversible
master-slave JK flip flop designed from the reversible equivalent gates. Table 5.6
shows the evaluation of the proposed reversible master-slave JK flip flop.
R
K
R
Q
J
S
S
CP
Fig. 5.11 Conventional master-slave JK flip flop
SALEEM-II
SALEEM-II
A
P
J
B
Q
0
C
R
CP
A
P
K
B
Q
0
C
R
SALEEM-II
1
A
P
1
B
Q
C
R
A
P
A
P
B
Q
0 C
R
A
P
B
Q
C
R
SALEEM-II
CP
SALEEMII Q
B
J.CP
0
C
A
R
S
Circuit
in
Fig.5.2
P
R
K.CP
0
B
Q
C
R
SALEEM-II
Fig. 5.12 Proposed reversible master-slave JK flip flop
0
SALEEM-II
S
Circuit
in
Fig.5.2
R
126
5 Reversible Sequential Logic Circuits
Table 5.6 Evaluation of the proposed reversible master-slave JK flip flop
Proposed circuit
Existing circuit [2]
Number of gates
Number of garbage outputs
11
18
13
21
The reversible master-slave versions of the various flip flops can also be
designed using the same approach used in the above design. Thus, the basic units
required for the design of the complex sequential circuits have been provided,
which can be appropriately used to design complex circuits [3].
5.1.7
The Superiority of Using the SALEEM Gate
in Reversible Flip Flops Design
The proposed designs of reversible flip flops, discussed in the previous
sub-Sections, are based on the new SALEEM reversible gate presented in Chap. 3.
The evaluation Tables (5.1, 5.2, 5.3, 5.4, 5.5 and 5.6) show clearly the superiority
of the proposed reversible flip flops over those given in [2], in which the designs are
based on three different types of reversible gates (as mentioned in Sect. 5.1.1).
Another work based on using Fredkin gate in logic synthesis of reversible flip
flops is given in [3]. Also, similar proposed designs of reversible flip flops based on
using the Kerntopf gate have been achieved. Due to limitation of space, the details
of these designs are not discussed here. Table 5.7 shows clearly the superiority of
using the SALEEM reversible gate over the other types of reversible gates in
reversible logic synthesis of sequential circuits.
5.2
Complex Reversible Sequential Circuits
The reversible D flip flop is used in the implementation of more complex reversible
sequential circuits [3]. The following is some examples of such circuits. Figure 5.13
shows a reversible shift register built from the proposed reversible D flip flop. Each
clock pulse shifts the contents of the register one bit position to the right.
Figure 5.14 shows a reversible serial transfer of data from register A to register B
using the proposed D flip flop. Figure 5.15 shows a reversible serial adder built
from the proposed reversible sequential circuits. The two binary numbers to be
added are stored in two shift registers. Bits are added one pair at a time, sequentially, through a reversible full adder. A full adder designed using a single reversible
TSG gate is the most optimal in terms of the number of reversible gates and garbage
outputs, as discussed in [4] and the literature cited there. The TSG gate is shown in
Fig. 5.16. The full adder designed using TSG in Fig. 5.17 requires only one
reversible gate (one TSG gate) and produces only two garbage outputs.
6
14
15
18
20
37
2
4
5
6
6
11
RS
Clocked RS
D
T
JK
Master-slave
(JK)
2
5
5
6
7
13
Proposed circuit (using
SALEEM gate)
No. of
Garbage
GGS
gates
outputs
Reversible flip
flop type
4
6
6
8
8
14
4
8
7
8
10
16
12
22
20
24
28
46
Proposed circuit (using
Kerntopf gate)
No. of
Garbage
GGS
gates
outputs
Table 5.7 The superiority of using the SALEEM gate in reversible sequential circuits
8
7
22
–
9
–
13
–
11
10
34
4
8
8
12
12
21
12
22
23
34
34
60
–
4
6
7
10
10
18
Garbage
outputs
No. of
gates
GGS
No. of
gates
Garbage
outputs
Existing circuit [3]
Existing circuit [2]
–
35
–
30
27
90
GGS
5.2 Complex Reversible Sequential Circuits
127
128
5 Reversible Sequential Logic Circuits
SI
Serial Input
CP
CP
A
P
0
B
Q
C
0
SO Serial
Output
Reversible
D flip flop
Reversible
D flip flop
Reversible
D flip flop
Reversible
D flip flop
CP
0
R
SALEEM-II
0
B
0
C
CP
P
A
P
A
Q
R
CP
CP
0 B
Q CP
0
0
0 C
0
0
SALEEM-II
R
SALEEM-II
A
P
CP
B
Q
CP
C
R
0
SALEEM-II
Fig. 5.13 Reversible shift register built from reversible D flip flop
SI
Serial
Input
Reversible Shift
Register A
CP
SO
SO
P
A
CP
0
B
Q
0
C
R
SO
0
SALEEM-II
Shift Control
A
P
Clock
B
Q
0
C
R
SI
SO
Reversible Shift
Register B
SALEEM-II
Serial
Output
CP
Fig. 5.14 Serial transfer from reversible register A to reversible register B
SI
CP
External
Input
SI
CP
Shift
right
A
P
Clock
B
Q
0
C
R
0
0
SALEEM-II
A
P
B
Q
C
R
CP
0
0
A
P
B
Q
C
R
SO
Reversible Shift
Register B
SO B
Sum
Reversible
Full Adder
Cout
Cin
CP
0
CP
SALEEM-II
A
Reversible Shift
Register A
SALEEM-II
0
Q
Reversible
D flip flop
Clear
Fig. 5.15 Reversible serial adder
D
CP
5.3 Novel Reversible Sequential Elements
129
Fig. 5.16 Reversible TSG gate
Fig. 5.17 Reversible TSG gate as full adder
5.3
Novel Reversible Sequential Elements
Methods for design of reversible flip flop circuits based on the characteristic
equations of the flip flops are introduced in [5, 6]. These methods of design give
more optimal circuits than the direct transformation methods described in Sect. 5.1.
These methods require the derivation of the truth table from the characteristic
equation of the required flip flop. This truth table is irreversible, and it is converted
to a reversible truth table by adding garbage outputs (as necessary) to have an equal
numbers of inputs and outputs. Then, this reversible table is realized as a reversible
circuit. The following is a description of the designs of reversible flip flops using
this approach and utilizing the SALEEM gates.
5.3.1
New Design of Reversible T Flip Flop
The characteristic equation of the T flip flop is:
Qþ ¼ Q ðT CLKÞ
where, Qþ is the next state output value of the flip flop, and Q is the present state
output value. The new circuit (Fig. 5.18) consists of two reversible gates and
produces two garbage outputs (outputs that are not subsequently used). This is
exactly the same that obtained in [5]. But, the new circuit gives the two complementary outputs Qþ and Qþ , while the circuit in [5] gives the output Qþ only. That
is due to the use of the SALEEM gate.
The wire which connects Qþ to Q is a unit wire with a specific delay. This delay
is the time difference of the Q and Qþ signals.
130
5 Reversible Sequential Logic Circuits
SALEEM-I
SALEEM-III
T
A
P
CLK
B
Q
Q
C
R
G
1
A
P
CLK
0
B
Q
Q+
C
R
Q+
Q+
Fig. 5.18 New reversible T flip flop
Fredkin
SALEEM-I
CLK
CLK
1
A
P
D
G
0
B
Q
C
R
Fig. 5.19 New reversible D flip flop
5.3.2
New Design of Reversible D Flip Flop
The characteristic equation of the D flip flop is
Qþ ¼ ðD CLKÞ ðQ CLKÞ
¼ ðD CLKÞ Q ðQ CLKÞ
The circuit in Fig. 5.19 is synthesized by using a Fredkin gate to realize the
characteristic equation (i.e., to calculate Qþ ). Then the SALEEM-I gate is used to
produce the two complementary outputs of the circuit. The circuit consists of two
reversible gates and produces two garbage outputs. This result is the same that
obtained in [5]. But, as mentioned in the previous sub-Section, the circuits in [5]
have the Qþ output only.
5.3.3
New Design of Reversible JK Flip Flop
The characteristic equation of the JK flip flop is
Qþ ¼ ðJ CLKÞQ QðK CLKÞ
¼ ðJ CLKÞð1 QÞ Qð1 K CLKÞ
¼ Q ðJ CLKÞ ðK Q CLKÞ ðJ Q CLKÞ
5.3 Novel Reversible Sequential Elements
SALEEM-II
J
CLK
K
A
SALEEM-II
P
A
J
B
Q
C
R
131
G1
X
J
SALEEM-II
P
CLK
B
Q
C
R
G2
Y
Y
A
SALEEM-I
P
CLK
B
Q
C
R
G3
1
0
A
P
B
Q
C
R
Fig. 5.20 New reversible JK flip flop
Figure 5.20 shows the complete circuit diagram of the new reversible JK flip
flop. It consists of four reversible gates and produces three garbage outputs, exactly
as in [5]. But, the two complementary outputs are provided here. Another difference
is that the reversible gates used in the circuit of Fig. 5.20 are (3 * 3) reversible gates,
which are simpler than the (4 * 4) reversible gates used in [5].
5.3.4
New Design of Reversible Master-Slave Flip Flops
The new reversible master-slave D, T, and JK flip flops are shown in Figs. (5.21,
5.22 and 5.23), respectively.
D flip flop
D flip flop
(master)
(slave)
Fig. 5.21 New reversible master-slave D flip flop
T flip flop
D flip flop
(master)
(slave)
Fig. 5.22 New reversible master-slave T flip flop
132
5 Reversible Sequential Logic Circuits
JK flip flop
D flip flop
(master)
(slave)
Fig. 5.23 New reversible master-slave JK flip flop
In some literatures, what is called “flip flop” here, it is called “latch” there. Also,
what is called “master-slave flip flop” here, it is called “flip flop” there.
5.3.5
Evaluation of the New Reversible Flip Flops
It is clear from the previous sub-Sections, the superiority of the design method
based on the realization of the characteristic equations of flip flops (denoted as
method 2) over the direct transformation method described in Sect. 5.1 (denoted as
method 1). Table 5.8 shows the big differences between the results of the two
methods. The number of gates used in the designs given by method 2 is 50.8 %; of
the designs in method 1 on average. The number of garbage outputs in the designs
of method 2 is 40.5 %; of the designs in method 1 on average.
Table 5.9 shows a comparison between the results of method 2 and those given
in a previous work [7]. The number of gates used in the designs given by method 2
is 47.3 %; of the designs in [7] on average. The number of garbage outputs in the
designs of method 2 is 34.8 %; of the designs in [7] on average.
Table 5.8 Comparison between the results of method 1 and method 2
Type of flip flop
T
D
JK
JK master-slave
Average
Number of gates
Method 2 Method 1
Ratio (%)
Number of garbage outputs
Method 2 Method 1 Ratio (%)
2
2
4
7
–
33.3
40.0
66.6
63.6
50.8
2
2
3
6
–
6
5
6
11
–
6
5
7
13
–
33.3
40.0
42.8
46.1
40.5
5.4 Multiple-Valued Reversible Sequential Circuits
133
Table 5.9 Comparison between the results of method 2 and those in [7]
Type of master-slave
flip flop
Number of gates
Method 2
[7]
Ratio (%)
Number of garbage outputs
Method 2
[7]
Ratio (%)
D
T
JK
Average
5
5
7
–
45.4
38.4
58.3
47.3
4
4
6
–
5.4
11
13
12
–
12
14
14
–
33.3
28.5
42.8
34.8
Multiple-Valued Reversible Sequential Circuits
Multiple-valued reversible logic is an emerging area in reversible and quantum
logic circuit synthesis. Multiple-valued reversible logic circuits can potentially
reduce the width of the reversible or quantum circuit which is a limitation in current
quantum technology. In [8], a method to synthesize the multiple-valued reversible
sequential circuits is proposed. Some basic sequential circuits such as D and T flip
flops and master-slave D flip flop are designed. The genetic algorithm is used as a
synthesis tool to design and optimize these circuits. The cost of a circuit is considered as the number of quantum 1 × 1 or 2 × 2 gates used for implementation of
the circuit. From a literature survey, it is believed that this is the first work to
propose multiple-valued reversible flip flops and sequential circuits, and it represents the beginning of the race.
5.5
Summary
Many years, the researches in reversible logic design were limited to the combinational logic circuits. To design a sequential logic circuit, it is necessary to use the
feedback, which seems to violate the basic laws of reversible logic circuits. In
reversible logic circuits loops are not allowed. It has been shown, in [9], that the
feedback is not a violating condition for reversible logic circuits. A circuit is
feasible by feedback if its transition function (or state transition table) remains
reversible, or its transfer matrix is unitary.
To construct a reversible sequential circuit, reversible sequential elements are
required. This chapter presents novel designs of reversible sequential elements such
as RS, D, T, and JK flip flops (latches). Based on these reversible flip flops, the
designs of the corresponding master-slave flip flops are constructed.
The novelty of the work in this chapter is the use of the new (SALEEM)
reversible gate to design complex reversible sequential circuits. The reversible flip
flops, registers and other complex sequential circuits are designed using SALEEM
gate. The design strategy is chosen in such a way to make them highly optimized in
terms of number of reversible gates and garbage outputs. Compared with previous
works, the implementation cost of the new designs, including the number of gates
134
5 Reversible Sequential Logic Circuits
and the number of garbage outputs, is significantly reduced. The gate count gives a
simple estimate of the implementation cost of the reversible circuit. For a reversible
circuit the number of garbage outputs shows the amount of information or energy
losses of the circuit. Therefore, it is preferred to design the circuit with the minimum possible number of gates and garbage outputs that will lead to minimizing
area and power consumption.
This work forms an important step in the building of complex reversible systems, which can execute more complicated operations using quantum computers.
The reversible circuits form the basic building block of quantum computers as all
quantum operations are reversible.
Next chapter will introduce the synthesis of quantum logic circuits for the
reversible structures.
References
1. J.E. Rice, An Analysis of Several Proposals for Reversible Latches, in Advances and
Innovations in Systems, Computing Sciences and Software Engineering, ed. by K. Elleithy
(Springer, Netherlands, 2007), pp. 203–206
2. H. Thapliyal, M. B. Srinivas, M. Zwolinski, A beginning in the reversible logic synthesis of
sequential circuits, in Proceedings of the 8th Military and Aerospace Programmable Logic
Devices (MAPLD) International Conference (NASA office of Logic Design), Washington D. C.,
September 2005
3. H. Thapliyal, M. B. Srinivas, An extension to DNA based Fredkin gate circuits: design of
reversible sequential circuits using Fredkin gates, SPIE International Symposium on
Optomechatronic Technologies, Sapporo, Japan, pp. 196–202, 5–7 December, 2005
4. H. Thapliyal, M. Zwolinski, Reversible logic to cryptographic hardware: a new paradigm, 2006.
www.arXiv.Org/pdf/cs/0610089
5. M. Chuang, C. Wang, Synthesis of reversible sequential elements, ACM J. Emerg Technol.
Comput. Syst. (JETC). 3, 4 (2008)
6. C.Y. Wang, M.L. Chuang, Reversible sequential apparatuses, Patent, National Tsing Hua
University, Taiwan, ROC, Agents: WPAT, PC; Intellectual Property Attorneys (IRVINE,
CA US, Origin, 2008)
7. J.E. Rice, A new look at reversible memory elements, in Proceedings of the IEEE International
Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, 21–24 May, 2006
8. M. Mohammadi, M. Eshghi, M. Haghparast, On design of multiple-valued sequential reversible
circuits for nanotechnology based systems, TENCON 2008, Hyderabad, India, 19–21
November, 2008
9. A. Banerjee, A. Pathak, On the synthesis of sequential reversible circuit. www.arXiv0707.
4233v1. [quant-ph] 28 July 2007
Chapter 6
Quantum Logic Circuits and Quantum
Computing
Quantum computing is a vast and fascinating interdisciplinary project of the 21st
century. Research and development in this monumental enterprise involve just
about every field of science and engineering [1]. At the dawn of the third millennium the dreams seem to become true due to quantum computing.
This chapter is organized as follows: Sect. 6.1 introduces the basics of quantum
computing. Quantum mechanics offers certain possibilities which are not present in
classical computing; one of them is referred to as superposition and is introduced in
Sect. 6.2. Afterwards bridges are built between classical and quantum computing in
Sects. 6.3 and 6.4 where generalization of registers and logic gates are investigated.
An analysis of quantum circuits is explained in Sect. 6.5. Synthesis methods of
quantum circuits are given in Sect. 6.6. Binary quantum decision trees and diagrams
are presented in Sect. 6.7. Fundamentals of ternary quantum computing are presented in Sect. 6.8. Finally, quantum computations using reversible structures (from
Chap. 3) are presented in Sect. 6.9.
6.1
Background
The field of computing is driven by boundless technological innovations. The time
between an ingenious idea coming from a research laboratory and its emergence as
a product or service is so short and the frequency of the commercialization cycle of
ideas is great [2]. The current drive towards increasing speed and miniaturization of
computers lead modern technology towards the subatomic domain (Quantum
Computing) [3]. Future computer circuits will therefore be based on nanotechnology, and the behavior of such circuits will have to be given in quantum mechanical
terms rather than in terms of classical physics, since on the atomic scale matter
obeys the laws of quantum mechanics [4, 5]. As current technology rushes forward,
several factors work together to push it toward the quantum computing world, and
push out the classical silicon-based chips. These factors include scaling in size,
energy consumption, and economics of building computers, and new applications
that are available with quantum computers that cannot be run on the classical
computers [3]. A race is on to build a different kind of computer that will exploit the
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_6
135
136
6 Quantum Logic Circuits and Quantum Computing
peculiarities of the quantum world to accomplish feats that are currently impossible.
The principles by which a quantum computer would work are quite different from
those governing today’s classical computers [6]. Quantum computers are devices
that use quantum mechanical phenomenon such as superposition and entanglement,
to perform operations on data. Having to take quantum mechanical effects into
account, quantum computing is something far stranger. It was almost three quarters
of a century after the discovery of quantum mechanics, and half a century after the
birth of information theory and the arrival of large-scale digital computation, that
people finally realized that quantum physics profoundly alters the character of
information processing and digital computation. Quantum mechanics provides new
computational paradigms that had not been imagined prior to the 1980s and whose
power was not fully appreciated until the mid-1990s [7].
Quantum computation is the extension of classical computation to the processing
of quantum information, using quantum systems such as individual atoms, molecules, or photons. It has the potential to bring about a revolution in computer
science. The genuine quantum phenomena have no classical analogue, such as
entanglement and interference, sometimes providing exponential speed-up compared with classical computers [8].
Quantum computing is a new and promising technology with the potential of
exponentially powerful computation, if only a large-scale one can be built. There are
several challenges in building a large-scale quantum computer (fabrication, verification, and architecture). The power of quantum computing comes from the ability
to store a complex state in a single bit. This also what makes quantum systems
difficult to build, verify, and design. Errors occur much more often than with classical computing, making error correction the dominant task that quantum architectures need to perform well. Several groups have successfully built 5–10 quantum bits
computers [9]. As promising as these developments are, it is still a long way from
building a reliable, large-scale quantum computer. The physical properties of
quantum matter make it very difficult to build a reliable quantum computer. There
are several aspects to this (error correction, communication and fabrication).
Quantum error correction is both more challenging and more cumbersome than in
classical computing. The power of quantum computation lies in the fact that each
quantum bit stores much more information than a classical bit. Implementation of
quantum computers presents a profound experimental challenge [8].
Essentially, three different approaches have been taken to the implementation of
quantum computers:
• Bulk resonance quantum implementations including NMR (Nuclear Magnetic
Resonance) [10–12], linear optics [13–15], and cavity quantum electrodynamics
[16];
• Atomic quantum implementations including trapped ions [17–19] and optical
lattices [20, 21]; and
• Solid-state quantum implementations including semiconductors [22–26] and
superconductors [27–34].
6.1 Background
137
The solid-state quantum computing implementations appear to offer the highest
promise for scaling the complexity of quantum computing for commercial applications [35].
Can quantum computers be built? This is the challenge that is keeping busy
many research teams of physicists and computer scientists around the world. The
next decade promises to be really exciting in terms of the ability to physically
manipulate quantum bits and implement quantum computers. But there is another
possibility: what if all these efforts at implementing quantum computers fail? This
would be even more interesting, because it would point to some fundamental flaw
in quantum physics, a theory that has stood unchallenged for a century [36].
Quantum computation is motivated as much by trying to clarify the mysterious
nature of quantum physics as by trying to create novel and super powerful
computers.
6.2
Quantum Bits and Superposition
In quantum computation quantum bits (qubits), pronounced q-bit, are used instead
of classical binary bits to represent information. These information units are derived
from the states of micro-particles such as photons, electrons or ions [37]. These
states are the basis states of computational quantum system. The spin is a quantum
mechanical property of particles that in certain cases can take only two mutually
exclusive values [38]. Assume an electron with two possible spin rotations: up and
down. Using ket notation these distinguishable states will be represented as j0i and
j1i, respectively. The two qubits can be identified with the following column
vectors
j 0i ¼
0
1
:
and j1i ¼
1
0
If a physical system such as a particle can be found in more than one state and its
state is unknown, it exists in a superposition of those states. That is, if there are two
possible states, the system can be said to exist in both at once until its state is
actually measured. Such a measurement collapses the system onto one state or
another [38].
Thus, an arbitrary state j;i can be written in either of the two equivalent forms
given below [39]:
a
:
j;i ¼ aj0i þ bj1i ¼
b
The entries of the state vector determine the readout probabilities: jaj2 is the
probability of j;i being measured in state j0i and jbj2 is the probability of j;i being
138
6 Quantum Logic Circuits and Quantum Computing
measured in state j1i. Since these are the only two possibilities, a and b are required
to satisfy jaj2 þ jbj2 ¼ 1. For quantum computing a and b are complex numbers and
are the so-called probability amplitudes [40–44].
The qubit concept parallels the bit in conventional computation, but offers a
much broader set of representations. Rather than a finite dimensional binary representation for information, the qubit is a member of a two-dimensional Hilbert
space containing a continuum of quantum states. Thus, quantum computers operate
in a much richer space than binary computers [35].
6.3
Qubit Registers
By a register of qubits, it simply means a logical qubit array with a fixed number of
qubits in a fixed order. A readout of a qubit register amounts to readouts of each
component qubit; thus readout of an n-qubit register might take the form
jb0 ijb1 i. . .jbn1 i for each bj 2 f0; 1g. This is abbreviated to jb0 b1 . . .bn1 i, and it is
called a bitstring state. Quantum mechanics demands the use of a natural generalization of bitstring concatenation called the tensor product [39]. Why the tensor
product? Tensor product captures the essence of superposition, that is if system A is
in state jAi and B in the state jBi then there should be some way to have a little of
A and a little of B. Tensor product exposes this. The tensor product is a way of
putting vector spaces together to form larger vector spaces [45].
For example, if it is required to represent the decimal number 6 in binary, a 3-bit
register is set up to read 110. Using qubits, this is written as
1
0
0
j110i ¼ j1i j1i j0i ¼
0
1
1
¼½ 0 0
0 0
0
0
1
0 T :
Quantum registers get more interesting when they contain one or more qubits
that aren’t in a pure state. Suppose that there are two qubits, q0 ¼ j1i and
q1 ¼ p1ffiffi2 ðj0i þ j1iÞ. To form a register r from their tensor product, then
1
1
r ¼ q0 q1 ¼ j1i pffiffiffi ðj0i þ j1iÞ ¼ pffiffiffi ðj10i þ j11iÞ:
2
2
Before measuring r, it’s simultaneously representing j10i and j11i, with equal
probability [44]. Mathematically, it is the tensor product operation that allows the
quantum logical system to grow dimensionally much faster than classical logics. In a
quantum system n qubits represent a superposition of 2n states while in a classical
system n bits represent only 2ndistinct states [37]. In general, a binary quantum
register (also called a scratchpad register) that is composed of k binary qubits can
6.3 Qubit Registers
139
have up to 2k possible states. The quantum register can be in any of the individual
states at any instant of time or in all of the states at the same time [46]. The fact that the
quantum register can be in all of the states at the same time is the reason for the binary
parallelism that exists at the binary quantum level. Due to this parallelism, a binary
quantum processor can operate on all of the states of the quantum register at the same
time (i.e., it can be modeled like application-specific 2k binary parallel processors).
6.4
Quantum Logic Gates
A quantum logic gate is a closed-system evolution (transformation) of the n-qubit
state space (Hilbert space, Hn ) [39]. n-dimensional Hilbert space is in general a
linear complex vector space. If jwi is a state vector in Hn , the operation of an
n-qubit quantum logic gate can be represented by jwi ! Ujwi for some unitary
2n 2n matrix U. A square matrix U is unitary iff Uy U ¼ I for I an identity matrix,
where Uy is the complex conjugate transpose (also called the “Hermitean conjugate”, or “adjoint”) of the U matrix.
Definition 6.1 An operator U is called unitary if Uy ¼ U1 .
Note that Uy ¼ U1 implies Uy U ¼ I, where I is the identity operator.
Definition 6.2 An operator T in a Hilbert space is called Hermitean (or self-adjoint)
if Ty ¼ T (i.e., it is equal to its own Hermitean conjugate) [47].
Quantum states which can be produced in more-than-one qubit systems, like:
jwi ¼
j00i þ j11i
pffiffiffi
;
2
such states are called entangled. This means that there are no individual qubit states
j;i1 and j;i2 such that jwi ¼ j;i1 j;i2 .
Entanglement is the state in which two quantum systems in indeterminate states
are linked so that measuring or manipulating one system instantaneously manipulates the second [38]. The power of quantum computation comes from the existence
of superposition of states of qubits, particularly entanglement, and the ability to
manipulate them through unitary transformations [10].
A two-qubit pure state j;i ¼ aj00i þ bj01i þ cj10i þ dj11i is entangled exactly
when ðad bcÞ 6¼ 0. It is easy to use this fact to check when a specific matrix is, or
is not, entangling [1]. The speedups in quantum computations seem to be due to the
entanglement, by which many computations are performed in parallel.
Quantum gates are defined by simply specifying their matrices. The quantum
logic operation of “doing nothing” is modeled by the identity matrix, serial composition of gates is modeled by the matrix products, and every quantum gate is
140
6 Quantum Logic Circuits and Quantum Computing
reversible. Because the probabilities must be preserved at the output of the quantum
gate, all matrices representing quantum gates are unitary [37]. Thus every quantum
gate, block and the entire circuit is described by a unitary matrix. While in general
the coefficients in unitary matrices of quantum circuits are complex numbers, there
are some special and important gates for which unitary matrices are just permutation matrices. (A permutation matrix has exactly one “1” in every row and in
every column and all other entries are zeros, it describes therefore an input-output
permutation of value vectors). There exist, however, other important gates whose
unitary matrices are not permutation matrices. Gates such as Hadamard gate (denoted by H) and Square Root of NOT Gate (denoted by V) belong to this second
category. A Hadamard gate is an example of a gate that has a unitary matrix which
is not a permutation matrix. Here are some useful matrices:
One-qubit gates:
1 1 1
0 1
Hadamard ðHÞ: pffiffiffi
; Pauli X ðNOTÞ:
;
1 0
2 1 1
0 j
1 0
1 0
Pauli Y:
; Pauli Z:
; PhaseðSÞ:
;
j 0
0 1
0 j
p
1
ðTÞ:
0
8
pffiffiffiffiffiffiffiffiffiffi
1 þ j 1 j
:
NOTðVÞ:
j 1
2
0
p ;
ej 4
Only X is permutative. The Hadamard gate’s utility is that it can take a qubit in a
pure state such as j0i and turn it into a superposition of states. If it is applied to each
qubit of an n-bit register, the result is a register that simultaneously represents 2n
different values. When H is applied to n qubits of a register simultaneously, then it
is called the Walsh or (Walsh-Hadamard) transformation on that register and it is
written as W [48].
Two-qubit gates:
2
1
60
Feynman ðCNOTÞ:4
0
0
2
1
60
Controlled Z:4
0
0
0
1
0
0
0
1
0
0
0
0
0
1
3
0 0
0 0 7
;
1 0 5
0 1
3
0
07
;
15
0
2
1
60
Swap:4
0
0
0
0
1
0
2
1
60
Controlled Phase:4
0
0
3
0
07
;
05
1
0
1
0
0
0
1
0
0
0
0
1
0
3
0
07
05
j
In a Hilbert space, any operator can be expressed, and therefore any symbolic
representation of a gate, by means of bra and ket vectors, where the bra vector is the
adjoint of the ket vector: jviy ¼ hvj.
6.4 Quantum Logic Gates
141
a
P
b
U
Q
Fig. 6.1 A general-purpose controlled gate
For instance, the NOT gate can be expressed as the following operator:
NOT ¼
0
1
1
0
¼
0
0
1
0 0
1
0
þ
¼
½0 1þ
½1 0
0
1 0
0
1
¼ j0ih1j þ j1ih0j;
and a general two-dimensional operator as [49]:
a00
a10
a01
a11
¼ a00 j0ih0j þ a01 j0ih1j þ a10 j1ih0j þ a11 j1ih1j:
The controlled-U gate (Fig. 6.1) works as follows: when the controlling signal a
is 0, the output Q equals the input b. When a is 1, then Q = U (b) (i.e. the output Q
is the operator of this gate (matrix U) applied to its input b).
The designer of quantum algorithms has to deal with standard probabilities, but
the designer of quantum circuits, which is the interest here, deals only with operations in quantum world because his input problem is described in such a way [37].
Quantum computer hardware must satisfy fundamental constraints [8]: (i) the qubits
must interact very weakly with the environment to preserve their superposition, and
(ii) the qubits must interact very strongly with one another to make logic gates and
transfer information.
6.5
Quantum Logic Circuits
A combinational quantum logic circuit consists of quantum gates, interconnected
by quantum wires, carrying qubits, without fan-out or feedback [39]. A quantum
circuit can be understood as representing the sequence of quantum logic operations
on a quantum register. Each line in the quantum circuit represents a wire. This wire
does not necessarily correspond to a physical wire; it may correspond instead to the
passage of time, or perhaps to a physical particle such as a photon (a particle of
light) moving from one location to another through space [45]. When building a
quantum network for computation and communication, photons that carry a
quantum state are called flying qubits, as opposed to atoms, which are then called
stationary qubits [49].
142
6 Quantum Logic Circuits and Quantum Computing
I2
I2
U1
U4
U7
V2
U
U2
U5
U8
V1
U3
I2
V3
(4)
(5)
U6
(2)
(1)
U9
(3)
(6)
Fig. 6.2 A typical quantum logic circuit
An example of a quantum logic circuit is depicted in Fig. 6.2. Information flows
from left to right, and the higher wires represent higher order qubits [39].
The
quantum
operation
performed
by
this
circuit
is
ðU7 U8 U9 Þ ðI2 V3 Þ ðV2 I2 Þ ðU4 U5 U6 Þ ðI2 V1 Þ ðU1 U2 U3 Þ.
The formulas describing quantum circuits must be read right to left (i.e. (6) (5)
(4) (3) (2) (1) as mentioned above).
Example 6.1 The circuit in Fig. 6.3 illustrates the process of evolving the input
binary quantum bits using a composite of binary quantum primitives in a mixture of
serial-like and parallel-like interconnects.
The evolution of the input qubit using cascaded (i.e. serially-interconnected)
quantum gates can be viewed in two equivalent perspectives [46]. The first perspective is to evolve the input qubit step by step using the serially interconnected
gates. The second perspective is to evolve the input qubit using the total quantum
circuit at once. Let evolving the input binary qubit j101i using the quantum circuit
in Fig. 6.3. The evolution matrices of the parallel-interconnected dashed boxes in
(5) and (6) are as follows (where the symbol || means parallel connection):
input ¼ j1i j0i j1i ¼
¼½ 0
(1)
0
0
0
0
1
0
1
0
1
0
1
0
0 T :
(3)
(2)
(4)
(5)
(6)
Fig. 6.3 Quantum circuit composed of serial and parallel interconnects of two wires (Buffers), a
single Feynman gate, and a single Swap gate
6.5 Quantum Logic Circuits
143
The evolution matrix for (5) = (1) || (2) is:
1
0
60
4
0
1
0
1
0
wire Feynman ¼
2
22
1
66 0
64
6 0
6
6 0
¼6
6
6
6
4
0
1
0
0
0
1
0
0
0
0
0
1
3
0
07
15
0
0
0
0
1
3
0
07
15
0
3
2
1
60
40
0
0
1
0
0
0
0
0
1
1
60
6
3
0
0
6
6
1 0
07
60
¼6
05
0 1
60
60
1
6
40
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
7
7
7
7
7
3 7:
0 7
7
0 77
5
1 5
0
The evolution matrix for (6) = (3) || (4) is:
2
2
1 0
60 0
Swap wire ¼ 4
0 1
0 0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
Perspective #1:
input ) ð5Þ ) output1 ; input2 ð¼ output1 Þ ) ð6Þ ) output2 :
22
1
66 0
64
6 0
6
6 0
6
6
6
6
4
0
1
0
0
0
0
0
1
3
0
07
15
0
2
1
60
40
0
1
0
0
0
2
1
60
6
60
6
60
60
6
60
6
40
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
3
3 2
0
0
76 0 7 6 0 7
7
7 6
76
76 0 7 6 0 7
7
7 6
76
76 0 7 6 0 7
;
¼6
3 7:6
7
0 76 0 7 6 0 7
7
76 1 7 6 1 7
0 77 6
7
7 6
1 55 4 0 5 4 0 5
0
0
0
32
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
3 2 3
32
0
0
0
076 0 7 6 0 7
7 6 7
76
076 0 7 6 0 7
7 6 7
76
076 0 7 6 1 7
¼ 6 7 ¼ j011i:
:6
7
076 0 7
7 6 0 7
7
7
6
7
076 1 7 6
6 0 7
4
5
4
5
0 5
0
0
0
0
1
3
0
07
7
07
7
07
:
07
7
7
07
05
1
144
6 Quantum Logic Circuits and Quantum Computing
Perspective #2:
input )ðð6Þð5ÞÞ ) output2 :
02
1
B6 0
B6
B6 0
B6
B6 0
B6 0
B6
B6
B6 0
@4 0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
3 22
1
0
0 7 66 0
7 64
076 0
76
076 0
:6
07
76
76
076
054
1
0
1
0
0
0
0
0
1
3
0
07
15
0
31 2
2
1
60
40
0
0
1
0
0
0
0
0
1
3
3 2
0
0
7C 6 0 7 6 0 7
7
7C 6 7 6
7C 6 0 7 6 0 7
7
7C 6 7 6
7C 6 0 7 6 1 7
¼ j011i:
3 7C:6 7 ¼ 6
0 7C 6 0 7 6 0 7
7
7
7C 6 7 6
0 7 7C 6 1 7 6 0 7
1 5 5A 4 0 5 4 0 5
0
0
0
Thus, the quantum circuit shown in Fig. 6.3 evolves the qubit j101i into the
qubit j011i.
6.6
Synthesis of Quantum Logic Circuits
Quantum analysis means to take the total synthesized quantum circuit of interconnected quantum sub-circuits and produce the total evolution matrix from it.
Quantum synthesis is the opposite; by having the total evolution matrix it is
required to produce within specific design constraints certain topological quantum
circuit made up of either totally serial interconnects (i.e., using only matrix product), totally parallel interconnects (i.e., using only tensor product), or a hybrid of
serial and parallel interconnects (i.e., using both matrix product and tensor product).
There are basically two methods of designing quantum circuits [37]. In the first
method a reversible circuit is designed with the rules: (1) no loops allowed in the
circuit and no loops internal to gates, (2) fan-out of every gate is one. These rules
preserve the reversible characteristic of gates thus the resulting circuit is also
completely reversible. Next, the circuit is made a quantum array by eliminating any
garbage output. Also, every crossing of two wires is replaced with the quantum
Swap gate making the circuit free from any two wires intersection in it. It is
relatively easy to transform a quantum array to its corresponding unitary matrix.
Tensor and standard matrix multiplications are used in this transformation.
The second design method for quantum circuits is to synthesize directly the
quantum array of a circuit that was initially specified by a unitary matrix. The
synthesis is done by one of two approaches:
(a) Composing matrices of elementary gates in series or in parallel until the matrix
of entire circuit becomes the same as the specification matrix.
(b) Decomposing the specification matrix of the entire circuit to parallel and serial
connections of unitary matrices until all matrices correspond to matrices of
elementary gates directly realizable in the given technology.
6.6 Synthesis of Quantum Logic Circuits
145
In another synthesis, called the approximate synthesis, it is not required that the
circuit specification matrix and the matrix of composed gates are exactly the same.
They can differ by small allowed values or/and differ in some matrix coordinates
only [37].
In summary, the synthesis of quantum circuits can be approached from two
different angles: (1) Synthesizing reversible circuits first that are later mapped into
quantum circuits or (2) targeting quantum gates directly during the synthesis
process.
6.7
Binary Quantum Decision Trees and Diagrams
Since various types of decision trees and diagrams are of fundamental importance in
binary and ternary logic, it is obvious that they will be also useful in binary
quantum logic [46]. Utilizing the binary Feynman and Swap evolution matrices that
were presented previously, the following represents the binary initial state (Buffer)
(which is equivalent to two wires), binary final state of a 2-qubit Swap register, and
binary final state of a 2-qubit Feynman register using the binary computational basis
states ½j00ij01ij10ij11i:
2
1
60
jwiBuffer ¼ ½j00ij01ij10ij11i4
0
0
2
1
60
jwiSwap ¼ ½j00ij01ij10ij11i4
0
0
2
1
60
jwiFeynman ¼ ½j00ij01ij10ij11i4
0
0
0
1
0
0
0
0
1
0
3
32
a1 a2
0
0 76 a1 b2 7
:
0 54 b1 a2 5
b1 b2
1
0
0
1
0
0
1
0
0
3
32
0
a1 a2
0 76 a1 a2 7
:
0 54 b1 a2 5
1
b1 b2
0
1
0
0
0
0
0
1
3
32
a1 a2
0
0 76 a1 b2 7
:
1 54 b1 a2 5
0
b1 b2
Figure 6.4(a, b) illustrate examples of the computational quantum decision trees
(CQDT), and Fig. 6.4c illustrates an example of the computational quantum decision diagram (CQDD), for the binary quantum computational basis states
fj00i; j01i; j10i; j11ig, where fai ; bj g are the probability amplitudes.
146
6 Quantum Logic Circuits and Quantum Computing
(a)
(b)
(c)
Fig. 6.4 Binary computational quantum decision tree (CQDT) and decision diagram (CQDD):
a Buffer CQDT, b Swap CQDT and c Feynman CQDD
6.8
Fundamentals of Ternary Quantum Computing
In ternary quantum logic, the j0i; j1i; and j2i qubits are used. These qubits are
represented by the vector that corresponds to the following [46]:
2 3
2 3
2 3
1
0
0
j0i ¼ 4 0 5; j1i ¼ 4 1 5; j2i ¼ 4 0 5:
0
0
1
For a ternary quantum register composed of 2 ternary qubits, 9 possible states of
the ternary quantum register are obtained:
fj00i; j01i; j02i; j10i; j11i; j12i; j20i; j21i; j22ig:
In general, a ternary quantum register that is composed of n ternary qubits can
have up to 3n distinct possible states. The ternary quantum register can be in any of
the individual states at any instant of time or at all of the states at the same time.
Due to this parallelism, a ternary quantum processor can operate on all of states of
the quantum register at the same time (it can be modeled like having
application-specific 3n ternary parallel processors).
6.8 Fundamentals of Ternary Quantum Computing
147
For a quantum register composed of 1-ternary qubit, and assuming the
orthonormalization of the computational basis states, the evolution state ðjwiÞ is
represented as follows:
jwiternaryqubit ¼ aj0i þ bj1i þ cj2i;
where a; b; and c are complex numbers called “probability amplitudes”, and in
general: jaj2 þ jbj2 þ jcj2 ¼ 1.
For a ternary quantum register which is composed of two ternary qubits, the
evolution quantum state jwi is represented as follows:
jwiternaryqubit 1 ¼ a1 j0i þ b1 j1i þ c1 j2i;
jwiternaryqubit 2 ¼ a2 j0i þ b2 j1i þ c2 j2i:
For two ternary qubits, and by using the tensor product:
jwi2ternaryqubit ¼ jwi1 jwi2 :
jwi can be represented using matrix-based form as follows [46]:
2
6
6
6
6
6
6
jwi2ternaryqubit ¼ ½j00i j01i j02i j10i j11i j12i j20i j21i j22i½E6
6
6
6
6
4
a1 a2
a1 b2
a1 c2
b1 a2
b1 b2
b1 c2
c1 a2
c1 b2
c1 c2
3
7
7
7
7
7
7
7;
7
7
7
7
5
where [E] is the evolution matrix.
As the entanglement in the case of binary quantum systems seems to be the
major factor behind the speedups of quantum computations by which many computations are performed in parallel, the same role of entanglement is expected to be
observed in the case of ternary quantum systems.
Analogously to the binary case, the input qubit to the ternary quantum gate is the
column index of the ternary evolution matrix, and the output qubit of the ternary
quantum gate is the row index of the ternary evolution matrix. The following is the
ternary Galois field Feynman and Swap evolution matrices, respectively [46]:
148
6 Quantum Logic Circuits and Quantum Computing
.
GF(3)
.
Using the above approach for the Feynman and Swap evolution matrices, the
ternary evolution matrices for ternary reversible Ferdkin gates, Toffoli gates, Davio
gates, and other ternary reversible primitives can be constructed. Ternary quantum
decision trees and diagrams can be derived in a similar manner to the binary case
mentioned in Sect. 6.7.
6.9
Quantum Computing for the Reversible Structures
As was demonstrated in previous Sections, the input qubits to any type of quantum
circuit can be evolved from input to output by using the normal matrix product for
serial interconnects and the tensor product for the parallel interconnects. The
evolution operations can be implemented using the matrix representation or the
corresponding QDTs or QDDs representations. This quantum evolution of the input
qubits can be performed using the quantum counterparts of the reversible structures
from Chap. 3.
One of the most efficient ways to realize quantum circuits is by using
cascade-based circuit topology of interconnected reversible quantum primitives
[50]. As an example, by using the following reversible Davio0 expansion:
2
1
! 4
f D0 ¼ 1
1
1þx
x
2þx
32
0
1 þ 2x þ x2
54 2
x2
2
1 þ x þ x2
32 3 2 3
f0
f r0
0 1
1 0 54 f 1 5 ¼ 4 f r1 5
2 2
f2
f r2
ð6:1Þ
6.9 Quantum Computing for the Reversible Structures
149
0
2(f0+ f1+ f2)
0
(2f1+ f2)x
2
2
x
x
2
x
x2
f0
f0
f1
(f0+ f1)
f2
(2f1+ f2)
f2
(f0+ f1+ f2)
0
fro
Fig. 6.5 Ternary GF quantum cascade for the realization of the output fro in the reversible
expansion in Eq. (6.1)
The ternary reversible Davio0 cascade shown in Fig. 6.5 is obtained.
It can be observed that, by using Eq. (6.1), other cascade forms can be created.
An important issue is the design of a reversible structure that is quantum-realizable
(i.e., the reversible circuit can be directly implemented (mapped) into a functioning
quantum system). This issue of technology mapping is important because while
each quantum primitive is reversible, the opposite is not necessarily true, i.e. not
each reversible primitive is quantum.
Spectral transforms that transform functions in the quantum domain (which is
the linear complex Hilbert vector space), such as the quantum Fourier transform, the
quantum Walsh transform, and the quantum Chrestenson transform, have been
addressed [45, 46] as methods that can be used to design quantum circuits of
quantum functions in the quantum domain (space) [50].
Next chapter will introduce new techniques to implement the Daubechies
Wavelets and Multiwavelets using quantum computing.
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lattices,” IEEE Conference on Quantum Electronics and Laser Science (QELS’99)
(Washington, DC, USA, 1999), p. 112
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Quantum Dot Spins: A Path Into Quantum Computing,” Proceedings of Quantum Electronics
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23. R.W. Keyes, Challenges for quantum computing with solid-state devices. IEEE Comput. 65–
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Evolutionary approach to quantum and reversible circuits synthesis. Artif. Intell. Rev. 20(3–4),
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Chapter 7
Wavelets and Multiwavelets
Implementation Using Quantum
Computing
In this chapter, new techniques to implement the Daubechies wavelets and multiwavelets are presented using quantum computing synthesis structures described in
Chap. 6.
Section 7.1 explains the background of using quantum computing to implement
wavelet transforms. Quantum circuits for the perfect shuffle permutation matrices
which arise in quantum wavelet transforms are discussed in Sect. 7.2. Two fundamental quantum wavelet pyramidal and packet algorithms are introduced in
Sect. 7.3. Finally, new quantum implementations of the most popular discrete
wavelet transform, namely, the 4-coefficient Daubechies wavelet and multiwavelet
transforms are developed in Sects. 7.4 and 7.5, respectively.
7.1
Introduction
As it happens in classical signal analysis, it is natural to expect that quantum
wavelet transform will find important future applications [1] for the treatment of
quantum databases and quantum data compression. Therefore, it is important to
develop quantum circuits for implementing wavelet and multiwavelet transforms. In
this chapter, efficient and complete quantum circuits are derived for the quantum
Daubechies D(4) wavelet and multiwavelet transforms representations. The fact that
quantum algorithms are describable in terms of unitary transformations is both good
news and bad for quantum computing. The good news is that knowing that a
quantum computer must perform a unitary transformation allows theorems to be
proved about the tasks that quantum computers can and cannot do [2]. On the other
hand, the bad news is that many computations that are required to perform are not
described in terms of unitary operators. For example, a desired computation might
be nonlinear, irreversible or both nonlinear and irreversible. Irreversibility can be
handled by incorporating extra “ancilla” qubits that permit to remember the input
corresponding to each output. But nonlinear transformations are still problematic.
Fortunately, there is an important class of computations, the unitary transforms,
such as the Fourier transform, Walsh-Hadamard transform and wavelet transforms,
that are describable, naturally, in terms of unitary operators [2]. Of these, the
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_7
153
154
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
Fourier and Walsh-Hadamard transforms have been the ones used most extensively
by the quantum computing algorithms [3–7]. However, the wavelet transforms are
every bit as useful as the Fourier transform; therefore it is considered, here, how to
achieve a quantum wavelet transform.
The process of finding a quantum circuit that implements the unitary operator of
the wavelet transform is to factor the wavelet operator into the direct sum, direct
product and dot product of smaller unitary operators. These operators correspond to
1-qubit and 2-qubit quantum gates. The permutation matrices play a pivotal role in
the factorization of the unitary operators that arise in the wavelet transforms. The
main issue in deriving feasible and efficient quantum circuits for the quantum
wavelet transforms considered in this chapter, is the design of efficient quantum
circuits for certain permutation matrices. The permutation matrices, due to their
specific structure, represent a very special subclass of unitary matrices [2].
Therefore, the key to achieve an efficient quantum implementation of permutation
matrices is the exploitation of this specific structure. The downshift permutation
matrix, designated as Q2n, which plays a major role in derivation of quantum
wavelet transforms is considered here. A quantum description of Q2n can be given
as a quantum arithmetic operator. This description then allows the quantum
implementation of Q2n by using the quantum arithmetic circuits. Given a wavelet
kernel, its application is usually performed according to the packet or pyramid
algorithms. In this chapter, two representative wavelet kernels are considered, the
Daubechies D(4) [8] wavelets and multiwavelets. Two new decompositions which
lead to gate-level circuits for their implementations are developed.
7.2
Quantum Circuits for Perfect Shuffle
Permutation Matrices
Q
In this Section, quantum circuits are developed for the perfect shuffle, 2n , permutation
matrices, which Q
arise in quantum wavelet transforms. A description of
Q
n−1
matrix
in
terms
of
its
, can be given as
2n
ij elements, for i and j = 0, 1, …, 2
8 8
< if i ¼ j=2 and j is even;
>
>
< 1 or
Y
:
¼
if i ¼ 2n1 þ ðj 1Þ=2 and j is odd
ij
>
>
:
0 otherwise
A quantum description of
Y
2n
Q
2n can be given by [2]
: j an1 an2 . . . a1 a0 i ! j a0 an1 an2 . . . a1 i
7.2 Quantum Circuits for Perfect Shuffle Permutation Matrices
155
Q
That is, for quantum computation 2n is the operator which performs the right
Q
qubit-shift operation on n qubits. While, t2n (t indicates the transpose) performs
the left qubit-shift operation, i.e.
Yt
2n
: j an1 an2 . . . a1 a0 i ! j an2 . . .a1 a0 an1 i
A set of efficient and practically realizable circuits for implementation
of Qubit
Q
Permutation Matrices can be built by using the qubit swap gate, 4 , where
2
Y
1
60
¼4
4
0
0
0
0
1
0
0
1
0
0
3
0
07
05
1
Q
The 4 gate, shown in Fig. 7.1a, can be implemented
Q with three EXOR (or
Controlled-NOT) gates as shown in Fig. 7.1b. The 4 gate offers two major
advantages for practical implementation:
• It performs a local operation, i.e., swapping the two neighboring qubits. This is
advantageous in practicalQrealizations of quantum circuits, and
• Due to the fact that
4 can be implemented using three EXOR (or,
Controlled-NOT)
gates,
it
is possible to implement Q
conditional operators
Q
,
for
example,
operators
of
the
form
involving
4
4 I2n 4 , by using
Controlledk–NOT gates [8], see Fig. 7.2.
Q
Q
A circuit for implementation of 2n by using 4 gates is shown in Fig. 7.3. This
circuit is based on a simple idea of successive
the neighboring qubits.
Q swapping ofQ
This circuit leads to a factorization of 2n in terms of 4 as
Y
2n
¼
Y
Y
Y
n2
n3 . . . I2ni i2
I
I
I
I
2
2
2
2
4
4
4
Y
Y I2n3 4 I2 I2n2 4
Also, a recursive factorization of
(a)
Fig. 7.1 The
(b)
Q
Q
ð7:1Þ
2i directly results from Fig. 7.3 as
(b)
4 gate (a) and its implementation by using three EXOR (Controlled-NOT) gates
156
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
Fig. 7.2 Controlledk—NOT gate
Fig. 7.3 Implementation of perfect shuffle permutation matrix,
Y
¼
2i
7.3
Y
I2
2i1
Q
2n
Y I2i2 4
ð7:2Þ
Quantum Wavelet Algorithms
Wavelets have been around since the late 1980s, and have found many applications
in signal processing, numerical analysis, operator theory, and other fields [9]. There
are several reasons for their success. On the one hand, the concept of wavelets can
be viewed as a synthesis of ideas which originated during the last 30 years in
engineering, physics, and pure mathematics. As a consequence of these interdisciplinary origins, wavelets appeal to scientists and engineers of many different
backgrounds. On the other hand, wavelets are a fairly simple mathematical tool
with a great variety of possible applications [10].
7.3 Quantum Wavelet Algorithms
157
The wavelet transform is a tool that cuts up data or functions or operators into
different frequency components, and then studies each component with a resolution
matched to its scale. The wavelet transform of a signal evolving in time depends on
two variables: scale (or frequency) and time; wavelets provide a tool for
time-frequency localization.
Generalizations include wavelet packets, multi-variate wavelets, ridgelets, curvelets, vaguelettes, slantlets, second generation wavelets, frames, and other constructions [9–13].
One such generalization is multiwavelets, which have been around since the
early 1990s. Multiwavelets have some advantages: they can have short support
coupled with high smoothness and high approximation order, and they can be both
symmetric and orthogonal. They also have some disadvantages: the discrete multiwavelet transform requires preprocessing and post processing steps. Also, the
theory becomes more complicated.
7.3.1
Wavelet Pyramidal and Packet Algorithms
Given a wavelet kernel, its corresponding wavelet transform is usually performed
according to a packet algorithm (PAA) or a pyramid algorithm (PYA). Wavelet
packets analysis is a generalization of wavelet pyramidal analysis offering a richer
decomposition procedure [14]. In the orthogonal wavelet decomposition procedure
(PYA), the generic step splits the approximation coefficients into two parts. After
splitting, a vector of approximation coefficients and a vector of detail coefficients
are obtained. Then next step consists on splitting the new approximation coefficient
vector, successive details are never reanalyzed. In the corresponding wavelet packet
situation, each detail coefficient vector is also decomposed into two parts using the
same approach as in approximation vector splitting. The general idea of the wavelet
packets is to iterate further the splitting of the frequency band, still keeping the
same pair of filters. This offers the richest analysis. The first step in devising
quantum counterparts of these algorithms is the development of suitable factorizations. Consider the Daubechies fourth-order wavelet kernel of dimension 2i,
ð4Þ
denoted as D2i . The factorizations of PAA and PYA for a 2n-dimensional vector
are given as [2]
Y ð4Þ
ð4Þ
PAA ¼ I2n2 D4
I2n3 8 . . . I2ni D2i
Y
Y ð4Þ
ð4Þ
I2ni1 D
Dn
.
.
.
I
n1
2
i
þ
1
2
2
2n 2
ð7:3Þ
158
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
Y
Y
ð4Þ
ð4Þ
n 8 ::: D i I2n 2i
n 2i þ 1
PYA ¼ D4 I2n 4
I
I
2
2
2
8
2i þ 1
Y
ð4Þ
2n D2n
ð7:4Þ
These factorizations allow analysis of the feasibility and efficiency of quantum
implementations of the packet and pyramid algorithms. The above analysis can be
extended to any wavelet kernel.
7.3.2
Daubechies D(4) Wavelet Factorization
The most popular discrete wavelet transform, namely, the Daubechies fourth-order
wavelet kernel of dimension 2n is given in a matrix form as [2]
0
c0
B c3
B
B
B
B
B
B :
ð4Þ
D2n ¼ B
B :
B
B
B
B
B
@ c2
c1
c1
c2
:
:
c2
c1
c0
c3
c3
c0
c1
c2
1
c2
c1
c3
c0
:
:
c0
c3
c1
c2
c3
c0
c2
c1
c0
c3
C
C
C
C
C
C
C
C
C
C
c3 C
C
c0 C
C
c1 A
c2
ð7:5Þ
pffiffi
pffiffi
pffiffi
pffiffi
pffiffi3 and c3 ¼ 1pffiffi3 :
where c0 ¼ 1 4þpffiffi2 3 ; c1 ¼ 3 4þpffiffi2 3 ; c2 ¼ 3
4 2
4 2
ð4Þ
The D2n matrix, as given by Eq. (7.5), is not suitable for a quantum impleð4Þ
mentation. A suitable factorization of D2n needs to be developed to achieve a
ð4Þ
feasible and efficient quantum implementation. A factorization of D2n is proposed
in [15] as
ð4Þ
D2n ¼ ðI2n1 C1 ÞS2n ðI2n1 C0 Þ
ð7:6Þ
where
c
C0 ¼ 2 3
c2
c2
c3
1
and C1 ¼
2
c0 =c3
1
1
c1 =c2
ð7:7Þ
7.3 Quantum Wavelet Algorithms
159
and S2n is a permutation matrix with a classical description given by
8
< 1 if i ¼ j and i is seven; or if i þ 2ðmod 2n Þ ¼ j and i is odd
Sij ¼
:
0 otherwise
Clearly, the main issue for a practical quantum implementation of Eq. (7.6) is the
quantum implementation of matrix S2n. It was shown in [2] that the permutation
matrix S2n can be written as a product of two permutation matrices as
S2n ¼ Q2n R2n
ð7:8Þ
where Q2n is the downshift permutation matrix given by
0
0
B0
B
B0
B
B
Q2n ¼ B
B
B
B
B
@0
1
1
0
0
0
0
1
1
0
1
0
0
0
0
C
C
C
C
C
C
C
C
C
C
1A
0
ð7:9Þ
and R2n is a permutation matrix can be written as
R2n ¼ I2n1 X
0
where X ¼
1
ð7:10Þ
1
: Substituting Eqs. (7.10) and (7.8) into Eq. (7.6), a new fac0
ð4Þ
torization of D2n is derived as
a0
a1
Q2n
an-2
an-1
C0 `
C1
ð4Þ
Fig. 7.4 A block-level circuit for implementation of D2n [2]
160
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
ð4Þ
D2n ¼ ðI2n1 C1 Þ Q2n ðI2n1 C00 Þ
ð7:11Þ
c2 c3
:
c3 c2
Figure 7.4 shows a block-level implementation of Eq. (7.11). Clearly, the main
issue for a practical quantum gate-level implementation of Eq. (7.11) is the quantum implementation of matrix Q2n.
where C00 ¼ X C0 ¼ 2
7.4
Quantum Implementation of Daubechies D(4) Wavelet
A new circuit for implementation of permutation matrix Q2n is developed based on
its description as a quantum arithmetic operator. Such a quantum arithmetic
description of Q2n is given [2] as:
Q2n : j an1 an2 . . .a1 a0 i ! j bn1 bn2 . . . b1 b0 i
ð7:12Þ
bi ¼ ai 1ðmod 2n Þ:
ð7:13Þ
where,
ð4Þ
This description of Q2n allows its quantum implementation and hence D2n by
using quantum arithmetic circuits.
In the following, it is shown how a circuit for jmi ! jm 1 mod 2n i can be
constructed. In binary representation, this mapping can be specified in terms of the
following operations:
j an1 . . . a1 a0 i ! j bn1 . . . b1 b0 i;
b0 ¼ a 0 1
with
b1 ¼ a 1 a 0 1 ¼ a 1 b0
b2 ¼ a2 c1 where c1 ¼ b0 b1 ;
b3 ¼ a3 c2 where c2 ¼ b2 c1 ;
bi ¼ ai ci1 where ci1 ¼ bi1 ci2 :
Calculating the ci’s and then the bi’s, the circuit in Fig. 7.5 is obtained.
Replacing the block Q2n in Fig. 7.4 with the circuit in Fig. 7.5, then Fig. 7.4
ð4Þ
represents a complete gate-level circuit for implementation of D2n :
7.5 Quantum Implementation of Daubechies D(4) Multiwavelet
161
Fig. 7.5 A new circuit for implementation of permutation matrix Q2n
7.5
Quantum Implementation of Daubechies D(4)
Multiwavelet
Classical wavelet theory is based on a scaling function ϕ(t) and a wavelet function
ψ(t), multiwavelets have two or more scaling and wavelet functions. The scaling
function ϕ(t) is replaced by a function vector Φ(t) = [ϕ1(t)…ϕr(t)]T called a multiscaling function. Likewise, the multiwavelet function is defined from the set of
wavelet functions as Ψ(t) = [ψ1(t)…ψr(t)]T.
The multiwavelet two-scale equations:
UðtÞ ¼
1
pffiffiffi X
2
Hk Uð2tkÞ
ð7:14Þ
k¼1
WðtÞ ¼
1
pffiffiffi X
2
Gk Uð2tkÞ
ð7:15Þ
k¼1
The recursion coefficients Hk and Gk are the low and high-pass filter impulse
responses. They are r × r matrices for each integer k. In practice, the value of r = 2.
The Hk and Gk scaling and wavelet matrices for GHM filter are [9]
162
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
H0 ¼
3 ffiffi
p
5 2
1
20
4
5
3
pffiffi
10 2
!
; H1 ¼
3 ffiffi
p
5 2
9
20
!
0
0
¼
;
H
9
2
p1ffiffi
20
0 0
¼
;
H
3
3
1
pffiffi
0
20
10 2
!
!
0
2
ð7:16Þ
G0 ¼
¼
7.5.1
1
20
1pffiffi
10 2
1
20
1
pffiffi
10 2
3
pffiffi
10 2
3
10
0
!
; G1 ¼
!
9
20
9
pffiffi
10 2
1ffiffi
p
2
0
; G2 ¼
9
20
9pffiffi
10 2
3
pffiffi
10 2
3
10
; G3
ð7:17Þ
0
Computation of Discrete Multiwavelet Transform
For computing discrete multiwavelet transform (DMWT), the transform matrix
(T) can be written as in Eq. (7.18). The steps of computing a single-level
DMWT are:
1. Checking input dimensions: Input vector should be of length N, where N must
be power of two.
2. Constructing the transformation matrix (T) as given in Eq. (7.18), this is a
2N × 2N matrix.
3. Preprocessing the input signal by repeating the input stream with the same
pffiffiffi
stream multiplied by a constant α, for GHM system functions a ¼ 1= 2. The
preprocessing input vector is of a 2N × 1 dimension.
4. Transformation of input vector by applying matrix multiplication of the
2N × 2N transformation matrix with the 2N × 1 preprocessing input vector.
0
H0
B G0
B
B
B
B
B
T¼B
B
B
B
B
B
@ H2
G2
H1
G1
H3
G3
H2
G2
H0
G0
H3
G3
H1
G1
1
H2
G2
H3
G3
H0
G0
C
C
C
C
C
C
C
C
C
C
C
C
H1 A
G1
ð7:18Þ
7.5 Quantum Implementation of Daubechies D(4) Multiwavelet
7.5.2
163
Computation of Inverse Discrete
Multiwavelet Transform
To compute a single level inverse DMWT (IDMWT), the following steps should be
followed:
1. The input is the 2N × 1 multiwavelet transformed vector.
2. Construct the 2N × 2N reconstruction matrix, R, which is the 2N × 2N transformation matrix T transposed.
3. Multiply matrix R (Eq. 7.19) with the 2N × 1 multiwavelet transformed vector.
4. Apply post processing by discarding the even rows 2, 4 … 2N from the
reconstructed 2N × 1 matrix to have an N × 1 resultant matrix.
0
H0
B H1
B
B H2
B
B H3
B
B
R¼B
B
B
B
B
B
B
@
7.5.3
G0
G1
G2
G3
H0
H1
H2
H3
G0
G1
G2
G3
H2
H3
H0
H1
1
G2
G3 C
C
C
C
C
C
C
C
C
C
C
C
C
C
G0 A
G1
ð7:19Þ
A New Quantum Implementation of Daubechies D(4)
Multiwavelet Transform
A new quantum implementation of Daubechies D(4) multiwavelet is proposed here,
as follows.
The transformation matrix T (Eq. 7.18) can be decomposed as the summation of
two matrices X and Y. The matrix X is shown below:
0
H0
B G0
B
B
B
B
B
X¼B
B
B
B
B
B
@
1
H1
G1
H0
G0
H1
G1
H0
G0
C
C
C
C
C
C
C
C
C
C
C
C
H1 A
G1
ð7:20Þ
164
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
The matrix X is a 22n 22n , where n is the number of input bits; it can be
described as:
X ¼ I22n2 A
ð7:21Þ
where,
H0
A¼
G0
H1
G1
ð7:22Þ
The H0, H1, G0, and G1 are as given in Eqs. (7.16) and (7.17), respectively.
The matrix Y is shown below:
0
B
B
B
B
B
B
Y¼B
B
B
B
B
B
@ H2
G2
1
H3
G3
H2
G2
H2
G2
H3
G3
H3
G3
C
C
C
C
C
C
C
C
C
C
C
C
A
ð7:23Þ
The matrix Y can be described as:
Y ¼ Q22n2 B
ð7:24Þ
where,
B¼
H2
G2
H3
G3
ð7:25Þ
Q22n2 is the downshift permutation matrix as described in the previous Section.
The H2, H3, G2, and G3 are as given in Eqs. (7.16) and (7.17), respectively.
Figure 7.6 shows the quantum realizations of the matrices X and Y as specified by
Eqs. 7.21 and 7.24, respectively. The circuit of the block Q22n2 in Fig. 7.6b is as
ð4Þ
shown previously in Fig. 7.5. Now, to obtain a single level of the D2n þ 1 multiwavelet transform, the X and Y outputs of Fig. 7.6a, b are applied as inputs to a
quantum adder circuit as shown in Fig. 7.7. The addition of two registers jXi and
jYi can be written as jX, Yi ! jX, X + Yi, where the result of addition is written
into one of the input registers. To prevent overflows, the second register (initially
loaded in state jYi) should be of size q + 1 if both X and Y are encoded on q qubits.
In addition, a temporary register of size q is required, initially in state j0i, to which
the carries of the addition are written (the last carry is the most significant bit of the
result and is written in the last qubit of the second register) [16].
7.5 Quantum Implementation of Daubechies D(4) Multiwavelet
(a)
165
(b)
Fig. 7.6 The realizations of: a Eq. 7.21, b Eq. 7.24; where q = 2n – 1
Fig. 7.7 The realization of
the Daubechies D(4)
multiwavelet transform
The operation of the quantum addition network is illustrated in Fig. 7.8, and can
be described as follows:
• In a first step, all the carries ci are calculated through the relation ci ← xi AND yi
AND ci−1, where xi, yi and ci represent the ith qubit of the first, second and
temporary (carry) register, respectively. Figure 7.9 illustrates the circuit (carry 1)
that performs the carry operation. The last carry gives the most significant digit
of the result.
• Then, subsequently all these operations (except for the last one) are reversed in
order to restore every qubit of the temporary register to its initial state j0i. This
enables to reuse the same temporary register. The other q qubits of the result are
computed through the relation yi ← xi EXOR yi EXOR ci−1 and stored in the
second register. This operation computes the q first digits of the sum (the basic
circuit that performs the summation of three qubits modulo 2 is shown in
Fig. 7.9). The (carry 2) circuit in Fig. 7.8 represents the reversed sequence of
elementary gates embedded in the (carry 1) circuit.
166
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
Fig. 7.8 The quantum adder circuit
Fig. 7.9 Basic carry and sum
operations for the quantum
adder
7.5 Quantum Implementation of Daubechies D(4) Multiwavelet
7.5.4
167
A New Quantum Implementation of Inverse
Daubechies D(4) Multiwavelet Transform
A new quantum implementation of inverse Daubechies D(4) multiwavelet transform
is proposed here, as follows.
The reconstruction matrix R (Eq. 7.19) can be decomposed as the summation of
two matrices Z and W. The matrix Z is shown below:
0
H0
B H1
B
B
B
B
Z¼B
B
B
B
B
@
G0
G1
H0
H1
G0
G1
1
H0
H1
C
C
C
C
C
C
C
C
C
C
G0 A
G1
ð7:26Þ
The matrix Z can be described as:
Z ¼ I22n2 C
ð7:27Þ
where,
H0
C¼
H1
G0
G1
ð7:28Þ
The H0, H1, G0 and G1 are as given in Eqs. (7.16) and (7.17), respectively.
The matrix W is:
0
B
B
B H2
B
B H3
W¼B
B
B
B
B
@
G2
G3
H2
H3
H2
H3
G2
G3
1
G2
G3 C
C
C
C
C
C
C
C
C
C
A
ð7:29Þ
The matrix W can be described as:
W ¼ Qt22n2 D
ð7:30Þ
168
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
Fig. 7.10 Implementation of the inverse Daubechies D(4) multiwavelet transform
where,
2
0 0
61 0
6
6
Qt22n2 ¼ 6 0 1
6 ..
4 .
0 0
..
.
1
3
1
07
7
07
7
.. 7
. 5
0
ð7:31Þ
and
H2
D¼
H3
G2
:
G3
ð7:32Þ
The H2, H3, G2 and G3 are as given in Eqs. (7.16) and (7.17), respectively.
The realization of Eq. (7.27) is similar to that of Eq. (7.21). Also, the realization
of Eq. (7.30) is similar to that of Eq. (7.24), but the Qt22n2 (i.e. the transpose of the
downshift permutation matrix) is used instead of Q22n2 . Figure 7.10 shows the
entire quantum implementation of the inverse D(4) multiwavelet transform.
The quantum arithmetic description of Qt2n is given as:
Qt2n : j an1 an2 . . . a1 a0 i ! j bn1 bn2 . . .b1 b0 i
where bi = ai + 1 (mod 2n).
This description of Qt2n allows its quantum implementation. Hence, it is required
to construct a quantum circuit for jmi ! jm þ 1 mod 2n i. In binary representation, this mapping can be specified in terms of the following operations:
7.5 Quantum Implementation of Daubechies D(4) Multiwavelet
Fig. 7.11 A new circuit for implementation of permutation Qt2n matrix
j an1 an2 . . . a1 a0 i ! j bn1 bn2 . . . b1 b0 i;
b0 ¼ a 0 1
with
b1 ¼ a 1 a 0
b2 ¼ a2 c1 ; where c1 ¼ a1 a0
bi ¼ ai ci1 ; where ci1 ¼ ai1 ci2 for 3 i n 1
Calculating the ci’s and then the bi’s, the circuit in Fig. 7.11 is obtained.
169
170
7 Wavelets and Multiwavelets Implementation Using Quantum Computing
References
1. M. Terraneo, D.L. Shepelyansky, Imperfection effects for multiple applications of the quantum
wavelet transform. Phys. Rev. Lett. 90(25), 257902 (2003)
2. A. Fijany, C.P. Williams, Quantum wavelet transforms: fast algorithms and complete circuits,
in First NASA International Conference on Quantum Computing and Communication (Palm
Spring, 1998), 17–21 Feb 1998, arXiv.quant-ph/9809004v1
3. S. Imre, F. Balazs, Quantum Computing and Communications: An Engineering Approach
(Wiley, NY, 2005)
4. P. Kaye, R. Laflamme, M. Mosca, An Introduction to Quantum Computing (Oxford University
Press Inc, England, 2007)
5. M.A. Nielsen, I.L. Chuang, Quantum Computation and Quantum Information (Cambridge
University Press, Cambridge, 2000)
6. R. Jozsa, Quantum Algorithms and the Fourier Transform. Los Alamos preprint archive.
http://xxx.Lanl.Gov/archive/quant-ph/9707033
7. A. Barenco, A. Ekert, K.-A. Suominen, P. Torma, Approximate quantum fourier transform
and decoherence. Phys. Rev. A 54, 139 (1996). arXiv:quant-ph/9601018v1
8. D. Beckman, A.N. Chari, S. Devabhatuni, J. Preskill, Efficient networks for quantum
factoring. Phys. Rev. A 54(2), 1034 (1996). www.arXiv.quant-ph/9602016v1
9. F. Keinert, Wavelets and Multiwavelets (Chapman and Hall/CRC, UK, 2004)
10. I. Daubechies, Ten Lectures on Wavelets (SIAM, Philadelphia, 1992)
11. A. Klappenecker, Wavelets and Wavelet Packets on Quantum Computers (1999). http://xxx.
Lanl.gov/archive/quant-ph/9909014v1
12. Y.-K. Liu, Quantum Algorithms Using the Curvelet Transform (2009). arXiv.0810.4968v2
[quant-ph]
13. J.D. Edwards, Wavelet Analysis of Two Dimensional Quantum Scattering, Ph.D. thesis,
Department of Physics, Harvard University, Massachusetts
14. A. Susan, ECG Processing Using Wavelets (2000). http://cyber.felk.cvut.cz/gerstner/biolab/
bio_web/teach/KP/WaveletTheory
15. P. Høyer, Efficient Quantum Transforms (1997). http://xxx.lanl.gov/archive/quant-ph/9702028
16. V. Vedral, A. Barenco, A. Ekert, Quantum network for elementary arithmetic operations.
Phys. Rev. A 54, 147 (1995). www.arXiv.org/quant-ph/9511018v1
Chapter 8
Conclusions and Future Researches
Recently, reversible computing has become a fast developing area of research. It
has attracted attention of researchers because of new perspectives to build almost
energy loss-less, ultra-small, and ultra-fast quantum computers. Moreover, there are
some tasks in other areas, including cryptography, digital signal processing, communication, and computer graphics, requiring that all the information encoded in
the inputs be preserved in the outputs. Logic synthesis for reversible circuits is a
first step toward synthesis of quantum circuits. Top world universities, companies
and government institutions are in a race of developing new methodologies,
algorithms and circuits on reversible logic, quantum logic, reversible and quantum
computing and nano-technologies. Quantum computation is a promising application of reversible logic. But, research in the area of quantum circuits is still at the
beginning. Nevertheless, first promising results exist: At the University of
Innsbruck, in Austria, one of the first quantum circuits consisting of 8 qubits was
built in 2005. This has been further improved so that today circuits with dozens of
qubits exist—with upward trend. Even first commercial realizations of quantum
circuits (e.g. a random number generator) are available [1]. Reversible logic is
important in this area because every quantum operation is inherently reversible.
Thus, progress in the domain of reversible logic can be directly applied to quantum
logic.
8.1
Conclusions
The book provides several original contributions to reversible logic synthesis that
can be systematically used to synthesize and evaluate logic functions using
reversible logic. This is the first literature that presents together in an organized
form a variety of twelve known reversible logic synthesis methods.
The main contributions of this book can be summarized as follows:
• A new rule is introduced for eliminating garbage outputs in ternary reversible
Shannon circuits (Sect. 3.2). It depends on testing the entries of the RSGBFM
matrix of the circuit. Then deciding whether it is possible of direct combining
© Springer International Publishing Switzerland 2016
S.M.R. Taha, Reversible Logic Synthesis Methodologies with Application
to Quantum Computing, Studies in Systems, Decision and Control 37,
DOI 10.1007/978-3-319-23479-3_8
171
172
•
•
•
•
•
•
•
•
•
•
•
8 Conclusions and Future Researches
between the forward and the inverse circuits, or some permutations are required
between the outputs of the forward circuit before they are applied to the inverse
circuit.
New algorithms are presented for realizing Shannon, Davio, and (Shannon/
Davio) hybrid expansions of ternary functions into three-dimensional lattice
circuits (Sect. 3.5.4).
The minimal realization of symmetric and non-symmetric ternary functions
in three-dimensional lattice structures using a new optimization method
(Sect. 3.5.6). Guidelines are applied to decide the order of control variables for
minimal realization of the different (Shannon, Davio, and hybrid) decompositions. It is based on calculating the RSPP value of the ternary function.
The minimal realization of symmetrical binary and ternary functions using
reversible lattice circuits and without the need to repeat variables. It is required
that the symmetry indices of the function in the CIN nodes should be of equal
values, otherwise there is a need to repeat variables.
The application of the new algorithm (Sect. 3.5.9) for the 3DTDRL logic circuits synthesis. Both of the synthesis and analysis stages of the algorithm are
achieved simultaneously.
The invention of a new reversible gate (SALEEM) with three versions I, II, and
III (Sect. 3.9.3). It is universal in two arguments which can contribute significantly in reversible logic community. It can be also called reversible logic
module (RLM) [2].
The novel design of (RPGA) synthesis method that makes use of the new
(SALEEM) reversible gate (Sect. 3.9.4). It is superior to previous types of
(RPGA) structures in that the same type of gates is used in the implementation
of the entire circuit.
The application of the new optimization rule (Sect. 3.14) for the constructive
synthesis method of reversible circuits. It is guaranteed that the use of this rule
yields minimal circuits.
A new procedure for the evaluation of the twelve most popular reversible
synthesis techniques (Chap. 4). The (GGS) factor is used for the evaluation. The
synthesis method that yields the minimal value of the (GGS) factor is the best
choice for optimal circuit realization.
For the first time the comparative advantages and disadvantages of the twelve
reversible logic synthesis methods are provided in Table 4.4.
The novel designs of reversible latches and flip flops (Chap. 5). These designs of
new reversible sequential logic circuits are based on utilizing the new
(SALEEM) reversible gate. The implementation costs of the new designs are
more competitive than the currently available designs (Tables 5.8 and 5.9).
The novel implementations of the Daubechies wavelet and multiwavelet
transformations using quantum computing techniques (Chap. 7). Also, a new
quantum implementation of inverse Daubechies multiwavelet transform is
proposed.
8.2 Promising Areas of Further Researches
8.2
173
Promising Areas of Further Researches
Results of the presented book form the basis for further researches. Currently,
several topics need more investigation.
1. There is a lack of technologies with which to build reversible gates. Work is
currently continuing in this area. These technologies are such as
• CMOS, in particular adiabatic CMOS.
• Optical, thermodynamic technology.
• Nanotechnology and DNA technology.
2. The reversible logic synthesis methodologies presented in this book are for
binary and ternary logic systems. It is suggested to extend the same methodologies for multiple-valued reversible logic circuit synthesis. Multiple-valued
reversible logic circuits can potentially reduce the width of the reversible or
quantum circuit which is a limitation in current quantum technology.
3. While there is much research into how to design combinational circuits using
reversible logic, there is little in the area of sequential reversible logic implementations. There is no limitation inherent to reversible logic preventing the
design of sequential circuits. Researches in this area are such as
• The design of state machine using reversible gates. It has reversibility in
logic at every interface between the logic gates and across the circuits. At
any point in the whole circuit, it is possible to map and trace back the output
to a unique input, which satisfies the criteria for reversible systems. This
concept unravels a possibility to implement such very low power state
machines. Such designs would be extremely useful for space applications,
where power consumption is of primary concern. The concept seems to be
quite promising for quantum computing.
• The design of multiple-valued reversible sequential circuits. This is an
emerging area in reversible and quantum logic circuit synthesis.
4. As an application to utilizing quantum computing, the Daubechies quantum
wavelet and multiwavelet transforms are implemented in this book. In a similar
manner, the other types of wavelet and multiwavelet transformations can be
achieved (a promising task for the future).
5. Optical realizations are suggested as a future work for two-valued and
multiple-valued reversible logic circuits. Many optical devices are naturally
reversible. When processing light, such devices can operate on the inputs as
outputs and the outputs as inputs. Optical realizations of reversible logic circuits
can be achieved using linear and non-linear optics domains.
6. The implementation of artificial neural network using multiple-valued quantum
computing is a good area of future researches. The importance of neural networks in application is their ability to learn to perform functions in a problem
domain, based on interacting with data from that domain. A key role in the
process is performed by the training set. The role of training set in classical
174
8 Conclusions and Future Researches
neural network learning can be implemented in the quantum domain. Thus,
there is motivation to establish a mechanism for converting the training set from
the problem domain into the quantum domain. It is possible as a future work to
determine multiple-valued quantum computation equivalents of supervised and
unsupervised learning strategies.
7. Furthermore, questions related to test of reversible circuits will emerge in future.
Already today, first models and approaches in this area exist [1]. But due to the
absence of large physical realizations, it is hard to evaluate the suitability of
them. Additionally, existing approaches cover only some possible technologies.
With ongoing progress in the development of further (and larger) physical
quantum computing or reversible realizations, new models and approaches are
needed to efficiently test them. Then, at the latest, also the design for reversible
logic needs a comprehensive consideration of testing issues.
This is a “global view” on upcoming challenges in this domain. Overall, the
development of an elaborated design flow that is comparable to the one for traditional circuit design (that has been developed in the last 30 years) will take further
years of research. In this context, the contributions in this book provide a good
starting point.
References
1. R. Wille, R. Drechsler, Towards a Design Flow for Reversible Logic. (Springer
Science + Business Media B.V., New York, 2010)
2. S.M.R. Taha, Design of reversible programmable gate array based on new reversible logic
modules. Int. J. Comput. Appl. 93(10), 26–31 (2014)