PWM DC-DC Power Converters Textbook, 2nd Edition

Pulse-Width Modulated DC-DC Power Converters Second Edition Marian K. Kazimierczuk Pulse-Width Modulated DC–DC Power Converters Pulse-Width Modulated DC–DC Power Converters Second Edition MARIAN K. KAZIMIERCZUK Wright State University, Dayton, Ohio, USA This edition first published 2016 © 2016 John Wiley & Sons, Ltd Registered office John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom For details of our global editorial offices, for customer services and for information about how to apply for permission to reuse the copyright material in this book please see our website at www.wiley.com. The right of the author to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988. All rights reserved. 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Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. It is sold on the understanding that the publisher is not engaged in rendering professional services and neither the publisher nor the author shall be liable for damages arising herefrom. If professional advice or other expert assistance is required, the services of a competent professional should be sought Library of Congress Cataloging-in-Publication Data Kazimierczuk, Marian K. Pulse-width modulated DC–DC power converters / Marian K. Kazimierczuk. – Second edition. pages cm Includes bibliographical references and index. ISBN 978-1-119-00954-2 (cloth) 1. DC-to-DC converters. 2. Pulse circuits. 3. PWM power converters. I. Title. TK7872.C8K387 2015 621.381′ 044–dc23 2015018212 A catalogue record for this book is available from the British Library. ISBN: 9781119009542 Set in 9.5/11.5pt Times by Aptara Inc., New Delhi, India 1 2016 To my wife Alicja Contents About the Author xxi Preface xxiii Nomenclature xxv 1 Introduction 1.1 Classification of Power Supplies 1.2 Basic Functions of Voltage Regulators 1.3 Power Relationships in DC–DC Converters 1.4 DC Transfer Functions of DC–DC Converters 1.5 Static Characteristics of DC Voltage Regulators 1.6 Dynamic Characteristics of DC Voltage Regulators 1.7 Linear Voltage Regulators 1.7.1 Series Voltage Regulator 1.7.2 Shunt Voltage Regulator 1.8 Topologies of PWM DC–DC Converters 1.9 Relationships Among Current, Voltage, Energy, and Power 1.10 Summary References Review Questions Problems 1 1 3 4 5 6 9 12 13 14 16 18 19 19 20 21 2 Buck PWM DC–DC Converter 2.1 Introduction 2.2 DC Analysis of PWM Buck Converter for CCM 2.2.1 Circuit Description 2.2.2 Assumptions 2.2.3 Time Interval: 0 < t ≤ DT 2.2.4 Time Interval: DT < t ≤ T 2.2.5 Device Stresses for CCM 2.2.6 DC Voltage Transfer Function for CCM 2.2.7 Boundary Between CCM and DCM 2.2.8 Capacitors 2.2.9 Ripple Voltage in Buck Converter for CCM 2.2.10 Switching Losses with Linear MOSFET Output Capacitance 2.2.11 Switching Losses with Nonlinear MOSFET Output Capacitance 2.2.12 Power Losses and Efficiency of Buck Converter for CCM 2.2.13 DC Voltage Transfer Function of Lossy Converter for CCM 2.2.14 MOSFET Gate-Drive Power 22 22 22 22 25 25 26 27 27 29 31 33 39 40 43 48 48 viii 3 Contents 2.2.15 Gate Driver 2.2.16 Design of Buck Converter for CCM 2.3 DC Analysis of PWM Buck Converter for DCM 2.3.1 Time Interval: 0 < t ≤ DT 2.3.2 Time Interval: DT < t ≤ (D + D1 )T 2.3.3 Time Interval: (D + D1 )T < t ≤ T 2.3.4 Device Stresses for DCM 2.3.5 DC Voltage Transfer Function for DCM 2.3.6 Maximum Inductance for DCM 2.3.7 Power Losses and Efficiency of Buck Converter for DCM 2.3.8 Design of Buck Converter for DCM 2.4 Buck Converter with Input Filter 2.5 Buck Converter with Synchronous Rectifier 2.6 Buck Converter with Positive Common Rail 2.7 Quadratic Buck Converter 2.8 Tapped-Inductor Buck Converters 2.8.1 Tapped-Inductor Common-Diode Buck Converter 2.8.2 Tapped-Inductor Common-Transistor Buck Converter 2.8.3 Watkins–Johnson Converter 2.9 Multiphase Buck Converter 2.10 Switched-Inductor Buck Converter 2.11 Layout 2.12 Summary References Review Questions Problems 49 50 52 56 58 58 59 59 62 63 65 68 68 76 76 79 79 81 82 83 85 85 85 87 88 88 Boost PWM DC–DC Converter 3.1 Introduction 3.2 DC Analysis of PWM Boost Converter for CCM 3.2.1 Circuit Description 3.2.2 Assumptions 3.2.3 Time Interval: 0 < t ≤ DT 3.2.4 Time Interval: DT < t ≤ T 3.2.5 DC Voltage Transfer Function for CCM 3.2.6 Boundary Between CCM and DCM 3.2.7 Ripple Voltage in Boost Converter for CCM 3.2.8 Power Losses and Efficiency of Boost Converter for CCM 3.2.9 DC Voltage Transfer Function of Lossy Boost Converter for CCM 3.2.10 Design of Boost Converter for CCM 3.3 DC Analysis of PWM Boost Converter for DCM 3.3.1 Time Interval: 0 < t ≤ DT 3.3.2 Time Interval: DT < t ≤ (D + D1 )T 3.3.3 Time Interval: (D + D1 )T < t ≤ T 3.3.4 Device Stresses for DCM 3.3.5 DC Voltage Transfer Function for DCM 3.3.6 Maximum Inductance for DCM 3.3.7 Power Losses and Efficiency of Boost Converter for DCM 3.3.8 Design of Boost Converter for DCM 90 90 90 90 91 93 94 94 95 98 100 102 103 107 110 111 112 112 112 117 117 120 Contents 4 ix 3.4 3.5 3.6 Bidirectional Buck and Boost Converters Synchronous Boost Converter Tapped-Inductor Boost Converters 3.6.1 Tapped-Inductor Common-Diode Boost Converter 3.6.2 Tapped-Inductor Common-Load Boost Converter 3.7 Duality 3.8 Power Factor Correction 3.8.1 Power Factor 3.8.2 Boost Power Factor Corrector 3.8.3 Electronic Ballasts for Fluorescent Lamps 3.9 Summary References Review Questions Problems 127 129 129 131 132 133 134 134 138 141 141 142 143 143 Buck–Boost PWM DC–DC Converter 4.1 Introduction 4.2 DC Analysis of PWM Buck–Boost Converter for CCM 4.2.1 Circuit Description 4.2.2 Assumptions 4.2.3 Time Interval: 0 < t ≤ DT 4.2.4 Time Interval: DT < t ≤ T 4.2.5 DC Voltage Transfer Function for CCM 4.2.6 Device Stresses for CCM 4.2.7 Boundary Between CCM and DCM 4.2.8 Ripple Voltage in Buck–Boost Converter for CCM 4.2.9 Power Losses and Efficiency of the Buck–Boost Converter for CCM 4.2.10 DC Voltage Transfer Function of Lossy Buck–Boost Converter for CCM 4.2.11 Design of Buck–Boost Converter for CCM 4.3 DC Analysis of PWM Buck–Boost Converter for DCM 4.3.1 Time Interval: 0 < t ≤ DT 4.3.2 Time Interval: DT < t ≤ (D + D1 )T 4.3.3 Time Interval: (D + D1 )T < t ≤ T 4.3.4 Device Stresses of the Buck–Boost Converter in DCM 4.3.5 DC Voltage Transfer Function of the Buck–Boost Converter for DCM 4.3.6 Maximum Inductance for DCM 4.3.7 Power Losses and Efficiency of the Buck–Boost Converter in DCM 4.3.8 Design of Buck–Boost Converter for DCM 4.4 Bidirectional Buck–Boost Converter 4.5 Synthesis of Buck–Boost Converter 4.6 Synthesis of Boost–Buck (Ćuk) Converter 4.7 Noninverting Buck–Boost Converters 4.7.1 Cascaded Noninverting Buck–Boost Converters 4.7.2 Four-Transistor Noninverting Buck–Boost Converters 4.8 Tapped-Inductor Buck–Boost Converters 4.8.1 Tapped-Inductor Common-Diode Buck–Boost Converter 4.8.2 Tapped-Inductor Common-Transistor Buck–Boost Converter 4.8.3 Tapped-Inductor Common-Load Buck–Boost Converter 4.8.4 Tapped-Inductor Common-Source Buck–Boost Converter 145 145 145 145 146 146 148 149 150 151 152 155 158 159 162 165 166 167 167 167 170 172 174 180 181 183 184 184 184 186 186 187 188 191 x Contents 4.9 Summary References Review Questions Problems 192 192 193 193 5 Flyback PWM DC–DC Converter 5.1 Introduction 5.2 Transformers 5.3 DC Analysis of PWM Flyback Converter for CCM 5.3.1 Derivation of PWM Flyback Converter 5.3.2 Circuit Description 5.3.3 Assumptions 5.3.4 Time Interval: 0 < t ≤ DT 5.3.5 Time Interval: DT < t ≤ T 5.3.6 DC Voltage Transfer Function for CCM 5.3.7 Boundary Between CCM and DCM 5.3.8 Ripple Voltage in Flyback Converter for CCM 5.3.9 Power Losses and Efficiency of Flyback Converter for CCM 5.3.10 DC Voltage Transfer Function of Lossy Converter for CCM 5.3.11 Design of Flyback Converter for CCM 5.4 DC Analysis of PWM Flyback Converter for DCM 5.4.1 Time Interval: 0 < t ≤ DT 5.4.2 Time Interval: DT < t ≤ (D + D1 )T 5.4.3 Time Interval: (D + D1 )T < t ≤ T 5.4.4 DC Voltage Transfer Function for DCM 5.4.5 Maximum Magnetizing Inductance for DCM 5.4.6 Ripple Voltage in Flyback Converter for DCM 5.4.7 Power Losses and Efficiency of Flyback Converter for DCM 5.4.8 Design of Flyback Converter for DCM 5.5 Multiple-Output Flyback Converter 5.6 Bidirectional Flyback Converter 5.7 Ringing in Flyback Converter 5.8 Flyback Converter with Passive Dissipative Snubber 5.9 Flyback Converter with Zener Diode Voltage Clamp 5.10 Flyback Converter with Active Clamping 5.11 Two-Transistor Flyback Converter 5.12 Summary References Review Questions Problems 195 195 196 197 197 197 199 200 201 203 204 205 207 210 211 214 217 219 220 221 222 225 226 228 232 237 237 240 240 241 241 243 244 244 245 6 Forward PWM DC–DC Converter 6.1 Introduction 6.2 DC Analysis of PWM Forward Converter for CCM 6.2.1 Derivation of Forward PWM Converter 6.2.2 Time Interval: 0 < t ≤ DT 6.2.3 Time Interval: DT < t ≤ DT + tm 6.2.4 Time Interval: DT + tm < t ≤ T 6.2.5 Maximum Duty Cycle 246 246 246 246 248 251 253 253 Contents 7 xi 6.2.6 Device Stresses 6.2.7 DC Voltage Transfer Function for CCM 6.2.8 Boundary Between CCM and DCM 6.2.9 Ripple Voltage in Forward Converter for CCM 6.2.10 Power Losses and Efficiency of Forward Converter for CCM 6.2.11 DC Voltage Transfer Function of Lossy Converter for CCM 6.2.12 Design of Forward Converter for CCM 6.3 DC Analysis of PWM Forward Converter for DCM 6.3.1 Time Interval: 0 < t ≤ DT 6.3.2 Time Interval: DT < t ≤ DT + tm 6.3.3 Time Interval: DT + tm < t ≤ (D + D1 )T 6.3.4 Time Interval: (D + D1 )T < t ≤ T 6.3.5 DC Voltage Transfer Function for DCM 6.3.6 Maximum Inductance for DCM 6.3.7 Power Losses and Efficiency of Forward Converter for DCM 6.3.8 Design of Forward Converter for DCM 6.4 Multiple-Output Forward Converter 6.5 Forward Converter with Synchronous Rectifier 6.6 Forward Converters with Active Clamping 6.7 Two-Switch Forward Converter 6.8 Forward–Flyback Converter 6.9 Summary References Review Questions Problems 254 255 255 256 258 261 262 269 269 272 273 273 274 277 278 280 288 288 288 290 291 292 293 293 294 Half-Bridge PWM DC–DC Converter 7.1 Introduction 7.2 DC Analysis of PWM Half-Bridge Converter for CCM 7.2.1 Circuit Description 7.2.2 Assumptions 7.2.3 Time Interval: 0 < t ≤ DT 7.2.4 Time Interval: DT < t ≤ T∕2 7.2.5 Time Interval: T∕2 < t ≤ T∕2 + DT 7.2.6 Time Interval: T∕2 + DT < t ≤ T 7.2.7 Device Stresses 7.2.8 DC Voltage Transfer Function of Lossless Half-Bridge Converter for CCM 7.2.9 Boundary Between CCM and DCM 7.2.10 Ripple Voltage in Half-Bridge Converter for CCM 7.2.11 Power Losses and Efficiency of Half-Bridge Converter for CCM 7.2.12 DC Voltage Transfer Function of Lossy Converter for CCM 7.2.13 Design of Half-Bridge Converter for CCM 7.3 DC Analysis of PWM Half-Bridge Converter for DCM 7.3.1 Time Interval: 0 < t ≤ DT 7.3.2 Time Interval: DT < t ≤ (D + D1 )T 7.3.3 Time Interval: (D + D1 )T < t ≤ T∕2 7.3.4 DC Voltage Transfer Function for DCM 7.3.5 Maximum Inductance for DCM 296 296 296 296 299 299 301 303 304 304 304 305 306 308 311 312 315 315 320 322 322 326 xii Contents 7.4 Summary References Review Questions Problems 326 327 327 328 8 Full-Bridge PWM DC–DC Converter 8.1 Introduction 8.2 DC Analysis of PWM Full-Bridge Converter for CCM 8.2.1 Circuit Description 8.2.2 Assumptions 8.2.3 Time Interval: 0 < t ≤ DT 8.2.4 Time Interval: DT < t ≤ T∕2 8.2.5 Time Interval: T∕2 < t ≤ T∕2 + DT 8.2.6 Time Interval: T∕2 + DT < t ≤ T 8.2.7 Device Stresses 8.2.8 DC Voltage Transfer Function of Lossless Full-Wave Converter for CCM 8.2.9 Boundary Between CCM and DCM 8.2.10 Ripple Voltage in Full-Bridge Converter for CCM 8.2.11 Power Losses and Efficiency of Full-Bridge Converter for CCM 8.2.12 DC Voltage Transfer Function of Lossy Converter for CCM 8.2.13 Design of Full-Bridge Converter for CCM 8.3 DC Analysis of PWM Full-Bridge Converter for DCM 8.3.1 Time Interval: 0 < t ≤ DT 8.3.2 Time Interval: DT < t ≤ (D + D1 )T 8.3.3 Time Interval: (D + D1 )T < t ≤ T∕2 8.3.4 DC Voltage Transfer Function for DCM 8.3.5 Maximum Inductance for DCM 8.4 Phase-Controlled Full-Bridge Converter 8.5 Summary References Review Questions Problems 330 330 330 330 332 332 334 336 336 337 337 338 339 340 344 345 351 351 353 355 356 359 361 362 362 362 363 9 Small-Signal Models of PWM Converters for CCM and DCM 9.1 Introduction 9.2 Assumptions 9.3 Averaged Model of Ideal Switching Network for CCM 9.4 Averaged Values of Switched Resistances 9.5 Model Reduction 9.6 Large-Signal Averaged Model for CCM 9.7 DC and Small-Signal Circuit Linear Models of Switching Network for CCM 9.7.1 Large-Signal Circuit Model of Switching Network for CCM 9.7.2 Linearization of Switching Network Model for CCM 9.8 Block Diagram of Small-signal Model of PWM DC–DC Converters 9.9 Family of PWM Converter Models for CCM 9.10 PWM Small-Signal Switch Model for CCM 9.11 Modeling of Ideal Switching Network for DCM 9.11.1 Relationships Among DC Components for DCM 9.11.2 Small-Signal Model of Ideal Switching Network for DCM 365 365 366 366 369 375 377 381 381 384 385 386 389 391 391 395 Contents xiii 9.12 Averaged Parasitic Resistances for DCM 9.13 Summary References Review Questions Problems 398 400 402 405 405 10 Small-Signal Characteristics of Buck Converter for CCM 10.1 Introduction 10.2 Small-Signal Model of the PWM Buck Converter 10.3 Open-Loop Transfer Functions 10.3.1 Open-Loop Control-to-Output Transfer Function 10.3.2 Delay in Control-to-Output Transfer Function 10.3.3 Open-Loop Input-to-Output Transfer Function 10.3.4 Open-Loop Input Impedance 10.3.5 Open-Loop Output Impedance 10.4 Open-Loop Step Responses 10.4.1 Open-Loop Response of Output Voltage to Step Change in Input Voltage 10.4.2 Open-Loop Response of Output Voltage to Step Change in Duty Cycle 10.4.3 Open-Loop Response of Output Voltage to Step Change in Load Current 10.5 Open-Loop DC Transfer Functions 10.6 Summary References Review Questions Problems 407 407 407 408 409 416 418 420 423 426 426 431 433 434 436 436 437 438 11 Small-Signal Characteristics of Boost Converter for CCM 11.1 Introduction 11.2 DC Characteristics 11.3 Open-Loop Control-to-Output Transfer Function 11.4 Delay in Open-Loop Control-to-Output Transfer Function 11.5 Open-Loop Audio Susceptibility 11.6 Open-Loop Input Impedance 11.7 Open-Loop Output Impedance 11.8 Open-Loop Step Responses 11.8.1 Open-Loop Response of Output Voltage to Step Change in Input Voltage 11.8.2 Open-Loop Response of Output Voltage to Step Change in Duty Cycle 11.8.3 Open-Loop Response of Output Voltage to Step Change in Load Current 11.9 Summary References Review Questions Problems 439 439 439 440 449 451 455 457 461 461 464 465 467 467 468 468 12 Voltage-Mode Control of PWM Buck Converter 12.1 Introduction 12.2 Properties of Negative Feedback 12.3 Stability 12.4 Single-Loop Control of PWM Buck Converter 12.5 Closed-Loop Small-Signal Model of Buck Converter 12.6 Pulse-Width Modulator 470 470 471 474 475 478 478 xiv Contents 12.7 12.8 12.9 Feedback Network Transfer Function of Buck Converter with Modulator and Feedback Network Control Circuits 12.9.1 Error Amplifier 12.9.2 Proportional Controller 12.9.3 Integral Controller 12.9.4 Proportional-Integral Controller 12.9.5 Integral-Single-Lead Controller 12.9.6 Loop Gain 12.9.7 Closed-Loop Control-to-Output Voltage Transfer Function 12.9.8 Closed-Loop Input-to-Output Transfer Function 12.9.9 Closed-Loop Input Impedance 12.9.10 Closed-Loop Output Impedance 12.10 Closed-Loop Step Responses 12.10.1 Response to Step Change in Input Voltage 12.10.2 Response to Step Change in Reference Voltage 12.10.3 Closed-Loop Response to Step Change in Load Current 12.10.4 Closed-Loop DC Transfer Functions 12.11 Summary References Review Questions Problems 483 486 489 489 490 492 493 497 504 504 506 508 509 511 511 513 515 515 518 519 519 520 13 Voltage-Mode Control of Boost Converter 13.1 Introduction 13.2 Circuit of Boost Converter with Voltage-Mode Control 13.3 Transfer Function of Modulator, Boost Converter Power Stage, and Feedback Network 13.4 Integral-Double-Lead Controller 13.5 Design of Integral-Double-Lead Controller 13.6 Loop Gain 13.7 Closed-Loop Control-to-Output Voltage Transfer Function 13.8 Closed-Loop Audio Susceptibility 13.9 Closed-Loop Input Impedance 13.10 Closed-Loop Output Impedance 13.11 Closed-Loop Step Responses 13.11.1 Closed-Loop Response to Step Change in Input Voltage 13.11.2 Closed-Loop Response to Step Change in Reference Voltage 13.11.3 Closed-Loop Response to Step Change in Load Current 13.12 Closed-Loop DC Transfer Functions 13.13 Summary References Review Questions Problems 521 521 521 523 527 532 536 537 539 539 542 544 544 547 548 549 552 552 552 553 14 Current-Mode Control 14.1 Introduction 14.2 Principle of Operation of PWM Converters with Peak CMC 14.3 Relationship Between Duty Cycle and Inductor-Current Slopes 14.4 Instability of Closed-Current Loop 554 554 555 559 560 Contents 14.5 Slope Compensation 14.5.1 Analysis of Slope Compensation in Time Domain 14.5.2 Boundary of Slope Compensation for Buck and Buck–Boost Converters 14.5.3 Boundary Slope Compensation for Boost Converter 14.6 Sample-and-Hold Effect on Current Loop 14.6.1 Natural Response of Inductor Current to Small Perturbation in Closed-Current Loop 14.6.2 Forced Response of Inductor Current to Step Change in Control Voltage in Closed-Current Loop 14.6.3 Relationship Between s-Domain and z-Domain 14.6.4 Transfer Function of Closed-Current Loop in z-Domain 14.7 Closed-Loop Control Voltage-to-Inductor Current Transfer Function in s-Domain 14.7.1 Approximation of Hicl by Rational Transfer Function 14.7.2 Step Responses of Closed-Inner Loop 14.8 Loop Gain of Current Loop 14.8.1 Loop Gain of Inner Loop in z-Domain 14.8.2 Loop Gain of Inner Loop in s-Domain 14.9 Gain-Crossover Frequency of Inner Loop 14.10 Phase Margin of Inner Loop 14.11 Maximum Duty Cycle for Converters Without Slope Compensation 14.12 Maximum Duty Cycle for Converters with Slope Compensation 14.13 Minimum Slope Compensation for Buck and Buck–Boost Converter 14.14 Minimum Slope Compensation for Boost Converter 14.15 Error Voltage-to-Duty Cycle Transfer Function 14.16 Closed-Loop Control Voltage-to-Duty Cycle Transfer Function of Current Loop 14.17 Alternative Representation of Current Loop 14.18 Current Loop with Disturbances 14.18.1 Modified Approximation of Current Loop 14.19 Voltage Loop of PWM Converters with Current-Mode Control 14.19.1 Control-to-Output Transfer Function for Buck Converter 14.19.2 Block Diagram of Power Stages of PWM Converters 14.19.3 Closed-Voltage Loop Transfer Function of PWM Converters with Current-Mode Control 14.19.4 Closed-Loop Audio Susceptibility of PWM Converters with Current-Mode Control 14.19.5 Closed-Loop Output Impedance of PWM Converters with Current-Mode Control 14.20 Feedforward Gains in PWM Converters with Current-Mode Control without Slope Compensation 14.21 Feedforward Gains in PWM Converters with Current-Mode Control and Slope Compensation 14.22 Control-to-Output Voltage Transfer Function of Inner Loop with Feedforward Gains 14.23 Audio-Susceptibility of Inner Loop with Feedforward Gains 14.24 Closed-Loop Transfer Functions with Feedforward Gains 14.25 Slope Compensation by Adding a Ramp to Inductor Current Waveform 14.26 Relationships for Constant-Frequency Current-Mode On-Time Control 14.27 Summary References Review Questions Problems xv 564 564 569 570 570 572 575 577 578 580 582 588 588 588 590 595 596 598 600 605 607 610 614 618 618 619 624 624 627 628 628 630 631 634 636 637 638 638 639 639 640 644 644 xvi Contents 14.28 Appendix: Sample-and-Hold Modeling 14.28.1 Sampler of the Control Voltage 14.28.2 Zero-Order Hold of Inductor Current 14.28.3 Approximations of esTs 645 645 648 650 15 Current-Mode Control of Boost Converter 15.1 Introduction 15.2 Open-Loop Small-Signal Transfer Functions 15.2.1 Open-Loop Duty Cycle-to-Inductor Current Transfer Function 15.2.2 High-Frequency Open-Loop Duty Cycle-to-Inductor Current Transfer Function 15.2.3 Open-Loop Input Voltage-to-Inductor Current Transfer Function 15.2.4 Open-Loop Inductor-to-Output Current Transfer Function 15.3 Open-Loop Step Responses of Inductor Current 15.3.1 Open-Loop Response of Inductor Current to Step Change in Input Voltage 15.3.2 Open-Loop Response of the Inductor Current to Step Change in the Duty Cycle 15.3.3 Open-Loop Response of Inductor Current to Step Change in Load Current 15.4 Closed-Current-Loop Transfer Functions 15.4.1 Forward Gain 15.4.2 Loop Gain of Current Loop 15.4.3 Closed-Loop Gain of Current Loop 15.4.4 Control-to-Output Transfer Function 15.4.5 Input Voltage-to-Duty Cycle Transfer Function 15.4.6 Load Current-to-Duty Cycle Transfer Function 15.4.7 Output Impedance of Closed-Current Loop 15.5 Closed-Voltage-Loop Transfer Functions 15.5.1 Control-to-Output Transfer Function 15.5.2 Control Voltage-to-Feedback Voltage Transfer Function 15.5.3 Loop Gain of Voltage Loop 15.5.4 Closed-Loop Gain of Voltage Loop 15.5.5 Closed-Loop Audio Susceptibility with Integral Controller 15.5.6 Closed-Loop Output Impedance with Integral Controller 15.6 Closed-Loop Step Responses 15.6.1 Closed-Loop Response of Output Voltage to Step Change in Input Voltage 15.6.2 Closed-Loop Response of Output Voltage to Step Change in Load Current 15.6.3 Closed-Loop Response of Output Voltage to Step Change in Reference Voltage 15.7 Closed-Loop DC Transfer Functions 15.8 Summary References Review Questions Problems 653 653 653 653 659 660 665 667 667 670 672 675 675 675 675 677 684 688 690 695 695 695 697 701 703 704 706 706 708 708 710 711 711 712 712 16 Open-Loop Small-Signal Characteristics of PWM Boost Converter for DCM 16.1 Introduction 16.2 Small-Signal Model of Boost Converter for DCM 16.3 Open-Loop Control-to-Output Transfer Function 16.4 Open-Loop Input-to-Output Voltage Transfer Function 16.5 Open-Loop Input Impedance 16.6 Open-Loop Output Impedance 713 713 713 716 719 724 725 Contents 17 xvii 16.7 Step Responses of Output Voltage of Boost Converter for DCM 16.7.1 Response of Output Voltage to Step Change in Input Voltage 16.7.2 Response of Output Voltage to Step Change in Duty Cycle 16.7.3 Response of Output Voltage to Step Change in Load Current 16.8 Open-Loop Duty Cycle-to-Inductor Current Transfer Function 16.9 Open-Loop Input Voltage-to-Inductor Current Transfer Function 16.10 Open-Loop Output Current-to-Inductor Current Transfer Function 16.11 Step Responses of Inductor Current of Boost Converter for DCM 16.11.1 Step Response of Inductor Current to Step Change in Input Voltage 16.11.2 Step Response of Inductor Current to Step Change in Duty Cycle 16.11.3 Step Response of Inductor Current to Step Change in Load Current 16.12 DC Characteristics of Boost Converter for DCM 16.12.1 DC-to-DC Voltage Transfer Function of Lossless Boost Converter for DCM 16.12.2 DC-to-DC Voltage Transfer Function of Lossy Boost Converter for DCM 16.12.3 Efficiency of Boost Converter for DCM 16.13 Summary References Review Questions Problems 728 728 730 730 731 735 735 738 738 740 741 742 742 743 745 745 745 746 746 Silicon and Silicon-Carbide Power Diodes 17.1 Introduction 17.2 Electronic Power Switches 17.3 Atom 17.4 Electron and Hole Effective Mass 17.5 Semiconductors 17.6 Intrinsic Semiconductors 17.7 Extrinsic Semiconductors 17.7.1 n-Type Semiconductor 17.7.2 p-Type Semiconductor 17.7.3 Maximum Operating Temperature 17.8 Wide Band Gap Semiconductors 17.9 Physical Structure of Junction Diodes 17.9.1 Formation of Depletion Layer 17.9.2 Charge Transport 17.10 Static I–V Diode Characteristic 17.11 Breakdown Voltage of Junction Diodes 17.11.1 Depletion-Layer Width 17.11.2 Electric Field Intensity Distribution 17.11.3 Avalanche Breakdown Voltage 17.11.4 Punch-Through Breakdown Voltage 17.11.5 Edge Terminations 17.12 Capacitances of Junction Diodes 17.12.1 Junction Capacitance 17.12.2 Diffusion Capacitance 17.13 Reverse Recovery of pn Junction Diodes 17.13.1 Qualitative Description 17.13.2 Reverse Recovery in Resistive Circuits 747 747 747 748 749 750 751 756 756 759 761 762 764 765 767 768 772 773 775 779 781 782 784 784 787 789 789 790 xviii 18 Contents 17.13.3 Charge-Continuity Equation 17.13.4 Reverse Recovery in Inductive Circuits 17.14 Schottky Diodes 17.14.1 Static I–V Characteristic of Schottky Diodes 17.14.2 Breakdown Voltages of Schottky Diodes 17.14.3 Junction Capacitance of Schottky Diodes 17.14.4 Switching Characteristics of Schottky Diodes 17.15 Solar Cells 17.16 Light-Emitting Diodes 17.17 SPICE Model of Diodes 17.18 Summary References Review Questions Problems 793 796 798 801 802 802 802 806 809 810 811 815 816 817 Silicon and Silicon-Carbide Power MOSFETs 18.1 Introduction 18.2 Integrated MOSFETs 18.3 Physical Structure of Power MOSFETs 18.4 Principle of Operation of Power MOSFETs 18.4.1 Cutoff Region 18.4.2 Formation of MOSFET Channel 18.4.3 Linear Region 18.4.4 Saturation Region 18.4.5 Antiparallel Diode 18.5 Derivation of Power MOSFET Characteristics 18.5.1 Ohmic Region 18.5.2 Pinch-off Region 18.5.3 Channel-Length Modulation 18.6 Power MOSFET Characteristics 18.7 Mobility of Charge Carriers 18.7.1 Effect of Doping Concentration on Mobility 18.7.2 Effect of Temperature on Mobility 18.7.3 Effect of Electric Field on Mobility 18.8 Short-Channel Effects 18.8.1 Ohmic Region 18.8.2 Pinch-off Region 18.9 Aspect Ratio of Power MOSFETs 18.10 Breakdown Voltage of Power MOSFETs 18.11 Gate Oxide Breakdown Voltage of Power MOSFETs 18.12 Specific On-Resistance 18.13 Figures-of-Merit of Semiconductors 18.14 On-Resistance of Power MOSFETs 18.14.1 Channel Resistance 18.14.2 Accumulation Region Resistance 18.14.3 Neck Region Resistance 18.14.4 Drift Region Resistance 18.15 Capacitances of Power MOSFETs 18.15.1 Gate-to-Source Capacitance 819 819 819 819 824 824 824 824 825 825 826 826 829 830 831 833 834 836 840 846 846 847 848 850 852 852 855 857 857 857 858 859 862 862 Contents xix 18.15.2 Drain-to-Source Capacitance 18.15.3 Gate-to-Drain Capacitance 18.16 Switching Waveforms 18.17 SPICE Model of Power MOSFETs 18.18 IGBTs 18.19 Heat Sinks 18.20 Summary References Review Questions Problems 864 864 875 877 879 880 886 888 888 889 19 Electromagnetic Compatibility 19.1 Introduction 19.2 Definition of EMI 19.3 Definition of EMC 19.4 EMI Immunity 19.5 EMI Susceptibility 19.6 Classification of EMI 19.7 Sources of EMI 19.8 Safety Standards 19.9 EMC Standards 19.10 Near Field and Far Field 19.11 Techniques of EMI Reduction 19.12 Insertion Loss 19.13 EMI Filters 19.14 Feed-Through Capacitors 19.15 EMI Shielding 19.16 Interconnections 19.17 Summary References Review Questions Problem 891 891 891 892 892 893 893 895 896 896 897 897 898 898 900 900 902 903 903 903 904 A Introduction to SPICE 907 B Introduction to MATLAB® 910 C Physical Constants 915 Answers to Problems 917 Index 925 About the Author Marian K. Kazimierczuk is Frederick A. White Distinguished Professor of Electrical Engineering at Wright State University, Dayton, Ohio, USA. He received the M.S., Ph.D., and D.Sc. degrees from Warsaw University of Technology, Department of Electronics, Warsaw, Poland. He is the author of six books, over 180 archival refereed journal papers, over 210 conference papers, and seven patents. His research interests are in power electronics, including RF high-efficiency power amplifiers and oscillators, PWM dc–dc power converters, resonant dc–dc power converters, modeling and controls of power converter, highfrequency magnetic devices, electronic ballasts, active power factor correctors, semiconductor power devices, wireless charging systems, renewable energy sources, energy harvesting, green energy, and evanescent microwave microscopy. Professor Kazimierczuk is a Fellow of the IEEE. He served as Chair of the Technical Committee of Power Systems and Power Electronics Circuits, IEEE Circuits and Systems Society. He served on the Technical Program Committees of the IEEE International Symposium on Circuits and Systems (ISCAS) and the IEEE Midwest Symposium on Circuits and Systems. He also served as Associate Editor of the IEEE Transactions on Circuits and Systems, Part I, Regular Papers, IEEE Transactions on Industrial Electronics, International Journal of Circuit Theory and Applications, and Journal of Circuits, Systems, and Computers, and as Guest Editor of the IEEE Transactions on Power Electronics. He was an IEEE Distinguished Lecturer. Professor Kazimierczuk received the Presidential Award for Outstanding Faculty Member at Wright State University in 1995. He was Brage Golding Distinguished Professor of Research at Wright State University in 1996–2000. He received the Trustees’ Award from Wright State University for Faculty Excellence in 2004. He received the Outstanding Teaching Award from the American Society for Engineering Education (ASEE) in 2008. He was also honored with the Excellence in Research Award, Excellence in Teaching Awards, and Excellence in Professional Service Award in the College of Engineering and Computer Science, Wright State University. He is listed in Top Authors in Engineering and Top Authors in Electrical & Electronic Engineering. Professor Kazimierczuk is the author or co-author of six books: Resonant Power Converters, 2nd Ed., Wiley, Pulse-Width Modulated DC–DC Power Converters, IEEE Press/Wiley, High-Frequency Magnetic Components, 2nd Ed. (translated in Chinese), Wiley, RF Power Amplifiers, 2nd Ed. (translated in Chinese), Wiley, Electronic Devices, A Design Approach, Pearson/Prentice Hall, and Laboratory Manual to Accompany Electronic Devices, A Design Approach, 2nd Ed., Pearson/Prentice Hall. Preface This book is about switching-mode dc–dc power converters with pulse-width modulation (PWM) control. It is intended as a power electronics textbook at the senior and graduate levels for students majoring in electrical engineering, as well as a reference for practicing engineers in the area of power electronics. The purpose of the book is to provide foundations for semiconductor power devices, topologies of PWM switching-mode dc–dc power converters, modeling, dynamics, and controls of PWM converters. The book is devoted to energy conversion. The first part of the book covers topologies of transformerless and isolated PWM converters, such as buck, boost, and buck–boost, flyback, forward, half-bridge, and full-bridge converters. The second part covers small-signal circuit models of PWM converters, transfer functions of PWM converter power stages, voltage-mode control, and current-mode control of PWM converters. The third part presents silicon and silicon carbide power devices. The textbook assumes that the student is familiar with general circuit analysis techniques and electronic circuits. Complete solutions for all problems are included in the Solutions Manual, which is available from the publisher for those instructors who adopt the book for their courses. I am pleased to express my gratitude to Dr. Nisha Kondrath and Agasthya Ayachit for MATLAB® figures, proofreading, suggestions, and critical evaluation of the manuscript. Throughout the entire course of this project, the support provided by John Wiley & Sons was excellent. I wish to express my sincere thanks to Ella Mitchell, Associate Commissioning Editor, Electrical Engineering; Peter Mitchell, Publisher, Engineering Technology; and Richard Davis, Senior Project Editor. It has been a real pleasure working with them. Last but not least, I wish to thank my family for the support. The author would welcome and greatly appreciate suggestions and corrections from the readers, for the improvements in the technical content as well as the presentation style. Marian K. Kazimierczuk Nomenclature A Ai AJ BW C Cb Cc Cds Cgd Cgs Ciss Cmin Co Coss Cox Crss c D d dm dT ESR fc fz f0 fp fs f−180 Hsh ICrms Ipk Irms ID IDM IDrms II IL ILB IO IOmax IOmin Transfer function of forward path in negative feedback system Inductor-to-load current transfer function Cross-sectional area of junction Bandwidth Filter capacitance Blocking capacitance Coupling capacitance Drain–source capacitance of MOSFET Gate–drain capacitance of MOSFET Gate–source capacitance of MOSFET MOSFET input capacitance at VDS = 0, Ciss = Cgs + Cgd Minimum value of filter capacitance C Transistor output capacitance MOSFET output capacitance at VGD = 0, Coss = Cgs + Cds Oxide capacitance per unit area MOSFET transfer capacitance, Crss = Cgd Speed of light DC component of on-duty cycle of switch AC component of on-duty cycle of switch Amplitude of small-signal component of on-duty cycle of switch Total on-duty cycle of switch Equivalent series resistance of capacitors and inductors Gain-crossover frequency Frequency of zero of transfer function Corner frequency Frequency of pole of transfer function Switching frequency Phase-crossover frequency Transfer function of sampler and zero-order hold rms value of capacitor current iC Magnitude of cross-conduction current rms value of current i Average diode current Peak diode current rms value of diode current DC input current of converter Average current through inductor L Average current through inductor L at CCM/DCM boundary DC output current of converter Maximum value of dc load current IO Minimum value of dc load current IO xxvi IOB ISM ISrms ii i0i (t) io iC iD iL iO iS Ki Ko k L Le Ln Lp Lm Lmax Lmin LNR LOR MIDC MVDC Mv Mvcl Mvi Mvo me me ∗ mh mh ∗ NA ND Np Ns n n+ ni nn np np0 pn pn0 pp PM Pton PD Nomenclature DC output current at the boundary between CCM and DCM Peak switch current rms value of switch current iS AC component of input current Zero-order-hold AC component of input current AC component of load current Current through filter capacitor C Diode current Current through inductor L Total load current Switch current Input feedforward gain Output feedforward gain Boltzmann constant Inductance, Channel length Effective channel length Electron diffusion length Hole diffusion length Magnetizing inductance of transformer Maximum inductance L for DCM operation Minimum inductance L for CCM operation Line regulation Load regulation DC current transfer function of converter DC voltage transfer function of converter Open-loop input-to-output voltage function of converter Closed-loop input-to-output voltage function of converter Open-loop input voltage-to-inductor current transfer function Open-loop input-to-output voltage function of converter at f = 0 Mass of free electron Effective mass of electron Mass of hole Effective mass of hole Concentration of acceptors Concentration of donors Number of turns of primary winding Number of turns of secondary winding Transformer turns ratio, electron concentration density Electron concentration of heavily doped semiconductor by donors Intrinsic carrier concentration Majority electron concentration Minority electron concentration Thermal equilibrium minority electron concentration Minority hole concentration Thermal equilibrium minority hole concentration Majority hole concentration Phase margin Turn-on switching losses Total diode conduction loss Nomenclature PFET PG PI PLS PM PO PRF PrC PVF p p+ Q Qg QF Qrr q RDR RF RL RLB RLmax RLmin rC rDS q S Smax SR T TA Tc Tcl Ti TJ Tm Tp Tpi Tpo THD tf tr trr Vbi VC Vcm VCpp VE Vt VBD Overall power dissipation in MOSFET (excluding gate-drive power) Gate-drive power DC input power of converter Overall power dissipation of converter Phase margin DC output power of converter Conduction loss in diode forward resistance RF Conduction loss in filter capacitor ESR Conduction loss in diode offset voltage VF Hole concentration Hole concentration of heavily doped semiconductor by acceptors Quality factor Gate charge Forward stored charge Reverse recovery charge Magnitude of electron charge Resistance of drift region Diode forward resistance DC load resistance DC load resistance at CCM/DCM boundary Maximum value of load resistance RL Minimum value of load resistance RL Equivalent series resistance (ESR) of filter capacitor On-resistance of MOSFET Electron charge Specific resistance of drift region Maximum percentage overshoot Slew rate of op-amps Switching period, Loop gain Ambient temperature Voltage transfer function of controller Closed-loop control-to-output transfer function Loop gain of current loop Junction temperature Transfer function of pulse-width modulator Open-loop control-to-output transfer function Open-loop duty cycle-to-inductor current transfer function Open-loop control-to-output transfer function at f = 0 Total harmonic distortion Fall time Rise time Reverse recovery time Built-in potential DC component of control voltage Amplitude of small-signal component of control voltage Peak-to-peak ripple voltage of the filter capacitance DC component of error voltage Gate-to-source threshold voltage Breakdown voltage xxvii xxviii Nomenclature VBR VDM VDS VDSS VF VGD VGSpp VI VO VR Vr Vrcpp VSM VT VTm vC vc v∗c (t) v∗c (j𝜔) vDS vE vF ve vd vf vL vi vo vsat vr vrc vth vsat W WC WL Zi Zicl Zo Zocl 𝛽 ΔiL 𝜂 𝜃 𝜇 𝜇p 𝜇n 𝜉 𝜌 Reverse blocking (breakdown) voltage Reverse peak voltage of diode Drain–source dc voltage of MOSFET Drain–source breakdown voltage of MOSFETs Diode offset voltage, dc component of feedback voltage Gate-to-drain voltage of MOSFET Peak-to-peak gate-to-source voltage DC component of input voltage of converter DC output voltage of converter DC reference voltage Peak-to-peak value of output ripple voltage Peak-to-peak ripple voltage across ESR Peak switch voltage Thermal voltage Peak ramp voltage of pulse-width modulator Total control voltage AC component of control voltage Sampled AC component of control voltage Spectrum of sampled AC component of control voltage Drain–source voltage of MOSFET Total error voltage Total feedback voltage AC component of error voltage Average drift velocity AC component of feedback voltage Voltage across inductance L AC component of converter input voltage AC component of converter output voltage Saturation velocity of carriers AC component of reference voltage Voltage across ESR of filter capacitor Thermal velocity of electron Saturated average drift velocity Channel width Energy stored in capacitor Energy stored in inductor Open-loop input impedance of converter Closed-loop input impedance of converter Open-loop output impedance of converter Closed-loop output impedance of converter Transfer function of feedback network Peak-to-peak of inductor ripple current Efficiency of converter Thermal resistance Carrier mobility Mobility of holes Mobility of electrons Damping ratio Resistivity Nomenclature 𝜎 𝜏 𝜏n 𝜏p 𝜙 𝜓 𝜔 𝜔c 𝜔d 𝜔0 𝜔p 𝜔z Conductivity, Damping factor Minority carrier lifetime, Time constant Electron lifetime Hole lifetime Phase of transfer function, Magnetic flux Initial phase Angular frequency Unity-gain angular crossover frequency Damped angular resonant frequency Corner angular frequency Angular frequency of simple pole Angular frequency of simple zero xxix 1 Introduction 1.1 Classification of Power Supplies Power supply technology is an enabling technology that allows us to build and operate electronic circuits and systems [1–28]. All active electronic circuits, both digital and analog, require power supplies. Many electronic systems require several dc supply voltages. Power supplies are widely used in computers, telecommunications, instrumentation equipment, aerospace, medical, and defense electronics. A dc supply voltage is usually derived from a battery or an ac utility line using a transformer, rectifier, and a filter. The resultant raw dc voltage is not constant enough and contains a high ac ripple that is not appropriate for most applications. Voltage regulators are used to make the dc voltage more constant and to attenuate the ac ripple. A power supply is a constant voltage source with a maximum current capability. There are two general classes of power supplies: regulated and unregulated. The output voltage of a regulated power supply is automatically maintained within a narrow range, e.g., 1 or 2% of the desired nominal value, in spite of line voltage, load current, and temperature variations. Regulated dc power supplies are called dc voltage regulators. There are also dc current regulators, such as battery chargers. Figure 1.1 shows a classification of regulated power supply technologies. Two of the most popular categories of voltage regulators are linear regulators and switching-mode power supplies (SMPS). There are two basic linear regulator topologies: the series voltage regulator and the shunt voltage regulator. The switching-mode voltage regulators are divided into three categories: pulse-width modulated (PWM) dc–dc converters, resonant dc–dc converters, and switched-capacitor (also called charge-pump) voltage regulators. In linear voltage regulators, transistors are operated in the active region as dependent current sources with relatively high voltage drops at high currents, dissipating a large amount of power and resulting in low efficiency. Linear regulators are heavy and large, but they exhibit low noise level and are suitable for audio applications. In switching-mode converters, transistors are operated as switches, which inherently dissipate much less power than transistors operated as dependent current sources. The voltage drop across the transistors is very low when they conduct high current and the transistors conduct a nearly zero current when the voltage drop across them is high. Therefore, the conduction losses are low and the efficiency of switching-mode converters is high, usually above 80% or 90%. However, switching losses reduce the efficiency at high frequencies. Switching losses increase proportionally to switching frequency. Linear and switched-capacitor regulator circuits (except for large capacitors) can be fully integrated and are used in low-power and low-voltage applications, usually below several watts and Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 2 Pulse-Width Modulated DC–DC Power Converters Power supplies Switching regulators Linear regulators Series regulator Shunt regulator Figure 1.1 Switchedcapacitor regulators Resonant regulators PWM regulators Classification of power supply technologies. 50 V. PWM and resonant regulators are used at high power and voltage levels. They are small in size, light in weight, and have high conversion efficiency. Figure 1.2 shows block diagrams of two typical ac–dc power supplies that convert the widely available ac power to dc power. The power supply of Figure 1.2(a) contains a dc linear voltage regulator, whereas the power supply of Figure 1.2(b) contains a switching-mode voltage regulator. The power supply shown in Figure 1.2(a) consists of a low-frequency step-down power line transformer, a front-end rectifier, a low-pass filter, a linear voltage regulator, and a load. The nominal voltage of the ac utility power line is 110 Vrms in the United States and 230 Vrms in Europe. However, the actual line voltage varies within a range of about ±20% of the nominal voltage. The frequency of the ac line voltage is very low (50 Hz in Europe, 60 Hz in United States, 400 Hz in aircraft applications, and 20 kHz in space applications). The line transformer provides dc isolation from the ac power line and reduces a relatively high line voltage to a lower voltage (ranging usually from 5 to 28 Vrms ). Since the frequency of the ac line voltage is very low, the line transformer is heavy and bulky. The output voltage of the front-end rectifier/filter is unregulated and it varies because the peak voltage of the ac line varies. Therefore, a voltage regulator is required between the rectifier/filter and the load. There still exists a need for universal power supplies that can accept any utility line voltage in the world, ranging from 85 to 264 Vrms . The power supply shown in Figure 1.2(b) consists of a front-end rectifier, a low-pass filter, an isolated dc–dc switching-mode voltage regulator, and a load. It is run directly from the ac line. The ac voltage is rectified directly Unregulated AC Lowfrequency transformer Rectifier Regulated Linear voltage regulator Filter DC Load (a) Unregulated AC Rectifier Filter DC Isolated switching regulator Regulated DC Load (b) Figure 1.2 regulator. Block diagrams of ac–dc power supplies. (a) With a linear regulator. (b) With a switching-mode voltage Introduction 3 from the ac power line, which does not require a bulky low-frequency line transformer. Hence, such a circuit is called an off-line power supply (plug into the wall). The switching-mode voltage regulator contains a high-frequency transformer to obtain dc isolation for the entire power supply. Since the switching frequency is much higher than that of the ac line frequency, the size and weight of a high-frequency transformer as well as inductors and capacitors is reduced. The switching frequency usually ranges from 25 to 500 kHz. To avoid audio noise, the switching frequency should be above 20 kHz. A PWM switching-mode voltage regulator generates a high-frequency rectangular voltage wave, which is rectified and filtered. The duty cycle (or the pulse width) of the rectangular wave is varied to control the dc output voltage. Therefore, these voltage regulators are called PWM dc–dc converters. Power converters are required to convert one form of electric energy to another. A dc–dc converter is a power supply that converts a dc input voltage into a desired regulated dc output voltage. The dc input may be an unregulated or regulated voltage. Often, the input of a dc–dc converter is a battery or a rectified ac line voltage. A voltage regulator should provide a constant voltage to the load, even if line voltage, load current, and temperature vary. Unlike in linear voltage regulators, the output voltage in PWM dc–dc converters may be either lower or higher than the input voltage and are called either step-down or step-up converters. In a step-down converter, the output voltage is lower than the input voltage. In a step-up converter, the output voltage is higher than the input voltage. Some converters may act as both step-down and step-up converters. The output voltage source may be of the same polarity (noninverting) or opposite polarity (inverting) to that of the polarity of the input voltage. The dc–dc converters may have common negative or common positive input and output terminals. Converters may have a single output or multiple outputs. In addition, there are fixed or adjustable output voltage power supplies. Fixed output voltage supplies (e.g., 1.8 V) are used for power electronic circuits that require a specific supply voltage. Power supplies with adjustable output voltage (e.g., from 0 to 30 V) are convenient for laboratory tests. In some applications, programmable power supplies with digitally selected output voltages are required. Power supplies may be nonisolated or isolated. Transformers can be used to obtain dc isolation between the input and output and between the different outputs. Common requirements of most power supplies are: high efficiency, high power density, high reliability, and low cost. 1.2 Basic Functions of Voltage Regulators The simplest voltage regulator is a Zener diode regulator, shown in Figure 1.3. It is a shunt regulator. However, the performance of the Zener diode regulator is not satisfactory for most applications. Therefore, negative feedback techniques are usually used in voltage regulators to improve the performance. A block diagram of a voltage regulator with negative feedback is shown in Figure 1.4. It consists of a power stage (a dc–dc converter), a feedback network, a reference voltage Vref , and a control circuit (also called an error amplifier). The feedback network monitors the output voltage and reduces the error signal. The control circuit compares the feedback voltage with the reference voltage, generates an error voltage, amplifies it, and adjusts the transistor base current to keep the output voltage VO constant. The load current IO may vary over a very wide range: IOmin ≤ IO ≤ IOmax . Consequently, the load resistance RL = VO ∕IO also varies over a wide range: RLmin ≤ RL ≤ RLmax , where RLmin = VO ∕IOmax and RLmax = VO ∕IOmin . Most regulated power supplies have a short-circuit or current-overload protection circuit, which limits the output II + VI Figure 1.3 IO RS IZ RL + VO Zener diode voltage regulator. 4 Pulse-Width Modulated DC–DC Power Converters II IO + VI DC–DC converter RL + VO R1 β Control circuit R2 Vref Figure 1.4 Block diagram of a voltage regulator with negative feedback. current to a safe level to protect the power supply and/or the load. The input voltage of a voltage regulator is usually unregulated and can vary over a wide range: VImin ≤ VI ≤ VImax . For example, the dc input voltage in telecommunication power supplies is 36 ≤ VI ≤ 72 V with a nominal input voltage VInom = 48 V. The input voltage source may be a battery, a rectified single-phase or three-phase ac line voltage. The output voltage of a battery decreases when the battery is discharged. The peak voltage of a utility line varies as much as 10% or 20%, causing the rectified dc voltage to vary. The operating temperature of semiconductor and passive devices may also change from Tmin to Tmax , affecting the performance of power supplies. The basic functions of a dc–dc converter are as follows: (1) to provide conversion of a dc input voltage VI to the desired dc output voltage within a tolerance range, for example, VO = 1.2 V±1%; (2) to regulate the output voltage VO against variations in the input voltage VI , the load current IO (or the load resistance RL ), and the temperature; (3) to reduce the output ripple voltage below the specified level; (4) to ensure fast response to rapid changes in the input voltage and load current (or load resistance); (5) to provide dc isolation; (6) to provide multiple outputs; (7) to minimize the electromagnetic interference (EMI) below levels specified by EMI standards. 1.3 Power Relationships in DC–DC Converters The input current iI of many switching-mode dc–dc converters is pulsating. The dc component of the converter input current is given by T II = 1 i dt. T ∫0 I (1.1) Hence, the dc input power of a dc–dc converter is T PI = T 1 1 V i dt = VI i dt = VI II . T ∫0 I I T ∫0 I (1.2) The ac components of the output voltage and current are assumed to be very small and can be neglected. Therefore, dc output power of a dc–dc converter is PO = VO IO (1.3) PLS = PI − PO . (1.4) and the power loss in the converter is Introduction 5 The efficiency of the dc–dc converter is 𝜂= PO PO 1 = = P PI PO + PLS 1 + LS (1.5) PO from which PLS = PO ( ) 1 −1 . 𝜂 (1.6) The normalized power loss PLS ∕PO decreases as the converter efficiency increases. For example, for 𝜂 = 25%, PLS ∕PO = 300%, but for 𝜂 = 95%, PLS ∕PO = 5.26%. 1.4 DC Transfer Functions of DC–DC Converters The dc voltage transfer function (also called the dc voltage conversion ratio or the dc voltage gain) of a dc–dc converter is MVDC = VO VI (1.7) IO . II (1.8) and the dc current transfer function of a dc–dc converter is MIDC = Hence, the efficiency of a dc–dc converter is 𝜂= PO I V = O O = MIDC MVDC . PI II VI (1.9) From (1.7), (1.8), and (1.9), VO = MVDC VI (1.10) IO M = VDC IO . MIDC 𝜂 (1.11) and II = These equations can be represented by the dc circuit model of a dc–dc converter shown in Figure 1.5. II IO IO MIDC VI = MVDC η IO Figure 1.5 + MVDCVI A dc model of a dc–dc converter. RL + VO 6 Pulse-Width Modulated DC–DC Power Converters IO = Const TA = Const VO VOnom Actual Ideal ΔVO ΔVI 0 Figure 1.6 VImin VInom VImax VI Output voltage Vo versus input voltage VI for voltage regulators illustrating line regulation. 1.5 Static Characteristics of DC Voltage Regulators The quality of a power supply can be described by three parameters: line regulation, load regulation, and thermal regulation. The output voltage VO of most voltage regulators increases as the input voltage VI increases, as shown in Figure 1.6. Therefore, one figure-of-merit of voltage regulators for steady-state operation is line regulation, which is a measure of the regulator’s ability to maintain the predescribed nominal output voltage VOnom under slowly varying input voltage conditions. The line regulation is the ratio of the output voltage change ΔVO to a corresponding change in the input voltage ( ) ) ( ΔVO || mV LNR = (1.12) | ΔVI ||I =Const and T =Const V O A where TA is the ambient temperature. For example, for a linear voltage regulator LM140, ΔVO = 10 mV at IO = 0.5 A, TA = 25◦ C, and 7.5 V≤ VI ≤ 20 V. Hence, LNR = 10∕(20 − 7.5) = 0.8 mV/V. The percentage line regulation (PLNR) is defined as the ratio of the percentage change in the output voltage to a corresponding change in the input voltage ΔVO × 100% | VOnom | ( ) % (1.13) | | ΔVI |IO =Const and TA =Const V where TA is the ambient temperature. Ideally, the line regulation should be zero, in which case the output voltage is independent of the input voltage. In practice, the line regulation (LNR) should be less than 0.1%. For example, for a linear voltage regulator LM317, the typical value of the line regulation is PLNR = 0.01%∕V at IO = 20 mA, TA = 25◦ C, and 3 V ≤ (VI − VO ) ≤ 40 V. The output voltage VO of voltage regulators decreases as the load current IO increases due to a varying load resistance, as shown in Figure 1.7. Hence, the second figure-of-merit of voltage regulators for steady-state operation is load regulation, which is a measure of the regulator’s ability to maintain a constant output voltage VOnom under slowly varying load conditions over a certain range of load current, usually from zero load current to a maximum load current IOmax . The load regulation is given by ) ( ΔVO || mV LOR = | ΔIO ||V =Const and T =Const A I A ( ) | V − VOmin | mV = Omax . (1.14) | IOmax − IOmin ||V =Const and T =Const A I A The load regulation LOR should be less than 1%. PLNR = Introduction 7 VI = Const T A = Const VO Ideal VO(NL) VO(minL) Actual VO(FL) 0 Figure 1.7 IOmin IOmax IO Output voltage VO versus output current IO for voltage regulators illustrating load regulation. The percentage load regulation for voltage regulators that have no minimum load requirement is defined as PLOR = VO(NL) − VO(FL) VO(FL) | | × 100%| (%) | |VI =Const and TA =Const (1.15) where VO(NL) is the no-load (open-circuit) output voltage and VO(FL) is the full-load output voltage, which corresponds to a maximum load current IOmax . In some voltage regulators, such as PWM converters operated in the continuous conduction mode, the minimum load current IOmin is not zero. The output voltage at the minimum load current is VO(minL) . In this case, the load regulation is defined as PLOR = | | × 100%| (%). | |VI =Const and TA =Const VO(minL) − VO(FL) VO(FL) (1.16) For an ideal voltage regulator, the load regulation is zero. For example, for a linear voltage regulator LM117, PLOR2 = 0.3% for 5 mA≤ IO ≤ 100 mA and TA = 25◦ C. The line regulation and the load regulation can be combined into a line/load regulation LLR = ΔVO × 100% | VOnom | ΔIO ( ) % . | | |VI =Const and TA =Const A (1.17) Sometimes power supply manufacturers specify the equivalent dc output resistance Ro . A dc model of a real voltage source consists of an ideal voltage source V and an output resistance Ro , as shown in Figure 1.8. The output voltage is given by VO = V − Ro IO (1.18) ΔVO = −Ro ΔIO . (1.19) from which IO Ro V Figure 1.8 + VO RL DC model of voltage source with an output resistance. 8 Pulse-Width Modulated DC–DC Power Converters Hence, the incremental or dynamic output resistance is defined as the ratio of change in the output voltage to the corresponding change in the load current Ro = − − VOmax ΔVO V = − Omin = −LOR(Ω). ΔIO IOmax − IOmin (1.20) When IOmin = 0, the dc output resistance is given by Ro = VO(NL) − VO(FL) IOmax . (1.21) The output resistance of a voltage regulator should be as low as possible so that a change in the output current ΔIO will result only in a small change in the output voltage ΔVO = −Ro ΔIO . Ideally, Ro should be zero, resulting in the output voltage that is independent of the load current. At high frequencies (or for fast changes in the load current), the output resistance has a complex output impedance. From Figure 1.8, the output voltage at the full load resistance RFL = RLmin is VO(FL) = VO(NL) RFL . Ro + RFL (1.22) Hence, the percentage load regulation when the voltage regulator operates from full load to no-load can be expressed as ( ) R +R VO(FL) oR FL − VO(FL) VO(NL) − VO(FL) R FL PLOR = × 100% = × 100% = o × 100%. (1.23) VO(FL) VO(FL) RFL A very low output resistance can be obtained by using negative feedback with shunt connection of the power stage and the feedback network at the output. The relationship between the open-loop output resistance Ro and the closed-loop output resistance Rof is Rof = Ro 1 + 𝛽A (1.24) where A is the dc (or low-frequency) voltage gain of the forward path and 𝛽 is the transfer function of the feedback network. A third figure-of-merit of voltage regulators is the thermal regulation defined as THR = ΔVO × 100% | VOnom | ΔPD ( ) % | | W |IO =Const and VI =Const (1.25) where ΔPD is the change in power dissipation. For example, for a linear voltage regulator LM317, THR = 0.04%∕W. The static or dc input resistance of a dc voltage regulator at a given operating point Q is Rin(DC) = VI . II (1.26) Since PO = VO2 RL (1.27) and PI = VI2 Rin(DC) (1.28) Introduction 9 the converter efficiency can be expressed as P 𝜂= O = PI ( VO2 RL VI2 = VO VI )2 Rin(DC) RL 2 = MVDC Rin(DC) RL . (1.29) Rin(DC) Hence, one obtains the dc input resistance of dc voltage regulators as a function of load resistance RL and the dc–dc voltage transfer function Rin(DC) = 𝜂RL 2 MVDC . (1.30) 1.6 Dynamic Characteristics of DC Voltage Regulators Voltage regulators should minimize the amount of ripple voltage at the output. The parameter that describes this feature is called the ripple rejection ratio defined as RRR = Vri Vr (1.31) where Vr is the output ripple resulting from an input ripple Vri . For example, for a linear voltage regulator LM317, RRR = 80 dB = 104 at f = 120 Hz. If the input ripple Vri = 1 V, then the output ripple is Vr = Vri ∕RRR = 1∕104 = 0.1 mV. Dynamic transient performance of voltage regulators is described by line transient response and load transient response. In general, transient response is the shape of a signal as it moves between two steady-state points. Figure 1.9 shows a circuit for testing line transient response of voltage regulators. A test is made at a fixed load current IO , usually 50% of its rated full-load current IOmax . The input voltage vI contains step changes of magnitude ΔvI superimposed on its dc component VI , as shown in Figure 1.10(a). As a result, the output voltage vO contains transients just after the step changes in the input voltage, as shown in Figure 1.10(b). When the input voltage vI abruptly increases, the output voltage vO also increases initially and then returns to a steady-state value. On the other hand, when the input voltage vI abruptly decreases, the output voltage also decreases initially and then returns to a steady-state value. The abrupt change in the input voltage may cause an oscillatory (or underdamped) response characterized by overshoot and undershoot through the limits of a static regulation band. The response may be overdamped or critically damped. A closed-loop step response should be nonoscillatory. An oscillatory step response of a closed-loop circuit indicates that the margins of stability are too low or the circuit is unstable. The settling time ts and the transient component Vpk should be below the specified levels. Figure 1.11 shows a circuit for testing a transient response to a sudden electrical load changes. The input voltage VI is held constant, usually at the nominal value VInom . Step changes in the load current are obtained using an active load that acts like a current sink. Its waveform is a square wave with a dc offset, as shown in Figure 1.12(a). The step changes in the load current cause a transient response in the converter output voltage. When the load vI Figure 1.9 vi VI Voltage regulator IO = IOmax 2 RL + VO Circuit for testing the line transient response of voltage regulators. 10 Pulse-Width Modulated DC–DC Power Converters vI Δ vI VI 0 t (a) vO Vpk ts ts VOmax Vpk 0 VOmin VOnom t (b) Figure 1.10 Waveforms illustrating line transient response of voltage regulators. (a) Waveform of the input voltage vI . (b) Waveform of the output voltage vO . current is abruptly decreased, the output voltage initially increases and then returns to its steady-state value. The two parameters of output voltage are the peak transient voltage Vpk and the settling time ts . The settling time ts should be less than 200–500 ms and Vpk should be below a specified value. Usually, nonoscillatory response is expected in closed-loop power supplies to ensure sufficient stability margins. Another circuit for testing the load transient response is shown in Figure 1.13. The input voltage VI is held constant, usually at the nominal value VInom . A step change in the load current may be obtained by switching the load resistance RL . A resistor R1 is connected in parallel with a series combination of a resistor R2 and a fast switch, for example, a power metal-oxide-semiconductor-field-effect transistor (MOSFET). If the switch is off, the load resistance is high, equal to RL1 = R1 , and the steady-state load current is low, equal to IO1 = VO ∕RL1 . If the switch is on, the load resistance is low, equal to RL2 = R1 R2 ∕(R1 + R2 ), and the steady-state load current is high, equal to IO2 = VO ∕RL2 . Therefore, when the load resistance is switched from RL1 to RL2 and vice versa, the load current iO experiences step changes in magnitude ΔIO superimposed on the dc load current IO , for example, from 0.1IOmax to 0.9IOmax . This causes the output voltage to change just after the step change in the load current, as shown in Figure 1.12(b). When the load current iO abruptly increases, the output voltage vO initially decreases and then returns to a steady-state value and vice versa. In general, the response may be underdamped (or oscillatory), critically damped, or overdamped, but a nonoscillatory response is normally required. iO + VI Figure 1.11 DC–DC converter + VO Circuit for testing the transient response to a sudden electrical load change using an active current sink. Introduction 11 iO IOmax Δ IO 0 t (a) vO Vpk ts ts VOmax Vpk 0 VOmin VOnom t (b) Figure 1.12 Waveforms illustrating load transient response of voltage regulators. (a) Waveform of the load current iO . (b) Waveform of the output voltage vO . Many voltage regulators are operated with a constant load resistance RL (or a constant load current IO ) for relatively long time intervals. In addition, these regulators have a negative feedback controller, which maintains a constant output voltage VO . Therefore, the dc output power PO = VO2 ∕RL is also constant. Such operating conditions are called constant power load. If the output power PO and the efficiency 𝜂 are constant, the input power PI = PO ∕𝜂 = VI II is also constant. The dc input voltage of a dc voltage regulator can be expressed by VI = P PI = O. II 𝜂II (1.32) Figure 1.14 shows a plot of the input voltage VI as a function of the dc input current II at a constant output power PO . If the input voltage VI is increased, the input current II = PI ∕VI decreases under constant power load conditions. Therefore, the slope of the II –VI characteristic is negative at any operating point Q. The dynamic input resistance (also called the ac or incremental input resistance) of the voltage regulator with a constant input power PI for slow changes of the input voltage and current at a given operating point Q (i.e., for low frequencies) is given by ( ) PI P d(VI ) V d = − 2I = − I = −Rin(DC) . Ri = = (1.33) dII dII II II II iO + VI = VInom Figure 1.13 MOSFET. Voltage regulator + vO R1 R2 + vGS Circuit for testing the load transient response with a switched load resistance from R1 to R1 ||R2 using a 12 Pulse-Width Modulated DC–DC Power Converters VI Rin(DC) Q Ri Δ VI Δ I I II Figure 1.14 Voltage–current characteristic of a constant power source. Note that for a constant input power, the dynamic input resistance is just the negative of the static input resistance. The dynamic input resistance of a voltage regulator with a constant output power PO and a constant efficiency 𝜂 is Ri = d(VI ) d = dII dII ( PO 𝜂II ) = PO d 𝜂 dII ( ) RL I 2 P 1 = − O2 = − 2O . II 𝜂II 𝜂II (1.34) From (1.9), one obtains IO V 𝜂 𝜂 =𝜂 I = V = . O II VO MVDC (1.35) VI Substitution of (1.35) into (1.34) produces Ri = − 𝜂RL 2 MVDC . (1.36) It can be seen that the dynamic input resistance of a dc voltage regulator with a constant power load is negative and directly proportional to the load resistance RL . The dynamic input resistance is a negative reflected load resistance. 1.7 Linear Voltage Regulators There are two basic topologies of linear voltage regulators: the series voltage regulator and the shunt voltage regulator. These topologies are shown in Figure 1.15. A band gap reference voltage source Vref is applied to the noninverting input of the op-amp. The input voltage of the op-amp is the difference between the noninverting input voltage V + and the inverting input voltage V − given by Vi(op−amp) = V + − V − . Since the input voltage of an op-amp with negative feedback is almost zero, the voltage across the resistor R2 is controlled by the reference voltage source Vref . Thus, VR2 = VO R2 ≈ Vref . R1 + R2 Rearrangement of this equation gives the output voltage for both linear voltage regulators ( ) R1 +1 . VO ≈ Vref R2 (1.37) (1.38) The range of the output current of linear voltage regulators is from 0 to a maximum value IOmax , usually determined by a current limiting circuit. Introduction II 13 lO + + R1 VI Vref RL + VO R2 (a) II IO RS IC + + VI R1 Vref RL + VO R2 (b) Figure 1.15 Basic circuits of linear voltage regulators. (a) Series voltage regulator. (b) Shunt voltage regulator. 1.7.1 Series Voltage Regulator The series voltage regulator is shown in Figure 1.15(a). It employs a pass transistor whose collector-to-emitter voltage VCE is controlled to compensate for varying the input voltage. Referring to Figure 1.15(a), VI = VCE + VO . (1.39) ΔVI = ΔVCE . (1.40) Since VO is constant, Thus, a change in the input voltage will result in the same change in the voltage drop across the pass transistor. The pass transistor behaves like a variable resistor Rv . The series voltage regulator can be represented as a voltage divider composed of the variable resistor Rv and the load resistor RL . When the output voltage VO decreases, the variable resistance also decreases, causing the output voltage across the load resistance to increase, and vice versa. The voltage drop across Rv can be expressed as VCE = VI − VO = Rv IO . (1.41) At a fixed load current IO , a change in the input voltage is given by ΔVCE = ΔVI = ΔRv IO . When the input voltage is changed by ΔVI , the resistance is changed by ΔRv = ΔVI ∕IO . (1.42) 14 Pulse-Width Modulated DC–DC Power Converters II IO VDS + + + VI R1 R L Vref Figure 1.16 + VO R2 Typical low drop-out (LDO) voltage regulator topology. The efficiency of a series voltage regulator can be derived by observing that IO ≈ II 𝜂= PO I V V = O O ≈ O = MVDC . PI II VI VI (1.43) It can be seen that the efficiency of a series voltage regulator is equal to the dc voltage transfer function MVDC . If the input voltage VI is much higher than the output voltage VO , the efficiency is very low. For example, if VI = 20 V and VO = 5 V, then 𝜂 = 5∕20 = 25%. This is a very low efficiency. However, if VI = 8 V and VO = 5 V, then 𝜂 = 5∕8 = 62.5%. The power loss in the pass transistor is expressed by PLS ≈ IO (VI − VO ). (1.44) Thus, the power loss increases with increasing load current IO and the voltage drop across the pass transistor ΔV = VI − VO . The series voltage regulator will work properly as long as VI does not drop too low, which causes the op-amp to saturate. The op-amp must be in the linear region to function properly as a control circuit. The minimum voltage difference between the unregulated input voltage and the regulated output voltage VDO = VImin − VO at which the circuit ceases to regulate against further reduction in the input voltage is called the drop-out voltage. For most series voltage regulators, this voltage is about 2 V, but in some voltage regulators VDO can be as low as 0.1 V. Voltage regulators with a low drop-out (LDO) voltage are called LDO regulators. In these regulators, a pnp or an NMOS transistor is used as a pass component, as shown in Figure 1.16. The series voltage regulator is quiet because its transistor always operates in the pinch-off region as a dependent current source and does not generate a lot of noise like that in switching-mode power supplies. In addition, a series voltage regulator is simple to design and build. 1.7.2 Shunt Voltage Regulator The shunt voltage regulator is shown in Figure 1.15(b). It employs a shunt transistor, in which the current is controlled to compensate for the change in the input voltage or the load current. The output voltage is held constant by varying the collector current IC of the shunt transistor. The shunt transistor acts like a variable resistor. When the output voltage VO decreases, the op-amp output voltage also decreases, the shunt transistor conducts less heavily, and the variable resistance increases. Thus, less current is diverted from the load, causing an increase in the load current and the output voltage. Using Kirchhoff’s current law (KCL), II = IC + IO . (1.45) When the load current IO is changed at a fixed input voltage VI , the input current II = (VI − VO )∕Rs is constant and therefore ΔIC = −ΔIO . (1.46) Introduction 15 Equation (1.45) can be rewritten as VI − VO = IC + IO . Rs (1.47) When the input voltage changes at a fixed load current IO , ΔVI = ΔIC , Rs (1.48) ΔVI = Rs ΔIC = ΔVRs . (1.49) from which Thus, the output voltage VO is held constant by varying the voltage drop across the series resistor Rs , which in turn is controlled by varying the collector current IC of the shunt transistor. The shunt regulator is inherently short-circuit proof. The output current under short-circuit conditions is given by IO(sc) = VI . Rs (1.50) The power loss in resistor Rs is PRs = (VI − VO )II = (VI − VO )(IO + IC ). (1.51) The power loss in the shunt transistor is PQ = VO IC = VO (II − IO ) (1.52) IO PO V I V = OO = O . PI VI II VI IO + IC (1.53) and the efficiency is defined as 𝜂= Thus, the shunt voltage regulator is less efficient than the series voltage regulator due to the power loss in both series resistor Rs and shunt transistor. However, the line transient response of the shunt regulator is better than that of the series regulator. The shunt voltage regulator must be protected against input overvoltage conditions. The major characteristics of IC linear voltage regulators are as follows: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Simple circuit Very small size and low weight Cost effective Low noise level Wide bandwidth and fast step response to load and line changes Low input and output voltages, usually below 40 V Low output current, usually below 3 A Low output power, usually below 25 W Low efficiency (especially for VI ≫ VO ), usually between 20% and 60% Only step-down linear voltage regulators are possible Only noninverting linear voltage regulators are possible Large low-frequency (50 or 60 Hz) transformers are required in AC–DC power supplies with linear voltage regulators. 16 Pulse-Width Modulated DC–DC Power Converters 1.8 Topologies of PWM DC–DC Converters Switched-mode technology employs a wide variety of topologies. Figure 1.17 shows a family of single-ended PWM dc–dc converters, such as buck, boost, buck–boost, flyback, forward, Ćuk (boost–buck), SEPIC (singleended primary input converter), and dual-SEPIC [7] (also called zeta or inverse-SEPIC) converters. The SEPIC converter is noninverting step-down/step-up converter. Its voltage ratio is MVDC = VO ∕VI = D∕(1 − D). The flyback converter is a transformer version of the buck–boost converter, and the forward converter is a transformer version of the buck converter. The flyback and dual-SEPIC converters are identical on the primary side of the transformer. Also, the Ćuk and SEPIC converters are identical on the primary side of the transformer. The flyback and SEPIC converters are identical on the secondary side of the transformer. Also, the Ćuk and dual-SEPIC converters are identical on the secondary side of the transformer. Figure 1.18 depicts the multiple-switch PWM dc–dc converters: half-bridge, full-bridge, and push–pull converters. Switched-mode converters use duty-cycle control of a switching element to block the flow of energy from Buck Boost L + + L C C Buck/Boost Flyback + L C C + Forward L L + L ′ Cuk + C C C C L L C L C + L C + SEPIC C C + L L Dual SEPIC (Zeta) C + L C L C L + L Figure 1.17 C + C Single-ended PWM dc–;dc nonisolated and isolated converters. Introduction 17 Half-Bridge converter VI VI 2 VI 2 S1 Cb n:1:1 D1 L S2 Cb C 0 RL + VO D2 (a) Full-Bridge converter S1 n:1:1 S4 D1 L C + RL VO RL VO VI S2 S3 D2 (b) Push-Pull converter S1 n:1 D1 C VI S2 L n:1 + D2 (c) Figure 1.18 Multiple-switch isolated PWM dc–dc converters. the input to the output and thus achieve voltage regulation. The advantages of these converters include significant reduction of a transformer and energy storage components. Since switched-mode converters can operate at high frequencies, a small transformer with a ferrite core can be used. The reduced size is very important in many applications, such as aerospace, computers, and wireless technologies. However, there is a penalty paid due to the increased noise, which is present at both input and output of the supply due to the switching action of semiconductor devices. In addition, the control circuit is much more complicated than that used in linear regulators. 18 Pulse-Width Modulated DC–DC Power Converters Power MOSFETs are often used as controllable switches. In 1979, International Rectifier patented the first commercially viable power MOSFET, called the HEXFET. Fast recovery diodes, ultrafast recovery [28], and hyperfast recovery pn junction diodes, or Schottky diodes are used in switching dc–dc power converters. In 1976, Silicon General introduced the industry’s first PWM controller IC, the SG1524. 1.9 Relationships Among Current, Voltage, Energy, and Power The average value of current i(t) is given by T IAV = and the rms value of the current is 1 1 i(t)dt = T ∫0 2𝜋 ∫0 √ i(𝜔t)d(𝜔t) √ T 1 i2 (t)dt = T ∫0 Irms = 2𝜋 1 2𝜋 ∫0 (1.54) 2𝜋 i2 (𝜔t)d(𝜔t). (1.55) Likewise, the average value of voltage v(t) is expressed by T VAV = 1 1 v(t)dt = T ∫0 2𝜋 ∫0 2𝜋 v(𝜔t)d(𝜔t) and the rms value of the voltage is given by √ √ T 2𝜋 1 1 v2 (t)dt = v2 (𝜔t)d(𝜔t). Vrms = T ∫0 2𝜋 ∫0 (1.56) (1.57) The instantaneous power is p(t) = i(t)v(t). (1.58) The energy dissipated in a component or delivered by a source over a time interval t1 is t1 W= t1 p(t)dt = ∫0 ∫0 i(t)v(t)dt. (1.59) For periodic waveforms in steady state, the average real power absorbed by a component or delivered by a source is the time average value of the instantaneous power over a period T of the operating frequency T P= T 1 1 W = fW. p(t)dt = i(t)v(t)dt = T ∫0 T ∫0 T (1.60) For periodic waveforms in steady state, the average charge stored in a capacitor over one period is zero T Q= iC (t)dt = 0. ∫0 (1.61) This is called the principle of capacitor charge balance or capacitor ampere-second balance. Thus, the average current through a capacitor for steady-state operation is zero IC(AV) = T Q 1 = i (t)dt = 0. T T ∫0 C (1.62) For periodic waveforms in steady state, the average magnetic flux linkage of an inductor over one period is zero T 𝜆= ∫0 vL (t)dt = 0. (1.63) Introduction 19 This is called the principle of inductor flux linkage balance or inductor volt-second balance. Hence, the average voltage across an inductor in steady state is zero T VL(AV) = 1 𝜆 = v (t)dt = 0. T T ∫0 L (1.64) The instantaneous energy stored in a capacitor is wC (t) = 1 2 Cv (t) 2 C (1.65) wL (t) = 1 2 Li (t). 2 L (1.66) and in an inductor is 1.10 Summary r The main function of voltage regulators is the regulation of the dc output voltage against changes in the load current, the input voltage, and the temperature. r Additional functions of voltage regulators are the dc isolation, ripple voltage reduction, and fast transient response to rapid changes in the load current and the input voltage. r Voltage regulators can be categorized into linear voltage regulators, switching-mode dc–dc converters, and switched-capacitor voltage regulators. r Linear voltage regulators have simple circuit, low power levels, low noise (EMI), low output ripple voltage, excellent load and line regulation, wide bandwidth and fast transient response to load and line changes, but have low efficiency and are only step-down regulators. r There are series and shunt linear voltage regulators. r In linear voltage regulators, transistors are operated as dependent current sources. r In PWM dc–dc converters, transistors are operated as switches. Therefore, the voltage is low when the current is high, and the current is zero when the voltage is high, yielding low conduction loss and high efficiency. r PWM converters are sources of EMI because of the hard switching action of transistors and diodes. r Switching voltage regulators have high efficiency, high power density, and high power levels. They can be step-down or step-up converters and can have multiple-output voltages, but they have slow response to load and line changes, produce high level of EMI, and have high output ripple voltage. r Flyback converters are used at power levels in the range 0–50 W. Forward converters are used in the range 50–500 W. Half-bridge converters are used in the range 100–1000 W. Full-bridge converters are used for power level above 500 W. r Power converters are sources of EMI/RFI noise. r EMI noise can be conducted and radiated. The conducted noise is in the range from 9 kHz to 30 MHz. The radiated noise is in the range from 30 MHz to 1 GHz. r EMI noise can be differential-mode noise and common-mode noise. References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York, NY: Van Nostrand, 1981. [3] K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. [4] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [5] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. 20 Pulse-Width Modulated DC–DC Power Converters [6] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [7] J. Jóźwik and M. K. Kazimierczuk, “Dual SEPIC PWM switching-mode dc/dc converter,” IEEE Transactions on Industrial Electronics, vol. IE-36, pp. 64–70, February 1989. [8] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [9] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. [10] M. K. Kazimierczuk and D. Czarkowski, Resonant Power Converters, 2nd Ed. New York: John Wiley & Sons, 2011. [11] D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. [12] A. M. Trzynadlowski, Introduction to Modern Power Electronics. New York: John Wiley & Sons, 1998. [13] P. T. Krein, Elements to Power Electronics. New York: Oxford University Press, 1998. [14] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2nd Ed. Norwall, MA: Kluwer Academic Publisher, 2001. [15] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [16] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Upper Saddle River, NJ: Prentice Hall, 2004. [17] W. Shepherd and L. Zhang, Power Converter Circuits. New York: Marcel Dekker, 2004. [18] S. Ang and A. Oliva, Power-Switching Converters, 2nd Ed. Boca Raton, FL: CRC/Taylor & Francis, 2004. [19] A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. [20] I. Batarseh, Power Electronics Circuits. New York: John Wiley & Sons, 2004. [21] M. H. Rashid, Editor, Power Electronics Handbook. New York: Academic Press, 2006. [22] M. H. Rashid and H. M. Rashid, SPICE for Power Electronics and Electric Power, 2nd Ed. Boca Raton, FL: CRC/Taylor & Francis, 2006. [23] C. P. Basso, Switch-Mode Power Supply. New York: McGraw-Hill, 2008. [24] M. K. Kazimierczuk, RF Power Amplifiers. Chichester, UK: John Wiley & Sons, 2014. [25] M. K. Kazimierczuk, High-Frequency Magnetic Components, 2nd Ed. Chichester, UK: John Wiley & Sons, 2014. [26] S. Buso and P. Mattavelli, Digital Control in Power Electronics. Morgan & Claypool Publishers, 2006. [27] S. Maniktala, Switching Power Supply Design and Optimization. New York: McGraw-Hill, 2005. [28] M. K. Kazimierczuk, “Reverse recovery power pn junction diodes,” International Journal of Circuits, Systems, and Computers, vol. 5, no. 4, pp. 747–755, December 1995. Review Questions 1.1 List the main functions of dc–dc converters. 1.2 Give a classification of power supplies. 1.3 Define line regulation of voltage regulators. 1.4 Define load regulation of voltage regulators. 1.5 Define thermal regulation of voltage regulators. 1.6 Define the dc input resistance of voltage regulators. 1.7 Define the dynamic input resistance of voltage regulators. 1.8 Define the ripple rejection ratio of voltage regulators. 1.9 What is the line transient response of voltage regulators? 1.10 What is the load transient response of voltage regulators? 1.11 How are transistors operated in linear voltage regulators? 1.12 What are the basic topologies of linear voltage regulators? Introduction 21 1.13 Give the expression for the efficiency of the series voltage regulator. 1.14 What is the range of efficiency for linear voltage regulators? 1.15 What is the range of output power for linear voltage regulators? 1.16 Can you build a step-up linear voltage regulator? 1.17 What is the size and weight of a transformer in power supplies with linear voltage regulators? 1.18 What is the noise level in linear voltage regulators? 1.19 What are LDO voltage regulators? 1.20 How are transistors and diodes operated in switching-mode dc–dc power converters? 1.21 How is the dc isolation achieved in switching-mode power supplies? 1.22 Compare the efficiency of linear and PWM switching-mode voltage regulators. Problems 1.1 A voltage regulator experiences a 100 mV change in the output voltage, when its input voltage changes by 10 V at IO = 0.2 A and TA = 25◦ C. The nominal output voltage is VOnom = 3.3 V. Determine the line regulation and the percentage line regulation. 1.2 A voltage regulator is rated for an output current IO = 0–50 mA. Under the no-load condition, the output voltage is 5 V. Under the full-load condition, the output voltage 4.99 V. Find load regulation, the percentage load regulation, the dc output resistance, and load/line regulation. 1.3 A series linear voltage regulator is operated under the following conditions: VI = 6–15 V, VO = 3.3V, and IO = 0–0.4 A. Find the minimum and maximum efficiency of the voltage regulator at full load. 1.4 A voltage regulator has RL = 10 Ω, VI = 10 V, VO = 5 V, and 𝜂 = 90%. Find the dc input resistance. 1.5 A boost PWM converter operating in CCM is rated for an output current of 0.5–1 A. The output voltage at minimum load current is 20 V and at full load current is 19.95 V. Find the load regulation in (mV/A), the percentage load regulation in (%), and the dc output resistance (Ω). 2 Buck PWM DC–DC Converter 2.1 Introduction This chapter studies the PWM buck switching-mode converter, often referred to as a “chopper” [1–30]. Analysis is given for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Current and voltage waveforms for all the components of the converter are derived. The dc voltage function is derived for both the modes. Voltage and current stresses of the components are found. The boundary between CCM and DCM is determined. An expression for the output voltage ripple is derived. The power losses in all the components and the transistor gatedrive power are estimated. The overall efficiency of the converter is determined. Design examples are also given. 2.2 DC Analysis of PWM Buck Converter for CCM 2.2.1 Circuit Description In general, a basic PWM converter, such as buck, boost, and buck–boost converter, contains a single-pole, doublethrow switch, which controls the energy flow from the source to the load. A circuit of the PWM buck dc–dc converter is depicted in Figure 2.1(a). It consists of four components: a power MOSFET used as a controllable switch S, a rectifying diode D1 , an inductor L, a filter capacitor C. Resistor RL represents a dc load. Power MOSFETs are the most commonly used controllable switches in dc–dc converters because of their high speeds. In 1979, International Rectifier patented the first commercially viable power MOSFET, the HEXFET. Other power switches such as bipolar junction transistors (BJTs), isolated gate bipolar transistors (IGBTs), or MOS-controlled thyristors (MCTs) may also be used. The diode D1 is called a freewheeling diode, a flywheel diode, or a catch diode. The transistor and the diode form a single-pole, double-throw switch, which controls the energy flow from the source to the load. The task for the capacitor and the inductor is energy storage and transfer. The switching network, composed of the transistor and the diode, “chops” the dc input voltage VI , and therefore the converter is often called a “chopper,” which produces a reduced average voltage. The switch S is controlled by a pulse-width modulator and is turned on and off at the switching frequency fs = 1∕T. The duty cycle D is defined as ton t D = on = = fs ton T ton + toff Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 (2.1) Buck PWM DC–DC Converter L S vGS + VI 23 D1 C RL + VO RL + VO RL + VO (a) iS L iL + vL VI vD + C (b) L + vS VI iL + vL iD C (c) Figure 2.1 PWM buck converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. where ton is the time interval when the switch S is closed and toff is the time interval when the switch S is open. Since the duty cycle D of the drive voltage vGS is varied, so does the duty ratio of other waveforms. This permits the regulation of the dc output voltage against changes in the dc input voltage VI and the load resistance RL (or the √ load current IO ). The circuit L-C-RL acts like a second-order low-pass filter whose corner frequency is fo = 1∕(2𝜋 LC). The output voltage VO of the buck converter is always lower than the input voltage VI . Therefore, it is a step-down converter. The buck converter “bucks” the voltage to a lower level. Because the gate of the MOSFET is not referenced to ground, it is difficult to drive the transistor. The converter requires a floating gate drive. With the input current of the converter being discontinuous, a smoothing LC filter may be required at the input. The buck converter can operate in a CCM or in a DCM, depending on the waveform of the inductor current. In CCM, the inductor current flows for the entire cycle, whereas in DCM, the inductor current flows only for a part of the cycle. In DCM, it falls to zero, remains at zero for some time interval, and then starts to increase. Operation at the boundary between CCM and DCM is called the critical mode (CRM). Let us consider the buck converter operation in the CCM. Figures 2.1(b) and (c) shows the equivalent circuits of the buck converter for CCM when the switch S is on and the diode D1 is off, and when the switch is off and the diode is on, respectively. The principle of the converter operation is explained by the idealized current and voltage waveforms depicted in Figure 2.2. At time t = 0, the switch is turned on by the driver. Consequently, the voltage across the diode is vD = −VI , causing the diode to be reverse biased. The voltage across the inductor L is vL = VI − VO and therefore the inductor current increases linearly with a slope of (VI − VO )∕L. For CCM, iL (0) > 0. The inductor current iL flows through the switch, resulting in iS = iL when the switch is on. During this time interval, the energy is transferred from the dc input voltage source VI to the inductor, capacitor, and the load. At time t = DT, the switch is turned off by the driver. 24 Pulse-Width Modulated DC–DC Power Converters vGS 0 DT T t vL VI VO A+ 0 DT VO VI iL IO VI T t A VO VO L L Δ iL 0 T t DT T t DT T t DT iS ISM IO II 0 vS VSM VI 0 iD IDM IO ID 0 vD 0 DT T DT T t t VI Figure 2.2 Idealized current and voltage waveforms in the PWM buck converter for CCM. Buck PWM DC–DC Converter 25 The inductor has a nonzero current when the switch is turned off. Because the inductor current waveform is a continuous function of time, the inductor current continues to flow in the same direction after the switch turns off. Therefore, the inductor L acts as a current source, which forces the diode to turn on. The voltage across the switch is VI and the voltage across the inductor is −VO . Hence, the inductor current decreases linearly with a slope of −VO ∕L. During this time interval, the input source VI is disconnected from the circuit and does not deliver energy to the load and the LC circuit. The inductor L and capacitor C form an energy reservoir that maintains the load voltage and current when the switch is off. At time t = T, the switch is turned on again, the inductor current increases and hence energy increases. PWM converters are operated at hard switching because the switch voltage waveform is rectangular and the transistor is turned on at a high voltage. The power switch S and the diode D1 convert the dc input voltage VI into a square wave at the input of the L-C-RL circuit. In other words, the dc input voltage VI is chopped by the transistor–diode switching network. The L-C-RL circuit acts as a second-order low-pass filter and converts the square wave into a low-ripple dc output voltage. Since the average voltage across the inductor L is zero for steady state, the average output voltage VO is equal to the average voltage of the square wave. The width of the square wave is equal to the on-time of the switch S and can be controlled by varying the duty cycle D of the MOSFET gate-drive voltage. Thus, the square wave is a pulse-width modulated (PWM) voltage waveform. The average value of the PWM voltage waveform is VO = DVI , which depends on the duty cycle D and is almost independent of the load for CCM operation. Theoretically, the duty cycle D may be varied from 0% to 100%. This means that the output VO ranges from 0 to VI . Thus, the buck circuit is a step-down converter. In practice, the dc input voltage VI varies over a specified range while the output voltage VO should be held at a fixed value. If the dc voltage VI is increased, the duty cycle D is reduced so that the product DVI being the average value of the PWM voltage remains constant. On the other hand, if the input voltage VI is reduced, the duty cycle D is increased so that the average value of the PWM signal is constant. Therefore, the amount of energy delivered from the input voltage source VI to the load can be controlled by varying the switch on-duty cycle D. If the output voltage VO and the load resistance RL (or the load current IO ) are constant, the output power is also constant. When the input voltage VI increases, the switch on-time is reduced to transfer the same amount of energy. The practical range of D is usually from 5% to 95% due to resolution. The duty cycle D is controlled by a control circuit. The inductor current contains an ac component which is independent of the dc load current in CCM and a dc component which is equal to the dc load current IO . As the dc output current IO flows through the inductor L, only one-half of the B–H curve of the inductor ferrite core is exploited. Therefore, the inductor L should be designed such that the core will not saturate. To avoid core saturation, a core with an air gap and sufficiently large volume may be required. 2.2.2 Assumptions The analysis of the buck PWM converter of Figure 2.1(a) begins with the following assumptions: (1) The power MOSFET and the diode are ideal switches. (2) The transistor output capacitance, the diode capacitance, and the lead inductances are zero and thereby switching losses are neglected. (3) Passive components are linear, time invariant, and frequency independent. (4) The output impedance of the input voltage source VI is zero for both dc and ac components. (5) The converter operates in steady state. (6) The switching period T = 1∕fs is much shorter than the time constants of reactive components. (7) The dc output voltage VO is constant, but the dc input voltage VI and the load resistance RL are variable. 2.2.3 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch S is on and the diode D1 is off. An ideal equivalent circuit for this time interval is shown in Figure 2.1(b). When the switch is on, the voltage across the diode vD is approximately 26 Pulse-Width Modulated DC–DC Power Converters equal to −VI , causing the diode to be reverse biased. The voltage across the switch vS and the diode current are zero. The voltage across the inductor L is given by vL = V I − V O = L diL . dt (2.2) Hence, the current through the inductor L and the switch S is t iS = iL = t V − VO V − VO 1 t + iL (0) vL dt + iL (0) = I dt + iL (0) = I ∫ ∫ L 0 L L 0 (2.3) where iL (0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes (VI − VO )DT + iL (0) L and the peak-to-peak ripple current of the inductor L is iL (DT) = ΔiL = iL (DT) − iL (0) = (VI − VO )DT (V − VO )D VI D(1 − D) = I = . L fs L fs L (2.4) (2.5) The diode voltage is vD = −VI . (2.6) VDM = VI . (2.7) Thus, the peak value of the diode reverse voltage is The average value of the inductor current is equal to the dc output current IO . Hence, the peak value of the switch current is Δi ISM = IO + L . (2.8) 2 The instantaneous energy stored in the magnetic field in the inductor is [ ]2 1 1 V − VO wL (t) = Li2L = L I t + iL (0) . (2.9) 2 2 L The increase in the magnetic energy stored in the inductor L during the time interval 0 to DT is given by ] 1 [ ΔwL(in) = L i2L (DT) − i2L (0) . 2 The time interval 0 to DT is terminated when the switch is turned off by the gate driver. (2.10) 2.2.4 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch S is off and the diode D1 is on. Figure 2.1(c) shows an ideal equivalent circuit for this time interval. Since iL (DT) is nonzero at that instant, the switch turns off and the fact that the inductor current iL is a continuous function of time, the inductor acts as a current source and turns the diode on. The switch current iS and the diode voltage vD are zero and the voltage across the inductor L is diL . dt The current through the inductor L and the diode can be found as vL = −VO = L iD = iL = (2.11) t t t V V 1 1 vL dt + iL (DT) = (−VO )dt + iL (DT) = − O dt + iL (DT) = − O (t − DT) + iL (DT) L ∫DT L ∫DT L ∫DT L (2.12) Buck PWM DC–DC Converter 27 where iL (DT) is the initial condition of the inductor L at t = DT. The peak-to-peak ripple current of the inductor L is V T(1 − D) VO (1 − D) ΔiL = iL (DT) − iL (T) = O = . (2.13) L fs L Note that the peak-to-peak value of the inductor current ripple ΔiL is independent of the load current IO in CCM and depends only on the dc input voltage VI and thereby on the duty cycle D. For a fixed output voltage VO , the maximum value of the peak-to-peak inductor ripple current occurs at the maximum input voltage VImax , which corresponds to the minimum duty cycle Dmin . It is given by ΔiLmax = VO (1 − Dmin ) . fs L (2.14) The switch voltage vS and the peak switch voltage VSM are given by vS = VSM = VI . (2.15) The diode and switch peak currents are given by ΔiL . (2.16) 2 This time interval ends at t = T when the switch is turned on by the driver. The decrease in the magnetic energy stored in the inductor L during time interval DT < t ≤ T is given by ] 1 [ ΔWL(out) = L i2L (DT) − i2L (T) . (2.17) 2 For steady-state operation, the increase in the magnetic energy ΔWL(in) is equal to the decrease in the magnetic energy ΔWL(out) . The transient and steady-state waveforms in converters with commercial components can be obtained from computer simulations using SPICE model. IDM = ISM = IO + 2.2.5 Device Stresses for CCM The maximum voltage and current stresses of the switch and the diode in CCM for steady-state operation are VSMmax = VDMmax = VImax (2.18) and ISMmax = IDMmax = IOmax + (V V (1 − Dmin ) − VO )Dmin ΔiLmax = IOmax + Imax = IOmax + O . 2 2fs L 2fs L (2.19) 2.2.6 DC Voltage Transfer Function for CCM The voltage and current across a linear inductor are related by Faraday’s law in its differential form diL . dt For steady-state operation, the following boundary condition is satisfied vL = L (2.20) iL (0) = iL (T). (2.21) 1 v dt = diL L L (2.22) Rearranging (2.20), 28 Pulse-Width Modulated DC–DC Power Converters and integrating both sides yields T T 1 v dt = diL = iL (T) − iL (0) = 0. ∫0 L ∫0 L (2.23) The integral form of Faraday’s law for an inductor under steady-state conditions is T vL dt = 0. ∫0 (2.24) The average value of the voltage across an inductor for steady state is zero. Thus, T VL(AV) = 1 v dt = 0. T ∫0 L (2.25) This equation is also called a volt-second balance for an inductor, which means that “volt-second” stored is equal to “volt-second” released. The inductor average voltage for PWM converters operating in CCM is DT VL(AV) = T vL dt + ∫0 vL dt = 0 (2.26) vL dt. (2.27) ∫DT from which DT ∫0 T vL dt = − ∫DT This means that the area encircled by the positive part of the inductor voltage waveform A+ is equal to the area encircled by the negative part of the inductor voltage waveform A− , that is, [ DT ] T 1 VL(AV) = vL dt + vL dt = 0 (2.28) ∫DT T ∫0 where DT A+ = ∫0 vL dt (2.29) vL dt. (2.30) and T A− = − ∫DT Referring to Figure 2.2, (VI − VO )DT = VO (1 − D)T (2.31) VO = DVI . (2.32) which simplifies to the form For a lossless converter, VI II = VO IO . Hence, from (2.32), the dc voltage transfer function (or the voltage conversion ratio) of the lossless buck converter is given by MV DC ≡ VO I = I = D. VI IO (2.33) The range of MV DC is 0 ≤ MV DC ≤ 1. (2.34) Buck PWM DC–DC Converter 29 Note that the output voltage VO is independent of the load resistance RL . It depends only on the dc input voltage VI and the duty cycle D. The sensitivity of the output voltage with respect to the duty cycle is dVO = VI . (2.35) dD In most practical situations, VO = DVI is constant which means that if VI is increased, D should be decreased by a control circuit to keep VO constant, and vice versa. The dc current transfer function is given by S≡ MIDC ≡ IO 1 = II D (2.36) and its value decreases from ∞ to 1 as D is increased from 0 to 1. From (2.8), (2.15), and (2.33), the switch and the diode utilization in the buck converter is characterized by the output-power capability cp ≡ PO V I V V = O O ≈ O = O = D. VSM ISM VSM ISM VSM VI (2.37) As D is increased from 0 to 1, so does cp . 2.2.7 Boundary Between CCM and DCM Figure 2.3 depicts the inductor current waveform at the boundary between the CCM and the DCM, where iL (0) = 0. This waveform can be described by VI − VO t, L iL = for 0 < t ≤ DT (2.38) resulting in the peak inductor current ΔiL = iL (DT) = (V − VO )D VO (1 − D) (VI − VO )DT = I = L fs L fs L (2.39) where VI = VO ∕MV DC = VO ∕D for a lossless buck converter. Hence, one obtains a dc load current at the boundary IOB = (V − VO )D VO (1 − D) ΔiL = I = 2 2fs L 2fs L (2.40) VO 2fs L . = IOB 1−D (2.41) and the load resistance at the boundary RLB = Figures 2.4 and 2.5 show the normalized load current IOB ∕(VO ∕2fs L) = 1 − D and the load resistance RLB ∕(2fs L) = 1∕(1 − D) at the boundary between CCM and DCM as functions of the duty cycle D, respectively. The plots can be obtained using MATLAB® , described in Appendix B. iL ΔiLmax VImax VO L VImin VO L VO L IOB 0 Figure 2.3 DminT DmaxT T t Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax . 30 Pulse-Width Modulated DC–DC Power Converters 1 0.8 IOB /(VO /2fsL) CCM 0.6 0.4 DCM 0.2 0 0 0.2 0.4 D 0.6 0.8 1 Figure 2.4 Normalized load current IOB ∕(VO ∕2fs L) at the boundary between CCM and DCM as a function of the duty cycle D for buck converter. 10 RLB /(2 fs L) 8 6 DCM 4 2 CCM 0 0 0.2 0.4 D 0.6 0.8 1 Figure 2.5 Normalized load resistance RLB ∕(2fs L) at the boundary between CCM and DCM as a function of the duty cycle D for buck converter. Buck PWM DC–DC Converter 31 For the worst case, IOmin = IOBmax = V − VO V (1 − Dmin ) ΔiLmax = Imax = O . 2 2fs Lmin 2fs Lmin (2.42) Hence, the minimum inductance required to maintain the CCM operation for the duty cycle ranging from Dmin to Dmax is L > Lmin = Dmin (VImax − VO ) VO (1 − Dmin ) RLmax (1 − Dmin ) = = . 2fs IOmin 2fs IOmin 2fs (2.43) As the switching frequency fs increases, the minimum inductance Lmin decreases. Therefore, high switching frequencies are desirable to reduce the size of the inductor. In some applications, the inductance L can be much higher than Lmin in order to reduce the ripple current through the inductor and the filter capacitor. Therefore, it is easier to reduce the output voltage ripple, to avoid the core saturation, and to reduce the winding and core losses. In a real converter, the efficiency 𝜂 < 1, and therefore MV DC = VO ∕VI = 𝜂D. Since VI = VO ∕(𝜂D), ( ) 1 V − D O (V − VO )DT (V − VO )D 𝜂 = I = (2.44) ΔiL = iL (DT) = I L fs L fs L ( IOB = (V − VO )D ΔiL = I = 2 2fs L VO ) 1 −D 𝜂 2fs L ( ) 1 − D V O min (V − V )D Δi 𝜂 O min = IOmin = IOBmax = Lmax = Imax 2 2fs Lmin 2fs Lmin and ( ) ( ) 1 RLmax 1𝜂 − Dmin Dmin (VImax − VO ) VO 𝜂 − Dmin L > Lmin = = = , 2fs IOmin 2fs IOmin 2fs (2.45) (2.46) (2.47) where Dmin = MV DCmin ∕𝜂 = VO ∕(𝜂VImax ). A gapped ferrite core should be used to make the inductor because the inductor current contains a dc component, and therefore the core may saturate. The inductance is given by L= 𝜇0 A c N 2 l (2.48) lg + 𝜇c r where N is the number of turns, Ac is the core cross-sectional area, lc is the magnetic path length (MPL), and lg is the air-gap length. If the dc output current IO and the dc input voltage VI are fixed, the peak-to-peak inductor current ΔiL = 2IO can be made very large while maintaining the converter operation in CCM. In this case, the ripple current of the inductor should be limited, for example, ΔiL ∕(2IO ) ≤ 10%. 2.2.8 Capacitors Capacitors are classified according to dielectric material used between the conductors. The following types of capacitors are used in switching-mode power supplies: r wet aluminum electrolytic capacitors r wet tantalum electrolytic capacitors 32 Pulse-Width Modulated DC–DC Power Converters r solid electrolytic capacitors r ceramic capacitors. Wet electrolytic capacitors can be built using aluminum or tantalum. They are made of two aluminum foils. A paper spacer soaked in wet electrolyte separates the two aluminum foils. One of the aluminum foils is coated with an insulating aluminum oxide layer, which forms the capacitor dielectric material. The aluminum foil coated in aluminum oxide is the anode of the capacitor. The liquid electrolyte and the second aluminum foil act as a cathode of the capacitor. The two aluminum foils with attached leads are rolled together with the electrolyte soaked paper in a cylindrical aluminum case to form a wet aluminum electrolyte capacitor. Wet electrolyte tantalum capacitors are formed in a similar manner as wet aluminum electrolyte capacitors except that the dielectric material is tantalum oxide. Solid electrolytic capacitors are constructed similarly to wet electrolytic capacitors except that a solid dielectric material is used in place of a wet dielectric material These capacitors have moderate capacitances and a higher ripple current rating. Electrolytic capacitors are the most commonly used in power electronics because of a high ratio of capacitance per unit volume and low cost. Ceramic capacitors use ceramic dielectric to separate two conductive plates. The ceramic dielectric material is composed of titanium dioxide (Class I) or barium titanate (Class II). Ceramic capacitors can be disc capacitors or multilayer ceramic (MLC) capacitors. Disc capacitors have low capacitance per unit volume. Conductive material is placed on the ceramic dielectric material forming interlace fingers. Ceramic capacitors have lower capacitances than electrolytic capacitors. The capacitances of ceramic capacitors are usually below 1 𝜇F. Ceramic capacitors have very low values of ESR. This property reduces voltage ripple and power loss. Important parameters of capacitors are the capacitance C, the equivalent series resistance (ESR) rC , and the series equivalent inductance (ESL) Ls , the self-resonant frequncy fr , and the breakdown voltage VBD . The capacitance is 𝜖r 𝜖A (2.49) d where A is the area of each conductor, d is the thickness of the dielectric, 𝜖r is the relative permittivity of the dielectric, and 𝜖0 = 8.85 × 10−12 F/m is the permittivity of free space. The ESR is the sum of the resistances of leads, the resistances of the contacts, and the resistance of the plate conductors. The ESL is the inductance of the leads. The self-resonant frequency is C= 1 . √ 2𝜋 CLs (2.50) DF = 𝜔CrC . (2.51) fr = The dissipation factor of a capacitor is The quality factor of a capacitor at a frequency f = 𝜔∕(2𝜋) is QC = 1 1 . = 𝜔CrC DF (2.52) For the buck converter, the ESL is connected in series with the filter inductance L and does not present a problem. However, the ESL can have a negative effect in boost converter. Capacitors are rated for the breakdown voltage and the maximum rms value of the ripple current. The maximum rms ripple current is the limit of ac current and is dependent of the temperature and frequency of the current 2 conducted by a capacitor. The ripple current flowing through the ESR causes power loss PC = rC Iac(rms) , which generates heat within the capacitor. Electrolytic tantalum capacitors have the highest values of ESR, and ceramic capacitors have the lowest ESR. The performance of electrolytic capacitors is highly affected by operating conditions, such as frequency, ac current, dc voltage, and temperature. The ESR is frequency dependent. As the frequency increases, the ESR first Buck PWM DC–DC Converter 33 decreases, usually reaches a minimum value at the self-resonant frequency, and then increases. For electrolytic capacitors, the ESR decreases as the dc voltage increases. It also decreases as the peak-to-peak ac ripple voltage increases. The ESR is often measured by manufacturers at the capacitor self-resonant frequency. The ESR of capacitors controls the peak-to-peak value of the output ripple voltage. Also, the higher the ESR of the capacitor, the greater the heat generated due to the continuous flow of current through the ESR. This reduces the converter efficiency and life expectancy of the power supply. During aging process, the electrolytic liquid inside the capacitor gradually evaporates, causing an increase in ESR. When a voltage is applied between the conductors and across the dielectric of a capacitor, an electric field is induced in the dielectric. The electric energy is stored in the electric field. The dielectric has a maximum value of the electric field strength EBD = VBD ∕d, resulting in a capacitor breakdown voltage VBD . 2.2.9 Ripple Voltage in Buck Converter for CCM A model of the filter capacitor consists of capacitance C, equivalent series resistance rC , and equivalent series inductance LESL The impedance of the capacitor model is )] [ ( ) ( 𝜔 1 𝜔 ZC = rC + j 𝜔LESL − = rC 1 + jQCo (2.53) − r 𝜔C 𝜔r 𝜔 where the self-resonant frequency of the filter capacitor is fr = 1 √ 2𝜋 CLESL (2.54) and the quality factor of the capacitor at its self-resonant frequency is QCo = 1 . 𝜔r CrC (2.55) Figures 2.6 and 2.7 show plots of the magnitude |ZC | and phase 𝜙ZC of the capacitor for C = 1 𝜇F, rC = 50 mΩ, and LESL = 15 nH. The filter capacitor impedance is capacitive below the self-resonant frequency and inductive above the self-resonant frequency. The input voltage of the second-order low-pass LCR output filter is rectangular with a maximum value VI and a duty cycle D. This voltage can be expanded into a Fourier series ] [ ∞ ∑ sin(n𝜋D) cos n𝜔s t v = DVI 1 + 2 n𝜋D n=1 ] [ sin 2𝜋D sin 3𝜋D sin 𝜋D cos 𝜔s t + cos 2𝜔s t + cos 3𝜔s t + ⋯ . = DVI + 2DVI (2.56) 𝜋D 2𝜋D 3𝜋D The components of this series are transmitted through the output filter to the load. It is difficult to determine the peak-to-peak output voltage ripple Vr using the Fourier series of the output voltage. Therefore, a different approach will be taken for deriving an expression for Vr . A simpler derivation [24] is given below. A model of the output part of the buck converter for frequencies lower than the capacitor self-resonant frequency (i.e., f ≤ fr ) is shown in Figure 2.8. The filter capacitor in this figure is modeled by its capacitance C and its equivalent series resistance (ESR) designated by rC . Figure 2.9 depicts current and voltage waveforms in the converter output circuit. The dc component of the inductor current flows through the load resistor RL while the ac component is divided between the capacitor C and the load resistor RL . In practice, the filter capacitor is designed so that the impedance of the capacitive branch is much less than the load resistance RL . Consequently, the load ripple current is very small and can be neglected. Thus, the current through the capacitor is approximately equal to the ac component of the inductor current, that is, iC ≈ iL − IO . Pulse-Width Modulated DC–DC Power Converters 5 10 4 10 3 | ZC | (Ω) 10 2 10 1 10 0 10 −1 10 −2 10 0 2 10 10 Figure 2.6 4 10 f (Hz) 6 10 8 10 Magnitude of the capacitor impedance. 90 60 30 C ϕ (°) 34 0 −30 −60 −90 4 10 5 10 Figure 2.7 6 10 f (Hz) 7 10 Phase of the capacitor impedance. 8 10 Buck PWM DC–DC Converter L 35 iO = IO + io iL iC C + vC rC + vrc RL + VO + vo Figure 2.8 Model of the output circuit of the buck converter for frequencies lower than the self-resonant frequency of the filter capacitor. For the interval 0 < t ≤ DT, when the switch is on and the diode is off, the capacitor current is given by iC = ΔiL t ΔiL − DT 2 (2.57) resulting in the ac component of the voltage across the ESR ( vrc = rC iC = rC ΔiL ) 1 t − . DT 2 (2.58) iL IO 0 DT T t ic Δ 0 DT T 2 T DT T DT T t vrc 0 t vc 0 t vo 0 Figure 2.9 Vr t min DT t max T t Waveforms illustrating the ripple voltage in the PWM buck converter. 36 Pulse-Width Modulated DC–DC Power Converters The voltage across the filter capacitance vC consists of the dc voltage VC and the ac voltage vc , that is, vC = VC + vc . Only the ac component vc may contribute to the output ripple voltage. The ac component of the voltage across the filter capacitance is found as ( 2 ) t t( ) Δi Δi 1 1 t t vc = − dt + vc (0) = L − t + vc (0). iC dt + vc (0) = L (2.59) C ∫0 C ∫0 DT 2 2C DT For steady state, vc (DT) = vc (0). The waveform of the voltage across capacitance C is a parabolic function. The ac component of the output voltage is the sum of voltage across the filter capacitor ESR rC and the filter capacitance C [ vo = vrc + vc = ΔiL ] (r ) r t2 1 C + − t − C + vc (0). 2CDT DT 2C 2 (2.60) Let us consider the minimum value of the voltage vo . The derivative of the voltage vo with respect to time is ) ( r dvo 1 t = ΔiL + C − . (2.61) dt CDT DT 2C Setting this derivative to zero, the time at which the minimum value of vo occurs is given by tmin = DT − rC C. 2 (2.62) The minimum value of vo is equal to the minimum value of vrc if tmin = 0. This occurs at a minimum capacitance, which is given by Cmin(on) = Dmax . 2fs rCmax (2.63) Consider the time interval DT < t ≤ T when the switch S is off and the diode D1 is on. Referring to Figure 2.9, the current through the capacitor is iC = − ΔiL (t − DT) ΔiL + (1 − D)T 2 (2.64) resulting in the voltage across the ESR ] [ 1 t − DT vrc = rC iC = rC ΔiL − + (1 − D)T 2 (2.65) and the voltage across the capacitor ] [ t ΔiL t 1 t − DT 1 vc = − + dt + vc (DT) i dt + vc (DT) = C ∫DT C C ∫DT (1 − D)T 2 [ 2 ] Δi t − 2DTt + (DT)2 + t − DT + vc (DT). = L − 2C (1 − D)T Adding (2.65) and (2.66) yields the ac component of the output voltage ] [ 2 ] [ Δi t − 2DTt + (DT)2 1 t − DT vo = rc ΔiL − + + L − + t − DT + vc (DT). (1 − D)T 2 2C T(1 − D) (2.66) (2.67) The derivative of vo with respect to time is [ ] r Δi dvo Δi t − DT 1 =− C L + L − + . dt (1 − D)T C (1 − D)T 2 (2.68) Buck PWM DC–DC Converter 37 Setting the derivative to zero, the time at which the maximum value of vo occurs is expressed by (1 + D)T − rC C. (2.69) 2 The maximum value of vo is equal to the maximum value of vrc if tmax = DT. This occurs at a minimum capacitance, which is given by tmax = Cmin(off ) = 1 − Dmin . 2fs rCmax (2.70) The peak-to-peak ripple voltage is independent of the voltage across the filter capacitance C and is determined only by the ripple voltage across the ESR if C ≥ Cmin = max{Cmin(on) , Cmin(off ) } = max{Dmax , 1 − Dmin } . 2fs rC (2.71) Hence, Dmax 2fs rC for Dmin + Dmax > 1 (2.72) 1 − Dmin 2fs rC for Dmin + Dmax < 1. (2.73) Cmin = and Cmin = For the worst case, Dmin = 0 or Dmax = 1. Thus, the above condition is satisfied at any value of D if C ≥ Cmin = 1 . 2rC fs (2.74) If condition (2.71) is satisfied, the peak-to-peak ripple voltage of the buck converter is Vr = rC ΔiLmax = rC VO (1 − Dmin ) . fs L (2.75) For steady-state operation, the average value of the ac component of the capacitor voltage vc is zero, that is, T 1 v dt = 0 T ∫0 c (2.76) resulting in vc (0) = ΔiL (2D − 1) . 12fs C (2.77) Waveforms of vrc , vc , and vo are depicted in Figure 2.10 for three values of the filter capacitance C. In Figure 2.10(a), the peak-to-peak value of vo is higher than the peak-to-peak value of vrc because C < Cmin . Figures 2.10(b) and (c) shows the waveforms for C = Cmin and C > Cmin , respectively. For both these cases, the peak-to-peak voltages of vo and vrc are the same. For aluminum electrolytic capacitors, 𝜏 = rC C ≈ 65 × 10−6 s. If condition (2.71) is not satisfied, both the voltage drop across the filter capacitor C and the voltage drop across the ESR contribute to the ripple output voltage. The ac component of the voltage across the filter capacitor increases when the ac component of the charge stored in capacitor is positive. The positive charge is equal to the area under the capacitor current waveform for iC > 0. The capacitor current is positive during time interval T∕2. The maximum increase of the charge stored in the filter capacitor in every cycle T is T ΔiLmax 2 ΔQ = 2 2 = TΔiLmax Δi = Lmax . 8 8fs (2.78) 38 Pulse-Width Modulated DC–DC Power Converters 0.08 vo c vc vr Vrc , Vc ,Vo (V) 0.04 0 −0.04 −0.08 0 0.2 0.4 0.6 0.8 1 t/T (a) 0.08 vo c vc vr Vrc , Vc ,Vo (V) 0.04 0 −0.04 −0.08 0 0.2 0.4 0.6 0.8 1 t/T (b) 0.08 vo c vc vr Vrc , Vc ,Vo (V ) 0.04 0 −0.04 −0.08 0 0.2 0.4 0.6 0.8 1 t/T (c) Figure 2.10 Waveforms of vc , vrc , and vo at three values of the filter capacitor for CCM. (a) C < Cmin . (b) C = Cmin . (c) C > Cmin . Buck PWM DC–DC Converter 39 Hence, using (2.39), the voltage ripple across the capacitance C is 2 VCpp = 2 V (1 − D ) (1 − Dmin )𝜋 VO fo ΔQ ΔiLmax = = O 2 min = C 8fs C 8fs LC 2fs2 (2.79) (1 − Dmin )VO ΔiLmax = . 8fs VCpp 8fs2 LVCpp (2.80) √ where fo = 1∕(2𝜋 LC) is the corner frequency of the output filter. The minimum filter capacitance required to reduce its peak-to-peak ripple voltage below a specified level VCpp is Cmin = Thus, Cmin is inversely proportional to fs2 . Therefore, high switching frequencies are desirable to reduce the size of the filter capacitor. Using (2.39), the peak-to-peak voltage ripple across the ESR is Vrcpp = rC ΔiLmax = rC VO (1 − Dmin ) . fs L (2.81) Hence, the conservative estimation of the total voltage ripple is VO (1 − Dmin ) rC VO (1 − Dmin ) . + fs L 8fs2 LC Vr ≈ VCpp + Vrcpp = (2.82) 2.2.10 Switching Losses with Linear MOSFET Output Capacitance Let us assume that the MOSFET output capacitance Co is linear. First, we shall consider the transistor turn-off transition. During this time interval, the transistor is off, the drain-to-source voltage vDS increases from nearly zero to VI , and the transistor output capacitance is charged. Because dQ = Co dvDS , the charge transferred from the input voltage source VI to the transistor output capacitance Co during the turn-off transition is T Q= ∫0 VI iI dt = VI dQ = Co ∫0 dvDS = Co VI ∫0 (2.83) yielding the energy transferred from the input voltage source VI to the converter during the turn-off transition as T WV I = ∫0 T p(t)dt = ∫0 T vI iI dt = VI iI dt = VI Q = Co VI2 . ∫0 (2.84) An alternative method for deriving an expression for the energy delivered from a dc source VI to a series R-Co circuit after turning on VI is as follows. The input current is iI = VI − t e 𝜏 R (2.85) where 𝜏 = RCo is the time constant. Hence, ∞ WV I = ∫0 ∞ vI iI dt = VI ∫0 iI dt = VI2 R ∫0 ∞ t e− 𝜏 dt = VI2 𝜏 R = Co VI2 . (2.86) Using dWs = QdvDS ∕2, the energy stored in the transistor output capacitance Co at the end of the transistor turn-off transition, when vDS = VI , is given by VI Ws = ∫0 V dWs = I 1 1 1 Q dvDS = QVI = Co VI2 . 2 ∫0 2 2 (2.87) 40 Pulse-Width Modulated DC–DC Power Converters Thus, the energy lost in the parasitic resistance of the capacitor charging path is the turn-off switching energy loss described by 1 1 Wturn-off = WVI − Ws = Co VI2 − Co VI2 = Co VI2 2 2 which results in the turn-off switching power loss in the resistance of the charging path (2.88) Wturn-off 1 (2.89) = fs Wturn-off = fs Co VI2 . T 2 After turn-off, the transistor remains in the off-state for some time interval and the charge Ws is stored in the output capacitance Co . The efficiency of charging a linear capacitance from a dc voltage source is 50%. Now consider the transistor turn-on transition. When the transistor is turned on, its output capacitance Co is shorted out through the transistor on-resistance rDS , the charge stored in Co decreases, and the drain-to-source voltage decreases from VI to nearly zero. As a result, all the energy stored in the transistor output capacitance is dissipated as heat in the transistor on-resistance rDS . Therefore, the turn-on switching energy loss is Pturn-off = Wturn-on = Ws = 1 C V2 2 o I (2.90) resulting in the turn-on switching power loss in the MOSFET Wturn-on 1 = fs Wturn-on = fs Co VI2 . (2.91) T 2 The turn-on loss is independent of the transistor on-resistance rDS as long as the transistor output capacitance is fully discharged before the turn-off transition begins. The total switching energy loss in every cycle of the switching frequency during the process of first charging and then discharging of the output capacitance is given by Pturn-on = Psw(FET) = Wsw = Wturn-off + Wturn-on = WVI = Co VI2 (2.92) and the total switching loss in the converter is Wsw = fs Wsw = fs Co VI2 . (2.93) T For a linear capacitance, one-half of the switching power is lost in the MOSFET and the other half is lost in the resistance of the charging path of the transistor output capacitance, that is, Pturn-on = Pturn-off = Psw ∕2. The behavior of a diode is different from that of a transistor because a diode cannot discharge its parallel capacitance through its forward resistance. This is because a diode does not turn on until its voltage drops to the threshold voltage. However, the junction diodes suffer from the reverse recovery at turn-off. Psw = 2.2.11 Switching Losses with Nonlinear MOSFET Output Capacitance The MOSFET drain-to-source capacitance Cds is a nonlinear capacitance of the pn step-junction body-diode, which depends on the drain-to-source voltage vDS . This capacitance is given by √ CJ0 VB = CJ0 for vDS ≥ −VB (2.94) Cds = √ vDS v DS + VB 1+ VB where CJ0 is the zero-bias junction capacitance and VB is the built-in potential barrier and it is in the range 0.55–0.9 V. From (2.94), √ √ VI + VB VI Cds (vDS ) = Cds (VI ) ≈ Cds (VI ) . (2.95) vDS + VB vDS Buck PWM DC–DC Converter 41 Manufacturers of power MOSFETs usually specify the capacitances Crss = Cgd , Ciss = Cgs + Cgd , and Coss = Cds + Cgd at f = 1 MHz. The capacitances Crss and Coss are measured at VDS = 25 V and VGS = 0 V. Hence, Cds25 = Coss − Crss . The output capacitance at vDS = VI is √ CJ0 5C 25 + VB Cds (VI ) = √ = Cds25 ≈ √ds25 . (2.96) V VI + VB VI 1 + VI B Since dQ = Cds dvDS , the charge transferred from the dc input voltage source VI to the drain-to-source junction capacitance Cds during the turn-off transition is given by √ vDS vDS VB C (v )dv = CJ0 dv Q(vDS ) = ∫−VB ds DS DS ∫−VB vDS + VB DS √ = 2CJ0 VB (vDS + VB ) = 2(vDS + VB )Cds (vDS ) ≈ 2Cds (vDS )vDS . (2.97) Hence, Q(VI ) = 2(VI + VB )Cds (VI ) ≈ 2Cds (VI )VI . (2.98) The energy transferred from the input dc voltage source VI to the converter during the turn-off transition is given by VI WV I = ∫−VB VI vI iI dt = VI i dt = VI Q(VI ) = 2VI (VI + VB )Cds (VI ) ≈ 2Cds (VI )VI2 . ∫−VB I (2.99) Because dWs = QdvDS ∕2, the energy stored in the drain-to-source capacitance Cds at vDS is vDS Ws (vDS ) = ∫−VB DS DS √ √ 1 QdvDS = CJ0 VB vDS + VB dvDS ∫ ∫ 2 −VB −VB v dWs = v 2 2 (v + VB )2 Cds (vDS ) ≈ Cds (vDS )v2DS . 3 DS 3 Hence, one obtains the energy stored in Cds at VI = (2.100) 2 2 (V + VB )2 Cds (VI ) ≈ Cds (VI )VI2 . (2.101) 3 I 3 Therefore, the energy lost in the resistance of the charging path of the MOSFET output capacitance is given by Ws = 2 4 Wturn-off = WVI − Ws ≈ 2Cds (VI )VI2 − Cds (VI )VI2 = Cds (VI )VI2 . (2.102) 3 3 Hence, the switching power loss dissipated in the resistance r of the path of charging the transistor output capacitance is √ Wturn-off 4 20 Pr = Pturn-off = = fs Wturn-off = fs Cds (VI )VI2 = fs Cds25 VI3 . (2.103) T 3 3 The transistor equivalent linear output capacitance that causes the same switching power loss in the charging path resistance r during the turn-off transition as the linear one is derived as √ 1 4 20 fs Ceq(r) VI2 = fs Cds (VI )VI2 = fs Cds25 VI3 (2.104) 2 3 3 producing Ceq(r) = 40C 8 C (V ) = √ds25 . 3 ds I 3 VI (2.105) 42 Pulse-Width Modulated DC–DC Power Converters During the turn-on transition, all the energy stored in the transistor output capacitance is lost in the MOSFET on-resistance rDS Wturn-on = Ws = 2 2 C (V )(V + VB )2 ≈ Cds (VI )VI2 . 3 ds I I 3 (2.106) Thus, the MOSFET turn-on switching loss is √ Wturn-on 2 10 = fs Wturn-on = fs Cds (VI )VI2 = fs Cds25 VI3 . (2.107) T 3 3 The transistor equivalent linear output capacitance that causes the same switching power loss in the MOSFET on-resistance during the turn-on transition as the linear one can be obtained as √ 1 2 10 fs Ceq(FET) VI2 = fs Cds (VI )VI2 = fs Cds25 VI3 (2.108) 2 3 3 resulting in Psw(FET) = Pturn-on = Ceq(FET) = 20C 4 C (V ) = √ds25 . 3 ds I 3 VI (2.109) The total switching energy loss in each cycle of the switching frequency is Wsw = Wturn-off + Wturn-on = WVI = 2Cds (VI )VI2 (2.110) and the total switching loss in the converter is √ Wsw = fs Wsw = 2fs Cds (VI )VI2 = 10fs Cds25 VI3 . (2.111) T The transistor equivalent linear output capacitance Ceq(sw) that produces the same amount of the switching loss as the nonlinear one at a given VI can be derived as √ fs Ceq(sw) VI2 = 2fs Cds (VI )VI2 = 10fs Cds25 VI3 (2.112) Psw = yielding 10C Ceq(sw) = 2Cds (VI ) = √ ds25 . VI (2.113) The turn-off switching power loss is twice as high as the turn-on switching power loss for the MOSFET with a nonlinear output capacitance. The ratio of these losses is Pturn-off Pturn-on = 2. (2.114) Example 2.1 A power MOSFET IRF510 with VB = 0.774158 V, Crss = 25 pF, and Coss = 100 pF is operated in the buck PWM converter at VI = 100 V and fs = 100 kHz. Find: Cds25 , CJ0 , Cds (VI ), Q(VI ), Wsw , Psw , Ceq(sw) , Wturn-on , Psw(FET) , Ceq(FET) , Wturn-off , Pturn-off , and Ceq(r) . Solution: The transistor drain-to-source capacitance at VDS = 25 V is Cds25 = Coss − Crss = 100 − 25 = 75 pF. The zero-bias drain-to-source capacitance is √ CJ0 = Cds25 25 1+ = 75 × VB √ 1+ 25 = 432.75 pF. 0.774158 (2.115) (2.116) Buck PWM DC–DC Converter 43 The drain-to-source capacitance at VI = 100 V is Cds (VI ) = √ CJ0 432.75 × 10−12 = √ = 37.93 pF. V 100 1 + VI 1 + 0.774158 (2.117) B The charge transferred from the dc input source to Cds during the turn-off transition is Q(VI ) = 2(VI + VB )Cds (VI ) = 2 × (100 + 0.774158) × 37.93 × 10−12 = 7.6447 nC. (2.118) The switching energy is Wsw = WVI = 2VI2 Cds (VI ) = 2 × 1002 × 37.93 × 10−12 = 758.6 nJ. (2.119) Psw = 2fs VI2 Cds (VI ) = 2 × 100 × 103 × 1002 × 37.93 × 10−12 = 75.86 mW. (2.120) The switching loss is The equivalent linear switching capacitance is Ceq(sw) = 2Cds (VI ) = 2 × 37.93 × 10−12 = 75.86 pF. (2.121) The energy lost during the turn-on transition is equal to the energy stored in Cds at the end of the turn-off transition when vDS = VI . This energy is 2 2 2 V C (V ) = × 1002 × 37.93 × 10−12 = 252.87 nJ. 3 I ds I 3 The switching power loss in the MOSFET is Wturn-on = Ws = 2 2 2 f V C (V ) = × 100 × 103 × 1002 × 37.93 × 10−12 = 25.287 mW. 3 s I ds I 3 The equivalent linear turn-on capacitance is Psw(FET) = 4 4 C (V ) = × 37.93 × 10−12 = 50.57 pF. 3 ds I 3 The energy lost in the resistance of the charging path of Cds during the turn-off transition is Ceq(FET) = Wturn-off = 4 2 4 V C (V ) = × 1002 × 37.93 × 10−12 = 505.73 nJ. 3 I ds I 3 (2.122) (2.123) (2.124) (2.125) The turn-off switching loss is 4 2 4 f V C (V ) = × 100 × 103 × 1002 × 37.93 × 10−12 = 50.573 mW. 3 s I ds I 3 The turn-off equivalent linear capacitance is Pturn-off = Ceq(r) = 8 8 C (V ) = × 37.93 × 10−12 = 101.1 pF. 3 ds I 3 (2.126) (2.127) 2.2.12 Power Losses and Efficiency of Buck Converter for CCM An equivalent circuit of the buck converter with parasitic resistances is shown in Figure 2.11. In this figure, rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The slope of the ID –VDS curves in the ohmic region is equal to the inverse of the MOSFET on-resistance 1∕rDS . The MOSFET on-resistance rDS increases with temperature because the mobility of electrons 𝜇n ≈ K1 ∕T 2.5 decreases with temperature T in the range from 100 to 400◦ C, where K1 is a constant. Typically, rDS doubles as the temperature rises by 100◦ C. 44 Pulse-Width Modulated DC–DC Power Converters iS iL rDS IO rL L iC C iD VI RF rC VF Figure 2.11 + VO RL Equivalent circuit of the buck converter with parasitic resistances and the diode offset voltage. The large-signal model of a diode consists of a battery VF in series with a forward resistance RF . The voltage across the conducting diode is VD = VF + RF ID . If a line is drawn along the linear high-current portion of the ID –VD curve (or log(ID )–VD ) extending to the VD -axis, the intercept on the VD -axis is VF and the slope is 1∕RF . The threshold voltage VF is typically 0.7 V for silicon (Si) pn junction diodes, and VF = 2.8 V for silicon carbide (SiC) pn junction diodes. The threshold voltage VF = 0.3–0.4 V for silicon Schottky diodes and VF = 2 V for silicon carbide Schottky diodes. The threshold voltage VF of silicon diodes decreases with temperature at the rate of 2 mV/◦ C. The series resistance RF of pn junction diodes decreases with temperature, while resistance RF of Schottky diodes increases with temperature. The conduction losses will be evaluated assuming that the inductor current iL is ripple free and is equal to the dc output current IO . Hence, the switch current can be approximated by { IO , for 0 < t ≤ DT (2.128) iS = 0, for DT < t ≤ T which results in its rms value √ ISrms = √ T 1 i2 dt = T ∫0 S 1 T ∫0 √ IO2 dt = IO D (2.129) DrDS P . RL O (2.130) DT and the MOSFET conduction loss 2 PrDS = rDS ISrms = DrDS IO2 = The transistor conduction loss PrDS is proportional to the duty cycle D at a fixed load current IO . At D = 0, the switch is off for the entire cycle and therefore the conduction loss is zero. At D = 1, the switch is on for the entire cycle, resulting in a maximum conduction loss. Assuming that Dmax = VO ∕VImin as for the lossless converter, the maximum MOSFET conduction power is 2 PrDSmax = Dmax rDS IOmax = Dmax rDS V r POmax ≈ O DS POmax . RLmin VImin RLmin (2.131) Assuming that the transistor output capacitance Co is linear, the switching loss is expressed by Psw = fs Co VI2 = fs Co VO2 MV2 DC fC R = s 2o L PO . MV DC (2.132) The maximum switching loss is 2 Psw(max) = fs Co VImax = fs Co VO2 MV2 DCmin = 2 fs Co RLmin VImax VO2 PO . (2.133) Buck PWM DC–DC Converter Excluding the MOSFET gate-drive power, the total power dissipation in the MOSFET is ) ( Psw DrDS fs Co RL 1 2 2 PFET = PrDS + = DrDS IO + fs Co VI = PO . + 2 2 RL 2MV2 DC Similarly, the diode current can be approximated by { 0, for iD = IO , for yielding its rms value √ T √ 1 i2 dt = T ∫0 D IDrms = 45 (2.134) 0 < t ≤ DT DT < t ≤ T (2.135) √ 1 IO2 dt = IO 1 − D ∫ T DT (2.136) T and the power loss in RF 2 PRF = RF IDrms = (1 − D)RF IO2 = (1 − D)RF PO . RL (2.137) The average value of the diode current is T ID = T 1 1 i dt = I dt = (1 − D)IO T ∫0 D T ∫DT O (2.138) which gives the power loss associated with the voltage VF PVF = VF ID = (1 − D)VF IO = (1 − D)VF PO . VO Thus, the overall diode conduction loss is ( PD = PVF + PRF = (1 − D)VF IO + (1 − D)RF IO2 = (1 − D) (2.139) VF RF + VO RL ) PO . (2.140) The diode conduction loss PD decreases, when the duty cycle D increases at a fixed load current IO . At D = 0, the diode is on for the entire cycle, resulting in a maximum conduction loss. At D = 1, the diode is off for the entire cycle and therefore the conduction loss is zero. The maximum diode conduction loss is ) )( ) ( ( V R R VF VF PDmax = (1 − Dmin ) POmax ≈ 1 − O POmax . + F + F (2.141) VO RLmin VImax VO RLmin Typically, the power loss in the inductor core can be ignored and only the copper loss in the inductor winding should be considered. The inductor current can be approximated by iL ≈ IO (2.142) ILrms = IO (2.143) leading to its rms value and the inductor conduction loss rL P . RL O (2.144) rL P . RLmin Omax (2.145) 2 = rL IO2 = PrL = rL ILrms The maximum power loss in the inductor is 2 PrLmax = rL IOmax = 46 Pulse-Width Modulated DC–DC Power Converters Using (2.13), (2.57), and (2.64), the rms current through the filter capacitor is found to be √ T VO (1 − D) Δi 1 i2 dt = √ L = √ ICrms = T ∫0 C 12 12f L (2.146) s and the power loss in the filter capacitor rC Δi2L 2 PrC = rC ICrms = 12 = rC VO2 (1 − D)2 = 12fs2 L2 rC RL (1 − D)2 PO . 12fs2 L2 (2.147) The maximum power loss in the capacitor is PrCmax = rC Δi2Lmax 12 = rC VO2 (1 − Dmin )2 12fs2 L2 ≈ ( )2 V rC RL 1 − V O Imax 12fs2 L2 POmax . (2.148) The overall power loss is given by PLS = PrDS + Psw + PD + PrL + PrC = DrDS IO2 + fs Co VI2 + (1 − D)(VF IO + RF IO2 ) + rL IO2 + [ = DrDS fs Co RL + 2 + (1 − D) RL MV DC ( VF RF + VO RL ) + r R (1 − D)2 rL + C L 2 2 RL 12fs L ] PO . rC Δi2L 12 (2.149) Thus, the converter efficiency is 𝜂= PO PO 1 1 = = = P Dr +(1−D)RF +rL fC R r R (1−D)2 (1−D)VF PI PO + PLS 1 + LS 1 + DS + + s o L + C L PO RL VO 1 = 1+ DrDS +(1−D)RF +rL fC R r RL (1−D)2 (1−D)V + DV F + s Do2 L + C 12f 2 2 RL I s L MV2 DC 12fs2 L2 . (2.150) For D = 0, the switch is off and the diode is on, yielding the converter efficiency 𝜂= 1 R +r V 1 + FR L + VF L O . (2.151) For D = 1, the switch is on and the diode is off, resulting in the converter efficiency 𝜂= 1 r +r 1 + DSR L . (2.152) L If the inductor peak-to-peak current ripple ΔiL = VO (1 − D)∕(fs L) = D(1 − D)VI ∕(fs L) is taken into account, the rms value of the switch current is given by √ √ ( )2 √ 1 ΔiL D 2 2 ISrms = (ISmin + ISmin ISmax + ISmax ) = IO D 1 + (2.153) 3 12 IO where ISmin = IO − ΔiL ∕2 and ISmax = IO + ΔiL ∕2. Similarly, the rms value of the diode current is √ √ )2 ( √ ) 1 ΔiL 1−D ( 2 2 IDrms = IDmin + IDmin IDmax + IDmax = IO 1 − D 1 + 3 12 IO (2.154) Buck PWM DC–DC Converter where IDmin = IO − ΔiL ∕2 and IDmax = IO + ΔiL ∕2. The rms value of the inductor current is √ √ ( )2 ) 1 ΔiL 1( 2 2 = IO 1 + ILmin + ILmin ILmax + ILmax . ILrms = 3 12 IO 47 (2.155) For example, for ΔiL ∕IO = 0.1, ILrms = 1.0017IO , and for ΔiL ∕IO = 0.5, ILrms = 1.0408IO . Assuming that the resistances rL , rDS , and RF are constant and frequency independent, the conduction power loss in the MOSFET is given by [ [ ( ( )2 ] )2 ] rDS D 1 ΔiL 1 ΔiL 2 2 PrDS = rDS ISrms = rDS DIO 1 + (2.156) = 1+ PO . 12 IO RL 12 IO The conduction power loss in the diode forward resistance is [ [ ( ( )2 ] )2 ] RF (1 − D) 1 ΔiL 1 ΔiL 2 2 PRF = RF IDrms = RF (1 − D)IO 1 + = 1+ PO . 12 IO RL 12 IO (2.157) Assuming that the inductor resistance rL is independent of frequency, the power loss in the inductor winding is given by [ [ ( ( )2 ] )2 ] rL 1 ΔiL 1 ΔiL 2 2 PrL = rL ILrms = rL IO 1 + (2.158) = 1+ PO . 12 IO RL 12 IO The overall power loss is [ ( )2 ] } { DrDS + (1 − D)RF + rL fs Co RL (1 − D)VF rC RL (1 − D)2 1 ΔiL PO . + + PLS = 1+ + 2 RL 12 IO VO 12fs2 L2 MV DC (2.159) Hence, the converter efficiency is 𝜂= Dr +(1−D)R +r 1 + DS R F L L = 1 [ ( )2 ] fC R r RL (1−D)2 ΔiL (1−D)V 1 1 + 12 I + V F + Ms 2o L + C 12f 2 L2 O O V DC s 1 . [ ( )2 ] DrDS +(1−D)RF +rL f s Co R L rC RL (1−D)2 ΔiL RL (1−D)VF 1 1 + 12 DV + DV + D2 + 12f 2 L2 1+ R L I I (2.160) s For example, for ΔiL ∕IO = 0.1, For ΔiL ∕IO = 0.2, [ ( )2 ] ) ( 1 1 1 2 PrL = rL ILrms = rL IO2 1 + = 1.0008333rL IO2 . = rL IO2 1 + 12 10 1200 (2.161) [ ( ) ] ) ( 1 1 2 1 2 PrL = rL ILrms = rL IO2 1 + = 1.00333rL IO2 . = rL IO2 1 + 12 5 300 (2.162) In the buck converter, part of the dc input power is transferred directly to the output and is converted to ac power, which is then converted back to dc power. It can be shown that the amount of power which is converted to ac power is PAC = (1 − D)PO (2.163) and the amount of the dc power that directly flows to the output is PDC = DPO . (2.164) 48 Pulse-Width Modulated DC–DC Power Converters 2.2.13 DC Voltage Transfer Function of Lossy Converter for CCM The dc component of the input current is T II = 1 1 i dt = T ∫0 S T ∫0 DT IO dt = DIO (2.165) leading to the dc current transfer function of the buck converter MIDC ≡ IO 1 = . II D (2.166) This equation holds true for both lossless and lossy converters. The converter efficiency can be expressed as 𝜂= V I M PO = O O = MV DC MIDC = V DC PI VI II D (2.167) from which the voltage transfer function of the lossy buck converter is MV DC = 𝜂 D = 𝜂D = DrDS +(1−D)RF +rL fC R r R (1−D)2 (1−D)VF MIDC 1+ + + s o L + C L RL = VO MV2 DC D Dr +(1−D)R +r f Co R L r RL (1−D)2 (1−D)V 1 + DS R F L + DV F + (Vs ∕V + C 12f 2 2 2 L I O I) s L 12fs2 L2 . (2.168) For D = 1, MV DC = 𝜂 < 1. From (2.168), the on-duty cycle is D= MV DC V = O. 𝜂 𝜂VI (2.169) The duty cycle D at a given dc voltage transfer function is higher for the lossy converter than that of a lossless converter. This is because the switch S must be closed for a longer period of time for the lossy converter to transfer enough energy to supply both the required output energy and the converter losses. Substitution of (2.169) into (2.150) gives the converter efficiency 𝜂= where N𝜂 (2.170) D𝜂 ( ) {[ ( )] r R r − RF r R r − RF 2 VF VF + 1 + MV DC + C2 L2 − DS + C2 L2 − DS VO 6fs L RL VO 6fs L RL ( ) 1 }2 M 2 rC RL r R R + rL VF fs Co RL − V DC2 2 + + 2 + C 2 L2 1+ F RL VO 3fs L 12fs L MV DC N𝜂 = 1 + MV DC and ( r R R + rL VF fs Co RL D𝜂 = 2 1 + F + + 2 + C 2 L2 RL VO 12fs L MV DC (2.171) ) . (2.172) 2.2.14 MOSFET Gate-Drive Power When the transistor is driven by a square-wave voltage source, the MOSFET gate-drive power is associated with charging the transistor input capacitance, when the gate-to-source voltage increases, and discharging this Buck PWM DC–DC Converter 49 capacitance when the gate-to-source voltage decreases. Unfortunately, the input capacitance of power MOSFETs is highly nonlinear and therefore it is difficult to determine the gate-drive power, using the transistor input capacitance. In data sheets, a total gate charge Qg stored in the gate-to-source capacitance and the gate-to-drain capacitance is given at a specified gate-to-source voltage VGS (usually, VGS = 10 V) and a specified drain-to-source voltage VDS (usually, VDS = 0.8 of the maximum rating). Using a square-wave voltage source to drive the MOSFET gate, the energy transferred from the gate-drive source to the transistor is WG = Qg VGSpp . (2.173) This energy is lost during one cycle T of the switching frequency fs = 1∕T for charging and discharging the MOSFET input capacitance. Thus, the MOSFET gate-drive power is WG = fs WG = fs Qg VGSpp . T The gate-drive power PG is proportional to the switching frequency fs . The power gain is defined by PG = kp = PO . PG (2.174) (2.175) The power-added efficiency (PAE) incorporates the gate-drive power PG by subtracting it from the output power PO and is defined by 𝜂PAE = PO − PG . PI (2.176) If the power gain kp is high, 𝜂PAE ≈ 𝜂. If the power gain kp < 1, 𝜂PAE < 0. The total efficiency is defined by 𝜂t = PO . PI + PG (2.177) POAVG . PIAVG (2.178) The average efficiency is defined by 𝜂AVG = In order to determine this efficiency, the probability-density functions of the average input and output powers are required. 2.2.15 Gate Driver Both the gate and the source of the MOSFET in the buck converter are connected to two hot points. Therefore, it is difficult to drive the transistor. The driver is usually an integrated circuit, which requires a power supply and one end terminal of the power supply should be connected to ground. One option is to connect the driver between the gate and ground. In this case, KVL is vG − vGS + vDS − VI = 0 (2.179) vGS = vG − VI + vDS . (2.180) yielding When the MOSFET is on, vDS ≈ 0, resulting in vGS = vG − VI . (2.181) 50 Pulse-Width Modulated DC–DC Power Converters If the gate-to-source voltage vGS in the on state is 5–10 V, the on-gate voltage is vG(ON) = VI + vGS(ON) ≈ VI + 5 V to VI + 10 V. (2.182) For example, if VI = 5 V, vG(ON) = 5 + 5 = 10 V to vG(ON) = 5 + 10 = 15 V. However, if VI = 100 V, vG(ON) = 100 + 5 = 105 V to 100 + 10 = 110 V. When the MOSFET is off, the diode is on, vD ≈ 0, and vG(OFF) − vGS(OFF) = 0. If vG(OFF) = VI , vGS(OFF) = vG(OFF) = VI = 100 V. This high voltage will break the SiO2 dielectric in the gate. 2.2.16 Design of Buck Converter for CCM Design a PWM buck converter operating in CCM to meet the following specifications: VI = 28 ± 4 V, VO = 12 V, IOmin = 1 A, IOmax = 10 A, fs = 100 kHz, and Vr ∕VO ≤ 1%. Solution: The minimum, nominal, and maximum values of the input voltage VImin = 24 V, VInom = 28 V, and VImax = 32 V. The maximum and minimum values of the dc output power are POmax = VO IOmax = 12 × 10 = 120 W (2.183) POmin = VO IOmin = 12 × 1 = 12 W. (2.184) and The minimum and maximum values of the load resistance are V 12 = 1.2 Ω RLmin = O = IOmax 10 (2.185) and RLmax = VO 12 = 12 Ω. = IOmin 1 (2.186) The minimum, nominal, and maximum values of the dc voltage transfer function are MV DCmin = VO 12 = 0.375 = VImax 32 (2.187) MV DCnom = VO 12 = 0.43 = VInom 28 (2.188) MV DCmax = VO 12 = 0.5. = VImin 24 (2.189) and Assume the converter efficiency 𝜂 = 85%. The minimum, nominal, and maximum values of the duty cycle are Dmin = MV DCmin 0.375 = = 0.441 𝜂 0.85 (2.190) Dnom = MV DCnom 0.43 = = 0.506 𝜂 0.85 (2.191) Dmax = MV DCmax 0.5 = = 0.588. 𝜂 0.85 (2.192) and Buck PWM DC–DC Converter 51 Assuming the switching frequency fs = 100 kHz, the minimum inductance that is required to maintain the converter in CCM is ) ( ( ) 1 − 0.441 RLmax 1𝜂 − Dmin 12 × 0.85 Lmin = = = 44.18 𝜇H. (2.193) 2fs 2 × 105 Let us use a standard value of the inductane L = 50 𝜇H/rL = 0.05 Ω. The maximum inductor ripple current is ΔiLmax = VO (1 − Dmin ) 12 × (1 − 0.441) = 5 = 1.3416 A. fs L 10 × 50 × 10−6 (2.194) The ripple voltage is VO 12 = = 120 mV. (2.195) 100 100 If the filter capacitance is large enough, Vr = rCmax ΔiLmax and the maximum ESR of the filter capacitor is Vr = rCmax = Vr 120 × 10−3 = 89.5 mΩ. = ΔiLmax 1.3416 (2.196) Let rC = 50 mΩ. The minimum value of the filter capacitance at which the ripple voltage is determined by the ripple voltage across the ESR is } { D Dmax 1 − Dmin 0.588 Cmin = max = max = , = 58.8 𝜇F. (2.197) 2fs rC 2fs rC 2fs rC 2 × 105 × 50 × 10−3 Pick C = 100 𝜇F/25 V/50 mΩ. The corner frequency of the output low-pass filter is fo = 1 √ = 2𝜋 LC 1 = 2.25 kHz. √ −6 2𝜋 50 × 10 × 100 × 10−6 (2.198) Thus, fs ∕fo = 100∕2.25 = 44.4. The bandwidth of the converter is approximately equal to the corner frequency. The voltage and current stresses of power MOSFET and diode are VSMmax = VDMmax = VImax = 32 V (2.199) and ΔiLmax 1.427 = 10 + = 10.7135 A. (2.200) 2 2 An International Rectifier IRF150 power MOSFET is selected, which has VDSS = 100 V, ISM = 40 A, rDS = 55 mΩ, Co = 100 pF, and Qg = 63 nC. Also, an MBR1060 Schottky barrier diode is chosen, which has IDM = 20 A, VDM = 60 V, VF = 0.4 V, and RF = 25 mΩ. The power losses and the efficiency will be calculated at the minimum load resistance RLmin = 1.2 Ω and the maximum dc input voltage VImax = 32 V, which correspond to the minimum duty cycle Dmin = 0.441. The conduction power loss in the MOSFET is ISMmax = IDMmax = IOmax + 2 PrDS = Dmin rDS IOmax = 0.441 × 0.055 × 102 = 2.426 W (2.201) 2 Psw = fs Co VImax = 105 × 100 × 10−12 × 322 = 0.01 W. (2.202) and the switching loss is Hence, the total power loss in the MOSFET is PFET = PrDS + Psw = 2.426 + 0.005 = 2.431 W. 2 (2.203) 52 Pulse-Width Modulated DC–DC Power Converters However, the maximum conduction power loss in the MOSFET occurs at the minimum dc input voltage VImin = 24 V, 2 RLmin = 1.2 Ω, and Dmax = 0.588. Thus, PrDSmax = Dmax rDS IOmax = 0.588 × 0.055 × 102 = 3.234 W. The diode loss due to VF is PVF = (1 − Dmin )VF IOmax = (1 − 0.441) × 0.4 × 10 = 2.236 W (2.204) the diode loss due to RF is 2 PRF = (1 − Dmin )RF IOmax = (1 − 0.441) × 0.025 × 102 = 1.398 W (2.205) and the total diode conduction loss is PD = PVF + PRF = 2.236 + 1.398 = 3.634 W. (2.206) The power loss in the inductor dc ESR rL = 50 mΩ is 2 PrL = rL IOmax = 0.05 × 102 = 5 W. (2.207) rC (ΔiLmax )2 0.05 × 1.4272 = = 0.008 W. 12 12 (2.208) The power loss in the capacitor ESR is PrC = The total power loss is PLS = PrDS + Psw + PD + PrL + PrC = 2.426 + 0.01 + 3.634 + 5 + 0.008 = 11.078 W (2.209) and the efficiency of the converter at full load is 𝜂= PO 120 = 91.55%. = PO + PLS 120 + 11.078 (2.210) If the assumed efficiency is much different than the calculated one in (2.210), a next iteration step is needed with a new assumed converter efficiency. Note that the maximum conduction power loss in the MOSFET occurs at VImin = 24 V and RLmin = 1.2 Ω and is given by 2 PrDS = Dmax rDS IOmax = 0.588 × 0.055 × 102 = 3.234 W. (2.211) Assuming that the peak-to-peak gate-to-source voltage is VGSpp = 16 V, the MOSFET gate-drive power is PG = fs Qg VGSpp = 105 × 63 × 10−9 × 16 = 100.8 mW. (2.212) The efficiency 𝜂 of the designed buck converter was computed from (2.170) through (2.172) over the entire range of the specified operating conditions. Next, the duty cycle D was computed from (2.169), using the calculated efficiency 𝜂. The plots of 𝜂 and D as functions of VI , IO , and RL are shown in Figures 2.12 through 2.17 for rDS = 55 mΩ, RF = 25 mΩ, VF = 0.4 V, rL = 50 mΩ, rC = 50 mΩ, L = 40 𝜇H, Co = 100 pF, and fs = 100 kHz. The converter efficiency 𝜂 decreases as the load current IO increases (or the load resistance RL decreases). The minimum efficiency 𝜂min occurs at the maximum load current IOmax and the maximum dc input voltage VImax . The duty cycle D decreases when VI increases, and D increases when IO increases (or RL decreases). 2.3 DC Analysis of PWM Buck Converter for DCM Equivalent circuits for the PWM buck converter operating in the DCM are depicted in Figure 2.18. Idealized current and voltage waveforms are shown in Figure 2.19. At time t = 0 when the switch is turned on, the inductor current is zero. For the time interval 0 < t ≤ DT, the switch is on and the diode is off as depicted in Figure 2.18(b). The voltage across the diode is −VI . The voltage across the inductor is VI − VO , which causes the inductor current to increase Buck PWM DC–DC Converter 98 53 RL = 12 Ω 97 η (%) 96 2.4 Ω 95 94 93 92 91 24 1.2 Ω 25 26 27 28 VI (V) 29 30 31 32 Figure 2.12 Efficiency 𝜂 of the designed buck converter as a function of dc input voltage VI for CCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. 0.56 0.54 0.52 RL = 1.2 Ω 0.5 D 0.48 0.46 0.44 2.4 Ω 0.42 12 Ω 0.4 0.38 24 25 26 27 28 VI (V) 29 30 31 32 Figure 2.13 Duty cycle D of the designed buck converter as a function of dc input voltage VI for CCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. 54 Pulse-Width Modulated DC–DC Power Converters 98 97 V I = 24 V η (%) 96 28 V 95 32 V 94 93 92 91 Figure 2.14 and 32 V. 1 2 3 4 5 IO (A) 6 7 8 9 10 Efficiency 𝜂 of the designed buck converter as a function of load current IO for CCM at VI = 24 V, 28 V, 0.56 V I = 24 V 0.54 0.52 0.5 D 0.48 28 V 0.46 0.44 0.42 32 V 0.4 0.38 Figure 2.15 and 32 V. 1 2 3 4 5 IO (A) 6 7 8 9 10 Duty cycle D of the designed buck converter as a function of load current IO for CCM at VI = 24 V, 28 V, Buck PWM DC–DC Converter 55 98 V I = 24 V 97 32 V 96 η (%) 28 V 95 94 93 92 91 1 2 3 4 5 6 7 RL (Ω) 8 9 10 11 12 Figure 2.16 Efficiency 𝜂 of the designed buck converter as a function of load resistance RL for CCM at VI = 24 V, 28 V, and 32 V. 0.56 0.54 V I = 24 V 0.52 0.5 D 0.48 0.46 28 V 0.44 0.42 0.4 0.38 32 V 1 2 3 4 5 6 7 RL (Ω) 8 9 10 11 12 Figure 2.17 Duty cycle D of the designed buck converter as a function of load resistance RL for CCM at VI = 24 V, 28 V, and 32 V. 56 Pulse-Width Modulated DC–DC Power Converters L S vGS + VI iS D1 RL + VO RL + VO C RL + VO C RL + VO C (a) L iL + vL VI vD + C (b) L + vS iL + vL iD VI (c) + vS VI vD + (d) Figure 2.18 PWM buck converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF. linearly from zero. At time t = DT, the switch is turned off and the inductor current is diverted from the switch to the freewheeling diode. The equivalent circuit is shown in Figure 2.18(c) for time interval DT < t ≤ (D + D1 )T. The voltage across the switch is VI . The voltage across the inductor is −VO , causing the inductor current to decrease linearly. This current flows through the diode. At time t = (D + D1 )T, the diode current reaches zero and the diode begins to turn off. Since the diode cannot conduct negative current (neglecting the reverse-recovery current), the inductor current remains zero until the switch is turned on at time t = T. Figure 2.18(d) shows the equivalent circuit for time interval (D + D1 )T < t ≤ T. The voltage across the inductor is zero because its current is constant and equals zero. At time t = T, the switch is turned on and the inductor current increases from zero. 2.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is on and the diode is off. The equivalent circuit is shown in Figure 2.18(b). The switch voltage vS and the diode current iD are zero. The voltage across the inductor L is vL = V I − V O = L diL , dt iL (0) = 0. (2.213) Hence, the current through the inductor and switch is t iS = iL = t V − VO 1 1 t. v dt = (V − VO )dt = I L ∫0 L L ∫0 I L (2.214) Buck PWM DC–DC Converter vGS 0 T DT t vL VI VO A+ 0 A− DT VO T t iL Δ iL VI VO VO L L DT D1T IO 0 D2T T t DT T t DT T t DT T t iS ISM IS 0 vS VI VI VO 0 iD IDM ID 0 vD 0 VO DT T t VI Figure 2.19 Idealized current and voltage waveforms in the PWM buck converter for DCM. 57 58 Pulse-Width Modulated DC–DC Power Converters Thus, the peak current through the switch and inductor is ISM = ΔiL = iL (DT) = (V − VO )D (VI − VO )DT = I . L fs L (2.215) The voltage across the diode is vD = −VI . (2.216) The end of this time interval occurs when the switch is turned off by the driver. 2.3.2 Time Interval: DT < t ≤ (D + D1 )T The equivalent circuit for this time interval is shown in Figure 2.18(c). The switch is off and the diode is on. Hence, iS = 0 and vD = 0. The voltage across the inductor L is vL = −VO = L diL dt (2.217) and the inductor and diode currents are obtained using (2.215) t iD = iL = =− t 1 1 v dt + iL (DT) = (−VO )dt + iL (DT) L ∫DT L L ∫DT VO V (V − VO )DT (t − DT) + iL (DT) = − O (t − DT) + I . L L L (2.218) These currents can also be derived as iD = iL = =− t t V 1 1 vL dt = (−VO )dt = − O [t − (D + D1 )T] ∫ ∫ L (D+D1 )T L (D+D1 )T L V D T V VO (t − DT) + O 1 = − O (t − DT) + iL (DT). L L L (2.219) Hence, the diode and inductor peak currents are found as IDM = ΔiL = iL (DT) = D1 VO fs L (2.220) or DT IDM = ΔiL = DT V D V D T 1 1 v dt = (−VO )dt = O 1 = O 1 . L ∫(D+D1 )T L L ∫(D+D1 )T L fs L (2.221) The peak voltage across the switch is VSM = VI . (2.222) This time interval ends when the diode current reaches zero. 2.3.3 Time Interval: (D + D1 )T < t ≤ T During this time interval, both the switch and the diode are off. The equivalent circuit is shown in Figure 2.18(d). The inductor current iL , the inductor voltage vL , the switch current iS , and the diode current iD are zero. The voltage across the switch is vS = V I − V O (2.223) Buck PWM DC–DC Converter 59 and the voltage across the diode is vD = −VO . (2.224) This time interval ends when the switch is turned on by the driver. 2.3.4 Device Stresses for DCM Using (2.7) and (2.15), one obtains the voltage stress of the switch and the diode in DCM for steady-state operation VSMmax = VDMmax = VImax . (2.225) From (2.215), the current stress of the switch and the diode in DCM for steady-state operation is ISMmax = IDMmax = ΔiLmax = (VImax − VO )Dmin . fs L (2.226) 2.3.5 DC Voltage Transfer Function for DCM Referring to Figure 2.19 and using the volt-second balance principle, A+ = A− . Hence, (VI − VO )DT = VO D1 T (2.227) VO D = . VI D + D1 (2.228) which leads to MV DC = From (2.215) and (2.228), the peak-to-peak value of the inductor current is ΔiL = V D(1 − MV DC ) (VI − VO )DT = O . L fs LMV DC (2.229) The dc output current is equal to the average value of the inductor current IO = T V D(D + D1 )(1 − MV DC ) (D + D1 )ΔiL 1 = O iL dt = . T ∫0 2 2fs LMV DC (2.230) Substitution of (2.228) into (2.230) yields IO = VO D2 (1 − MV DC ) 2fs LMV2 DC which can be rearranged to the form √ √ 2fs LMV2 DC IO 2fs LMV2 DC D= = (1 − MV DC )VO RL (1 − MV DC ) VO RL = D≤1− for (2.231) 2fs L 2f LI = 1− s O. RL VO (2.232) Thus, the duty cycle D increases with increasing IO when VO and MV DC (or VI ) are held constant. The inductance required to obtain a desired dc voltage transfer function at given values of D, RL , and fs is L= D2 RL (1 − MV DC ) 2fs MV2 DC . (2.233) At the boundary between CCM and DCM, MV DCB = DB (2.234) 60 Pulse-Width Modulated DC–DC Power Converters 1 MVDC = 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 D CCM 0.5 DCM 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0.2 0.4 0.6 IO /(VO /2fsL) 0.8 1 Figure 2.20 Duty cycle D as a function of the normalized load current IO ∕(VO ∕2fs L) at various values of MV DC for the lossless buck converter. as in CCM. Substitution of this into (2.232) yields the duty cycle DB at the boundary MV DCB = DB = 1 − 2fs L 2f LI = 1− s O. RL VO (2.235) As the normalized load current IO ∕(VO ∕2fs L) is increased from 0 to 1, the boundary duty cycle DB decreases from 1 to 0. At D close to 1, the converter operates in CCM practically at any load. At D close to zero, there is a large load range in which the converter operates in DCM. Figures 2.20 and 2.21 show plots of D versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of MV DC for both CCM and DCM for the lossless buck converter, respectively. Rearranging (2.232), one obtains 2fs L 2 M + MV DC − 1 = 0. D2 RL V DC (2.236) Solving this equation for MV DC gives MV DC = 2 2 = √ √ 8f LI 8fs L 1 + 1 + Ds2 V O 1 + 1 + D2 R L for MV DC ≤ 1 − 2fs L 2f LI = 1− s O. RL VO (2.237) O The dc voltage transfer function depends on the load resistance RL for DCM. Figures 2.22 and 2.23 display MV DC versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of D for both CCM and DCM for the lossless buck converter, respectively. Buck PWM DC–DC Converter 61 1 0.9 MVDC = 0.9 0.7 0.7 0.6 0.6 D CCM 0.8 0.8 DCM 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 10 1 2 10 RL/(2fsL) 10 Figure 2.21 Duty cycle D as a function of the normalized load resistance RL ∕(2fs L) at various values of MV DC for the lossless buck converter. 1 D = 0.9 0.9 0.8 0.8 CCM 0.7 0.7 0.6 MVDC 0.6 0.5 0.5 0.4 0.4 DCM 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0.2 0.4 0.6 IO /(VO /2fsL) 0.8 1 Figure 2.22 DC voltage transfer function MV DC as a function of the normalized load current IO ∕(VO ∕2fs L) at fixed values of D for the lossless buck converter. 62 Pulse-Width Modulated DC–DC Power Converters 1 0.9 D = 0.9 0.7 0.7 0.6 MVDC 0.6 0.5 0.4 0.3 CCM 0.8 0.8 0.5 DCM 0.4 0.3 0.2 0.2 0.1 0.1 0 0 10 1 2 10 RL/(2fsL) 10 Figure 2.23 DC voltage transfer function MV DC as a function of the normalized load resistance RL ∕(2fs L) at fixed values of D for the lossless buck converter. Using (2.228) and (2.237), D1 can be expressed in terms of D, RL , fs , and L as (√ ) ( ) 8fs L D 1 1+ 2 −1 . −1 = D1 = D MV DC 2 D RL (2.238) It can be seen that D1 depends on D, RL , L, and fs . 2.3.6 Maximum Inductance for DCM Figure 2.24 shows the waveforms of the inductor current at the boundary between DCM and CCM for VI = VImin and VI = VImax . Using (2.39), the minimum value of the inductor peak current at the boundary between DCM and CCM is − VO (DBmax ) VO (1 − DBmax ) V = . (2.239) ΔiLmin = Imax fs Lmax fs Lmax iL VImax VO L VImin VO L ΔiLmin IOB 0 Figure 2.24 DminT DmaxT T VO L t Waveforms of the inductor current at the boundary between DCM and CCM for VI = VImin and VI = VImax . Buck PWM DC–DC Converter 63 Therefore, the dc output current at the boundary can be expressed as IOB = IOmax = V (1 − DBmax ) V ΔiLmin = O = O 2 2fs Lmax RLmin (2.240) which yields Lmax = RLmin (1 − DBmax ) 2fs (2.241) where DBmax is the maximum duty cycle at the boundary between the CCM and DCM modes for the lossy buck converter and is given by DBmax = VO MV DCmax = . 𝜂 𝜂VImin (2.242) The dwell-duty cycle is Dw = 1 − Dmax − D1min = 1 − Dmin − D1max = 1 − Dmax − √ = 1− Dmax MV DCmax + Dmax = 1 − 2fs Lmax . 𝜂RLmin (1 − MV DCmax ) Dmax MV DCmax (2.243) Hence, the maximum inductance for a given dwell-duty cycle is Lmax = 𝜂RLmin (1 − MV DCmax )(1 − Dw )2 . 2fs (2.244) For example, for RLmin = 1.2 Ω, MV DCmax = 0.5, fs = 100 kHz, 𝜂 = 0.9, and Dw = 0.05, we get Lmax = 2.4368 𝜇H. The filter capacitor can be designed using the same approach as that for CCM. The maximum ripple voltage occurs at full power, for which the inductor waveform is close to that of the boundary between the DCM and CCM. 2.3.7 Power Losses and Efficiency of Buck Converter for DCM Substitution of (2.228) into (2.229) yields the inductor, switch, and diode peak current √ ( ) 2(1 − MV DC ) DVO 1 ΔiL = ISM = IDM = − 1 = VO . fs L MV DC fs LRL Using this expression, one obtains the rms value of the switch current √ √ √ √ √ √ DT 2MV2 DC (1 − MV DC ) √ 1 D 2 = VO ISrms = i2S dt = ΔiL T ∫0 3 3RL fs LRL and the conduction loss in the MOSFET 2 PrDS = rDS ISrms = rDS DΔi2L 3 √ 2r = DS 3 2MV2 DC (1 − MV DC ) fs LRL PO . (2.245) (2.246) (2.247) The switching loss is Psw = fs Co VI2 = fs Co VO2 MV2 DC fC R = s 2o L PO . MV DC (2.248) 64 Pulse-Width Modulated DC–DC Power Converters The total power loss in the MOSFET is ⎡ 2r P PFET = PrDS + sw = ⎢ DS ⎢ 3 2 ⎣ √ 2MV2 DC (1 − MV DC ) fs LRL + fs Co RL ⎤⎥ PO . 2MV2 DC ⎥ ⎦ Using (2.238) and (2.245), one arrives at the rms value of the diode current √ √ √ √ √ √ (D+D1 )T 2(1 − MV DC )3 D √ 1 2 1 IDrms = = VO i2D dt = ΔiL T ∫DT 3 3RL fs LRL which gives the diode conduction loss due to RF 2 PRF = RF IDrms = D1 RF Δi2L 3 (2.249) (2.250) √ 2(1 − MV DC )3 PO . fs LRL 2RF = 3 Using (2.218), (2.230), (2.238), and (2.245), one obtains the average diode current ( )2 T D2 VO 1 1 ID = i dt = − 1 = IO (1 − MV DC ) T ∫0 D 2fs L MV DC (2.251) (2.252) resulting in the diode conduction loss due to VF PVF = VF ID = VF IO (1 − MV DC ) = VF (1 − MV DC ) PO . VO Hence, the overall diode conduction loss is ⎡ V (1 − M 2R V DC ) PD = PVF + PRF = ⎢ F + F ⎢ VO 3 ⎣ √ 2(1 − MV DC )3 ⎤⎥ P . ⎥ O fs LRL ⎦ Using (2.238) and (2.245), one obtains the rms value of the inductor current √ √ √ √ √ √ √ (D+D1 )T 1 − D 2(1 − MV DC ) D + D 1 2 √ w 1 ILrms = i2L dt = ΔiL = ΔiL = VO T ∫0 3 3 3RL fs LRL which leads to the power loss in the inductor ESR 2 = PrL = rL ILrms rL Δi2L (D + D1 ) 3 = rL Δi2L (1 − Dw ) 3 (2.253) (2.254) (2.255) √ 2r = L 3 2(1 − MV DC ) PO . fs LRL (2.256) Neglecting the power loss in the ESR of the filter capacitor, the total converter power loss is given by √ √ 2 ⎡ 2r 2M (1 − M ) f C R 2(1 − MV DC )3 2R V DC V DC + s 2o L + F PLS = PrDS + Psw + PD + PrL = ⎢ DS ⎢ 3 fs LRL 3 fs LRL MV DC ⎣ √ ] VF (1 − MV DC ) 2rL 2(1 − MV DC ) + + (2.257) PO . VO 3 fs LRL The efficiency of the buck converter in DCM is defined as 𝜂≡ PO PO 1 = = P PI PO + PLS 1 + LS PO (2.258) Buck PWM DC–DC Converter 65 which gives √ √ [ 2rDS 2MV2 DC (1 − MV DC ) fs Co RL 2RF 2(1 − MV DC )3 VF (1 − MV DC ) 𝜂 = 1+ + 2 + + 3 fs LRL 3 fs LRL VO MV DC √ ]−1 2rL 2(1 − MV DC ) + . 3 fs LRL (2.259) The dc input current of the converter is described by II = 1 T ∫0 DT iS dt = 1 T ∫0 yielding the dc input power 2 PI = VI II = D VI (VI − VO ) = 2fs L DT D2 (VI − VO ) (VI − VO )t dt = L 2fs L ( ) V D2 VI2 1 − VO I 2fs L = ( ) D2 VI2 1 − MV DC 2fs L (2.260) . (2.261) The dc output power is PO = VO2 RL . (2.262) Hence, the efficiency of the buck converter operating in DCM is given by 𝜂= 2fs LMV2 DC 2fs LVO2 PO = = . PI D2 VI2 (1 − MV DC ) D2 RL (1 − MV DC ) (2.263) The duty cycle √ D= 2fs LMV2 DC IO 𝜂VO (1 − MV DC ) √ = 2fs LMV2 DC 𝜂RL (1 − MV DC ) for D<1− 2fs L 2f LI =1− s O RL VO (2.264) 2fs L 2f LI = 1− s O. RL VO (2.265) and the dc voltage transfer function of the lossy buck converter for DCM MV DC = 2 2 = √ √ 8f LI 8fs L 1 + 1 + 𝜂Ds2 VO 1 + 1 + 𝜂D2 R L for D<1− O At the boundary between DCM and CCM, D = D1 = 0.5, and ΔiL ∕IO = 2. Hence, the power loss in the inductor winding is given by [ )2 ] ( ( ) 1 1 ΔiL 2 PrL = rL ILrms = rL 1 + (2.266) = PO 1 + × 22 = 2.3333PO . 3 IO 3 2.3.8 Design of Buck Converter for DCM Design a PWM buck converter to meet the following specifications: POmin = 0, POmax = 120 W, VO = 12 V, VImin = 24 V, VInom = 28 V, VImax = 32 V, fs = 100 kHz, and Vr ∕VO ≤ 6%. The maximum load current is P 120 IOmax = Omax = = 10 A (2.267) VO 12 66 Pulse-Width Modulated DC–DC Power Converters and the minimum load resistance is VO 12 = = 1.2 Ω. IOmax 10 (2.268) MV DCmin = VO 12 = 0.375 = VImax 32 (2.269) MV DCnom = VO 12 = 0.4286 = VInom 28 (2.270) VO 12 = 0.5. = VImin 24 (2.271) RLmin = The dc voltage transfer functions are and MV DCmax = Let us assume 𝜂 = 0.9. The maximum duty cycle at the boundary between CCM and DCM at full load RLmin = 1.2 Ω occurs at VImin = 24 V DBmax = MV DCmax VO 12 = = = 0.5556 𝜂 𝜂VImin 0.9 × 24 (2.272) resulting in the maximum inductance required for DCM operation Lmax = RLmin (1 − DBmax ) 1.2 × (1 − 0.5556) = = 2.6665 𝜇H. 2fs 2 × 100 × 103 Pick L = 2.4 𝜇H. The maximum duty cycle at RLmin = 1.2 Ω, VImin = 24 V, and L = 2.4 𝜇H is √ √ 2fs LMV2 DCmax 2 × 100 × 103 × 2.4 × 10−6 × 0.52 Dmax = = = 0.4714 𝜂RLmin (1 − MV DCmax ) 0.9 × 1.2 × (1 − 0.5) ( D1min = Dmax 1 MV DCmax ) −1 ( = 0.4714 × ) 1 − 1 = 0.4714 0.5 (2.273) (2.274) (2.275) and Dmax + D1min = 0.4714 + 0.4714 = 0.9428 < 1. The nominal duty cycle at RLmin = 1.2 Ω and VInom = 28 V is √ √ 2fs LMV2 DCnom 2 × 100 × 103 × 2.4 × 10−6 × 0.42862 Dnom = = = 0.378 𝜂RLmin (1 − MV DCnom ) 0.9 × 1.2 × (1 − 0.4286) ( D1nom = Dnom 1 MV DCnom ) −1 ( = 0.378 × ) 1 − 1 = 0.5039 0.4286 (2.276) (2.277) (2.278) and Dnom + D1nom = 0.378 + 0.5039 = 0.8819 < 1. (2.279) Buck PWM DC–DC Converter The minimum duty cycle at RLmin = 1.2 Ω and VImax = 32 V is √ √ 2fs LMV2 DCmin 2 × 100 × 103 × 2.4 × 10−6 × 0.3752 Dmin = = = 0.3162 𝜂RLmin (1 − MV DCmin ) 0.9 × 1.2 × (1 − 0.375) ( D1max = Dmin ) 1 MV DCmin −1 ( = 0.3162 × ) 1 − 1 = 0.527 0.375 67 (2.280) (2.281) and Dmin + D1max = 0.3162 + 0.527 = 0.8432 < 1. (2.282) The maximum peak switch, diode, and inductor current occurs at RLmin = 1.2 Ω and VImax = 32 V and is found as ISMmax = IDMmax = ΔiLmax = Dmin (VImax − VO ) 0.3162 × (32 − 12) = = 26.35 A. fs L 100 × 103 × 2.4 × 10−6 (2.283) The maximum switch and diode voltage stress is VSMmax = VDMmax = VImax = 32 V. (2.284) Let us choose an IRF150 power MOSFET with VDSS = 100 V, ISM = 40 A, rDS = 0.055 Ω, Co = 100 pF, and Qg = 63 nC. In addition, we select an MBR4040 Schottky diode with VDM = 40 V, IDM = 40 A, VF = 0.4 V, and RF = 25 mΩ. The ripple voltage is Vr = 0.06VO = 0.06 × 12 = 720 mV. (2.285) Vr 720 = = 27.32 mΩ. ΔiLmax 26.35 (2.286) The minimum filter capacitor ESR is rCmax = Pick rC = 25 mΩ. The minimum filter capacitance is Cmin = 1 1 = = 200 𝜇F. 2rC fs 2 × 0.025 × 100 × 103 (2.287) Pick C = 220 𝜇F/25 V/25 mΩ. Let us estimate the power losses in various components at RLmin = 1.2 Ω and VImin = 24 V. The conduction power loss in the MOSFET is √ √ 2rDS 2MV2 DCmax (1 − MV DCmax ) 2 × 0.52 × (1 − 0.5) 2 × 0.055 × 120 = 4.1 W. PrDS = POmax = 3 fs LRLmin 3 100 × 103 × 2.4 × 10−6 × 1.2 (2.288) The switching loss is 2 Psw = fs Co VImin = 100 × 103 × 100 × 10−12 × 242 = 0.006 W. (2.289) Hence, the total power loss in the MOSFET is PFET = PrDS + Psw = 4.1 + 0.003 = 4.103 W. 2 (2.290) 68 Pulse-Width Modulated DC–DC Power Converters The diode conduction loss due to RF is √ √ 2RF 2(1 − MV DCmax )3 2 × (1 − 0.5)3 2 × 0.025 × 120 = 1.864 W. (2.291) PRF = POmax = 3 fs LRLmin 3 100 × 103 × 2.4 × 10−6 × 1.2 The power loss in the diode due to VF is PVF = VF IOmax (1 − MV DCmax ) = 0.4 × 10 × (1 − 0.5) = 2 W. (2.292) Hence, the overall diode conduction loss is PD = PRF + PVF = 1.864 + 2 = 3.864 W. Assuming rL = 0.05 Ω, the power loss in the inductor ESR is √ √ 2rL 2(1 − MV DCmax ) 2 × (1 − 0.5) 2 × 0.05 PrL = POmax = × 120 = 7.454 W. 3 fs LRLmin 3 100 × 103 × 2.4 × 10−6 × 1.2 (2.293) (2.294) The total power loss is PLS = PrDS + Psw + PD + PrL = 4.1 + 0.006 + 3.864 + 7.454 = 15.424 W (2.295) resulting in the converter efficiency 𝜂= PO 120 = 88.61%. = PO + PLS 120 + 15.424 (2.296) Assuming the gate-to-source peak-to-peak voltage VGSm = 8 V, the MOSFET gate-drive power is PG = fs Qg VGSm = 100 × 103 × 63 × 10−9 × 8 = 50.4 mW. (2.297) The converter efficiency 𝜂 can be computed from (2.258) and the duty cycle D from (2.264). Figures 2.25 and 2.26 depict plots of the converter efficiency 𝜂 and the duty cycle D as functions of the DC input voltage VI at fixed load resistances RL , respectively, at rDS = 55 mΩ, RF = 25 mΩ, VF = 0.4 V, rL = 50 mΩ, rC = 25 mΩ, L = 2.4 𝜇H, Co = 100 pF, and fs = 100 kHz. It can be seen that the efficiency 𝜂 decreases as the input voltage VI increases. Figures 2.27 through 2.30 show plots of the converter efficiency 𝜂 and duty cycle D versus the load current IO and the load resistance RL for DCM at fixed values of the dc input voltage VI . The efficiency decreases with respect to IO and increases with respect to RL . 2.4 Buck Converter with Input Filter The disadvantage of the buck converter topology shown in Figure 2.1(a) is discontinuous and pulsating input current waveform because the switch is connected in series with the input voltage source. The input current flows when the switch is closed and is abruptly interrupted when the switch is opened. In order to obtain a continuous input current, a second-order L1 -C1 low-pass filter can be added at the input of the converter, as depicted in Figure 2.31. 2.5 Buck Converter with Synchronous Rectifier A buck converter topology with a synchronous rectifier is shown in Figure 2.32(a). This circuit is obtained by replacing the diode with an n-channel MOSFET. In general, diodes have an offset voltage VF and may be comparable to the output voltage in low-voltage applications. In contrast, MOSFETs do not have an offset voltage. If the on-resistance of a MOSFET is low, the forward voltage drop across the MOSFET is very low, reducing the conduction loss and yielding high efficiency. Some low-breakdown voltage MOSFETs have the on-resistance rDS Buck PWM DC–DC Converter 69 95 R = 12 Ω L 94 93 η (%) 92 RL = 2.4 Ω 91 90 89 RL = 1.2 Ω 88 87 24 25 26 27 28 VI (V) 29 30 31 32 Figure 2.25 Efficiency 𝜂 as a function of the DC input voltage VI for the buck converter given in the design example for DCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. 0.5 0.45 0.4 RL = 1.2 Ω D 0.35 0.3 RL = 2.4 Ω 0.25 0.2 0.15 0.1 24 RL = 12 Ω 25 26 27 28 VI (V) 29 30 31 32 Figure 2.26 Duty cycle D as a function of the dc input voltage VI for the buck converter given in the design example for DCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. 70 Pulse-Width Modulated DC–DC Power Converters 97 96 95 94 η (%) 93 92 91 V = 24 V I 90 V I = 28 V 89 V = 32 V I 88 87 Figure 2.27 32 V. 0 1 2 3 4 5 IO (A) 6 7 8 9 10 Efficiency 𝜂 of the buck converter as a function of the load current IO for DCM at VI = 24 V, 28 V, and 0.5 0.45 V = 24 V I 0.4 0.35 V I = 28 V V = 32 V I D 0.3 0.25 0.2 0.15 0.1 0.05 0 Figure 2.28 32 V. 0 1 2 3 4 5 IO (A) 6 7 8 9 10 Duty cycle D of the buck converter as a function of the load current IO for DCM at VI = 24 V, 28 V, and Buck PWM DC–DC Converter 71 95 V I = 24 V 94 V = 32 V I 93 V I = 28 V η (%) 92 91 90 89 88 87 Figure 2.29 32 V. 1 2 3 4 5 6 7 RL (Ω) 8 9 10 11 12 Efficiency 𝜂 of the buck converter as a function of load resistance RL for DCM at VI = 24 V, 28 V, and 0.5 0.45 0.4 D 0.35 0.3 0.25 V I = 24 V 0.2 V I = 28 V 0.15 0.1 Figure 2.30 32 V. V I = 32 V 1 2 3 4 5 6 7 RL (Ω) 8 9 10 11 12 Duty cycle D of the buck converter as a function of load resistance RL for DCM at VI = 24 V, 28 V, and 72 Pulse-Width Modulated DC–DC Power Converters L1 VI Figure 2.31 L2 C1 vGS + C2 RL + VO Buck converter with an input L1 -C1 low-pass filter. as low as 6 mΩ. In addition, operation in DCM can be avoided because the channel of the transistor can conduct current in both directions. The synchronous buck converter operates in CCM from no load to full load. The two MOSFETs are driven in a complimentary manner. The low side n-channel MOSFET replaces a Schottky diode and operates in the third quadrant because the current normally flows from source to drain. When both the transistors are n-channel MOSFETs, it is difficult to drive the upper MOSFET because both the gate and the source are connected to “hot” points. One solution is to use a transformer with one primary winding and two secondary windings. The primary winding is connected to a driver, for example, an integrated circuit (IC) driver. One transformer output is noninverting and the other transformer output is inverting. The synchronous buck converter suffers from cross-conduction (or shoot-through) effect, resulting in high current spikes in both transistors. This produces high losses and reduces the efficiency. A nonoverlapping driver can produce a dead time and reduce the cross-conduction loss. During the dead time periods, the inductor current flows through the lower MOSFET body diode. This body diode has a very slow reverse recovery characteristic that can adversely affect the converter efficiency. An external Schottky diode can be connected in parallel with the low-side MOSFET to shunt the body diode and to prevent it from affecting the converter performance. The added Schottky diode can have a much lower L VI C RL + VO C RL + VO (a) L VI (b) Figure 2.32 Buck converter with a synchronous rectifier. (a) With two n-channel MOSFETs. (b) CMOS buck converter. Buck PWM DC–DC Converter 73 L VI C Figure 2.33 R + VO Synchronous buck converter with a transformer driver. current rating than the diode in the conventional nonsynchronous buck converter because it only conducts during the small dead time when both MOSFETs are off. If the upper MOSFET is a PMOS and the lower MOSFET is an NMOS, then the circuit is similar to a digital CMOS inverter, as shown in Figure 2.32(b). In this case, both transistors can be driven by the same gate-to-source voltage. The peak-to-peak gate-to-source voltage should be equal or close to the dc input voltage VI . Therefore, the CMOS buck synchronous converter is a good topology for applications with a low dc voltage VI . The whole converter can be integrated, except for the filter capacitor C. The PMOS transistor has larger capacitances because it must have larger area due to lower mobility of holes. At a high voltage VI , the peak-to-peak gate-to-source voltage is high and may break the MOSFET gate. The same gate-to-drive voltage may cause cross-conduction of both transistors, generating high spikes and drastically reducing the converter efficiency. A dead time will reduce the current spikes, but this requires two nonoverlapping gate-to-source voltages to drive the MOSFETs. The synchronous buck converter is especially attractive in power supplies with a very low output voltage (e.g., VO = 3.3 V or VO = 1 V) and/or a wide load range, including operation from no-load to full-load. Its main advantage is higher efficiency than that of the conventional buck converter. The synchronous buck converter may be used as a bidirectional converter. Figure 2.33 shows a synchronous buck converter with a transformer driver. If both MOSFETs are n-channel devices, then the upper output of the transformer should be noninverting and the other should be inverting. If the upper transistor is a PMOS and the bottom transistor is an NMOS, then both transformer outputs should be noninverting or inverting. Figure 2.34 shows a synchronous buck converter with a voltage mirror driver. The voltage mirror driver acts as a voltage shifter for the ac voltage waveform so that the gate-to-source voltage of the n-channel MOSFET is the same as the source-to-gate voltage of the p-channel MOSFET. Unlike in the CMOS synchronous buck converter, the peak-to-peak voltage of the gate-to-source voltage can be lower than the dc input voltage VI . Therefore, this driver is good for applications with high values of VI . L VI Cb C Figure 2.34 R + VO Synchronous buck converter with a voltage mirror driver. 74 Pulse-Width Modulated DC–DC Power Converters The minimum inductance for the synchronous converter is limited only by the inductor current. For CCM, the maximum inductor current ripple is VO (1 − Dmin ) . fs Lmin (2.298) VO (1 − Dmin ) (1 − Dmin )RLmin = . fs ΔiLmax fs ΔiLmax ∕IOmax (2.299) ΔiLmax = Hence, the minimum inductance is given by Lmin = The choice between synchronous rectification and Schottky diode rectification is as follows. Synchronous rectifiers should be used for VO ≤ 2 V, fs ≤ 300 kHz, and 10 A ≤ IO ≤ 100 A. Schottky diodes should be used for VO > 5 V and fs > 1 MHz, IO < 10 A, and IO > 100 A. The efficiency of the buck converter with synchronous rectifier is 𝜂= PO = PI 1 , [ ( )2 ] Dr +(1−D)r +r 2fs Co RL rC RL (1−D)2 ΔiL 1 + 1 + DS1 R DS2 L 1 + 12 + I M2 12f 2 L2 L O (2.300) s V DC where ΔiL = VO (1 − D)∕(fs L) = D(1 − D)VI ∕(fs L) and ΔiL ∕IO = RL (1 − D)∕(fs L) = RL (1 − VO ∕VI )∕fs L = (1 − VO ∕VI )VO ∕(fs LIO ). If rDS1 = rDS2 , the converter efficiency becomes 𝜂= 1 1 = [ [ ( )2 ] ( )2 ] 2 r +r 2f C R r RL (1−D) (r +r )I 2f C V r V (1−D)2 ΔiL ΔiL 1 1 + Ms 2 o L + C 12f + I (Vs o∕VO)2 + C12fO2 L2 I 1 + DSR L 1 + 12 1 + DS V L O 1 + 12 2 L2 I I L = (r +r )P 1 + DS V 2L O O O O s V DC O O O I s O 1 1 = . [ [ ( )2 ] ( )2 ] 2fs Co VO2 rC VO2 (1−D)2 rDS +rL 2f C R r RL (1−D)2 1 ΔiL RL 1 ΔiL RL 1 + 12 V + P (V ∕V )2 + 12f 2 L2 P 1 + 12 DV + sDo2 L + C 12f 1+ R 2 L2 O O O I O s L I s (2.301) Figures 2.35, 2.36, and 2.37 show the efficiency 𝜂 of the buck converter with synchronous rectifier as functions of the load current IO , the load resistance RL , and the output power PO , respectively, at VO = 12 V, VI = 28 V, rDS = 55 mΩ, rL = rC = 50 mΩ, D = 0.506, MV DC = 0.43, fs = 100 kHz, and Co = 100 pF. The inductor current ripple is ΔiL = VO (1 − D)∕(fs L) = 12 × (1 − 0.506)∕(105 × 40 × 10−6 ) = 1.482 A. It can be observed that the converter efficiency 𝜂 decreases for low values of load current IO ≤ 0.2 A, which corresponds to large values of load resistance RL ≥ 60 Ω and low values of output power PO ≤ 24 mW. The dc voltage transfer function is MV DC = VO = 𝜂D = VI D [ ( )2 ] r +r 2f C R r RL (1−D)2 ΔiL 1 + Ms 2 o L + C 12f 1 + DSR L 1 + 12 2 L2 I L = (r +r )I 1 + DS V L O O 1+ O (rDS +rL )PO VO2 1 1 + 12 [ ( = r +r 1 + DSR L L s V DC D [ ( )2 ] 2f C V r V (1−D)2 ΔiL 1 1 + 12 I + I (Vs o∕VO)2 + C12fO2 L2 I [ = O 1 1 + 12 ( O D )2 ] ΔiL PO VO I O s 2f C V 2 r V 2 (1−D)2 + P (Vs o∕VO )2 + C12fO2 L2 P O D )2 ] ΔiL RL DVI O O I s . + 2fs Co RL r RL (1−D)2 + C 12f 2 2 D2 s L O (2.302) Buck PWM DC–DC Converter 75 100 98 96 94 η (%) 92 90 88 86 84 82 80 0 2 4 6 IO (A) 8 10 12 Figure 2.35 Efficiency 𝜂 of the buck converter with synchronous rectifier as a function of the load current IO at VI = 28 V and VO = 12 V. 100 90 80 70 η (%) 60 50 40 30 20 10 0 0 10 1 10 2 10 3 RL (Ω) 10 4 10 5 10 Figure 2.36 Efficiency 𝜂 of the buck converter with synchronous rectifier as a function of the load resistance RL at VI = 28 V and VO = 12 V. 76 Pulse-Width Modulated DC–DC Power Converters 100 99 98 η (%) 97 96 95 94 93 92 91 0 20 40 60 PO (W) 80 100 120 Figure 2.37 Efficiency 𝜂 of the buck converter with synchronous rectifier as a function of the output power PO at VI = 28 V and VO = 12 V. Figures 2.38 and 2.39 show the efficiency 𝜂 of the buck converter with synchronous rectifier and the voltage transfer function MV DC as functions of the duty cycle D at the load resistance RL = 1.2 Ω, respectively, at VI = 28 V, rDS = 55 mΩ, rL = rC = 50 mΩ, fs = 100 kHz, and Co = 100 pF. 2.6 Buck Converter with Positive Common Rail Figure 2.40 shows the derivation of a buck converter topology, in which the positive potential of both the input and output voltages is common and can be connected to the ground. The classical buck converter with a negative common rail is depicted in Figure 2.40(a). Figure 2.40(b) shows the converter circuit with the MOSFET and the inductor moved to the common rail of Figure 2.40(a). The resulting positive bus is now the common rail. Figure 2.40(c) shows the circuit of Figure 2.40(b) flipped so that the positive rail is at the bottom. Gate-Drive with Respect to Ground. One of the disadvantages of the buck converter shown in Figure 2.1(a) is the difficulty of driving the transistor because neither the gate nor the source is connected to the ground. Figure 2.41 shows a topology of the buck converter, in which the gate is referenced to ground, but the output of the converter is not grounded. This topology may be useful in some preliminary laboratory tests of the converter because a simple driver may be used. It can also be used in applications, where the load is not connected to ground, for example, a bulb or an LED with variable brightness. Figure 2.42 shows a topology of the buck converter, in which both the source of the MOSFET and the output of the converter are connected to ground, but it requires a floating power supply. 2.7 Quadratic Buck Converter In order to increase the range of the conversion ratio, two buck converters can be cascaded. However, this circuit requires twice as many components as a single-stage buck converter, which increases the size, weight, Buck PWM DC–DC Converter 77 100 90 80 70 η (%) 60 50 40 30 20 10 0 0 0.2 0.4 D 0.6 0.8 1 Figure 2.38 Efficiency 𝜂 of the buck converter with synchronous rectifier as a function of duty cycle D at fixed RL = 1.2 Ω and VI = 28 V. 1 0.9 0.8 0.7 MVDC 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 D 0.6 0.8 1 Figure 2.39 DC voltage transfer function MV DC of the buck converter with synchronous rectifier as a function of duty cycle D at fixed RL = 1.2 Ω and VI = 28 V. 78 Pulse-Width Modulated DC–DC Power Converters L + VI C RL + VO C RL + VO C RL (a) + VI L (b) L VI + VO + (c) Figure 2.40 Derivation of the buck converter topology with the positive common rail. (a) Classical buck converter with a negative common rail. (b) Buck converter with the MOSFET and the inductor moved to the negative branch, resulting in the positive common rail. (c) Buck converter with a positive common rail. and cost. A quadratic buck converter [25–28] is shown in Figure 2.43. The dc voltage transfer function of this converter is MV DC = VO = 𝜂D2 . VI (2.303) The quadratic buck converter contains only one transistor. L C RL + VO VI + vGS Figure 2.41 Topology of the buck converter with the gate referenced to ground and floating output voltage. Buck PWM DC–DC Converter VI 79 L C + vGS RL VO + Figure 2.42 Topology of the buck converter in which both the MOSFET source and the converter output are grounded, but this topology requires a floating power supply. 2.8 Tapped-Inductor Buck Converters The simplest method of extending the range of the dc voltage transfer function MV DC is by replacing the inductor L with a tapped inductor in the basic dc–dc converters. The turns ratio n of the tapped inductor is present in MV DC . It permits to adjust the duty cycle value to achieve high efficiency. Very low and very high values of the duty cycle can be avoided. Also, the utilization of the switching devices cp and passive devices can be improved. Tapped-inductor buck converters are shown in Figure 2.44. These circuits are high step-down converters. The tapped inductor acts as a transformer and its magnetizing inductance acts as an output filter inductor. A magnetic core with an air gap can be used to build the tapped inductor. The tapped inductor may store magnetic energy. 2.8.1 Tapped-Inductor Common-Diode Buck Converter Consider the common-diode (CD) tapped-inductor buck converter shown in Figure 2.44(a). The voltage transfer function of the tapped inductor is n= Np + Ns Np v = = + 1. vs Ns Ns (2.304) When the MOSFET is on and the diode is off, VI − VO = v = nvs (2.305) producing the voltage across the Ns winding vs = VI − VO . n (2.306) When the MOSFET is off and the diode is on, vs = V O . (2.307) L2 L1 VI D1 C1 D2 Figure 2.43 D3 C2 RL Quadratic buck converter. + VO 80 Pulse-Width Modulated DC–DC Power Converters Np v + + vp VI Ns + vs RL C + VO (a) Ns vs + v vp + VI C RL + VO C RL + VO + Np (b) + Np vs + Ns v p VI + v (c) Figure 2.44 Tapped-inductor buck converters. (a) Tapped-inductor common-diode buck converter. (b) Tappedinductor common-switch buck converter. (c) Watkins–Johnson (common-source) converter. Using the volt-second balance for the Ns winding, we obtain the dc voltage transfer function for the common-diode converter operating in CCM MV DC = VO D . = VI D + n(1 − D) (2.308) The dc voltage transfer function MV DC versus D for CCM is illustrated in Figure 2.45. The current and voltage stresses are ) ( M 1 − MV DC ISM1 = V DC IO = MV DC + IO (2.309) D n ( VSM1 = VI + (n − 1)VO = 1 MV DC ) + n − 1 VO ) ( VI − VO 1 n + VO = 1 + − VO . n M n The magnetizing inductance on the terminals of winding Ns is )2 ( Ls L Lm = Lp + Ls VSM2 = where L = Lp + Ls is the total winding inductance. (2.310) (2.311) (2.312) Buck PWM DC–DC Converter 81 1 0.8 n=1 0.6 MVDC 2 0.4 5 10 0.2 0 Figure 2.45 0 0.25 0.5 D 0.75 1 DC voltage transfer function of common-diode tapped-inductor buck converter for CCM. The circuit has several advantages, such as high voltage conversion ratio, low switch current stress, and low diode voltage stress. The main disadvantage of the tapped-inductor buck converter is the effect of the leakage inductance of winding Np . When the upper transistor is turned off, the leakage inductance forms a resonant circuit with the drain-to-source capacitance of that transistor, causing ringing. This increases the transistor peak voltage and switching loss. A higher voltage transistor is required, which will have a higher on-resistance, resulting in a higher conduction loss. MOSFET on-resistance rapidly increases with rated breakdown voltage. An active-clamp technique may be used to reduce the switch peak voltage. 2.8.2 Tapped-Inductor Common-Transistor Buck Converter Consider the tapped-inductor common-transistor (CT) buck converter shown in Figure 2.44(b). When the MOSFET is on and the diode is off, vs = V I − V O . (2.313) v = −VO = nvs (2.314) When the MOSFET is off and the diode is on, resulting in VO . (2.315) n Applying the volt-second balance, we arrive at the dc voltage transfer function for the common-switch converter operating in CCM vs = − MV DC = VO D = . VI D + 1−D n Figure 2.46 shows plots of MV DC as function of D for CCM. (2.316) 82 Pulse-Width Modulated DC–DC Power Converters 1 n = 10 0.8 5 0.6 MVDC 2 0.4 1 0.2 0 Figure 2.46 0 0.25 0.5 D 0.75 1 DC voltage transfer function of tapped-inductor common-switch buck converter for CCM. 2.8.3 Watkins–Johnson Converter Now, we will analyze the Watkins–Johnson (WJ) converter, which is a tapped-inductor common-source (CS) converter. The converter was named after its inventors, Watkins–Johnson Company. It has been used to power traveling wave tubes that exhibit a negative input resistance and are used in satellite communications. The circuit has two poles and a single LHP zero. When the MOSFET is on and the diode is off, v vs = V I − V O = (2.317) n yielding v = n(VI − VO ). (2.318) When the MOSFET is off and the diode is on, vp = VI = v − vs = v − v n−1 =v n n (2.319) resulting in v= n V. n−1 I (2.320) Applying the volt-second balance, n V (1 − D)T n−1 I we get the dc voltage transfer function of the Watkins–Johnson converter for CCM n(VI − VO )DT = MV DC = VO nD − 1 . = VI D(n − 1) (2.321) (2.322) Buck PWM DC–DC Converter 83 1 0.8 n=5 2 1.2 MVDC 0.6 0.4 0.2 0 Figure 2.47 CCM. 0 0.25 0.5 D 0.75 1 DC voltage transfer function of Watkins–Johnson (common-source) tapped-inductor buck converter for This function is illustrated in Figure 2.47. A multiple-output Watkins–Johnson converter can be built, for example, VO1 = 3.3 V and VO2 = 14 V [23]. 2.9 Multiphase Buck Converter So far, we have studied a single-phase buck converter. This circuit requires a relatively large filter capacitor to reduce the output voltage ripple. Microprocessors are supplied with a very low voltage and a very high current, for example, VO = 1.1 V and IO = 100 A. In these applications, there is a stringent requirement on the output voltage tolerance. The output voltage must remain within the required range under dynamic load variations. This imposes restrictions on the values of the filter inductance and the filter capacitance. A very wide bandwidth is required in AM modulators used in RF transmitters. Multiphase buck converter has a smaller filter capacitor and therefore a wider bandwidth. In a polyphase or multiphase buck converter, two or more single-phase converters are operated in parallel and feed the same filter capacitor and load resistance, resulting in ripple cancellation. A two-phase buck converter is shown in Figure 2.48. Usually, synchronous rectifiers are used as diodes. Current and voltage waveforms are shown in Figure 2.49 for the two-phase buck converter. In the two-phase buck converter, the drive signals vGS1 and vGS2 are shifted by 180◦ . When the individual phases of the converter are switched complimentarily, the output voltage ripple reduces considerably due to the ripple cancellation. In a two-phase buck converter, iL1 + iL2 is constant at D = 0.5, yielding a zero ac component. Therefore, the ac component of the current through the filter capacitor is also zero, resulting in zero ripple voltage. Partial ripple cancellation occurs at D ≠ 0.5. If n individual phases are operated in parallel, the frequency of the ripple in the output voltage is n times the switching frequency of each single-phase converter, that is, fr = nfs . The ripple cancellation occurs at D = 1∕n. Due to the reduced magnitude and increased frequency of the output voltage ripple, the required filter capacitance is reduced significantly. This improves the transient response of the power supply. 84 Pulse-Width Modulated DC–DC Power Converters L1 iL1 iS1 + vS1 vD1 + iS2 VI iL2 vD2 + Figure 2.48 IO C RL L2 iD2 + vS2 iL1 + iL2 iD2 Two-phase buck converter. vGS1 vGS2 vL1 t T VI VO t VO vL2 VI VO t VO iL1 t iL2 t iL1 + iL2 t vS1 t VI t iS1 vS2 t VI iS2 t vD1 t t VI iD1 vD2 VI t t iD2 DT Figure 2.49 (1– D)T T t Waveforms in two-phase buck converter. + VO Buck PWM DC–DC Converter iS1 C1 VI C2 Figure 2.50 85 L1 iL1 + vS1 vD1 + iS2 L2 iD1 + vS2 vD2 + iD2 iL2 C RL + VO Two-phase buck converter with two input capacitors. Figure 2.50 shows a two-phase buck converter, with two large capacitors C1 and C2 at the input. The voltage stresses of the switches in this converter are reduced. The dc voltage transfer function is MV DC = VO D = . VI 2 (2.323) 2.10 Switched-Inductor Buck Converter Figure 2.51 shows a circuit of a swithed-inductor buck converter. The dc voltage transfer function of this converter for CCM is given by MV DC = VO D . = VI 2−D (2.324) Figure 2.52 shows a plot of a dc voltage transfer function MV DC as a function of duty cycle D. 2.11 Layout The layout of the converter components is very important from EMI and power loss point of view. The dc current in each loop distributes to minimize the dc voltage drop around the loop, thus minimizing the dc conduction loss. The ac currents distribute to minimize energy stored in magnetic field for each current harmonic. Thus, the ac current flows through the path of the lowest inductance. 2.12 Summary r The PWM buck converter is a step-down converter (V < V ). O I r The buck converter is a transformerless converter. It does not provide dc isolation. r It can operate in two modes: CCM or DCM. S L1 VI C RL + VO L2 Figure 2.51 Switched-inductor buck converter. 86 Pulse-Width Modulated DC–DC Power Converters 1 0.9 0.8 0.7 MVDC 0.6 0.5 0.4 0.3 0.2 0.1 0 Figure 2.52 0 0.2 0.4 D 0.6 0.8 1 DC voltage transfer function of switched-inductor buck converter MV DC as a function of the duty cycle D. r The dc voltage transfer function of the buck converter is M V DC = VO ∕VI = D for CCM if the losses are neglected. It is independent of the load resistance RL (or the load current IO ) and depends only on the switch on-duty cycle D. Therefore, the output voltage VO = DVI is independent of the load resistance RL and depends only on the dc input voltage VI and the duty cycle D. r The converter has conduction losses and switching losses. r The duty cycle D of the lossy converter is greater than that of the lossless converter at the same dc voltage transfer function. r The peak-to-peak value of the inductor ripple current Δi is independent of the dc load current for CCM. L r The peak-to-peak value of the current through the filter capacitor C is relatively low and is equal to the peak-to-peak inductor ripple current ΔiL . r If the capacitance of the filter capacitor is sufficiently high, the output ripple voltage is determined only by the ESR of the filter capacitor and is independent of the capacitance of the filter capacitor. In order to reduce the output ripple voltage, it is necessary to chose a filter capacitor with a low ESR. r The minimum value of the inductor is determined by the boundary between CCM and DCM, ripple voltage, or ac losses in the inductor and the filter capacitor. r A disadvantage of the buck converter is that the input current is pulsating. However, an LC filter can be placed at the converter input to obtain a nonpulsating input √ current waveform. r The corner frequency of the output filter f = 1∕(2𝜋 LC) is independent of the load resistance. o r It is relatively difficult to drive the transistor because neither the source nor the gate is referenced to ground. Therefore, a transformer or an optical coupler is required in the driver circuit. r For CCM, the maximum conduction loss in the transistor occurs at the maximum load current I Omax and at the minimum input voltage VImin (i.e., at Dmax ). r For CCM, the maximum conduction loss in the diode occurs at the maximum load current I Omax and at the maximum input voltage VImax (i.e., at Dmin ). Buck PWM DC–DC Converter 87 r The dc voltage transfer function M V DC is independent of the inductance L for CCM, whereas MV DC depends on L for DCM. r The minimum efficiency occurs at the full load I Omax (or RLmin ) and at VImin for the buck converter operated in both CCM and DCM. r The peak currents, rms currents, and conduction losses in the switch, diode, and filter capacitor are higher in DCM than those in CCM at the same values of the dc input and output currents and output power. The device current stresses in DCM are higher than those in CCM by a factor of two or more. r The ESR of the inductor in DCM is usually lower than that in CCM because the inductance is lower. r A filter capacitor with a very low ESR is required for the buck converter to achieve a low ripple voltage. r The efficiency of the converter in CCM is higher than that in DCM at the same dc input and output currents and the same switching frequency. r Only one-half of the B–H curve of the inductor core is utilized in the buck converter because the dc current flows through the inductor L. References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. [3] K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. [4] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [5] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. [6] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [7] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [8] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Upper Saddle River, NJ: Prentice Hall, 2004. [9] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [10] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. [11] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [12] B. M. Bird, K. G. King, and D. A. G. Pedder, An Introduction to Power Electronics. New York, NY: John Wiley & Sons, 1993. [13] D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. [14] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. [15] I. Batarseh, Power Electronic Circuits. New York, NY: John Wiley & Sons, 2004. [16] A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. [17] A. Reatti, “Steady-state analysis including parasitic components and switching losses of buck and boost dc-dc converter,” International Journal of Electronics, vol. 77, no. 5, pp. 679–702, November 1994. [18] M. K. Kazimierczuk, “Reverse recovery of power pn junction diodes,” International Journal of Circuits, Systems, and Computers, vol. 5, no. 4, pp. 747–755, December 1995. [19] D. A. Grant and Y. Darraman, “Watkins-Johnson converter completes tapped inductor converter matrix,” Electronic Letters, vol. 39, no. 3, pp. 271–272, February 6, 2003. [20] T. H. Kim, J. H. Park, and B. H. Cho, “Small-signal modeling of the tapped-inductor converter under variable frequency control,” IEEE Power Electronics Specialists Conference, 2004, pp. 1648–1652. [21] K. Yao, M. Ye, M. Xu, and F. C. Lee, “Tapped-inductor buck converter for high-step-down dc-dc conversion,” IEEE Transactions on Power Electronics, vol. 20, no. 4, pp. 775–780, July 2005. [22] B. Axelord, Y. Berbovich, and A. Ioinovici, “Switched-capacitor/switched-inductor structure for getting transformerless hybrid dc-dc PWM converters,” IEEE Transactions on Circuits and Systems, vol. 55, no. 2, pp. 687–696, March 2008. [23] Y. Darroman and A. Ferré, “42-V/3-V Watkins-Johnson converter for automotive use,” IEEE Transactions on Power Electronics, vol. 21, no. 3, pp. 592–602, May 2006. 88 Pulse-Width Modulated DC–DC Power Converters [24] D. Czarkowski and M. K. Kazimierczuk, “Static- and dynamic-circuit models of PWM buck-derived converters,” IEE Proceedings Part G Devices Circuits and Systems, vol. 139, no. 6, pp. 669–679, December 1992. [25] D. Maksimović and S. Ćuk, “Switching converters with wide dc conversion range,” IEEE Transactions on Power Electronics, vol. 6, no. 1, pp. 151–157, January 1991. [26] A. Ayachit and M. K. Kazimierczuk, “Steady-state analysis of PWM quadratic buck converter in CCM,” IEEE Midwest Symposium on Circuits and Systems, Columbus, OH, August 3–7, 2013, pp. 49–52. [27] A. Ayachit and M. K. Kazimierczuk, “Power losses and efficiency analysis of PWM quadratic buck converter in CCM,” IEEE Midwest Symposium on Circuits and Systems, College Station, TX, August 4–8, 2014. [28] A. Ayachit and M. K. Kazimierczuk, “Open-loop transfer functions of PWM quadratic buck converter in CCM,” IEEE Industrial Electronics Society, Dallas, TX, November 2014, pp. 1643–1649. [29] L. Balogh, “Design and application guide for high speed MOSFET gate drive circuits.” Texas Instrument Publication. [30] P.-J. Liu, W.-S. Shan, J.-N. Tai, H.-S. Chen, J.-H. Chen, Y.-J. E. Chen, “A high-efficiency CMOS dc-dc converter with 9-𝜇s transient recovery time,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 59, no. 3, pp. 575–583, March 2012. pp. 687–696, March 2008. Review Questions 2.1 Define the converter operation in the CCM and the DCM. 2.2 Does the buck converter have a transformer version? 2.3 Is the input current of the basic buck converter pulsating? 2.4 How can the buck circuit be modified to obtain a nonpulsating input current? 2.5 Is the transistor driven with respect to ground in the buck converter? 2.6 How is the dc voltage transfer function MV DC related to the duty cycle D for the lossless buck converter operated in CCM? 2.7 Is the duty cycle D of the lossy buck converter lower or greater than that of the lossless converter at a given value of MV DC for CCM? 2.8 Does the dc voltage transfer function of the buck converter depend on the load resistance? 2.9 What determines the ripple voltage in the buck converter in CCM? 2.10 Compare the voltage and current stresses for the transistor and the diode in the buck converter for CCM and DCM. 2.11 Is the corner frequency of the output filter dependent on the load resistance in the buck converter? 2.12 Is the efficiency high at heavy or light loads for the buck converter operated in CCM? 2.13 Are both halves of the B–H curve of the inductor core utilized in the buck converter? Problems 2.1 Derive an expression for the dc voltage transfer function of the lossless buck converter operating in CCM using the diode voltage waveform. 2.2 A buck converter has VI = 22–32 V, VO = 14 V, IO = 0.2–2 A, and fs = 40 kHz. Find the minimum inductance L required to maintain the converter operation in the continuous conduction mode. 2.3 For the converter given in Problem 2.2, find the voltage and current stresses of the transistor and diode. Buck PWM DC–DC Converter 89 2.4 A buck PWM converter has VI = 10–14 V, VO = 5 V, IO = 0.2–1 A, fs = 200 kHz, L = 100 𝜇H, C = 100 𝜇F, and rC = 20 mΩ. Find the ripple voltage Vr and (Vr ∕VO ) × 100%. Also, calculate the ripple voltage across the filter capacitance and the corner frequency of the output filter. 2.5 For the converter given in Problem 2.4, the filter capacitance has been reduced to 47 𝜇F. Find the ripple voltage. 2.6 A PWM converter operates in CCM at VI = 10 V and VO = 5 V. Find the duty cycle D if (a) the converter efficiency 𝜂 = 100% and (b) the converter efficiency 𝜂 = 80%. 2.7 A buck converter operating in CCM has a MOSFET whose rDS = 0.025 Ω. The load current is IO = 10 A. Determine the MOSFET conduction loss at D = 0.1 and 0.9. 2.8 A buck converter operating in CCM has a diode whose RF = 0.025 Ω and VF = 0.3 V. The load current is IO = 10 A. Determine the diode conduction loss at D = 0.1 and 0.9. 2.9 A power MOSFET has VB = 0.75 V, Crss = 30 pF, and Coss = 130 pF at VDS = 25 V. It is used in a buck PWM converter with VI = 400 V and fs = 1 MHz. Find CJ0 , Cds (VI ), Q(VI ), Psw , Pturn-off and Psw(FET) . 2.10 A buck converter has VI = 22–32 V, VO = 14 V, IO = 0–2 A, and fs = 40 kHz. Find the maximum inductance L required to maintain the converter operation in the discontinuous conduction mode. Assume 𝜂 = 90%. 2.11 Design a buck PWM converter to meet the following specifications: VI = 12 V± 4 V, VO = 5 V, IO = 1–10 A, Vr ∕VO ≤ 1%, fs = 100 kHz, rL(dc) = 50 mΩ, rDS = 10 mΩ, Co = 200 pF, VF = 0.3 V, and RF = 20 mΩ. √ 2.12 Design a universal buck PWM converter to meet the following specifications: V = 85 2 V, VImax = Imin √ 264 2 V, VO = 48 V, IO = 0.2 to 2 A, Vr ∕VO ≤ 1%, fs = 200 kHz, rL = 1 Ω, rDS = 1 Ω, Co = 100 pF, VF = 0.7 V, and RF = 25 mΩ. 2.13 A buck converter has the following specifications: VI = 4–6 V, VO = 3 V, IO = 0–5 A, fs = 250 kHz, and Vr ∕VO ≤ 2%. Assume 𝜂 = 0.9. Find L, C, and rC . 2.14 A buck PWM converter has VI = 270 V ±5%, VO = 28 V, IO = 0–15 A, Vr ∕VO ≤ 5%, rL(dc) = 0.05 Ω, rC = 0.037 Ω, rDS = 0.3 Ω, Co = 150 pF, VF = 0.8 V, RF = 17.1 mΩ, and fs = 100 kHz. Find L, C, and rC . Assume the initial efficiency 𝜂 = 90% at full power. 2.15 A buck PWM converter has VI = 5 V ± 20%, VO = 1.8 V, IO = 1–10 A, Vr ∕VO ≤ 3%, rL(dc) = 0.02 Ω, rDS = 0.01 Ω, Co = 150 pF, VF = 0.3 V, RF = 18 mΩ, and fs = 500 kHz. Find L, C, rCmax , ISMmax , and VSMmax . Estimate PLS and 𝜂 at IOmax and VImin . Assume the initial efficiency 𝜂 = 80% at full power. 2.16 Design a buck converter to meet the following specifications: VI = 5 ± 1 V, VO = 3.3 V, IO = 0–5 A, Vr ∕VO ≤ 1%, fs = 500 kHz, rDS = 8 mΩ, RF = 20 mΩ, VF = 0.3 V, rL = 50 mΩ, and Qg = 50 nC. 2.17 Design a buck PWM converter to meet the following specifications: VI = 3.3 V ± 0.3 V, VO = 1.8 V, IO = 0.3–1.5 A, Vr ≤ 10 mV, and fs = 200 kHz. 3 Boost PWM DC–DC Converter 3.1 Introduction This chapter is devoted to the PWM boost dc–dc switching-mode converter [1–21]. The converter is analyzed for both CCM and DCM. Voltage and current waveforms are derived. The dc voltage transfer function is determined. The voltage and current stresses of the converter components are given. Expressions for the inductance and the capacitance are derived. Power losses are estimated. Design examples are given. 3.2 DC Analysis of PWM Boost Converter for CCM 3.2.1 Circuit Description The circuit of the PWM boost dc–dc converter is shown in Figure 3.1(a). Its output voltage VO is always higher than the input voltage VI for steady-state operation. It “boosts” the voltage to a higher level. The converter consists of an inductor L, a power MOSFET, a diode D1 , a filter capacitor C, and a load resistor RL . The switch S is turned on and off at the switching frequency fs = 1∕T with the on duty ratio D = ton ∕T, where ton is the time interval when the switch S is on. The boost converter can operate in one of the two modes: a continuous conduction mode (CCM) or a discontinuous conduction mode (DCM), depending on the waveform of the inductor current. The boost converter in DCM cannot operate at RL = ∞ because the filter capacitor has no path to discharge. The CCM will be considered first. Figures 3.1(b) and (c) show equivalent circuits of the boost converter for CCM when the switch S is on and the diode is off, and when the switch is off and the diode is on, respectively. Idealized waveforms of the currents and voltages that explain the principle of operation of the boost converter are depicted in Figure 3.2. For the time interval 0 < t ≤ DT, the switch is on. Therefore, the voltage across the diode is vD = −VO , causing the diode to be reverse biased. The voltage across the inductor is vL = VI . As a result, the inductor current increases linearly with a slope of VI ∕L. Consequently, the magnetic energy also increases. The switch current is equal to the inductor current. At t = DT, the switch is turned off by the gate-to-source voltage. The inductor acts as a current source and turns the diode on. The voltage across the inductor is vL = VI − VO < 0. Hence, the inductor current decreases with a slope of (VI − VO )∕L. The diode current is equal to the inductor current. During this time interval, the energy is transferred from the inductor L to the filter capacitor C and the load resistance RL . At time t = T, the switch is turned on again, terminating the cycle. Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 Boost PWM DC–DC Converter iL L + vL VI iD iS + v D + vS + vGS 91 C RL + VO C RL + VO C RL + VO (a) L iL + vL + vD iS VI (b) L + vL VI iL iD + vS (c) Figure 3.1 PWM boost converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. The boost converter has poor ability to prevent hazardous transients and failures. If a high positive voltage surge appears at the converter input, the input voltage exceeds the output voltage and the diode D1 is on for many cycles due to cycle skip. This generates a large current spike through the diode, which may destroy the diode. A similar problem exists at the initial turn-on of the converter when the input voltage is high and the output voltage is initially zero and while the output voltage is lower than the input voltage until steady-state conditions are approached. One way to protect the converter is to add a diode whose anode is connected to the input source VI and the cathode is connected to the output filter capacitor C. When the output voltage is lower than the input voltage, the additional diode and the filter capacitor form a peak rectifier and the energy flows from the input to the output of the converter through the additional diode. When the output voltage becomes higher than the input voltage, the additional diode is reverse biased and turns off and the boost converter begins normal operation. The output power level of the boost converter is usually between 20 and 400 W. This converter is commonly used as an active power factor corrector. 3.2.2 Assumptions The analysis of the boost PWM converter of Figure 3.1(a) begins with the following assumptions: (1) The power MOSFET and the diode are ideal switches. (2) The transistor output capacitance, the diode capacitance, and lead inductances (and thereby switching losses) are zero. 92 Pulse-Width Modulated DC–DC Power Converters vGS 0 DT T t T t vL VI A+ 0 VI DT A VO VI iL VI L II – VO L ΔiL 0 T t DT T t DT T t DT iS VI ISM L II IS 0 vS VSM VO iD 0 IDM II IO 0 vD 0 vDM Figure 3.2 DT T DT T t t VO Idealized current and voltage waveforms in the PWM boost converter for CCM. Boost PWM DC–DC Converter 93 (3) Passive components are linear, time invariant, and frequency independent. (4) The output impedance of the input voltage source VI is zero for both dc and ac components. 3.2.3 Time Interval: 0 < t ≤ DT The switch S is on and the diode is off during the time interval 0 < t ≤ DT. An ideal equivalent circuit for this time interval is shown in Figure 3.1(b). When the switch is on, the voltage across the diode vD is approximately equal to −VO and therefore the diode is reverse biased. The voltage across the switch vS and the diode current are zero. The voltage across the inductor L is diL dt (3.1) t t V 1 1 vL dt + iL (0) = VI dt + iL (0) = I t + iL (0) L ∫0 L ∫0 L (3.2) vL = V I = L and the inductor current iL and the switch current iS is iS = iL = where iL (0) is the initial inductor current at time t = 0. From (3.2), the peak inductor current is obtained VI DT + iL (0). (3.3) L It will be shown shortly that the dc voltage transfer function is MVDC = VO ∕VI = II ∕IO = 1∕(1 − D). Hence, the peak-to-peak value of the inductor ripple current is expressed as iL (DT) = ΔiL = iL (DT) − iL (0) = VO D V D(1 − D) VD VI DT V DT + iL (0) − iL (0) = I = I = = O . L L fs L MVDC fs L fs L (3.4) For fixed values of VO , fs , and L, d(ΔiL ) VO = (1 − 2D) = 0. dD fs L (3.5) Setting this derivative to zero, one can show that the maximum value of ΔiL occurs at D = 0.5 and is given by ( ) 1 1 1 − VO V 2 2 = O . (3.6) ΔiLmax = fs L 4fs L As the duty cycle D is increased from 0 to 1, the peak-to-peak inductor ripple current ΔiL increases from zero, reaches its maximum at D = 0.5, and then decreases to zero. The diode voltage is vD = −VO . (3.7) Therefore, the diode is off. The average value of the inductor current IL is equal to the dc input current II . Hence, one arrives at the peak value of the switch current I Δi Δi (3.8) ISM = II + L = O + L . 2 1−D 2 This time interval is terminated at t = DT when the switch is turned off by the driver. The inductor current iL flows continuously for CCM. Since iL (DT) is nonzero when the switch is turned off, it acts almost as a current source and turns the diode on. The waveform of the magnetic energy stored in the inductor is wL (t) = 2 1 2 1 1 1 VI 2 1 2 LiL (t) + wL (0) = Li2L (t) + Li2L (0) = t + LiL (0). 2 2 2 2 L 2 (3.9) 94 Pulse-Width Modulated DC–DC Power Converters The increase in the inductor magnetic energy is 1 2 L[i (DT) − i2L (0)]. 2 L ΔWL(in) = (3.10) 3.2.4 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch is off and the diode is on. Figure 3.1(c) shows an ideal equivalent circuit of the lossless converter for this time interval. The switch current iS and the diode voltage vD are zero. The inductor discharges during this time interval. The voltage across the inductor L is vL = V I − V O = L diL <0 dt (3.11) which indicates that VO > VI . The current through the inductor and the diode can be found as t iD = iL = t V − VO 1 1 (t − DT) + iL (DT) vL dt + iL (DT) = (VI − VO )dt + iL (DT) = I ∫ ∫ L DT L DT L (3.12) where iL (DT) is the initial inductor current iL at t = DT. The peak-to-peak value of the inductor ripple current is ΔiL = iL (DT) − iL (T) = V D(1 − D) (VO − VI )(1 − D)T = O L fs L (3.13) where VI = VO (1 − D). The voltage across the switch S is given by vS = VO = VSM . (3.14) The peak diode current and the peak switch current are given by IDM = ISM = II + I Δi ΔiL = O + L. 2 1−D 2 (3.15) I ΔiLmax Δi = Omax + Lmax . 2 1 − Dmax 2 (3.16) For the worst case, this expression becomes IDMmax = ISMmax = IImax + This time interval ends at t = T when the switch is turned on by the driver. The decrease in the magnetic energy stored in the inductor L during the time interval DT < t ≤ T is ΔWL(out) = 1 2 L[i (DT) − i2L (T)]. 2 L (3.17) For steady state, the increase in the magnetic energy stored in the inductor during the time interval 0 < t ≤ DT is equal to the decrease in the magnetic energy stored in the inductor during the time interval DT < t ≤ T. 3.2.5 DC Voltage Transfer Function for CCM The average value of the voltage across the inductor for steady state is T 1 v dt = 0. T ∫0 L (3.18) VI DT = (VO − VI )(1 − D)T (3.19) VL(AV) = Referring to Figure 3.2, Boost PWM DC–DC Converter 95 which gives VI 1−D and results in the dc voltage transfer function for the lossless boost converter VO = (3.20) VO I 1 = I = . VI IO 1−D (3.21) MVDC ≡ The range of MVDC for the lossless converter is 1 ≤ MVDC ≤ ∞. (3.22) It will be shown shortly that the maximum value of MVDC is limited by losses. Rearrangement of (3.21) gives D=1− 1 MVDC = MVDC − 1 . MVDC (3.23) The sensitivity of VO with respect to D is S≡ dVO VI = . dD (1 − D)2 (3.24) The dc current transfer function of the boost converter is I MIDC ≡ O = 1 − D. II (3.25) As D is increased from 0 to 1, MIDC decreases from 1 to 0. Using (3.21) and (3.25), the output-power capability of the boost converter is PO V I I I cp ≡ = O O = O ≈ O = 1 − D. (3.26) VSM ISM VSM ISM ISM II As D is increased from 0 to 1, cp decreases from 1 to 0. 3.2.6 Boundary Between CCM and DCM Figure 3.3 shows the inductor current waveform at the boundary between the CCM and the DCM. This waveform is given by iL = VI t L 0 < t ≤ DT (3.27) VO D V D(1 − D) VI DT = . = O L fs LMVDC fs L (3.28) for from which ΔiL = iL (DT) = iL IIB 0 Figure 3.3 VI VO L VI L Δ iL DT T t Waveform of the inductor current at the boundary between CCM and DCM for the boost converter. 96 Pulse-Width Modulated DC–DC Power Converters 0.16 CCM 0.14 0.1 0.08 I OB /(VO /2fs L) 0.12 0.06 DCM 0.04 0.02 0 0 0.2 0.4 D 0.6 0.8 1 Figure 3.4 Normalized load current IOB ∕(VO ∕2fs L) at the boundary between CCM and DCM as a function of D for boost converter. The dc input current at the boundary between CCM and DCM is IIB = V D(1 − D) ΔiL = O 2 2fs L (3.29) whose maximum value occurs at D = 0.5. From (3.21) and (3.29), the dc output current at the boundary between CCM and DCM is IOB = IIB (1 − D) = − 1) V (M VO D(1 − D)2 = O VDC3 2fs L 2fs LMVDC (3.30) and the load resistance at the boundary is RLB = 3 2fs LMVDC VO 2fs L . = = IOB MVDC − 1 D(1 − D)2 (3.31) Figures 3.4 and 3.5 show the plots of IOB ∕(VO ∕2fs L) = D(1 − D)2 and RLB ∕(2fs L) = 1∕[D(1 − D)2 ] as functions of D. To find the maximum value of IOB , its derivative can be found as dIOB V = O (1 − 4D + 3D2 ) = 0. dD 2fs L (3.32) Thus, the maximum value of IOB occurs at Dm = 1 3 (3.33) Boost PWM DC–DC Converter 97 50 45 40 RLB /(2fs L) 35 30 CCM 25 20 15 DCM 10 0 Figure 3.5 converter. 0.2 0.4 D 0.6 0.8 1 Normalized load resistance RLB ∕(2fs L) at the boundary between CCM and DCM as a function of D for boost which corresponds to MVDC = 1.5. Substitution of (3.33) into (3.30) gives the maximum value of the load current at the boundary IOBmax = 2 VO 27 fs Lmin (3.34) and the minimum value of the load resistance at the boundary RLBmin = VO = 13.5fs Lmin . IOBmax (3.35) Hence, using IOBmax = IOmin = VO ∕RLmax , one arrives at the minimum value of the inductance L which ensures the operation in CCM at any value of D Lmin = 2 VO 2 RLmax = . 27 fs IOBmax 27 fs (3.36) If Dmax < 1∕3 or Dmin > 1∕3, a less conservative approach can be taken. Using (3.30), the following expressions can be derived ⎧ V D (1 − D )2 max ⎪ O max , for 2fs Lmin ⎪ IOBmax = ⎨ 2 ⎪ VO Dmin (1 − Dmin ) , for ⎪ 2fs Lmin ⎩ D< 1 3 D≥ 1 3 (3.37) 98 Pulse-Width Modulated DC–DC Power Converters iD C rC Figure 3.6 IO iC + vC + vrc RL + VO Equivalent circuit of the output part of the boost converter. and ⎧R D (1 − Dmax )2 ⎪ Lmax max , for 2fs ⎪ Lmin = ⎨ 2 ⎪ RLmax Dmin (1 − Dmin ) , for ⎪ 2fs ⎩ D< 1 3 (3.38) 1 D≥ . 3 3.2.7 Ripple Voltage in Boost Converter for CCM The output part of the boost converter is shown in Figure 3.6. The filter capacitor in this figure is modeled by its capacitance C and its equivalent series resistance (ESR) rC . Figure 3.7 shows current and voltage waveforms in the converter output circuit. The dc component of the diode current flows through the load resistor RL . The ac component of the diode current is divided between the capacitor branch and the load resistance branch. In practice, the filter capacitor is designed in such a way that the impedance of the capacitor branch is much less than the load resistance RL . Consequently, the current through the capacitor is approximately equal to the ac component of the diode current. The maximum peak-to-peak value of the capacitor current is ICpp = IDMmax ≈ IImax = IOmax 1 − Dmax (3.39) resulting in the peak-to-peak value of the voltage across rC Vrcpp = rC ICpp = rC IDMmax ≈ rC IOmax . 1 − Dmax (3.40) The peak-to-peak value of the output ripple voltage Vr is usually specified. Hence, the maximum peak-to-peak value of the ac component of the voltage across the capacitance C is found as VCpp ≈ Vr − Vrcpp . (3.41) On the other hand, this voltage is approximately given by VCpp = I VO Dmax D T ΔQmax = Omax max = Cmin Cmin fs RLmin Cmin (3.42) where ΔQmax is the charge decrease during the time interval from zero to DT. Rearrangement of (3.42) gives the minimum filter capacitance Cmin = IOmax Dmax Dmax VO = . fs VCpp fs RLmin VCpp (3.43) Boost PWM DC–DC Converter iD IDM Δ iL IO II 0 DT 1−D t T iC II − IO ΔQ IDM 0 DT −ΔQ II + IO T t − IO vrc = rc ic vrc ≈ rc II vrc 0 DT T t vc 0 Vc DT T t vo Vr 0 Figure 3.7 DT T t Waveforms illustrating the ripple voltage in the PWM boost converter. 99 100 Pulse-Width Modulated DC–DC Power Converters L rL iL iD VF IO RF iC C iS VI RL rC + VO rDS Figure 3.8 Equivalent circuit of the boost converter with parasitic resistances and the diode offset voltage. 3.2.8 Power Losses and Efficiency of Boost Converter for CCM An equivalent circuit of the boost converter with parasitic resistances is shown in Figure 3.8, where rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be evaluated assuming that the inductor current iL is ripple free and equals the dc input current II . Hence, the switch current can be approximated by { IO , for 0 < t ≤ DT II = 1−D (3.44) iS = 0, for DT < t ≤ T resulting in its rms value √ ISrms = T I 1 i2S dt = O T ∫0 1−D √ 1 T ∫0 DT √ IO D dt = 1−D (3.45) and the MOSFET conduction loss 2 PrDS = rDS ISrms = DrDS IO2 (1 − D)2 = DrDS PO . (1 − D)2 RL (3.46) Note that the transistor conduction loss increases rapidly with increasing duty cycle D at a fixed load current IO . Assuming that the transistor output capacitance Co is linear, the switching loss is expressed by 2 = fs Co VO2 = fs Co RL PO . Psw = fs Co VSM Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power) ] [ DrDS IO2 DrDS 1 1 1 2 PFET = PrDS + Psw = + fC V = + fC R P . 2 (1 − D)2 2 s o O (1 − D)2 RL 2 s o L O Likewise, the diode current can be approximated by { 0, iD = IO , II = 1−D for 0 < t ≤ DT for DT < t ≤ T (3.47) (3.48) (3.49) yielding its rms value √ IDrms = T I 1 i2 dt = O T ∫0 D 1−D √ T I 1 dt = √ O T ∫DT 1−D (3.50) Boost PWM DC–DC Converter 101 and the power loss in RF 2 PRF = RF IDrms = RF IO2 1−D = RF PO . (1 − D)RL (3.51) The diode power loss due to RF increases rapidly with increasing duty cycle D at fixed load current IO . The average value of the diode current is ID = T T IO 1 iD dt = dt = IO T ∫0 T(1 − D) ∫DT (3.52) which gives the power loss associated with the voltage VF PVF = VF ID = VF IO = Thus, the overall diode conduction loss is PD = PVF + PRF = VF IO + [ RF IO2 1−D = VF PO . VO (3.53) ] RF VF P . + VO (1 − D)RL O (3.54) The inductor current is iL ≈ II = IO 1−D (3.55) IO 1−D (3.56) leading to its rms value ILrms = II = and the inductor loss 2 PrL = rL ILrms = rL IO2 (1 − D)2 = rL PO . (1 − D)2 RL (3.57) The inductor loss increases rapidly with increasing duty cycle D at fixed load current IO . The current through the capacitor C is approximately given by { for 0 < t ≤ DT −IO , iC = DIO , for DT < t ≤ T. II − IO = 1−D Hence, one obtains the rms current through the filter capacitor √ √ T 1 D 2 i dt = IO ICrms = T ∫0 C 1−D (3.58) (3.59) and the power loss in the filter capacitor 2 = PrC = rC ICrms The overall power loss of the boost converter is PLS = PrDS + Psw + PD + PrL + PrC = [ DrC IO2 1−D = DrC PO . (1 − D)RL (3.60) ] RF + DrC rL + DrDS VF + + + f C R s o L PO (1 − D)2 RL (1 − D)RL VO (3.61) yielding the converter efficiency 𝜂= PO 1 1 = = . P r +Dr R +Dr V PO + PLS 1 + LS 1 + L DS + F C + F + f C R PO (1−D)2 RL (1−D)RL VO s o L (3.62) 102 Pulse-Width Modulated DC–DC Power Converters 100 R = 250 Ω L 90 75 Ω 80 25 Ω 70 η (%) 60 50 40 30 20 10 0 0 0.2 0.4 D 0.6 0.8 1 Figure 3.9 Efficiency of the boost converter 𝜂 versus D for VO = 28 V, rDS = 0.5 Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF. Figure 3.9 shows the efficiency of the boost converter 𝜂 as a function of the duty cycle D for VO = 28 V, rDS = 0.5 Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF. It can be seen that the efficiency 𝜂 decreases with increasing D and it is higher for higher load resistances RL . 3.2.9 DC Voltage Transfer Function of Lossy Boost Converter for CCM The dc component of the output current is T IO = T 1 1 i dt = I dt = (1 − D)II T ∫0 D T ∫DT I (3.63) leading to the dc current transfer function of the boost converter MIDC ≡ IO = 1 − D. II (3.64) This equation holds true for both lossless and lossy converters. The efficiency of the converter can be expressed as 𝜂= PO V I = O O = MVDC MIDC = MVDC (1 − D) PI VI II (3.65) from which the voltage transfer function of the lossy boost converter is MVDC = 𝜂 1 = . 1 − D (1 − D)[1 + rL +DrDS + RF +DrC + VF + f C R ] (1−D)2 RL (1−D)RL VO s o L (3.66) Boost PWM DC–DC Converter 103 9 8 R = 250 Ω L 7 M VDC 6 75 Ω 5 4 25 Ω 3 2 1 0 0 0.2 0.4 D 0.6 0.8 1 Figure 3.10 DC voltage transfer function MVDC of the lossy boost converter as a function of D for CCM at VO = 28 V, rDS = 0.5Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF. Figure 3.10 depicts MVDC as a function of D. The duty cycle of the lossy boost converter is D=1− 𝜂V 𝜂 =1− I. MVDC VO (3.67) Thus, the duty cycle D increases as the efficiency decreases at a fixed value of MVDC . Substitution of (3.67) into (3.62) yields the converter efficiency 𝜂= N𝜂 D𝜂 (3.68) where N𝜂 = RL − MVDC (RF + rC − rDS ) )} 12 ( { r V 2 RL (rL + rDS ) 1 + F − C + fs Co RL + [MVDC (RF + rC − rDS ) − RL ]2 − 4MVDC VO RL and ( D𝜂 = 2RL ) rC VF 1+ − + fs Co RL . VO RL (3.69) (3.70) 3.2.10 Design of Boost Converter for CCM Design a PWM boost converter to meet the following specifications: VI is the US single-phase rectified utility line voltage, VO = 400 V, IOmax = 0.225 A, IOmin = 5% of IOmax , and Vr ∕VO < 1%. 104 Pulse-Width Modulated DC–DC Power Converters Solution: Assume that the converter is operated in CCM. The rms voltage of the US utility line changes from 90 V (low line) to 132 V (high line) for normal operation. Hence, the minimum, nominal, and maximum values of the dc voltages at the output of a full-bridge front-end rectifier are √ √ VImin = 2Vrms(min) = 2 × 90 = 127 V (3.71) √ √ (3.72) VInom = 2Vrms(nom) = 2 × 110 = 156 V and VImax = √ 2Vrms(max) = √ 2 × 132 = 187 V. (3.73) The minimum load current is IOmin = IOmax 0.225 = = 11.25 mA. 20 20 (3.74) The maximum and minimum values of the output power are POmax = VO IOmax = 400 × 0.225 = 90 W (3.75) POmin = VO IOmin = 400 × 0.01125 = 4.5 W. (3.76) and The minimum and the maximum load resistances are V 400 = 1.778 kΩ RLmin = O = IOmax 0.225 (3.77) and RLmax = VO IOmin = 400 = 35.6 kΩ. 0.01125 (3.78) The minimum, nominal, and maximum values of the dc voltage transfer function are MVDCmin = VO 400 = 2.14 = VImax 187 (3.79) MVDCnom = VO 400 = 2.56 = VInom 156 (3.80) MVDCmax = VO 400 = 3.15. = VImin 127 (3.81) and Assume that the efficiency 𝜂 of the converter is 90%. Hence, the minimum, nominal, and maximum values of the duty cycle are Dmin = 1 − 𝜂 0.9 = 0.579 =1− MVDCmin 2.14 (3.82) Dnom = 1 − 𝜂 0.9 = 0.65 =1− MVDCnom 2.56 (3.83) Dmax = 1 − 𝜂 0.9 = 0.714. =1− MVDCmax 3.15 (3.84) and Boost PWM DC–DC Converter 105 Let us assume the switching frequency fs = 100 kHz. The minimum inductance that ensures CCM operation at any duty cycle D is Lmin = 2 RLmax 2 35.6 × 103 = = 26.37 mH. 27 fs 27 0.1 × 106 (3.85) Since Dmin = 0.58 > 1∕3, the minimum inductance required for CCM operation can be calculated as Lmin = RLmax Dmin (1 − Dmin )2 35.6 × 103 × 0.579 × (1 − 0.579)2 = = 18.23 mH. 2fs 2 × 100 × 103 (3.86) Pick L = 20 mH. One can design this inductor so that its dc ESR is rL(dc) = 2.1 Ω. For D > 0.5, the maximum inductor peak-to-peak current of the ac component occurs at Dmin . Hence, ΔiLmax = VO Dmin (1 − Dmin ) 400 × 0.579 × (1 − 0.579) = = 48.75 mA. fs L 105 × 20 × 10−3 (3.87) The current and voltage stresses of the MOSFET and the diode are ISMmax = IDMmax = IOmax V D (1 − Dmax ) 400 × 0.714 × (1 − 0.714) 0.225 = + + O max = 0.8071 A (3.88) 1 − Dmax 2fs L 1 − 0.714 2 × 105 × 20 × 10−3 and VSM = VDM = VO = 400 V. (3.89) One can select an MTP4N50 power MOSFET with VDSS = 500 V, ISM = 4 A, rDS = 1 Ω, Qg = 27 nC, and Co = 100 pF. An ultrafast recovery diode MUR1560 is also chosen, which has VDM = 600 V, IDM = 15 A, VF = 0.7 V, and RF = 17.1 m Ω. The ripple voltage is Vr = 0.01VO = 0.01 × 400 = 4 V. (3.90) Let us assume that the ripple voltage is equally divided between the capacitance and the ESR. Thus Vrcpp = VCpp = Vr 4 = = 2 V. 2 2 (3.91) 2 = 2.478 Ω 0.8071 (3.92) Hence, the maximum ESR is rCmax = Vrcpp IDMmax = and the minimum filter capacitance is Cmin = Dmax VO 0.714 × 400 = 5 = 0.8 μF. fs RLmin VCpp 10 × 1778 × 2 (3.93) Pick a metallized polyester capacitor with C = 1 μ F/630 V/1 Ω. The minimum corner frequency of the output filter is fomin = 1 1 = = 4.4706 Hz 2𝜋CRLmax 2 × 𝜋 × 10−6 × 35.6 × 103 (3.94) and the maximum corner frequency of the output filter is fomax = 1 1 = 89.5 Hz. = 2𝜋CRLmin 2 × 𝜋 × 10−6 × 1778 (3.95) 106 Pulse-Width Modulated DC–DC Power Converters The rms values of the inductor current is ILrms ≈ IImax = IOmax 0.225 = 0.787 A = 1 − Dmax 1 − 0.714 (3.96) resulting in the inductor power loss 2 = 2.1 × 0.7872 = 1.3 W. PrL = rL ILrms The rms values of the switch current is √ √ Dmax IOmax 0.714 × 0.225 = 0.6648 A = ISrms = 1 − Dmax 1 − 0.714 (3.97) (3.98) which leads to the MOSFET conduction loss 2 PrDS = rDS ISrms = 1 × 0.66482 = 0.442 W. (3.99) The output capacitance of the MOSFET is Co = 100 pF. Hence, the switching loss is 2 Psw = fs Co VSM = fs Co VO2 = 105 × 100 × 10−12 × 4002 = 1.6 W. (3.100) The total power loss in the MOSFET is PFET = PrDS + Psw = 0.442 + 0.8 = 1.242 W. 2 (3.101) The diode power loss due to the diode offset voltage VF is PVF = VF IOmax = 0.7 × 0.225 = 0.1575 W. (3.102) I 0.225 IDrms = √ Omax = √ = 0.421 A 1 − Dmax 1 − 0.714 (3.103) The diode rms current is resulting in the power loss due to the diode forward resistance RF 2 PRF = RF IDrms = 0.0171 × 0.4212 = 3 mW. (3.104) PD = PVF + PRF = 0.158 + 0.003 = 0.161 W. (3.105) Thus, the diode conduction loss is The capacitor rms current is √ ICrms = IOmax Dmax = 0.225 1 − Dmax √ 0.714 = 0.3555 A. 1 − 0.714 (3.106) Assuming the ESR of the filter capacitor rC = 1 Ω, the power loss in the capacitor is 2 = 1 × 0.35552 = 0.1263 W. PrC = rC ICrms (3.107) Boost PWM DC–DC Converter 107 100 R = 1.778 kΩ L 95 R = 3.556 kΩ L η (%) 90 85 80 75 R = 36.5 kΩ L 70 120 130 140 150 V (V) 160 170 180 190 I Figure 3.11 Efficiency 𝜂 of the designed boost converter as a function of VI at fixed values of RL for CCM. The total power loss is PLS = PrDS + Psw + PD + PrL + PrC = 0.442 + 1.6 + 0.161 + 1.3 + 0.1263 = 3.63 W (3.108) and the converter efficiency at full load is 𝜂= POmax 90 = 96.12%. = POmax + PLS 90 + 3.63 (3.109) Assuming the magnitude of the gate-to-source voltage VGSm = 7 V, the gate-drive power is calculated as PG = fs Qg VGSm = 105 × 27 × 10−9 × 7 = 18.9 mW. (3.110) Using (3.68) through (3.70), the efficiency 𝜂 of the designed boost converter can be computed over the entire range of VI and IO (or RL ) for CCM. Using the calculated efficiency 𝜂, the duty cycle D can be calculated from (3.67). Figures 3.11 and 3.12 depict the efficiency 𝜂 and the duty cycle D of the designed boost converter versus the dc input voltage VI at fixed load resistances RL . Plots of the efficiency 𝜂 and the duty cycle D as functions of IO at fixed values of VI are shown in Figures 3.13 and 3.14. Figures 3.15 and 3.16 show the efficiency 𝜂 and the duty cycle D of the designed converter as functions of RL at fixed values of VI . The efficiency 𝜂 increases as IO increases (or RL decreases). The maximum efficiency 𝜂max occurs at the maximum load current IOmax , and the minimum efficiency 𝜂min occurs at the minimum load IOmin , which is an advantage of the boost converter. The duty cycle D increases as VI and IO decrease. 3.3 DC Analysis of PWM Boost Converter for DCM Equivalent circuits for the PWM boost converter operating in the DCM are depicted in Figure 3.17. Idealized current and voltage waveforms are shown in Figure 3.18. For the time interval 0 < t ≤ DT, the switch is on and 108 Pulse-Width Modulated DC–DC Power Converters 0.8 0.75 R = 36.5 kΩ L D 0.7 0.65 R = 1.778 kΩ L 0.6 R = 3.556 kΩ L 0.55 0.5 120 Figure 3.12 130 140 150 VI (V) 160 170 180 190 Duty cycle D of the boost converter designed as a function of VI at fixed values of RL for CCM. 100 VI = 187 V 95 VI = 156 V VI = 127 V η (%) 90 85 80 75 70 Figure 3.13 0 0.05 0.1 I (A) O 0.15 0.2 0.25 Efficiency 𝜂 of the designed boost converter as a function of load current IO at fixed values of VI for CCM. Boost PWM DC–DC Converter 109 0.8 0.75 VI = 127 V D 0.7 0.65 VI = 156 V 0.6 VI = 187 V 0.55 0.5 Figure 3.14 0 0.05 0.1 IO (A) 0.15 0.2 0.25 Duty cycle D of the designed boost converter as a function of load current IO at fixed values of VI for CCM. 100 V = 187 V I V = 156 V I 95 V I = 127 V η (%) 90 85 80 75 70 0 5 10 15 20 R (kΩ) 25 30 35 40 L Figure 3.15 CCM. Efficiency 𝜂 of the designed boost converter as a function of load resistance RL at fixed values of VI for 110 Pulse-Width Modulated DC–DC Power Converters 0.8 V = 127 V I 0.75 V I = 156 V D 0.7 V I = 187 V 0.65 0.6 0.55 0 Figure 3.16 CCM. 5 10 15 20 RL (kΩ) 25 30 35 40 Duty cycle D of the designed boost converter as a function of load resistance RL at fixed values of VI for therefore the diode is off. The voltage across the inductor is VI and the inductor current increases linearly from zero. For the time interval DT < t ≤ (D + D1 )T, the switch is off and the diode is on. At time t = (D + D1 )T, the inductor and diode current reaches zero, turning the diode off. For the time interval (D + D1 )T < t ≤ T, both the switch and the diode are off. Since the current through the inductor is constant (equal to zero), the voltage across the inductor is zero. At time t = T, the switch is turned on and the inductor current starts to increase from zero. 3.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is on and the diode is off. The equivalent circuit is shown in Figure 3.17(b). The switch voltage vS and the diode current iD are zero. The voltage across the inductor L is diL , i (0) = 0 dt L (3.111) t t V 1 1 vL dt = VI dt = I t. L ∫0 L ∫0 L (3.112) vL = V I = L and the inductor and switch current is iS = iL = Hence, the peak switch and inductor current is ISM = ΔiL = iL (DT) = VD VI DT = I . L fs L (3.113) The voltage across the diode is vD = −VO . (3.114) Boost PWM DC–DC Converter iD iL L iS + v +vL VI D C RL G V C RL + VO C RL + VO + vD + vS C RL + VO + vS + vGS 111 O (a) iL L + vL + vD iS VI (b) L iL + vL VI iD + vS (c) VI (d) Figure 3.17 PWM boost converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF. Therefore, the diode is off. The energy stored in the magnetic field of the inductor is 2 2 wL (t) = V t 1 2 LiL (t) = I . 2 2L (3.115) This time interval ends when the switch is turned off by the driver. 3.3.2 Time Interval: DT < t ≤ (D + D1 )T The equivalent circuit for this time interval is shown in Figure 3.17(c). The switch is off and the diode is on. Hence, iS = 0 and vD = 0. The voltage across the inductor L is given by vL = V I − V O = L diL < 0. dt (3.116) 112 Pulse-Width Modulated DC–DC Power Converters Using (3.113), the diode and inductor current is t t V − VO 1 1 (t − DT) + iL (DT) vL dt + iL (DT) = (VI − VO )dt + iL (DT) = I L ∫DT L ∫DT L V − VO V DT (t − DT) + I . = I L L The peak diode and inductor current is obtained as iD = iL = DT IDM = ΔiL = (3.117) DT (V − VI )D1 (V − VI )D1 T 1 1 = O . v dt = (V − VO )dt = O L ∫(D+D1 )T L L ∫(D+D1 )T I L fs L (3.118) The voltage across the switch is vS = VSM = VO . (3.119) The energy stored in the magnetic field of the inductor is [ ] DVI 2 1 1 V − VO (t − DT) + wL = Li2L (t) = L I . 2 2 L fs L (3.120) When the diode current reaches zero, this time interval ends. 3.3.3 Time Interval: (D + D1 )T < t ≤ T During this time interval, both the switch and the diode are off. The equivalent circuit is shown in Figure 3.17(d). The inductor current iL , the inductor voltage vL , the switch current iS , and the diode current iD are zero. The voltage across the switch is vS = V I (3.121) vD = V I − V O . (3.122) and the voltage across the diode is This time ends when the switch is turned on by the driver. 3.3.4 Device Stresses for DCM The maximum switch and diode voltage stresses for steady state are VSMmax = VDMmax = VO . (3.123) The maximum steady-state switch and diode current stresses occur at full power and they are ISMmax = IDMmax = ΔiLmax = VImin Dmax . fs L (3.124) 3.3.5 DC Voltage Transfer Function for DCM Referring to Figure 3.18 and using the volt-second balance, VI DT = (VO − VI )D1 T (3.125) leading to MVDC = VO I D = I =1+ . VI IO D1 (3.126) Boost PWM DC–DC Converter vGS 0 T DT t vL VI 0 A+ DT VI − VO A− T t iL ΔiL VI VI −VO L L DT D1T II 0 D2T t DT T t DT T t DT T t DT T iS ISM VI L IS 0 vS VSM = VO VI 0 iD IDM IO = ID 0 vD 0 VI – VO t VDM = – VO Figure 3.18 Idealized current and voltage waveforms in the PWM boost converter for DCM. 113 114 Pulse-Width Modulated DC–DC Power Converters From (3.113) and (3.126), the peak-to-peak inductor current is ΔiL = iL (DT) = VO D VI DT = . L fs LMVDC (3.127) Using (3.126) and (3.127), the dc input current is obtained as an average value of the inductor current II = T D2 VO (D + D1 )DVO (D + D1 )ΔiL 1 iL dt = = = T ∫0 2 2fs LMVDC 2fs L(MVDC − 1) (3.128) VO D2 II = . MVDC 2fs LMVDC (MVDC − 1) (3.129) from which IO = Hence, √ √ D= 2fs LIO MVDC (MVDC − 1) = VO 2fs LMVDC (MVDC − 1) . RL (3.130) At the boundary between CCM and DCM, MVDCB = 1∕(1 − DB ) as in CCM. Therefore, the boundary occurs at 2fs LIO 2f L = s = DB (1 − DB )2 . VO RL (3.131) As the normalized load current is increased from zero to 4fs LIO ∕(27VO ), the boundary duty cycle DB increases from zero to 1/3 and then decreases to zero. Figures 3.19 and 3.20 show plots of the duty cycle D versus the normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of MVDC for both CCM and DCM. 1 MVDC = 10 0.9 5 0.8 3 0.7 D 0.6 CCM 2 DCM 0.5 0.4 1.5 0.3 1.2 0.2 0.1 0 0 0.05 0.1 IO /(VO /2fs L) 0.15 0.2 Figure 3.19 Duty cycle D as a function of normalized load current IO ∕(VO ∕2fs L) at various values of MVDC for the lossless boost converter. Boost PWM DC–DC Converter 115 1 M 0.9 VDC 0.8 0.7 = 10 5 3 D 0.6 0.5 0.4 CCM 2 DCM 1.5 0.3 0.2 1.2 0.1 0 0 10 1 10 2 RL/(2fsL) 3 10 10 Figure 3.20 Duty cycle D as a function of normalized load resistance RL ∕(2fs L) at various values of MVDC for the lossless boost converter. From (3.130), one obtains 2 MVDC − MVDC − D2 RL =0 2fs L (3.132) which produces the dc voltage transfer function of the boost converter for DCM √ √ 2D2 VO 2D2 RL 1+ 1+ 1+ 1+ 3 fs L fs LIO MVDC 2f LI V M −1 R = for L ≥ or s O ≤ VDC . MVDC = O = 3 VI 2 2 2fs L MVDC − 1 VO MVDC (3.133) It can be seen that MVDC depends on D, RL , L, and fs . Figures 3.21 and 3.22 depict plots of MVDC versus IO ∕(VO ∕2fs L) and RL ∕(2fs L) at fixed values of D. Rearrangement of (3.130) produces the inductance required for given values of MVDC , D, RL , and fs L= D2 RL . 2fs MVDC (MVDC − 1) From (3.126) and (3.130), one obtains D1 in terms of D, RL , L, and fs √ 2fs LMVDC D = = √ D1 = MVDC − 1 RL (MVDC − 1) (3.134) 2D 2D2 RL −1 1+ fs L . (3.135) 116 Pulse-Width Modulated DC–DC Power Converters 6 5.5 D = 0.8 5 4.5 0.75 M VDC 4 0.7 3.5 3 CCM 0.6 2.5 DCM 0.5 2 0.3 1.5 1 0 0.05 0.1 I /(V /2f L) O O 0.15 0.2 s Figure 3.21 DC voltage transfer function MVDC as a function of normalized load current IO ∕(VO ∕2fs L) at various values of D for the lossless boost converter. 6 5.5 5 D = 0.8 4.5 MVDC 4 3.5 0.75 0.7 3 2.5 2 1.5 1 0 10 CCM 0.6 DCM 0.5 0.3 1 10 RL/(2fsL) 2 10 Figure 3.22 DC voltage transfer function MVDC as a function of normalized load resistance RL ∕(2fs L) at various values of D for the lossless boost converter. Boost PWM DC–DC Converter 117 3.3.6 Maximum Inductance for DCM The dc output current at the boundary between DCM and CCM occurs at D = DBmin for D < 1∕3 and at D = DBmax for D > 1∕3. Therefore, ⎧V D (1 − DBmin )2 ⎪ O Bmin , 2fs Lmax ⎪ IOBmin = ⎨ 2 ⎪ VO DBmax (1 − DBmax ) , ⎪ 2fs Lmax ⎩ 1 3 for D< for 1 D≥ 3 (3.136) and ⎧R D (1 − DBmin )2 ⎪ Lmin Bmin , for 2fs ⎪ Lmax = ⎨ 2 ⎪ RLmin DBmax (1 − DBmax ) , for ⎪ 2fs ⎩ D< 1 3 (3.137) 1 D≥ . 3 If DBmin < 1∕3 and DBmax > 1∕3, Lmax = RLmin × min{DBmin (1 − DBmin )2 , DBmax (1 − DBmax )2 }. 2fs (3.138) MVDC , MVDC − 1 (3.139) The dwell-duty cycle is Dw = 1 − D − D1 = 1 − D − D MVDC − 1 =1−D yielding 1 − Dw = D MVDC . MVDC − 1 (3.140) Substitution of (3.130) for D gives [ ] (1 − Dw )(MVDC − 1) 2 2fs LMVDC (MVDC − 1) = , MVDC RL (3.141) producing the maximum inductance for a given dwell-duty cycle Lmax = RLmin (1 − Dw )2 (MVDCmax − 1) 3 2fs MVDCmax . (3.142) 3.3.7 Power Losses and Efficiency of Boost Converter for DCM Substitution of (3.133) into (3.127) yields √ DVO VD ΔiL = ISM = IDM = I = = VO fs L fs LMVDC 2(MVDC − 1) 2DVO 1 = √ ( ). fs LRL MVDC fs L 2D2 R 1+ 1+ fLL s (3.143) 118 Pulse-Width Modulated DC–DC Power Converters The rms value of the switch current is √ 1 T ∫0 ISrms = √ DT i2S dt = ΔiL √ √ √ √ √ 2(MVDC − 1)3 2D DVO √ 2 1 D = VO = √ √ 3 3RL fs LRL MVDC ⎛ ⎞ 2 3fs L ⎜1 + 1 + 2D RL ⎟ ⎜ fs L ⎟ ⎝ ⎠ (3.144) resulting in the MOSFET conduction loss 2 PrDS = rDS ISrms = DrDS Δi2L 3 √ 2r = DS 3 4rDS D3 VO2 2(MVDC − 1)3 1 PO = √ ( )2 2 2 fs LRL MVDC 3fs L 2D2 R 1+ 1+ fLL s 4r R D3 = DS2 L2 ( 3fs L (3.145) 1 √ )2 PO . 2D2 RL 1+ 1+ fL s The switching loss in the converter is Psw = fs Co VO2 = fs Co RL PO . (3.146) Likewise, the rms value of the diode current is √ IDrms = (D+D1 )T 1 T ∫DT √ i2D dt = ΔiL √ √ √ √ √ 2(MVDC − 1) D1 D 1 √ 2 = VO = 2VO √ √ 3 3RL fs LRL MVDC 3fs LRL 2D2 R 1+ 1+ fLL s (3.147) which gives the diode conduction loss associated with RF √ 4DRF VO2 D1 RF Δi2L 2RF 2(MVDC − 1) 1 2 PRF = RF IDrms = PO = = √ ( ) 3 3 fs LRL MVDC 3fs LRL 2D2 RL 1+ 1+ fL s 4DRF = ( 3fs L 1 1+ √ 2D2 R 1+ fLL (3.148) ) PO . s The average current through the diode is ID = IO , yielding the diode conduction loss associated with VF PVF = ID VF = IO VF = VF P . VO O (3.149) Therefore, the total diode conduction loss is [ PD = PVF + PRF = √ VF 2RF + VO 3 ⎞ ⎛ ] ⎟ ⎜V 2(MVDC − 1) 4DR 1 F ⎟P . PO = ⎜ F + √ ⎟ O ⎜ VO fs LRL MVDC 3fs L 2D2 RL 1 + f L + 1⎟ ⎜ s ⎠ ⎝ (3.150) Boost PWM DC–DC Converter The rms value of the inductor current is √ √ √ √ √ √ √ (D+D1 )T 2MVDC (MVDC − 1) D + D 1 2D √ 2 1 2 = VO iL dt = ΔiL = VO ILrms = T ∫0 3 3RL fs LRL 3fs LRL 119 (3.151) resulting in the conduction loss in the inductor ESR 2 = PrL = rL ILrms rL (D + D1 )Δi2L 3 √ 2r = L 3 2DrL VO2 2MVDC (MVDC − 1) 2DrL P . PO = = fs LRL 3fs LRL 3fs L O (3.152) The total power loss is √ √ √ 2rDS 2(MVDC − 1)3 2RF 2(MVDC − 1) 2rL 2MVDC (MVDC − 1) + + PLS = PrDS + Psw + PD + PrL = 3 fs LRL MVDC 3 fs LMVDC RL 3 fs LRL ] [ 4rDS RL D3 V 4DRF 1 1 (3.153) + F + fs Co RL PO = + √ ( ) 2 √ VO 3f L 3fs2 L2 ⎛ s 2D2 RL ⎞ 2 1+ 1+ fL ⎜1 + 1 + 2D RL ⎟ s ⎜ ⎟ fs L ⎝ ⎠ ] 2DrL VF + + + fs Co RL PO . 3fs L VO [ and the efficiency can be found to be √ √ [ PO 2rDS 2(MVDC − 1)3 2RF 2(MVDC − 1) PO 1 = = = 1+ + 𝜂= P PI PO + PLS 3 fs LRL MVDC 3 fs LMVDC RL 1 + LS PO √ + 2rL 3 2MVDC (MVDC − 1) VF + + fs Co RL fs LRL VO ]−1 [ 4r R D3 = 1 + DS2 L2 ( 3fs L 1 √ )2 2D2 R 1+ 1+ fLL (3.154) s + 4DRF ( 3fs L 2DrL VF 1 + + fs Co RL √ )+ 3fs L VO 2D2 RL 1+ 1+ fL ]−1 . s Using (3.128), the dc input power is PI = VI II = D2 VI VO 2fs L(MVDC − 1) (3.155) the dc output power is PO = VO2 RL (3.156) and the converter efficiency is 𝜂= PO − 1) 2f LM (M = s VDC2 VDC . PI D RL (3.157) 120 Pulse-Width Modulated DC–DC Power Converters Hence, the duty cycle for the lossy boost converter in DCM is √ √ 2fs LMVDC (MVDC − 1) 2fs LIO MVDC (MVDC − 1) D= = 𝜂RL 𝜂VO (3.158) and the dc voltage transfer function for the lossy boost converter in DCM is √ √ 2𝜂D2 VO 2𝜂D2 R 1+ 1+ fL L 1 + 1 + f LI 3 MVDC s s O 2fs LIO −1 VO M RL = for ≥ or = ≤ VDC . MVDC = 3 VI 2 2 2fs L MVDC − 1 VO MVDC (3.159) 3.3.8 Design of Boost Converter for DCM Example 3.1 Solution: A boost converter has the following parameters: VI = 8–18 V, VO = 24 V, POmax = 48 W, POmin = 0, rL = 0.05 Ω, rC = 0.01 Ω, rDS = 0.055 Ω, Co = 100 pF, RF = 0.025 Ω, VF = 0.3 V, fs = 100 kHz, and Vr ∕VO ≤ 1%. Find component values, component stresses, and the efficiency at full power. At full power, the maximum load current is POmax 48 =2A = VO 24 IOmax = (3.160) and the minimum load resistance is RLmin = VO IOmax = 24 = 12 Ω. 2 (3.161) The minimum and maximum values of the dc voltage transfer function are MVDCmin = VO 24 = 1.333 = VImax 18 (3.162) VO 24 = 3. = VImin 8 (3.163) and MVDCmax = Hence, the minimum and maximum values of the duty cycle at the CCM/DCM boundary are DBmin = 1 − 1 1 = 0.25 =1− MVDCmin 1.333 (3.164) 1 1 2 =1− = . MVDCmax 3 3 (3.165) and DBmax = 1 − The maximum inductances required for DCM operation at DBmax and DBmin are )2 ( 2 2 12 × × 1 − 2 R D (1 − DBmax ) 3 3 L1max = Lmin Bmax = = 4.444 μH 2fs 2 × 105 (3.166) and L2max = RLmin DBmin (1 − DBmin )2 12 × 0.25 × (1 − 0.25)2 = = 8.438 μH 2fs 2 × 105 (3.167) Boost PWM DC–DC Converter 121 resulting in the maximum inductance required for DCM operation under any operating conditions Lmax = min{L1max , L2max } = L1max = 4.444 μH. (3.168) Assuming the dwell-duty cycle Dw = 0.1, we get the maximum inductance L < Lmax = RLmin (1 − Dw )2 (MVDCmax − 1) = 3 2fs MVDCmax 12 × (1 − 0.1)2 (3 − 1) = 3.6 μH. 2 × 105 × 33 (3.169) Let L = 3.3 μ H < Lmax . Assuming 𝜂 = 0.9, the maximum duty cycle at RLmin = 12 Ω and VI = VImin = 8 V is √ √ 2fs LMVDCmax (MVDCmax − 1) 2 × 105 × 3.3 × 10−6 × 3 × (3 − 1) = 0.606 (3.170) = Dmax = 𝜂RLmin 0.9 × 12 and Dmax 0.606 = 0.303 3−1 (3.171) Dmax + D1min = 0.606 + 0.303 = 0.909 < 1 (3.172) Dw = 1 − Dmax − D1min = 1 − 0.909 = 0.0909. (3.173) D1min = MVDCmax − 1 = yielding and The maximum peak switch, diode, and inductor current is ISMmax = IDMmax = ΔiLmax = Dmin VImax 0.606 × 8 = 5 = 14.69 A. fs L 10 × 3.3 × 10−6 The minimum duty cycle at RLmin at RLmin = 12 Ω and V = VImax = 18 V is √ √ 2fs LMVDCmin (MVDCmin − 1) 2 × 105 × 3.3 × 10−6 × 1.333 × (1.333 − 1) = 0.165 = Dmin = 𝜂RLmin 0.9 × 12 (3.174) (3.175) and Dmin 0.165 = 0.495 1.333 − 1 (3.176) Dmin + D1max = 0.165 + 0.495 = 0.66 < 1 (3.177) Dw = 1 − Dmin − D1max = 1 − 0.66 = 0.34. (3.178) D1max = MVDCmin − 1 = producing and The maximum peak switch, diode, and inductor current is ISMmax = IDMmax = ΔiLmax = Dmin VImax 0.165 × 18 = 9 A. = 5 fs L 10 × 3.3 × 10−6 (3.179) The maximum switch and diode voltage stress is VSM = VDM = VO = 24 V. (3.180) The ripple voltage on the output voltage is Vr = 0.01VO = 0.01 × 24 = 0.24 V. (3.181) 122 Pulse-Width Modulated DC–DC Power Converters The peak-to-peak ripple voltage across rC = 0.01 Ω is VrC = rC IDMmax = 0.01 × 14.69 = 0.1469 V. (3.182) Thus, the ripple voltage across the filter capacitance C is VCpp = Vr − VrC = 0.24 − 0.1469 = 0.0931 V. (3.183) Hence, the minimum capacitance is Cmin = Dmax VO 0.606 × 24 = 5 = 130.18 μF. fs RLmin VCpp 10 × 12 × 0.0931 (3.184) Pick C = 150 μF/36 V/ 0.01 Ω. The component power losses will be calculated at VImin = 8 V, RLmin = 12 Ω, POmax = 48 W, and IOmax = 2 A. The conduction loss in the power MOSFET is √ √ 2rDS 2(MVDCmax − 1)3 2 × (3 − 1)3 2 × 0.055 POmax = PrDS = × 48 = 2.043 W. (3.185) 5 3 fs LRLmin MVDCmax 3 10 × 3.3 × 10−6 × 12 × 3 The switching loss is Psw = fs Co VO2 = 105 × 100 × 10−12 × 242 = 5.76 mW. The power loss in the diode forward resistance is √ √ 2(MVDCmax − 1) 2RF 2 × (3 − 1) 2 × 0.025 PRF = P = × 48 = 0.464 W 3 fs LRLmin MVDCmax Omax 3 105 × 3.3 × 10−6 × 12 × 3 (3.186) (3.187) and the power loss in the diode offset voltage source VF is PVF = VF IOmax = 0.3 × 2 = 0.6 W (3.188) PD = PRF + PVF = 0.464 + 0.6 = 1.064 W. (3.189) resulting in the diode conduction loss The power loss in the inductor is √ √ 2rL 2MVDCmax (MVDCmax − 1) 2 × 3 × (3 − 1) 2 × 0.05 POmax = PrL = × 48 = 2.785 W. 5 3 fs LRLmin 3 10 × 3.3 × 10−6 × 12 (3.190) The overall power loss is PLS = PrDS + Psw + PD + PrL = 2.043 + 0.006 + 1.064 + 2.785 = 5.898 W. (3.191) The efficiency of the converter boost for DCM is 𝜂= POmax 48 = 89.06%. = POmax + PLS 48 + 5.898 (3.192) Assuming the gate charge Qg = 50 nC and VDSpp = 8 V, the MOSFET gate-drive power is PG = fs Qg VGSm = 100 × 103 × 50 × 10−9 × 8 = 40 mW. (3.193) Figures 3.23 and 3.28 depict the efficiency 𝜂 and the duty cycle D of the designed boost converter as functions of VI at fixed load resistances RL for DCM. Figures 3.25 and 3.26 show the efficiency 𝜂 and the duty cycle D and of the designed converter as functions of IO and RL at fixed values of VI . Figures 3.28 and 3.27 depict the efficiency 𝜂 and the duty cycle D of the designed boost converter as functions of RL at fixed values of VI . The duty cycle Boost PWM DC–DC Converter 98 97 RL = 48 Ω 96 95 R = 24 Ω η (%) L 94 R = 12 Ω L 93 92 91 90 89 8 10 12 V (V) 14 16 18 I Figure 3.23 Efficiency 𝜂 as a function of VI at fixed values of RL for the boost converter in DCM. 0.6 0.5 R = 12 Ω L D 0.4 R = 24 Ω L 0.3 R = 48 Ω L 0.2 0.1 8 10 12 V (V) 14 16 18 I Figure 3.24 Duty cycle D as a function of VI at fixed values of RL for the boost converter in DCM. 123 Pulse-Width Modulated DC–DC Power Converters 98 97 V I = 18 V 96 η (%) 95 V I = 13 V 94 93 92 91 V =8V I 90 89 0 0.5 1 I (A) 1.5 2 O Figure 3.25 Efficiency 𝜂 as a function of IO at fixed values of VI for the designed boost converter in DCM. 0.6 0.5 V =8V I 0.4 D 124 0.3 V = 13 V I 0.2 V = 18 V I 0.1 0 0.5 1 I (A) 1.5 2 O Figure 3.26 Duty cycle D as a function of IO at fixed values of VI for the boost converter in DCM. Boost PWM DC–DC Converter 98 V = 18 V I 97 96 V I = 13 V 95 η (%) 94 93 VI = 8 V 92 91 90 89 10 15 20 25 30 R (Ω) 35 40 45 50 L Figure 3.27 Efficiency 𝜂 as a function of RL at fixed values of VI of the designed boost converter in DCM. 0.6 0.5 VI = 8 V D 0.4 0.3 V = 13 V I 0.2 V = 18 V I 0.1 10 15 20 25 30 R (Ω) 35 40 45 50 L Figure 3.28 Duty cycle D as a function of RL at fixed values of VI for DCM at fixed values of VI . 125 126 Pulse-Width Modulated DC–DC Power Converters D decreases as VI increases and IO decreases (or RL increases). The efficiency 𝜂 increases as VI increases and 𝜂 decreases as IO increases (or RL decreases). Example 3.2 A boost converter has the following parameters: VI = 10 V, VO = 20 V, POmax = 40 W, POmin = 0, rL = 0.1 Ω, rC = 0.1 Ω, rDS = 0.055 Ω, Co = 100 pF, RF = 0.025 Ω, VF = 0.3 V, fs = 50 kHz, and Vr ∕VO ≤ 5.5%. Find component values, component stresses, and the efficiency at full power. Solution: At full power, the maximum load current is POmax 40 =2A = VO 20 IOmax = (3.194) and the minimum load resistance is VO RLmin = IOmax = 20 = 10 Ω. 2 (3.195) The dc voltage transfer function is MVDC = VO 20 = 2. = VI 10 (3.196) Hence, the duty cycle at the CCM/DCM boundary for MVDC = 2 is 1 1 = 1 − = 0.5. MVDC 2 DB = 1 − (3.197) The maximum inductance required for DCM operation at DB is Lmax = RLmin DB (1 − DB )2 10 × 0.5 × (1 − 0.5)2 = = 12.5 μH. 2fs 2 × 50 × 103 (3.198) Assuming Dmax = 0.4 at full power, one obtains Dmax 0.4 = = 0.4 MVDC − 1 2 − 1 (3.199) Dmax + D1min = 0.4 + 0.4 = 0.8 < 1, (3.200) D1min = and L= D2max RLmin 2fs MVDC (MVDC − 1) = 0.42 × 10 = 8 μH. 2 × 50 × 103 × 2 × (2 − 1) (3.201) Thus, L < Lmax . The maximum peak switch, diode, and inductor current is ISMmax = IDMmax = ΔiLmax = Dmax VI 0.4 × 10 = = 10 A. fs L 5 × 104 × 8 × 10−6 (3.202) The maximum switch and diode voltage stress is VSM = VDM = VO = 20 V. (3.203) The peak-to-peak ripple voltage across rC = 0.1 Ω is VrC = rC IDM = 0.1 × 10 = 1 V. (3.204) The ripple voltage on the output voltage is Vr = 0.055VO = 0.055 × 20 = 1.1 V. (3.205) Boost PWM DC–DC Converter 127 Thus, the ripple voltage across the filter capacitance C is VCpp = Vr − VrC = 1.1 − 1 = 0.1 V. (3.206) Dmax VO 0.4 × 20 = 160 μF. = fs RLmin VCpp 5 × 104 × 10 × 0.1 (3.207) Hence, the minimum capacitance is Cmin = Pick C = 220 μF/36 V/0.1 Ω. The component power losses will be calculated at VI = 10 V, RLmin = 10 Ω, POmax = 40 W, and IOmax = 2 A. The conduction loss in the power MOSFET is √ √ 2rDS 2(MVDC − 1)3 2 × (2 − 1)3 2 × 0.055 POmax = PrDS = × 40 = 0.733 W. (3.208) 3 3 fs LRLmin MVDC 3 50 × 10 × 8 × 10−6 × 10 × 2 The switching loss is Psw = fs Co VO2 = 50 × 103 × 100 × 10−12 × 202 = 2mW. The power loss in the diode forward resistance is √ √ 2(MVDC − 1) 2RF 2 × (2 − 1) 2 × 0.025 × 40 = 0.333 W POmax = PRF = 3 fs LRLmin MVDC 3 50 × 103 × 8 × 10−6 × 10 × 2 (3.209) (3.210) and the power loss in the diode offset voltage source VF is PVF = VF IOmax = 0.3 × 2 = 0.6 W (3.211) PD = PRF + PVF = 0.333 + 0.6 = 0.933 W. (3.212) resulting in the diode conduction loss The power loss in the inductor is √ √ 2rL 2MVDC (MVDC − 1) 2 × 2 × (2 − 1) 2 × 0.1 × 40 = 2.667 W. POmax = PrL = 3 fs LRLmin 3 50 × 103 × 8 × 10−6 × 10 (3.213) The overall power loss is PLS = PrDS + Psw + PD + PrL = 0.733 + 0.002 + 0.933 + 2.667 = 4.335 W. (3.214) The efficiency of the converter is 𝜂= POmax 40 = = 90.22%. POmax + PLS 40 + 4.335 (3.215) 3.4 Bidirectional Buck and Boost Converters Figure 3.29(a) shows the classical boost converter topology with a negative common rail. In the converter of Figure 3.29(b), the inductor and the diode are moved to the negative rail, resulting in the boost converter topology with a positive common rail. Figure 3.29(c) shows the boost converter topology of Figure 3.29(b) flipped so that the positive common rail is at the bottom. A bidirectional buck and boost PWM converter [21] is shown in Figure 3.30. In this circuit, both switches are composed of a transistor and an antiparallel diode. They can conduct current in both directions, but can support 128 Pulse-Width Modulated DC–DC Power Converters L + VI C RL + VO C RL + VO C RL (a) + VI L (b) L VI + VO + (c) Figure 3.29 Derivation of the boost converter topology with a positive common rail. (a) Boost converter with a negative common rail. (b) Boost converter with the inductor and diode moved to the negative rail. (c) Boost converter with a positive common rail at the bottom. the voltage in only one direction. In other words, the switches are bidirectional for the current and unidirectional for the voltage. These are two-quadrant switches, which permit energy flow in both directions, from left to right, and vice versa. If a dc voltage source V1 is connected in parallel with the capacitor C1 and a load is connected in parallel with the capacitor C2 , the buck converter is obtained. In this case, the energy flows from left to right. The horizontal MOSFET channel is used as a controllable switch and its antiparallel diode is permanently off, whereas the vertical diode is used as a passive (naturally commutated) switch. The channel of the vertical MOSFET can be held permanently off or it can be turned on by a driver, when the vertical diode is on. In contrast, if a dc voltage source V2 is connected in parallel with the capacitor C2 and a load is connected in parallel with the capacitor C1 , the boost converter is obtained. Then, the energy flows from right to left. The channel of the vertical MOSFET is used as a controllable switch and its antiparallel diode is always off, whereas L V1 Figure 3.30 C1 C2 V2 < V1 Bidirectional buck and boost PWM converters. Boost PWM DC–DC Converter 129 L S1 D1 S3 D3 n:1 C VI RL + VO S4 S2 D2 Figure 3.31 D4 Isolated boost PWM converter. the horizontal diode is used as a passive switch. The channel of the horizontal MOSFET can be kept in the off-state during the whole cycle or it can be turned on, when the horizontal diode is on. Figure 3.31 shows an isolated boost converter. It consists of inductor L, full-bridge inverter, high-frequency transformer, bridge rectifier, and a filter capacitor. The circuit can operate as either a noninverting or inverting converter and it is suitable for high-power applications. 3.5 Synchronous Boost Converter Figure 3.32 shows a synchronous boost converter. In this circuit, the diode is replaced by a MOSFET. Assuming that both transistors have the same on-resistance rDS , the efficiency of the synchronous converter is 𝜂= PO = PI r +r +D(1−D)rC 1 + L DS (1−D)RL 1 . [ ( )2 ] ΔiL 1 1 + 12 I + fs Co RL (3.216) O The dc voltage transfer function of this converter is MVDC = VO = VI 1 [ ]. ( )2 ] r +r +D(1−D)rC ΔiL 1 1 + + f (1 − D) 1 + L DS C R s o L (1−D)R 12 I [ L (3.217) O 3.6 Tapped-Inductor Boost Converters A tapped-inductor common-transistor (CT) boost converter [13] is shown in Figure 3.33(a). It is a high step-up converter. The voltage transfer function of the tapped inductor is n= Np + Ns N v = =1+ s. vp Np Np (3.218) L 1 D VI D Figure 3.32 C R + VO Synchronous boost PWM converter. 130 Pulse-Width Modulated DC–DC Power Converters v + Np + vp Ns + vs VI + VO RL C (a) + v VI Np + vp + vs C RL + VO Ns C RL + VO Ns (b) + v VI Np + vp + vs (c) Figure 3.33 Tapped-inductor boost converters. (a) Tapped-inductor common-transistor boost converter. (b) Tappedinductor common-diode boost converter. (c) Tapped-inductor common-load boost converter. When the MOSFET is on and the diode is off, vp = V I . (3.219) v = VI − VO = nvp (3.220) When the MOSFET is off and the diode is on, resulting in vp = VI − VO . n (3.221) Using the volt-second balance for the Np winding across which the voltage is vS , VI DT = − VI − VO (1 − D)T. n (3.222) Hence, the dc voltage transfer function of the tapped-inductor common-transistor configuration operating in CCM is given by MVDC = VO nD + 1. = VI 1−D (3.223) Boost PWM DC–DC Converter 131 10 n = 10 8 5 MVDC 6 2 1 4 2 0 Figure 3.34 0 0.25 0.5 D 0.75 1 DC voltage transfer function of tapped-inductor common-transistor boost converter for CCM. Plots of MVDC as a function of D for CCM are shown in Figure 3.34. The magnetizing inductance Lm on the terminals of the winding Np is given by ( Lm = Np )2 Np + Ns L (3.224) where L is the total inductance of winding Lp + Ls . 3.6.1 Tapped-Inductor Common-Diode Boost Converter A tapped-inductor common-diode (CD) boost converter is shown in Figure 3.33(b). When the MOSFET is off and the diode is on, v = VI = nvp (3.225) resulting in vp = VI . n (3.226) When the MOSFET is off and the diode is on, vp = V I − V O (3.227) Using the volt-second balance for the inductance Lp across which the voltage is vp , VI DT = (VO − VI )(1 − D)T n (3.228) 132 Pulse-Width Modulated DC–DC Power Converters 10 8 MVDC 6 n=1 4 2 5 10 2 0 Figure 3.35 0 0.25 0.5 D 0.75 1 DC voltage transfer function of tapped-inductor common-diode boost converter for CCM. we obtain the dc voltage transfer function of the tapped-inductor common-diode in CCM MVDC = VO D + 1. = VI n(1 − D) (3.229) Figure 3.35 shows plots of MVDC as a function of D for CCM. 3.6.2 Tapped-Inductor Common-Load Boost Converter A tapped-inductor common-load (CL) boost converter is shown in Figure 3.33(c). It is an inverse Watkins–Johnson (IWJ) converter [21]. When the MOSFET is on and the diode is off, v (3.230) vp = V I − V O = n resulting in v = nvp = n(VI − VO ). (3.231) When the MOSFET is off and the diode is on, v s = V O = v − vp = v − n−1 v =v n n (3.232) producing v = VO n . n−1 (3.233) Applying the volt-second balance, n(VI − VO )DT = −VO n (1 − D)T. n−1 (3.234) Boost PWM DC–DC Converter 133 5 5 M VDC 4 n = 1.2 2 3 2 1 Figure 3.36 0 0.25 0.5 D 0.75 1 DC voltage transfer function of tapped-inductor common-load (IWJ) boost converter for CCM. Hence, we obtain the dc voltage transfer function of the tapped-inductor common-load boost converter MVDC = VO D(n − 1) = VI nD − 1 for D> 1 . n (3.235) Plots of MVDC as a function of D for the tapped-inductor common-diode boost converter operating in CCM are shown in Figure 3.36. 3.7 Duality In order to use the duality principles for dc–dc converters, it is useful to introduce the following simplifications: (1) An inductor in series with a parallel combination of filter capacitor and a load resistance (or the inductor in series with a load resistance) can be replaced by a dc current sink. (2) A filter capacitor in parallel with a resistor can be replaced by a voltage source. (3) A dc source in series with an inductor can be replaced by a dc current source. The duality principles in dc–dc converter are as follows: (1) (2) (3) (4) (5) (6) Replace a dc voltage source by a dc current source. Replace a series switch by a parallel switch, and vice versa. Replace a parallel diode by a series diode, and vice versa. Replace a dc current sink by a dc voltage source. Replace a dc voltage sink by a dc current source. ′ Replace the on-duty cycle D by the off-duty cycle D = 1 − D. 134 Pulse-Width Modulated DC–DC Power Converters L VI C RL + VO (a) IO VI (b) II VO (c) L VI C RL + VO (d) Figure 3.37 Derivation of the boost converter from the buck converter, or vice versa, using the duality principles. Figure 3.37 shows the derivation of the boost converter from the buck converter, or vice versa, using the duality principles. 3.8 Power Factor Correction 3.8.1 Power Factor The power factor describes the effectiveness of energy transmission from a source to a load. It indicates the power utilization efficiency. The loads can be resistive or reactive, and linear or nonlinear. Nonlinear loads generate current harmonics, which are injected into the utility power system, degrading it. Reactive components of the load impedance cause a phase shift between load current and voltage. If the power factor PF is low, the energy transmission loss is higher and the power station must produce more power to satisfy the needs of various loads. Thus, green energy requires a high-quality energy with a high power factor PF. Universal ac–dc power supplies of electronic systems should be designed to accept any level of utility voltage used in the world, which are in the range from 92 to 264 Vrms. A low utility line voltage in the United States is Boost PWM DC–DC Converter 135 is + vs VO ~ C RL + VO 0 Figure 3.38 t Full-wave peak rectifier. 92 Vrms and a high utility line voltage in Europe is 264 Vrms. Universal power supplies must satisfy IEC 61000-3-2 Class C regulation, IEC555-2 line harmonic standard, and VDE 0871B conducted emission standard. Information technology equipment must comply with EMI standards, such as CISPR-22, which determines the limits of the EMI noise generated in the frequency range from 150 kHz to 300 MHz. Conventional peak rectifiers contain a full-wave bridge rectifier followed by a large storage and filter capacitor, as shown in Figure 3.38. The diodes in these rectifiers conduct current for a very short portion of a cycle. The conduction angle of the diode current is very small because the filter capacitor remains charged at or near the peak ac voltage during each cycle. As a result, the rectifier diodes are reverse biased most of the time and no current flows. The unidirectional diode currents are reflected to the input of the front-end rectifier and form the line current waveform is composed of very narrow positive and negative pulses, as shown in Figure 3.39. Therefore, the input current waveform of peak rectifiers with capacitive filters consists of half-sine wave pulses and contains a lot of odd harmonics, up to the 25th harmonic. In addition, the phase shift 𝜙 between the fundamental components of the utility voltage and current gives cos 𝜙 = 0.6–0.8. Usually, THD > 130%, resulting in a very low power factor, usually, PF < 0.6. Power supplies must comply with power quality regulations, such as IEC 61000-3-2 Class C. The power factor is defined as ratio of the real power to the apparent power ∑∞ Pn Preal Time Average Real Power P Real Power PF = = n=1 = = = √ |S| Apparent Power (RMS Current) (RMS Voltage) I V rms rms P2real + P2rective ∑∞ n=1 Irms(n) Vrms(n) cos 𝜙n = √ , (3.236) ∑∞ 2 ∑∞ 2 n=1 Irms(n) n=1 Vrms(n) vs, is vs is 0 Figure 3.39 π 2π ωt Line voltage and current loaded by a full-wave peak rectifier. 136 Pulse-Width Modulated DC–DC Power Converters where the real power, called the average power or the time-average power, is given by P= the apparent power is √ |S| = 1 2𝜋 ∫0 1 2𝜋 ∫0 2𝜋 pd(𝜔t) = √ 2𝜋 v2 d(𝜔t) 1 2𝜋 ∫0 2𝜋 1 2𝜋 ∫0 2𝜋 vid(𝜔t)(W) √( )( ∞ ) √ ∞ √ 1∑ ∑ 1 √ = Vrms Irms i2 d(𝜔t) = V2 I2 2 n=1 mn 2 n=1 mn (3.237) (3.238) p = vi is the instantaneous power, and S = VI∗ = |S|e𝜙 is the complex power. Only the real power produces real work. Let us assume that the utility line voltage is purely sinusoidal √ vs = 2Vrms1 sin 𝜔t. (3.239) In general, the utility line current waveform is periodic and nonsinusoidal, which can be represented by a Fourier series √ √ √ (3.240) is = 2Irms1 sin(𝜔t + 𝜙1 ) + 2Irms2 sin(2𝜔t + 𝜙2 ) + 2Irms3 sin(3𝜔t + 𝜙3 ).... The rms value of the line ac current is Irms = The total harmonic distortion is defined by THD = √ 2 2 2 Irms1 + Irms2 + Irms3 + .... √ 2 2 2 Irms2 + Irms3 + Irms4 + ... Irms1 (3.241) . (3.242) The power factor for a sinusoidal voltage and a nonsinusoidal current is defined as PF = cos 𝜙1 V I I Irms1 P = rms1 rms1 = rms1 cos 𝜙1 = √ cos 𝜙1 Vrms Irms Vrms1 Irms Irms 2 2 2 Irms1 + Irms2 + Irms3 + ... = √ 1 1 + THD2 cos 𝜙1 = FDF FDA (3.243) where the distortion factor or the current distortion factor is FDF = Irms1 1 = √ Irms 1 + THD2 (3.244) and the displacement angle or the displacement factor is FDA = cos 𝜙1 . (3.245) The distortion factor FDF as function of THD is shown in Figure 3.40. Usually, for line rectifiers, 𝜙1 = 0 and the power factor becomes PF = Irms1 Irms1 1 = √ = √ . Irms 2 2 2 1 + THD2 Irms1 + Irms2 + Irms3 + ... (3.246) The range of PF is from 0 to 1. For perfect energy transmission from a source to a load, a unity power factor (PF = 1) is required. In this case, the load presented by an electric circuit to the utility line behaves like a linear Boost PWM DC–DC Converter 137 1 0.95 FDF 0.9 0.85 0.8 0.75 0.7 0 0.2 Figure 3.40 0.4 THD 0.6 0.8 1 Distortion factor FDF as a function of THD. resistance. When the rms values of current harmonics are zero, THD = 0 and PF = 1 (at cos 𝜙1 = 1). The total harmonic distortion (THD) in terms of the power factor PF is √ 1 THD = − 1. (3.247) PF 2 The rms value of input current of an ac–dc power converter with the output power PO and efficiency 𝜂 is Irms = PO . Vrms 𝜂PF (3.248) As off-line ac–dc converters deliver increasing amounts of power, power factor correction (PFC) becomes of great interest to both manufacturers and users. The line current, although in phase with the ac line voltage, is often nonsinusoidal with high peak values, placing high stress on circuit breakers, fuses, wall sockets, installation wires, and transformers. Since wall sockets are being pushed to their limit, safety becomes an important issue. In the United States, a typical office has a 15 A/110 V wall plug, which cannot be run at more than 80% of its rating according to the UL regulation. The maximum current drawn from the line is 12 Arms. Line voltages sag and become distorted. Also, there is an increased power loss in the transmission line resistance because a larger rms current is required for a given real power P at PF < 1. Since power companies want to minimize the power loss in the transmission lines, they want the customers to have a power factor as close to 1 as possible. For this reason, they will provide penalties or price incentives to encourage the users to reduce the cost of energy transmission. A typical value of the power factor for single-phase 110/220 Vrms lines is 0.65, but it can go as low as 0.49, depending on the front-end rectifier and the line impedance, which is in the range from 0.1 to 1.5 Ω. The apparent power becomes much larger than the real power when the power factor is poor. Rising power quality requirements and the proliferation of electronic equipment are demanding that off-line converters incorporate PFC. There are passive and active power factor correctors. Passive PFCs use a large input choke. If a choke inductance is large enough, a PFC of 0.9 is possible. However, such chokes tend to be very large and heavy, reducing the power density. A 138 Pulse-Width Modulated DC–DC Power Converters is + vs VO ~ + VO RL 0 Figure 3.41 t Full-wave rectifier without filter capacitor. full-wave rectifier without a large filter capacitor shown in Figure 3.41 has a sinusoidal line current, but its output voltage is not constant. This fact can be used for designing PFCs. 3.8.2 Boost Power Factor Corrector The circuit of a single-phase boost power factor corrector is depicted in Figure 3.42. It consists of a front-end rectifier and a boost PWM dc–dc converter. The rectifier does not contain a large filter capacitor to reduce the linefrequency voltage ripple. It usually contains a small filter capacitor at the output to reduced a switching-frequency current component generated by the boost converter. Current and voltage waveforms in the boost power factor corrector are shown in Figure 3.44. The rectifier output voltage |vs | is a full-wave rectified sinusoid. The minimum √ value of the peak rectified voltage for the low US utility line is Vpk(min) = 2 × 92 = 130 V and the maximum value √ of the peak rectified voltage for the high European utility line is Vpk(max) = 2 × 264 = 373 V. The time-dependent rectified voltage |vs | is converted into a dc voltage VO . A control circuit forces the inductor current iL of the boost converter to follow a full-wave rectified sinusoidal reference voltage |vs |. Since the boost converter is a step-up converter, the output voltage VO must be higher than the maximum value of the voltage |vs |, that is, VO > 373 V. Various dc voltages are derived from the dc voltage VO , using dc–dc converters. Figure 3.44 shows a complete ac-to-dc converter. It consists of an EMI filter, full-wave rectifier, and a boost power-factor corrector. The line voltage is sinusoidal and is given by vs = Vm sin 𝜔t. (3.249) The voltage at the output of the front-end full-wave rectifier is |vs | = Vm | sin 𝜔t|. iL is vs ~ + vs Figure 3.42 (3.250) iD L C RL Boost power factor corrector. + VO Boost PWM DC–DC Converter Boost Converter EMI Filter iL LDM vs ~ CDM + CCM LCM CDM LCM 139 iD L vs C RL + VO CCM LDM Figure 3.43 Boost power factor corrector. The voltage transfer function is M(t) = VO VO 1 = = |vs | Vm | sin 𝜔t| 1 − D(t) (3.251) |vs | V | sin 𝜔t| =1− m . VO VO (3.252) resulting in the duty cycle D(t) = 1 − Figure 3.45 shows the waveforms of the duty cycle D(t) in the boost power factor corrector at VO = 400 V for a half of a cycle of the line frequency at Vrms = 90 V and Vrms = 264 V. The maximum value of the duty cycle is 1 and occurs Vo , vs , iL Vo vs iL 0 (a) vs , is ωt vs is 0 ωt (b) Figure 3.44 Waveforms in the boost power factor corrector for a cycle of the line frequency. (a) Waveforms of the rectified line voltage |vs |, output voltage VO , and inductor current iL . (b) Waveform of the line voltage vs and line current is . 140 Pulse-Width Modulated DC–DC Power Converters 1 0.9 0.8 0.7 D(t) 0.6 0.5 0.4 0.3 0.2 Vs = 90 V(rms) 0.1 0 Vs = 264 V(rms) 0 20 40 60 80 100 120 140 160 180 ω t (o) Figure 3.45 Waveforms of the duty cycle D(t) in the boost power factor corrector at VO = 400 V for a half of a cycle of the line frequency at Vrms = 90 V and Vrms = 264 V. at 𝜔t = 0, 𝜋, and 2𝜋. The minimum value of the duty cycle is Dmin = 1 − Vsm ∕VO and occurs √ √ at 𝜔t = 𝜋∕2 and 3𝜋∕2. For Vrms = 90 V, Dmin = 1 − 2 × 90∕400 = 0.6818 and for Vrms = 264 V, Dmin = 1 − 2 × 264∕400 = 0.06666. The inductor current is shaped to have a full-wave rectified waveform iL = ILm | sin 𝜔t|. (3.253) is = Ism sin 𝜔t = ILm sin 𝜔t. (3.254) The input current of the rectifier is Thus, the boost converter represents a resistive load to the utility line, yielding THD = 0 and FDF = 1. The line current is in phase with the line voltage, yielding FDA = cos 𝜙1 = 1. Thus, PF = 1. The diode current waveform is ) ( Vsm | sin 𝜔t| V I ILm | sin 𝜔t| = sm Lm sin2 𝜔t. (3.255) iD = [1 − D(t)]iL = 1 − 1 + VO VO Since sin2 𝜔t = 1 1 − cos 2𝜔t 2 2 (3.256) we obtain iD = 1 Vsm ILm 1 Vsm ILm − cos 2𝜔t = ID − id . 2 VO 2 VO (3.257) Boost PWM DC–DC Converter 141 is + vs L ~ L C C1 C2 Figure 3.46 Electronic ballast with boost active power factor corrector for fluorescent lamps [16]. The dc component of the diode current ID flows through the load and nearly all of the second harmonic of the diode current id flows through the output filter capacitor C. The ac component of the voltage across the filter capacitor is vAC = 1 𝜔C ∫0 𝜔t id d(𝜔t) = − 1 Vsm ILm 2 𝜔CVO ∫0 𝜔t cos 2𝜔td(𝜔t) = − Vsm ILm sin 2𝜔t = −VCm(AC) sin 2𝜔t (3.258) 4𝜔CVO where amplitude of the second harmonic of the output voltage is VCm(AC) = Vsm ILm V I = sm sm . 4𝜔CVO 4𝜔CVO (3.259) Hence, the filter capacitance is Cmin = Ps(max) Vsm Ism = 4𝜔VO VCm(AC) 2𝜔VO VCm(AC) (3.260) where the maximum power drawn from the line is Ps(max) = 1 V I . 2 sm sm (3.261) 3.8.3 Electronic Ballasts for Fluorescent Lamps Figure 3.46 shows an application of the boost active power factor corrector in an electronic ballast for fluorescent lamps [16]. The dc output voltage of the boost PFC supplies a Class-D half-bridge dc-to-ac high-frequency resonant inverter. When the voltage at the input of the front-end rectifier is turned-on, the plasma in the fluorescent lamp off, the lamp resistance is infinity, and the voltage across the lamp increases until the plasma is ignited. Then the lamp resistance decreases and the voltage across the lamp also decreases. The lamp remains on until the switch of the utility voltage is turned-off, producing a healthy light, free of flickering. This instant-start ballast. The efficiency of fluorescent lamps is about 5–6 times higher than that of the incandescent lamps. Active power factor correctors are widely used in power supplies. 3.9 Summary r r r r r The boost converter is a step-up circuit. It has only a transformerless version. It can be operated either in CCM or DCM. Its advantage is that the input current has a continuous (nonpulsating) waveform. It is easy to drive the MOSFET in the boost converter because the gate is referenced to ground. 142 Pulse-Width Modulated DC–DC Power Converters r If losses are neglected, the dc voltage transfer function for CCM is M VDC = VO ∕VI = 1∕(1 − D). It increases from 1 to ∞ as D is increased from 0 to 1. r The dc voltage transfer function of the lossy converter is lower than that of the lossless converter at the same duty cycle D. The difference is especially significant at the duty cycle D close to 1. r As D is increased from 0 to 1, the dc voltage transfer function of the lossy boost converter initially increases, reaches its maximum value, and then decreases back to 0. r The converter should not be used at D close to 1 because of its poor efficiency. r The peak-to-peak current through the filter capacitor is very high; it is equal to the peak-to-peak value of the diode current IDM . r It is easy to drive the MOSFET because the gate is referenced to ground. r The dc voltage transfer function M VDC depends on the inductance L for DCM, and it is independent of L for CCM. r For the boost converter operating in CCM, the maximum efficiency occurs at full load I Omax (or RLmin ) and at the maximum dc input voltage VImmax . r For the boost converter operating in CCM, the minimum efficiency occurs at full load I Omax (or RLmin ) and at the minimum dc input voltage VImin . References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. [3] K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. [4] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [5] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York, NY: Van Nostrand, 1985. [6] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [7] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Upper Saddle River, NJ: Prentice Hall, 2004. [8] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [9] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [10] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. [11] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [12] B. M. Bird, K. G. King, and D. A. G. Pedder, An Introduction to Power Electronics. New York: John Wiley & Sons, 1993. [13] R. D. Middlebrook, “A continuous model for tapped-inductor boost converter,” Proceedings of the IEEE Power Electronics Specialists Conference, Culver City, CA, June 9–11, 1975, pp. 63–79. [14] S. Ćuk and R. D. Middlebrook, “Coupled-inductor and other extensions of a new optimum topology switching dc-dc converter,” IEEE IAS Conference, 1977, pp. 1110–1126. [15] B. W. Dishner, “Boost/buck dc/dc converter,” US Patent 4,801,859, January 31, 1989. [16] M. K. Kazimierczuk and W. Szaraniec, “Electronic ballast for fluorescent lamps,” IEEE Transactions on Power Electronics, vol. 8, pp. 386–395, October 1993. [17] D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. [18] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. [19] I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. [20] A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. [21] D. A. Grant and Y. Darroman, “Inverse Watkins-Johnson converter − analysis reveals its merits,” Electronics Letters, vol. 39, no. 18, pp. 1342–1343, September 4, 2003. Boost PWM DC–DC Converter 143 Review Questions 3.1 What is the range of the dc voltage transfer function for the lossless and lossy boost PWM converter? 3.2 How does the efficiency of the boost converter depend on the duty cycle? 3.3 Is it easy to obtain a low ripple voltage in the boost PWM converter? 3.4 Is the current flowing into the filter capacitor and the load continuous in the boost PWM converter? 3.5 Is the input current of the boost PWM converter pulsating? 3.6 Are both halves of the B–H curve of the inductor core used in the boost PWM converter? 3.7 Is the corner frequency fo dependent on the load resistance RL in the boost converter? 3.8 Is the efficiency high at heavy or light loads for the boost converter? 3.9 Does the maximum power loss in each component of the boost converter occur at the minimum or the maximum duty cycle? 3.10 What is the complex power? 3.11 What is the apparent power? 3.12 What is the power factor? 3.13 What is the total harmonic distortion? 3.14 Draw the circuit of the boost power factor corrector and explain its principle of operation. Problems 3.1 Derive an expression for the dc voltage transfer function MVDC of a lossless boost converter using the steady-state condition for the inductor current. 3.2 A boost PWM converter has the following data: VI = 125–350 V, VO = 380 V, PO = 6.8–68 W, and fs = 50 kHz. Compute the voltage and current stresses of the transistor and the diode. 3.3 A boost PWM converter has the following data: VI = 8–16 V, VO = 24 V, IO = 0.2–2 A, and fs = 200 kHz. Calculate the minimum inductance required for the converter operation in CCM. Assume 𝜂 = 90%. 3.4 A boost PWM converter has the following data: VI = 8–12 V, VO = 24 V, IO = 0.2–2 A, and fs = 200 kHz. Calculate the minimum inductance required for the converter operation in CCM. Assume 𝜂 = 90%. 3.5 A boost PWM converter is operated in CCM at VI = 14 V and VO = 28 V. Find the required duty cycle D for the converter efficiency (a) 𝜂 = 100% and (b) 𝜂 = 80%. 3.6 A boost PWM converter employs a power MOSFET with an on-resistance rDS = 0.02 Ω. The load current is IO = 10 A. Calculate the transistor conduction loss at D = 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9. 3.7 A boost PWM converter employs a diode with a forward resistance RF = 0.02 Ω. The load current is IO = 10 A. Calculate the diode conduction loss due to the forward resistance RF at D = 0.1, 0.2, 0.5, 0.8, and 0.9. 3.8 A boost PWM converter employs an inductor with a dc resistance rL = 0.02 Ω. The load current is IO = 10 A. Calculate the inductor loss at D = 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9. 144 Pulse-Width Modulated DC–DC Power Converters 3.9 For the boost converter with VI = 8–16 V, VO = 24 V, IO = 0.2–2 A, and fs = 200 kHz, find the maximum inductance required to maintain the converter in DCM. √ √ 3.10 Design a boost PWM converter with the following specifications: VImin = 90 2 V, VImax = 240 2 V, VO = 400 V, IO = 0.2–2 A, Vr ∕VO ≤ 1%, rL = 2.5 Ω, rDS = 1 Ω, Co = 100 pF, RF = 25 m Ω, VF = 0.7 V, rC = 50 m Ω, and fs = 50 kHz. Find L, C, and 𝜂. 3.11 Design a boost PWM converter to meet the following specifications: VImin = 25 V, VInom = 28 V, VImax = 31 V, VO = 270 V, RLmin = 462 Ω, RLmax = 518 Ω, fs = 25 kHz, Vr ∕VO ≤ 1%, VF = 1.5 V, RF = 0.188 Ω, rDS = 0.3 Ω, Co = 400 pF, rL = 0.21 Ω, and rC = 0.1 Ω. Find L, C, ISM , VSM , and 𝜂. 3.12 Design a boost converter to meet the following specifications: VI = 24±4 V, VO = 48 V, IO = 0.2 to 2 A, Vr ∕VO ≤ 1%, fs = 100 kHz, rDS = 0.2 Ω, rL(dc) = 0.25 Ω, RF = rC = 25 m Ω, VF = 0.8 V, and Co = 250 pF. Find L, C, ISM , VSM , and 𝜂. 3.13 Design a boost converter to meet the following specifications: VI = 10–24 V, VO = 28 V, IO = 0.5–1 A, Vr ∕VO ≤ 1%, fs = 100 kHz, rDS = 0.2 Ω, rL(dc) = 0.11 Ω, rC = 25 m Ω, RF = 25 m Ω, VF = 0.3 V, and Co = 150 pF. Find L, C, ISM , VSM , and 𝜂. 3.14 Design a boost converter to meet the following specifications: VI is the US single-phase rectified utility line, VO = 400 V, IO = 0–0.225 A, Vr ∕VO ≤ 1%, fs = 100 kHz, rDS = 1 Ω, Co = 150 pF, Qg = 27 nC, rL = 2.1 Ω, rC = 0.25Ω, RF = 17.1 m Ω, and VF = 0.7 V, and Co = 150 pF. Find L, C, ISM , VSM , and 𝜂. 3.15 Design a boost converter for photovoltaic applications to meet the specifications: VI = 1.5 ± 0.5 V, VO = 5 V, IO = 0.2–4 A, Vr ∕VO ≤ 2%, and fs = 250 kHz. 4 Buck–Boost PWM DC–DC Converter 4.1 Introduction This chapter covers the buck–boost PWM switching-mode converter [1–21]. The circuit of the converter is described. The current and voltage waveforms for various components are derived. The device stresses are found. The dc voltage transfer function is determined. An expression for the minimum inductance is derived from the condition for the boundary between CCM and DCM. A design equation for the filter capacitor is developed from the ripple voltage requirement. Power losses in all devices and the overall efficiency are estimated. Illustrative design examples are given for both CCM and DCM. Finally, the buck–boost converter is derived from the buck and boost converters. 4.2 DC Analysis of PWM Buck–Boost Converter for CCM 4.2.1 Circuit Description The circuit of the PWM buck–boost dc–dc converter [1–21] is shown in Figure 4.1(a). It consists of a power MOSFET used as a controllable switch, an inductor L, a diode, a filter capacitor C, and a load resistor RL . The switch is turned on and off at the switching frequency fs = 1∕T with the on duty ratio D = ton ∕T, where ton is the time interval when the switch is on. It is difficult to drive the transistor because source is not connected to ground. Therefore, the driver is floating as neither end is connected to ground. Two modes of operation exist: CCM and DCM. Figures 4.1(b) and (c) show equivalent circuits of the buck–boost converter for CCM when the switch is on and the diode is off, and when the switch is off and the diode is on, respectively. The principle of operation of the buck–boost converter is explained by the idealized waveforms of the currents and voltages shown in Figure 4.2. During the time interval 0 < t ≤ DT, the switch is on and the diode is off as indicated in Figure 4.1(b). The voltage across the diode is −(VI + VO ) and maintains the diode in the off-state. The voltage across the inductor is VI and gives rise to a linear increase in the inductor current with a slope of VI ∕L. During time interval DT < t ≤ T, the switch is off and the diode is on as shown in Figure 4.1(c). The voltage across the inductor is −VO and causes the inductor current to decrease linearly with a slope of −VO ∕L. The voltage across the switch is VI + VO . At time t = T, the switch is turned on again and the next cycle begins. Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 146 Pulse-Width Modulated DC–DC Power Converters iS iD vGS + VI iL C L RL VO + C RL VO + C RL VO + (a) iS iL L VI + vL vD + (b) iD iL + vS VI L vL (c) Figure 4.1 PWM buck–boost converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. 4.2.2 Assumptions The analysis of the buck–boost PWM converter of Figure 4.1(a) is based on the following assumptions: (1) The power MOSFET and the diode are ideal switches. (2) The transistor output capacitance and the diode capacitance as well as lead inductances (and thereby switching losses) are zero. (3) Passive components are linear, time invariant, and frequency independent. (4) The output impedance of the input voltage source VI is zero for both dc and ac components. 4.2.3 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch is on and the diode is off. An ideal equivalent circuit for this time interval is shown in Figure 4.1(b). When the switch is on, the voltage across the diode vD is approximately equal to −(VI + VO ), causing the diode to be reverse biased. The voltage across the switch vS and the diode current iD are zero. The voltage across the inductor L is given by vL = V I = L diL . dt (4.1) Hence, one obtains the current through the inductor L and the switch iS = iL = t t V 1 1 vL dt + iL (0) = V dt + iL (0) = I t + iL (0) L ∫0 L ∫0 I L (4.2) Buck–Boost PWM DC–DC Converter vGS 0 DT T t T t vL VI A+ 0 A− DT VO iL II + IO VI VO L L II + IO = IO 1− D ILM 0 DT T t DT T t DT T t DT T t DT T iS ISM II IS 0 vS VSM VI + VO VI 0 iD IDM IO 0 vD 0 t VO (VO +VI ) Figure 4.2 Idealized current and voltage waveforms for the PWM buck–boost converter for CCM. 147 148 Pulse-Width Modulated DC–DC Power Converters where iL (0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes iL (DT) = VI DT VD + iL (0) = I + iL (0) L fs L (4.3) and the peak-to-peak value of the ripple current through the inductor L is ΔiL = iL (DT) − iL (0) = VD VI DT = I . L fs L (4.4) It will be shown shortly that the dc voltage transfer function is MVDC = VO ∕VI = II ∕IO = D∕(1 − D). Hence, we can find the diode voltage ( ) V 1 vD = −(VI + VO ) = −VO (4.5) +1 = − O. MVDC D The average value of the inductor current IL is equal to the sum of the dc input current II and the dc output current IO . Hence, one arrives at the peak value of the switch current ISM ISM = IL(peak) = II + IO + I Δi ΔiL = O + L. 2 1−D 2 (4.6) An increase of the magnetic energy in the inductor L is ΔWL(in) = 1 2 L[i (DT) − i2L (0)]. 2 L (4.7) This time interval is terminated at t = DT when the switch is turned off by an external driver. The inductor current iL is a continuous function of time. Since iL (DT) is nonzero when the switch turns on, the inductor acts as a current source, thus turning the diode on. 4.2.4 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch is off and the diode is on. Figure 4.1(c) shows an ideal equivalent circuit for this time interval. The switch current iS and the diode voltage vD are zero. The voltage across the inductor L is vL = −VO = L diL . dt (4.8) Hence, one obtains the current through the inductor L and the diode t iD = iL = =− t 1 1 v dt + iL (DT) = (−VO )dt + iL (DT) L ∫DT L L ∫DT V VO VD (t − DT) + iL (DT) = − O (t − DT) + I + iL (0) L L fs L (4.9) where iL (DT) is the initial current of the inductor L at t = DT. The peak-to-peak value of the ripple current through the inductor L is ΔiL = iL (DT) − iL (T) = VO T(1 − D) VO (1 − D) = . L fs L (4.10) Since VO ∕VI = D∕(1 − D), the voltage across the switch is given by vS = VSM = VI + VO = VO D (4.11) Buck–Boost PWM DC–DC Converter 149 resulting in a maximum value of the peak voltage across the switch and the diode VSMmax = VDMmax = VImax + VO = VO . Dmin (4.12) The peak diode and switch currents are IDM = IL(peak) = II + IO + I Δi ΔiL = O + L. 2 1−D 2 (4.13) I ΔiLmax Δi = Omax + Lmax . 2 1 − Dmax 2 (4.14) The maximum values of the peak currents are IDMmax = ISMmax ≈ IImax + IOmax + Note that the maximum dc input current occurs at Dmax , whereas the maximum peak-to-peak ripple current of the inductor occurs at Dmin . The “off” time interval ends at t = T when the switch is turned on by an external driver. The decrease in the magnetic energy stored in inductor L during interval DT < t ≤ T is ΔWL(out) = ] 1 [2 L iL (DT) − i2L (T) . 2 (4.15) For steady-state operation, the increase in the magnetic energy stored in the inductor ΔEL(in) is equal to the decrease in the stored magnetic energy in the inductor ΔEL(out) . 4.2.5 DC Voltage Transfer Function for CCM Referring to Figure 4.2 and using a volt-second balance, A+ = A− , we can write DTVI = (1 − D)TVO (4.16) which can be rearranged to the form VO = DVI 1−D (4.17) resulting in the dc voltage transfer function of the lossless converter MVDC ≡ VO I D . = I = VI IO 1−D (4.18) The range of MVDC for the lossless buck–boost converter is 0 ≤ MVDC < ∞. (4.19) For the lossless buck–boost converter, MVDC increased from 0 to ∞ as D increased from 0 to 1. It follows from (4.17) that the output voltage VO is independent of the load resistance RL and depends only on the dc input voltage VI . It will be shown shortly that MVDC is significantly altered by losses, especially when the values of D is close to 1. From (4.18), D= MVDC . MVDC + 1 (4.20) The sensitivity of the output voltage with respect to the duty cycle is S≡ dVO VI = . dD (1 − D)2 (4.21) 150 Pulse-Width Modulated DC–DC Power Converters In practice, VO should be held constant. If VI increases, D should be decreased by a control circuit so that VO remains constant, and vice versa. The dc current transfer function is MIDC ≡ IO 1−D = II D (4.22) and its value decreases from ∞ to zero as D is increased from 0 to 1. Using (4.11), VO VO 1 = = =D V VSM VI + VO 1+ I (4.23) IO IO 1 ≈ = = 1 − D. I ISM II + IO 1+ I (4.24) VO and using (4.22), IO Thus, the switch and the diode utilization in the buck–boost converter is characterized by the output-power capability cp ≡ PO V I MVDC = O O ≈ D(1 − D) = . VSM ISM VSM ISM (MVDC + 1)2 (4.25) As D is increased from 0 to 1, cp increases from 0, reaches a maximum equal to 0.25 at D = 0.5, and then decreases back to zero. 4.2.6 Device Stresses for CCM The dc input power is PI = II VI and the dc output power is PO = IO VO . Neglecting power losses, PO = PI , that is, VO IO = VI II . Hence, MVDC = VO I 1 D . = I = = VI IO MIDC 1−D (4.26) 1 − Dmin . Dmin (4.27) Therefore, VImax = VO The maximum switch and diode peak voltages for steady state in CCM are VSMmax = VDMmax = VImax + VO = VO . Dmin (4.28) The maximum inductor current ripple is given by ΔiLmax = VO (1 − Dmin ) . fs L (4.29) From (4.26), the dc component of the input current is D I . (4.30) 1−D O The maximum value of the dc input current occurs at IOmax and VImin , that is, at MVDCmax and Dmax . Hence, II = MVDC IO = IImax = MVDCmax IOmax = Dmax I . 1 − Dmax Omax (4.31) Buck–Boost PWM DC–DC Converter 151 iL VImax L iLmax VImin L ILB DminT DmaxT 0 Figure 4.3 VO L T t Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax . The average inductor current IL is equal to the sum of the average switch current IS and the average diode current ID . In turn, the average switch current IS is equal to the average input current II and the average diode current ID is equal to the average output current IO . Thus, IL = IS + ID = II + IO = IO . 1−D (4.32) Hence, the maximum switch and diode peak currents for steady state in CCM are I V (1 − Dmax ) ΔiLmin = Omax + O . 2 1 − Dmax 2fs L ISMmax = IDMmax = IImax + IOmax + (4.33) Note that ΔiL = ΔiLmin when II = IImax . 4.2.7 Boundary Between CCM and DCM Figure 4.3 depicts the inductor current waveform at the boundary between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM). This waveform can be described by iL = VI t L 0 < t ≤ DT. (4.34) V (1 − Dmin ) VI DT = O . L fs Lmin (4.35) for From (4.18), VI = VO (1 − D)∕D. Therefore, ΔiLmax = iL (DT) = The dc inductor current at the boundary between CCM and DCM is ILB = V (1 − Dmin ) ΔiLmax = O . 2 2fs Lmin (4.36) IO 1−D (4.37) From (4.32), IL = which results in the dc output current at the boundary IOB = ILB (1 − Dmin ) = VO (1 − Dmin )2 . 2fs L (4.38) The load resistance at the boundary is RLB = VO 2fs L = . IOB (1 − Dmin )2 (4.39) 152 Pulse-Width Modulated DC–DC Power Converters 1 0.9 0.8 IOB/(V O/2fsL) 0.7 0.6 CCM 0.5 0.4 0.3 DCM 0.2 0.1 0 0 0.2 0.4 D 0.6 0.8 1 Figure 4.4 Normalized load current IOB ∕(VO ∕2fs L) as a function of D at the boundary between CCM and DCM for buck–boost converter. Hence, the minimum value of the inductance L is found as Lmin = VO (1 − Dmin )2 (1 − Dmin )2 R = Lmax . 2fs IOB 2fs (4.40) Figures 4.4 and 4.5 show the normalized load current IOB ∕(VO ∕2fs L) = (1 − D)2 and load resistance RLB ∕(2fs L) = 1∕(1 − D)2 as functions of D at the boundary between CCM and DCM. 4.2.8 Ripple Voltage in Buck–Boost Converter for CCM The output part of the buck–boost converter is shown in Figure 4.6, where the filter capacitor is modeled by its capacitance C and its ESR denoted by rC . Figure 4.7 displays current and voltage waveforms for the converter output circuit. The dc component of the inductor current equals the dc load current IO . The ac component of the inductor current flows through the capacitor C and the load resistance RL . In most practical applications, the current through the capacitor is approximately equal to the ac component of the inductor current. The peak-to-peak value of the capacitor current may be written as ICpp = IDM ≈ II + IO = IO 1−D (4.41) rC IOmax . 1 − Dmax (4.42) resulting in the peak-to-peak value of the voltage across rC Vrcpp = rC ICpp = rC IDMmax ≈ Buck–Boost PWM DC–DC Converter 153 30 25 RLB/(2fsL) 20 DCM 15 CCM 10 5 0 0 0.2 0.4 D 0.6 0.8 1 Figure 4.5 Normalized load resistance RLB ∕(2fs L) as a function of D at the boundary between CCM and DCM for buck–boost converter. The peak-to-peak value of the output ripple voltage Vr is usually given. Hence, the maximum peak-to-peak value of the ac component of the voltage across the capacitance C is found as VCpp ≈ Vr − Vrcpp . (4.43) On the other hand, this voltage is approximately given by VCpp = D T I VO Dmax ΔQmax = Omax max = Cmin Cmin fs RLmin Cmin (4.44) where ΔQmax is the maximum decrease in charge during the time interval from zero to DT. Rearrangement of (4.44) gives Cmin = IOmax Dmax Dmax VO = . fs VCpp fs RLmin VCpp iD C rC Figure 4.6 IO iC + vC + vrc RL + VO Output circuit of the buck–boost converter for deriving the output voltage ripple. (4.45) 154 Pulse-Width Modulated DC–DC Power Converters iD IDM ΔiL 0 IO II 1−D T DT t iC II − IO ΔQ IDM 0 II + IO DT T t −ΔQ − IO vrc = rc ic 0 Vrc˜= rc II Vrc DT T t vc 0 Vc DT T t vo Vr 0 Figure 4.7 DT T t Waveforms associated with the ripple voltage for the PWM buck–boost converter for CCM. Buck–Boost PWM DC–DC Converter iS VF rDS RF iD IO iL iC rL rC RL VI 155 L C VO + Figure 4.8 Equivalent circuit of the buck–boost converter with parasitic resistances and the diode offset voltage to determine power losses. 4.2.9 Power Losses and Efficiency of the Buck–Boost Converter for CCM An equivalent circuit of the buck–boost converter with parasitic resistances is shown in Figure 4.8. In this figure, rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be evaluated assuming that the inductor current iL is ripple free and equals the dc current II + IO . Hence, the switch current can be approximated by { IO , for 0 < t ≤ DT IL = II + IO = 1−D iS = (4.46) 0, for DT < t ≤ T resulting in its rms value √ ISrms = T I 1 i2S dt = O T ∫0 1−D √ 1 T ∫0 DT √ IO D dt = 1−D (4.47) and the MOSFET conduction loss 2 PrDS = rDS ISrms = DrDS IO2 (1 − D)2 = DrDS PO . (1 − D)2 RL (4.48) Assuming that the transistor output capacitance Co is linear, the switching loss is expressed as 2 = fs Co (VI + VO )2 = Psw = fs Co VSM = fs Co RL (1 + MVDC )2 PO 2 MVDC fs Co VO2 D2 = fs Co VO2 (1 + MVDC )2 2 MVDC fC R P = s o 2L O D . (4.49) Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power) ] [ DrDS IO2 P DrDS fs Co RL 1 2 f PFET = PrDS + sw = + C (V + V ) = + O 2 (1 − D)2 2 s o I (1 − D)2 RL 2D2 [ ] DrDS fs Co RL (1 + MVDC )2 + PO = PO . 2 (1 − D)2 RL 2MVDC Similarly, the diode current may be approximated by { 0, iD = IO , IL = II + IO = 1−D for for 0 < t ≤ DT DT < t ≤ T (4.50) (4.51) 156 Pulse-Width Modulated DC–DC Power Converters which yields its rms value √ IDrms = T I 1 i2 dt = O T ∫0 D 1−D √ T I 1 dt = √ O T ∫DT 1−D (4.52) and the power loss in RF 2 PRF = RF IDrms = RF IO2 1−D = RF PO . (1 − D)RL (4.53) The average value of the diode current is ID = T T IO 1 iD dt = dt = IO T ∫0 (1 − D)T ∫DT (4.54) which gives the power loss associated with the voltage VF PVF = VF ID = VF IO = VF PO . VO (4.55) ] VF RF P . + VO (1 − D)RL O (4.56) Thus, the overall diode conduction loss is PD = PVF + PRF = VF IO + RF IO2 1−D [ = The inductor current is iL ≈ II + IO = IO 1−D (4.57) IO 1−D (4.58) leading to its rms value ILrms ≈ II + IO = and the inductor conduction loss 2 PrL = rL ILrms = rL IO2 (1 − D)2 = rL PO . (1 − D)2 RL (4.59) The current through the filter capacitor is { −IO , for iC = DIO , for II = 1−D 0 < t ≤ DT DT < t ≤ T (4.60) and the rms current through the filter capacitor is found as √ ICrms = T 1 i2 dt = IO T ∫0 C √ √ D = IL D(1 − D) = IS 1−D √ 1−D D (4.61) Buck–Boost PWM DC–DC Converter 157 100 90 R = 12 Ω L 80 R = 2.4 Ω L 70 η (%) 60 RL = 1.2 Ω 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 D 0.6 0.7 0.8 0.9 1 Figure 4.9 Efficiency of the buck–boost converter 𝜂 versus duty cycle D at various load resistances for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. and the power loss in the filter capacitor 2 PrC = rC ICrms = DrC IO2 1−D = DrC PO . (1 − D)RL (4.62) The overall power loss is given by rL IO2 RF IO2 2 + + f C (V + V ) + V I + s o I O F O 1 − D (1 − D)2 (1 − D)2 [ ] DrC IO2 DrDS + rL fs Co RL (1 + MVDC )2 VF R + DrC = + + + + F PO . 2 1−D V R (1 − D)2 RL MVDC O L (1 − D) PLS = PrDS + Psw + PD + PrL + PrC = DrDS IO2 (4.63) Thus, the converter efficiency is 𝜂= PO = PO + PLS 1 1 = . PLS rL + DrDS RF + DrC VF fs Co RL (1 + MVDC )2 1+ 1+ + + + PO (1 − D)2 RL (1 − D)RL VO M2 (4.64) VDC Figure 4.9 shows the efficiency of the buck–boost converter 𝜂 as a function of the duty cycle D at various load resistances for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. At the duty cycle D close to zero, the conduction losses are low, but the switching loss is high because VI is high at a fixed value of VO . Hence, the efficiency decreases to zero. At the duty cycle D close to 1, the conduction losses are high, reducing the efficiency to zero. Therefore, the operation at very low and high values of D should be avoided. 158 Pulse-Width Modulated DC–DC Power Converters 4.2.10 DC Voltage Transfer Function of Lossy Buck–Boost Converter for CCM The dc component of the input current is T II = 1 1 i dt = T ∫0 S T ∫0 DT IL dt = DIL = D(II + IO ) (4.65) where IL = II + IO . Similarly, the dc component of the output current is T IO = T 1 1 i dt = I dt = (1 − D)IL = (1 − D)(II + IO ). T ∫0 D T ∫DT L (4.66) Hence, one obtains the dc current transfer function of the buck–boost converter MIDC ≡ IO 1 1−D = − 1. = II D D (4.67) This equation holds true for both lossless and lossy converter. The converter efficiency can be expressed as 𝜂= PO V I (1 − D)MVDC = O O = MVDC MIDC = PI VI II D (4.68) from which the voltage transfer function of the lossy buck–boost converter is MVDC = 𝜂 𝜂D = 𝜂MVDC(lossless) = = MIDC 1−D D ]. [ rL + DrDS RF + DrC VF fs Co RL (1 − D) 1 + + + + (1 − D)2 RL (1 − D)RL VO D2 (4.69) Figure 4.10 portrays MVDC as a function of D at various load resistances for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. It can be seen that MVDC first increases 4 3.5 3 R = 12 Ω L MVDC 2.5 2 RL = 2.4 Ω 1.5 1 RL = 1.2 Ω 0.5 0 0 0.2 0.4 D 0.6 0.8 1 Figure 4.10 The dc voltage transfer function MVDC of the lossy buck–boost converter for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. Buck–Boost PWM DC–DC Converter 159 with D, reaches the maximum value, and then decreases to zero. This is because the efficiency is very low at D close to 1. From (4.69), the on-duty cycle is D= MVDC 1 1 = . 𝜂 = 𝜂VI MVDC + 𝜂 1+ 1 + MVDC V (4.70) O Notice that the duty cycle D at a given dc voltage transfer function is greater for the lossy converter than that for the lossless converter. The switch must be closed for a greater portion of the cycle in the lossy converter to transfer energy equal to the output energy and the losses. Substitution of (4.70) into (4.64) gives the efficiency of the buck–boost converter 𝜂= where N𝜂 (4.71) D𝜂 ( ) {[ ( )] 2rL + rDS + RF + rC 2rL + rDS + RF + rC 2 + 1 − MVDC RL RL [ ]} 1 2 2 (rL + rDS ) 4MVDC rL + RF VF fs Co RL (1 + MVDC )2 1+ ×− + + 2 RL RL VO MVDC N𝜂 = 1 − MVDC and [ r + RF VF fs Co RL (1 + MVDC )2 + + D𝜂 = 2 1 + L 2 RL VO MVDC (4.72) ] . (4.73) 4.2.11 Design of Buck–Boost Converter for CCM Design a PWM buck–boost converter that meets the following specifications: VI = 28 V ± 4 V, VO = 12 V, IO = 1–10 A, and Vr ∕VO ≤ 1%. Solution: The maximum and minimum values of the output power are POmax = VO IOmax = 12 × 10 = 120 W (4.74) POmin = VO IOmin = 12 × 1 = 12 W. (4.75) and The minimum and maximum values of the load resistance are V 12 RLmin = O = = 1.2 Ω IOmax 10 (4.76) and RLmax = VO IOmin = 12 = 12 Ω. 1 (4.77) The minimum, nominal, and maximum values of the dc voltage transfer function are MVDCmin = VO 12 = 0.375, = VImax 32 (4.78) MVDCnom = VO 12 = 0.429, = VInom 28 (4.79) 160 Pulse-Width Modulated DC–DC Power Converters and MVDCmax = VO 12 = 0.5. = VImin 24 (4.80) Assume the converter efficiency 𝜂 = 85%. The minimum, nominal, and maximum values of the duty cycle are Dmin = MVDCmin 0.375 = = 0.306, MVDCmin + 𝜂 0.375 + 0.85 (4.81) Dnom = MVDCnom 0.429 = = 0.335, MVDCnom + 𝜂 0.429 + 0.85 (4.82) MVDCmax 0.5 = = 0.37. MVDCmax + 𝜂 0.5 + 0.85 (4.83) and Dmax = Selecting the switching frequency fs = 100 kHz, the minimum inductance is Lmin = RLmax (1 − Dmin )2 12 × (1 − 0.306)2 = = 28.9 μH. 2fs 2 × 105 (4.84) Pick L = 30 μH. The peak-to-peak value of the ac component of the inductor current is ΔiLmin = VO (1 − Dmax ) 12 × (1 − 0.37) = 5 = 2.52 A. fs L 10 × 30 × 10−6 (4.85) The maximum dc input current occurs at VImin = 24 V, which corresponds to the maximum dc voltage transfer function MVDCmax = 0.5. This current is given by IImax = MVDCmax IOmax = 0.5 × 10 = 5 A. (4.86) The current and voltage stresses of the semiconductor devices are ISMmax = IDMmax = IImax + IOmax + ΔiLmin 2.52 = 5 + 10 + = 16.26 A 2 2 (4.87) and VSMmax = VDMmax = VO + VImax = 12 + 32 = 44 V. (4.88) Let us select an International Rectifier IRF142 power MOSFET whose VDSS = 100 V, ISM = 24 A, rDS = 0.11 Ω, Qg = 38 nC, and Co = 100 pF. Choose also an MUR2510 ultrafast recovery diode whose IF(AV) = 25 A, VDM = 100 V, VF = 0.7 V, and RF = 20 mΩ. The ripple voltage is Vr = VO 12 = = 120 mV. 100 100 (4.89) Assume that Vrcpp = 100 mV. Hence, one obtains the maximum value of the ESR of the filter capacitor Vrcpp 100 × 10−3 = 6.15 mΩ. 16.26 (4.90) VCpp = Vr − Vrcpp = 120 − 100 = 20 mV (4.91) rCmax = IDMmax = The ripple voltage across the filter capacitance is Buck–Boost PWM DC–DC Converter 161 and the filter capacitance is Cmin = Dmax VO 0.37 12 = 1850 μF. = 5 fs RLmin VCpp 10 × 1.2 0.02 (4.92) Pick C = 2.2 mF/25 V/6 mΩ. The power losses and the efficiency will be calculated for full load IOmax = 10 A and minimum dc input voltage VImin = 24 V, corresponding to Dmax = 0.37. The rms value of the inductor current is ILrms = IOmax 10 = 15.87 A. = 1 − Dmax 1 − 0.37 (4.93) Assuming the dc ESR of the inductor rL = 50 mΩ, one arrives at the loss in the ESR of the inductor 2 = 0.05 × 15.872 = 12.59 W. PrL = rL ILrms The switch rms current is ISrms = √ IOmax Dmax 1 − Dmax √ 10 0.37 = = 9.655 A 1 − 0.37 (4.94) (4.95) which gives the MOSFET conduction loss 2 = 0.11 × 9.6552 = 10.254 W. PrDS = rDS ISrms (4.96) 2 = fs Co (VImin + VO )2 = 105 × 100 × 10−12 × (24 + 12)2 = 12.96 mW. Psw = fs Co VSMmin (4.97) The switching loss is The total power loss in the MOSFET (without the gate drive power) is PFET = PrDS + Psw 0.01296 = 10.25 + = 10.26 W. 2 2 (4.98) The rms diode current is I 10 IDrms = √ Omax = √ = 12.6 A. 1 − Dmax 1 − 0.37 (4.99) 2 = 0.02 × 12.62 = 3.175 W PRF = RF IDrms (4.100) PVF = VF IOmax = 0.7 × 10 = 7 W (4.101) PD = PVF + PRF = 7 + 3.175 = 10.175 W. (4.102) Thus, the power loss due to RF is and the power loss due to VF is resulting in the diode conduction loss The rms current of the filter capacitor is ICrms = IOmax √ Dmax = 10 1 − Dmax √ 0.37 = 7.66 A. 1 − 0.37 (4.103) Hence, the power loss in the ESR of the filter capacitor is 2 PrC = rC ICrms = 0.006 × 7.662 = 0.352 W. (4.104) The total power loss is PLS = PrDS + Psw + PD + PrL + PrC = 10.254 + 0.013 + 10.175 + 12.59 + 0.352 = 33.384 W. (4.105) 162 Pulse-Width Modulated DC–DC Power Converters 94 R = 12 Ω L 92 90 η (%) 88 RL = 2.5 Ω 86 84 82 80 R = 1.2 Ω L 78 76 24 Figure 4.11 in CCM. 25 26 27 28 VI (V) 29 30 31 32 Efficiency 𝜂 as a function of the dc input voltage VI at fixed load resistances RL for the buck–boost converter Hence, the converter efficiency is 𝜂= PO 120 = 78.24%. = PO + PLS 120 + 33.384 (4.106) Assuming that the peak-to-peak gate-to-source voltage is VGSpp = 14 V, the gate-drive power is PG = fs VGSpp Qg = 105 × 14 × 38 × 10−9 = 53.2 mW. (4.107) Using (4.71) through (4.73), the efficiency 𝜂 of the designed buck–boost converter can be computed for the specified range of VI and IO for CCM. Using the computed efficiency 𝜂, the duty cycle D can be calculated from (4.70). The plots of the efficiency 𝜂 and the duty cycle D versus VI at fixed load resistances RL are depicted in Figures 4.11 and 4.12, respectively. Figures 4.13 and 4.14 show the plots of the efficiency 𝜂 and the duty cycle D versus the load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V. Plots of the efficiency 𝜂 and the duty cycle D versus RL at fixed values of VI are shown in Figures 4.15 and 4.16. The efficiency 𝜂 decreases as IO increases (or RL decreases). The duty cycle D increases as VI decreases and IO increases (or RL decreases). 4.3 DC Analysis of PWM Buck–Boost Converter for DCM Equivalent circuits for the PWM buck–boost converter operating in the DCM are depicted in Figure 4.17. Idealized current and voltage waveforms are shown in Figure 4.18. Prior to time t = 0, the inductor current is zero. At time t = 0, the switch is turned on, causing the diode to turn off. The voltage across the inductor is VI and the inductor current increases linearly from zero. At time t = DT, the switch is turned off and the diode turns on. The voltage across the inductor is −VO . Therefore, the inductor current decreases linearly. This current flows through the diode. Buck–Boost PWM DC–DC Converter 163 0.4 0.38 R = 1.2 Ω L 0.36 R = 2.5 Ω D L 0.34 R = 12 Ω L 0.32 0.3 0.28 24 25 26 27 28 VI (V) 29 30 31 32 Figure 4.12 Duty cycle D as a function of the dc input voltage VI at fixed load resistances RL for the buck–boost converters in CCM. 94 92 90 η (%) 88 86 V I = 32 V 84 V I = 28 V 82 V = 24 V I 80 78 76 1 2 3 4 5 IO (A) 6 7 8 9 10 Figure 4.13 Efficiency 𝜂 as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM. 164 Pulse-Width Modulated DC–DC Power Converters 0.4 V = 24 V I 0.38 D 0.36 V I = 28 V 0.34 0.32 V I = 32 V 0.3 0.28 1 2 3 4 5 IO (A) 6 7 8 9 10 Figure 4.14 Duty cycle D as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM. 94 92 V = 32 V I 90 V I = 24 V η (%) 88 86 84 V I = 28 V 82 80 78 76 0 2 4 6 RL (Ω) 8 10 12 Figure 4.15 Efficiency 𝜂 as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in CCM. Buck–Boost PWM DC–DC Converter 165 0.4 0.38 D 0.36 V I = 24 V 0.34 V = 28 V I 0.32 0.3 V = 32 V I 0.28 0 2 4 6 RL (Ω) 8 10 12 Figure 4.16 Duty cycle D as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM. Once the diode current reaches zero, the diode begins to turn off. Since both the transistor and the diode are off, the inductor current is zero until the switch is turned on. 4.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is on and the diode is off. The equivalent circuit is shown in Figure 4.17(b). The switch voltage vS and the diode current iD are zero. The voltage across the inductor L is vL = V I = L diL , dt iL (0) = 0 (4.108) and the inductor and switch current is iS = iL = t t V 1 1 vL dt = V dt = I t. L ∫0 L ∫0 I L (4.109) Hence, one obtains the peak switch and inductor current ISM = ΔiL = iL (DT) = VD VI DT = I . L fs L (4.110) The voltage across the diode is vD = −(VI + VO ). This time interval ends when the switch is turned off by the driver. (4.111) 166 Pulse-Width Modulated DC–DC Power Converters iS iD vGS + VI iL L C RL VO + C RL VO + C RL VO + C RL VO + (a) iS iL L VI vD + + vL (b) iD + vS VI L iL + vL (c) + vS + vD VI (d) Figure 4.17 PWM buck–boost converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF. 4.3.2 Time Interval: DT < t ≤ (D + D1 )T The equivalent circuit for this time interval is shown in Figure 4.17(c). The switch is off and the diode is on. Hence, iS = 0 and vD = 0. The voltage across the inductor L is diL dt and, using (4.110), the inductor and diode current is obtained as vL = −VO = L iD = iL = (4.112) t t V 1 1 vL dt + iL (DT) = (−VO )dt + iL (DT) = − O (t − DT) + iL (DT) L ∫DT L ∫DT L VO V DT (t − DT) + I . L L The peak diode and inductor current is found to be (4.113) =− DT IDM = ΔiL = DT V D T V D 1 1 vL dt = (−VO )dt = O 1 = O 1 . L ∫(D+D1 )T L ∫(D+D1 )T L fs L (4.114) Buck–Boost PWM DC–DC Converter 167 The peak voltage across the switch is VSM = VI + VO . (4.115) This time interval ends when the diode current reaches zero. 4.3.3 Time Interval: (D + D1 )T < t ≤ T During this time interval, both the switch and the diode are off. The equivalent circuit is shown in Figure 4.17(d). The inductor current iL , the inductor voltage vL , the switch current iS , and the diode current iD are zero. The voltage across the switch is vS = V I (4.116) vD = −VO . (4.117) and the voltage across the diode is This time interval ends when the switch is turned on by the driver. 4.3.4 Device Stresses of the Buck–Boost Converter in DCM From (4.111) and (4.115), the voltage stress of the transistor and the diode is VSMmax = VDMmax = VImax + VO (4.118) and, from (4.110) and (4.114), the current stress of the transistor and the diode is ISMmax = IDMmax = ΔiLmax = VImax Dmin . fs L (4.119) 4.3.5 DC Voltage Transfer Function of the Buck–Boost Converter for DCM Referring to Figure 4.18 and using the volt-second balance principle, VI DT = VO D1 T (4.120) which leads to MVDC = VO I D = I = . VI IO D1 (4.121) Using (4.110), the dc output current is found as IO = T V D DV D Δi 1 i dt = 1 L = 1 I = O . T ∫0 D 2 2fs L RL (4.122) Thus, MVDC = VO DD1 RL . = VI 2fs L Equating the right-hand sides of (4.121) and (4.123) produces √ 2fs L D1 = . RL (4.123) (4.124) 168 Pulse-Width Modulated DC–DC Power Converters vGS 0 T DT t vL VI 0 A+ A− T t D2T T t DT T t DT T t DT T t T t DT VO iL Δ iL IL VI VO L L DT D1T II + IO 0 iS ISM IS 0 vS VSM VI + VO VI 0 iD IDM ID 0 vD 0 VO DT (VI + VO ) Figure 4.18 Waveforms for the PWM buck–boost converter operating in DCM. Buck–Boost PWM DC–DC Converter 169 Substitution of this into (4.121) yields the dc voltage transfer function of the buck–boost converter for DCM √ MVDC = D √ √ VO RL =D 2fs L 2fs LIO D≤1− for √ 2fs L =1− RL 2fs LIO . VO (4.125) It follows from this equation that MVDC depends on D, RL , L, and fs . From (4.125), √ D = MVDC √ √ 2fs L = MVDC RL 2fs LIO VO for D≤1− √ 2fs L =1− RL 2fs LIO . VO (4.126) At the boundary between the DCM and CCM modes, MVDCB = DB . 1 − DB (4.127) Hence, from (4.126), one obtains the boundary duty cycle √ DB = 1 − √ 2fs L =1− RL 2fs LIO . VO (4.128) Figures 4.19 and 4.20 show plots of the duty cycle D versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of MVDC for both CCM and DCM. 1 MVDC = 7 0.9 0.8 3 0.7 1.5 D 0.6 1 0.5 CCM 0.4 0.5 DCM 0.3 0.3 0.2 0.1 0.1 0 0 0.2 0.4 0.6 IO/(V O/2fsL) 0.8 1 Figure 4.19 Duty cycle D as a function of the normalized load current IO ∕(VO ∕2fs L) at fixed values of MVDC for the lossless buck–boost converter. 170 Pulse-Width Modulated DC–DC Power Converters 1 0.9 0.8 MVDC = 7 CCM 3 DCM 0.7 D 0.6 0.5 1.5 1 0.4 0.3 0.5 0.2 0.3 0.1 0.1 0 0 10 1 10 2 RL/(2fsL) 10 3 10 Figure 4.20 Duty cycle D as a function of the normalized load resistance RL ∕(2fs L) at fixed values of MVDC for the lossless buck–boost converter. Substitution of (4.126) into (4.128) produces the dc voltage transfer function of the buck–boost converter at the boundary √ √ VO RL −1= − 1. (4.129) MVDCB = 2fs L 2fs LIO Plots of MVDC as a function of normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at fixed values of D are depicted in Figures 4.21 and 4.22, respectively. 4.3.6 Maximum Inductance for DCM Referring to Figure 4.2, the minimum value of the inductor peak current at the boundary between DCM and CCM is ΔiLmin = V (1 − DBmax ) VImin DBmax T = O . Lmax fs Lmax (4.130) The dc inductor current at the boundary between CCM and DCM is ILB = V (1 − DBmax ) ΔiLmin = O . 2 2fs Lmax (4.131) IO 1−D (4.132) Using (4.22), IL = Buck–Boost PWM DC–DC Converter 171 5 4.5 D = 0.8 4 CCM 3.5 0.75 MVDC 3 2.5 0.7 2 0.6 1.5 0.5 1 0.4 DCM 0.5 0 0.2 0 0.2 0.4 0.6 IO/(V O/2fsL) 0.8 1 Figure 4.21 DC voltage transfer function MVDC versus normalized load current IO ∕(VO ∕2fs L) at fixed values of duty cycle D for the lossless buck–boost converter. 5 4.5 4 D = 0.8 CCM 3.5 MVDC 3 2.5 0.75 0.7 DCM 2 1.5 1 0.6 0.5 0.4 0.5 0 0 10 0.2 1 10 RL/(2fsL) 2 10 Figure 4.22 DC voltage transfer function MVDC versus normalized load resistance RL ∕(2fs L) at fixed values of duty cycle D for the lossless buck–boost converter. 172 Pulse-Width Modulated DC–DC Power Converters from which the dc output current at the boundary is obtained VO (1 − DBmax )2 V = O . 2fs Lmax RLmin IOB = ILB (1 − DBmax ) = (4.133) The load resistance at the boundary is VO 2fs L = . IOB (1 − Dmin )2 RLB = (4.134) Therefore, the maximum inductance L required for operation in DCM is VO (1 − DBmax )2 R (1 − DBmax )2 = Lmin . 2fs IOB 2fs Lmax = (4.135) 4.3.7 Power Losses and Efficiency of the Buck–Boost Converter in DCM Using (4.125), the peak inductor, switch, and diode current is DVO DVI ΔiL = ISM = IDM = = = VO fs L fs LMVDC The rms value of the switch current is √ √ DT 1 T ∫0 ISrms = i2S dt = ΔiL D = VO 3 √ √ 2 . fs LRL (4.136) 2D . 3fs LRL (4.137) Therefore, the MOSFET conduction loss is 2 PrDS = rDS ISrms = DrDS Δi2L 3 = 2rDS DVO2 3fs LRL = 2DrDS 2r PO = DS 3fs L 3 √ 2 M P . fs LRL VDC O (4.138) From (4.115) and (4.125), the switching loss is ( 2 Psw = fs Co VSM = fs Co (VI + VO )2 = fs Co VO2 (√ PO = fs Co RL 2fs L +1 D2 RL ( )2 1 MVDC +1 = fs Co RL 1 MVDC )2 +1 )2 PO . (4.139) The rms value of the diode current is √ ( )0.25 √ (D+D1 )T D 1 8 1 = VO i2D dt = ΔiL . IDrms = T ∫DT 3 9fs LR3 (4.140) L Hence, the power loss in the diode associated with RF is 2 = PRF = RF IDrms D1 RF Δi2L 3 = 2RF VO2 √ 3RL 2RF 2 = fs LRL 3 √ 2 P . fs LRL O (4.141) The average diode current is ID = IO , resulting in the diode loss associated with VF PVF = VF ID = VF IO = VF P . VO O (4.142) Buck–Boost PWM DC–DC Converter 173 Thus the overall diode conduction loss is ( PD = PVF + PRF = VF 2RF + VO 3 √ 2 fs LRL ) PO . (4.143) Using (4.124) and (4.126), the rms value of the current through the inductor L is √ 1 T ∫0 ILrms = (D+D1 )T √ i2L dt = ΔiL √ √ ( ) √ √ 2D 2fs L D + D1 √ = VO 1+ . 3 3fs LRL D2 RL (4.144) The power loss in the inductor ESR is therefore given by 2 = PrL = rL ILrms PO = 2rL M 3 VDC rL Δi2L (D + D1 ) 3 √ 2 fs LRL ( 1+ = 2rL DVO2 √ ( 3fs LRL ) 1 PO . 1+ 2fs L D2 RL ) 2r D = L 3fs L √ ( 1+ 2fs L D2 RL ) (4.145) MVDC The total power loss in the converter is √ 2DrDS 2RF V 2 + + F 3fs L 3 fs LRL VO √ ( )2 (√ )] 2fs L 2fs L 2DrL 1+ + fs Co RL +1 + 3fs L D2 RL D2 RL [ PLS = PrDS + Psw + PD + PrL = √ √ ( )2 2rDS 2R V 2 2 1 MVDC + F + F + fs Co RL +1 3 fs LRL 3 fs LRL VO MVDC √ ( )] 2r 1 2 1+ PO . + L MVDC 3 fs LRL MVDC [ PO = (4.146) This leads to the efficiency of the buck–boost converter in DCM 𝜂≡ PO PO = = PI PO + PLS = 1 P 1 + LS PO 1 √ ) (√ )2 2DrDS 2RF 2fs L 2fs L VF 2DrL 2 + 1+ + 1+ + + fs Co RL +1 3fs L 3 fs LRL 3fs L VO D2 RL D2 RL √ √ √ ( ) [ 2r V 2R 2r 1 2 2 2 1+ + F = 1 + DS MVDC + F + L MVDC 3 fs LRL 3 fs LRL 3 fs LRL MVDC VO ( )2 ]−1 1 + fs Co RL +1 . (4.147) MVDC √ ( 174 Pulse-Width Modulated DC–DC Power Converters The dc input current is II = 1 T ∫0 DT iI dt = 1 T ∫0 DT V D2 VI t dt = I L 2fs L (4.148) yielding the dc input power PI = VI II = VI2 D2 2fs L . (4.149) The dc output power is PO = VO2 RL . (4.150) The dc input power, dc output power, and the efficiency are related by PO = 𝜂PI (4.151) producing VO2 RL = 𝜂VI2 D2 2fs L . (4.152) Hence, the dc voltage transfer function of lossy converter is √ √ VO 𝜂VO 𝜂RL MVDC ≡ =D =D VI 2fs L 2fs LIO √ D RL 2fs L = √ . √ √ ( ) (√ )2 √ √ √ 2fs L 2fs L V 2DrL 2 √1 + 2DrDS + 2RF 1+ + F + fs Co RL + +1 3fs L 3 fs LRL 3fs L VO D2 RL D2 RL (4.153) Thus, √ D = MVDC √ 2fs L = MVDC 𝜂RL 2fs LIO . 𝜂VO (4.154) 4.3.8 Design of Buck–Boost Converter for DCM Design a PWM buck–boost converter that meets the following specifications: VI = 28 V ± 4 V, VO = 12 V, IO = 0–10 A, and Vr ∕VO ≤ 1%. Solution: The maximum and minimum values of the output power are POmax = VO IOmax = 12 × 10 = 120 W (4.155) POmin = VO IOmin = 12 × 0 = 0 W. (4.156) and Buck–Boost PWM DC–DC Converter The minimum and maximum values of the load resistance are V 12 RLmin = O = = 1.2 Ω IOmax 10 175 (4.157) and RLmax = VO 12 = = ∞. IOmin 0 (4.158) The minimum, nominal, and maximum values of the dc voltage transfer function are MVDCmin = VO 12 = = 0.375 VImax 32 (4.159) MVDCnom = VO 12 = 0.429 = VInom 28 (4.160) VO 12 = 0.5. = VImin 24 (4.161) and MVDCmax = Assume the converter efficiency 𝜂 = 85%. The minimum, nominal, and maximum values of the duty cycle are Dmin = MVDCmin 0.375 = = 0.306 MVDCmin + 𝜂 0.375 + 0.85 (4.162) Dnom = MVDCnom 0.429 = = 0.335 MVDCnom + 𝜂 0.429 + 0.85 (4.163) MVDCmax 0.5 = = 0.37. MVDCmax + 𝜂 0.5 + 0.85 (4.164) and Dmax = Assuming the switching frequency fs = 100 kHz, the maximum inductance required for DCM operation is Lmax = RLmin (1 − Dmax )2 1.2 × (1 − 0.37)2 = = 2.3814 μH. 2fs 2 × 105 Pick L = 2.2 μH. At full load RL = RLmin , √ 2fs L = 0.5 𝜂RLmin Dmax = MVDCmax √ √ 2fs L = 0.429 𝜂RLmin Dnom = MVDCnom √ Dmin = MVDCmin and 2fs L = 0.375 𝜂RLmin √ D1max = 2fs L = 𝜂RLmin √ 2 × 105 × 2.2 × 10−6 = 0.328 0.85 × 1.2 √ √ (4.165) (4.166) 2 × 105 × 2.2 × 10−6 = 0.282 0.85 × 1.2 (4.167) 2 × 105 × 2.2 × 10−6 = 0.246, 0.85 × 1.2 (4.168) 2 × 105 × 2.2 × 10−6 = 0.6568. 0.85 × 1.2 (4.169) 176 Pulse-Width Modulated DC–DC Power Converters Hence, Dmax + D1max = 0.328 + 0.6568 = 0.9848 < 1. (4.170) The current and voltage stresses of the semiconductor devices are ISMmax = IDMmax = ΔiLmax = VImax Dmin 32 × 0.246 = 5 = 35.78 A fs L 10 × 2.2 × 10−6 (4.171) and VSMmax = VDMmax = VO + VImax = 12 + 32 = 44 V. (4.172) Select an International Rectifier IRF142 power MOSFET whose VDSS = 100 V, ISM = 24 A, rDS = 0.11 Ω, Qg = 38 nC, and Co = 100 pF. Also, select an MUR2510 ultrafast recovery diode whose IF(AV) = 25 A, VDM = 100 V, VF = 0.7 V, and RF = 20 mΩ. The ripple voltage is VO 12 = = 120 mV. 100 100 Assume that Vrcpp = 100 mV. Hence, one obtains the maximum value of the ESR of the filter capacitor Vr = Vrcpp (4.173) 100 × 10−3 = 2.795 mΩ. 35.78 (4.174) VCpp = Vr − Vrcpp = 120 − 100 = 20 mV (4.175) rCmax = IDMmax = The ripple voltage across the filter capacitance is and the filter capacitance is Cmin = Dmax VO 0.328 12 = 1.64 mF. = 5 fs RLmin VCpp 10 × 1.2 0.02 (4.176) Pick C = 1.8 mF/25 V/2.5 mΩ. Power losses and efficiency will be calculated at full power and VImin = 24 V at which D = Dmax = 0.328. The maximum conduction power loss in the MOSFET occurs at full load RLmin = 1.2 Ω and Dmax = 0.328 and is given by PrDS = 2rDS Dmax VO2 3fs LRLmin = 2 × 0.11 × 0.328 × 122 = 13.12 W. 3 × 105 × 2.2 × 10−6 × 1.2 (4.177) The transistor output capacitance is Co = 100 pF. The switching loss occurs at VImin = 24 V and is given by 2 Psw = fs Co VSMmin = fs Co (VImin + VO )2 = 105 × 100 × 10−12 × (24 + 12)2 = 12.96 mW. (4.178) The power loss in the MOSFET is Psw 0.013 = 13.12 + = 13.126 W. 2 2 The diode conduction power loss due to RF is √ √ 2RF VO2 2 × 0.02 × 122 2 2 = 4.404 W = PRF = 3RLmin fs LRLmin 3 × 1.2 105 × 2.2 × 10−6 × 1.2 PFET = PrDS + (4.179) (4.180) and the diode conduction power loss due to VF is PVF = VF IOmax = 0.7 × 10 = 7 W. (4.181) Buck–Boost PWM DC–DC Converter 177 Hence, the total diode conduction power loss is PDmax = PRF + PVF = 4.404 + 7 = 11.404 W. (4.182) Assuming the ESR of the inductor rL = 10 mΩ, the power loss in the inductor winding is ) ( √ ( √ ) 2rL Dmax VO2 2fs L 2 × 0.01 × 0.328 × 122 2 × 105 × 2.2 × 10−6 = 3.397 W. PrL = 1+ 1+ = 3fs LRLmin D2max RLmin 0.3282 × 1.2 3 × 105 × 2.2 × 10−6 × 1.2 (4.183) Neglecting the power loss in the filter capacitor, the total power loss in the converter is PLS = PrDS + Psw + PD + PrL = 13.12 + 0.013 + 11.404 + 3.397 = 27.932 W. (4.184) The converter efficiency is 𝜂= POmax 120 = 81.11%. = POmax + PLS 120 + 27.932 (4.185) Assuming that the peak-to-peak gate-to-source voltage is VGSpp = 14 V, the gate-drive power is PG = fs VGSpp Qg = 105 × 14 × 38 × 10−9 = 53.2 mW. (4.186) The converter efficiency 𝜂 can be computed from (4.147) and the duty cycle D from (4.154). The plots of the efficiency 𝜂 versus VI at fixed load resistances are depicted in Figure 4.23. Figure 4.24 shows the plot of D as VI increases from 24 to 32 V for the buck–boost converter in CCM given in the design example. Figure 4.25 shows the plots of the efficiency 𝜂 versus the load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V. Figure 4.26 depicts plots of the duty cycle D as a function of the dc load current IO for DCM at VImin = 24 V, VInom = 28 V, and VImax = 32 V. Plots of the efficiency 𝜂 versus RL at fixed values of VI are shown in Figure 4.27. Figure 4.28 92.5 RL = 75 Ω 92 91.5 η (%) 91 RL = 15 Ω 90.5 90 89.5 RL = 7.5 Ω 89 88.5 24 Figure 4.23 in DCM. 25 26 27 28 VI (V) 29 30 31 32 Efficiency 𝜂 as a function of the dc input voltage VI at fixed load resistances for the buck–boost converter 178 Pulse-Width Modulated DC–DC Power Converters 0.14 RL = 7.5 Ω 0.12 0.1 D RL = 15 Ω 0.08 0.06 RL = 75 Ω 0.04 0.02 24 25 26 27 28 VI (V) 29 30 31 32 Figure 4.24 Duty cycle D as a function of the dc input voltage VI at various load resistances for the buck–boost converter in DCM. 94 92 η (%) 90 88 VI = 32 V 86 VI = 24 V 84 VI = 28 V 82 80 0 2 4 IO (A) 6 8 10 Figure 4.25 Efficiency 𝜂 as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. Buck–Boost PWM DC–DC Converter 179 0.35 0.3 V = 24 V VI = 28 V I 0.25 D 0.2 V = 32 V I 0.15 0.1 0.05 0 0 2 4 IO (A) 6 8 10 Figure 4.26 Duty cycle D as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. 91 90 V = 32 V I 89 VI = 28 V 88 VI = 24 V η (%) 87 86 85 84 83 82 81 0 2 4 6 RL (Ω) 8 10 12 Figure 4.27 Efficiency 𝜂 as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. 180 Pulse-Width Modulated DC–DC Power Converters 0.35 0.3 D 0.25 VI = 24 V 0.2 0.15 VI = 32 V 0.1 VI = 28 V 0.05 0 2 4 6 RL (Ω) 8 10 12 Figure 4.28 Duty cycle D as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. exhibits the plots of the duty cycle D as a function of the load resistance RL for DCM at VImin = 24 V, VInom = 28 V, and VImax = 32 V. 4.4 Bidirectional Buck–Boost Converter A bidirectional buck–boost converter is shown in Figure 4.29. It is derived from a conventional unidirectional buck–boost converter of Figure 4.1(a) by replacing a diode with a MOSFET. If a dc voltage source is connected in parallel with the capacitor C1 and a load is connected in parallel with the capacitor C2 , the energy flows from left to right. On the other hand, if a dc voltage source is connected in parallel with the capacitor C2 and a load is connected in parallel with the capacitor C1 , the energy flows from right to left. + V1 Figure 4.29 C1 L C2 V2 + Bidirectional buck–boost converter. Buck–Boost PWM DC–DC Converter D VI Figure 4.30 −1 1 1− D 181 VO < 0 Block diagram of the buck–boost converter. 4.5 Synthesis of Buck–Boost Converter The buck–boost converter can be derived from the buck and boost converters [15]. The dc-to-dc voltage transfer function of the buck–boost converter for CCM can be represented as follows: MVDC = ( ) VO D 1 = (D)(−1) . =− VI 1−D 1−D (4.187) Hence, a block diagram of the buck–boost converter can be presented, as shown in Figure 4.30, where VO < 0. It consists of a converter with the dc-to-dc voltage transfer function equal to D such as the buck converter, an inverting unity-gain block with a voltage transfer function equal to −1, and a converter with the dc-to-dc voltage transfer function equal to 1∕(1 − D) such as the boost converter. Due the presence of the inverting unity-gain block, the polarity of the boost converter input voltage should be opposite to that of the buck converter output voltage. Figure 4.31 shows the transformation of the boost converter from the circuit accepting a positive input voltage to the circuit accepting a negative input voltage. A conventional + + − − (a) + + − − (b) − − + + (c) Figure 4.31 Transformation of the boost converter. (a) Boost converter with a positive input voltage. (b) Boost converter with inductor and diode moved to the bottom common rail. (c) Boost converter with a negative input voltage. 182 Pulse-Width Modulated DC–DC Power Converters D2 S1 − − + + S2 D1 − + − + (a) − + D2 − S1 + S2 D1 − + − + (b) S1 C S2 A D2 D D1 C′ D2 D − − i=0 + + B (c) S1 S2 A − + D1 + − B (d) A D2 D − S1 + − + B (e) Figure 4.32 Derivation of the buck–boost converter. (a) Buck and modified boost converters connected by a unity-gain inverter. (b) Filter capacitor is removed from the circuit and two inductors are combined into one inductor. (c) Simplified ′ circuit. (d) Conductor CC is removed. (e) Redundant components S2 and D1 are removed. boost converter with a positive input voltage is depicted in Figure 4.31(a). In Figure 4.31(b), the inductor and the diode are moved to the common rail. In Figure 4.31(c), the converter is flipped over to obtain a circuit that accepts a negative input voltage. Figure 4.32(a) shows the buck and modified boost converters connected by the unity-gain inverter, where the transistors in both the converters are synchronized to the same switching frequency fs and have the same duty cycle D. The inductors in the buck and boost converters ideally act as current sources and the dc current through the filter capacitor of the buck converter is zero for steady-state operation. Therefore, the filter capacitor can be removed Buck–Boost PWM DC–DC Converter 183 from the circuit and the two inductors can be combined into one inductor, as shown in Figure 4.32(b). A simplified ′ circuit is depicted in Figure 4.32(c). It can be seen that the current in the conductor CC is zero and therefore this conductor can be removed from the circuit. When both transistors are off and both diodes are on, the conductor is connected to an open circuit between the two transistors and conducts zero current. When both transistors are ′ on and both diodes are off, the conductor is connected to an open circuit between points B and C and conducts no current. Therefore, this conductor can be removed from the circuit, as shown in Figure 4.32(d). Finally, the redundant components S2 and D1 can be removed to obtain the inverting buck–boost converter, as depicted in Figure 4.32(e). 4.6 Synthesis of Boost–Buck (Ćuk) Converter A derivation of the boost–buck converter [16], known as the Ćuk converter, is shown in Figure 4.33. The dc-to-dc voltage transfer function of the boost–buck converter for CCM can be written as ( ) V D 1 = (−1)(D). (4.188) MVDC = O = VI 1−D 1−D This equation represents the product of the dc voltage transfer functions of boost converter, inverting unity-gain stage, and buck converter with negative input voltage, as shown in Figure 4.33(a). The circuit is redrawn in Figure 4.33(b) and it reveals a redundant MOSFET and a redundant diode. Removing the redundant components, we obtain the boost–buck (Ćuk) converter, shown in Figure 4.33(c). If we replace the horizontal capacitor by a series combination of two capacitors, a transformer can be inserted between the two capacitors and ground to obtain an isolated Ćuk converter. B A + − + − − + − + (a) B − + − A + − + (b) − + − + − + (c) Figure 4.33 Derivation of the Ćuk (boost–buck) converter. (a) Cascaded boost converter, inverting unity-gain stage, and buck converter with negative input voltage. (b) Simplified circuit to reveal redundant components. (c) Ćuk (boost– buck) converter. 184 Pulse-Width Modulated DC–DC Power Converters L + VI + C RL VO (a) L1 L2 + + VI C1 C2 RL VO (b) Figure 4.34 Noninverting cascaded buck–boost and boost–buck converters. (a) Noninverting buck–boost converter. (b) Noninverting boost–buck converter. 4.7 Noninverting Buck–Boost Converters 4.7.1 Cascaded Noninverting Buck–Boost Converters There is a great demand for a noninverting step-down/step-up dc–dc converter, especially for battery powered portable electronics applications. For example, the voltage of the lithium-ion battery changes from 4.2 to 2.8 V and the supply voltage of an electronic circuit is 3.3 V. A noninverting step-down/step-up converter can be obtained by cascading the buck and boost converters. The output filter capacitor of the buck converter can be removed and the buck output filter inductor and the boost input filter inductor can be combined to obtain a noninverting buck–boost converter shown in Figure 4.34(a). A noninverting boost–buck converter is shown in Figure 4.34(b). A noninverting synchronous boost–buck converter is shown in Figure 4.35. 4.7.2 Four-Transistor Noninverting Buck–Boost Converters A four-transistor CMOS noninverting buck–boost converter [18] is shown in Figure 4.36(a). It consists of four switches, an inductor L, and a filter capacitor C. Each pair of the transistors is a CMOS inverter that consists of an NMOS and a PMOS. Synchronous rectification is employed to increase efficiency. This is a reconfigurable converter topology. If the transistor Q3 is on and the transistor Q4 is off, a synchronous buck converter is obtained, as shown in Figure 4.36(b). The transistors Q1 and Q2 are used to control the duty cycle. If the transistor Q1 is on L1 VI Figure 4.35 Q1 Q3 L2 C1 Q2 Q4 C2 RL + VO Noninverting cascaded synchronous CMOS boost–buck converter. Buck–Boost PWM DC–DC Converter Q1 VI L Q2 Q3 C RL + VO C RL + VO RL + VO Q4 185 (a) Q1 VI L Q2 Q3 Q4 (b) L Q1 VI Q3 Q2 Q4 C (c) Figure 4.36 converter. Four-transistor CMOS noninverting buck–boost converter. (a) Circuit. (b) Buck converter. (c) Boost and the transistor Q2 is off, a synchronous boost converter is obtained, as shown in Figure 4.36(c). The transistors Q3 and Q4 are used to control the duty cycle. The input voltage VI is compared to a reference voltage to reconfigure the converter structure to the buck or boost converter. The smooth transition between the two converters may create a problem because it is difficult to achieve the duty cycle close to 0 in the boost converter and the duty cycle close to 1 in the buck converter for VI ≈ VO . A four-transistor noninverting buck–boost converter with four NMOS transistors is shown in Figure 4.37. The four-transistor noninverting buck–boost converter shown in Figure 4.38(a) can be operated in such a way that all transistors are switched in every cycle. When transistors Q1 and Q4 are on and transistors Q2 and Q3 are off in every cycle, the inductor L is charged as shown Figure 4.38(b). When transistors Q2 and Q3 are on and transistors Q1 and Q4 are off in every cycle, the inductor L is discharged into the capacitor C and the load resistor RL as shown in Figure 4.38(c). The efficiency of the converter in this mode of operation is reduced because all four switches turn on and off every cycle, increasing switching losses. Figure 4.39 shows a circuit of a switching inductor buck–boost PWM converter. The dc voltage transfer function of this circuit is MVDC = VO 2D . = VI 1−D (4.189) 186 Pulse-Width Modulated DC–DC Power Converters Q1 VI L Q2 Q3 C RL + VO C RL + VO RL + VO Q4 (a) Q1 VI L Q2 Q3 Q4 (b) L Q1 VI Q3 Q2 Q4 C (c) Figure 4.37 Four-transistor noninverting buck–boost converter with nMOS transistors. (a) Circuit. (b) Buck converter. (c) Boost converter. 4.8 Tapped-Inductor Buck–Boost Converters 4.8.1 Tapped-Inductor Common-Diode Buck–Boost Converter Tapped-inductor buck–boost converters are shown in Figure 4.40. The turns ratio of the tapped inductor is defined as Ns + Np Np v n= = =1+ . (4.190) vs Ns Ns The tapped-inductor common-diode buck–boost converter is shown in Figure 4.40(a). When the MOSFET is on, v = VI . (4.191) When the MOSFET is off, vs = V O = v . n (4.192) Hence, VI DT = −nVO (1 − D)T. (4.193) Buck–Boost PWM DC–DC Converter Q1 VI L Q2 Q3 C RL + VO C RL + VO Q4 187 (a) Q1 VI Q3 L Q2 Q4 (b) Q1 L Q3 + Q2 VI Q4 RL C VO (c) Figure 4.38 Four-transistor noninverting buck–boost converter. (a) Circuit. (b) For time interval when the inductor is charged. (c) For time interval when the inductor is discharged. Thus, the dc voltage transfer function for CCM for the tapped-inductor common-diode buck–boost converter is MVDC = VO D . =− VI n(1 − D) (4.194) Figure 4.41 shows MVDC as a function of D for the tapped-inductor common-diode converter operating in CCM. 4.8.2 Tapped-Inductor Common-Transistor Buck–Boost Converter The tapped-inductor common-transistor buck–boost converter is shown in Figure 4.40(b). When the MOSFET is on, v (4.195) vs = VI = . n L VI C L Figure 4.39 RL + VO Switching-inductor inverting buck–boost converter. 188 Pulse-Width Modulated DC–DC Power Converters Ns + vs + VI v + vp RL + VO < 0 C RL + VO < 0 C RL + VO < 0 C Np (a) VI Ns + + vs v + vp Np (b) Ns + vs + VI v + vp Np (c) Figure 4.40 Tapped-inductor buck–boost converters. (a) Tapped-inductor common-diode buck–boost converter. (b) Tapped-inductor common-tansistor buck–boost converter. (c) Tapped-inductor common-load buck–boost converter. When the MOSFET is off, v = VO . (4.196) nVI DT = −VO (1 − D)T. (4.197) Hence, The dc voltage transfer function of the tapped-inductor common-transistor buck–boost converter for CCM is MVDC = VO nD =− . VI 1−D (4.198) This transfer function is identical to the dc voltage transfer function of the flyback converter. Figure 4.42 shows plots of MVDC as a function of D for the tapped-inductor common-transistor converter operating in CCM. 4.8.3 Tapped-Inductor Common-Load Buck–Boost Converter The tapped-inductor common-load buck-boost converter is shown in Figure 4.40(b). When the MOSFET is on, vs = V I − V O = v . n (4.199) Buck–Boost PWM DC–DC Converter 189 0 −1 n=1 2 5 MVDC −2 −3 −4 −5 Figure 4.41 0 0.25 0.5 D 0.75 1 DC voltage transfer function of tapped-inductor common-diode buck–boost converter for CCM. 0 −1 5 2 n=1 MVDC −2 −3 −4 −5 Figure 4.42 0 0.25 0.5 D 0.75 1 DC voltage transfer function of tapped-inductor common-transistor buck–boost converter for CCM. 190 Pulse-Width Modulated DC–DC Power Converters 0 n = 1.2 −1 5 2 MVDC −2 −3 −4 −5 Figure 4.43 0 0.25 D 0.5 0.75 DC voltage transfer function of tapped-inductor common-load buck–boost converter for CCM. When the MOSFET is off, vp = V O = n−1 v. n (4.200) n (1 − D)T. n−1 (4.201) Hence, n(VI − VO )DT = −VO The dc voltage transfer function of the tapped-inductor common-load buck–boost converter for CCM is MVDC = VO D(n − 1) = VI n(1 − D) D< for 1 . n (4.202) Figure 4.43 shows plots of MVDC as a function of D for the tapped-inductor common-load buck–boost converter operating in CCM. Ns + vs VI Figure 4.44 Np + C vp RL + VO < 0 Tapped-inductor common-source buck–boost converter. Buck–Boost PWM DC–DC Converter 191 4.8.4 Tapped-Inductor Common-Source Buck–Boost Converter A tapped-inductor common-source buck–boost converter is shown in Figure 4.44 [21]. When the switch is on, v = nVI . (4.203) When the switch is off, n−1 v n (4.204) n (V − VI ). n−1 O (4.205) n (V − VI )(1 − D)T. n−1 O (4.206) vs = V O − V I = which gives v= Hence, nVI DT = − The dc voltage transfer function of the tapped-inductor common-source buck–boost converter operating in for CCM is given by MVDC = VO 1 − nD = VI 1−D for D> 1 . n (4.207) Figure 4.45 shows plots of the dc voltage transfer function MVDC of tapped-inductor common-source buck–boost converter for CCM. A noninverting flyback converter with two transformer terminals connected together also belongs to the inductortapped buck-boost converter family. 0 n=5 −1 2 1.2 MVDC −2 −3 −4 −5 Figure 4.45 0 0.25 0.5 D 0.75 1 DC voltage transfer function of tapped-inductor common-source buck–boost converter for CCM. 192 Pulse-Width Modulated DC–DC Power Converters 4.9 Summary r r r r r r r r r r r r r r The buck–boost converter can be derived from the buck and boost converters. The buck–boost converter can be used either as a step-down or a step-up converter. It is an inverting converter. The inductor in the buck–boost converter can be replaced by a transformer, resulting in a flyback converter. For the lossless buck–boost converter, the dc voltage transfer function is MVDC = D∕(1 − D) for CCM. For the lossy buck–boost converter, the dc voltage transfer has lower values than those for the lossless converter, especially when the duty cycle D is close to 1. For this reason, the maximum value of the dc voltage transfer function is limited. The converter should not be used at D close to 1 because its efficiency is poor for D > 0.85. Therefore, D is usually below 85%. The peak-to-peak value of the current through the filter capacitor is very high, equal to the diode peak current IDM . The input current is pulsating. It is relatively difficult to drive the transistor in the buck–boost converter because both the source and the gate of the transistor are connected to “hot” points. Therefore, the driver is floating because neither end is connected to ground. Usually, a transformer or optical coupling is required. The inductance L for DCM is much lower than that for CCM. In DCM, D1 is independent of D. The MOSFET and diode peak current for DCM is higher than that for CCM, approximately by a factor of 2. In DCM, the diode power loss is independent of the duty cycle, that is, VI . References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. [3] K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. [4] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [5] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. [6] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [7] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [8] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Upper Saddle River, NJ: Prentice Hall, 2004. [9] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [10] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. [11] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [12] B. M. Bird, K. G. King, and D. A. G. Pedder, An Introduction to Power Electronics. New York: John Wiley & Sons, 1993. [13] D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. [14] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. [15] B. Bryant and M. K. Kazimierczuk, “Derivation of PWM dc-dc buck-boost converter topology,” IEEE International Symposium on Circuits and Systems, Scottsdale, AZ, May 26–29, 2002, Paper V-841, pp. 443–446. [16] B. Bryant and M. K. Kazimierczuk, “Derivation of the Ćuk PWM dc-dc converter circuit topology,” IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 25–28, 2003, Vol. III, pp. 841–844. [17] I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. [18] M. Gaboriault and A. Notman, “A high efficiency, noninverting buck-boost dc-dc converter,” IEEE Applied Power Electronics Conference, 2004, vol. 3, pp. 1411–1415. Buck–Boost PWM DC–DC Converter 193 [19] A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. [20] M. Asano, D. Abe, and H. Koizumi, “A common grounded Z-source buck-boost converter,” IEEE International Symposium on Circuits and Systems, 2011, pp. 490–493. [21] D. A. Grant and Y. Darroman, “Extending the tapped-inductor dc-to-dc converter family,” Electronic Letters, vol. 37, no. 3, pp. 145–146, 2001. Review Questions 4.1 What is the range of the dc voltage transfer function for the lossless and lossy buck–boost converter? 4.2 How does the efficiency of the buck–boost converter change with the duty cycle? 4.3 Is it difficult to drive the transistor in the buck–boost converter? 4.4 Is the input current of the buck–boost converter pulsating? 4.5 Is the current through the filter capacitor continuous in the buck–boost converter? What is the peak-to-peak value of the capacitor current? 4.6 Is only one-half of the B–H curve of the inductor core utilized in the buck–boost converter? 4.7 Is the buck–boost converter an attractive type of converter? If so, explain why. 4.8 Is the corner frequency of the output filter dependent on the load resistance in the buck–boost converter? 4.9 Explain why the obtained circuit cannot function as a dc–dc converter, when the polarity of the diode is reversed in the buck–boost converter. Problems 4.1 A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 1–2 A, 𝜂 = 100%, and fs = 50 kHz. Find the minimum inductance required for CCM operation. 4.2 A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 1–2 A, 𝜂 = 85%, and fs = 50 kHz. Find the minimum inductance required for CCM operation. 4.3 A buck–boost PWM converter (given in Problem 4.1) has VI = 127–187 V, VO = 48 V, IO = 1–2 A, L = 420 μH, and fs = 50 kHz. Find the voltage and current stresses of the transistor and the diode. 4.4 A buck–boost PWM converter (given in Problem 4.2) has VI = 127–187 V, VO = 48 V, IO = 1–2 A, L = 420 μH, and fs = 50 kHz. Find the filter capacitance and the ESR so that Vr ∕VO ≤ 1%. 4.5 A buck–boost PWM converter employs a filter capacitor with an ESR rC = 10 mΩ. The load current is IO = 10 A and the converter operates in CCM. Calculate the power loss in the filter capacitor at D = 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9. 4.6 A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 0–2 A, 𝜂 = 100%, and fs = 50 kHz. Find the maximum inductance required for DCM operation. 4.7 A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 0–2 A, 𝜂 = 85%, and fs = 50 kHz. Find the maximum inductance required for DCM operation. 4.8 Derive an expression for the dc voltage transfer function of the lossless and lossy buck–boost PWM converter operated in DCM using the principle of energy conservation. 194 Pulse-Width Modulated DC–DC Power Converters 4.9 A buck–boost PWM converter has VI = 42–60 V, VO = 28 V, IO = 0.2–2 A, Vr ∕VO ≤ 1%, rDS = 0.1 Ω, RF = 35 mΩ, VF = 0.7 V, rL = 12 mΩ, Co = 200 pF, and fs = 100 kHz. Find the converter efficiency. 4.10 A buck–boost converter has VI = 42–60 V, VO = 28 V, IO = 0.2–2 A, rDS = 0.2 Ω, RF = 20 mΩ, VF = 0.7 V, rL = 0.15 Ω, rC = 25 mΩ, Co = 200 pF, Vr ∕VO ≤ 1%, and fs = 100 kHz. Find L, C, ISM , VSM , and 𝜂. 4.11 Design a buck–boost PWM converter to meet the following specifications: VImin = 42 V, VInom = 48 V, VImax = 60 V, VO = 28 V, IO = 0.2–2 A, Vr ∕VO ≤ 1.5%, fs = 100 kHz, rL = 0.32 Ω, rC = 33 mΩ, rDS = 0.4 Ω, RF = 20 mΩ, VF = 0.7 V, and Co = 100 pF. 4.12 In a buck–boost converter, VI = 48 ± 6 V, VO = 12 V, IO = 0.4–4 A, Vr ∕VO ≤ 1%, and fs = 200 kHz. Find L, C, and rCmax . 5 Flyback PWM DC–DC Converter 5.1 Introduction A PWM flyback dc–dc converter [1–20] is a transformer (or isolated) version of the buck–boost converter. A transformer is used to eliminate any direct (dc) electrical connection between the input and the output of the converter power stage. This safety feature is required in many applications, especially in medical equipment. For example, 1.5 kV dc isolation is typical for worldwide compliance. The safety standard in the United States is regulated by the Underwriters Laboratory (UL) in the United States of America. For most worldwide system applications, power supplies should satisfy the following safety agency standards: UL1950, VDE0805(EN60950, IEC950), and CSA C22.2, No. 950-95. In addition, the transformer allows the converters to achieve much higher or lower values of the dc voltage transfer function than their transformerless counterparts. This transformer is also called coupled inductor. Since the operating frequency of PWM converters is much higher than 50–60 Hz line frequency, the transformer, inductors, and capacitors are much smaller than those operated at line frequencies. The transformer performs several functions in the flyback converter: (1) (2) (3) (4) (5) It provides dc isolation. It stores the magnetic energy. It changes the voltage levels. The output voltages can be either positive or negative. Additional secondary transformer windings and rectifiers may be added to provide more than one output voltage of any polarity. A multiple-output transformer allows one switching-mode power supply to provide all the voltages required by most product designs, for example, 5 V, −5 V, 12 V, and −12 V. The flyback converter is used in low-power applications, typically from 20 to 200 W. It has a low parts count. The magnetizing inductance of the transformer is used to store magnetic energy, and therefore, an inductor is not required. However, a large transformer core is needed for higher power levels. An air gap is normally used to avoid core saturation. The voltage stress of the switch is high. The flyback converter is widely used in computers, TV sets, and other electronic equipment. Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 196 Pulse-Width Modulated DC–DC Power Converters 5.2 Transformers Let us consider an ideal noninverting transformer shown in Figure 5.1(a). In an ideal transformer, both coils share precisely the same magnetic flux 𝜙 = 𝜙21 = 𝜙12 and have the coupling coefficient k = 1. The voltages of the transformer are given by v1 = N1 d𝜙 dt (5.1) and d𝜙 (5.2) dt where N1 is the number of turns of the primary winding and N2 is the number of turns of the secondary winding. The ratio of the two voltages is v2 = N2 N1 d𝜙 N v1 dt = = 1 =n d𝜙 v2 N2 N2 (5.3) dt where n is the transformer turns ratio. i1 i2 n:1 + + v1 N1 N2 v2 (a) i1 i2 n:1 + + N1 v1 v2 N2 (b) i1 Ideal Transformer n :1 + v1 i2 + Lm v2 (c) Figure 5.1 Transformer. (a) Ideal noninverting transformer. (b) Ideal inverting transformer. (c) Model of a transformer consisting of an ideal noninverting transformer and a magnetizing inductance Lm . Flyback PWM DC–DC Converter 197 The instantaneous input power of the transformer is Pi = i1 v1 and the instantaneous output power of the transformer is Po = i2 v2 . Assuming that the efficiency of the transformer 𝜂 = Po ∕Pi = 1, one obtains i1 v1 = i2 v2 from which the ratio of the voltages and currents is given by i v1 = 2. v2 i1 (5.4) (5.5) From (5.3) and (5.5), one obtains the relationship among voltages, currents, and turns ratio for the ideal noninverting transformer i N v1 = 2 = 1 = n. (5.6) v2 i1 N2 Figure 5.1(b) shows an ideal inverting transformer. The input voltage is given by (5.1) and the output voltage is d𝜙 . (5.7) dt Equations (5.4) and (5.5) hold true. Therefore, the relationship for the ideal inverting transformer is given by v2 = −N2 i N v1 = 2 = − 1 = −n. v2 i1 N2 (5.8) Thus, v2 is out of phase by 180◦ with respect to v1 and i2 is out of phase by 180◦ with respect to i1 . A complete model of an actual transformer contains a number of components such as magnetizing inductance, core resistance, resistances of the windings, leakage inductances, and stray capacitances. A simple transformer model, shown in Figure 5.1(c), is usually used for analysis of PWM converters. It consists of an ideal transformer and a magnetizing inductance Lm . This model reflects the transformer capability to store magnetic energy in Lm and to transform the ac current and voltage levels. 5.3 DC Analysis of PWM Flyback Converter for CCM 5.3.1 Derivation of PWM Flyback Converter Figure 5.2 shows the derivation of the PWM flyback converter. The PWM buck–boost converter is shown in Figure 5.2(a). It is an inverting dc–dc converter. Its disadvantage is that the gate is driven with respect to a “hot” point. The inductor may be replaced by a noninverting transformer in the buck–boost converter, resulting in an inverting flyback PWM converter. The transformer magnetizing inductance Lm can be used to store the magnetic energy. Gapped cores are usually used to obtain a low magnetizing inductance Lm . The converter of Figure 5.2(b) has a gate driven with respect to a “hot” point as the buck–boost converter. This circuit can be redrawn so that the gate is driven with respect to ground, as depicted in Figure 5.2(c), because the switch and the primary of the transformer are connected in series. If the direction of the diode and the filter capacitor (if it is an electrolytic capacitor) is reversed, and the polarity of the transformer is reversed, a noninverting flyback PWM converter is obtained as shown in Figure 5.2(d). To accomplish dc isolation between the input and the output, a control circuit must also have dc isolation. Optocouplers or transformers are used to provide dc isolation in a control circuit. The transformer can have many secondary windings, and therefore a flyback converter can have multiple outputs. Some of them can have positive voltages and others negative voltages, depending upon the polarity of secondary outputs. Figure 5.3 shows a power supply, which consists of a front-end rectifier and a PWM flyback converter. 5.3.2 Circuit Description An equivalent circuit of the noninverting PWM flyback dc–dc converter is depicted in Figure 5.4. It consists of a power MOSFET operated as a switch, a transformer, a diode, and a filter capacitor C. The transformer performs two 198 Pulse-Width Modulated DC–DC Power Converters VI C RL + VO < 0 C RL + VO < 0 C RL + VO < 0 C RL + VO > 0 (a) n:1 VI (b) n:1 VI (c) n:1 VI (d) Figure 5.2 Derivation of the PWM flyback converter from the PWM buck–boost converter. (a) Buck–boost converter. (b) Flyback inverting converter. (c) Flyback inverting converter with the gate driven with respect to ground. (d) Flyback noninverting converter with the gate driven with respect to ground. vs ~ n:1 Cl Figure 5.3 + + VI C RL VO Power supply consisting of a rectifier and a PWM flyback converter. Flyback PWM DC–DC Converter i1 199 i2 n:1 + v1 Lm + vD + v2 C RL + VO C RL + VO iLm VI iS (a) i1 + v1 Lm VI i2 = iD n:1 + v2 iLm + vS (b) Figure 5.4 Equivalent circuits of the noninverting PWM flyback converter for CCM. (a) Equivalent circuit when the switch is ON and the diode is OFF. (b) Equivalent circuit when the switch is OFF and the diode is ON. functions: it provides dc isolation and stores the magnetic energy. It is the simplest transformer-isolated converter. The power level for the flyback converter is usually between 20 to 200 W. There are two modes of operation: CCM and DCM. Figures 5.4(a) and (b) show equivalent circuits of the noninverting flyback converter of Figure 5.2(d) for CCM when the switch is on and the diode is off, and when the switch is off and the diode is on, respectively. The transformer is modeled by an ideal transformer and its magnetizing inductance Lm . The principle of operation of the flyback converter is explained by the idealized waveforms of the currents and voltages shown in Figure 5.5. During the time interval 0 < t ≤ DT, the switch is on and the diode is off as indicated in Figure 5.4(a). The voltage across the diode is −(VI ∕n + VO ), which maintains the diode in the off-state. The voltage across the magnetizing inductance Lm is VI and gives rise to a linear increase of the magnetizing inductance current with a slope of VI ∕Lm . During the time interval DT < t ≤ T, the switch is off and the diode is on as shown in Figure 5.4(b). The voltage across the magnetizing inductance Lm is −nVO , which causes the magnetizing inductance current to decrease linearly with a slope of −nVO ∕Lm . The voltage across the switch is VI + nVO . At time t = T, the switch is turned on again and the next cycle begins. 5.3.3 Assumptions The analysis of the flyback PWM converter of Figure 5.4(a) is based on the following assumptions: (1) The power MOSFET and the diode are ideal switches. (2) The transistor output capacitance, the diode capacitance, and lead inductances (and thereby switching losses) are zero. (3) The transformer leakage inductances and the stray capacitances are neglected. (4) Passive components are linear, time invariant, and frequency independent. (5) The output impedance of the input voltage source VI is zero for both dc and ac components. 200 Pulse-Width Modulated DC–DC Power Converters vGS 0 t T DT vLm VI 0 DT nVO 0 iS ISM VI Lm 0 vS VI + nVO vD T DT II + DT 0 n2 VO Lm DT 0 t IO n DT 0 iD IDM t nVO Lm VI Lm iLm IO II + n T DT T t T t IO + n II T t T t VI + VO n Figure 5.5 Idealized current and voltage waveforms in the PWM inverting flyback converter for CCM. 5.3.4 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch is on and the diode off. An ideal equivalent circuit for this time interval is shown in Figure 5.4(a). When the switch is on, the voltage across the diode vD is approximately equal to −(VI ∕n + VO ), causing the diode to be reverse biased. The voltage across the switch vS and the diode current are zero. Because iD = i2 = 0, (5.9) i2 = 0. −n (5.10) i1 = Flyback PWM DC–DC Converter 201 The voltage across the magnetizing inductance Lm is given by vLm = VI = Lm diLm . dt (5.11) Hence, one obtains the current through the magnetizing inductance Lm and the switch iS = iLm = t t V 1 1 vLm dt + iLm (0) = V dt + iLm (0) = I t + iLm (0) Lm ∫0 Lm ∫0 I Lm (5.12) where iLm (0) is the initial current in the magnetizing inductance Lm at time t = 0. The peak current of the magnetizing inductance is V DT VD iLm (DT) = I + iLm (0) = I + iLm (0) (5.13) Lm fs Lm and the peak-to-peak value of the ripple current through the magnetizing inductance Lm is ΔiLm = iLm (DT) − iLm (0) = VI DT VD = I . Lm fs Lm (5.14) It will be shown shortly that the dc voltage transfer function of the flyback converter is MVDC = VO ∕VI = II ∕IO = D∕[n(1 − D)]. Hence, we can find the peak value of the diode reverse voltage ) ( V VI VDM = − + VO = − O (5.15) n D from which ( VDMmax = − VImax + VO n ) =− VO . Dmin (5.16) The peak value of the switch current ISM is I IO Δi Δi ISM = II + O + Lm = + Lm n 2 n(1 − D) 2 (5.17) ΔiLm(max) IOmax I Δi + . ISMmax = IImax + Omax + Lm = n 2 n(1 − Dmax ) 2 (5.18) which gives An increase of the magnetic energy in the magnetizing inductance Lm is ΔWLm(in) = 1 L [i2 (DT) − i2Lm (0)]. 2 m Lm (5.19) This time interval is terminated at t = DT when the switch is turned off by an external driver. The current through the magnetizing inductance iLm is a continuous function of time and because iLm (DT) is nonzero at the switch turn-off, it acts as a current source, thus turning on the diode. 5.3.5 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch is off and the diode is on. Figure 5.4(b) shows an ideal equivalent circuit for this time interval. The switch current iS and the diode voltage vD are zero. The voltage across the secondary of the transformer is v2 = V O (5.20) 202 Pulse-Width Modulated DC–DC Power Converters resulting in the voltage across the primary of the transformer v1 = −nv2 = −nVO . (5.21) Therefore, the voltage across the magnetizing inductance Lm is diLm . dt The current through the magnetizing inductance Lm can be found as vLm = −nVO = Lm t iLm = (5.22) t 1 1 v dt + iLm (DT) = (−nVO )dt + iLm (DT) Lm ∫DT Lm Lm ∫DT =− nVO nV VD (t − DT) + iLm (DT) = − O (t − DT) + I + iLm (0) Lm Lm fs Lm (5.23) where iLm (DT) is the initial current of the magnetizing inductance Lm at t = DT. The peak-to-peak value of the ripple current through the magnetizing inductance Lm is ΔiLm = iLm (DT) − iLm (T) = nVO T(1 − D) nVO (1 − D) = . Lm fs Lm (5.24) The current of the primary of the ideal transformer is i1 = −iLm = nVO (t − DT) − iLm (DT) Lm (5.25) which leads to the secondary and the diode current iD = i2 = −ni1 = niLm = − n2 V O (t − DT) + niLm (DT). Lm (5.26) Because VO ∕VI = D∕n(1 − D), the peak voltage across the switch S is given by nVO D resulting in a maximum value of the peak voltage across the switch VSM = VI + nVO = VSMmax = VImax + nVO = nVO . Dmin (5.27) (5.28) The peak diode current is IDM = nII + IO + I nΔiLm nΔiLm = O + 2 1−D 2 (5.29) which for the worst case becomes IDMmax = nIImax + IOmax + nΔiLm(max) 2 = nΔiLm(max) IOmax . + 1 − Dmax 2 (5.30) This time interval ends at t = T when the switch is turned on by a external driver. A decrease of the magnetic energy stored in the magnetizing inductance Lm during the interval DT < t ≤ T is 1 L [i2 (DT) − i2Lm (T)]. (5.31) 2 m Lm For steady-state operation, the increase in the stored magnetic energy in the magnetizing inductance ΔWLm(in) is equal to the decrease in the stored magnetic energy in the inductance ΔWLm(out) . ΔWLm(out) = Flyback PWM DC–DC Converter 203 5.3.6 DC Voltage Transfer Function for CCM Referring to Figure 5.5 and using a volt-second balance, A+ = A− , we can write DTVI = (1 − D)TnVO , (5.32) which can be rearranged to the form VO = DVI , n(1 − D) (5.33) resulting in the dc voltage transfer function of the lossless converter MV DC ≡ VO I D . = I = VI IO n(1 − D) (5.34) The range of MV DC for the lossless flyback converter for 0 ≤ D ≤ 1 is 0 ≤ MV DC < ∞. (5.35) Notice that the plot of nMV DC = D∕(1 − D) is the same as that of the dc voltage transfer function MV DC = D∕(1 − D) for the buck–boost converter given in Chapter 4. It follows from (5.33) that the output voltage VO is independent of the load resistance RL and depends only on the dc input voltage VI . It will be shown shortly that MV DC is significantly altered by losses, especially at values of D close to 1. From (5.34), D= nMV DC . nMV DC + 1 (5.36) The sensitivity of the output voltage with respect to the duty cycle is S≡ dVO VI = . dD n(1 − D)2 (5.37) In practice, VO should be held constant. If VI increases, D should be decreased by a control circuit so that VO remains constant, and vice versa. The dc current transfer function is MI DC ≡ IO n(1 − D) = . II D (5.38) and its value decreases from ∞ to zero as D is increased from 0 to 1. Using (5.34), VO VO 1 D = = = V VSM VI + nVO n n+ I (5.39) IO IO n ≈ = = n(1 − D). IO nI ISM 1+ I I + (5.40) VO and using (5.38), I n IO Thus, the switch and the diode utilization in the flyback converter is characterized by the output-power capability cp ≡ PO V I = O O = D(1 − D). VSM ISM VSM ISM (5.41) As D is increased from 0 to 1, cp increases from 0, reaches a maximum equal to 0.25 at D = 0.5, and then decreases back to zero. 204 Pulse-Width Modulated DC–DC Power Converters iLm ΔiLm(max) VImax –nVO Lm Lm lOB n VImin Lm DmaxT DminT 0 T t Figure 5.6 Waveform of the current through the magnetizing inductance Lm at the boundary between CCM and DCM for the flyback converter. 5.3.7 Boundary Between CCM and DCM Figure 5.6 depicts the current waveform of the magnetizing inductance at the boundary between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) for the flyback converter. This waveform can be described by iLm = VI t Lm 0 < t ≤ DT. (5.42) nVO (1 − D) fs Lm (5.43) nVO (1 − Dmin ) . fs Lm(min) (5.44) for Using (5.34), VI = nVO (1 − D)∕D. Hence, ΔiLm = iLm (DT) = resulting in ΔiLm(max) = The dc current through the magnetizing inductance at the boundary between CCM and DCM is ILmB = ΔiLm(max) 2 . (5.45) The energy transferred from the input dc voltage source VI to the magnetizing inductance during one cycle for the boundary case is WOB = Lm(min) Δi2Lm(max) 2 (5.46) which produces the dc output power at the boundary POB = fs Lm(min) Δi2Lm(max) fs Lm(min) n2 VO2 (1 − Dmin )2 n2 VO2 (1 − Dmin )2 WOB = fs WOB = = = . 2 T 2 2fs Lm(min) 2fs2 Lm(min) (5.47) On the other hand, the dc power transferred from the converter to the load at the CCM/DCM boundary can be expressed as POB = VO2 RLmax = VO2 RLB (5.48) Flyback PWM DC–DC Converter 205 1 0.9 0.8 2 IOB /( n VO /2fs Lm ) 0.7 0.6 CCM 0.5 0.4 0.3 DCM 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 D Figure 5.7 Normalized load current IOB ∕(n2 VO ∕2fs Lm ) at the boundary between CCM and DCM as functions of D for the flyback converter. where RLB = RLmax = VO ∕IOmin . Hence, the minimum value of the magnetizing inductance Lm is Lm(min) = n2 VO2 (1 − Dmin )2 n2 VO (1 − Dmin )2 n2 RLmax (1 − Dmin )2 = = . 2fs 2fs IOmin 2fs POmin (5.49) The load resistance RLB at the boundary between the CCM and DCM modes is 2fs Lm 2 n (1 − D)2 (5.50) n2 VO (1 − D)2 . 2fs Lm (5.51) RLB = and the load current at the boundary is IOB = Figures 5.7 and 5.8 show the normalized load current IOB ∕(n2 VO ∕2fs Lm ) = (1 − D)2 and load resistance RLB ∕(2fs Lm ∕n2 ) = 1∕(1 − D)2 at the boundary between CCM and DCM as functions of D. Ferrite material should be used for the transformer. When the relative permeability of the core magnetic material is high, the magnetic energy stored in the transformer is low. The magnetic core should contain an air gap to avoid saturation and store a large amount of magnetic energy in the air gap. 5.3.8 Ripple Voltage in Flyback Converter for CCM The output part of the flyback converter is shown in Figure 5.9, where the filter capacitor is modeled by its capacitance C and its ESR denoted by rC . Figure 5.10 displays current and voltage waveforms in the converter output circuit. The dc component of the diode current equals the dc load current IO . The ac component of the diode 206 Pulse-Width Modulated DC–DC Power Converters 40 35 2 RLB /( 2fs Lm /n ) 30 25 20 DCM 15 CCM 10 5 0 0 0.2 0.4 0.6 0.8 1 D Figure 5.8 Normalized load resistance RLB ∕(2fs Lm ∕n2 ) at the boundary between CCM and DCM as functions of D for the flyback converter. current flows approximately through the filter capacitor Cf . The peak-to-peak value of the capacitor current may be written as IO 1−D (5.52) rC IOmax . 1 − Dmax (5.53) ICpp = IDM ≈ nII + IO = resulting in the peak-to-peak value of the voltage across rC Vrcpp = rC ICpp ≈ The peak-to-peak value of the output ripple voltage Vr is usually specified. Hence, the maximum peak-to-peak value of the ac component of the voltage across the capacitance C is found as Vcpp ≈ Vr − Vrcpp . iD C rC Figure 5.9 (5.54) IO iC + vC + vrc RL + VO Output circuit of the flyback converter. Flyback PWM DC–DC Converter iD nII + IO = IDM 0 DT iC 0 − IO −ΔQ ΔQ T t nII = IO = DT T t DT T t 207 IO 1− D IO 1− D vrc 0 vc DT 0 T t vo 0 Figure 5.10 DT Vr T t Waveforms illustrating the ripple voltage in the PWM flyback converter. On the other hand, this voltage is approximately given by Vcpp = I VO Dmax D T ΔQmax = Omax max = Cmin Cmin fs RLmin Cmin (5.55) where ΔQmax is the charge decrease during the time interval from zero to DT. Rearrangement of (5.55) gives Cmin = IOmax Dmax Dmax VO = . fs Vcpp fs RLmin Vcpp (5.56) 5.3.9 Power Losses and Efficiency of Flyback Converter for CCM An equivalent circuit of the flyback converter with parasitic resistances is shown in Figure 5.11. In this figure, rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the magnetizing inductance Lm representing core losses, and rC is the ESR of the filter capacitor C. The conduction losses will be found assuming that the magnetizing inductance current iLm is ripple free. Hence, the switch current can be approximated by { I IO , for 0 < t ≤ DT II + nO = n(1−D) (5.57) iS = 0, for DT < t ≤ T 208 Pulse-Width Modulated DC–DC Power Converters n:1 Lm rL VI rT1 rDS Figure 5.11 IO RF VF rT 2 C rC iD iL m iC RL + VO iS Equivalent circuit of the flyback converter with parasitic resistances and the diode offset voltage. resulting in its rms value √ ISrms = T IO 1 i2S dt = T ∫0 n(1 − D) √ 1 T ∫0 DT √ IO D , dt = n(1 − D) (5.58) resulting in the conduction loss in the MOSFET and in the primary winding of the transformer 2 PrDS = rDS ISrms = rDS DIO2 = DrDS PO (1 − D)2 n2 RL (5.59) = DrT1 PO . (1 − D)2 n2 RL (5.60) n2 (1 − D)2 and the primary winding of the transformer 2 PrT1 = rT1 ISrms = rT1 DIO2 n2 (1 − D)2 Assuming that the transistor output capacitance Co is linear, the switching loss is expressed as 2 Psw = fs Co VSM = fs Co (VI + nVO )2 = = fs Co n2 VO2 D2 = fs Co VO2 (1 + nMV DC )2 MV2 DC fs Co n2 RL PO fs Co RL (1 + nMV DC )2 PO = . D2 MV2 DC Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power) ] [ DrDS IO2 Psw fs Co n2 RL DrDS 1 2 = 2 PO + f C (V + nVO ) = + PFET = PrDS + 2 n (1 − D)2 2 s o I (1 − D)2 n2 RL 2D2 [ ] DrDS fs Co RL (1 + nMV DC )2 = + PO . (1 − D)2 n2 RL 2MV2 DC Similarly, the diode current may be approximated by { 0, iD = IO nII + IO = 1−D , which yields its rms value √ IDrms = T I 1 i2D dt = O T ∫0 1−D for 0 < t ≤ DT for DT < t ≤ T √ T I 1 dt = √ O T ∫DT 1−D (5.61) (5.62) (5.63) (5.64) Flyback PWM DC–DC Converter 209 leading to the power loss in the diode forward resistance RF RF IO2 = RF PO (1 − D)RL (5.65) = rT2 PO . (1 − D)RL (5.66) T T IO 1 iD dt = dt = IO T ∫0 (1 − D)T ∫DT (5.67) 2 PRF = RF IDrms = 1−D and the resistance in the secondary winding of the transformer rT2 IO2 2 = PrT2 = rT2 IDrms 1−D The average value of the diode current is ID = which gives the power loss associated with the voltage VF PVF = VF ID = VF IO = VF PO . VO (5.68) Thus, the overall diode conduction loss is PD = PVF + PRF = VF IO + RF IO2 1−D [ = PO ] RF VF . + VO (1 − D)RL (5.69) The current through the magnetizing inductance is IO I iLm ≈ II + O = n n(1 − D) (5.70) IO I ILm(rms) ≈ II + O = n n(1 − D) (5.71) leading to its rms value and the conduction loss in rL 2 PrL = rL ILm(rms) = rL IO2 n2 (1 − D)2 = rL PO . (1 − D)2 n2 RL (5.72) The current through the filter capacitor is { iC = −IO , for 0 < t ≤ DT DIO nII = 1−D , for DT < t ≤ T and the rms current through the filter capacitor is found as √ √ √ T √ 1 D 1−D 2 = IL D(1 − D) = IS i dt = IO ICrms = T ∫0 C 1−D D (5.73) (5.74) and the power loss in the filter capacitor 2 = PrC = rC ICrms DrC IO2 1−D = DrC PO . (1 − D)RL (5.75) 210 Pulse-Width Modulated DC–DC Power Converters The overall power loss is given by PLS = PrDS + PrT1 + Psw + PD + PrT2 + PrL + PrC DrC IO2 + 1−D 1−D n2 (1 − D)2 n2 (1 − D)2 [ ] D(rDS + rT1 ) + rL RF + rT2 + DrC VF fs Co RL (1 + nMV DC )2 + + + = PO . (1 − D)RL VO (1 − D)2 n2 RL MV2 DC = (rDS + rT1 )DIO2 + fs Co (VI + nVO )2 + VF IO + (RF + rT2 )IO2 + rL IO2 (5.76) Thus, the converter efficiency is 𝜂= PO 1 1 = = . PLS D(rDS +rT1 )+rL RF +rT2 +DrC f C R (1+nMV DC )2 V PO + PLS 1+ 1+ + + F + s o L PO (1−D)2 n2 R (1−D)RL L VO (5.77) MV2 DC 5.3.10 DC Voltage Transfer Function of Lossy Converter for CCM The dc component of the input current is T II = 1 1 i dt = T ∫0 S T ∫0 DT IO D IO dt = . n(1 − D) n(1 − D) (5.78) Hence, one obtains the dc current transfer function of the flyback converter MI DC ≡ IO n(1 − D) . = II D (5.79) This equation holds true for both lossless and lossy converter. The converter efficiency can be expressed as 𝜂= PO V I n(1 − D)MV DC = O O = MV DC MI DC = PI VI II D (5.80) from which the voltage transfer function of the lossy flyback converter is MV DC = 𝜂 𝜂D D . = = MI DC n(1 − D) n(1 − D)[1 + D(rDS +rT1 )+rL + RF +rT2 +DrC + VF + fs Co n2 RL ] n2 RL (1−D)2 RL (1−D) VO (5.81) D2 Hence, the duty cycle for the lossy converter is given by D= nMV DC 1 = nMV DC + 𝜂 1+ 𝜂 . (5.82) nMV DC Notice that the duty cycle D at a given dc voltage transfer function is greater for the lossy converter than that for the lossless converter. Substitution of (5.82) into (5.77) yields the efficiency of the flyback converter for CCM 𝜂= N𝜂 D𝜂 (5.83) Flyback PWM DC–DC Converter 211 where MV DC (2rL + rDS + rT1 ) nMV DC (RF + rT2 + rC ) − nRL RL ] {[ (2r + rDS + rT1 ) nMV DC (RF + rT2 + rC ) 2 M + 1 − V DC L − nRL RL [ ]} 12 2 4MV DC (rDS + rT1 + rL ) r R + rT2 VF fs Co RL (1 + nMV DC )2 1 + 2L + F − + + RL RL VO n RL MV2 DC N𝜂 = 1 − and [ r R + rT2 VF fs Co RL (1 + nMV DC )2 D𝜂 = 2 1 + 2 L + F + + RL VO n RL MV2 DC (5.84) ] . (5.85) 5.3.11 Design of Flyback Converter for CCM Design a universal power supply that accepts a single-phase utility line voltage from 85 to 264 Vrms at frequencies 50, 60, and 400 Hz, VO = 5 V, IO = 1–10 A, and Vr ∕VO ≤ 1%. Solution: The maximum and minimum output powers are POmax = VO IOmax = 5 × 10 = 50 W (5.86) POmin = VO IOmin = 5 × 1 = 5 W. (5.87) and The minimum and maximum load resistances are RLmin = VO 5 = 0.5 Ω = IOmax 10 (5.88) and RLmax = VO 5 = 5 Ω. 1 (5.89) 2 = 120.21 V (5.90) = IOmin The minimum and maximum dc input voltages are VImin = 85 × and VImax = 264 × √ √ 2 = 373.35 V. (5.91) Hence, the minimum and maximum values of the dc voltage transfer function are MV DCmin = VO 5 = 0.01339 = VImax 373.35 (5.92) MV DCmax = VO 5 = = 0.04159. VImin 120.21 (5.93) and Assume the converter efficiency 𝜂 = 80% and Dmax = 0.36. Hence, the transformer turns ratio is n= Let n = 11. 𝜂Dmax 0.8 × 0.36 = 10.82. = (1 − Dmax )MV DCmax (1 − 0.36) × 0.04159 (5.94) 212 Pulse-Width Modulated DC–DC Power Converters The minimum and maximum duty cycle is Dmin = nMV DCmin 11 × 0.01339 = = 0.1555 nMV DCmin + 𝜂 11 × 0.01339 + 0.8 (5.95) Dmax = nMV DCmax 11 × 0.04159 = = 0.3638. nMV DCmax + 𝜂 11 × 0.04159 + 0.8 (5.96) and Assuming the switching frequency fs = 100 kHz, the minimum magnetizing inductance is Lm(min) = n2 RLmax (1 − Dmin )2 112 × 5 × (1 − 0.1555)2 = = 2.157 mH. 2fs 2 × 105 (5.97) Pick Lm = 2.5 mH. The peak-to-peak value of the ac component of the current through the magnetizing inductance is ΔiLm(max) = nVO (1 − Dmin ) 11 × 5 × (1 − 0.1555) = = 0.1858 A. fs Lm 105 × 2.5 × 10−3 (5.98) The maximum dc input current occurs at VImin = 120.21 V, which corresponds to the maximum dc voltage transfer function MV DCmax = 0.04159. This current is given by IImax = MV DCmax IOmax = 0.04159 × 10 = 0.4159 A. (5.99) The current and voltage stresses of the semiconductor devices are ΔiLm(max) I 10 0.1858 = 0.4159 + + = 1.418 A, ISMmax = IImax + Omax + n 2 11 2 IDMmax = nIImax + IOmax + nΔiLm(max) 2 = 11 × 0.4159 + 10 + 11 × 0.1858 = 15.597 A, 2 VSMmax = VImax + nVO = 373.35 + 11 × 5 = 428.35 V, (5.100) (5.101) (5.102) and VImax 373.35 + VO = + 5 = 38.94 V. (5.103) n 11 Let us select an International Rectifier IRF840 power MOSFET whose VDSS = 500 V, ISM = 8 A, rDS = 0.85 Ω, Qg = 42 nC, and Co = 100 pF, and an MBR2540 Schottky barrier diode whose IDM = 25 A, VDM = 40 V, VF = 0.3 V, and RF = 10 mΩ. The ripple voltage is VDMmax = Vr = 0.01VO = 0.01 × 5 = 50 mV. (5.104) Let us assume Vrcpp = 40 mV and VCpp = 10 mV. Hence, one obtains the maximum value of the ESR of the filter capacitor rCmax = Vrcpp IDMmax = 40 × 10−3 = 2.56 mΩ 15.597 (5.105) and the filter capacitance Cmin = Pick C = 4 mF/25 V/2.5 mΩ. Dmax VO 0.3638 × 5 = 5 = 3.638 mF. fs RLmin VCpp 10 × 0.5 × 0.01 (5.106) Flyback PWM DC–DC Converter 213 The power losses and the converter efficiency will be calculated at the maximum load current IOmax = 10 A and the maximum input voltage VImax = 373.35 V. The rms value of the current through the magnetizing inductance is I 10 ILm(rms) ≈ ILm = IImax + Omax = 0.4159 + = 1.325 A. n 11 Assuming the dc value of rL = 350 mΩ, one obtains 2 = 0.35 × 1.3252 = 0.6145 W. PrL = rL ILm(rms) The switch rms current is √ 10 0.3638 = = 0.8619 A ISrms = n(1 − Dmax ) 11 × (1 − 0.3638) √ IOmax Dmax (5.107) (5.108) (5.109) which gives the MOSFET conduction loss 2 PrDS = rDS ISrms = 0.85 × 0.86192 = 0.6313 W. (5.110) Assuming the resistance of the primary winding of the transformer rT1 = 0.9 Ω, the conduction loss in rT1 is 2 = 0.9 × 0.86182 = 0.6684 W. PrT1 = rT1 ISrms (5.111) The switching loss is Psw = fs Co n2 VO2 D2min = 105 × 100 × 10−12 × 112 × 52 = 1.251 W. 0.15552 (5.112) Hence, PFET = PrDS + Psw 1.251 = 0.6313 + = 0.6313 + 0.625 = 1.256 W. 2 2 (5.113) The rms diode current is I 10 IDrms = √ Omax = √ = 12.537 A. 1 − Dmax 1 − 0.3638 (5.114) Thus, the power loss due to RF is 2 = 0.01 × 12.5372 = 1.572 W PRF = RF IDrms (5.115) PVF = VF IOmax = 0.3 × 10 = 3 W, (5.116) PD = PVF + PRF = 3 + 1.572 = 4.572 W. (5.117) and the power loss due to VF is resulting in the diode conduction loss Assuming the resistance of the secondary winding of the transformer rT2 = 20 mΩ, the power loss in rT2 is 2 = 0.02 × 12.5372 = 3.144 W. PrT2 = rT2 IDrms The rms current of the filter capacitor is √ ICrms = IOmax Dmax = 10 1 − Dmax √ 0.3638 = 7.562 A. 1 − 0.3638 (5.118) (5.119) Hence, the power loss in the ESR of the filter capacitor is 2 = 0.0025 × 7.5622 = 0.143 W. PrC = rC ICrms (5.120) 214 Pulse-Width Modulated DC–DC Power Converters 90 RL = 1 Ω R = 0.5 Ω L 85 80 η (%) RL = 5 Ω 75 70 65 100 150 200 250 V (V) 300 350 400 I Figure 5.12 Efficiency 𝜂 versus dc input voltage VI at various load resistances RL for the flyback converter in CCM. The total power loss is PLS = PrDS + Psw + PD + PrL + PrT1 + PrT2 + PrC = 0.6313 + 1.25 + 4.572 + 0.6144 + 0.6684 + 3.144 + 0.143 = 11.0231 W. (5.121) Hence, the converter efficiency at full power is 𝜂= POmax 50 = 81.9%. = POmax + PLS 50 + 11.0231 (5.122) A rectangular positive gate-to-source voltage of magnitude VGSm = 8 V is used to drive the MOSFET. Therefore, the gate-drive power is PG = fs Qg VGSm = 105 × 42 × 10−9 × 8 = 33.6 mW. (5.123) Using (5.83) through (5.85), one can calculate the efficiency 𝜂 as a function of the dc input voltage VI at fixed load resistances RL for the designed flyback converter in CCM; the plots are depicted in Figure 5.12. Knowing the efficiency 𝜂, the duty cycle D can be computed from (5.82). Figure 5.13 shows the duty cycle D as a function of dc input voltage VI for the flyback converter designed for CCM. Figures 5.14 and 5.15 show the efficiency 𝜂 as a function of the dc output current IO at fixed dc input voltages VI , respectively. Plots of the efficiency 𝜂 and the duty cycle D versus the load resistance RL at fixed dc input voltages VI are depicted in Figures 5.16 and 5.17. The duty cycle D decreases as VI increases. 5.4 DC Analysis of PWM Flyback Converter for DCM Equivalent circuits for the PWM flyback converter operating in the DCM are depicted in Figure 5.18. Idealized current and voltage waveforms are shown in Figure 5.19. Prior to time t = 0, the current through the magnetizing Flyback PWM DC–DC Converter 215 0.4 0.35 RL = 0.5 Ω D 0.3 0.25 RL = 1 Ω R =5Ω L 0.2 0.15 0.1 100 150 200 250 V (V) 300 350 400 I Figure 5.13 Duty cycle D versus dc input voltage VI at fixed load resistances RL for the flyback converter in CCM. 90 V = 120 V I V I = 187 V 85 V = 373 V I η (%) 80 75 70 65 60 1 2 3 4 5 I (A) 6 7 8 9 10 O Figure 5.14 Efficiency 𝜂 versus dc load current IO at fixed values of dc input voltage VI for the flyback converter in CCM. 216 Pulse-Width Modulated DC–DC Power Converters 0.4 V I = 120 V 0.35 D 0.3 V = 187 V I 0.25 0.2 V = 373 V 0.15 I 1 2 3 4 5 I (A) 6 7 8 9 10 O Figure 5.15 in CCM. Duty cycle D versus dc load current IO at fixed values of dc input voltage VI for the flyback converter 90 V I = 120 V 85 V I = 187 V η (%) 80 75 V I = 373 V 70 65 60 0.5 Figure 5.16 1 1.5 2 2.5 3 RL (Ω) 3.5 4 4.5 5 Efficiency 𝜂 versus load resistance RL at dc fixed values of input voltage VI for the flyback converter in CCM. Flyback PWM DC–DC Converter 217 0.4 V I = 120 V 0.35 D 0.3 V = 187 V I 0.25 0.2 V = 373 V I 0.15 0.5 1 1.5 2 2.5 3 R (Ω) 3.5 4 4.5 5 L Figure 5.17 in CCM. Duty cycle D versus load resistance RL at dc fixed values of input voltage VI for the flyback converter inductance Lm is zero. At time t = 0, the switch is turned on. The diode remains off. The voltage across the magnetizing inductance is VI and the current through this inductance increases linearly from zero. At time t = DT, the switch is turned off and the diode turns on. The voltage across the magnetizing inductance is −VO . Therefore, the current through the magnetizing inductance decreases linearly. This current is reflected to the secondary of the transformer and flows through the diode. Once the diode current reaches zero, the diode begins to turn off. The current through the magnetizing inductance is zero until the switch is turned on. 5.4.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is on and the diode is off. The equivalent circuit is shown in Figure 5.18(a). The current through the diode and the secondary is iD = i2 = 0, resulting in the current through the primary i1 = −i2 ∕n = 0. The voltage across the primary and the magnetizing inductance Lm is v1 = vLm = VI = Lm diLm , dt iLm (0) = 0 (5.124) and the magnetizing inductance and switch current is iS = iLm = t t V 1 1 vLm dt = VI dt = I t. Lm ∫0 Lm ∫0 Lm (5.125) Hence, one obtains the peak value of the switch current and the magnetizing inductance current ISM = iLm(max) = ΔiLm = iLm (DT) = VI DT VD = I . Lm fs Lm (5.126) 218 Pulse-Width Modulated DC–DC Power Converters i2 i1 n:1 + v1 Lm + vD + v2 C RL + VO C RL + VO C RL + VO iLm VI iS (a) i1 i2 = iD n:1 + v1 Lm + v2 iLm VI + vS (b) i1 + v1 Lm VI i 2 = iD n:1 + v2 + vD iLm iS + vS (c) Figure 5.18 Equivalent circuits of the PWM flyback converter for DCM. (a) Equivalent circuit when the switch is ON and the diode is OFF. (b) Equivalent circuit when the switch is OFF and the diode is ON. (c) Equivalent circuit when both the switch and the diode are OFF. The voltage across the secondary winding is V v v2 = − 1 = − I , n n (5.127) ) VI + VO , n (5.128) VImax + VO . n (5.129) resulting in the voltage across the diode ( vD = − from which VDM(max) = This time interval ends when the switch is turned off by the driver. Flyback PWM DC–DC Converter 219 vGS 0 vLm t T DT VI 0 DT −nVO iLm Δ iLm 0 VI Lm − DT D1T T t T t T t nVO Lm iS 0 vS DT VI + nVO VI 0 iD 0 vD2 0 DT T t DT T t DT T VI + VO n Figure 5.19 VO t Idealized current and voltage waveforms in the PWM flyback converter for DCM. 5.4.2 Time Interval: DT < t ≤ (D + D1 )T The equivalent circuit for this time interval is shown in Figure 5.18(b). The switch is off and the diode is on. Hence, iS = 0 and vD = 0. Since v2 = V O , (5.130) the voltage across the magnetizing inductance Lm and the primary of the transformer is v1 = vLm = −nv2 = −nVO = Lm diLm . dt (5.131) 220 Pulse-Width Modulated DC–DC Power Converters From (5.126), the current through the magnetizing inductance is t iLm = t 1 1 v dt + iLm (DT) = (−nVO )dt + iLm (DT) Lm ∫DT Lm Lm ∫DT =− nVO nV V DT (t − DT) + iLm (DT) = − O (t − DT) + I . Lm Lm Lm (5.132) Since b ∫a a (−x)dx = − ∫b a (−x)dx = ∫b xdx, (5.133) the peak value of this current is DT ΔiLm = DT nVO D1 1 1 vLm dt = (−nVO )dt = . ∫ ∫ Lm (D+D1 )T Lm (D+D1 )T fs Lm (5.134) Using (5.132), one arrives at the current through the primary of the transformer i1 = −iLm = nVO VD (t − DT) − I Lm fs Lm (5.135) and the current through the diode and the secondary of the transformer iD = i2 = −ni1 = − n2 V O nV D (t − DT) + I . Lm fs Lm (5.136) Thus, from (5.126), the peak value of the diode current is nVI D . fs Lm (5.137) v1 = −nv2 = −nVO , (5.138) vS = VSM = VI − v1 = VI + nVO , (5.139) VSMmax = VImax + nVO . (5.140) IDM = nISM = Because the peak voltage across the switch is which produces This time interval ends when the diode current reaches zero. 5.4.3 Time Interval: (D + D1 )T < t ≤ T During this time interval, both the switch and the diode are off. The equivalent circuit is shown in Figure 5.18(c). For this circuit, iD = i2 = 0 (5.141) i1 = 0. (5.142) iS = 0. (5.143) resulting in Also, Flyback PWM DC–DC Converter 221 Because both iS and i1 = 0, iLm = 0. (5.144) Hence, v1 = vLm = Lm diLm = 0, dt (5.145) resulting in v2 = 0. (5.146) vS = V I (5.147) vD = −VO . (5.148) The voltage across the switch is and the voltage across the diode is This time interval ends when the switch is turned on by the driver. 5.4.4 DC Voltage Transfer Function for DCM Method I: Referring to Figure 5.19 and using the volt-second balance for vLm , VI DT = nVO D1 T (5.149) which leads to MV DC = VO I D = I = . VI IO nD1 (5.150) Using (5.126), the dc output current is found as T IO = (D+D1 )T 1 1 i dt = T ∫0 D T ∫DT iD dt = V D1 nΔiLm nDD1 VI = = O 2 2fs Lm RL (5.151) resulting in MV DC = VO nDD1 RL = . VI 2fs Lm (5.152) Equating the right-hand sides of (5.150) and (5.152) produces √ √ 2fs Lm 2fs Lm IO D1 = = n2 R L n2 V O and substitution of this into (5.150) yields √ MV DC = D Hence, D = MV DC √ VO RL =D . 2fs Lm IO 2fs Lm √ √ 2fs Lm IO = MV DC VO (5.153) √ √ 2fs Lm RL for D<1− (5.154) 2fs Lm IO =1− n2 V O 2fs Lm . n2 R L (5.155) 222 Pulse-Width Modulated DC–DC Power Converters Since the magnetizing inductance reflected to the transformer secondary is given by Lms = one obtains Lm , n2 (5.156) √ D MV DC = n and √ D = nMV DC √ VO D = 2fs Lms IO n RL 2fs Lms √ √ √ 2fs Lms = nMV DC RL (5.157) 2fs Lms IO VO for D<1− At the boundary between DCM and CCM, 2fs Lms IO =1− VO 2fs Lms . RL (5.158) √ D DB MV DCB = = B n(1 − DB ) n RL . 2fs Lms Hence, one obtains the duty cycle at the boundary √ √ √ √ 2fs Lm IO 2fs Lm 2fs Lms IO 2fs Lms DB = 1 − =1− =1− =1− . 2 2 V RL n VO n RL O Using (5.155) and (5.160), the dc voltage transfer function at the boundary is obtained as √ √ √ √ n2 V O VO n2 R L RL −1= −1= −1= − 1. nMV DCB = 2fs Lm IO 2fs Lm 2fs Lms IO 2fs Lms (5.159) (5.160) (5.161) Figures 5.20 and 5.21 depict plots of D versus IO ∕(VO ∕2fs Lms ) and RL ∕(2fs Lms ) at various values of nMV DC for both CCM and DCM, respectively. Plots of nMV DC versus IO ∕(VO ∕2fs Lms ) and RL ∕(2fs Lms ) at various values of D are shown in Figures 5.22 and 5.23. Method II: The dc component of the input current equals the dc component of the switch current ) DT DT ( D2 VI VI 1 1 II = IS = tdt = iS dt = . (5.162) T ∫0 T ∫0 Lm 2fs Lm Therefore, the dc input power is PI = VI II = D2 VI2 2fs Lm . (5.163) The dc output power is PO = VO2 RL . (5.164) Equating right-hand sides of (5.163) and (5.164), one obtains (5.154). 5.4.5 Maximum Magnetizing Inductance for DCM The minimum value of the magnetizing inductance peak current at the boundary between the DCM and CCM occurs at D = DBmax . From (5.43), ΔiLm(min) = nVO (1 − DBmax ) . fs Lm(max) (5.165) Flyback PWM DC–DC Converter 223 1 nM VDC 0.9 0.8 =7 3 0.7 1.5 D 0.6 1 0.5 CCM 0.4 0.5 DCM 0.3 0.3 0.2 0.1 0.1 0 0 0.2 0.4 0.6 I /(V /2f L ) O O 0.8 1 s ms Figure 5.20 Duty cycle D as a function of normalized load current IO ∕(VO ∕2fs Lms ) at fixed values of MV DC for the lossless flyback converter in CCM and DCM. 1 0.9 0.8 nM VDC =7 3 CCM DCM 0.7 D 0.6 0.5 1.5 1 0.4 0.3 0.5 0.2 0.3 0.1 0 0 10 0.1 1 10 2 RL/(2fsLms) 10 3 10 Figure 5.21 Duty cycle D as a function of load resistance RL ∕(2fs Lms ) at fixed values of MV DC for the lossless flyback converter in CCM and DCM. 224 Pulse-Width Modulated DC–DC Power Converters 5 4.5 D = 0.8 4 CCM 3.5 0.75 nM VDC 3 2.5 0.7 2 0.6 1.5 0.5 1 0.4 DCM 0.5 0 0.2 0 0.2 0.4 0.6 I /(V /2f L ) O O 0.8 1 s ms Figure 5.22 DC voltage transfer function MV DC as a function of normalized load current IO ∕(VO ∕2fs Lms ) at fixed values of D for the lossless flyback converter. 5 4.5 4 D = 0.8 CCM 3.5 nM VDC 3 2.5 0.75 0.7 DCM 2 1.5 1 0.6 0.5 0.4 0.5 0 0 10 0.2 1 10 R /(2f L L 2 10 ) s ms Figure 5.23 DC voltage transfer function MV DC as a function of normalized load resistance RL ∕(2fs Lms ) at fixed values of D for the lossless flyback converter. Flyback PWM DC–DC Converter 225 The dc current through the magnetizing inductance at the boundary between CCM and DCM is ILmB = ΔiLm(min) 2 = nVO (1 − DBmax ) . 2fs Lm(max) (5.166) The energy transferred from the input dc voltage source VI to the magnetizing inductance during one cycle for the boundary case is WOB = Lm(max) Δi2Lm(min) 2 (5.167) which results in the dc output power at the boundary fs Lm(max) Δi2Lm(min) fs Lm(max) n2 VO2 (1 − DBmax )2 n2 VO2 (1 − DBmax )2 WOB = fs WOB = = = . POB = POmax = 2 T 2 2fs Lm(max) 2fs2 Lm(max) (5.168) The dc power transferred from the converter to the load at the boundary can be expressed as POB = VO2 RLmin . (5.169) Hence, the maximum value of the magnetizing inductance Lm is Lm(max) = n2 VO2 (1 − DBmax )2 n2 VO (1 − DBmax )2 n2 RLmin (1 − DBmax )2 = = . 2fs 2fs IOB 2fs POmax Another method for deriving an expression for Lm is as follows. The dwell-duty ratio at full power is √ √ 2fs Lm 2fs Lm Dw = 1 − Dmax − D1max = 1 − MV DCmax − 𝜂RLmin n2 RLmin (5.170) (5.171) resulting in Lm(max) = RLmin (1 − Dw )2 . 2fs ( MV DCmax 1 )2 √ +n 𝜂 (5.172) 5.4.6 Ripple Voltage in Flyback Converter for DCM The peak-to-peak value of the capacitor current is ICpp = IDM = nVO D1 nDVI = fs Lm fs Lm (5.173) resulting in the peak-to-peak value of the voltage across rC Vrcpp = rC IDM = rC nDVI r nV D = C O 1. fs Lm fs Lm (5.174) The voltage drop across the capacitor Vcpp ≈ Vr − Vrcpp . (5.175) The voltage across the capacitance is Vcpp = I VO Dmax D T ΔQmax = Omax max = Cmin Cmin fs RLmin Cmin (5.176) 226 Pulse-Width Modulated DC–DC Power Converters where ΔQmax is the charge decrease during the time interval from zero to DT. Rearrangement of (5.55) gives Cmin = IOmax Dmax Dmax VO = . fs Vcpp fs RLmin Vcpp (5.177) 5.4.7 Power Losses and Efficiency of Flyback Converter for DCM The peak current through the magnetizing inductance and the switch is DVO DVI ΔiLm = ISM = = = VO fs Lm fs Lm MV DC The rms value of the switch current is √ ISrms = 1 T ∫0 √ DT √ i2S dt = ΔiLm D = VO 3 DrDS Δi2Lm 2rDS DVO2 2 . fs Lm RL √ (5.178) 2D . 3fs Lm RL (5.179) = 2DrDS P 3fs Lm O (5.180) = 2DrT1 P . 3fs Lm O (5.181) Therefore, the MOSFET conduction loss is 2 PrDS = rDS ISrms = = 3 3fs Lm RL and the conduction loss in the primary winding resistance rT1 is 2 PrT1 = rT1 ISrms = DrT1 Δi2Lm 3 = 2rT1 DVO2 3fs Lm RL The maximum conduction loss in rDS and rT1 occurs at a full-load resistance RLmin and a low input voltage VImin . At low input voltage VImin , the duty cycle takes on a maximum value Dmax . At a full-load resistance RLmin , a large current is drawn from the line. Both these effects result in a maximum value of the switch rms current ISrms . The switching loss is given by ( )2 1 2 = fs Co (VI + nVO )2 = n2 fs Co VO2 +1 Psw = fs Co VSM nMV DC √ ( )2 ( )2 2fs Lm 1 2 2 = n fs Co RL + 1 PO = n fs Co RL + 1 PO . (5.182) nMV DC n2 D2 RL The maximum switching loss occurs at the maximum switch voltage VSMmax = VImax + nVO and is independent of the load. The peak diode current is √ 2 IDM = nΔiLm = nVO (5.183) fs Lm RL and the rms value of the diode current is √ ( )0.25 √ (D+D1 )T D1 1 8n2 2 = VO IDrms = iD dt = nΔiLm . T ∫DT 3 9fs Lm R3 (5.184) L Hence, the power loss in the diode due to RF is 2 PRF = RF IDrms = 2 D1 RF IDM 3 = D1 RF n2 Δi2Lm 3 = 2nRF VO2 3RL √ 2nRF 2 = fs Lm RL 3 √ 2 P fs Lm RL O (5.185) Flyback PWM DC–DC Converter 227 and the conduction loss in the secondary winding resistance rT2 is 2 PrT2 = rT2 IDrms = 2 D1 rT2 IDM 3 = D1 rT2 n2 Δi2Lm 3 = 2nrT2 VO2 √ 3RL 2nrT2 2 = fs Lm RL 3 √ 2 P . fs Lm RL O (5.186) The average diode current is ID = IO , resulting in the diode loss associated with VF PVF = VF ID = VF IO = VF P . VO O ( √ Thus the overall diode conduction loss is PD = PVF + PRF = VF 2nRF + VO 3 (5.187) 2 fs Lm RL ) PO . (5.188) Using (5.153), (5.155), and (5.178), the rms value of the current through the magnetizing inductance is √ √ √ ( ) √ √ (D+D1 )T √ 2D 2fs Lm D + D 1 √ 1 2 ILm(rms) = 1+ . (5.189) = VO iLm dt = ΔiLm T ∫0 3 3fs Lm RL n2 D2 RL The power loss in rL is therefore given by 2 PrL = rL ILm(rms) = rL Δi2Lm (D + D1 ) 3 = 2rL DVO2 3fs Lm RL ( 1+ √ 2fs Lm n2 D2 RL ) 2r D = L 3fs Lm √ ( 1+ 2fs Lm n2 D2 RL ) PO . (5.190) The total power loss in the converter is ⎡ 2D(r + r ) 2n(R + r ) √ 2 DS T1 F T2 + PLS = PrDS + Psw + PrT1 + PD + PrT2 + PrL = ⎢ ⎢ 3fs L 3 fs Lm RL ⎣ √ )2 ( ) (√ ⎤ 2fs Lm 2fs Lm 2DrL VF 2 + + n fs Co RL + 1 ⎥ PO . 1+ + 2 2 2 2 ⎥ 3fs Lm VO n D RL n D RL ⎦ (5.191) This leads to the converter efficiency 𝜂≡ √ ⎡ PO PO 1 2 ⎢1 + 2D(rDS + rT1 ) + 2n(RF + rT2 ) = = = P ⎢ PI PO + PLS 3fs Lm 3 fs Lm RL 1 + PLS ⎣ O 2DrL + 3fs Lm [ = 1+ (√ 2fs Lm +1 n2 D2 RL 2MV DC (rDS + rT1 ) 3 2r M + L V DC 3 √ 2 fs Lm RL ) √ ( V + F + n2 fs Co RL VO (√ 2n(RF + rT2 ) 2 + fs Lm RL 3 2fs Lm +1 n2 D2 RL √ )2 −1 ⎤ ⎥ ⎥ ⎦ 2 fs Lm RL ( ) )2 ]−1 VF 1 1 2 +1 + + n fs Co RL +1 . nMV DC VO nMV DC (5.192) 228 Pulse-Width Modulated DC–DC Power Converters The dc input current is given by II = 1 T ∫0 DT iLm dt = 1 T ∫0 DT VI t V D2 dt = I Lm 2fs Lm (5.193) producing the dc input power PI = VI II = VI2 D2 2fs Lm . (5.194) The dc output power is PO = VO2 ∕RL . Since PO = 𝜂PI , the dc voltage transfer function of the lossy flyback converter is √ √ √ VO √ 2D(rDS + rT1 ) 2n(RF + rT2 ) 𝜂RL RL ⎡⎢ 2 = 𝜂MV DC(lossless) = D =D + MV DC ≡ 1+ VI 2fs Lm 2fs Lm ⎢ 3fs Lm 3 fs Lm RL ⎣ 2DrL + 3fs Lm (√ 2fs Lm +1 n2 D2 RL ) V + F + n2 fs Co RL VO Hence, (√ √ D = MV DC )2 − 2 ⎤ ⎥ . ⎥ ⎦ 1 2fs Lm +1 n2 D2 RL (5.195) √ 2fs Lm = MV DC 𝜂RL 2fs Lm IO . 𝜂VO (5.196) 5.4.8 Design of Flyback Converter for DCM Design a universal dc–dc converter for laptop computers that accepts a rectified single-phase utility line voltage from 85 to 264 Vrms, VO = 15 V, IO = 0–2 A, and Vr ∕VO ≤ 1%. Solution: The maximum output power is POmax = VO IOmax = 15 × 2 = 30 W (5.197) and the minimum output power is zero. The minimum load resistance is RLmin = VO IOmax = 15 = 7.5 Ω 2 (5.198) and the maximum load resistance is infinity. The minimum and maximum values of the dc input voltage are √ √ (5.199) VImin = 2Vrms(min) = 2 × 85 = 120.21 V and VImax = √ 2Vrms(max) = √ 2 × 264 = 373.35 V. (5.200) Thus, the minimum and maximum dc voltage transfer functions are MV DC(min) = VO 15 = 0.0402 = VImax 373.35 (5.201) MV DC(max) = VO 15 = 0.125. = VImin 120.21 (5.202) and Flyback PWM DC–DC Converter 229 Assume that the duty cycle at the CCM/DCM boundary is DBmax = 0.4 and the converter efficiency is 𝜂 = 0.85. Hence, one obtains the transformer turns ratio n= 𝜂DBmax 0.85 × 0.4 = 4.533. = (1 − DBmax )MV DCmax (1 − 0.4) × 0.125 (5.203) Pick n = 5. Assume that the switching frequency is fs = 100 kHz. From (5.170), the maximum magnetizing inductance required to maintain the converter in DCM is found as Lm(max) = n2 RLmin (1 − DBmax )2 52 × 7.5 × (1 − 0.4)2 = = 337.5 𝜇H. 2fs 2 × 105 Pick Lm = 300 𝜇H. From (5.195), the minimum duty cycle occurs at VImax = 373.35 V √ √ 2fs Lm 2 × 105 × 300 × 10−6 Dmin = MV DC(min) = 0.123 = 0.0402 𝜂RLmin 0.85 × 7.5 and the maximum duty cycle occurs at VImin = 120.21 V √ √ 2fs Lm 2 × 105 × 300 × 10−6 = 0.383. = 0.125 Dmax = MV DC(max) 𝜂RLmin 0.85 × 7.5 The maximum duty cycle of the diode at any input voltage VI is √ √ 2fs Lm 2 × 105 × 300 × 10−6 = 0.5659. D1max = = n2 RLmin 52 × 7.5 (5.204) (5.205) (5.206) (5.207) At VImin = 120.21 V, Dmax + D1max = 0.383 + 0.5659 = 0.9489 < 1. (5.208) Dmin + D1max = 0.1233 + 0.5659 = 0.6889 < 1. (5.209) and at VImax = 373.35 V, Assuming the dwell-duty ratio Dw = 0.05, we get Lm(max) = RLmin (1 − Dw )2 (1 − 0.05)2 7.5 = ( ) ( )2 = 301.57 𝜇H. 2 2fs 2 × 105 0.125 MV DCmax 1 1 √ √ +n +5 𝜂 (5.210) 0.85 From (5.126) and (5.137), one obtains the maximum peak switch current ISMmax = ΔiLm(max) = Dmin VImax 0.123 × 373.35 = 5 = 1.531 A fs Lm 10 × 300 × 10−6 (5.211) and the maximum peak diode current IDMmax = nΔiLm(max) = 5 × 1.531 = 7.655 A. (5.212) Using (5.129) and (5.140), one can find the maximum value of the diode voltage VImax 373.35 + VO = + 15 = 89.67 V n 5 and the maximum value of the switch voltage VDMmax = VSMmax = VImax + nVO = 373.35 + 5 × 15 = 448.35 V. (5.213) (5.214) 230 Pulse-Width Modulated DC–DC Power Converters The maximum ripple voltage is 15 = 150 mV. 100 Assuming that the ESR of the filter capacitor is rC = 10 mΩ, the voltage drop across rC is found as Vr = Vrcpp = rC IDM(max) = 10 × 10−3 × 7.655 = 76.55 mV. (5.215) (5.216) Hence, the maximum voltage across the filter capacitance is Vcpp = Vr − Vrcpp = 150 − 76.55 = 73.45 mV. (5.217) Therefore, the minimum filter capacitance is Cmin = Dmax VO 0.383 × 15 = 5 = 104.29 𝜇F. fs RLmin Vcpp 10 × 7.5 × 0.07345 (5.218) Let C = 120 𝜇F/25 V/10 mΩ. Choose an International Rectifier IRF840 power MOSFET with rDS = 0.85 Ω, VDSS = VSM = 500 V, ISM = 8 A, Qg = 42 nC, and Co = 100 pF. Also, select an MBR10100 Schottky diode with VDM = 100 V, IDM = IF(AV) = 10 A, VF = 0.35 V at 25◦ C, VF = 0.24 V at 100◦ C, and RF = 30 mΩ. The maximum conduction loss in the MOSFET occurs at full load RLmin = 7.5 Ω and at D = Dmax = 0.383, which corresponds to the low line VI = VImin = 120.21 V. This power is given by PrDS(max) = 2rDS Dmax VO2 3fs Lm RLmin = 2 × 0.85 × 0.383 × 152 = 0.217 W. 3 × 105 × 300 × 10−6 × 7.5 (5.219) The conduction loss in the MOSFET at D = Dmin = 0.123, which corresponds to the high line VI = VImax = 373.35 V, is PrDS(min) = 2rDS Dmin VO2 3fs Lm RLmin = 2 × 0.85 × 0.123 × 152 = 0.07 W. 3 × 105 × 300 × 10−6 × 7.5 (5.220) The transistor output capacitance is Co = 100 pF. Hence, the switching loss at VImin = 120.21 V is 2 Psw(min) = fs Co VSM(min) = fs Co (VImin + nVO )2 = 105 × 100 × 10−12 × (120.21 + 5 × 15)2 = 0.381 W (5.221) and the switching loss at VImax = 373.35 V is 2 Psw(max) = fs Co VSM(max) = 105 × 100 × 10−12 × 448.352 = 2.01 W. (5.222) The power loss in the MOSFET at VImin = 120.21 V is Psw 0.381 = 0.217 + = 0.1905 + 0.072 = 0.4075 W 2 2 and the power loss in the MOSFET at VImax = 373.35 V is PFET(min) = PrDS + Psw 2.01 = 0.07 + = 0.069 + 1.005 = 1.075 W. 2 2 The conduction power loss in the diode due to RF at any input voltage VI is √ √ 2nRF VO2 2 × 5 × 0.03 × 152 2 2 PRF = = = 0.283 W 3RLmin fs Lm RLmin 3 × 7.5 105 × 300 × 10−6 × 7.5 PFET(max) = PrDS + (5.223) (5.224) (5.225) and the diode conduction loss due to VF at any input voltage VI is PVF = VF IOmax = 0.35 × 2 = 0.7 W (5.226) Flyback PWM DC–DC Converter 231 which gives the total diode conduction loss at any input voltage VI PD = PRF + PVF = 0.283 + 0.7 = 0.983 W. (5.227) Let rT1 = 1 Ω and rT2 = 0.03 Ω. Hence, one obtains the conduction loss in the primary winding at VImin = 120.21 V as PrT1(max) = 2rT1 Dmax VO2 3fs Lm RLmin = 2 × 1 × 0.383 × 152 = 0.255 W 3 × 105 × 300 × 10−6 × 7.5 (5.228) = 2 × 1 × 0.123 × 152 = 0.082 W 3 × 105 × 300 × 10−6 × 7.5 (5.229) and at VImax = 373.35 V PrT1(min) = 2rT1 Dmin VO2 3fs Lm RLmin and the conduction loss in the secondary winding at any input voltage VI √ √ 2nrT2 VO2 2 × 5 × 0.03 × 152 2 2 PrT2 = = = 0.283 W. 3RLmin fs Lm RLmin 3 × 7.5 105 × 300 × 10−6 × 7.5 (5.230) Assume that the series resistance of the magnetic core is rL = 0.5 Ω. Thus, the power loss in rL at VImin is √ ( ) 2rL Dmax VO2 2fs Lm PrL(max) = 1+ 3fs Lm RLmin n2 D2max RLmin ( ) √ 2 × 0.5 × 0.383 × 152 2 × 105 × 300 × 10−6 = 1+ = 0.316 W (5.231) 52 × 0.3832 × 7.5 3 × 105 × 300 × 10−6 × 7.5 and at VImax is ( √ ) 2fs Lm PrL(min) = 1+ 3fs Lm RLmin n2 D2min RLmin ) ( √ 2 × 0.5 × 0.123 × 152 2 × 105 × 300 × 10−6 = = 0.2296 W. 1+ 52 × 0.1232 × 7.5 3 × 105 × 300 × 10−6 × 7.5 2rL Dmin VO2 (5.232) The total power loss and the converter efficiency at VImin = 120.21 V and RLmin = 7.5 Ω are PLS = PrDS(max) + Psw(min) + PD + PrT1(max) + PrT2 + PrL(max) = 0.217 + 0.381 + 0.983 + 0.255 + 0.283 + 0.316 = 2.435 W (5.233) PO 30 = 92.49%. = PO + PLS 30 + 2.435 (5.234) and 𝜂= The total power loss and the converter efficiency at VImax and RLmin are PLS = PrDS(min) + Psw(max) + PD + PrT1(min) + PrT2 + PrL(min) = 0.07 + 2.01 + 0.983 + 0.082 + 0.283 + 0.2296 = 3.6576 W (5.235) PO 30 = 89.13%. = PO + PLS 30 + 3.6576 (5.236) and 𝜂= 232 Pulse-Width Modulated DC–DC Power Converters 95 R = 7.5 Ω L 90 RL = 15 Ω 85 η (%) 80 75 70 RL = 75 Ω 65 60 55 100 150 200 250 V (V) 300 350 400 I Figure 5.24 Efficiency 𝜂 as a function of dc input voltage VI at fixed load resistances for the flyback converter in DCM. Assuming that the rectangular gate-to-source voltage changes from 0 to VGSpp = 7 V, the gate-drive power is PG = fs Qg VGSpp = 105 × 42 × 10−9 × 7 = 29.4 mW. (5.237) The efficiency 𝜂 can be calculated from (5.192) and the duty cycle D from (5.196). Figures 5.24 through 5.29 show the efficiency 𝜂 and the duty cycle D versus the dc input voltage VI , load current IO , and load resistance RL for the flyback converter designed in the above example for DCM. 5.5 Multiple-Output Flyback Converter In many applications such as computers, power supplies are required to provide several outputs at different voltages, which can be both positive and negative, and may be required to be isolated from each other. Multiple outputs can be obtained by adding additional secondary windings to the transformer, each with its own rectifier and output low-pass filter. Figure 5.30 shows an example of a two-output flyback converter. However, only one of the outputs can be regulated with a negative feedback loop by controlling the duty cycle D of the transistor, and other outputs are not regulated. Normally, the output with the highest output power is regulated. Other outputs will follow according to the duty cycle determined by the control loop of the main output. If the input voltage VI increases, the duty cycle D is reduced for all outputs. If other outputs are required to be regulated, a linear regulator or a magamp post regulator may be added on each low-power output. Figure 5.31 shows an equivalent circuit of multiple-output flyback converter. The turns ratios of the transformer are Np n1 = (5.238) Ns1 Flyback PWM DC–DC Converter 233 0.4 0.35 0.3 D 0.25 RL = 7.5 Ω 0.2 R = 15 Ω L 0.15 0.1 RL = 75 Ω 0.05 0 100 150 200 250 V (V) 300 350 400 I Figure 5.25 Duty cycle D as a function of dc input voltage VI at fixed load resistances for the flyback converter in DCM. 95 V = 120 V I 90 V = 187 V I V = 373 V I η (%) 85 80 75 70 65 60 Figure 5.26 0 0.5 1 IO (A) 1.5 2 Efficiency 𝜂 as a function of dc load current IO at fixed load resistances for the flyback converter in DCM. 234 Pulse-Width Modulated DC–DC Power Converters 0.4 0.35 V = 120 V I 0.3 D 0.25 VI = 187 V 0.2 0.15 V = 373 V I 0.1 0.05 0 0 0.5 1 I (A) 1.5 2 O Figure 5.27 Duty cycle D as a function of dc load current IO at fixed load resistances for the flyback converter in DCM. 95 V = 120 V I 90 V = 187 V I 85 η (%) 80 75 V = 373 V I 70 65 60 55 Figure 5.28 0 10 20 30 40 RL (Ω) 50 60 70 80 Efficiency 𝜂 as a function of load resistance RL at fixed dc input voltages for the flyback converter in DCM. Flyback PWM DC–DC Converter 235 0.4 0.35 0.3 D 0.25 0.2 VI = 120 V 0.15 V = 187 V I 0.1 V = 373 V I 0.05 0 0 10 20 30 40 R (Ω) 50 60 70 80 L Figure 5.29 Duty cycle D as a function of load resistance RL at fixed dc input voltages for the flyback converter in DCM. and n2 = Np Ns2 . (5.239) The dc voltage transfer functions of the flyback converter are [20] MV DC1 = VO1 D = VI n1 (1 − D) (5.240) MV DC2 = VO2 D = VI n2 (1 − D) (5.241) and C1 RL1 + VO1 C2 RL2 + VO2 + VI Figure 5.30 Multiple-output flyback converter. 236 Pulse-Width Modulated DC–DC Power Converters D1 n1:1 is1 ip + Lm Vl + Cf 1 Ls1 VO1 RL1 – vLm Lp D2 – is1 + Cf 2 Ls2 RL2 VO2 VGS – n2:1 Figure 5.31 Equivalent circuit of multiple-output flyback converter. yielding VO1 n = 2 VO2 n1 (5.242) and VI = n1 VO1 (1 − D) n2 VO2 (1 − D) = . D D (5.243) Consider the minimum magnetizing inductance Lm(min) required for CCM operation. The boundary between CCM and DCM on the CCM side occurs at VImax , which corresponds to Dmin . At the boundary between CCM and DCM, the peak current through the magnetizing inductor is ΔiLm(max) = VImax Dmin fs Lm(min) (5.244) and the magnetic energy stored in the magnetizing inductance is WOB = V 2 D2 1 Lm(min) Δi2Lm(max) = Imax min . 2 2Lm(min) (5.245) All this energy is transferred to both output loads. Thus, the output power delivered to both outputs is POB = 2 2 VO1 VO2 V 2 D2 WOB 1 = fs WOB = fs Lm(min) Δi2Lm(max) = Imax min = PO1B + PO2B = + . T 2 2fs Lm(min) RL1(max) RL2(max) (5.246) Thus, 2 n21 VO1 (1 − Dmin )2 2fs Ln(min) = ( 2 VO1 RL1max + n1 n2 )2 2 VO1 RL2max . (5.247) Hence, the minimum magnetizing inductance required for CCM operation of the flyback converter with two outputs is L > Lm(min) = n21 (1 − Dmin )2 2fs 1 RL1max 1 ( )2 + n1 n2 . 1 RL2max (5.248) Flyback PWM DC–DC Converter 237 Similarly, 2 n21 VO2 (1 − Dmin )2 2fs Ln(min) ( = n2 n1 )2 2 VO2 + RL1max 2 VO2 (5.249) RL1max yielding the minimum magnetizing inductance required for CCM operation n22 (1 − Dmin )2 L > Lm(min) = 1 ( )2 2fs n2 n1 1 RL1max . (5.250) +R1 L2max For n1 = n2 , we get L > Lm(min) = n21 (1 − Dmin )2 RL1max RL2max . 2fs RL1max + RL2max (5.251) The minimum magnetizing inductance for the flyback converter with n outputs required for CCM operation is given by L > Lm(min) = n21 (1 − Dmin )2 2fs ( )2 1 RL1max + n1 n2 1 ( )2 1 n1 n3 + RL2max 1 RL3max +⋯+ ( )2 n1 nn . (5.252) 1 RLnmax The boundary between CCM and DCM on the DCM side occurs at VImin , which corresponds to Dmax . The maximum magnetizing inductance required for DCM operation of the flyback converter with two outputs is L < Lm(max) = n22 (1 − Dmax )2 2fs 1 ( )2 n2 n1 1 RL1min . (5.253) +R1 L2min The maximum magnetizing inductance required for DCM operation of the flyback converter with n outputs is L < Lm(max) = n21 (1 − Dmax )2 2fs 1 RL1min ( )2 + n1 n2 1 RL2min 1 ( )2 + n1 n3 1 RL3min +⋯+ ( )2 n1 nn . (5.254) 1 RLnmin The magnetizing inductance of multiple-output flyback converter for CCM and DCM is the same as that of the single-output flyback converter with the same maximum total output power. 5.6 Bidirectional Flyback Converter A derivation of a bidirectional flyback converter is shown in Figure 5.32. A unidirectional noninverting flyback converter is depicted in Figure 5.32(a). Figure 5.32(b) shows the same converter with the cathode of the diode connected to ground. If the diode in this circuit is replaced by a MOSFET, a bidirectional flyback converter is obtained as depicted in Figure 5.32(c). 5.7 Ringing in Flyback Converter The leakage inductance of transformers of all isolated dc–dc converters may lead to ringing, increased voltage stresses, and increased power loss, resulting in a significant degradation of circuit performance. The ringing is caused by parasitic oscillations between the transformer leakage inductance and the transistor output capacitance. The leakage inductance on the primary side of the transformer is given by Ll = (1 − k)Lp (5.255) 238 Pulse-Width Modulated DC–DC Power Converters n:1 C1 V1 C2 V2 C2 V2 C2 V2 (a) n:1 C1 V1 (b) n:1 C1 V1 (c) Figure 5.32 Derivation of a bidirectional flyback converter. (a) Unidirectional noninverting flyback converter. (b) Unidirectional noninverting flyback converter with the cathode of the diode connected to ground. (c) Bidirectional flyback converter. where Lp is the inductance of the primary winding and k is the coupling coefficient of the transformer primary and secondary windings. Typical values of k are in the range 0.98–0.99. For example, for Lp = 2.5 mH and k = 0.98, we obtain Ll = (1 − 0.98) × 2.5 × 10−3 = 50 𝜇H. In a single-transistor flyback converter, a voltage spike and ringing is developed at the leading edge of the switch voltage vS at each transistor turn-off due to the transformer leakage inductance Ll . A high voltage spike and ringing are superimposed on the steady-state transistor voltage VSM = VI + nVO . When the transistor is turned off, the transformer leakage inductance Ll , the transistor output capacitance Co = Coss = Cds + Cgd , and the transformer stray input capacitance Cp form a resonant circuit, as shown in Figure 5.33. The current through the leakage inductance Ll is R − pt iLl = ILl (0)e 2Ll cos 𝜔o t (5.256) the voltage across the leakage inductance is R − pt R R − pt − pt vLl = ILl (0)Zo e 2Ll sin 𝜔o t = ISM Zo e 2Ll sin 𝜔o t = VLl (pk) e 2Ll sin 𝜔o t (5.257) and the voltage across the switch is R − pt vS = VI + nVO + vLl = VI + nVO + ISM Zo e 2Ll sin 𝜔o t (5.258) Flyback PWM DC–DC Converter Rp 239 n:1 Lm C RL + VO Cp VI Ll Co Figure 5.33 Equivalent circuit of flyback converter when the transistor is OFF. where ILl (0) = ISM is the current in the leakage inductance Ll just before the switch turns off, Rp is the primary winding resistance, VLl (pk) = ISM Zo , the frequency of ringing is 𝜔o = √ 1 Ll (Co + Cp ) the characteristic impedance of the resonant circuit is √ 1 = Zo = 𝜔o Ll = 𝜔o (Co + Cp ) (5.259) Ll . Co + Cp (5.260) Hence, the peak voltage across the switch is VSM = VI + nVO + ISM Zo . (5.261) The energy stored in the leakage inductance just before the transistor turn off is WLl = 1 1 2 Ll ILl (0)2 = Ll ISM 2 2 (5.262) resulting in the power loss due to ringing Pring = WLl T = fs WLl = 1 f L I2 . 2 s l SM (5.263) Example 5.1 A flyback converter (designed for CCM) has Ll = 50 𝜇H, Co = 470 pF, Cp = 30 pF, ISMmax = 1.418 A, VSMmax = 373 V, n = 11, VO = 5 V, and fs = 100 kHz. Find the ringing frequency, the maximum switch voltage, and the power loss due to ringing. Solutions: The ringing frequency is fo = 1 1 = 1 MHz = √ √ 2𝜋 Ll (Co + Cp ) 2𝜋 50 × 10−6 (470 + 30) × 10−12 the characteristic impedance is √ Zo = (5.264) √ Ll = Co + Cp 50 × 10−6 = 316.23 Ω (470 + 30) × 10−12 (5.265) the peak value of the voltage across the leakage inductance is VLl (pk) = ISMmax Zo = 1.418 × 316.23 = 448.4 V (5.266) 240 Pulse-Width Modulated DC–DC Power Converters n:1 Rs Cs RL C + VO VI Figure 5.34 Flyback converter with dissipative RCD snubber. the maximum value of the voltage across the switch is VSMmax = VImax + nVO + Zo ISMmax = 373 + 11 × 5 + 448.4 = 876.4 V (5.267) and the power loss due to ringing is 1 1 f L I2 = × 100 × 103 × 50 × 10−6 × 1.4182 = 5.02 W. (5.268) 2 s l SMmax 2 The switch conduction loss also increased because a transistor with a much higher breakdown voltage VDSS and a much higher on-resistance rDS must be used. Pring = 5.8 Flyback Converter with Passive Dissipative Snubber One way to reduce the magnitude of ringing is to use a passive dissipative RCD snubber, as shown in Figure 5.34. A large capacitance acts as a voltage source whose average voltage is nVO . When the ringing voltage increases the diode turns on and a constant voltage is dropped across the transformer primary winding and a transistor. The maximum peak voltage of the transistor is VSMmax = VImax + nVO . (5.269) Most of the energy stored in the leakage inductance is dissipated in the snubber resistor R and the snubber diode, reducing the converter efficiency. 5.9 Flyback Converter with Zener Diode Voltage Clamp In order to reduce the magnitude of the ringing, a voltage limiter (or voltage clamp) in the form of a Zener diode in series with a diode connected back-to-back may be added across the transformer winding as shown in Figure 5.35. This is also a dissipative voltage clamp. When the transistor is turned off, the voltage across the primary winding reverses, and the diodes conduct. The voltage across the magnetizing inductance is vLm = nVO . The Zener diode behaves like a dc voltage source with its voltage Vz . The voltage across the leakage inductance after the switch is n:1 C RL + VO > 0 VI Figure 5.35 Flyback converter with a Zener diode voltage clamp across the transformer primary winding. Flyback PWM DC–DC Converter 241 turned off and the Zener diode turns on is vLl = Vz + 0.7 V. The voltage across the switch after it is turned off is given by VSM = VI + vLm + vLl = VI + nVO + Vz + 0.7 V. (5.270) The current through the leakage inductance and the diodes decreases linearly. When the diode current reaches zero, the diodes turns off, and the voltage across the switch is expressed by VSM = VI + nVO . (5.271) The Zener diode voltage clamp is used in low voltage converters, where Vz ≤ 50 V. It is not used in universal-input, off-line flyback converters. 5.10 Flyback Converter with Active Clamping Figure 5.36 shows three nearly lossless active clamp circuits. These circuits may also provide zero-voltage switching (ZVS), reducing switching losses, reducing EMI, and increasing the efficiency. The clamping circuit consists of transistor Q2 and the coupling capacitor Cc . In the converter depicted in Figure 5.36(a), the clamping circuit is connected across the primary. This circuit is called the high-end n-channel active clamp. The main transistor Q1 is driven with the duty cycle D and the clamp transistor is driven with the duty cycle 1 − D. The voltage across the clamp capacitor is VCc(H) = nVO + VLl (5.272) where VLl is the voltage across the leakage inductance, which can be up to 0.4nVO . the converter shown in Figure 5.36(b), the clamping circuit is connected across the main switch. It is called the low-end n-channel active clamp. The voltage across the clamping capacitor Cc is VCc(H) = VI + nVO + VLl . (5.273) In the converter shown in Figure 5.36(c), the clamping circuit contains a p-channel MOSFET. This circuit is called the low-end p-channel active clamp. 5.11 Two-Transistor Flyback Converter A two-switch flyback converter with two fast diodes is shown in Figure 5.37. Both transistors are on and off simultaneously. When the transistors are turned off, the two clamping diodes D2 and D3 are forced to turn on by the current of the magnetizing inductance Lm and clamp the voltage across the transistors and the primary winding to VSMmax = VImax . Therefore, steady-state voltage across each switch is reduced over that of a singleswitch flyback converter, which is VSM = VI + nVO . The peak value of the single-switch flyback converter is VSM = VI + nVO + Vpk(ring) , where Vpk(ring) is the magnitude of the voltage ringing superimposed on the steady-state 2 . The conduction loss in each transistor voltage. The conduction loss in the single-switch converter PDS1 = rDS1 Isrms 2 transistor is the two-switch converter PDS2 = rDS2 Isrms . The ratio of the conduction loss in the transistor of the single-switch flyback converter to the conduction loss in both the transistors in the two-switch flyback converter is ( ( )2.2 )2.2 PrDS1 r 1 VBD1 1 VImax + nVO + Vpk(ring) = DS1 = = 2PrDS2 2rDS2 2 VBD2 2 VImax ( ( )2.2 ) nVO + Vpk(ring) nVO 2.2 1 1 1+ 2+ = ≈ (5.274) 2 VImax 2 VImax where VBD1 is the breakdown voltage of the MOSFET in the single-switch flyback converter and VBD2 is the breakdown voltage of the MOSFETs in the two-switch flyback converter. The maximum overshoot of the second-order 242 Pulse-Width Modulated DC–DC Power Converters n:1 CC C RL + VO C RL + VO C RL + VO Q2 VI 1 D D Q1 (a) n: 1 CC VI 1 D Q1 D (b) n: 1 VI CC Q1 Q2 D 1 D (c) Figure 5.36 Flyback converter with clamp circuits to avoid ringing. (a) High-end n-channel active clamp. (b) Low-end n-channel active clamp. (c) Low-end p-channel active clamp. system causing ringing can be as high as 100%, resulting in Vpk(ring) ≈ VImax . Thus, the conduction loss in the two transistors of the two-switch flyback converter is lower than that of the single-switch flyback converter. The current of the magnetizing inductance flows through the clamping diodes D2 and D3 , and also through the rectifier diode D1 . The current of the two clamping diodes decreases gradually to zero with slope VI ∕Lm . When the current of the clamping diodes reaches zero, the diodes turn off at zero current and do not suffer from the reverse recovery problems. The converter is used in both CCm and DCM, especially at high dc input voltages VI . The dc voltage transfer function of the two-transistor flyback converter is identical to that of the single-transistor flyback converter. For CCM, the dc voltage transfer function is MV DC = VI 𝜂D . = VO n(1 − D) (5.275) Flyback PWM DC–DC Converter D3 S1 D1 + + VI C D2 Figure 5.37 243 R VO S2 Two-switch flyback converter that eliminates ringing. The advantage of the two-switch flyback converter over its single-switch counterpart is the reduced voltage stress of the switch. This voltage is well determined. In addition, there is no need for a snubber across the primary winding to dissipate the energy stored in the leakage inductance of the primary winding. The disadvantage of the two-transistor flyback converter is the floating gate driver of the high side transistor. 5.12 Summary r The flyback converter is the lowest cost regulator because it has the lowest parts count and the output filter inductor is not required. It consists of only four components. r The transformer provides dc isolations and its magnetizing inductance stores the energy and no extra inductor is required. r The flyback converter can be derived from the buck–boost converter by replacing the inductor with a transformer. r The equations for the flyback converter are similar to those of the buck–boost converter. To obtain the equations for the flyback converters from the buck–boost converter, MV DC should be replaced by nMV DC , VI reflected to the secondary side of the transformer should be replaced by VI ∕n, and the load current IO reflected to the primary side of the transformer should be replaced by IO ∕n. r The flyback converter can be used either as a step-down or a step-up converter. r It can be either inverting or noninverting converter, depending on the polarity of the transformer, the rectifier diode, and the filter capacitor. r The flyback converter may be used to build multiple-output power supplies. r The voltage and current stresses are high in the flyback converter. r The typical power range of the flyback converter is from 20 to 2000 W. r For the lossless flyback converter, the dc voltage transfer function is M V DC = D∕n(1 − D) for CCM. r For the lossy converter, the dc voltage transfer has lower values than those for the lossless converter, especially for the duty cycle D close to 1. For this reason, the maximum value of the dc voltage transfer function is limited. r The converter should not be used at D close to 1 because its efficiency is poor for D from 0.9 to 1. r The peak-to-peak value of the current through the filter capacitor is large, equal to the peak-to-peak value of the diode current IDM . r The input current is pulsating. r The corner frequency of the output filter f = 1∕(2𝜋CR ) depends on the load resistance R . o L L r It is very easy to drive the transistor in the flyback converter because the source is connected to ground. r In the flyback converter, only one-half of the B–H curve of the transformer core is utilized. Therefore, a core with an air gap and a relatively large volume is normally required to avoid saturation. 244 Pulse-Width Modulated DC–DC Power Converters r The two-switch flyback converter has a reduced voltage stress of the switch from V SMmax = VImax + nVO + Vpk(ring) and the energy stored in the leakage inductance of the primary winding is returned to the dc input voltage source, thus eliminating the need for a snubber across the primary winding. References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [3] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. [4] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [5] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood, NJ: Prentice-Hall, 2004. [6] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [7] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [8] J. G. Kassakian, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. [9] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [10] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. [11] R. Watson, F. C. Lee, and G. C. Hua, “Utilization of an active-clamp circuit to achieve soft switching in flyback converter,” IEEE Transactions on Power Electronics, vol. 11, no. 1, pp. 162–169, January 1996. [12] H. Chung, S. Y. Hui, and W. H. Wang, “An isolated ZVS/ZCS flyback converter using the leakage inductance of the coupled inductor,” IEEE Transactions on Industrial Electronics, vol. 45, no. 4, pp. 679–682, August 1998. [13] H. Chung, S. Y. Hui, and W. H. Wang, “A zero-current switching PWM flyback converter with a simple auxiliary switch,” IEEE Transactions on Power Electronics, vol. 14, no. 2, pp. 329–342, March 1999. [14] I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. [15] D. Murthy-Bellur and M. K. Kazimierczuk, “Two-switch flyback dc-dc converter in continous-conduction mode,” International Journal of Circuit Theory and Applications, vol. 39, no. 8, pp. 849–864, August 2011. [16] D. Murthy-Bellur and M. K. Kazimierczuk, “Two-switch flyback dc-dc converter in discontinous-conduction mode,” International Journal of Circuit Theory and Applications, vol. 39, no. 11, pp. 1145–1160, November 2011. [17] D. Murthy-Bellur and M. K. Kazimierczuk, “Isolated two-switch zeta converter with reduced transistor voltage stress,” IEEE Transactions on Circuits and Systems, Part II, Express Brief, vol. 58, no. 1, pp. 41–45, January 2011. [18] D. Murthy-Bellur and M. K. Kazimierczuk, “Zero-current transition two-switch flyback pulse-width modulated dc-dc converter,” IET Power Electronics, vol. 4, no. 3, pp. 288–295, 2011. [19] D. Murthy-Bellur and M. K. Kazimierczuk, “Active clamp ZVS two-switch flyback dc-dc converter,” IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 15–18, 2011, pp. 241–244. [20] N. Kondrath, A. Ayachit, and M. K. Kazimierczuk, “Minimum required magnetizing inductance for multiple-output flyback dc-dc converter in CCM,” IET Electronic Letters, vol. 51, no. 12, pp. 930–931, June 11, 2015. Review Questions 5.1 What are the roles of the transformer in the flyback PWM converter? 5.2 Is the flyback converter a step-down or a step-up converter? 5.3 What is the useful range of the duty cycle for the flyback converter? 5.4 What is the useful range of the dc voltage transfer function for the flyback converter? 5.5 Is the transformer required to store energy in the flyback converter? 5.6 Is it difficult to drive the transistor in the flyback converter? 5.7 Is the peak-to-peak value of the current through the filter capacitor large in the flyback converter? 5.8 Is the flyback converter a complicated converter? Flyback PWM DC–DC Converter 245 5.9 What is the typical range of the output power of the flyback converter? 5.10 Is the flyback converter an inverting or a noninverting converter? 5.11 Can the flyback converter be used in multiple-output power supplies? Draw an example circuit of such a converter? 5.12 Is the switch voltage stress low in the flyback converter? 5.13 Is the size of the magnetic core small in the flyback converter? 5.14 Is it useful to use a core with an air gap in the flyback converter? Problems 5.1 The dc input voltage of a flyback PWM converter operating in CCM is the US single-phase rectified voltage and the dc output voltage is VO = 800 V. Find the transformer turns ratio n. 5.2 The dc input voltage of a flyback PWM converter is the US single-phase rectified voltage, the dc output voltage is VO = 800 V, and the transformer turns ratio is n = 1/3. Find the voltage stresses of the switch and the diode. 5.3 The dc input voltage of a flyback PWM converter is the US single-phase rectified voltage, the dc output voltage is VO = 800 V, the minimum load current is IOmin = 0.2 A, the maximum input voltage VImax = 187 V, the switching frequency is fs = 50 kHz, the efficiency is 𝜂 = 0.95, and the transformer turns ratio is n = 1/3. Find the minimum magnetizing inductance of the transformer to maintain the operation in CCM. 5.4 A flyback PWM converter is supplied by the US single-phase rectified line voltage, VO = 800 V, IO = 0.2–0.5 A, the minimum input voltage VImin = 127 V, the minimum duty cycle Dmin = 0.6, n = 1/3, Lm = 2 mH, and fs = 50 kHz. Find the current stresses of the switch and the diode. 5.5 A flyback PWM converter is supplied by the US single-phase rectified line voltage, VO = 800 V, IO = 0.2–0.5 A, n = 1/3, the maximum dc input current is IImax = 3.15 A, MV DCmin = 6.229, fs = 50 kHz, and Vr ∕VO ≤ 1%. Find the filter capacitance. 5.6 Design a flyback PWM converter to meet the following specifications: VI = 270 Vdc ±10%, VO = 28 V, IO = 0.2–2 A, and Vr ∕VO ≤ 1%. Find n, Lm , C, and 𝜂. 5.7 The dc input voltage of a flyback PWM converter is the US single-phase rectified voltage, the dc output voltage is VO = 800 V, the minimum load current is IOmin = 0 A, the maximum load current is IOmax = 0.5 A, the switching frequency is fs = 50 kHz, the efficiency is 𝜂 = 0.95, and the transformer turns ratio is n = 1/3. Find the maximum magnetizing inductance of the transformer to maintain the operation in DCM. 5.8 Design a flyback converter to meet the following specifications: VI = 240 to 300 Vdc, VO = 28 V, IO = 0.2–2 A, fs = 200 kHz, Vr ∕VO ≤ 1%, rL = 2 Ω, rDS = 0.5 Ω, rT1 = 50 mΩ, rT2 = 10 mΩ, rC = 50 mΩ, VF = 0.7 V, RF = 25 mΩ, and Co = 100 pF. Find n, Dmin , Dmax , L, C, and 𝜂. 5.9 Design a flyback converter whose VI is the US rectified line voltage 92–132 Vrms, VO = 800 V, IO = 50–500 mA, Vr ∕VO ≤ 1%. Find Lm , C, rC , ISM , VSM , and n. 5.10 Design a universal power supply that accepts a single-phase line voltage from 85 to 264 Vrms at f = 50–440 Hz, VO = 5 V, IO = 0–10 A, and Vr ∕VO ≤ 1%. Assume rDS = 0.85 Ω, RF = 10 mΩ, VF = 0.3 V, rC = 2.5 mΩ, rL = 0.35 Ω, rT1 = 0.9 Ω, rT2 = 0.02 Ω, fs = 100 kHz, Co = 100 pF, and the initial efficiency 𝜂 = 80%. 5.11 Draw a circuit of a multiple-output flyback converter with VO1 = 5 V, VO2 = 12 V, and VO3 = 12 V. 6 Forward PWM DC–DC Converter 6.1 Introduction The PWM forward converter [1–18] is one of the most widely used converters. It is a single-ended isolated (i.e., transformer) converter and can be derived from the buck converter. Therefore, it belongs to the family of the buck-derived converters. A core reset circuit is required in this converter. The transformer is not required to store magnetic energy. The switch must withstand high voltage stress. The forward converter is suitable for low and medium power applications, usually from 30 to 500 W. It is used in either single output or multiple-output power supplies. This chapter presents a steady-state analysis of the PWM forward converter for both CCM and DCM. Design examples are given for both modes. 6.2 DC Analysis of PWM Forward Converter for CCM 6.2.1 Derivation of Forward PWM Converter The forward converter can be derived from the buck converter by adding the transformer and diode D1 between the switch and the diode D2 . Therefore, the forward converter is one of the buck-derived converters. Figure 6.1 shows the derivation of the forward converter. The buck converter is depicted in Figure 6.1(a). It is a transformerless converter. Its disadvantage is that the gate of the MOSFET is driven with respect to a “hot point.” In Figure 6.1(b), an inductor Lm and a diode D1 are added between the switch and the freewheeling diode D2 . Notice that the inductor Lm cannot be connected directly in parallel with the diode D2 because the average steady-state voltage across the inductor is zero, whereas the average voltage across the diode is negative. To remove this contradiction, the diode D1 is added between the inductor Lm and the diode D2 . The average voltage across the diode D2 is equal to the average voltage across the diode D1 . The switch and the diode D1 are either on or off during the same time intervals. In contrast, the diode D2 is in the opposite state to both the switch and the diode D1 for CCM. When the switch is on, the voltage across the inductor Lm is equal to VI and therefore the inductor current increases linearly. When the switch is turned off, the diode D1 also turns off, making an open circuit for the inductor Lm . The current and the energy stored in the inductor Lm at this time is nonzero. Therefore, some provision must be added to demagnetize the inductor Lm . One way is to add an extra winding coupled to the inductor Lm and a diode D3 , as shown in Figure 6.1(b). The polarity of the extra winding must be such that the voltage across Lm is negative in order to cause the current through Lm to decrease. In addition, the switch must be held off long enough to allow Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 Forward PWM DC–DC Converter S 247 L VI D2 C RL + VO C RL + VO RL + VO RL + VO (a) D1 VI L Lm D3 D2 (b) D1 n :1 VI D3 N1 N2 L D2 N3 C (c) n1:1 D3 n3:n1 D1 L D2 C VI (d) Figure 6.1 Derivation of the forward PWM converter. (a) Buck converter. (b) An inductor Lm , diode D1 , an additional winding, and diode D3 are added to the buck converter. (c) Forward converter with the MOSFET gate driven with respect to a “hot point.” (d) Forward converter with the MOSFET gate driven with respect to ground. the inductor current to decrease to zero. The energy stored in the inductor Lm at the time the switch is turned off is returned to the dc input source VI . The inductor Lm can be replaced by a transformer, resulting in the forward converter shown in Figure 6.1(c). Because the MOSFET is connected in series with the primary of the transformer, it can be shifted so that the gate is driven with respect to ground, as shown in Figure 6.1(d). The transformer core reset is obtained by adding a tertiary winding to the transformer (also called a clamp winding) in series with a diode D3 . It generally has the same number of turns as the primary in most applications and is usually bifilar wound. 248 Pulse-Width Modulated DC–DC Power Converters It clamps the voltage across the switch at twice the line voltage VI if the number of turns of the primary and the tertiary are the same. Its main function is to return energy stored in the magnetizing inductance to the input voltage source VI and therefore reset the core after each cycle of operation. The duty cycle of the switch is limited to allow the core to reset. Its maximum value is 50% if the number of turns of the primary and the tertiary are the same. There are other core reset circuits, but most of them are lossy circuits. A negative output voltage can be obtained by reversing the secondary and diodes D1 and D2 . A multiple-output converter can be obtained by adding extra secondary windings, diodes D1 and D2 , and an inductor L, and a filter capacitor C. The magnetizing inductance in the forward converter is not required to store energy. The transformer employs only one-half of the B–H curve of the magnetic core. Therefore, the core usually requires an air gap and may be bulky. The input current waveform is pulsating, but an LC input filter can be added to obtain a nonpulsating input current. The forward converter is usually suitable for applications where the power level is between 30 and 500 W. The analysis of the forward PWM converter of Figure 6.1(d) is based on the following assumptions: (1) The power MOSFET and the diode are ideal switches. (2) The transistor output capacitance and the diode capacitance, as well as lead inductances are zero, which implies zero switching losses. (3) The transformer leakage inductances and stray capacitances are neglected. (4) Passive components are linear, time invariant, and frequency independent. (5) The output impedance of the input voltage source VI is zero for both dc and ac components. 6.2.2 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch and the diode D1 are on, and the diodes D2 and D3 are off. An ideal equivalent circuit for this time interval is shown in Figure 6.2(a). The actual transformer is modeled by an ideal transformer and the magnetizing inductance Lm . The relationship among the transformer voltages and the transformer turns ratio is v1 : v2 : v3 = N1 : N2 : (−N3 ) (6.1) where N1 , N2 , and N3 are the numbers of turns of the primary, secondary, and tertiary, respectively. The voltage ratio can also be expressed as ) ( N N (6.2) v 1 : v2 : v 3 = 1 : 1 : − 3 N2 N2 from which v1 : v2 : v3 = n1 : 1 : (−n3 ) (6.3) where n1 = N1 ∕N2 and n3 = N3 ∕N2 . The power balance for the ideal transformer is i1 v1 = i2 v2 + i3 v3 , where i3 = iD3 . When the switch is on, the voltage across the primary of the ideal transformer and the magnetizing inductance Lm is diLm . (6.4) dt The boundary condition of the magnetizing inductance is iLm (0) = 0 as shown later. Hence, one obtains the current through the magnetizing inductance Lm v1 = vLm = VI = Lm iLm = t t V 1 1 vLm dt = V dt = I t. Lm ∫0 Lm ∫0 I Lm (6.5) Forward PWM DC–DC Converter i1 n3: n1 VI + vD3 Lm + v3 iS n1:1 + v1 i2 = iD1 L iL + vL + v2 vD2 + iLm 249 C RL + VO RL + VO RL + VO (a) i1 n3: n1 VI iD3 + v3 n1:1 + v2 + v1 Lm i2 L +vD1 iL + vL iD2 C iLm + vS (b) i1 n3: n1 + vD3 VI + v3 Lm n1:1 i2 + v2 + v1 L +vD1 iLm iL + vL iD2 C + vS (c) Figure 6.2 Equivalent circuits for different time intervals for the forward PWM converter operating in CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ DT + tm . (c) For DT + tm < t ≤ T. The peak value of the magnetizing current is given by ΔiLm = iLm (DT) = VI DT DVI = Lm fs Lm (6.6) whose maximum value occurs at VImax and Dmin or at VImin and Dmax Dmin VImax . fs Lm(min) (6.7) Dmin VImax fs ΔiLm(max) (6.8) ΔiLm(max) = Thus, the minimum magnetizing inductance is Lm(min) = where ΔiLm(max) is usually 5–10% of the maximum peak current of the ideal transformer primary I1max . 250 Pulse-Width Modulated DC–DC Power Converters The voltage across the secondary of the transformer is found as v1 V = I. n1 n1 (6.9) VI di − VO = L L . n1 dt (6.10) v2 = Thus, the voltage across inductance L is vL = This leads to the current through the secondary, diode D1 , and inductance L V I − VO t n1 1 t + iL (0) i2 = iD1 = iL = vL dt + iL (0) = L ∫0 L (6.11) resulting in ( iL (DT) = VI − VO n1 ) ( DT L + iL (0) = and ( ΔiL = iL (DT) − iL (0) = VI − VO n1 ) D + iL (0) fs L VI − VO n1 (6.12) ) D fs L . (6.13) The current through the primary of the transformer is V I − VO i (0) i2 n1 t+ L = i1 = n1 n1 L n1 (6.14) and the current through the switch iS = i1 + iLm = VI − VO n1 n1 L ⎡ VI − V O iL (0) VI V ⎤ i (0) n t+ + I ⎥t + L . + t=⎢ 1 ⎢ n1 L n1 Lm Lm ⎥ n1 ⎣ ⎦ (6.15) VI . n1 (6.16) The voltage across the diode D2 is vD2 = −vL − VO = − Using (6.4), one obtains the voltage across the tertiary winding ) ( ) ( ( ) ( ) N3 N3 ∕N2 n3 n3 v3 = − v1 = − v1 = − v1 = − VI N1 N1 ∕N2 n1 n1 (6.17) and the voltage across the diode D3 ( vD3 = v3 − VI = − ) n3 + 1 VI . n1 The waveforms in the forward converter for CCM are shown in Figure 6.3. (6.18) Forward PWM DC–DC Converter vGS vGS 0 0 t T DT vLm VI n3 DT T n1 Lm 0 i1 0 VO VI iLm VO t VI n3 DT iL VI Lm IO tm T t 0 iD1 0 DT T iS 0 i1 iD2 DT n1 n3 VI 1 t 0 vD1 VI iD3 T t DT T t DT T DT T VI n1 VO L VO L t T vS 0 DT t iLm 0 t T DT vL VI n1 0 n1 251 DT 0 T t t DT T DT T VI t n3 vD2 0 vD3 0 T DT T DT VI 1 n3 n1 Figure 6.3 t VI t 0 VI t n1 Waveforms in the PWM forward converter for CCM. 6.2.3 Time Interval: DT < t ≤ DT + tm Figure 6.2(b) shows an ideal equivalent circuit for the forward converter during the time interval DT < t ≤ DT + tm . During this time interval, the switch and diode D1 are off, and the diodes D2 and D3 are on. The voltage across the inductor L is vL = −VO = L diL . dt (6.19) 252 Pulse-Width Modulated DC–DC Power Converters Hence, the current through the inductor L and the diode D2 can be found as i2 = iD2 = iL = t t V V 1 vL dt + iL (DT) = − O dt + iL (DT) = − O (t − DT) + iL (DT) L ∫DT L ∫DT L (6.20) where iL (DT) is the initial condition of the inductor L at t = DT. The peak-to-peak value of the current ripple through the inductor L is ΔiL = iL (DT) − iL (T) = VO T(1 − D) VO (1 − D) = . L fs L (6.21) Referring to Figure 6.2(b), the voltage across the tertiary is v3 = V I . Hence, the voltage across the primary and the magnetizing inductance Lm is ( ) ( ) di n1 n1 v3 = − VI = Lm Lm . v1 = vLm = − n3 n3 dt (6.22) (6.23) Hence, iLm = t n V DVI 1 vLm dt + iLm (DT) = − 1 I (t − DT) + ∫ Lm DT n3 L m fs Lm n1 V I DVI (t − DT) − n3 L m fs Lm i1 = −iLm = and ( i3 = iD3 = − n1 n3 ) ( i1 = n1 n3 ) n2 V I n DV iLm = − 21 (t − DT) + 1 I . n3 fs Lm n3 L m The peak current of the diode D3 occurs at t = DT and is given by ( ) n1 DVI ID3M = iD3 (DT) = . n3 fs Lm (6.24) (6.25) (6.26) (6.27) The voltages across the secondary and the diode D1 are v V vD1 = v2 = − 3 = − I n3 n3 and the voltage across the switch is ( v S = V I − v1 = ) n1 + 1 VI . n3 (6.28) (6.29) At time t = DT + tm , the current through the magnetizing inductance iLm and the diode current iD3 reach zero, terminating this time interval. Since iLm (DT + tm ) = 0, n 3 D n3 = DT n1 fs n1 (6.30) n3 Dmax n = 3 Dmax T. n1 fs n1 (6.31) tm = from which tm(max) = For n3 = n1 , tm = DT and tm(max) = Dmax T. Forward PWM DC–DC Converter 253 The magnetizing inductance is given by Lm = 𝜇0 N12 Ac (6.32) l lg + 𝜇c r where N1 is the number of turns in the primary winding, Ac is the core cross-sectional area, lc is the core length, lg the air gap length, and 𝜇r is the core relative permeability. The maximum magnetic flux density is Bmax = 𝜇0 N1 ΔiLm l lg + 𝜇c r = 𝜇0 N1 DVI DVI < Bs ( ) = lc N 1 Ac fs fs Lm lg + 𝜇 (6.33) r where Bs is the core saturation flux density. 6.2.4 Time Interval: DT + tm < t ≤ T An equivalent circuit of the forward converter for the time interval DT + tm < t ≤ T is shown in Figure 6.2(c). During this time interval, the switch, the diode D1 , and the diode D3 are off and the diode D2 is on. The voltages across the transformer windings and the diode D2 are v1 = v2 = v3 = vLm = 0. The voltage across the switch is vS = V I (6.34) vD3 = −VI . (6.35) and the voltage across the diode D3 is The voltage across the inductor L and the current through the diode D2 and inductor L are given by (6.19) and (6.20), respectively. 6.2.5 Maximum Duty Cycle To ensure the transformer core reset, the current through the magnetizing inductance Lm must decrease to zero in every cycle for the steady-state operation. Otherwise, the current and the energy stored in the magnetizing inductance Lm at the end of each cycle would be greater than that at the end of the previous cycle. This would lead to a catastrophic failure of the converter. Therefore, the duty cycle for the forward converter has its maximum permissible value DMAX . The transformer core reset condition can be expressed as DT + tm ≤ T (6.36) tm ≤ (1 − D)T. (6.37) DMAX T + tm = T (6.38) tm = (1 − DMAX )T. (6.39) or For the worst case, this condition is or The voltage across the magnetizing inductance vLm is VI for 0 < t ≤ DT and −(n1 ∕n3 )VI for DT < t ≤ DT + tm . Using the volt-second balance, ( ) n1 VI (1 − DMAX )T. VI DMAX T = (6.40) n3 254 Pulse-Width Modulated DC–DC Power Converters Rearranging this equation yields DMAX = n1 n1 n3 +1 n 1 . +1 n = n3 3 (6.41) 1 As the ratio n3 ∕n1 increases from 0.25 to 4, DMAX decreases from 0.8 to 0.2. For n3 = n1 , DMAX = 0.5. From (6.41), n3 1 = − 1. n1 DMAX (6.42) Hence, from (6.29), the peak switch voltage becomes ( ) VI n1 + 1 VI = . VSM = n3 1 − DMAX (6.43) As n3 ∕n1 increases from 0.25 to 4, VSM increases from 1.25VI to 5VI . For n3 = n1 , VSM = 2VI . The peak switch voltage VSM increases with increasing DMAX (i.e., with increasing ratio n1 ∕n3 ) and becomes very high at DMAX close to 1. Therefore, one should avoid DMAX > 0.8. In many applications, n3 = n1 is used. 6.2.6 Device Stresses The maximum value of the peak switch voltage and current through the switch are ( ) VImax n1 + 1 VImax = VSMmax = n3 1 − DMAX (6.44) and ISMmax = I ID1Mmax Δi + ΔiLm(max) = Omax + Lmax + ΔiLm(max) . n1 n1 2n1 (6.45) The maximum value of the peak voltage across the diode D1 is VD1Mmax = VImax n3 (6.46) the maximum value of the peak voltage across the diode D2 is VD2Mmax = VImax n1 (6.47) and the peak values of the currents through the diodes D1 and D2 are ID1Mmax = ID2Mmax = IOmax + ΔiLmax . 2 The maximum value of the peak voltage across the diode D3 is ( ) n3 V + 1 VImax = Imax VD3Mmax = n1 DMAX and the peak value of the current through diode D3 is ( ) ( ) n1 n1 Dmin VImax ID3Mmax = ΔiLm(max) = . n3 n3 fs Lm As n3 ∕n1 increases from 0.25 to 4, VD3M increases from 1.25VI to 5VI . For n3 = n1 , VD3M = 2VI . (6.48) (6.49) (6.50) Forward PWM DC–DC Converter 255 6.2.7 DC Voltage Transfer Function for CCM From Figure 6.3, the voltage across the inductor L is vL = VI ∕n1 − VO for 0 < t ≤ DT and vL = −VO for DT < t ≤ T. Applying the volt-second balance, ( ) VI − VO DT = VO (1 − D)T (6.51) n1 from which the dc voltage transfer function of the lossless converter is obtained MV DC ≡ VO I D = I = VI IO n1 for D ≤ DMAX . (6.52) The output voltage VO is independent of the load resistance RL . It depends only on the dc input voltage VI . In most practical situations, VO = DVI ∕n1 is constant. If VI is increased, D should be decreased by a control circuit to keep VO constant, and vice versa. The dc current transfer function is given by IO n = 1 II D MI DC ≡ for D ≤ DMAX . (6.53) From (6.44), (6.45), and (6.52), the switch and the diode utilization in the forward converter is characterized by the output-power capability PO V I = O O = D. VSM ISM VSM ISM cp ≡ (6.54) As D is increased from 0 to 1, so does cp . 6.2.8 Boundary Between CCM and DCM Figure 6.4 shows the inductor current waveform iL at the boundary between CCM and DCM. The inductor current waveform is ( ) VI − VO n1 t for 0 < t < DT (6.55) iL = L yielding ( ( ) ) VI VI − V − V DT D O O n1 n1 = . (6.56) ΔiL = L fs L Taking into account the converter efficiency 𝜂, we get MV DC = iL VImax n1 L iLmax VO 𝜂D = VI n1 VO VImin n1 L (6.57) VO VO L IOB 0 Figure 6.4 DminT DmaxT T t Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax . 256 Pulse-Width Modulated DC–DC Power Converters from which VI = n1 V O 𝜂D ( VO ΔiL = (6.58) ) 1 −D 𝜂 (6.59) fs L and ( VO ΔiLmax = 1 − Dmin 𝜂 fs Lmin ) . The dc output current at the boundary between CCM and DCM is ( ) 1 − D V O min VO Δi 𝜂 = . IOB = Lmax = 2 2fs Lmin RLmax (6.60) (6.61) The load resistance at the CCM/DCM boundary is RLB = VO 2f L = 1 s IOB −D for D ≤ DMAX . (6.62) 𝜂 Hence, the minimum value of the inductance L is found to be ( ) ( ) VO 1𝜂 − Dmin RLmax 1𝜂 − Dmin = Lmin = 2fs IOB 2fs (6.63) where Dmin = n1 MV DCmin ∕𝜂 = n1 VO ∕(𝜂VImax ). Equation (6.63) is the same as that for the buck converter. Figures 6.5 and 6.6 show the normalized load current IOB ∕(VO ∕2fs L) = 1 − D and load resistance RLB ∕(2fs L) = 1∕(1 − D) at the boundary between CCM and DCM as functions of the duty cycle D for DMAX = 0.5 and 𝜂 = 1, respectively. 6.2.9 Ripple Voltage in Forward Converter for CCM The ripple voltage for the forward converter can be found in the same way as for the buck converter. The peak-topeak ripple on the output voltage is independent of the voltage across the filter capacitance and is determined only by the ripple voltage across the ESR if the following condition is satisfied } { Dmax 1 − Dmin C ≥ Cmin = max . (6.64) , 2fs rC 2fs rC In the worst case, Dmin = 0. Thus, the above condition is satisfied at any value of D if C ≥ Cmin = 1 . 2rC fs (6.65) If condition (6.64) is satisfied, the peak-to-peak ripple voltage of the forward converter is Vr = rC ΔiLmax = rC VO (1 − Dmin ) . fs L (6.66) If condition (6.64) is not met, the voltages across the filter capacitance and the ESR contribute to the total output voltage ripple. The maximum increase in the charge stored in the filter capacitor is ΔQ = Δi 1 T ΔiLmax = Lmax . 22 2 8fs (6.67) Forward PWM DC–DC Converter 257 1 0.95 0.9 0.85 IOB/(V O/2fsL) CCM 0.8 0.75 0.7 DCM 0.65 0.6 0.55 0.5 0 0.1 0.2 D 0.3 0.4 0.5 Figure 6.5 Normalized load current IOB ∕(VO ∕2fs L) at the boundary between CCM and DCM as a function of duty cycle D for the forward converter at DMAX = 0.5 and 𝜂 = 1. 2 1.9 1.8 1.7 RLB/(2fsL) DCM 1.6 1.5 1.4 CCM 1.3 1.2 1.1 1 0 0.1 0.2 D 0.3 0.4 0.5 Figure 6.6 Normalized load Resistance RLB ∕(2fs L) at the boundary between CCM and DCM as a function of duty cycle D for the forward converter at DMAX = 0.5 and 𝜂 = 1. 258 Pulse-Width Modulated DC–DC Power Converters iD1 n1:1 rT 2 iL RF VF iD2 VI L rL RF VF iC IO C RL rC + VO rT1 iS rDS Figure 6.7 Equivalent circuit of the forward converter with parasitic resistances to determine component losses (the branch with diode D3 is neglected). Using (6.60) and (6.67), the peak-to-peak ripple voltage across the filter capacitance C is VCpp = V (1 − D ) (1 − Dmin )𝜋 2 VO fo2 ΔQ ΔiLmax = = O 2 min = C 8fs C 8fs LC 2fs2 (6.68) (1 − Dmin )VO ΔiLmax = . 8fs VCpp 8fs2 LVCpp (6.69) √ where fo = 1∕(2𝜋 LC) is the corner frequency of the output low-pass filter. The minimum capacitance is Cmin = The peak-to-peak ripple voltage across the ESR is Vrcpp = rC ΔiLmax = rC VO (1 − Dmin ) . fs L (6.70) The total ripple of the output voltage is approximately given by Vr ≈ VCpp + Vrcpp = VO (1 − Dmin ) rC VO (1 − Dmin ) . + fs L 8fs2 LC (6.71) 6.2.10 Power Losses and Efficiency of Forward Converter for CCM Figure 6.7 depicts an equivalent circuit of the forward converter with parasitic resistances, rDS is the MOSFET on-resistance, rT1 is the winding resistance of the primary, rT2 is the winding resistance of the secondary, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. Neglecting the ripple of the inductor current, the switch current can be approximated by {I O , for 0 < t ≤ DT n1 iS = (6.72) 0, for DT < t ≤ T which results in its rms value √ ISrms = 1 T ∫0 T √ √ √ √ 1 DT IO2 IO D √ 2 iS dt = dt = T ∫0 n21 n1 (6.73) and the conduction loss in the power MOSFET 2 PrDS = rDS ISrms = rDS DIO2 n21 = DrDS n21 RL PO . (6.74) Forward PWM DC–DC Converter 259 Assuming that the transistor output capacitance Co is linear, the switching loss is Psw = fs Co VI2 = n21 fs Co RL fs Co RL PO = = PO . D2 MV2 DC MV2 DC fs Co VO2 (6.75) Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power) ) ( DrDS IO2 Psw DrDS fs Co RL 1 2 = PO . + fs CVI = + PFET = PrDS + 2 n1 2 n21 RL 2MV2 DC (6.76) The conduction loss in the winding of the primary is 2 PrT1 = rT1 ISrms = rT1 DIO2 n21 DrT1 = n21 RL PO . (6.77) Let us assume that the diodes D1 and D2 are identical. The current through the diode D1 and the secondary winding of the transformer can be approximated by { IO , for 0 < t ≤ DT (6.78) iD1 = 0, for DT < t ≤ T producing its rms value √ ID1rms = T 1 i2 dt = T ∫0 D1 √ 1 T ∫0 √ IO2 dt = IO D (6.79) DRF P . RL O (6.80) IO dt = DIO (6.81) DT and the power losses in RF 2 PRF1 = RF ID1rms = DRF IO2 = The average value of the current through the diode D1 is T ID1 = 1 1 i dt = T ∫0 D1 T ∫0 DT which gives the power loss associated with the voltage VF of diode D1 PV F1 = VF ID1 = VF IO D = DVF P . VO O Thus, the total conduction loss in diode D1 is given by ( PD1 = PV F1 + PRF1 = VF IO D + RF IO2 D = PO D (6.82) VF RF + VO RL ) . (6.83) The power loss in rT2 is 2 PrT2 = rT2 ID1rms = DrT2 IO2 = DrT2 P . RL O The power loss in both the primary and secondary winding is ) ( rT1 D + rT2 PO . PrT = PrT1 + PrT2 = 2 R n1 L (6.84) (6.85) 260 Pulse-Width Modulated DC–DC Power Converters The current of diode D2 can be approximated by { 0, for iD2 = IO , for yielding its rms value √ T √ 1 i2 dt = T ∫0 D1 ID2rms = 0 < t ≤ DT DT < t ≤ T (6.86) √ 1 IO2 dt = IO 1 − D T ∫DT (6.87) T and the power loss in RF 2 PRF2 = RF ID2rms = (1 − D)RF IO2 = (1 − D)RF PO . RL (6.88) The average value of the current through the diode D2 is found as T ID2 = T 1 1 i dt = I dt = (1 − D)IO T ∫0 D2 T ∫DT O (6.89) from which the power loss associated with the voltage VF of diode D2 is obtained as PV F2 = VF ID2 = VF IO (1 − D) = (1 − D)VF PO . VO Thus, the overall conduction loss in diode D2 is (6.90) ( PD2 = PV F2 + PRF2 = VF IO (1 − D) + RF IO2 (1 − D) = PO (1 − D) VF RF + VO RL ) . (6.91) The power losses in the diode D3 and the tertiary winding as well as the power transferred back from the magnetizing inductance to the input voltage source VI are neglected. The inductor current is iL ≈ IO (6.92) ILrms = IO (6.93) leading to its rms value and the inductor conduction loss 2 = rL IO2 = PrL = rL ILrms rL P . RL O (6.94) The current through the filter capacitor can be expressed as ⎧ ΔiL t ΔiL for ⎪ DT − 2 , iC = ⎨ Δi (t−DT) Δi L L ⎪ − (1−D)T + 2 , for ⎩ 0 < t ≤ DT DT < t ≤ T. Using (6.21) and (6.95) the rms current through the filter capacitor is found to be √ T VO (1 − D) Δi 1 ICrms = i2 dt = √ L = √ T ∫0 C 12 12f L (6.95) (6.96) s and the power loss in the filter capacitor is 2 = PrC = rC ICrms rC VO2 (1 − D)2 rC (ΔiL )2 r R (1 − D)2 = = C L 2 2 PO . 2 2 12 12fs L 12fs L (6.97) Forward PWM DC–DC Converter 261 Neglecting the power loss in the transformer core reset circuit, the overall power loss is given by D(rDS + rT1 )IO2 PLS = PrDS + Psw + PD1 + PD2 + PrT1 + PrT2 + PrL + PrC = + rL IO2 + rC Δi2L 12 [ = PO D(rDS + rT1 ) n21 RL n21 + fs Co VI2 + VF IO + RF IO2 + DrT2 IO2 r + RF + DrT2 VF fs Co RL rC RL (1 − D)2 + L + + 2 + RL VO 12fs2 L2 MV DC ] . (6.98) Thus, the converter efficiency is 𝜂= PO 1 1 = = . PLS D(rDS +rT1 ) fC R r R (1−D)2 VF rL +RF +DrT2 PO + PLS 1+ 1+ + + + s o L + C L PO n21 RL VO MV2 DC RL (6.99) 12fs2 L2 6.2.11 DC Voltage Transfer Function of Lossy Converter for CCM The dc component of the input current is II = T T IO DI 1 1 iS dt = dt = O T ∫0 T ∫0 n1 n1 (6.100) yielding the dc current transfer function of the forward converter MI DC ≡ IO n = 1. II D (6.101) This transfer function is the same for both lossless and lossy converters. The converter efficiency can be expressed as 𝜂= PO V I n M = O O = MV DC MI DC = 1 V DC PI VI II D (6.102) from which the dc voltage transfer function of the lossy forward converter is MV DC = 𝜂 𝜂D D = = [ ]. D(rDS +rT1 ) fC R r R (1−D)2 VF RF +rL +DrT2 MI DC n1 n 1+ + + + s o L + C L 1 n21 RL VO MV2 DC RL (6.103) 12fs2 L2 From (6.103), the on-duty cycle is D= n1 MV DC . 𝜂 (6.104) The duty cycle D is greater for the lossy converter than that for the lossless converter at a given dc voltage transfer function. Substituting (6.104) into (6.99), one obtains the efficiency for the forward converter in CCM 𝜂= where ( N𝜂 = 1 − n1 MV DC [ − rDS + rT1 RL rC n21 MV2 DC 3fs2 L2 n21 RL ( r R r + T2 − C2 L2 RL 6fs L ) N𝜂 (6.105) D𝜂 {[ + ( n1 MV DC r R V r + RF fs Co RL 1+ F + L + 2 + C 2 L2 VO RL 12f L MV DC s rDS + rT1 n21 RL r R r + T2 − C2 L2 RL 6fs L ) ]2 −1 ]} 12 (6.106) 262 and Pulse-Width Modulated DC–DC Power Converters ( r R V r + RF fs Co RL D𝜂 = 2 1 + F + L + 2 + C 2 L2 VO RL 12fs L MV DC ) . (6.107) 6.2.12 Design of Forward Converter for CCM Design a PWM forward converter operating in CCM to meet the following specifications: VO = 5 V, IOmin = 2 A, IOmax = 20 A, Vr ∕VO ≤ 1%, and the input voltage is the US single-phase utility line rectified voltage. Solution: The minimum, nominal, and maximum values of the input voltage are √ √ VImin = 2 × Vrms(min) = 2 × 90 = 127 V VInom = and VImax = √ √ 2 × Vrms(nom) = 2 × Vrms(max) = √ 2 × 110 = 156 V √ 2 × 132 = 187 V. (6.108) (6.109) (6.110) The minimum, nominal, and maximum values of the dc voltage transfer function are MV DCmin = VO 1 5 = 0.02674 = = VImax 187 37.4 (6.111) MV DCnom = VO 1 5 = 0.03205 = = VInom 156 31.2 (6.112) MV DCmax = VO 1 5 = 0.03937 = . = VImin 127 25.4 (6.113) and The maximum and minimum values of the dc output power are POmax = VO IOmax = 5 × 20 = 100 W (6.114) POmin = VO IOmin = 5 × 2 = 10 W. (6.115) and The minimum and maximum values of the load resistance are RLmin = VO 5 = 0.25 Ω 20 (6.116) VO 5 = = 2.5 Ω. IOmin 2 (6.117) IOmax = and RLmax = Let us assume the switching frequency fs = 100 kHz, the converter efficiency 𝜂 = 80%, and Dmax ≈ 0.4. The transformer turns ratio is n1 = 𝜂Dmax 0.8 × 0.4 = 8.128. = MV DCmax 0.03937 (6.118) Forward PWM DC–DC Converter 263 Pick n1 = n3 = 8. The minimum, nominal, and maximum values of the duty cycle are Dmin = n1 MV DCmin 8 × 0.02674 = = 0.2674 𝜂 0.8 (6.119) Dnom = n1 MV DCnom 8 × 0.03205 = = 0.3205 𝜂 0.8 (6.120) Dmax = n1 MV DCmax 8 × 0.03937 = = 0.3937. 𝜂 0.8 (6.121) and Hence, tm(max) ∕T = Dmax = 0.3937. The maximum permissible duty cycle is 1 1 = 0.5. = 1 + 1 +1 n (6.122) RLmax (1 − Dmin ) 2.5 × (1 − 0.2674) = = 9.1575 μH. 2fs 2 × 105 (6.123) DMAX = n3 1 Thus, Dmax < DMAX . The minimum inductance is Lmin = Let L = 20 μH. The maximum peak-to-peak value of the inductor ripple current is ΔiLmax = VO (1 − Dmin ) 5 × (1 − 0.2674) = 5 = 1.832 A. fs L 10 × 20 × 10−6 (6.124) Vr = 0.01VO = 0.01 × 5 = 50 mV. (6.125) The ripple voltage is The maximum ESR of the filter capacitor is rCmax = Vr 50 = 27.29 mΩ. = ΔiLmax 1.832 (6.126) Let rC = 25 mΩ. Thus, the filter capacitance is } { } { 1 − Dmin Dmax 1 − Dmin 1 − 0.2674 0.3937 1 − 0.2674 = max = , , = Cmin = max = 146.52 μF. 2fs rC 2fs rC 2fs rC 2fs rC 2fs rC 2 × 105 × 0.025 (6.127) Pick C = 200 μF/16 V/25 mΩ. The corner frequency of the low-pass output filter is fo = 1 1 = 2.516 kHz. = √ √ −6 2𝜋 LC 2𝜋 20 × 10 × 200 × 10−6 (6.128) Hence, fs ∕fo = 100∕2.516 = 39.75. The voltage stresses of the rectifier diodes are VD1Mmax = VImax 187 = 23.375 V = n3 8 (6.129) VD2Mmax = VImax 187 = 23.375 V = n1 8 (6.130) 264 Pulse-Width Modulated DC–DC Power Converters and the current stresses of these diodes are ID1Mmax = ID2Mmax = IOmax + ΔiLmax 1.832 = 20 + = 20.916 A. 2 2 (6.131) The maximum peak current through the primary of the ideal transformer is I1max = ID1Mmax 20.916 = 2.615 A. = n1 8 (6.132) Assume that the maximum peak current through the magnetizing inductance is less than 10% of the maximum peak current through the primary of the ideal transformer. Thus, ΔiLm(max) = 0.1I1max = 0.1 × 2.615 = 0.262 A. (6.133) The minimum magnetizing inductance is then Lm(min) = Pick Lm = 2 mH. The stresses of the diode D3 are Dmin VImax 0.2674 × 187 = 1.9 mH. = fs ΔiLm(max) 100 × 103 × 0.262 ( VD3Mmax = ) n3 + 1 VImax = 2VImax = 2 × 187 = 374 V n1 and ( ID3Mmax = n1 n3 (6.134) (6.135) ) ΔiLm(max) = 0.262 A. The voltage and current stresses of the switch are ( ) n1 + 1 VImax = 2VImax = 2 × 187 = 374 V VSMmax = n3 (6.136) (6.137) and ISMmax = I1max + ΔiLm(max) = 2.615 + 0.262 = 2.877 A. (6.138) An International Rectifier IRF740 power MOSFET is selected, which has VDSS = 400 V, ISM = 10 A, rDS = 0.55 Ω, Qg(typ) = 41 nC, Qgmax = 60 nC, and Co = 100 pF. Two MBR2540 Schottky barrier diodes are chosen, which has IDM = 25 A, VDM = 40 V, VF = 0.3 V, and RF = 16 mΩ. A fast recovery MR826 diode is selected with VDM = 600 V and IDM(AV) = 5 A. We will calculate power losses for POmax = 100 W and VImin = 127 V. The conduction power loss in the MOSFET is 2 rDS Dmax IOmax 0.55 × 0.3937 × 202 = 1.353 W 82 (6.139) 2 = 105 × 100 × 10−12 × 1272 = 0.161 W. Psw = fs Co VImin (6.140) PrDS = n21 = the switching loss is Assuming rT1 = 50 mΩ, PrT1 = 2 rT1 Dmax IOmax n21 = 0.05 × 0.3937 × 202 = 0.123 W. 82 (6.141) Forward PWM DC–DC Converter 265 The power loss due to RF in diode D1 is 2 PRF1 = Dmax RF IOmax = 0.3937 × 0.016 × 202 = 2.52 W (6.142) the power loss due to VF in diode D1 is PV F1 = VF IOmax Dmax = 0.3 × 20 × 0.3937 = 2.362 W (6.143) resulting in the conduction loss in diode D1 PD1 = PRF1 + PV F1 = 2.52 + 2.362 = 4.882 W. (6.144) 2 PrT2 = Dmax rT2 IOmax = 0.3937 × 0.01 × 202 = 1.575 W. (6.145) Assuming rT2 = 10 mΩ, Hence, the power loss in both primary and secondary windings is PrT = PrT1 + PrT2 = 0.123 + 1.575 = 1.698 W. (6.146) The power loss due to RF in diode D2 is 2 = (1 − 0.3937) × 0.016 × 202 = 3.88 W PRF2 = (1 − Dmax )RF IOmax (6.147) the power loss due to VF in diode D2 is PV F2 = (1 − Dmax )VF IOmax = (1 − 0.3937) × 0.3 × 20 = 3.64 W (6.148) the conduction loss in diode D2 is PD2 = PRF2 + PV F2 = 3.88 + 3.64 = 7.52 W. (6.149) Assuming that the dc ESR of the inductor is rL = 15 mΩ, one obtains the power loss in the inductor ESR 2 = 0.015 × 202 = 6 W PrL = rL IOmax (6.150) the power loss in the capacitor ESR PrC = rC (ΔiLmax )2 0.025 × 1.8322 = = 7 mW 12 12 (6.151) the total power loss PLS = PrDS + Psw + PrT1 + PrT2 + PD1 + PD2 + PrL + PrC = 1.353 + 0.161 + 0.123 + 1.575 + 4.882 + 7.52 + 6 + 0.007 = 21.621 W (6.152) and the efficiency of the converter 𝜂= PO 100 = 82.22%. = PO + PLS 100 + 21.621 (6.153) If the magnitude of the gate-to-source voltage is VGSm = 7 V, then the gate-drive power is PG = fs Qgmax VGSm = 105 × 60 × 10−9 × 7 = 42 mW. (6.154) The efficiency 𝜂 can be calculated from (6.105) through (6.107). Once the efficiency is known, the duty cycle D can be computed from (6.104). Figures 6.8 through 6.13 show the characteristics of the designed forward converter. It can be seen that the efficiency 𝜂 decreases as IO increases (or RL decreases). The minimum efficiency 𝜂min occurs at IOmax . The duty cycle D increases as VI decreases and IO increases (or RL decreases). The plots are similar to those of the buck converter. 266 Pulse-Width Modulated DC–DC Power Converters 92 RL = 2.5 Ω 91 90 89 R = 0.5 Ω L η (%) 88 87 86 85 84 RL = 0.25 Ω 83 82 120 Figure 6.8 in CCM. 130 140 150 VI (V) 160 170 180 190 Efficiency 𝜂 as a function of the dc input voltage VI at RL = 0.25 Ω, 0.5 Ω, and 2.5 Ω for the forward converter 0.44 0.42 R = 0.5 Ω 0.4 L R = 0.25 Ω L 0.38 D 0.36 0.34 RL = 2.5 Ω 0.32 0.3 0.28 0.26 120 Figure 6.9 in CCM. 130 140 150 VI (V) 160 170 180 190 Duty cycle D as a function of the dc input voltage VI for the forward converter at fixed load resistances RL Forward PWM DC–DC Converter 267 92 91 90 89 η (%) 88 87 86 85 V I = 187 V V I = 127 V 84 83 V = 156 V 82 I 2 4 6 8 10 12 IO (A) 14 16 18 20 Figure 6.10 Efficiency 𝜂 as a function of the dc load current IO at VI = 127 V, 156 V, and 187 V for the forward converter in CCM. 0.44 V = 127 V I 0.42 0.4 0.38 D 0.36 V = 156 V I 0.34 0.32 0.3 V = 187 V I 0.28 0.26 2 4 6 8 10 12 IO (A) 14 16 18 20 Figure 6.11 Duty cycle D as a function of the dc load current IO at VI = 127 V, 156 V, and 187 V for the forward converter in CCM. 268 Pulse-Width Modulated DC–DC Power Converters 92 V I = 127 V V = 156 V I 91 V = 187 V I 90 89 η (%) 88 87 86 85 84 83 82 0 0.5 1 RL (Ω) 1.5 2 2.5 Figure 6.12 Efficiency 𝜂 as a function of the load resistance RL at VI = 127 V, 156 V, and 187 V for the forward converter in CCM. 0.44 0.42 0.4 V = 127 V I 0.38 D 0.36 0.34 V = 156 V I 0.32 0.3 0.28 V = 187 V I 0.26 0 0.5 1 RL (Ω) 1.5 2 2.5 Figure 6.13 Duty cycle D as a function of the load resistance RL at VI = 127 V, 156 V, and 187 V for the forward converter in CCM. Forward PWM DC–DC Converter 269 6.3 DC Analysis of PWM Forward Converter for DCM Figure 6.14 shows equivalent circuits for the PWM forward converter operating in DCM. Idealized current and voltage waveforms are depicted in Figure 6.15. At time t = 0 when the switch is turned on, the inductor current is zero. For the time interval 0 < t ≤ DT, the switch and the diode D1 are on, and the diodes D2 and D3 are off as shown in Figure 6.14(a). The voltage across the primary is VI and across the secondary is VI ∕n1 . The voltage across the inductor is VI ∕n1 − VO , causing the inductor current to increase linearly from zero. At time t = DT, the switch is turned off, turning the diode D1 off and the diodes D2 and D3 on. The equivalent circuit is shown in Figure 6.14(b) for time interval DT < t ≤ DT + tm . The voltage across the switch is VI . The voltage across the inductor is −VO , causing the inductor current to decrease linearly. The voltage across the magnetizing inductance is vLm = −(n1 ∕n3 )VI . Therefore, the current through the magnetizing inductance and the diode D3 decreases linearly. At time t = DT + tm , these two currents reach zero and the diode D3 turns off. The equivalent circuit for the time interval DT + tm < t ≤ (D + D1 )T is shown in Figure 6.14(c). The voltage across the inductance L is −VO and therefore the current through this inductance and the diode D2 decreases linearly. At time t = (D + D1 )T, the current through the inductor L and the diode D2 reaches zero and the diode D3 turns off. The inductor current remains zero until the switch is turned on at time t = T. Figure 6.14(d) displays the equivalent circuit for the time interval (D + D1 )T < t ≤ T. The voltage across the inductor is zero because its current is zero. At time t = T, the switch is turned on and the inductor current commences to increase from zero. 6.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch and the diode D1 are on, and the diodes D2 and D3 are off. The equivalent circuit is shown in Figure 6.14(a). The switch voltage vS and the diode currents iD2 and iD3 are zero. The voltage across the primary and the magnetizing inductance Lm is v1 = vLm = VI = Lm diLm , dt iLm (0) = 0 (6.155) resulting in the current through the magnetizing inductance iLm = t t V 1 1 vLm dt + 0 = V dt = I t Lm ∫0 Lm ∫0 I Lm (6.156) and the peak current of the magnetizing inductance VI DT DVI = . Lm fs Lm (6.157) N3 ∕N2 n n v1 = − 3 v1 = − 3 V I N1 ∕N2 n1 n1 (6.158) ) n3 +1 . n1 (6.159) ΔiLm = iLm (DT) = The voltage across the tertiary winding is v3 = − which gives the voltage across the diode D3 ( vD3 = v3 − VI = −VI Since the voltage vD3 is negative, the diode D3 is off. The voltage across the secondary is v2 = v1 V = I n1 n1 (6.160) 270 Pulse-Width Modulated DC–DC Power Converters i1 n3: n1 + vD3 VI n1:1 + Lm v1 i2 = iD1 iL + vL + v2 vD2 + iLm + v3 L C RL + VO RL + VO RL + VO RL + VO iS (a) i1 n3: n1 VI iD3 + v3 n1:1 i2 + v2 + Lm v1 L iL + vD1 + vL iD2 C iLm + vS (b) i1 n3: n1 + vD3 VI n1:1 i2 + + vD1 v2 + Lm v1 L iL + vL iD2 C iLm + v3 + vS (c) i1 n3: n1 + vD3 VI + v3 n1:1 i2 + + vD1 v2 + Lm v1 iLm L vD2 + iL + vL C + vS (d) Figure 6.14 Equivalent circuits for different time intervals for the forward PWM converter operating in DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ DT + tm . (c) For DT + tm < t ≤ (D + D1 )T. (d) For (D + D1 )T < t ≤ T. Forward PWM DC–DC Converter vGS vGS 0 0 t T DT vLm VI T DT 0 t VO VI n1 Lm n3 VI Lm iL 0 tm DT DT VI n1 VO L T t VO L IO t T t T D1T VO VI n3 iLm DT vL VI n1 0 n1 271 0 i1 D1T DT T t T t T t iD1 0 T DT 0 iS 0 t iD2 iLm i1 T DT vS n1 n3 VI 1 t 0 vD1 VI 0 iD3 0 vD3 0 0 T DT DT DT T n3 n1 Figure 6.15 t tm T DT VO t n3 vD2 0 t VI DT VI t T VI 1 DT DT VI n1 VO T t Waveforms in the PWM forward converter for DCM. and the voltage across the diode D2 is vD2 = −v2 = − VI n1 (6.161) which maintains diode D2 in the off state. The voltage across the inductor L is v L = v2 − V O = VI di − VO = L L , n1 dt iL (0) = 0 (6.162) 272 Pulse-Width Modulated DC–DC Power Converters and the inductor and switch current is t 1 1 v dt = i2 = iD1 = iL = L ∫0 L L ∫0 resulting in the peak inductor current ( ΔiL = iL (DT) = VI − VO n1 t( VI ) − VO VI n t − VO dt = 1 n1 L ) ( DT = L VI − VO n1 fs L (6.163) ) D . (6.164) The current through the primary is V i1 = I − VO i2 n t = 1 n1 n1 L (6.165) yielding the current through the switch iS = i1 + iLm = VI − VO n1 n1 L ⎡ VI − V O VI V ⎤ n t+ + I ⎥ t. t=⎢ 1 ⎢ n1 L Lm Lm ⎥ ⎣ ⎦ (6.166) 6.3.2 Time Interval: DT < t ≤ DT + tm The equivalent circuit for this time interval is shown in Figure 6.14(b). The switch and the diode D1 are off, and the diodes D2 and D3 are on. The voltage across the inductor L is vL = −VO = L diL dt (6.167) resulting in the current through the inductor L and diode D2 t t 1 1 v dt + iL (DT) = (−VO )dt + iL (DT) L ∫DT L L ∫DT ( ) VI − VO DT VO VO n1 . = − (t − DT) + iL (DT) = − (t − DT) + L L L iD2 = iL = (6.168) The peak inductor current is found as DT ΔiL = DT V D T 1 1 v dt = (−VO )dt = O 1 . L ∫(D+D1 )T L L ∫(D+D1 )T L (6.169) The voltage across the tertiary winding is v3 = V I (6.170) which gives the voltage across primary and the magnetizing inductance di n n v1 = vLm = − 1 v3 = − 1 VI = Lm Lm n3 n3 dt (6.171) the current through the magnetizing inductance iLm = t n V n V DVI 1 v dt + iLm (DT) = − 1 I (t − DT) + iLm (DT) = − 1 I (t − DT) + Lm ∫DT Lm n3 L m n3 L m fs Lm (6.172) Forward PWM DC–DC Converter 273 the current through the primary i1 = −iLm = n1 V I (t − DT) − iLm (DT) n3 L m (6.173) and the current through the diode D3 n2 V I n n i3 = iD3 = − 1 i1 = − 21 (t − DT) + 1 iLm (DT). n3 n3 n3 L m (6.174) The voltage across the secondary is v V v2 = − 3 = − I n3 n3 (6.175) VI n3 (6.176) and the voltage across the diode D1 is vD1 = v2 = − and the voltage across the switch is ) ( ( ) n n1 +1 . v S = V I − v1 = V I − − 1 V I = V I n2 n3 (6.177) This time interval ends when the current through the magnetizing inductance and therefore through the diode D3 reaches zero. 6.3.3 Time Interval: DT + tm < t ≤ (D + D1 )T It is assumed that tm < D1 T. During this time interval, the switch and the diodes D1 and D3 are off, and the diode D2 is on. The equivalent circuit is shown in Figure 6.14(c). The voltages across the transformer windings and diodes D1 and D2 are vLm = v1 = v2 = v3 = vD1 = vD2 = 0, the currents are iLm = i1 = i2 = iD1 = i3 = iD3 = 0, the voltage across the diode D3 is vD3 = −VI (6.178) vS = V I . (6.179) and the voltage across the switch is The inductor voltage and current waveforms are given by (6.167) and (6.168). This time interval is terminated when the current through the diode D2 reaches zero. 6.3.4 Time Interval: (D + D1 )T < t ≤ T During this time interval, the switch and all the diodes are off. The equivalent circuit is shown in Figure 6.14(d). The inductor current iL , the inductor voltage vL , the switch current iS , and the diode currents iD1 , iD2 , and iD3 are zero. The voltage across the switch is vS = V I (6.180) vD1 = vD2 = −VO (6.181) vD3 = −VI . (6.182) the voltages across the diodes D1 and D2 are and the voltage across the diode D3 is This time interval ends when the switch is turned on by the driver. 274 Pulse-Width Modulated DC–DC Power Converters 6.3.5 DC Voltage Transfer Function for DCM Referring to the inductor voltage waveform in Figure 6.15 and using the volt-second balance, ( ) VI − VO DT = VO D1 T n1 (6.183) which gives the dc-to-dc voltage transfer function MV DC = VO D . = VI n1 (D + D1 ) (6.184) From (6.164) and (6.184), the peak inductor current is ) ( VI − V DT O V D(1 − n1 MV DC ) n1 ΔiL = = O . L n1 MV DC fs L (6.185) The dc output current is equal to the average value of the inductor current and from (6.184) and (6.185) can be expressed as IO = T V D(D + D1 )(1 − n1 MV DC ) (D + D1 )ΔiL 1 = O i dt = . T ∫0 L 2 2fs Ln1 MV DC (6.186) Using (6.184) and (6.185), IO = Solving for D gives √ D= √ 2fs Ln21 MV2 DC RL (1 − n1 MV DC ) = VO D2 (1 − n1 MV DC ) = VO . RL for D≤1− 2fs Ln21 MV2 DC 2fs LIO n21 MV2 DC VO (1 − n1 MV DC ) (6.187) 2fs L 2f LI = 1− s O. RL VO (6.188) At the boundary between CCM and DCM, n1 MV DCB = DB (6.189) as in CCM. Substitution of this into (6.188) yields the duty cycle DB at the boundary DB = 1 − 2fs L 2f LI = 1− s O. RL VO (6.190) Figures 6.16 and 6.17 show plots of D versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of n1 MV DC and n3 = n1 for the lossless forward converter, respectively. From (6.188), 2fs L 2 2 n M + n1 MV DC − 1 = 0 D2 RL 1 V DC (6.191) which yields the dc-to-dc voltage transfer function of the forward converter for DCM MV DC = VO = VI 2 2 ) ( √ ) = ( √ 8f LI 8fs L n1 1 + 1 + Ds2 V O n1 1 + 1 + D2 R L for D≤1− 2f LI 2fs L = 1− s O. RL VO (6.192) O It can be seen that MV DC depends on D, RL , L, and fs for DCM. Figures 6.18 and 6.19 show plots of n1 MV DC versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of D and n3 = n1 (i.e., DMAX = 0.5) for the lossless forward converter, respectively. Forward PWM DC–DC Converter 275 1 0.9 0.8 0.7 D 0.6 n1MVDC = 0.5 0.5 CCM 0.4 DCM 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0.2 0.4 0.6 IO/(V O/2fsL) 0.8 1 Figure 6.16 Duty cycle D as a function of IO ∕(VO ∕2fs L) at constant values of n1 MV DC and n3 = n1 for the lossless forward converter. 0.9 0.8 0.7 0.6 n M D 0.5 1 VDC = 0.5 CCM 0.4 0.4 0.3 0.2 0.1 0 0 10 Figure 6.17 converter. DCM 0.3 0.2 0.1 1 RL/(2fsL) 10 Duty cycle D as a function of RL ∕(2fs L) at constant values of n1 MV DC and n3 = n1 for the lossless forward 276 Pulse-Width Modulated DC–DC Power Converters 1 0.9 0.8 0.7 n1MVDC 0.6 D = 0.5 0.5 CCM 0.4 0.4 DCM 0.3 0.3 0.2 0.2 0.1 0.1 0 Figure 6.18 0 0.2 0.4 0.6 IO/(V O/2fsL) 0.8 1 n1 MV DC as a function of RL ∕(2fs L) at constant values of D for the lossless forward converter for n3 = n1 . 0.9 0.8 0.7 n1MVDC 0.6 0.5 D = 0.5 0.4 0.3 0.4 CCM DCM 0.3 0.2 0.2 0.1 0 0 10 Figure 6.19 0.1 1 RL/(2fsL) 10 n1 MV DC as a function of RL ∕(2fs L) at constant values of D for the lossless forward converter for n3 = n1 . Forward PWM DC–DC Converter From (6.184) and (6.192), (√ (√ ) ) ( ) 8fs L 8fs LIO D D 1 D1 = D −1 = 1+ 2 −1 = 1+ 2 −1 . n1 MV DC 2 2 D RL D VO 277 (6.193) Neglecting the current through the magnetizing inductance iLm , that is, iLm ≪ i1 , the converter input current iI is equal to the current through the primary i1 for 0 < t ≤ DT V I − VO i n iI = i1 + iLm ≈ i1 = 2 = 1 t n1 n1 L yielding the average value of the converter input current II = 1 T ∫0 DT VI − VO n1 n1 L D2 tdt = and the dc input power D2 VI PI = VI II = ( ( (6.194) VI − VO n1 ) (6.195) 2n1 fs L VI − VO n1 2n1 fs L ) . (6.196) The dc output power is PO = VO2 RL . (6.197) The converter efficiency is 𝜂= 2fs Ln21 MV2 DC PO . = 2 PI D RL (1 − n1 MV DC ) (6.198) Rearrangement of this equation gives the duty cycle of the lossy forward converter for DCM √ √ 2fs Ln21 MV2 DC 2fs LIO n21 MV2 DC 2f L 2f LI D= = for D < 1 − s = 1 − s O 𝜂RL (1 − n1 MV DC ) 𝜂VO (1 − n1 MV DC ) RL VO (6.199) and the voltage transfer function MV DC = VO = VI 2 2 ) ( ) = ( √ √ 8f LI 8fs L n1 1 + 1 + 𝜂Ds2 VO n1 1 + 1 + 𝜂D2 R for D<1− 2fs L 2f LI = 1− s O. RL VO (6.200) O L 6.3.6 Maximum Inductance for DCM The waveforms of the inductor current iL at the boundary between the DCM and CCM at the minimum input voltage VImin and at the maximum input voltage VImax are depicted in Figure 6.20. The minimum value of the inductor peak current at the boundary between CCM and DCM occurs at DB = DBmax and can be obtained from (6.21) as ΔiLmin = VO (1 − DBmax ) . fs Lmax (6.201) The dc output current at the boundary between the CCM and DCM IOB is equal to the maximum load current IOmax and is given by IOB = IOmax = V (1 − DBmax ) V ΔiLmin = O = O . 2 2fs Lmax RLmin (6.202) 278 Pulse-Width Modulated DC–DC Power Converters iL VImax n1 L VO VImin n1 L VO DminT DmaxT T iLmin IOB 0 Figure 6.20 VO L t Waveforms of the inductor current at the boundary between DCM and CCM for VImin and VImax . Thus, the maximum inductance required to maintain the converter operation in DCM is Lmax = RLmin (1 − DBmax ) VO (1 − DBmax ) = 2fs 2fs IOmax (6.203) n V n1 MV DCmax = 1 O. 𝜂 𝜂VImin (6.204) where DBmax = 6.3.7 Power Losses and Efficiency of Forward Converter for DCM The peak inductor current is √ 2(1 − n1 MV DC ) . fs LRL ΔiL = VO The rms switch current is √ ISrms = 1 T ∫0 DT i2S dt = ΔiL n1 √ (6.205) √ √ √ √ 2n21 MV2 DC (1 − n1 MV DC ) D VO √ 2 = 3 n1 3RL fs LRL (6.206) resulting in MOSFET conduction power loss 2 PrDS = rDS ISrms = DrDS Δi2L 3n21 √ = 2rDS 2n21 MV2 DC (1 − n1 MV DC ) 3n21 fs LRL PO . (6.207) The switching loss is Psw = fs Co VI2 = fs Co VO2 MV2 DC fC R = s 2o L PO . MV DC (6.208) The power loss in the MOSFET is ⎡ 2r P PF ET = PrDS + sw = ⎢ DS ⎢ 3n2 2 ⎣ 1 √ 2n21 MV2 DC (1 − n1 MV DC ) fs LRL + fs Co RL ⎤⎥ PO . 2MV2 DC ⎥ ⎦ (6.209) The power loss in the winding resistance of the primary is 2 = PrT1 = rT1 ISrms DrT1 Δi2L 3n21 √ = 2rT1 2n21 MV2 DC (1 − n1 MV DC ) 3n21 fs LRL PO . (6.210) Forward PWM DC–DC Converter 279 The rms value of the current through diode D1 is √ 1 T ∫0 ID1rms = √ DT i2D1 dt = ΔiL √ √ √ √ 2n21 MV2 DC (1 − n1 MV DC ) √ D 2 = VO 3 3RL fs LRL (6.211) yielding the power loss in the forward resistance of D1 2 PRF1 = RF ID1rms = RF DΔi2L 3 √ 2RF = 3 2n21 MV2 DC (1 − n1 MV DC ) fs LRL PO . (6.212) The average current through diode D1 is ID1 = 1 T ∫0 DT iD1 dt = IO n1 MV DC (6.213) resulting in the power loss in VF of D1 n1 MV DC VF PO . VO PV F1 = VF ID1 = n1 MV DC IO VF = (6.214) Hence, the power loss in diode D1 is ⎡n M V 2R PD1 = PV F1 + PRF1 = PO ⎢ 1 V DC F + F ⎢ VO 3 ⎣ √ 2n21 MV2 DC (1 − n1 MV DC ) ⎤ ⎥. ⎥ fs LRL ⎦ The power loss in the winding resistance of the secondary is √ rT2 DΔi2L 2rT2 2n21 MV2 DC (1 − n1 MV DC ) 2 PrT2 = rT2 ID1rms = = PO . 3 3 fs LRL The winding power loss in both primary and secondary is given by ) √ 2 2 ( rT1 2 2n1 MV DC (1 − n1 MV DC ) PrT = PrT1 + PrT2 = + r PO . T2 3 fs LRL n21 (6.215) (6.216) (6.217) The rms value of the current through the diode D2 is √ ID2rms = (D+D1 )T 1 T ∫DT √ i2D2 dt = ΔiL √ √ √ √ 2(1 − n1 MV DC )3 D1 √ 2 = VO 3 3RL fs LRL (6.218) yielding the power loss in RF of D2 PRF2 = RF ID2rms = D1 RF Δi2L 3 √ 2RF = 3 2(1 − n1 MV DC )3 PO . fs LRL (6.219) The average current through diode D2 is T 2 D VO 1 ID2 = i dt = T ∫0 D2 2fs L ( 1 MV DC )2 −1 = IO (1 − n1 MV DC ) (6.220) 280 Pulse-Width Modulated DC–DC Power Converters which leads to the power loss in VF of diode D2 PV F2 = VF ID2 = VF IO (1 − n1 MV DC ) = VF (1 − n1 MV DC ) PO . VO Hence, the conduction power loss in diode D2 is ⎡ V (1 − n M 2R 1 V DC ) + F PD2 = PV F2 + PRF2 = ⎢ F ⎢ VO 3 ⎣ √ 2(1 − MV DC )3 ⎤⎥ P . ⎥ O fs LRL ⎦ The rms value of the inductor current is √ √ √ √ √ √ (D+D1 )T 2(1 − n1 MV DC ) D + D 1 √ 2 1 2 ILrms = = VO iL dt = ΔiL T ∫0 3 3RL fs LRL yielding the power loss in the inductor winding 2 = PrL = rL ILrmas rL Δi2L (D + D1 ) 3 (6.221) (6.222) (6.223) √ 2r = L 3 2(1 − n1 MV DC ) PO . fs LRL (6.224) The total converter power loss is PLS = PrDS + Psw + PD1 + PD2 + PrL + PrT1 + PrT2 √ ( ) √ 2 2 ⎡ r +r 2 2n1 MV DC (1 − n1 MV DC ) fs Co RL 2RF 2(1 − n1 MV DC )3 VF DS T1 ⎢ = + RF + rT2 + 2 + + ⎢ 3 fs LRL 3 fs LRL VO n21 MV DC ⎣ √ 2rL 2(1 − n1 MV DC ) ⎤⎥ P . + (6.225) ⎥ O 3 fs LRL ⎦ The efficiency of the forward converter for DCM is given by ) √ 2 2 ( ⎡ PO PO + r r 1 2 2n1 MV DC (1 − n1 MV DC ) DS T1 𝜂= = = = ⎢1 + + RF + rT2 PLS 2 ⎢ PI PO + PLS 3 fs LRL n1 1+ P ⎣ O √ −1 √ fs Co RL 2RF 2(1 − n1 MV DC )3 VF 2rL 2(1 − n1 MV DC ) ⎤⎥ + 2 + + + . ⎥ 3 fs LRL VO 3 fs LRL MV DC ⎦ (6.226) 6.3.8 Design of Forward Converter for DCM Design a universal PWM forward converter operating in DCM to meet the following specifications: VO = 5 V, IOmin = 0 A, IOmax = 20 A, Vr ∕VO ≤ 10%, and the input voltage is the single-phase utility line rectified voltage anywhere in the world whose rms voltage is in the range from 85 to 264 Vrms. Solution: The minimum and maximum values of the dc input voltage are √ √ VImin = 2 × Vrms(min) = 2 × 85 = 120 V and VImax = √ 2 × Vrms(max) = √ 2 × 264 = 373 V. (6.227) (6.228) Forward PWM DC–DC Converter 281 The minimum and maximum values of the dc voltage transfer function are MV DCmin = VO 1 5 = = 0.0134 = VImax 373 74.6 (6.229) MV DCmax = VO 1 5 = = 0.04167. = VImin 120 24 (6.230) and The maximum value of the dc output power is POmax = VO IOmax = 5 × 20 = 100 W. (6.231) The minimum load resistance is RLmin = VO 5 = 0.25 Ω. = IOmax 20 (6.232) Let us assume the switching frequency fs = 100 kHz, the converter efficiency 𝜂 = 80%, and Dmax ≈ 0.4. In this case, the transformer turns ratio is n1 = 𝜂Dmax 0.8 × 0.4 = 7.679. = MV DCmax 0.04167 (6.233) Pick n1 = n3 = 8. The maximum permissible duty cycle is 1 1 = = 0.5. 1+1 + 1 n DMAX = n3 (6.234) 1 Thus, Dmax < DMAX . The minimum and maximum values of the duty cycle at the CCM/DCM boundary are n1 MV DCmin 8 × 0.0134 = = 0.134 𝜂 0.8 (6.235) n1 MV DCmax 8 × 0.04167 = = 0.4167. 𝜂 0.8 (6.236) RLmin (1 − DBmax ) 0.25 × (1 − 0.4167) = = 0.729 μH. 2fs 2 × 105 (6.237) DBmin = and DBmax = The maximum inductance is Lmax = Pick a standard inductance L = 0.56 μH. The maximum duty cycle at VI = VImin = 120 V and RLmin is √ √ 2fs Ln21 MV2 DCmax 2 × 105 × 0.56 × 10−6 × 82 × 0.041672 = 0.3055 = Dmax = 𝜂(1 − n1 MV DCmax )RLmin 0.8 × (1 − 8 × 0.04167) × 0.25 resulting in ( D1min = Dmax 1 n1 MV DCmax ) −1 ( = 0.3055 ) 1 − 1 = 0.6109 8 × 0.04167 (6.238) (6.239) and hence Dmax + D1min = 0.3055 + 0.6109 = 0.9164 < 1. (6.240) 282 Pulse-Width Modulated DC–DC Power Converters The minimum inductor current is ( ΔiLmin = VImin − VO n1 ( ) Dmax = fs L 120 −5 8 ) 0.3055 = 54.46 A. 105 × 0.56 × 10−6 The minimum duty cycle at VI = VImax = 373 V and RLmin is √ √ 2fs Ln21 MV2 DCmin 2 × 105 × 0.56 × 10−6 × 82 × 0.01342 = Dmin = = 0.0849 𝜂(1 − n1 MV DCmin )RLmin 0.8 × (1 − 8 × 0.0134) × 0.25 which gives ( D1max = Dmin ) 1 −1 n1 MV DCmin ( = 0.0849 ) 1 − 1 = 0.707 8 × 0.0134 (6.241) (6.242) (6.243) producing Dmin + D1max = 0.0134 + 0.707 = 0.7204 < 1. The maximum inductor current is ΔiLmax = ( VImax − VO n1 ) ( Dmin fs L = 373 −5 8 (6.244) ) 0.0849 105 × 0.56 × 10−6 = 63.106 A. (6.245) The ripple voltage is Vr = 0.1 × VO = 0.1 × 5 = 500 mV. (6.246) The maximum ESR of the filter capacitor is rCmax = Vr 500 = 7.92 mΩ. = ΔiLmax 63.106 (6.247) Let rC = 7 mΩ. Thus, the filter capacitance is } { } { 1 − Dmin Dmax 1 − Dmin 1 − 0.0849 0.3055 1 − 0.0849 = max = = 653.64 μF. , , = Cmin = max 2fs rC 2fs rC 2fs rC 2fs rC 2fs rC 2 × 105 × 0.007 (6.248) Pick C = 1 mF/16 V/7 mΩ. The current and voltage stresses of the rectifier diodes are ID1Mmax = ID2Mmax = ΔiLmax = 63.106 A (6.249) VD1Mmax = VImax 373 = 46.625 V = n3 8 (6.250) VD2Mmax = VImax 373 = 46.625 V. = n1 8 (6.251) and The maximum peak current through the primary of the ideal transformer I1max = ID1Mmax 63.106 = 7.888 A = n1 8 (6.252) Forward PWM DC–DC Converter 283 and the maximum peak current through the magnetizing inductance is ΔiLm(max) = 0.1I1max = 0.1 × 7.888 = 0.7888 A (6.253) producing the minimum magnetizing inductance Lm(min) = Dmin VImax 0.0849 × 373 = 5 = 0.4 mH. fs ΔiLm(max) 10 × 0.7888 (6.254) The current and voltage stresses of the switch are ISMmax = I1max + ΔiLm(max) = 7.888 + 0.7888 = 8.6768 A and ( VSMmax = ) n1 + 1 VImax = 2VImax = 2 × 373 = 746 V. n3 The current and voltage stresses of diode D3 are ( ) n3 ΔiLm(max) = 0.7888 A ID3Mmax = n1 and ( VD3Mmax = ) n3 + 1 VImax = 2VImax = 2 × 373 = 746 V. n1 (6.255) (6.256) (6.257) (6.258) A Cree SiC CMF20120D power MOSFET is selected, which has VDSS = 1200 V, ISM = 42 A, rDS = 80 mΩ, TJmax = 125◦ C, junction-to-case thermal resistance 𝜃JC = 0.51 K/W, and TO247-3 package. Two MBR2540 Schottky barrier diodes are also chosen for D1 and D2 , which has IDM = 25 A, VDM = 40 V, VF = 0.3 V, and RF = 16 mΩ. A Cree C2d05120a SiC Schottky diode is selected for D3 , which has VDM = 1.2 kV and IDM = 5 A. The power losses will be calculated for full load RLmin = 0.25 Ω and the maximum input voltage VImax = 373 V. The MOSFET conduction power loss is √ 2rDS 2n21 MV2 DCmin (1 − n1 MV DCmin ) POmax PrDS = fs LRLmin 3n21 √ 2 × 0.08 2 × 82 × 0.01342 (1 − 8 × 0.0134) = × 100 = 0.1009 W. (6.259) 3 × 82 105 × 0.56 × 10−6 × 0.25 The switching loss is 2 Psw = fs Co VImax = 105 × 100 × 10−12 × 3732 = 1.391 W. (6.260) The power loss in the MOSFET is PF ET = PrDS + Psw 1.391 = 0.1009 + = 0.7964 W. 2 2 Assuming rT1 = 0.05 Ω, the power loss in the winding resistance of the primary is given by √ 2rT1 2n21 MV2 DCmin (1 − n1 MV DCmin ) PrT1 = POmax fs LRLmin 3n21 √ 2 × 0.05 2 × 82 × 0.01342 (1 − 8 × 0.0134) = × 100 = 0.063 W. 3 × 82 105 × 0.56 × 10−6 × 0.25 (6.261) (6.262) 284 Pulse-Width Modulated DC–DC Power Converters The power loss in the forward resistance of diode D1 is √ 2RF 2n21 MV2 DCmin (1 − n1 MV DCmin ) PRF1 = POmax 3 fs LRLmin √ 2 × 0.016 2 × 82 × 0.01342 (1 − 8 × 0.0134) = × 100 = 1.291 W 3 105 × 0.56 × 10−6 × 0.25 and the power loss in VF of diode D1 is PV F1 = n1 MV DCmin IOmax VF = 8 × 0.0134 × 20 × 0.3 = 0.643 W (6.263) (6.264) resulting the conduction loss in diode D1 PD1 = PRF1 + PV F1 = 1.291 + 0.643 = 1.934 W. Assuming rT2 = 0.01 Ω, the power loss in the winding resistance of the secondary is √ 2rT2 2n21 MV2 DCmin (1 − n1 MV DCmin ) POmax PrT2 = 3 fs LRLmin √ 2 × 0.01 2 × 82 × 0.01342 (1 − 8 × 0.0134) = × 100 = 0.807 W. 3 105 × 0.56 × 10−6 × 0.25 The winding power loss in both primary and secondary is given by PrT = PrT1 + PrT2 = 0.063 + 0.807 = 0.87 W. The power loss in the forward resistance RF of D2 is √ √ 2RF 2(1 − n1 MV DCmin )3 2(1 − 8 × 0.0134)3 2 × 0.016 POmax = × 100 = 10.76 W. PRF2 = 5 3 fs LRLmin 3 10 × 0.56 × 10−6 × 0.25 (6.265) (6.266) (6.267) (6.268) The power loss in VF of diode D2 is PV F2 = VF IOmax (1 − n1 MV DCmin ) = 0.3 × 20 × (1 − 8 × 0.0134) = 5.357 W. (6.269) Hence, the conduction power loss in diode D2 is PD2 = PV F2 + PRF2 = 5.357 + 10.76 = 16.12 W. Assuming rL = 0.015 Ω, the power loss in the inductor winding resistance is √ √ 2rL 2(1 − n1 MV DCmin ) 2(1 − 8 × 0.0134) 2 × 0.015 PrL = POmax = × 100 = 11.29 W. 3 fs LRLmin 3 105 × 0.56 × 10−6 × 0.25 (6.270) (6.271) The total converter power loss is PLS = PrDS + Psw + PD1 + PD2 + PrL + PrT = 0.1009 + 1.316 + 1.934 + 16.12 + 11.29 + 0.87 = 32.1191 W. (6.272) The efficiency of the forward converter is 𝜂= POmax 100 = 75.67%. = POmax + PLS 100 + 32.1191 (6.273) Figures 6.21 through 6.26 show the characteristics of the designed forward converter for DCM. The lowest efficiency 𝜂 occurs at IOmax and VImax . The duty cycle D decreases as VI increases and IO decreases (or RL increases). Forward PWM DC–DC Converter 285 92 R = 2.5 Ω L 91 90 89 R = 0.5 Ω L η (%) 88 87 86 85 84 RL = 0.25 Ω 83 82 120 Figure 6.21 in DCM. 130 140 150 VI (V) 160 170 180 190 Efficiency 𝜂 as a function of the dc input voltage VI at various load resistances RL for the forward converter 0.44 0.42 R = 0.5 Ω 0.4 L R = 0.25 Ω L 0.38 D 0.36 0.34 RL = 2.5 Ω 0.32 0.3 0.28 0.26 120 Figure 6.22 in DCM. 130 140 150 VI (V) 160 170 180 190 Duty cycle D as a function of the dc input voltage VI at various load resistances RL for the forward converter 286 Pulse-Width Modulated DC–DC Power Converters 88 V = 120 V I 86 84 V I= 187 V η (%) 82 V I= 373 V 80 78 76 74 72 70 Figure 6.23 in DCM. 0 5 10 IO (A) 15 20 Efficiency 𝜂 as a function of the dc load current IO at various dc input voltages VI for the forward converter 0.35 0.3 0.25 V I = 120 V D 0.2 0.15 V I = 187 V 0.1 V = 373 V I 0.05 0 Figure 6.24 in DCM. 0 5 10 IO (A) 15 20 Duty cycle D as a function of the dc load current IO at various dc input voltages VI for the forward converter Forward PWM DC–DC Converter 287 92 91 90 89 η (%) 88 87 86 85 V I = 187 V V I = 127 V 84 83 V = 156 V 82 Figure 6.25 in DCM. I 2 4 6 8 10 12 IO (A) 14 16 18 20 Efficiency 𝜂 as a function of the load current IO at various dc input voltages VI for the forward converter 0.44 0.42 0.4 V = 127 V I 0.38 D 0.36 0.34 V = 156 V I 0.32 0.3 0.28 V = 187 V I 0.26 Figure 6.26 in DCM. 0 0.5 1 RL (Ω) 1.5 2 2.5 Duty cycle D as a function of the load resistance RL at various dc input voltages VI for the forward converter 288 Pulse-Width Modulated DC–DC Power Converters Figure 6.27 Multiple-output forward converter. 6.4 Multiple-Output Forward Converter Figure 6.27 shows a two-output forward converter. In order to obtain the second output, the transformer has an extra secondary winding, which drives an additional rectifier composed of two diodes, an inductor, and a filter capacitor. More outputs can be obtained by adding more secondaries, rectifiers, and low-pass filters. Usually, only one output is controlled and other outputs are not regulated. If the dc input voltage VI is increased, the duty cycle D is decreased by the feedback network of the controlled output. Nearly the same decrease in D is also required by the unregulated outputs, maintaining the output voltages close to the required values. However, the load resistances may change in the direction opposite to that of the regulated output, causing variations of the output voltages. This is especially true for DCM operation, in which the output voltage is heavily dependent on the load resistance. Interactions between multiple outputs is called cross-regulation. 6.5 Forward Converter with Synchronous Rectifier Synchronous rectifiers are attractive in low output voltage applications (e.g., 1.8 or 3.3 V), where Schottky diodes may be replaced by low on-resistance MOSFETs, as shown in Figure 6.28. In the self-driven architecture shown in Figure 6.28(a), the MOSFETs are driven by the transformer output voltage. The transistor gates are connected to the opposite ends of the secondary winding, and the gate of each device is connected to the drain of another device. The rectifier MOSFETs are automatically synchronized to the main switch. The benefits of this topology are simplicity and low parts count. In the circuit of Figure 6.28(b), the MOSFETs are driven by an IC driver, which is normally a part of an IC control circuit. The transformer in the driver and the transformer in the power stage ensure dc isolation between the converter input and the output. Unlike diodes, MOSFETs do not have offset voltages. Low-voltage MOSFETs exhibit very low on-resistances, for example, 5 mΩ, yielding low conduction loss and high efficiency. Since MOSFETs can conduct current in both directions, the transformer reset circuit is not needed. A converter with a synchronous rectifier may operate only in CCM. 6.6 Forward Converters with Active Clamping A forward converter with three active clamping and core reset circuits is shown in Figure 6.29 [17]. The clamping circuit of Figure 6.29(a) is connected across the transformer primary. The main transistor Q1 is driven with the duty Forward PWM DC–DC Converter 289 n:1 + VO + VI (a) n:1 + VO + VI 1:1 (b) Figure 6.28 MOSFETs. Forward converters with synchronous rectifier. (a) With self-driven MOSFETs. (b) With IC driver of all cycle D and the clamp transistor is driven with the duty cycle 1 − D. This circuit is called the high-end n-channel active clamp. The MOSFET Q2 carries only the transformer magnetizing current, which has a small peak value compared to the reflected load current. Therefore, Q2 may have a much lower current rating than that of Q1 . A dead time is required between the time Q1 is turning off and the time Q2 is turning on. During the dead time, the primary current flows through the body diode of either MOSFET. This is a resonant time interval in which zero-voltage switching (ZVS) occurs. Neglecting the voltage drop across the leakage inductance, the voltage across the clamping capacitor Cc is VCc(H) = VI . 1−D (6.274) Therefore, it is also called the boost type clamp. The voltage across the main switch Q1 is given by VDS(Q1 ) = VI2 VI − nVO . (6.275) The clamping circuit of Figure 6.29(b) is connected in parallel with the main switch. It is called the low-end n-channel active clamp. Neglecting the voltage drop across the leakage inductance, the voltage across the clamping capacitor Cc is VCc(L) = D V. 1−D I (6.276) Therefore, it is also called the buck–boost type clamp. The voltage across the main switch Q1 is given by (6.275). The clamping circuit of Figure 6.29(c) is called the low-end p-channel active clamp. It uses a p-channel MOSFET. There is no need for the transformer reset circuit in all three circuits. 290 Pulse-Width Modulated DC–DC Power Converters L CC Q2 VI C RL + VO C RL + VO RL + VO 1 D Q1 D (a) L CC VI 1 D Q2 D Q1 (b) L C VI CC Q1 Q2 D 1 D (c) Figure 6.29 Forward converters with active clamping. (a) High-end n-channel active clamping. (b) Low-end n-channel active clamping. (c) Low-end p-channel active clamping. 6.7 Two-Switch Forward Converter A two-transistor forward converter is shown Figure 6.30. Both transistors are on simultaneously during the time interval 0 < t ≤ DT and are off during the reminder of the cycle. During the interval 0 < t ≤ DT, the voltage across the primary winding is VI , the current through the magnetizing inductance Lm flows through both transistors, and it increases with slope VI ∕Lm . After the transistors are turned off, the magnetizing inductance is demagnetized by diodes D1 and D2 , the voltage across the primary winding is −VI , the current of the magnetizing inductance Lm decreases to zero at time t = DT + tm with slope −VI ∕Lm , and the energy stored in the magnetizing inductance Lm is returned to the input voltage source VI . The magnetizing current is reset to zero before the beginning of the next cycle. The condition of a complete demagnetization of the core is tm ≤ 1 − D. When the magnetizing current Forward PWM DC–DC Converter Q1 D1 n:1 D3 VI L C D4 D2 291 RL + VO Q2 Figure 6.30 Two-transistor forward converter. decrease gradually and reaches zero, both demagnetization diodes turn off at zero current. Therefore, the duty cycle must be held in the range 0 < D < 0.5. There is no need for a core reset circuit, which usually consists of a separate winding and a diode. The rectifier circuit on the secondary side of the transformer is identical to that of the single-transistor forward converter. The horizontal rectifier diode conducts when both transistors are on, and the freewheeling diode conducts when both transistors are off. The dc voltage transfer function for CCM is MV DC = VO 𝜂D . = VI n (6.277) The two-switch forward converter has reduced ringing. The peak voltage across the switches is VSM = VI , which is much lower than that of a single-switch forward converter. The voltage rating of the switch in a single-switch forward converter is VSM = VI (1 + n1 ∕n3 ). However, the circuit requires a floating gate drive for the high side transistor. 6.8 Forward–Flyback Converter In a conventional forward converter, the diode D3 in the core flux reset circuit is connected to the dc input voltage source VI , as shown in Figure 6.1(d). In this circuit, the energy stored in the magnetic field of the transformer is transferred to the input dc source VI . Figure 6.31 shows a forward converter, in which the diode D3 of the core reset circuit is connected to the output filter capacitor C and the load resistor RL [13]. Therefore, the energy stored D3 N3 N1 N2 D1 L D2 C RL + VO VI Figure 6.31 Single-transistor forward–flyback converter. 292 Pulse-Width Modulated DC–DC Power Converters Q1 D1 D2 L n:1 D4 VI C RL + VO D5 D2 Figure 6.32 Q2 Two-transistor forward–flyback converter [19]. in the magnetic field of the transformer is transferred to the filter capacitor and the load. The maximum value of the magnetic filed density is Bmax = DVO T DVO = < Bs . N3 Ac N3 Ac fs (6.278) Figure 6.32 depicts a two-switch forward–flyback converter [19]. In this circuit, the voltage stress across the switches is reduced. It is VSMmax = VImax . 6.9 Summary r The PWM forward converter can be derived from the buck converter by adding a transformer, a diode, and a transformer core reset circuit. Therefore, it belongs to the family of buck-derived converters. r The PWM forward converter provides dc isolation between the input and the output. r The transformer allows the forward converter to obtain much lower and much higher values of the dc voltage transfer function than those of the buck converter. r The forward converter is a step-down or a step-up converter. r If the number of turns of the primary and tertiary is the same, the voltage stress on the transistor is twice the dc input voltage and the duty cycle D must be less than 0.5 in the forward converter. r The typical power level of the forward converter is from 30 to 500 W. r The transistor is driven with respect to ground in the forward converter. r The magnetizing inductance of the transformer is not required to store energy. r The forward converter requires a transformer core reset circuit. r The maximum duty cycle in the forward converter is less than 100% to allow for core reset. r The magnetic core utilization is poor in the forward converter because a dc current flows through the primary. r The forward converter can operate in two modes: CCM or DCM. r The dc voltage transfer function of the lossless forward converter is M V DC = D∕n1 . r The duty cycle D of the lossy converter is greater than that of the lossless converter at the same dc voltage transfer function. r The peak-to-peak value of the inductor current ripple Δi is independent of the dc load current for CCM. L r The peak-to-peak value of the current through the filter capacitor C is equal to the peak-to-peak inductor current ripple ΔiL . r The peak-to-peak ripple current through the filter capacitor decreases as the inductance L increases. r If the capacitance of the filter capacitor is sufficiently high, the output ripple voltage is determined only by the ESR of the filter capacitor and is independent of the capacitance of the filter capacitor. Forward PWM DC–DC Converter 293 r The minimum value of the inductance L is determined by the boundary between CCM and DCM, ripple of the output voltage, or ac losses in the inductor and/or the filter capacitor. r A disadvantage of the forward converter is that the input current is pulsating. However, a nonpulsating input current waveform can be obtained by inserting an input √ LC filter between the input dc source and the transistor. r The corner frequency of the output filter f = 1∕(2𝜋 LC) is independent of the load resistance. o r For the forward converter operating in CCM and DCM, the minimum efficiency occurs at the maximum load current IOmax (or RLmin ) and a high efficiency occurs at light loads. r The two-switch forward converter has a reduced voltage stress of the MOSFETs and does not require a separate core reset circuit. References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. [3] K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. [4] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [5] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. [6] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [7] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood Cliffs, NJ: Prentice Hall, 2004. [8] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [9] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [10] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. [11] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [12] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. [13] J. N. Park and T. R. Zaloun, “A dual mode forward flyback converter,” IEEE PESC, 1982, pp. 3–13. [14] J. Sebastian, J. Uceda, M. Rico, M. A. Pérez, and F. Aldana, “A complete study of the double forward-flyback converter,” IEEE Power Electronics Specialists Conference, 1988, pp. 142–149. [15] H. E. Tacca, “Single-switch two-output flyback-forward converter operation,” IEEE Transactions on Power Electronics, vol. 13, no. 5, pp. 903–911, September 1998. [16] Y.-M. Liu and L.-K. Chabg, “Single-stage soft-switching AC-DC converter with input-current shaping for universal line applications,” IEEE Transactions on Industrial Electronics, vol. 56, no. 2, pp. 467–479, February 2009. [17] B. Carsten, “Design techniques for transformer active reset circuits and high frequencies at power levels,” Proceedings of the High Frequency Power Conversion, 1990, pp. 235–246. [18] I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. [19] D. Murthy-Bellur and M. K. Kazimierczuk, “Two-switch flyback-forward PWM dc-dc converter with reduced switch voltage stress,” Proceedings of the IEEE International Symposium on Circuits and Systems, Paris, France, May 31–June 2, 2010, pp. 3705–3707. Review Questions 6.1 Does the forward PWM converter provide dc isolation between the input and the output? 6.2 Does the forward converter require a transformer core reset circuit? Explain its operation. 6.3 What is the range of the duty cycle in the forward converter? 6.4 Is the forward converter a step-down or a step-up converter? 6.5 Is the transformer required to store energy in the forward converter? 294 Pulse-Width Modulated DC–DC Power Converters 6.6 Is the input current of the basic forward converter pulsating? 6.7 How can the forward converter circuit be modified to obtain a nonpulsating input current? 6.8 Is the transistor drive circuit floating with respect to ground in the forward converter? 6.9 How is the dc voltage transfer function MV DC related to the duty cycle D of the lossless forward converter for CCM? 6.10 Is the duty cycle D of the lossy forward converter lower or greater than that of the lossless converter at a given value of MV DC for CCM? 6.11 Is the corner frequency of the output filter dependent on the load resistance in the forward converter? 6.12 Is it possible to obtain a negative output voltage in the forward converter? If so, draw a circuit of such a converter. 6.13 Is it possible to obtain multiple-output forward converter? If so, draw the circuit of such a converter. 6.14 Is it possible to control all the outputs in the forward converter? 6.15 What is the typical output power range of the forward converter? 6.16 Is the efficiency high at heavy or light loads for the forward converter? Problems 6.1 For the forward PWM converter, find the maximum duty cycle DMAX . (a) For n3 = 0.5n1 . (b) For n3 = 2n1 . (c) For n3 = 4n1 . 6.2 For the forward PWM converter, find the switch peak voltage in terms of the dc input voltage VI . (a) For n3 = 0.5n1 . (b) For n3 = 2n1 . (c) For n3 = 4n1 . 6.3 For the forward PWM converter, find the peak voltage of the diode D3 connected in series with the tertiary in terms of the dc input voltage VI . (a) For n3 = 0.5n1 . (b) For n3 = 2n1 . (c) For n3 = 4n1 . 6.4 A forward PWM converter is supplied by a European single-phase rectified utility line voltage and VO = 12 V. Find the primary-to-secondary transformer turns ratio n1 . 6.5 A forward PWM converter is supplied by a European single-phase rectified utility line voltage, VO = 12 V, and n1 = 8. Find the maximum permissible duty cycle DMAX . 6.6 A forward PWM converter is supplied by a European single-phase rectified utility line voltage, VO = 12 V, and n1 = n3 = 8. Find the minimum, nominal, and maximum duty cycle. 6.7 A forward PWM converter is supplied by a European single-phase rectified utility line voltage, VImax = 342 V, VO = 12 V, and n1 = n3 = 8. Find the voltage stresses of the semiconductor devices. 6.8 A forward PWM converter has VO = 12 V, IO = 4–40 A, n1 = n3 = 8, VImax = 342 V, 𝜂 = 90%, and fs = 75 kHz. Find the minimum inductance required for the CCM operation. 6.9 A forward PWM converter has VO = 12 V, IO = 4–40 A, the duty cycle Dmin = 0.3119, L = 20 μH, Dmin = 0.3119, fs = 75 kHz, and Vr ∕VO ≤ 1%. Find the filter capacitance and the corner frequency of the output filter. 6.10 A forward PWM converter has VO = 12 V, IO = 4–40 A, L = 20 μH, Dmin = 0.3119, and fs = 75 kHz. Find the current stresses of the rectifier diodes. Forward PWM DC–DC Converter 295 6.11 A forward PWM converter has VO = 12 V, IO = 4–40 A, n1 = n3 = 8, L = 20 μH, VImax = 342 V, Dmin = 0.3119, and fs = 75 kHz. Find the magnetizing inductance such that its peak current is less than 12% of the maximum peak current of the primary of the ideal transformer. 6.12 A forward PWM converter is supplied by a European single-phase rectified utility line voltage, VO = 12 V, IO = 4–40 A, n1 = n3 = 8, L = 20 μH, and fs = 75 kHz. Find the current stress of the switch. 6.13 For a forward PWM converter supplied by a European single-phase rectified utility line voltage, determine the maximum inductance required for DCM operation, if VO = 12 V, IO = 0–4 A, n1 = n3 = 8, and fs = 75 kHz. 6.14 Design a PWM forward converter that will meet the following specifications: the CCM, VI is the European single-phase rectified line voltage with Vrms = 220 V±10%, VO = 14 V, IOmin = 2 A, IOmax = 20 A, and Vr ∕VO ≤ 1%. Assume rDS = 1 Ω, VF = 0.56 V, RF = 25 mΩ, rL(dc) = 20 mΩ, rT1 = 100 mΩ, rT2 = 25 mΩ, Co = 100 pF, Lm = 5 mH, and fs = 100 kHz. Find component values, component stresses, and converter efficiency. 6.15 Design a PWM forward converter with VI = 48±6 V, VO = 5 V, IO = 2–20 A, fs = 50 kHz, Vr ∕VO ≤ 1%, and ΔiLm(max) ∕I1max ≤ 10%. Find L, Lm , C, rC , n1 , n3 , Dmin , Dmax , DMAX , VSMmax , ISMmax , VD1Mmax , ID1Mmax , VD2Mmax , ID2Mmax , VD3Mmax , ID3Mmax , and 𝜂. Assume the CCM, rDS = 0.18 Ω, VF = 0.4 V, RF = 20 mΩ, rL(dc) = 20 mΩ, rT1 = 50 mΩ, rT2 = 15 mΩ, and Co = 200 pF. 6.16 A PWM forward converter has VI = 24–32 V, IO = 2–20 A, VO = 18 V, and fs = 150 kHz. Find L, C, n1 , n3 , Dmin , Dmax , DMAX , VSMmax , ISMmax , ID1Mmax , VD1Mmax , and VD3Mmax . 6.17 Draw a circuit of a multiple-output dc–dc forward converter with VO1 = 3.3 V, VO2 = 12 V, and VO3 = −12 V. 7 Half-Bridge PWM DC–DC Converter 7.1 Introduction The half-bridge PWM dc–dc converter [1–12] contains two transistors, a transformer, and a rectifier. Its main advantage is that the voltage stresses of the transistors are low and equal to the maximum dc input voltage of the converter. It can handle the rectified dc voltage of the European 220 Vrms + 10% utility single-phase line, which usually ranges from 280 to 340 V. Power transistors with a 400-to-500 V voltage rating are readily available and may be used in this converter; therefore, the half-bridge converter is used in off-line power supplies. Another advantage is that the core saturation problems are minimized because the dc component of the current through the primary is zero due to the coupling or blocking capacitors in series with the primary. Since the primary is driven in both directions, the core is utilized more effectively. The disadvantages are the requirement of an additional power transistor and an isolated driver for the upper transistor. Typically, the converter is suitable for medium and high power applications ranging from 150 W to 1 kW and is widely used in telecommunication power supplies. It belongs to the family of buck-derived converters. The purpose of this chapter is to present an analysis and a design procedure for the half-bridge PWM converter. 7.2 DC Analysis of PWM Half-Bridge Converter for CCM 7.2.1 Circuit Description A circuit of the PWM half-bridge dc–dc converter is depicted in Figure 7.1(a). The converter consists of a PWM inverter and a PWM rectifier. The inverter consists of two power MOSFETs used as controllable switches S1 and S2 , a transformer, and two blocking capacitors Cb . The isolation transformer does not have to store energy. Its magnetizing inductance should be large enough to reduce the current through this inductance and the switches. Because of the blocking capacitors, the dc current through the primary of the transformer is zero, resulting in excellent core utilization. In addition, the core is operated in a bipolar mode because the primary winding is driven in both directions from VI ∕2 to −VI ∕2; therefore, the core is utilized more effectively. The core is half the size of equivalent transformers in single-transistor converters, in which magnetic cores are operated in unipolar mode. Therefore, the half-bridge converter provides a cost advantage over its single-transistor counterparts. The transistors are driven by nonoverlapping voltages that are out of phase by 180◦ . The maximum duty cycle of gate-to-source voltages is slightly less than 50% to avoid the situation, when both transistors are conducting at Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 Half-Bridge PWM DC–DC Converter VI VI 2 VI 2 297 S1 Cb n:1:1 D1 L S2 Cb + VO C RL C RL + VO C RL + VO 0 D2 (a) n:1 L (b) n:1 L (c) Figure 7.1 Half-bridge converter with two blocking capacitors. (a) With a transformer center-tapped rectifier. (b) With a full-bridge rectifier. (c) With a half-wave rectifier. the same time. In this case, the dc input voltage VI is connected to the ground through two on-resistances of the MOSFETs, generating a very large current spike and destroying the transistors. For example, if dc input voltage is VI = 340 V and the MOSFET on-resistance is rDS = 1 Ω, then the peak current through the MOSFETs is Ipk = VI ∕(2rDS ) = 340/2 = 170 A. The phenomenon when both transistors are conducting at the same time is called a cross conduction, and the current through the transistors is called a shoot-through current. The switching network of the inverter has two transistors in series (a totem pole arrangement), resulting in difficulty in driving the highend (upper) transistor because its gate is not referenced to ground. A small wide bandwidth (pulse) transformer is normally used to drive the upper transistor to achieve a square-wave gate-to-source voltage. A second pulse transformer is usually added to drive the bottom transistor. This driver provides dc isolation in the control path. DC isolation is required in the power stage and the control circuit to accomplish a dc isolation between the input and the output of a dc–dc converter. Pulse transformers also provide protection of a control circuit against high-voltage breakdown. The transistor may be broken in such a way that there is a short circuit between the transistor drain and gate, and a high voltage VI appears at the transistor gate. If the control circuit is directly coupled to the gate, a high voltage is applied across the control circuit output, destroying the control circuit. However, if a control circuit is coupled to the gate through a pulse transformer, the control circuit will not be damaged by a high voltage at the transistor gate. Assuming that both blocking capacitors Cb are identical, the voltage drop across each of them is VI ∕2. These are usually large electrolytic capacitors with very large tolerances, for example, –20% and +100%; therefore, the voltage drops across them may be different from VI ∕2. To make these voltages closer to each other, large balance resistors Rb of the order of 100 kΩ to 1 MΩ may be connected in parallel with the blocking capacitors. 298 Pulse-Width Modulated DC–DC Power Converters If the front-end rectifier is a voltage doubler, its filter capacitors can be used as the blocking capacitors Cb . The dc current through the primary of the transformer is zero because of the blocking capacitors Cb . However, this property is lost if resistors are connected in parallel with the blocking capacitors Cb . The half-bridge converter may employ the following rectifiers: a transformer center-tapped rectifier shown in Figure 7.1(a), a bridge rectifier depicted in Figure 7.1(b), or a half-wave rectifier with a freewheeling diode shown in Figure 7.1(c). Full-wave rectifiers (i.e., center-tapped and bridge rectifiers) are more suitable because the voltage across the primary winding changes in both directions, from VI ∕2 to −VI ∕2. The transformer center-tapped rectifier consists of two diodes D1 and D2 , an inductor L, a filter capacitor C, and a load resistor RL . It is most suitable for low-voltage applications because only one diode conducts while it carries the entire inductor current. Schottky diodes or low on-resistance power MOSFETs can be used as rectifying devices. The voltage stress of the diodes is high, equal to VI ∕n, and makes the center-tapped rectifier unsuitable for high-voltage applications. In contrast, the bridge rectifier is suitable for high-voltage applications because the voltage stress of the diodes is low, equal to VI ∕(2n), which is half of that in the center-taped rectifier. This rectifier is not suitable for low-voltage applications because two diodes conduct at the same time and the total forward voltage across the two diodes becomes comparable with the output voltage. As a result, the efficiency is poor at a low output voltage VO . To eliminate the dc current through the primary winding, a nonelectrolytic coupling capacitor Cc (2–10 μF) may be connected in series with the primary winding, as shown in Figure 7.2. The voltage across Cc is the average voltage across the bottom switch which is equal to VI ∕2. For the ac component, the dc input source VI in the converter of Figure 7.1(a) behaves similar to a short circuit and the two blocking capacitors are connected in parallel, resulting in the converter circuit shown in Figure 7.2(a), where Cc = 2Cb . S1 Cc VI S2 n:1:1 D1 L VI + 2 C + VO RL D2 (a) n:1 L C RL + VO C RL + VO (b) n:1 L (c) Figure 7.2 Half-bridge converter with a single coupling capacitor Cc . (a) With a transformer center-tapped rectifier. (b) With a bridge rectifier. (c) With a half-wave rectifier. Half-Bridge PWM DC–DC Converter 299 7.2.2 Assumptions Analysis of the half-bridge PWM converter with a transformer center-tapped rectifier, shown in Figure 7.1(a), is based on the following assumptions: (1) The power MOSFETs and the diodes are ideal switches. (2) Capacitances and lead inductances of the transistors and the diodes are zero. (3) The transformer is modeled by an ideal transformer and its magnetizing inductance Lm . Leakage inductances and stray capacitances are neglected. (4) Passive components are linear, time invariant, and frequency independent. (5) The output impedance of the input voltage source VI is zero for both dc and ac components. 7.2.3 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch S1 and the diode D1 are on and the switch S2 and the diode D2 are off. An ideal equivalent circuit for this time interval is shown in Figure 7.3(a). The voltage across the switch S2 is vS2 = VI . (7.1) The voltage across the primary and the magnetizing inductance Lm is di V VI = I = Lm Lm . 2 2 dt Hence, the current through the magnetizing inductance Lm is ) t t( V VI 1 1 iLm = dt + iLm (0) = I t + iLm (0) vLm dt + iLm (0) = ∫ ∫ Lm 0 Lm 0 2 2Lm v1 = vLm = VI − (7.2) (7.3) where iLm (0) is the initial current through the magnetizing inductance Lm at t = 0; this current is negative. The peak-to-peak ripple current through Lm is ΔiLm = iLm (DT) − iLm (0) = VI DT DVI = . 2Lm 2fs Lm (7.4) Consequently, iLm (0) = − ΔiLm VD =− I , 2 4fs L (7.5) ΔiLm VD = I , 2 4fs L (7.6) iLm (DT) = and iLm = VI VD t− I . 2Lm 4fs L (7.7) Dmin VImax 2fs Lm(min) (7.8) Dmin VImax . 2fs ΔiLm(max) (7.9) From (7.4), ΔiLm(max) = from which Lm(min) = 300 Pulse-Width Modulated DC–DC Power Converters iS1 i1 VI VI 2 + vS2 Lm n:1:1 iLm + v1 i2 = iD1 L + vL C + v2 + v3 iL RL + VO + vD2 (a) + vS1 VI VI 2 i1 + vS2 Lm n:1:1 VI VI 2 i1 iS2 Lm L iL + vL C + v2 iLm + v1 RL + VO + v3 iD2 (b) + vS1 i2 = iD1 n:1:1 i2 + vD1 + v3 iL + vL C + v2 iLm + v1 L RL + VO i3 iD2 (c) + vS1 VI VI 2 + vS2 i1 Lm n:1:1 iLm + v1 (d) i2 = iD1 + v2 L + vL C iL RL + VO + v3 iD2 Figure 7.3 Equivalent circuit of the half-bridge converter with a transformer center-tapped rectifier for CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ T∕2. (c) For T∕2 < t ≤ T∕2 + DT. (d) For T∕2 + DT < t ≤ T. Half-Bridge PWM DC–DC Converter 301 Note that DVI = Dmin VImax = Dmax VImin is constant if the output voltage VO is held constant. The output voltages of the transformer are v 2 = v3 = V v1 = I. n 2n (7.10) The voltage across the diode D2 is VI V V − I = − I. (7.11) 2n 2n n The negative diode voltage keeps the diode reverse biased, as originally assumed. The voltage across the inductor L is given by vD2 = −v2 − v3 = − VI di − VO = L L . 2n dt Hence, one obtains the current through the inductor L vL = t 1 1 i2 = iD1 = iL = v dt + iL (0) = L ∫0 L L ∫0 t( VI ) − VO VI 2n − VO dt + iL (0) = t + iL (0) 2n L where iL (0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes ( ) VI DT − V O 2n + iL (0) iL (DT) = L and the peak-to-peak value of the current ripple through the inductor L is ( ( ) ) VI VI − V − V DT D V (0.5 − D) O O 2n 2n = = O ΔiL = iL (DT) − iL (0) = L fs L fs L (7.12) (7.13) (7.14) (7.15) where VI = nVO ∕D as will be shown shortly. The current through the primary of the transformer is V I − VO i (0) i2 2n i1 = = t+ L n nL n (7.16) and the current through the switch is iS1 = i1 + iLm = VI − VO 2n nL V I − VO VD i (0) V i (0) V t+ L + I t + iLm (0) = 2n t+ L + I t− I . n 2Lm nL n 2Lm 4fs L (7.17) Current and voltage waveforms in the half-bridge converter for CCM are depicted in Figure 7.4. 7.2.4 Time Interval: DT < t ≤ T∕2 Figure 7.3(b) shows an equivalent circuit of the converter for the time interval DT < t ≤ T∕2, during which both switches are off and both diodes are on. Assuming that the off-resistances of the switches are the same, the voltages across both switches are V vS1 = vS2 = I . (7.18) 2 As a result, the voltage across the primary winding and the magnetizing inductance Lm is v1 = vLm = Lm diLm = 0. dt (7.19) 302 Pulse-Width Modulated DC–DC Power Converters T 2 vGS1 0 vGS2 T T DT DT 0 0 t T vS1 0 0 vS2 VI 0 DT vLm VI DT VI 0 VI iLm Figure 7.4 t T 2 T T 2 T VI 2n L DT t DT 0 vD1 t T t DT T 2 t T t T t T t T t IO 2 T 2 T 2 VI n iD2 0 DT vD2 0 T T VO L 0 T VI 2 Lm T 2 VO 0 iD1 IO VI 2 T 2 T 2 2 t T 2 DT VO iL 2 Lm 0 0 IO DT iS2 VO VI VI 2 t t DT vL VI n DT T DT vGS2 0 t DT iS1 0 T 2 vGS1 t DT VI n T t Waveforms in the half-bridge converter with a transformer center-tapped rectifier for CCM. resulting in the current through the magnetizing inductance iLm = iLm (DT) = − VI D 4fs L (7.20) and the current through the primary i1 = −iLm = −iLm (DT) = VI D . 4fs L (7.21) The currents through both secondary windings are equal in magnitude, but flow in the opposite direction, resulting in zero magnetic flux; therefore, the voltages across the transformer secondary windings are v2 = v3 = 0. (7.22) Hence, both rectifier diodes are on. The voltage across the inductor L is vL = −VO = L diL dt (7.23) Half-Bridge PWM DC–DC Converter 303 and the inductor current is iL = t V 1 v dt + iL (DT) = − O (t − DT) + iL (DT). L ∫DT L L (7.24) Assuming that the rectifier circuit is symmetrical, the inductor current is divided equally between the diodes V i (DT) i . iD1 = iD2 = L = − O (t − DT) + L 2 2L 2 (7.25) 7.2.5 Time Interval: T∕2 < t ≤ T∕2 + DT Figure 7.3(c) shows an equivalent circuit of the converter for the time interval T∕2 < t ≤ T∕2 + DT, during which the switch S1 and the diode D1 are off and the switch S2 and the diode D2 are on. The voltage across the switch S1 is vS1 = VI . (7.26) The voltage across the primary and the magnetizing inductance Lm is v1 = vLm = 0 − di V VI = − I = Lm Lm 2 2 dt (7.27) and the current through the magnetizing inductance is iLm = t ) ) ( ) ( ) V ( V ( VD 1 T T T T vLm dt + iLm =− I t− + iLm =− I t− + I . ∫ Lm T∕2 2 2Lm 2 2 2Lm 2 4fs Lm (7.28) The voltages at the transformer secondaries are v 2 = v3 = V v1 =− I. n 2n (7.29) V V VI − I =− I. 2n 2n n (7.30) The voltage across the diode D1 is vD1 = v2 + v3 = − The voltage across the inductor L is vL = VI di − VO = L L . 2n dt (7.31) Hence, the current through the bottom transformer winding, the diode D2 , and the inductor L is obtained as VI t ) ( ) ( ) − VO ( T 1 T T 2n = t− + iL . iD2 = −i3 = iL = vL dt + iL L ∫T∕2 2 L 2 2 (7.32) Hence, the current through the primary is ( ) T VI ( ) iL 2 − V i3 iD2 O T 2n =− t− − . i1 = = − n n nL 2 n (7.33) 304 Pulse-Width Modulated DC–DC Power Converters The current through the switch S2 is iS2 = −i1 − iLm = = VI − VO ( 2n nL VI − VO ( 2n nL T t− 2 ) T t− 2 ( ) T 2 iL + n ( ) ) iL + + T 2 n + ) ( ) VI ( T T − iLm t− 2Lm 2 2 ) VI ( VD T − I . t− 2Lm 2 4fs Lm (7.34) 7.2.6 Time Interval: T∕2 + DT < t ≤ T An equivalent circuit of the converter for the time interval T∕2 + DT < t ≤ T is shown in Figure 7.3(d). Both switches are off and both diodes are on during this time interval. The equivalent circuit for this time interval is the same as that of Figure 7.3(b). Therefore, the analysis of the converter is the same as that given in Section 7.2.4. 7.2.7 Device Stresses The maximum value of the voltage of each switch is VSMmax = VImax (7.35) and the maximum peak current of each switch is ΔiLm(max) I Δi IDMmax ΔiLm(max) + = Omax + Lmax + . n 2 n 2n 2 The maximum peak value of the voltage across each diode in the transformer center-tapped rectifier is ISMmax = VDMmax = VImax n (7.36) (7.37) and in the full-bridge rectifier is VImax . (7.38) 2n The average value of the inductor current is equal to the dc output current IO . Hence, one arrives at the peak current of each diode Δi (7.39) IDMmax = IOmax + Lmax . 2 VDMmax = 7.2.8 DC Voltage Transfer Function of Lossless Half-Bridge Converter for CCM Referring to Figure 7.4, ( ) ) ( VI 1 − VO DT = VO −D T 2n 2 (7.40) resulting in the dc voltage transfer function of the lossless converter MVDC ≡ VO I D = I = VI IO n for 0 ≤ MVDC ≤ 1 . 2n D ≤ 0.5. (7.41) The range of MVDC is (7.42) Half-Bridge PWM DC–DC Converter 305 For the lossless converter, the output voltage VO is independent of the load resistance RL and depends only on the dc input voltage VI . Rearrangement of (7.41) gives VI = nVO ∕D. Hence, from (7.15), VO ( 12 − Dmin ) ΔiLmax = fs L . (7.43) The sensitivity of the output voltage with respect to the duty cycle is S≡ dVO V = I. dD n (7.44) IO n = . II D (7.45) The dc current transfer function is MIDC ≡ As D is increased from 0 to 0.5, MIDC decreases from ∞ to 2n. From (7.35), (7.36), and (7.41), the switch and the diode utilization in the half-bridge converter is characterized by the output-power capability cp ≡ PO V I nVO nVO = OO = = = D. VSM ISM VSM ISM VSM VI (7.46) As D is increased from 0 to 0.5, cp increases from 0 to 0.5. 7.2.9 Boundary Between CCM and DCM The waveform of the inductor current at the boundary between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) is shown in Figure 7.5 and is given by iL = − VO (t − DT) + iL (DT) L for DT < t ≤ T 2 (7.47) from which ( ) VO T 12 − D ( ) T =− + iL (DT) = 0. iL 2 L This gives the maximum peak value of the inductor current at the CCM/DCM boundary ( ) ( ) VO T 12 − Dmin VO 12 − Dmin ΔiLmax = = . Lmin fs Lmin iL VImax 2n L Δ iLmax VO VImin 2n L (7.49) VO IOB VO L 0 Figure 7.5 (7.48) DminT DmaxT T 2 t Waveforms of the inductor current in the half-bridge converter at the boundary between CCM and DCM. 306 Pulse-Width Modulated DC–DC Power Converters 0.5 0.4 0.3 O IOB /(V /2fs L) CCM DCM 0.2 0.1 0 0 0.1 0.2 D 0.3 0.4 0.5 Figure 7.6 Normalized load current IOB ∕(VO ∕2fs L) = (0.5 − D) as a function of duty cycle D at the boundary between CCM and DCM for the half-bridge converter. The dc output current at the boundary between CCM and DCM is ( ) VO 12 − Dmin VO ΔiLmax = = . IOmin = IOB = 2 2fs Lmin RLmax (7.50) Hence, the load resistance at the CCM/DCM boundary is RLB = VO 2fs L . = IOB 0.5 − D Thus, one obtains at the minimum value of the inductance L ( ) ( ) ( ) VImax VO 12 − Dmin RLmax 12 − Dmin Dmin 2n − VO Lmin = = = . 2fs IOmin 2fs 2fs IOmin (7.51) (7.52) Figures 7.6 and 7.7 show the normalized load current IOB ∕(VO ∕2fs L) = (0.5 − D) and the normalized load resistance RLB ∕(2fs L) = 1∕(0.5 − D) as functions of duty cycle D at the boundary between CCM and DCM for the half-bridge converter, respectively. 7.2.10 Ripple Voltage in Half-Bridge Converter for CCM The analysis of the ripple voltage for the half-bridge converter is similar to that of the buck converter. It can be shown that the ripple output voltage is equal to the ripple voltage across the ESR if } { Dmax 0.5 − Dmin , (7.53) C ≥ Cmin = max , 2rC fs 2rC fs Half-Bridge PWM DC–DC Converter 307 20 18 16 12 LB s R /(2f L) 14 10 DCM 8 6 4 CCM 2 0 0 0.1 0.2 D 0.3 0.4 0.5 Figure 7.7 Normalized load resistance RLB ∕(2fs L) as a function of duty cycle D at the boundary between CCM and DCM for the half-bridge converter. where Dmax ≤ 0.5. If condition (7.53) is satisfied, the peak-to-peak ripple output voltage Vr is expressed by Vr = rC ΔiLmax = rC VO (0.5 − Dmin ) . fs L (7.54) Setting Dmax = 0.5 or Dmin = 0, one obtains the worst case condition for the capacitance at which the ripple is determined by the ESR of the filter capacitor for any value of D C ≥ Cmin = 1 . 4rC fs (7.55) If condition (7.53) is not met, the peak-to-peak ripple output voltage Vr depends on the voltage across both the filter capacitance and the ESR. The maximum increase of the capacitor charge during each half of the cycle T is T ΔiLmax 2 ΔQ = 4 2 = TΔiLmax Δi = Lmax 16 16fs (7.56) resulting in the ripple voltage across the capacitance C VCpp = V (0.5 − Dmin ) 𝜋 2 VO (0.5 − Dmin )fo2 ΔQ ΔiLmax = = = O C 16fs C 16fs2 LC 4fs2 (7.57) √ where fo = 1∕(2𝜋 LC) is the corner frequency of the output low-pass filter. Hence, Cmin = (0.5 − Dmin )VO ΔiLmax = . 16fs VCpp 16fs2 LVCpp (7.58) 308 Pulse-Width Modulated DC–DC Power Converters The peak-to-peak ripple voltage across the ESR is rC VO (0.5 − Dmin ) . fs L (7.59) VO (0.5 − Dmin ) rC VO (0.5 − Dmin ) + . fs L 16fs2 LC (7.60) Vrcpp = rC ΔiLmax = The total ripple output voltage can be approximated by Vrpp ≈ VCpp + Vrcpp = 7.2.11 Power Losses and Efficiency of Half-Bridge Converter for CCM Figure 7.8 depicts an equivalent circuit of the half-bridge converter with parasitic components, where rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be determined assuming that the ripple of the inductor current is zero. Therefore, the inductor current can be approximated as iL ≈ IO . The current through the switch S1 can be expressed by { IO , for n iS1 = 0, for (7.61) 0 < t ≤ DT DT < t ≤ T. (7.62) The rms value of the switch S1 current is √ √ √ )2 DT DT ( I D I 1 1 O O i2S1 dt = dt = IS1rms = T ∫0 T ∫0 n n (7.63) and the conduction loss in the upper MOSFET is 2 PrDS1 = rDS1 IS1rms = DrDS1 IO2 n2 = DrDS1 P . n2 R L O (7.64) If the on-resistances of both the MOSFETs are identical, that is, rDS1 = rDS2 = rDS , the conduction losses in both the MOSFETs are the same, that is, PrDS1 = PrDS2 = PrDS . Assuming that the transistor output capacitance Co is linear, the switching loss per transistor is Psw = fs Co VI2 = VI rCb Cb iCb D2 = fs Co VO2 2 MVDC f C n2 R P fC R P = s o 2 L O = s o2 L O . D MVDC (7.65) iS1 Cb iCb fs Co n2 VO2 rDS rT1 iT1 iD1 n:1:1 rT2 RF VF rDS iL iC iS2 rCb L IO rL C rC RL + VO iD2 rT3 RF V F Figure 7.8 Equivalent circuit of the half-bridge converter with parasitic resistances to determine component losses. Half-Bridge PWM DC–DC Converter 309 Hence, one obtains the total power dissipation in each MOSFET (excluding the drive power) ) ( ) ( DrDS IO2 Psw DrDS fs Co n2 RL DrDS fs Co RL 1 2 = PO = PO . (7.66) + fs Co VI = + + PFET = PrDS + 2 2 2 n2 n2 R L 2D2 n2 RL 2MVDC The current through the bottom blocking capacitors is ⎧ IO ⎪ 2n , ⎪ 0, iCb ≈ ⎨ IO ⎪ − 2n , ⎪ 0, ⎩ 0 < t ≤ DT DT < t ≤ T∕2 T∕2 < t ≤ T∕2 + DT T∕2 + DT < t ≤ T. for for for for (7.67) Hence, the rms value of each blocking capacitor current is √ [ √ √ √ √ )2 )2 ] ) T DT ( T∕2+DT ( DT ( √1 IO D I I IO 2 1 2 O O √ 2 ICbrms = i dt = dt + dt = dt = . − ∫T∕2 T ∫0 Cb T ∫0 2n 2n T ∫0 2n n 2 (7.68) The power loss in the ESR rCb of each blocking capacitor is 2 PrCb = rCb ICbrms = rCb DIO2 2n2 = DrCb P . 2n2 RL O (7.69) The rms value of the current through the primary winding is √ [ √ √ ) ) ] T( DT ( T∕2+DT ( √1 ) IO 2 IO 2 1 √ 2 2 IrT1rms = dt + dt iS1 + iS2 dt = ∫T∕2 T ∫0 T ∫0 n n √ 2 T ∫0 = DT ( IO n )2 √ IO 2D dt = n (7.70) and the conduction loss in the primary winding resistance is 2 = PrT1 = rT1 IT1rms 2DrT1 IO2 2DrT1 P . n2 R L O (7.71) 0 < t ≤ DT DT < t ≤ T∕2 T∕2 < t ≤ T∕2 + DT T∕2 + DT < t ≤ T (7.72) n2 = The current through the diode D1 can be approximated by ⎧I , ⎪ IO ⎪ O, iD1 = ⎨ 2 0, ⎪ IO ⎪ 2, ⎩ leading to its rms value ID1rms = √ for for for for √ [ √ √ ) ] T DT T∕2 ( √1 IO 2D + 1 IO 2 1 √ 2 2 i dt = IO dt + 2 dt = ∫DT T ∫0 D1 T ∫0 2 2 (7.73) and the power loss in RF 2 PRF1 = RF ID1rms = (2D + 1)RF IO2 4 = (2D + 1)RF PO . 4RL (7.74) 310 Pulse-Width Modulated DC–DC Power Converters The average value of the diode current is ID(AV) = T I 1 iD1 dt = O T ∫0 2 (7.75) which gives the power loss associated with the voltage VF PVF1 = VF ID(AV) = VF IO V = F PO . 2 2VO (7.76) ] [ VF IO V (2D + 1)RF = + F PO . 2 4RL 2VO (7.77) Thus, the overall diode conduction loss is PD1 = PRF1 + PVF1 = (2D + 1)RF IO2 4 + The power loss in the secondary winding resistance rT2 is 2 = PrT2 = rT2 IDrms (2D + 1)rT2 IO2 4 = (2D + 1)rT2 PO . 4RL (7.78) If both secondary winding resistances rT2 and rT3 are equal, then the conduction losses in both output windings are the same, that is, PrT2 = PrT3 = PrT . The rms value of the inductor current is ILrms ≈ IO (7.79) and the inductor conduction loss 2 PrL = rL ILrms = rL IO2 = rL P . RL O (7.80) The current through the filter capacitor is ⎧ ΔiL ΔiL ⎪ DT t − 2 , Δi iC ≈ iL − IO = ⎨ − ( L ) (t − DT) + ΔiL , 1 2 −D T ⎪ 2 ⎩ for 0 < t ≤ DT for DT < t ≤ T∕2. Hence, using (7.43), one arrives at the rms value of the capacitor current ) ( √ 1 − D V T∕2 O Δi 2 1 i2C dt = √ L = √ ICrms = (T∕2) ∫0 12 12f L (7.81) (7.82) s and the power loss in the ESR of the filter capacitor )2 )2 ( ( rC VO2 12 − D rC RL 12 − D PO 2 r (Δi ) 2 PrC = rC ICrms = C L = = . 12 12fs2 L2 12fs2 L2 (7.83) The overall power loss is given by PLS = 2PrDS1 + 2Psw + PrT1 + 2PrCb + 2PrT2 + 2PD1 + PrL + PrC [2D(rDS + rT1 ) + DrCb ]IO2 (2D + 1)(RF + rT2 )IO2 rC (ΔiL )2 2 12 ( )2 ⎡ ⎤ 1 r R − D C L 2 rL ⎢ 2D(rDS + rT1 ) + DrCb 2fs Co RL (2D + 1)(RF + rT2 ) VF ⎥ + + + + + =⎢ ⎥ PO . 2 2 2 2 2R V R n RL 12fs L MVDC L O L ⎢ ⎥ ⎣ ⎦ = n2 + 2fs Co VI2 + + VF IO + rL IO2 + (7.84) Half-Bridge PWM DC–DC Converter 311 Thus, the converter efficiency is 𝜂= PO 1 = = P PO + PLS 1 + LS 1 ( )2 . rC RL 12 −D D[2(rDS +rT1 )+rCb ] 2fs Co RL (2D+1)(RF +rT2 ) VF rL 1+ + M2 + + V + R + 12f 2 L2 n2 RL 2RL O L s VDC PO (7.85) 7.2.12 DC Voltage Transfer Function of Lossy Converter for CCM Using (7.62), the dc component of the input current can be found as ) DT DT ( DI IO 1 1 dt = O . iS1 dt = II = T ∫0 T ∫0 n n (7.86) This produces the dc current transfer function of the half-bridge converter MIDC ≡ IO n = . II D (7.87) This equation is valid for both lossless and lossy converters. The converter efficiency can be expressed as 𝜂= PO V I nMVDC = O O = MVDC MIDC = PI VI II D (7.88) from which the voltage transfer function of the lossy half-bridge converter is MVDC = 𝜂 𝜂D = = MIDC n D [ n 2D(rDS +rT1 )+DrCb 1+ + n2 RL 2fs Co n2 RL D2 )2 ] . ( rC RL 12 −D (2D+1)(RF +rT2 ) VF rL + + V + R + 12f 2 L2 2RL O L s (7.89) Hence, one arrives at the on-duty cycle D= nVO nMVDC = . 𝜂 𝜂VI (7.90) The duty cycle D, at a given dc voltage transfer function, is greater for the lossy converter than for the lossless converter. The switches must be closed for a longer portion of the lossy converter period in order to transfer enough energy to be equal to the required output energy and the converter losses. Substitution of (7.90) into (7.85) gives the efficiency of the half-bridge converter 𝜂= N𝜂 (7.91) D𝜂 where nMVDC [2(rDS + rT1 ) + rCb ] nMVDC (RF + rT2 ) rC RL nMVDC − + RL n2 R L 12fs2 L2 {[ ]2 nMVDC [2(rDS + rT1 ) + rCb ] nMVDC (RF + rT2 ) rC RL nMVDC + + − −1 RL n2 R L 12fs2 L2 N𝜂 = 1 − − and 2 rC RL n2 MVDC 3fs2 L2 ( [ r R R + rT2 VF 2fs Co RL r + + + C 2 L2 1+ L + F 2 RL 2RL VO 48f MVDC sL r R r R + rT2 VF 2fs Co RL + + + C 2 L2 D𝜂 = 2 1 + L + F 2 RL 2RL VO 48f L MVDC s ]} 1 2 (7.92) ) . (7.93) 312 Pulse-Width Modulated DC–DC Power Converters 7.2.13 Design of Half-Bridge Converter for CCM √ Design a PWM√half-bridge converter operating in CCM to meet the following specifications: VInom = 2 × 110 = √ 156 V, VImin = 2 × 90 = 127 V, VImax = 2 × 132 = 187 V, VO = 5 V, IOmin = 4 A, IOmax = 40 A, and Vr ∕VO ≤ 1%. Solution: A half-bridge converter with a transformer center-tapped rectifier is selected for the design because the output voltage is low. The maximum and minimum values of the dc output power are POmax = VO IOmax = 5 × 40 = 200 W (7.94) POmin = VO IOmin = 5 × 4 = 20 W. (7.95) and The minimum and maximum values of the load resistance are V 5 = 0.125 Ω RLmin = O = IOmax 40 (7.96) and RLmax = VO IOmin = 5 = 1.25 Ω. 4 (7.97) The minimum, nominal, and maximum values of the dc voltage transfer function are MVDCmin = VO 5 1 = = 0.02674, = VImax 187 37.4 (7.98) MVDCnom = VO 1 5 = 0.03205 = , = VInom 156 31.2 (7.99) MVDCmax = VO 1 5 = 0.03937 = . = VImin 127 25.4 (7.100) and Assume the converter efficiency 𝜂 = 75% and the maximum duty cycle is Dmax ≈ 0.4. Hence, the transformer turns ratio is 𝜂Dmax 0.75 × 0.4 n= = = 7.62. (7.101) MVDCmax 0.03937 Pick n = 7. The minimum, nominal, and maximum values of the duty cycle are Dmin = nMVDCmin 7 × 0.02674 = = 0.2496 𝜂 0.75 (7.102) Dnom = nMVDCnom 7 × 0.03205 = = 0.299 𝜂 0.75 (7.103) Dmax = nMVDCmax 7 × 0.03937 = = 0.3674. 𝜂 0.75 (7.104) and Assume the switching frequency fs = 100 kHz. The minimum inductance required to maintain the converter in CCM is ) ( ( ) RLmax 12 − Dmin 1.25 × 12 − 0.2496 Lmin = = = 1.565 μH. (7.105) 2fs 2 × 105 Half-Bridge PWM DC–DC Converter 313 Let L = 20 μH. An inductance L much larger than Lmin was selected in order to reduce the ripple current through the inductor and thereby the filter capacitance. The maximum ripple of the inductor current is ( ) ( ) 5 × 12 − 0.2496 VO 12 − Dmin ΔiLmax = = = 0.626 A. (7.106) fs L 105 × 20 × 10−6 The ripple voltage is Vr = VO 5 = = 50 mV. 100 100 (7.107) If the filter capacitance is large enough, Vr = rCmax ΔiLmax and the maximum ESR of the filter capacitor is rCmax = Vr 50 × 10−3 = 79.87 mΩ. = ΔiLmax 0.626 (7.108) Pick rC = 50 mΩ. The minimum value of the filter capacitance at which the ripple voltage is determined by the ripple voltage across the ESR is { } { } 1 1 Dmax 2 − Dmin D 0.3674 0.3674 2 − 0.2496 Cmin = max , , = 36.74 μF. = max = max = 5 2fs rC 2fs rC 2fs rC 2fs rC 2fs rC 2 × 10 × 50 × 10−3 (7.109) Pick C = 47 μF/50 mΩ/16 V. The voltage and current stresses of the diodes are VDMmax = VImax 187 = = 26.7 V n 7 (7.110) and IDMmax = IOmax + ΔiLmax 0.626 = 40 + = 40.313 A. 2 2 (7.111) The maximum peak value of the current through the ideal transformer primary is I1max = IDMmax 40.313 = = 5.759 A. n 7 (7.112) The maximum peak-to-peak current through the magnetizing inductance should be limited to, say, 10% of I1max , which gives ΔiLm(max) = 0.1I1max = 0.1 × 5.759 = 0.1IDMmax = 0.576 A. n (7.113) From (7.9), the minimum magnetizing inductance is Lm(min) = Dmin VImax 0.2496 × 187 = = 405.2 μH. 2fs ΔiLm(max) 2 × 105 × 0.576 (7.114) The voltage and current stresses of the power MOSFETs are VSMmax = VImax = 187 V (7.115) and ISMmax = IDMmax ΔiLm(max) 40.313 0.576 + = + = 6.047 A. n 2 7 2 (7.116) 314 Pulse-Width Modulated DC–DC Power Converters International Rectifier IRF640 power MOSFETs are chosen, which have VDSS = 200 V, ISM = 18 A, rDS = 180 mΩ, Co = 100 pF, and Qg = 43 nF. MBR2545CT Schottky barrier diodes are selected, which have ID(AV)max = 30 A, IFSM = 300 A, VDM = 45 V, VF = 0.27 V, and RF = 13.25 mΩ. The conduction power loss in each MOSFET is 2 Dmax rDS IOmax 0.3674 × 0.18 × 402 = 2.159 W 72 (7.117) 2 Psw = fs Co VImax = 105 × 100 × 10−12 × 1872 = 0.35 W. (7.118) PrDS1 = = n2 the switching loss per transistor is Assuming that the winding resistance of the primary is rT1 = 20 mΩ and the winding resistances of the transformer on the secondaries are rT2 = rT3 = 5 mΩ, the conduction power losses are PrT1 = 2 2Dmax rT1 IOmax n2 = 2 × 0.3674 × 0.02 × 402 = 0.48 W 72 (7.119) and 2 (2Dmax + 1)rT2 IOmax (2 × 0.3674 + 1) × 0.005 × 402 = 3.47 W. 4 4 Assuming that rCb = 50 mΩ, the power loss in the ESR of each blocking capacitor is PrT2 = PrT3 = PrCb = 2 rCb Dmax IOmax 2n2 = (7.120) 0.05 × 0.3674 × 402 = 0.3 W. 2 × 72 (7.121) = The diode loss due to RF is PRF1 = 2 (2Dmax + 1)RF IOmax 4 = (2 × 0.3674 + 1) × 0.01325 × 402 = 9.194 W 4 (7.122) the diode loss due to VF is PVF1 = VF IOmax 0.27 × 40 = = 5.4 W 2 2 (7.123) and the conduction loss in each diode is PD1 = PRF1 + PVF1 = 9.194 + 5.4 = 14.594 W. (7.124) Assuming that the ESR of the inductor is rL = 10 mΩ, 2 PrL = rL IOmax = 0.01 × 402 = 16 W (7.125) and the power loss in the ESR of the capacitor is rC Δi2L 0.05 × 0.6262 = 1.6 mW. 12 12 Neglecting the MOSFET gate-drive power, the total power loss is PrC = = (7.126) PLS = 2PrDS + 2Psw + 2PrCb + PrT1 + 2PrT2 + 2PD1 + PrL + PrC = 2 × 2.159 + 2 × 0.35 + 2 × 0.3 + 0.48 + 2 × 3.47 + 2 × 14.594 + 16 + 0.002 = 58.228 W (7.127) and the efficiency of the converter is 𝜂= PO 200 = 77.45%. = PO + PLS 200 + 58.228 (7.128) Half-Bridge PWM DC–DC Converter 92 315 R = 1.25 Ω L 90 88 R = 0.25 Ω L η (%) 86 84 82 80 R = 0.125 Ω L 78 76 120 Figure 7.9 in CCM. 130 140 150 VI (V) 160 170 180 190 Efficiency 𝜂 as a function of dc input voltage VI at fixed load resistances RL for the half-bridge converter If the peak-to-peak gate-to-source voltage is VGSpp = 14 V, the gate drive power per transistor is PG = fs Qg VGSpp = 100 × 103 × 43 × 10−9 × 14 = 60.2 mW. (7.129) Figures 7.9 and 7.10 depict the efficiency 𝜂 and the duty cycle D versus the dc input voltage VI at fixed load resistances RL . Plots of the efficiency 𝜂 and the duty cycle D versus the dc load current IO at various dc input voltages VI are shown in Figures 7.11 and 7.12. Figures 7.13 and 7.14 illustrate the efficiency 𝜂 and the duty cycle D as functions of the dc load resistance RL at fixed dc input voltages VI . The efficiency 𝜂 decreases as IO increases (or RL decreases). The minimum efficiency 𝜂min occurs at IOmax and VImin . The duty cycle D increases as VI decreases and IO increases (or RL decreases). 7.3 DC Analysis of PWM Half-Bridge Converter for DCM 7.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch S1 and the diode D1 are on and the switch S2 and the diode D2 are off. The equivalent circuit is shown in Figure 7.15(a). The switch voltage vS1 and the diode current iD2 are zero. The voltage across the switch S2 is vS2 = VI . (7.130) The voltage across the primary and the magnetizing inductance is v1 = vLm = VI − di V VI = I = Lm Lm 2 2 dt (7.131) 316 Pulse-Width Modulated DC–DC Power Converters 0.36 0.34 0.32 RL = 0.25 Ω R = 0.125 Ω L D 0.3 0.28 0.26 RL = 1.25 Ω 0.24 0.22 0.2 120 130 140 150 V (V) 160 170 180 190 I Figure 7.10 in CCM. Duty cycle D as a function of dc input voltage VI at fixed load resistances for the half-bridge converter 92 90 88 η (%) 86 84 V I = 187 V 82 V = 127 V I 80 V I = 156 V 78 76 0 5 10 15 20 I (A) 25 30 35 40 O Figure 7.11 in CCM. Efficiency 𝜂 as a function of dc load current IO at fixed dc input voltages VI for the half-bridge converter Half-Bridge PWM DC–DC Converter 317 0.36 0.34 0.32 V I = 127 V D 0.3 0.28 0.26 V = 156 V I 0.24 0.22 0.2 Figure 7.12 in CCM. V I = 187 V 0 5 10 15 20 IO (A) 25 30 35 40 Duty cycle D as a function of dc load current IO at fixed dc input voltages VI for the half-bridge converter 92 V I = 127 V 90 V = 187 V V I = 156 V I 88 η (%) 86 84 82 80 78 76 0 0.2 0.4 0.6 R (Ω) 0.8 1 1.2 1.4 L Figure 7.13 in CCM. Efficiency 𝜂 as a function of load resistance RL at fixed dc input voltages VI for the half-bridge converter 318 Pulse-Width Modulated DC–DC Power Converters 0.36 0.34 0.32 V = 127 V I D 0.3 0.28 0.26 V = 156 V I 0.24 0.22 V = 187 V I 0.2 Figure 7.14 in CCM. 0 0.2 0.4 0.6 RL (Ω) 0.8 1 1.2 1.4 Duty cycle D as a function of load resistance RL at fixed dc input voltages VI for the half-bridge converter resulting in the current through the magnetizing inductance iLm = t V 1 vLm dt + iLm (0) = I t + iLm (0). Lm ∫0 2Lm (7.132) Hence, ΔiLm = iLm (DT) − iLm (0) = iLm (0) = − VI D 2fs Lm (7.133) ΔiLm VD =− I 2 4fs Lm (7.134) ΔiLm VD = I 2 4fs Lm (7.135) iLm (DT) = and iLm = VI VD t− I . 2Lm 4fs Lm (7.136) V v1 = I n 2n (7.137) V V VI − I =− I. 2n 2n n (7.138) The voltages at the output of the transformer are v 2 = v3 = which gives the voltage across the diode D2 vD2 = −v2 − v3 = − iS1 VI VI 2 iL i2 = iD1 i1 L n:1:1 + vS2 Lm + vL C + v2 iLm + v1 + v3 RL + VO + vD2 (a) + vS1 VI VI 2 i1 + vS2 Lm VI VI 2 Lm iL + vL C RL + VO + v3 iD2 i2 = iD1 i1 + vS 2 L + v2 iLm + v1 (b) + vS1 i2 = iD1 n:1:1 L n:1:1 + vL C + + vD1 v2 iLm + v1 + v3 iL RL + VO + vD2 iD2 (c) + vS1 VI VI 2 i1 iS2 Lm n:1:1 VI VI 2 + vS2 i1 + v3 Lm (e) L iL + vL C RL + VO iS1 iD2 n:1:1 iLm + v1 + vD1 + v2 iLm + v1 (d) + vS1 i2 i2 = iD1 + v2 L iL + vL C RL + VO + v3 iD2 Figure 7.15 Equivalent circuit of the half-bridge converter with a transformer center-tapped rectifier for DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ (D + D1 )T. (c) For (D + D1 )T < t ≤ T∕2. (d) For T∕2 < t ≤ T∕2 + DT. (e) For T∕2 + DT < t ≤ T∕2 + (D + D1 )T. 320 Pulse-Width Modulated DC–DC Power Converters The voltage across the inductor L is VI di − VO = L L , 2n dt vL = iL (0) = 0 (7.139) and the inductor and switch current is t 1 1 i2 = iD1 = iL = v dt = L ∫0 L L ∫0 Hence, the peak inductor current is ( ΔiL = iL (DT) = IDM1 = t( VI − VO 2n VI ) − VO VI 2n − VO dt = t. 2n L ( ) DT = L VI − VO 2n (7.140) ) fs L D . (7.141) The primary current is V I − VO i2 2n i1 = = t n nL (7.142) and the current through the upper switch is iS1 = i1 + iLm = VI − VO 2n V I − VO V V VD t + I t + iLm (0) = 2n t+ I t− I . 2Lm nL 2Lm 4fs Lm nL (7.143) The waveforms in the half-bridge converter for DCM are depicted in Figure 7.16. 7.3.2 Time Interval: DT < t ≤ (D + D1 )T The equivalent circuit for this time interval is shown in Figure 7.15(b). Both switches are off and both diodes are on. The voltages across the switches are VI 2 (7.144) v 1 = v2 = v3 = 0 (7.145) vS1 = vS2 = resulting in the transformer voltages the voltage across the primary and the magnetizing inductance diLm =0 dt (7.146) VI DT VD VD VD + iLm (0) = I − I = I 2Lm 2fs Lm 4fs Lm 4fs Lm (7.147) v1 = vLm = Lm the current through the magnetizing inductance iLm = iLm (DT) = and the current through the primary of the ideal transformer i1 = −iLm = −iLm (DT) = − VI D . 4fs Lm (7.148) The voltage across the inductor L is vL = −VO = L diL dt (7.149) Half-Bridge PWM DC–DC Converter vGS1 vGS1 T 2 0 vGS2 0 T t DT T VI 2n 0 vS1 0 iS2 VI VI 2 0 vLm VI 0 Figure 7.16 T VI 2Lm t T T t VI 2 T 2 VI 2 t T t T t VI 2Lm T 2 T t T 2 DT T Vo 0 Vo Io 0 T t t DT vL iL T VI 2 vS2 0 T 2 T 2 0 iLm t DT iS1 0 vGS2 0 321 T 2 VI V 2n o L T t T t T t Vo L T iD1 Io Io 2 0 vD1 0 VI n iD2 T 2 Vo 0 vD2 0 VI n T 2 T t T Vo t T t Waveforms in the half-bridge converter with a transformer center-tapped rectifier for DCM. and the inductor current is obtained using (7.141) t t V 1 1 vL dt + iL (DT) = (−VO )dt + iL (DT) = − O (t − DT) + iL (DT) L ∫DT L ∫DT L ( ) VI − VO DT VO 2n . = − (t − DT) + L L iL = (7.150) Therefore, the peak inductor current is found as VO D1 T . L (7.151) V i iD1 = iD2 = L = − O (t − DT) + iL (DT). 2 2L (7.152) ΔiL = iL (DT) − iL [(D + D1 )T] = The currents through the diodes are This time interval ends when the diode currents iD1 and iD2 reach zero. 322 Pulse-Width Modulated DC–DC Power Converters 7.3.3 Time Interval: (D + D1 )T < t ≤ T∕2 During this time interval, both switches S1 and S2 and both diodes D1 and D2 are off. The equivalent circuit is shown in Figure 7.15(c). The inductor current iL , the inductor voltage vL , the switch currents iS1 , iS2 and the diode currents iD1 , iD2 are zero. The voltages across the switches are VI 2 (7.153) v 1 = v2 = v3 = 0 (7.154) vD1 = vD2 = −VO . (7.155) vS1 = vS2 = the voltages across the transformer windings are and the voltages across the diodes are The voltage across the primary and the magnetizing inductance is diLm =0 dt (7.156) VI DT VD VD VD + iLm (0) = I − I = I 2Lm 2fs Lm 4fs Lm 4fs Lm (7.157) v1 = vLm = Lm the current through the magnetizing inductance is iLm = iLm (DT) = and the current through the primary of the ideal transformer is i1 = −iLm = −iLm (DT) = − VI D . 4fs Lm (7.158) This time ends when the switch S1 is turned on by the driver. The second half of the period is similar to the first one. 7.3.4 DC Voltage Transfer Function for DCM Referring to Figure 7.16 and using the volt-second balance, ( ) VI − VO DT = VO D1 T 2n (7.159) which yields MVDC = VO D . = VI 2n(D + D1 ) (7.160) From (7.141) and (7.160), the peak-to-peak inductor current is ) ( VI ( ) − VO DT V D 2n 1 ΔiL = = IDM = O −1 . L fs L 2nMVDC Using (7.160) and (7.161), IO = 1 (T∕2) ∫0 (D+D1 )T iL dt = (D + D1 )ΔiL = DVO (D + D1 ) fs L ( ) 1 −1 . 2nMVDC (7.161) (7.162) From (7.160), D + D1 = D∕(2nMVDC ). Substituting this into (7.162), one obtains IO = VO D2 (1 − 2nMVDC ) 2 4fs Ln2 MVDC = VO RL (7.163) Half-Bridge PWM DC–DC Converter which gives √ √ (2nMVDC )2 fs LIO = (1 − 2nMVDC )VO D= 323 (2nMVDC )2 fs L (1 − 2nMVDC )RL D≤ for 1 2fs L 1 2fs LIO − = − . 2 RL 2 VO (7.164) At the boundary between CCM and DCM, the dc voltage transfer function is the same as that in CCM and is given by MVDCB = DB . n (7.165) Substitution of this into (7.164) yields the duty cycle DB at the boundary DB = 1 2fs L 1 2fs LIO − = − . 2 RL 2 VO (7.166) Figures 7.17 and 7.18 show plots of D versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of nMVDC for both CCM and DCM for the lossless half-bridge converter. Rearrangement of (7.164) leads to fs L (2nMVDC )2 + 2nMVDC − 1 = 0 D2 RL (7.167) which yields MVDC = VO = VI 1 1 ) √ ( √ ) = ( 4f LI 4fs L n 1 + 1 + Ds2 V O n 1 + 1 + D2 R for D≤ 1 2fs L 1 2fs LIO − = − . 2 RL 2 VO (7.168) O L 0.6 nMVDC = 0.5 0.5 0.4 D 0.4 0.3 0.3 CCM 0.2 DCM 0.2 0.1 0.1 0 0 0.1 0.2 0.3 I /(V /2f L) O O 0.4 0.5 s Figure 7.17 Duty cycle D versus normalized load current IO ∕(VO ∕2fs L) at fixed values of nMVDC for CCM and DCM for the lossless half-bridge converter. 324 Pulse-Width Modulated DC–DC Power Converters 0.6 nM VDC 0.5 = 0.5 0.4 0.4 D CCM 0.3 0.3 DCM 0.2 0.2 0.1 0.1 0 0 10 1 2 10 R /(2f L) L 10 s Figure 7.18 Duty cycle D versus normalized load resistance RL ∕(2fs L) at fixed values of nMVDC for CCM and DCM for the lossless half-bridge converter. Notice that nMVDC strongly depends on D, RL , L, and fs for DCM. Figures 7.19 and 7.20 display nMVDC versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of D for both CCM and DCM for the lossless half-bridge converter. From (7.160) and (7.168), (√ ) ( ) 4fs L D 1 D1 = D −1 = 1+ 2 −1 2nMVDC 2 D RL ) (√ 4fs LIO 1 2f L 1 2f LI D 1+ 2 −1 for D ≤ − s = − s O . (7.169) = 2 2 RL 2 VO D VO The dc input current is II = 1 T ∫0 DT iI dt = 1 T ∫0 DT VI − VO 2n nL Hence, the dc input power is D2 VI PI = VI II = ( D2 tdt = VI − VO 2n 2nfs L ( VI − VO 2n 2nfs L ) . (7.170) ) . (7.171) The output power is PO = VO2 RL . (7.172) Half-Bridge PWM DC–DC Converter 325 0.6 D = 0.5 0.5 0.4 nMVDC 0.4 0.3 0.3 CCM 0.2 DCM 0.2 0.1 0.1 0 0 0.1 0.2 0.3 I /(V /2f L) O O 0.4 0.5 s Figure 7.19 DC voltage transfer function nMVDC versus normalized load current IO ∕(VO ∕2fs L) at fixed values of D for CCM and DCM for the lossless half-bridge converter. 0.6 0.5 nMVDC 0.4 D = 0.5 0.4 CCM 0.3 0.2 0.1 0 0 10 0.3 0.2 DCM 0.1 1 10 RL/(2fsL) 2 10 Figure 7.20 DC voltage transfer function nMVDC versus normalized load resistance RL ∕(2fs L) at fixed values of D for CCM and DCM for the lossless half-bridge converter. 326 Pulse-Width Modulated DC–DC Power Converters iL VImax 2n L VO Δ iLmin VImin 2n L IOB DminT 0 DmaxT VO VO L T 2 t Figure 7.21 Waveforms of the inductor current at the boundary between CCM and DCM in the half-bridge converter for VImin and VImax . Thus, the converter efficiency is (2nMVDC )2 fs L . D2 RL (1 − 2nMVDC ) Hence, one obtains the duty cycle for the lossy half-bridge converter in DCM √ √ (2nMVDC )2 fs L (2nMVDC )2 fs LIO 1 2f L 1 2f LI = for D ≤ − s = − s O D= 𝜂RL (1 − 2nMVDC ) 𝜂VO (1 − 2nMVDC ) 2 RL 2 VO 𝜂= and the voltage transfer function for the lossy half-bridge converter in DCM V 1 2fs L 1 2fs LIO 1 1 MVDC = O = ( = − . ) for D ≤ − ) = ( √ √ 4fs LIO 4fs L VI 2 RL 2 VO n 1 + 1 + 𝜂D2 V n 1 + 1 + 𝜂D2 R L (7.173) (7.174) (7.175) O 7.3.5 Maximum Inductance for DCM Figure 7.21 shows the waveforms of the inductor current at the boundary between CCM and DCM for VImin and VImax . The minimum peak value of the inductor current at the boundary occurs for VI = VImin , which corresponds to D = DBmax , and is described by ( ) VO 12 − DBmax . (7.176) ΔiLmin = fs Lmax The dc output current at the boundary is equal to the maximum output current given by ( ) VO 12 − DBmax V ΔiLmin = = O (7.177) IOmax = IOB = 2 2fs Lmax RLmin which yields ( ) ( ) RLmin 12 − DBmax VO 12 − DBmax = . (7.178) Lmax = 2fs 2fs IOmax 7.4 Summary r The PWM half-bridge converter is a step-down or a step-up converter. r The dc voltage transfer function of the lossless converter is M VDC = D∕n. r The voltage transfer function of the half-bridge converter is proportional to the duty cycle like in the buck converter; therefore, the converter belongs to the family of buck-derived converters. Half-Bridge PWM DC–DC Converter 327 r The maximum value of the duty cycle in the half-bridge converter is theoretically 50%. However, there must be a mandatory dead time when neither transistor conducts to avoid cross conduction. This implies that the duty cycle of the gate-to-source voltages should be slightly lower than 50%. r The transformer is not required to store energy in the half-bridge converter. r The transformer core utilization is excellent in the half-bridge converter because the dc current through the primary winding is zero and the primary is driven in both directions. r The voltage stress of the switches is low, equal to V ; therefore, the converter is used in off-line power Imax supplies. r The voltage stresses of the diodes are V ∕n for the transformer center-tapped rectifier and the half-wave Imax rectifier, and VImax ∕(2n) for the bridge rectifier. r The frequency of the waveforms in the output filter is twice the frequency of the MOSFET drivers. r The duty cycle D of the lossy converter is greater than that of the lossless converter at the same value of the dc voltage transfer function. r The peak-to-peak value of the inductor current ripple Δi is independent of the dc load current for CCM. L r The peak-to-peak value of the current through the filter capacitor C is relatively low; it is equal to the peak-topeak inductor current ripple ΔiL . r If the capacitance of the filter capacitor is sufficiently large, the output ripple voltage is determined only by the filter capacitor ESR and is independent of the filter capacitance. r The minimum value of the inductor is determined by the boundary between CCM and DCM, ripple voltage, or ac losses in the inductor and/or the filter capacitor. r The input current is pulsating. However, an input LC filter can be added at the converter input to obtain a nonpulsating input current waveform. √ r The corner frequency of the output filter f = 1∕(2𝜋 LC) is independent of the load resistance. o r It is relatively difficult to drive the upper transistor because the gate is not referenced to ground. Therefore, a transformer or an optocoupler is required to drive the circuit. References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. [3] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [4] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. [5] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [6] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood Cliffs, N J: Prentice Hall, 2004. [7] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [8] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [9] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, Mass.: Addison-Wesley, 1991. [10] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [11] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. [12] I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. Review Questions 7.1 Give an expression for the dc voltage transfer function of the lossless half-bridge converter. 7.2 What is the maximum value of the duty cycle of the half-bridge converter? 7.3 What happens when the duty cycle is too large in the half-bridge converter? 328 Pulse-Width Modulated DC–DC Power Converters 7.4 What is cross conduction? How would you prevent it? 7.5 Is the transformer required to store energy in the half-bridge converter? 7.6 What is the dc component of the current through the primary of the transformer in the half-bridge converter? 7.7 What is the total dc magnetic flux caused by the dc components of the diode currents in center-tapped, bridge, and half-wave rectifiers? 7.8 Is the input current of the basic half-bridge converter pulsating? 7.9 What are the voltage stresses of the switches in the half-bridge converter? 7.10 What are the voltage stresses of the diodes in the center-tapped, bridge, and half-wave rectifiers? 7.11 How can the circuit be changed to obtain a nonpulsating input current in the half-bridge converter? 7.12 Is the upper transistor driven with respect to ground in the half-bridge converter? 7.13 How is the dc voltage transfer function MVDC related to the duty cycle D of the lossless half-bridge converter for CCM? 7.14 Is the duty cycle D of the lossy half-bridge converter less than or greater than that of the lossless converter at a given value of MVDC for CCM? 7.15 Is the corner frequency of the output filter dependent on the load resistance? 7.16 How can the circuit of the half-bridge converter be modified to eliminate one blocking capacitor? 7.17 What are the best applications for a half-bridge converter with a transformer center-tapped rectifier? 7.18 What are the best applications for a half-bridge converter with a bridge rectifier? 7.19 Why is dead time required in the gate drive voltages of the half-bridge converter? 7.20 Is transformer core utilization good in the half-bridge converter? 7.21 Is the half-bridge converter a good candidate for applications in off-line power supplies? 7.22 Sketch the voltage waveform across the primary winding in the half-bridge converter. Problems 7.1 Derive an expression for the voltage stress of the diodes in the half-bridge PWM converter with a bridge rectifier. 7.2 The input voltage of a half-bridge PWM converter operating in CCM is the European single-phase rectified line voltage 220 Vrms ± 10% and VO = 12 V. Find the transformer turns ratio n, the minimum duty cycle Dmin , and the maximum duty cycle Dmax . 7.3 A half-bridge converter operating in CCM has VImax = 342 V and n = 9. Find the voltage stresses of the switches and the diodes. 7.4 A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 1–20 A, fs = 50 kHz and Dmin = 0.3424. Find the minimum inductance required to maintain the converter operation in CCM. 7.5 A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 1–20 A, L = 25 μH, n = 9, Dmin = 0.3424, Dmax = 0.4193, fs = 50 kHz, and Vr ∕VO < 2%. Find the minimum filter capacitance and the corner frequency of the output filter. Half-Bridge PWM DC–DC Converter 329 7.6 A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 1–20 A, L = 25 μH, n = 9, ΔiLmax = 1.513, and fs = 50 kHz. Determine the minimum magnetizing inductance at which its peak-to-peak current is less than 10% of the maximum peak current of the ideal transformer primary. 7.7 A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 0–20 A, n = 9, fs = 50 kHz, and Dmin = 0.3424. Find the maximum inductance required to maintain the converter operation in DCM. 7.8 Design a half-bridge converter operating in CCM to meet the following specifications: VI is the singlephase rectified European line voltage with Vrms is 220 V ± 10%, VO = 5 V, IOmin = 2 A, IOmax = 20 A, and Vr ∕VO ≤1%. Assume rDS = 1 Ω, rT1 = 150 mΩ, rT2 = rT3 = 40 mΩ, rL = 9 mΩ, rC = 35 mΩ, rCb = 350 mΩ, RF = 10 mΩ, VF = 0.3 V, and Co = 80 pF. Assume initially the converter efficiency 𝜂 = 85%. 7.9 Design a half-bridge converter whose VI is the single-phase rectified voltage 220 Vrms ± 10%, VO = 5 V, IO = 1–10 A, and Vr ∕VO ≤ 1%. Find L, C, Lm , rC , n, ISMmax , VSMmax , IDMmax , and VSMmax . 8 Full-Bridge PWM DC–DC Converter 8.1 Introduction The full-bridge PWM converter [1–12] contains two switching legs. Therefore, it draws two current pulses from the input voltage source per cycle of the transistor switching frequency and is capable of delivering more output power than the half-bridge converter. The voltage stresses of the switches are low and equal to the dc input voltage VI . For this reason, the full-bridge converter is used in off-line high-power supplies. This topology of the converter offers the highest power levels, from 500 W to 5 kW. The core is excited in both directions and is relatively small. Applications of the full-bridge converter include telecommunications and aerospace power supplies. The converter belongs to the family of buck-derived converters. This chapter describes, analyzes, and gives a design example of the full-bridge converter. 8.2 DC Analysis of PWM Full-Bridge Converter for CCM 8.2.1 Circuit Description A circuit of the PWM full-bridge dc–dc converter is depicted in Figure 8.1(a). It is composed of a PWM inverter and a PWM rectifier. The inverter consists of a transformer and four power MOSFETs used as controllable switches S1 , S2 , S3 , and S4 . The transistors in each switching leg are driven by nonoverlapping voltages that are out of phase by 180◦ . The maximum duty cycle of the gate-to-source voltages is slightly less than 50%. The waveforms of the gate-to-source voltages should be nonoverlapping to avoid the cross conduction. The switching part of the converter has a totem pole arrangement. Therefore, it is not easy to drive the upper transistors because their gates are not driven with respect to ground. Pulse transformers can be used to drive the upper transistors. The bottom transistors can also be driven by pulse transformers. Pulse transformers driving transistors S1 and S3 may be connected to one output of a control circuit. Similarly, pulse transformers driving transistors S2 and S4 may be connected to the second output of a control circuit. The two outputs of a control circuit provide nonoverlapping voltages, which are out of phase by 180◦ . The isolation transformer is not required to store energy. Its magnetizing inductance Lm should be Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 Full-Bridge PWM DC–DC Converter S1 S4 n:1:1 D1 331 L RL + VO C RL + VO C RL + VO C VI S2 S3 D2 (a) n:1 L (b) n:1 L (c) Figure 8.1 Full-bridge converter. (a) With a transformer center-tapped rectifier. (b) With a full-bridge rectifier. (c) With a half-wave rectifier. large enough to reduce the current through this inductance. On the other hand, if the magnetizing inductance is too large, it requires a large number of turns and is physically large. Ideally, the dc component of the current through the magnetizing inductance is zero. A coupling capacitor may be added in series with the primary winding to achieve zero dc component of the current through the magnetizing inductance and thereby removing an imbalance of the magnetic core. The full-bridge converter is well suited for high-power applications, usually from 0.5 kW to several kilowatts. It offers the highest power levels among all converters. In very high-power applications, insulated-gate bipolar transistors (IGBTs), thyristors, or MOSFET-controlled thyristors (MCTs) are used as switching devices. In addition, two or more power switching devices may be connected in parallel to increase current capability of every switch and output power levels. Three topologies can be used for the full-bridge converter: with a transformer center-tapped rectifier, with a full-bridge rectifier, or with a half-wave rectifier. The transformer center-tapped rectifier consists of two diodes D1 and D2 , an inductor L, a filter capacitor C, and a load resistor RL . IGBTs or MCTs can also be used. This rectifier is most suitable for low output voltage applications because only one diode conducts, when two switches are on. Schottky diodes or low on-resistance power MOSFETs can be used as rectifying devices. The voltage stress of the diodes is 2VI ∕n, which is higher than that in the bridge rectifier. Therefore, the transformer center-tapped rectifier is not suitable for high-voltage applications. The bridge rectifier is suitable for high output voltage applications because the voltage stress of the diodes is VI ∕n, which is half of the transformer center-tapped rectifier. This rectifier is not suitable for low-voltage applications because the two diodes conduct when the two switches are on, and the total forward voltage across the two diodes may become comparable with the output voltage, resulting in low efficiency. 332 Pulse-Width Modulated DC–DC Power Converters 8.2.2 Assumptions The analysis of the full-bridge PWM converter with a transformer center-tapped rectifier shown in Figure 8.1(a) is based upon the following assumptions: (1) The power MOSFETs and the diodes are ideal switches. (2) Transistor and diode capacitances as well as lead inductances are zero. (3) The transformer is modeled by an ideal transformer and its magnetizing inductance Lm . Leakage inductances and stray capacitances are neglected. (4) Passive components are linear, time invariant, and frequency independent. (5) The output impedance of the input voltage source VI is zero for both dc and ac components. 8.2.3 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switches S1 and S3 as well as the diode D1 are on, whereas the switches S2 and S4 as well as the diode D2 are off. An ideal equivalent circuit for this time interval is shown in Figure 8.2(a). The voltages across the switches S2 and S4 are vS2 = vS4 = VI . (8.1) The voltage across the primary winding and the magnetizing inductance Lm is v1 = vLm = VI = Lm diLm . dt (8.2) Hence, the current through the magnetizing inductance Lm is iLm = t t V 1 1 vLm dt + iLm (0) = VI dt + iLm (0) = I t + iLm (0), ∫ ∫ Lm 0 Lm 0 Lm (8.3) where iLm (0) is the initial current through the magnetizing inductance Lm at t = 0. This current is negative. The peak-to-peak ripple current of the magnetizing inductance is ΔiLm = iLm (DT) − iLm (0) = VI DT VD = I , Lm fs Lm (8.4) the current through the magnetizing inductance at t = 0 is iLm (0) = − ΔiLm VD =− I , 2 2fs Lm (8.5) and the current through the magnetizing inductance at t = DT is iLm (DT) = ΔiLm VD = I . 2 2fs Lm (8.6) The maximum value of the peak-to-peak ripple current of the magnetizing inductance is Dmin VImax fs Lm(min) (8.7) Dmin VImax . fs ΔiLm(max) (8.8) ΔiLm(max) = which gives the minimum magnetizing inductance Lm(min) = The voltages across the transformer secondary windings are v 2 = v3 = V v1 = I. n n (8.9) Full-Bridge PWM DC–DC Converter i1 + vS4 VI n:1:1 + v1 + vS4 VI n:1:1 + v1 n:1:1 Lm + v1 i1 VI Lm + vS2 n:1:1 iLm + v1 + vS3 (d) L RL + VO RL + VO iL + vL C i2 = iD1 (c) + vS4 + VO + v3 + vS3 + vS1 RL iL + vL C i2 = iD1 + v2 iLm VI L iD2 (b) i1 + VO + v3 + vS3 + vS1 i2 = iD1 + v2 iLm Lm + vS2 RL + vD2 (a) + vS1 iL + v3 + vS2 i1 L + vL C + v2 iLm Lm i2 = iD1 333 i2 = iD1 + v2 L iL + vL C + v3 iD2 Figure 8.2 Equivalent circuits of the full-bridge converter with a transformer center-tapped rectifier for CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ T∕2. (c) For T∕2 < t ≤ T∕2 + DT. (d) For T∕2 + DT < t ≤ T. The voltage across the diode D2 is vD2 = −v2 − v3 = − 2V VI VI − = − I. n n n (8.10) Since vD2 < 0, the diode D2 is off. The voltage across the inductor L is given by vL = VI di − VO = L L , n dt (8.11) 334 Pulse-Width Modulated DC–DC Power Converters resulting in the current through the inductor L t i2 = iD1 = iL = 1 1 v dt + iL (0) = L ∫0 L L ∫0 t( VI ) − VO VI − VO dt + iL (0) = n t + iL (0), n L where iL (0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes ) ( VI − VO DT n + iL (0) iL (DT) = L and the peak-to-peak value of the ripple current through the inductor L is ( ) VI − VO DT V (0.5 − D) n = O ΔiL = iL (DT) − iL (0) = L fs L (8.12) (8.13) (8.14) where VI = nVO ∕(2D) as will be shown shortly. The maximum value of the peak-to-peak ripple current through the inductor L is V (0.5 − Dmin ) ΔiLmax = O . (8.15) fs L The current through the primary winding of the ideal transformer is V I − VO i i (0) i i1 = 2 = L = n t+ L n n nL n (8.16) and the current through the switch is iS1 = iS3 = i1 + iLm = VI − VO n nL i (0) VI t+ L + t + iLm (0). n Lm (8.17) Figure 8.3 shows current and voltage waveforms in the full-bridge converter with a transformer center-tapped rectifier for CCM. 8.2.4 Time Interval: DT < t ≤ T∕2 Figure 8.2(b) shows an equivalent circuit of the converter for the time interval DT < t ≤ T∕2, during which all four switches are off and both diodes are on. Assuming that the off-resistances of the switches are same, the voltages across all the switches are V vS1 = vS2 = vS3 = vS4 = I . (8.18) 2 Therefore, the voltage across the primary winding and the magnetizing inductance Lm is diLm =0 dt which gives the current through the magnetizing inductance v1 = vLm = Lm iLm = iLm (DT) = VI D 2fs Lm (8.19) (8.20) and the current through the primary winding of the ideal transformer i1 = −iLm = −iLm (DT) = − VI D . 2fs Lm (8.21) Full-Bridge PWM DC–DC Converter T 2 vGS1, vGS3 0 vGS2, vGS4 0 T t iS1, iS3 T iS2, iS4 0 VI 0 t VO T 2 T t 0 iD1 IO t 0 vD1 VI 2 0 DT v1 = vLm VI 0 DT VI T 2 T 2 T T VI DT T 2 VI n L VO t 0 0 2VI t T t VO L DT T 2 T t T t T t T t IO 2 T 2 DT T 2 2VI n iD2 vD2 T T 2 DT 0 t VI Lm Lm 0 Figure 8.3 IO n t DT VO IO T T t DT vL iL T 2 DT vS2, vS4 vGS2, vGS4 0 VI VI 2 0 0 VI n DT vS1, vS3 iLm t DT IO n 0 T 2 vGS1, vGS3 DT 335 T 2 DT DT T t n Waveforms of the full-bridge converter with a transformer center-tapped rectifier for CCM. The voltages at the transformer outputs are v2 = v3 = 0. (8.22) The voltage across the inductor L is vL = −VO = L diL dt (8.23) and the inductor current is iL = t V 1 vL dt + iL (DT) = − O (t − DT) + iL (DT). L ∫DT L (8.24) Assuming that the rectifier circuit is symmetrical, the inductor current is divided equally between the diodes V i (DT) i . iD1 = iD2 = L = − O (t − DT) + L 2 2L 2 (8.25) 336 Pulse-Width Modulated DC–DC Power Converters 8.2.5 Time Interval: T∕2 < t ≤ T∕2 + DT Figure 8.2(c) shows an equivalent circuit of the converter for the time interval T∕2 < t ≤ T∕2 + DT, during which the switches S1 and S3 as well as the diode D1 are off, and the switches S2 and S4 as well as diode D2 are on. The voltages across the switches S1 and S3 are vS1 = vS3 = VI (8.26) and the voltage across the primary winding and the magnetizing inductance Lm is v1 = vLm = −VI = Lm diLm . dt (8.27) The current through the magnetizing inductance is t ) ) ( ) ( ) V ( V ( VD 1 T T T T =− I t− + iLm =− I t− + I vLm dt + iLm iLm = Lm ∫T∕2 2 Lm 2 2 Lm 2 2fs Lm (8.28) and the voltages at the output of the transformer are v 2 = v3 = V v1 =− I. n n (8.29) 2VI . n (8.30) The voltage across the diode D1 is vD1 = v2 + v3 = − The voltage across the inductor is expressed by VI di − VO = L L . n dt Hence, the current through the bottom transformer winding, the diode D2 , and the inductor L is vL = i3 = −iD2 = iL = t ( ) VI − V O ( ( ) ) T 1 T T = n t− + iL . vL dt + iL L ∫T∕2 2 L 2 2 Hence, the current through the primary winding is i i i1 = 3 = − D2 = − n n The current through the switches S2 and S4 is iS2 = iS4 = −i1 − iLm = = VI − VO ( n nL t− VI − VO ( n nL VI − VO ( n T t− 2 nL T 2 T t− 2 iL + ) n ( ) iL + T 2 T 2 n (8.32) ( ) ) iL − ( ) ) (8.31) T 2 n . + ) ( ) VI ( T T − iLm t− Lm 2 2 + ) VI ( VD T t− − I . Lm 2 2fs Lm (8.33) (8.34) 8.2.6 Time Interval: T∕2 + DT < t ≤ T An equivalent circuit of the converter for the time interval T∕2 + DT < t ≤ T is shown in Figure 8.2(d). All switches are off and both diodes are on during this time interval. The equivalent circuit of Figure 8.2(d) is the same as that of Figure 8.2(b). Consequently, the analysis of the converter is the same as that in Section 8.2.4. Full-Bridge PWM DC–DC Converter 337 8.2.7 Device Stresses The maximum peak value of the voltage across each switch is VSMmax = VImax (8.35) and the maximum peak value of the current through each switch is IOmax ΔiLmax ΔiLm(max) + + . n 2n 2 The maximum peak value of the voltage across each diode of the transformer center-tapped rectifier is ISMmax = 2VImax n and the maximum peak value of the voltage across each diode of the full-bridge rectifier is VDMmax = (8.36) (8.37) VImax . (8.38) n The average value of the inductor current is equal to the dc output current IO . Hence, the maximum peak value of each diode is given by VDMmax = IDMmax = IOmax + ΔiLmax . 2 (8.39) 8.2.8 DC Voltage Transfer Function of Lossless Full-Wave Converter for CCM Referring to Figure 8.3, ( ) ) ( VI 1 − VO DT = VO −D T n 2 (8.40) resulting in the dc voltage transfer function of the lossless converter MVDC ≡ VO I 2D = I = VI IO n for D ≤ 0.5. (8.41) The range of MVDC is 1 . (8.42) n For the lossless converter, the output voltage VO is independent of the load resistance RL and depends only on the dc input voltage VI . The sensitivity of the output voltage with respect to the duty cycle is 0 ≤ MVDC ≤ S≡ dVO 2VI = . dD n (8.43) IO n = . II 2D (8.44) The dc current transfer function is MIDC ≡ As D is increased from 0 to 0.5, MIDC decreases from ∞ to n. From (8.41), one obtains VI = nVO ∕(2D). Substitution of VI into (8.14) gives ΔiL = VO ( 12 − D) fs L . (8.45) 338 Pulse-Width Modulated DC–DC Power Converters iL VImax n L Δ i Lmax VO V Imin n VO L VO IOB L Dmin T 0 Figure 8.4 Dmax T T 2 t Waveforms of the inductor current in the full-bridge converter at the boundary between CCM and DCM. From (8.35), (8.36), and (8.41), IO ∕ISM ≈ n and VO ∕VSM = VO ∕VI = 2D∕n. Hence, the switch utilization in the full-bridge converter, characterized by the output-power capability, is given by cp ≡ PO V I nVO nVO = OO ≈ = = 2D. VSM ISM VSM ISM VSM VI (8.46) As D is increased from 0 to 0.5, cp increases from 0 to 1. 8.2.9 Boundary Between CCM and DCM The waveform of the inductor current at the boundary between CCM and DCM is shown in Figure 8.4 and is given by iL = − VO (t − DT) + iL (DT) L for DT < t ≤ T 2 (8.47) which produces ( ) VO T 12 − D ( ) T =− + iL (DT) = 0. iL 2 L Hence, one obtains the maximum peak value of the inductor current at the CCM/DCM boundary ) ( ) ( VO T 12 − Dmin VO 12 − Dmin = . ΔiLmax = iLmax (DT) = Lmin fs Lmin The dc output current at the boundary between CCM and DCM is ( ) VO 12 − Dmin VO ΔiLmax = = . IOB = IOmin = 2 2fs Lmin RLmax (8.48) (8.49) (8.50) Hence, the load resistance at the boundary between CCM and DCM is RLB = VO 2fs L . = IOB 0.5 − D (8.51) The minimum value of the inductance L required to maintain the converter operation in CCM is then expressed by ( ) ( ) ( ) V − V VO 12 − Dmin RLmax 12 − Dmin Dmin Imax O n Lmin = = = . (8.52) 2fs IOmin 2fs 2fs IOmin Full-Bridge PWM DC–DC Converter 339 0.5 0.4 0.3 I OB O s /(V /2f L) CCM DCM 0.2 0.1 0 0 0.1 0.2 D 0.3 0.4 0.5 Figure 8.5 Normalized load current IOB ∕(VO ∕2fs L) as function of duty cycle D at the boundary between CCM and DCM for the full-bridge converter. Figures 8.5 and 8.6 show the normalized load current IOB ∕(VO ∕2fs L) = 0.5 − D and the load resistance RLB ∕ (2fs L) = 1∕(0.5 − D) at the boundary between CCM and DCM as functions of the duty cycle D, respectively. 8.2.10 Ripple Voltage in Full-Bridge Converter for CCM An analysis similar to that of the buck converter reveals that the peak-to-peak output ripple voltage is equal to the peak-to-peak ripple voltage across the ESR if { } Dmax 0.5 − Dmin C ≥ Cmin = max , (8.53) 2rC fs 2rC fs where Dmax ≤ 0.5. This condition is satisfied at any duty cycle D ≤ 0.5 if C ≥ Cmin = 1 . 4rC fs (8.54) If condition (8.53) is met, the peak-to-peak output ripple voltage Vr is independent of the filter capacitance C and is determined by the ripple voltage across the ESR. Thus, Vr = rC ΔiLmax = rC VO (0.5 − Dmin ) . fs L (8.55) If condition (8.53) is not met, the peak-to-peak output ripple voltage is determined by both the voltage across the capacitance and the ESR. The maximum change of charge stored in the capacitor is ) ( ) ( ) ( Δi TΔiLmax Δi 1 T Lmax ΔQ = = = Lmax . (8.56) 2 4 2 16 16fs 340 Pulse-Width Modulated DC–DC Power Converters 20 18 16 12 s RLB /(2f L) 14 10 DCM 8 6 4 CCM 2 0 0 0.1 0.2 D 0.3 0.4 0.5 Figure 8.6 Normalized load resistance RLB ∕(2fs L) as function of duty cycle D at the boundary between CCM and DCM for the full-bridge converter. Hence, VCpp = V (0.5 − Dmin ) (0.5 − Dmin )fo2 ΔiLmax ΔQ = = O 2 = , C 16fs Cmin 16fs LCmin 16fs2 (8.57) V (0.5 − Dmin ) ΔiLmax = O 2 . 16fs VCpp 16fs LVCpp (8.58) rC VO (0.5 − Dmin ) . fs L (8.59) VO (0.5 − Dmin ) rC VO (0.5 − Dmin ) . + fs L 16fs2 LC (8.60) which gives Cmin = The ripple voltage across the ESR is Vrcpp = rC ΔiLmax = The output ripple voltage is approximately equal to Vr ≈ VCpp + Vrcpp = 8.2.11 Power Losses and Efficiency of Full-Bridge Converter for CCM Figure 8.7 depicts an equivalent circuit of the full-bridge converter with parasitic resistances, where rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be determined by assuming that the ripple of the inductor current is zero. Therefore, the inductor current can be approximated as iL ≈ IO . (8.61) Full-Bridge PWM DC–DC Converter iS4 iS1 VI rDS rDS iD1 iT 1 iL rCC rT 1 n:1:1 rT 2 RF VF CC iS3 iS2 rDS iC rDS IO rL L C rC 341 RL + VO iD2 rT 3 RF V F Figure 8.7 Equivalent circuit of the full-bridge converter with parasitic resistances to determine component losses. In the full-bridge converter, the duty cycle D must be less than 0.5. Assume that the peak value of the magnetizing current iLm is much lower than the peak value of the switch current. The current through the switches S1 and S3 can be expressed by { IO , for 0 < t ≤ DT (8.62) iS1 = iS3 = n 0, for DT < t ≤ T∕2. The rms value of the switches S1 and S3 is √ IS1rms = IS3rms = √ T 1 i2 dt = T ∫0 S1 1 T ∫0 DT ( IO n )2 √ IO D . dt = n (8.63) Similarly, the current through the switches S2 and S4 can be approximated by ⎧0, ⎪I iS2 = iS4 = ⎨ nO , ⎪0, ⎩ for 0 < t ≤ T∕2 for T∕2 < t ≤ T∕2 + DT for T∕2 + DT < t ≤ T. The rms value of the switches S2 and S4 is √ √ √ )2 T T∕2+DT ( I D I 1 1 O O . i2 dt = dt = IS2rms = IS4rms = T ∫0 S2 T ∫T∕2 n n (8.64) (8.65) The conduction power loss in each MOSFET is 2 PrDS1 = rDS IS1rms = DrDS IO2 n2 = DrDS P . n2 R L O (8.66) Assuming that the transistor output capacitance Co is linear, the switching loss per transistor is Psw = fs Co VI2 = fs Co n2 VO2 4D2 = fs Co VO2 2 MVDC f C n2 R fC R = s o 2 L PO = s 2o L PO . 4D MVDC The total power dissipation in each MOSFET (excluding the MOSFET drive power) is given by ) ( ) ( DrDS IO2 fs CVI2 Psw DrDS fs Co n2 RL DrDS fs Co RL PO = = = PO . + + + PFET = PrDS + 2 2 2 n2 n2 R L 8D2 n2 RL 2MVDC (8.67) (8.68) 342 Pulse-Width Modulated DC–DC Power Converters The current through the primary winding resistance rT1 is ⎧ IO ⎪n, ⎪0, irT1 = ⎨ IO ⎪n, ⎪0, ⎩ for for for for 0 < t ≤ DT DT < t ≤ T∕2 T∕2 < t ≤ T∕2 + DT T∕2 + DT < t ≤ T. (8.69) Hence, the rms value of the current through the primary winding resistance is √ [ √ √ √ √ )2 )2 ] ) T DT ( T∕2+DT ( DT ( √ IO 2D I I IO 2 1 1 2 O O √ 2 . i dt = dt + dt = dt = IrT1rms = ∫T∕2 T ∫0 rT1 T ∫0 n n T ∫0 n n (8.70) Thus, the conduction loss in the primary winding resistance rT1 is 2DrT1 IO2 2 = PrT1 = rT1 IrT1rms n2 = 2DrT1 P . n2 R L O (8.71) The conduction loss in the coupling capacitance resistance rcc is 2 Prcc = rcc Irc rms = 2Drcc IO2 2Drcc PO . (8.72) 0 < t ≤ DT DT < t ≤ T∕2 T∕2 < t ≤ T∕2 + DT T∕2 + DT < t ≤ T (8.73) n2 c = n2 R L The current of the diode D1 can be approximated by ⎧I , ⎪ IO ⎪ O, iD1 = ⎨ 2 0, ⎪ IO ⎪2, ⎩ leading to its rms value ID1rms = √ for for for for √ [ √ √ )2 ] T DT T∕2 ( √1 I IO 2D + 1 1 O √ 2 2 i dt = IO dt + 2 dt = ∫DT T ∫0 D1 T ∫0 2 2 (8.74) and the power loss in RF in each diode 2 = PRF1 = RF ID1rms (2D + 1)RF IO2 4 = (2D + 1)RF PO . 4RL (8.75) The average value of the diode current is ID = T I 1 i dt = O , T ∫0 D1 2 (8.76) which gives the power loss associated with the voltage VF in each diode PVF1 = VF ID = VF IO V = F PO . 2 2VO Thus, the overall conduction loss in each diode is PD1 = PRF1 + PVF1 = (2D + 1)RF IO2 4 + [ ] VF IO V (2D + 1)RF = + F PO . 2 4RL 2VO (8.77) (8.78) Full-Bridge PWM DC–DC Converter 343 Ideally, the current through the diode D2 is equal to the current through the diode D1 . Assuming that the diode D2 is the same as the diode D1 , the power loss in the diode D2 is the same as that in the diode D1 . The current through the upper secondary winding is equal to that through the diode D1 . Consequently, the power loss in the upper secondary winding resistance rT2 is 2 PrT2 = rT2 ID1rms = (2D + 1)rT2 IO2 4 = (2D + 1)rT2 PO . 4RL (8.79) The power loss in the bottom secondary winding resistance is PrT3 = PrT2 . The rms value of the inductor current is approximately equal to ILrms ≈ IO , (8.80) which gives the inductor conduction loss 2 = rL IO2 = PrL = rL ILrms rL P . RL O (8.81) The current through the filter capacitor is ⎧ ΔiL ΔiL for ⎪ DT t − 2 , Δi iC ≈ iL − IO = ⎨− ( L ) (t − DT) + ΔiL , for 2 ⎪ 12 −D T ⎩ 0 < t ≤ DT DT < t ≤ T∕2. (8.82) Hence, using (8.45), one obtains the rms value of the capacitor current √ 1 (T∕2) ∫0 ICrms = T∕2 VO ( 1 − D) Δi i2C dt = √ L = √ 2 12 12fs L (8.83) and the power loss in the filter capacitor rC RL ( 12 − D)2 rC VO2 ( 12 − D)2 rC (ΔiL )2 2 PrC = rC ICrms = = PO . = 12 12fs2 L2 12fs2 L2 (8.84) The overall power loss is given by PLS = 4PrDS1 + 4Psw + Prcc + PrT1 + 2PrT2 + 2PD1 + PrL + PrC = DIO2 (4rDS + 2rcc + 2rT1 ) n2 [ = D(4rDS + 2rcc + 2rT1 ) n2 R L + 4fs Co VI2 + + 4fs Co RL 2 MVDC + (2D + 1)(RF + rT2 )IO2 2 + VF IO + rL IO2 + rC (ΔiL )2 12 rC RL ( 12 − D)2 ] (2D + 1)(RF + rT2 ) VF r PO . + + L + 2RL VO RL 12fs2 L2 (8.85) Thus, the converter efficiency is 𝜂= PO 1 = = P PO + PLS 1 + LS PO 1 1+ D(4rDS +2rcc +2rT1 ) n2 RL 4f C R + Ms 2 o L + VDC rC RL ( 1 −D)2 (2D+1)(RF +rT2 ) V r + VF + RL + 12f 22 L2 2RL O L s . (8.86) 344 Pulse-Width Modulated DC–DC Power Converters 8.2.12 DC Voltage Transfer Function of Lossy Converter for CCM Neglecting the magnetizing current iLm , the input current of the converter can be approximated by ⎧ IO ⎪n, ⎪0, iI ≈ iS1 + iS4 = ⎨ IO ⎪n, ⎪0, ⎩ for for for for 0 < t ≤ DT DT < t ≤ T∕2 T∕2 < t ≤ T∕2 + DT T∕2 + DT < t ≤ T. Hence, the dc component of the input current is II = 1 (T∕2) ∫0 DT iS1 dt = 2 T ∫0 DT ( IO n ) dt = (8.87) 2DIO n (8.88) leading to the dc current transfer function of the full-bridge converter MIDC ≡ IO n . = II 2D (8.89) This equation is valid for both lossless and lossy converters. The converter efficiency can be expressed as 𝜂= PO V I nMVDC = O O = MVDC MIDC = PI VI II 2D (8.90) from which the voltage transfer function of the lossy full-bridge converter is MVDC = 𝜂 2𝜂D = = MIDC n 2D [ n 1+ D(4rDS +2rcc +2rT1 ) n2 RL rC RL ( 12 −D)2 4f C n2 R (2D+1)(RF +rT2 ) VF rL + s Do 2 L + + + + 2RL VO RL 12fs2 L2 ]. (8.91) From (8.91), the on-duty cycle is D= nVO nMVDC = . 2𝜂 2𝜂VI (8.92) The duty cycle D at a given dc voltage transfer function is greater for the lossy converter than that for the lossless converter. Substitution of (8.92) to (8.86) yields the efficiency of the full-bridge converter 𝜂= where N𝜂 (8.93) D𝜂 ( ) rC RL nMVDC nMVDC 4rDS + 2rcc + 2rT1 + R + r F T2 + 2 2RL n 24fs2 L2 {[ ( ) ]2 4rDS + 2rcc + 2rT1 rC RL nMVDC nMVDC RF + rT2 + − + −1 2RL n2 24fs2 L2 N𝜂 = 1 − − and 2 rC RL n2 MVDC 12fs2 L2 ( [ r R R + rT2 VF 4fs Co RL r + + + C 2 L2 1+ L + F 2 RL 2RL VO 48f MVDC sL r R r V R + rT2 4fs Co RL D𝜂 = 2 1 + L + F + F + + C 2 L2 2 RL VO 2RL 48f L MVDC s ]} 1 2 (8.94) ) . (8.95) Full-Bridge PWM DC–DC Converter 345 8.2.13 Design of Full-Bridge Converter for CCM √ Design a PWM √ full-bridge converter operating √in CCM to meet the following specifications: VInom = 2 × 220 = 311 V, VImin = 2 × 200 = 283 V, VImax = 2 × 240 = 340 V, VO = 48 V, IOmin = 2.5 A, IOmax = 25 A, and Vr ∕VO ≤ 1%. Solution: A full-bridge converter with a transformer center-tapped rectifier is selected for the design because the output voltage is low. The maximum and minimum values of the dc output power are POmax = VO IOmax = 48 × 25 = 1200 W (8.96) POmin = VO IOmin = 48 × 2.5 = 120 W. (8.97) and The minimum and maximum values of the load resistance are RLmin = VO IOmax = 48 = 1.92 Ω 25 (8.98) = 48 = 19.2 Ω. 2.5 (8.99) and RLmax = VO IOmin The minimum, nominal, and maximum values of the dc voltage transfer function are MVDCmin = VO 1 48 = 0.1412 = = VImax 340 7.083 (8.100) MVDCnom = VO 1 48 = 0.1543 = = VInom 311 6.479 (8.101) MVDCmax = VO 1 48 = 0.1696 = . = VImin 283 5.896 (8.102) and Let us assume the converter efficiency 𝜂 = 85% and the maximum duty cycle Dmax ≈ 0.4 < 0.5. Hence, the transformer turns ratio is n= 2𝜂Dmax 2 × 0.85 × 0.4 = 4.01. = MVDCmax 0.1696 (8.103) Let n = 4. The minimum, nominal, and maximum values of the duty cycle are Dmin = nMVDCmin 4 × 0.1412 = = 0.3322 2𝜂 2 × 0.85 (8.104) Dnom = nMVDCnom 4 × 0.1543 = = 0.3631 2𝜂 2 × 0.85 (8.105) Dmax = nMVDCmax 4 × 0.1696 = = 0.3991. 2𝜂 2 × 0.85 (8.106) and 346 Pulse-Width Modulated DC–DC Power Converters Assume the switching frequency fs = 50 kHz. The minimum inductance required to maintain the converter operation in CCM is ( ) ( ) RLmax 12 − Dmin 19.2 × 12 − 0.3322 = = 32.2 μH. (8.107) Lmin = 2fs 2 × 50 × 103 Pick L = 40 μH. The maximum ripple of the inductor current is ( ) ( ) 48 × 12 − 0.3322 VO 12 − Dmin ΔiLmax = = = 4.027 A. fs L 50 × 103 × 40 × 10−6 (8.108) The ripple voltage is VO 48 = = 480 mV. (8.109) 100 100 If the filter capacitance is large enough, Vr = rCmax ΔiLmax . Hence, the maximum ESR of the filter capacitor is Vr = rCmax = Vr 480 × 10−3 = 119.16 mΩ. = ΔiLmax 4.027 (8.110) Pick a capacitor with rC = 100 mΩ. The minimum value of the filter capacitance at which the ripple voltage is determined by the ripple voltage across the ESR is { } { } 1 1 Dmax 2 − Dmin D 0.3991 0.3991 2 − 0.3322 = 39.91 μF. Cmin = max , , = max = max = 2fs rC 2fs rC 2fs rC 2fs rC 2fs rC 2 × 50 × 103 × 0.1 (8.111) Pick C = 50 μF/100 V/100 mΩ. The corner frequency is fo = 1 1 = 3.559 kHz. = √ √ −6 2𝜋 LC 2𝜋 40 × 10 × 50 × 10−6 (8.112) Since i1 = iD1 ∕n, the maximum peak current through the ideal transformer primary winding is IOmax ΔiLmax 25 4.027 + = + = 6.25 + 0.503 = 6.753 A. (8.113) n 2n 4 2×4 Let us assume that the maximum peak-to-peak value of the magnetizing current is less than 10% of I1max . Thus, the maximum peak of the magnetizing inductance current is I1max = ΔiLm(max) = 0.1I1max = 0.1 × 6.753 = 0.6753 A. (8.114) Hence, the minimum magnetizing inductance is Lm(min) = Dmin VImax 0.3322 × 340 = 3.345 mH. = fs ΔiLm(max) 50 × 103 × 0.6753 (8.115) Pick Lm = 3.5 mH. The voltage and current stresses of the power MOSFETs are VSMmax = VImax = 340 V (8.116) and ISMmax = IOmax ΔiLmax ΔiLm(max) 25 4.027 0.6753 + + = + + = 6.25 + 0.503 + 0.338 = 7.091 A. n 2n 2 4 2×4 2 (8.117) Full-Bridge PWM DC–DC Converter 347 The voltage stress of the diodes in the transformer center-tapped rectifier is VDMmax = 2VImax 2 × 340 = = 170 V n 4 (8.118) ΔiLmax 4.027 = 25 + = 27.014 A. 2 2 (8.119) and the current stress of the diodes is IDMmax = IOmax + MTM15N40 power MOSFETs are selected, which have VDSS = 400 V, ISM = 15 A of continuous current, rDS = 300 mΩ, Qg = 110 nC, and Co = 100 pF. MR866 fast recovery diodes are selected, which have ID(AV)max = 40 A, IFSM = 350 A, VDM = 600 V, VF = 0.7 V, and RF = 12.5 mΩ. The power losses and the efficiency will be calculated at the maximum load current IOmax = 25 A and the minimum dc input voltage VImin = 283 V. The conduction power loss in each MOSFET is PrDS1 = 2 Dmax rDS IOmax = n2 0.3991 × 0.3 × 252 = 4.68 W. 42 (8.120) The switching power loss per transistor is 2 = 50 × 103 × 100 × 10−12 × 2832 = 0.4 W. Psw = fs Co VImin (8.121) Hence, the total power loss in each transistor is Psw 0.4 = 4.68 + = 4.88 W. 2 2 PMOS = PrDS1 + (8.122) Assume that the winding resistance of the primary winding is rT1 = 25 mΩ and the winding resistances of the transformer on the secondary side are rT2 = rT3 = 10 mΩ, the conduction power losses in these resistances are Prcc = PrT1 = 2 2Dmax rcc IOmax n2 2 2Dmax rT1 IOmax n2 = 2 × 0.3991 × 0.025 × 252 = 0.78 W 42 (8.123) = 2 × 0.3991 × 0.025 × 252 = 0.78 W 42 (8.124) and PrT2 = PrT3 = 2 (2Dmax + 1)rT2 IOmax 4 = (2 × 0.3991 + 1) × 0.01 × 252 = 2.81 W. 4 (8.125) The diode loss due to RF is PRF1 = 2 (2Dmax + 1)RF IOmax 4 = (2 × 0.3991 + 1) × 0.0125 × 252 = 3.512 W. 4 (8.126) The diode power loss due to VF is PVF1 = VF IOmax 0.7 × 25 = = 8.75 W 2 2 (8.127) and the conduction power loss in each diode is PD1 = PRF1 + PVF1 = 3.512 + 8.75 = 12.262 W. (8.128) Assuming that the dc inductor ESR is rL(dc) = 10 mΩ, the conduction power loss in the inductor ESR is 2 = 0.01 × 252 = 6.25 W PrL = rL IOmax (8.129) 348 Pulse-Width Modulated DC–DC Power Converters and the power loss in the capacitor ESR is PrC = rC (ΔiLmax )2 0.1 × 4.0272 = = 0.135 W. 12 12 (8.130) The total power loss is PLS = 4PrDS + 4Psw + Prcc + PrT1 + 2PrT2 + 2PD1 + PrL + PrC = 4 × 4.68 + 4 × 0.4 + 0.78 + 0.78 + 2 × 2.81 + 2 × 12.262 + 6.25 + 0.135 = 58.41 W (8.131) and the efficiency of the converter is 𝜂= POmax 1200 = 95.36%. = POmax + PLS 1200 + 58.41 (8.132) The peak-to-peak gate–source voltage is VGSpp = 14 V. Hence, one arrives at the gate-drive power per transistor PG = fs VGSpp Qg = 50 × 103 × 14 × 110 × 10−9 = 77 mW. (8.133) Figures 8.8 through 8.13 show the plots of the efficiency 𝜂 and the duty cycle D as functions of VI , IO and RL for the designed full-bridge converter for CCM. The efficiency 𝜂 was computed from (8.93) through (8.95) and the duty cycle D was calculated from (8.92). The efficiency 𝜂 first increases and then decreases as IO increases. The duty cycle D decreases as VI increases. 97 R = 3.84 Ω L 96.8 R = 19.2 Ω L η (%) 96.6 96.4 96.2 96 R = 1.92 Ω L 95.8 95.6 280 290 300 310 V (V) 320 330 340 I Figure 8.8 in CCM. Efficiency 𝜂 as a function of the dc input voltage VI at fixed load resistances RL for the full-bridge converter Full-Bridge PWM DC–DC Converter 349 0.36 0.35 0.34 D 0.33 0.32 R = 1.92 Ω L 0.31 RL = 3.84 Ω 0.3 R = 19.2 Ω L 0.29 280 290 300 310 V (V) 320 330 340 I Figure 8.9 in CCM. Duty cycle D as a function of the dc input voltage VI at fixed load resistances RL for the full-bridge converter 97.4 97.2 97 η (%) 96.8 96.6 V I = 340 V 96.4 V I = 283 V 96.2 V = 311 V I 96 95.8 95.6 Figure 8.10 in CCM. 0 5 10 IO (A) 15 20 25 Efficiency 𝜂 as a function of the dc load current IO at fixed dc input voltages VI for the full-bridge converter 350 Pulse-Width Modulated DC–DC Power Converters 0.36 V = 283 V I 0.35 0.34 D 0.33 V = 311 V I 0.32 0.31 0.3 V = 340 V I 0.29 0 5 10 I (A) 15 20 25 O Figure 8.11 in CCM. Duty cycle D as a function of the dc load current IO at fixed input voltages VI for the full-bridge converter 97.4 97.2 V I = 283 V 97 V = 311 V I η (%) 96.8 96.6 V I = 340 V 96.4 96.2 96 95.8 95.6 0 5 10 R (Ω) 15 20 L Figure 8.12 in CCM. Efficiency 𝜂 as a function of the load resistance IO at fixed input voltages VI for the full-bridge converter Full-Bridge PWM DC–DC Converter 351 0.36 V = 283 V I 0.35 0.34 D 0.33 V I = 311 V 0.32 0.31 0.3 V = 340 V I 0.29 0 5 10 R (Ω) 15 20 L Figure 8.13 in CCM. Duty cycle D as a function of the load resistance IO at fixed input voltages VI for the full-bridge converter 8.3 DC Analysis of PWM Full-Bridge Converter for DCM 8.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switches S1 and S3 and the diode D1 are on and the switches S2 and S4 and the diode D2 are off. The equivalent circuit is shown in Figure 8.14(a). The voltages across the switches S2 and S4 are vS2 = vS4 = VI , (8.134) v1 = V I , (8.135) the voltage across the primary winding is the voltages across the transformer secondary are v 2 = v3 = V v1 = I, n n (8.136) and the voltage across the diode D2 is 2VI . n (8.137) iL (0) = 0 (8.138) vD2 = −(v2 + v3 ) = − The voltage across the inductor L is vL = VI di − VO = L L , n dt 352 Pulse-Width Modulated DC–DC Power Converters i1 + vS4 VI n:1:1 iLm + vS4 VI n:1:1 iLm i1 + vS4 VI n:1:1 n:1:1 VI i1 Lm + vS2 n:1:1 iLm + v1 + vS3 (e) + vL C + VO i2 = iD1 L RL + VO RL + VO iL + vL C i2 = iD1 (d) + vS4 RL iL + v3 + vS3 + vS1 L + vD 2 + v2 + v1 Lm + VO iD2 iLm VI i2 = iD1 + v3 (c) i1 RL iL + vL C + v D1 v2 + + v1 + vS3 + vS1 L iD2 iLm Lm + vS2 + VO + v3 + vS3 (b) + vS1 i2 = iD1 + v2 + v1 Lm + vS2 RL + vD2 (a) + vS1 iL + v3 + vS2 i1 L + vL C + v2 + v1 Lm i2 = iD1 i2 = iD1 + v2 L iL + vL C + v3 iD2 Figure 8.14 Equivalent circuits of the full-bridge converter with a transformer center-tapped rectifier for DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ (D + D1 T)T. (c) For (D + D1 )T < t ≤ T∕2. (d) For T∕2 < t ≤ T∕2 + DT. (e) For T∕2 + DT < t ≤ (D + D1 )T. Full-Bridge PWM DC–DC Converter 353 and the inductor and switch current is t 1 1 i2 = iD1 = iL = v dt = L ∫0 L L ∫0 Hence, the peak inductor current is ( t( VI − VO n ΔiL = iL (DT) = IDM = VI ) − VO VI − VO dt = n t. n L ( ) DT L = VI − VO n fs L (8.139) ) D . (8.140) The voltage across the magnetizing inductance is diLm , i (0) < 0, dt Lm which yields the current through the magnetizing inductance vLm = VI = Lm iLm = (8.141) t V 1 vLm dt = I t + iLm (0) Lm ∫0 Lm (8.142) VI DT VD + iLm (0) = I + iLm (0). Lm fs Lm (8.143) and iLm (DT) = Hence, ΔiLm = iLm (DT) − iLm (0) = iLm (0) = − VI D , fs Lm (8.144) ΔiLm VD =− I , 2 2fs Lm (8.145) ΔiLm VD = I . 2 2fs Lm (8.146) and iLm (DT) = The current through the primary winding of the ideal transformer is V I − VO i t i1 = 2 = n n nL and the current through the switches S1 and S3 is VI iS1 = iS3 = i1 + iLm = n − VO nL (8.147) V t+ I − VO VI V VD t+ It− I . t + iLm (0) = n Lm nL Lm 2fs L (8.148) Figure 8.15 shows idealized current and voltage waveforms of the full-bridge converter with center-tapped rectifier for DCM. 8.3.2 Time Interval: DT < t ≤ (D + D1 )T The equivalent circuit for this time interval is shown in Figure 8.14(b). During this time interval, all the switches are off and both diodes are on. The voltages across the switches are vS1 = vS2 = vS3 = vS4 = VI 2 (8.149) 354 Pulse-Width Modulated DC–DC Power Converters T 2 vGS1, vGS3 0 vGS2, vGS4 0 VI 2n T 2 vS1, vS3 0 vS2, vS4 VI VI 2 0 VI T 2 T T 2 T Figure 8.15 DT D1T T DT vL VO 0 VO iL IO t VI n L T 2 VO 0 t T T 2 IO 0 vD1 0 t T t VI Lm T 2 0 vD2 T T t IO 2 T t T 2 T 2 VO T 2 0 t t T t iD2 VI 2 T t VO L iD1 T 2 Lm 0 t VI 2 0 vLm T VI VI 2 iS2, iS4 iLm vGS2 , vGS4 0 t DT iS1, iS3 0 0 T t DT 0 T 2 vGS1, vGS3 2VI n 2VI n Tt T t VO Tt Waveforms in the full-bridge converter with a transformer center-tapped rectifier for DCM. and the voltages across the primary winding and the secondary winding are v1 = v2 = v3 = 0. (8.150) diL dt (8.151) The voltage across the inductor L is vL = −VO = L and the inductor and diode current is obtained using (8.140) iL = t t V 1 1 vL dt + iL (DT) = (−VO )dt + iL (DT) = − O (t − DT) + iL (DT) L ∫DT L ∫DT L ( ) VI − VO DT VO n . = − (t − DT) + L L (8.152) Full-Bridge PWM DC–DC Converter 355 The peak inductor current is found as DT ΔiL = DT V D T 1 1 v dt = (−VO )dt = O 1 . L ∫(D+D1 )T L L ∫(D+D1 )T L (8.153) The currents of the diodes are t V i i (DT) 1 iD1 = iD2 = L = (−VO )dt + iL (DT) = − O (t − DT) + L . 2 L ∫DT 2L 2 (8.154) The voltage across the magnetizing inductance is vLm = 0, (8.155) the current through the magnetizing inductance is iLm = iLm (DT) = VI D , 2fs Lm (8.156) and the current through the primary winding of the ideal transformer is i1 = −iLm = − VI D . 2fs Lm (8.157) This time interval ends when the diode currents reaches zero. 8.3.3 Time Interval: (D + D1 )T < t ≤ T∕2 During this time interval, all switches and both diodes are off. The equivalent circuit is shown in Figure 8.14(c). The voltages across the switches are vS1 = vS2 = vS3 = vS4 = VI , 2 (8.158) the voltages across the primary and secondary windings are v1 = v2 = v3 = 0, (8.159) vD1 = vD2 = −VO . (8.160) and the voltages across the diodes are The inductor current iL , the inductor voltage vL , the switch currents, and the diode currents are zero. The voltage across the magnetizing inductance is vLm = 0, (8.161) the current through the magnetizing inductance is iLm = iLm (DT) = VI D , 2fs Lm (8.162) and the current through the primary winding of the ideal transformer is i1 = −iLm = − VI D . 2fs Lm This time ends when the switches S2 and S4 are turned on by the driver. (8.163) 356 Pulse-Width Modulated DC–DC Power Converters 8.3.4 DC Voltage Transfer Function for DCM Referring to Figure 8.15 and using the volt-second balance, ) ( VI − VO DT = VO D1 T n (8.164) which leads to MVDC = VO D . = VI n(D + D1 ) (8.165) From (8.140) and (8.165), the peak-to-peak inductor current is ( ) VI DT − V O V D(1 − nMVDC ) n ΔiL = = O . L nMVDC fs L (8.166) The dc output current is equal to the average value of the inductor current. Using (8.165) and (8.166), IO = 1 T∕2 ∫0 T∕2 iL dt = DVO (D + D1 )(1 − nMVDC ) VO D2 (1 − nMVDC ) 2 (D + D1 )TΔiL = (D + D1 )ΔiL = = . 2 T 2 nMVDC fs L n2 MVDC fs L (8.167) Hence, √ D= √ 2 n2 MVDC fs LIO (1 − nMVDC )VO = 2 n2 MVDC fs L for (1 − nMVDC )RL D≤ 1 2fs L 1 2fs LIO − = − . 2 RL 2 VO (8.168) At the boundary between CCM and DCM, MVDCB = 2DB n (8.169) as in CCM. Substitution of this into (8.168) yields the duty cycle DB at the boundary between CCM and DCM DB = 1 2fs L − . 2 RL (8.170) Figures 8.16 and 8.17 depict plots of D versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of nMVDC for both CCM and DCM for the lossless full-bridge converter. From (8.168), fs L 2 2 n MVDC + nMVDC − 1 = 0. D2 RL (8.171) Solving this equation for MVDC gives MVDC = VO = VI 2 2 ) ) = ( √ √ 4f LI 4fs L n 1 + 1 + Ds2 V O n 1 + 1 + D2 R ( L for D≤ 1 2fs L 1 2fs LIO − = − . 2 RL 2 VO (8.172) O Figures 8.18 and 8.19 show nMVDC versus normalized load current IO ∕(VO ∕2fs L) and normalized load resistance RL ∕(2fs L) at various values of D for both CCM and DCM for the lossless full-bridge converter. Notice that MVDC depends strongly on D, RL , L, and fs for DCM. Full-Bridge PWM DC–DC Converter 357 0.5 nM VDC = 0.9 0.8 0.4 0.7 0.6 0.3 CCM D 0.5 DCM 0.4 0.2 0.3 0.2 0.1 0.1 0 0 0.1 0.2 0.3 I /(V /2f L) O O 0.4 0.5 s Figure 8.16 Duty cycle D as a function of the normalized load current IO ∕(VO ∕2fs L) at fixed values of nMVDC for the lossless full-bridge converter. 0.5 nM VDC 0.4 = 0.9 0.8 0.7 CCM DCM 0.3 0.6 D 0.5 0.2 0.4 0.3 0.1 0.2 0.1 0 0 10 1 10 R /(2f L) L 2 10 s Figure 8.17 Duty cycle D as a function of normalized load resistance RL ∕(2fs L) at fixed values of nMVDC for the lossless full-bridge converter. 358 Pulse-Width Modulated DC–DC Power Converters 1 D = 0.4 0.8 0.3 VDC 0.6 nM CCM 0.2 0.4 DCM 0.1 0.2 0 0 0.1 0.2 0.3 I /(V /2f L) O O 0.4 0.5 s Figure 8.18 DC voltage transfer function nMVDC as a function of the normalized load current IO ∕(VO ∕2fs L) at fixed values of D for the lossless full-bridge converter. 1 0.8 D = 0.4 CCM 0.3 DCM nMVDC 0.6 0.4 0.2 0 0 10 0.2 0.1 1 10 R /(2f L) L 2 10 s Figure 8.19 DC voltage transfer function nMVDC as a function of normalized load resistance RL ∕(2fs L) at fixed values of D for the lossless full-bridge converter. Full-Bridge PWM DC–DC Converter Using (8.165) and (8.172), (√ ) ( ) 4fs L D 1 −1 = 1+ 2 −1 D1 = D nMVDC 2 D RL ) (√ 4fs LIO D = 1+ 2 −1 2 D VO 1 2fs L 1 2fs LIO − = − . 2 RL 2 VO for D≤ for 0 < t ≤ DT. 359 (8.173) The dc input current is VI iI = iS1 = i1 + iLm ≈ i1 = n − VO nL t resulting in the dc input current II = 1 T∕2 ∫0 DT iI dt = 2 T ∫0 DT VI − VO n nL and the dc input power D2 PI = VI II = D2 ( tdt = ( 2 VI − VO n (8.174) ) nfs L (8.175) ) VI − VO VI n nfs L . (8.176) The dc output power is PO = VO2 RL . (8.177) The efficiency of the converter is 𝜂= 2 fs Ln2 MVDC PO = 2 PI D RL (1 − nMVDC ) (8.178) which gives the duty cycle of the lossy full-bridge converter in DCM √ √ 2 2 n2 MVDC fs L n2 MVDC fs LIO 1 2f L 1 2f LI D= = for D ≤ − s = − s O . 𝜂RL (1 − nMVDC ) 𝜂VO (1 − nMVDC ) 2 RL 2 VO (8.179) Rearrangement of this yields MVDC = VO = VI 2 2 ) ( ) = ( √ √ 4f LI 4fs L n 1 + 1 + 𝜂Ds2 VO n 1 + 1 + 𝜂D2 R for D≤ 1 2fs L 1 2fs LIO − = − . 2 RL 2 VO (8.180) O L 8.3.5 Maximum Inductance for DCM The inductor current waveforms at the boundary between CCM and DCM for VImin and VImax are shown in Figure 8.20. The maximum output current at boundary between DCM and CCM is IOmax = IOB = V (0.5 − DBmax ) V ΔiLmin = O = O , 2 2fs Lmax RLmin (8.181) which gives the maximum inductance required to maintain the converter operation in DCM is Lmax = RLmin (0.5 − DBmax ) VO (0.5 − DBmax ) = . 2fs 2fs IOmax (8.182) 360 Pulse-Width Modulated DC–DC Power Converters iL VImax n VO VImin n L VO L Δ i Lmin VO L IOB Dmin T 0 T 2 Dmax T t Figure 8.20 Waveform of the inductor current in the full-bridge converter at the boundary between CCM and DCM for VImin and VImax . S1 V I S3 Rectifier S2 S4 v + Δφ Figure 8.21 S1 Full-bridge converter with phase-shift control. VI + v=0 S3 VI Rectifier S2 S1 S3 S4 Rectifier S2 + (a) S1 + v=0 (c) Figure 8.22 S1 S3 VI Rectifier S2 S4 (b) S3 VI v = VI S4 Rectifier S2 + v = VI (d) Equivalent circuits in full-bridge converter with phase-shift control. S4 Full-Bridge PWM DC–DC Converter 361 vGS1 0 π 2π ωt 0 π 2π ωt 0 π 2π ωt vGS2 vGS3 vGS4 0 ωt Δφ v VI 0 ωt VI Figure 8.23 Waveforms in full-bridge converter with phase-shift control. 8.4 Phase-Controlled Full-Bridge Converter A full-bridge converter with phase-shift control is shown in Figure 8.21. The phase of the gate-to-source voltages in the right switching leg are shifted by the phase Δ𝜙 with respect to the gate-to-source voltages in the left switching leg. Figure 8.22 depicts the equivalent circuits for the phase-controlled full-bridge converter. Waveforms for this circuit are shown in Figure 8.23. It can be seen that the duty cycle D of the voltage across the rectifier can be controlled by varying the phase shift Δ𝜙. The duty cycle D is given by D= 1 Δ𝜙 − . 2 2𝜋 (8.183) As the phase shift Δ𝜙 increases from 0 to 𝜋, the duty cycle of the upper pulse and the bottom pulse decreases from 0.5 to 0. 362 Pulse-Width Modulated DC–DC Power Converters 8.5 Summary r r r r r r r r r r r r r r r The PWM full-bridge converter is either a step-up or a step-down converter. The dc voltage transfer function of the lossless converter is MVDC = 2D∕n. The duty cycle must be less than 50%. The transformer is not required to store energy in the full-bridge converter. The magnetic core utilization is excellent because the flux can vary between ±Bs , where Bs is the saturation flux density. The converter has conduction losses and switching losses. The duty cycle D of the lossy converter is greater than that of the lossless converter at the same value of the dc voltage transfer function. The peak-to-peak value of the inductor ripple current ΔiL is independent of the dc load current for CCM. The peak-to-peak value of the current through the filter capacitor C is relatively low and is equal to the peak-to-peak inductor ripple current ΔiL . If the capacitance of the filter capacitor is sufficiently high, the output ripple voltage is determined only by the ESR of the filter capacitor and is independent of the capacitance of the filter capacitor. The minimum value of the inductor is determined by the boundary between CCM and DCM, output ripple voltage, core saturation, or ac losses in the inductor and/or the filter capacitor. The input current is pulsating. However, an LC filter can be added at the input of the converter to obtain a nonpulsating input current waveform. √ The corner frequency of the output filter fo = 1∕(2𝜋 LC) is independent of the load resistance. The output inductor can be made smaller because the ripple frequency is twice that of the single-ended converters. It is relatively difficult to drive the upper transistors because the gates are not referenced to ground. References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. [2] E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. [3] G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGraw-Hill, 1984. [4] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. [5] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [6] M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood Cliffs, N J: Prentice Hall, 2004. [7] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. [8] K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. [9] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, Mass.: Addison-Wesley, 1991. [10] A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. [11] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. [12] I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. Review Questions 8.1 Give the expression for the dc voltage transfer function of the lossless full-bridge converter. 8.2 What is the maximum value of the duty cycle for the full-bridge converter? 8.3 What happens when the duty cycle is too large? Full-Bridge PWM DC–DC Converter 363 8.4 How to prevent cross conduction in the full-bridge converter? 8.5 Is the transformer required to store energy in the full-bridge converter? 8.6 What is the dc component of the current through the primary winding of the transformer in the full-bridge converter? 8.7 Is the magnetic core utilization good in the full-bridge converter? 8.8 Is the input current of the basic full-bridge converter pulsating? 8.9 How can the circuit be modified to obtain a nonpulsating input current in the full-bridge converter? 8.10 Are the upper transistors driven with respect to ground in the full-bridge converter? 8.11 What is the correct value of the magnetizing inductance Lm of the transformer? 8.12 Do the losses increases or decrease the duty cycle D of the full-bridge converter at a given value of MVDC for CCM? 8.13 Is the corner frequency of the output filter dependent on the load resistance? 8.14 Compare the frequency of the output ripple voltage with the frequency of the gate-to-source voltages of the power transistors. Problems 8.1 Derive an expression for the voltage stress of the diodes in the full-bridge converter with the full-bridge rectifier. 8.2 A full-bridge PWM converter has the input voltage as the US single-phase rectified line, VO = 48 V, PO = 1– 2.5 kW, and fs = 35 kHz. Find the transformer turns ratio n, the minimum duty cycle Dmin , and the maximum duty cycle Dmax . 8.3 A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1–2.5 kW, and fs = 35 kHz. Find the voltage stresses of the transistors and the diodes. 8.4 A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1–2.5 kW, Dmin = 0.27, and fs = 35 kHz. Find the minimum inductance required to maintain the converter operation in CCM. Calculate the maximum value of peak-to-peak inductor ripple current and ΔiLmax ∕IOmax . 8.5 A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1–2.5 kW, Dmin = 0.27, and fs = 35 kHz. Find the minimum inductance at which the ratio of the peak-to-peak inductor ripple current to the maximum load current is less than 10%. 8.6 A full-bridge PWM converter has the input voltage as the US single-phase rectified line, VO = 48 V, PO = 1– 2.5 kW, L = 70 μH, and fs = 35 kHz, and Vr ∕VO ≤ 1%. Find the filter capacitance and the corner frequency of the output filter. 8.7 A full-bridge PWM converter has the input voltage as the US single-phase rectified line, VO = 48 V, PO = 1– 2.5 kW, fs = 35 kHz, and Vr ∕VO ≤ 1%. Find the minimum magnetizing inductance Lm(min) at which its maximum peak-to-peak current is less than 10% of the maximum peak current of the ideal transformer primary winding. 8.8 A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1–2.5 kW, and fs = 35 kHz. Find the current stresses of the transistors and the diodes. 364 Pulse-Width Modulated DC–DC Power Converters 8.9 A full-bridge dc–dc converter accepts a US single-phase rectified line and deliver VO = 1 kV. Find the transformer turns ratio n, the minimum duty cycle Dmin , and the maximum duty cycle Dmax . 8.10 A full-bridge dc–dc converter with a bridge rectifier accepts the US single-phase rectified line and has VO = 1 kV and n = 1∕10. Find the voltage stresses of the switches and the diodes. 8.11 A full-bridge dc–dc converter accepts the US single-phase rectified line and has VO = 1 kV, n = 1∕10, PO = 100 W to 1 kW, Dmin = 0.2815, and fs = 50 kHz. Find the minimum inductance for CCM operation. 8.12 A full-bridge dc–dc converter accepts the US single-phase rectified line and has VO = 1 kV, n = 1∕10, PO = 100 W to 1 kW, Dmin = 0.2814, Dmax = 0.4144, L = 25 mH, Vr ∕VO ≤ 1%, and fs = 50 kHz. Find the minimum filter capacitance and its minimum ESR. 8.13 A full-bridge dc–dc converter should accept the US three-phase rectified line and delivers VO = 1 kV. Find the transformer turns ratio n. √ 8.14 Design a full-bridge PWM converter suitable for telecommunication applications with VI = 2(220 V±10%), VO = 48 V, IO = 5–50 A, fs = 35 kHz, and Vr ∕VO ≤ 1%. Assume rDS = 0.3 Ω, Co = 100 pF, Qg = 110 nF, VF = 0.7 V, RF = 12.5 mΩ, rT1 = 25 mΩ, rT2 = 10 mΩ, and rL(dc) = 10 mΩ. Assume initially the converter efficiency 𝜂 = 96%. 8.15 Design a full-bridge PWM converter for aerospace applications with VI = 270 V±10%, VO = 28 V, IO = 10– 100 A, and Vr ∕VO ≤ 1%. 8.16 Design a full-bridge converter to meet the following specifications: VI = 48 ± 6 V, VO = 5 V, IO = 5–50 A, and Vr ∕VO ≤ 1%. Assume rDS = 0.18 Ω, Co = 100 pF, Qg = 110 nF, VF = 0.3 V, RF = 10 mΩ, rT1 = 10 mΩ, rT2 = 3 mΩ, rL(dc) = 4 mΩ, and fs = 50 kHz. Assume initially the converter efficiency 𝜂 = 75%. 8.17 Design a universal off-line full-bridge converter operating in CCM to meet the following specifications: the input voltage is from a single-phase utility line anywhere in world with the rms voltage V = 90–240 Vrms, f = 50∕60 Hz, VO = 48 V, IO = 5–50 A, fs = 100 kHz, and Vr ∕VO ≤ 1%. 9 Small-Signal Models of PWM Converters for CCM and DCM 9.1 Introduction Power stages of PWM converters are highly nonlinear systems because they contain at least one transistor and at least one diode, which are operated as switches. PWM converters are periodic variable structure systems. The converters normally require control circuits to regulate the dc output voltage against load and line variations. Typical control aspects of interest are frequency response, transient response, and stability. Linear control theory is well developed and it may offer valuable tools for studying the small-signal dynamic performance of PWM converters. However, in order to apply this theory, nonlinear power stages of PWM converters should be averaged and linearized [1–51]. There are two averaging methods for PWM converters: r state-space averaging method [1–43] r circuit-averaging method [9–33]. The state-space averaging method [1–43] is based on analytical averaging of state-space equations describing linear equivalent circuits for different states of a converter determined by the on–off status of the transistor(s) and the diode(s). The state-space equations are weighed according to the fraction of the switching cycle, during which the converter remains in a given state. However, the state-space averaging method requires a considerable amount of matrix algebra manipulations and is sometimes tedious, especially when the converter circuit contains a large number of passive elements or parasitic components. Moreover, it provides little insight into the converter behavior. On the other hand, in many power electronic circuits, the average values of voltages and currents of switching components rather than their instantaneous values are of the greatest interests. The circuit-averaging method involves the following steps: (1) Averaging of current and voltage waveforms of switching components over one switching period, (2) Replacement of switching components with nonlinear dc dependent current and voltage sources, (3) Averaging the parasitic components of the switching devices over one switching period, such as transistor on-resistance, diode forward resistance, and diode offset voltage, (4) Perturbation of the averaged current, voltage, and duty ratio waveforms to obtain large-signal time-dependent waveforms, Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 366 Pulse-Width Modulated DC–DC Power Converters (5) (6) (7) (8) (9) Replacement of dc dependent sources by nonlinear large-signal dependent current and voltage sources, Splitting the large-signal current, voltage, and duty cycle waveforms into the dc and ac components, Linearization of nonlinear dependent current and voltage sources, Separation of dc and small-signal variables, Representation of the dc variables by a dc circuit model and representation of the small-signal ac variables by a small-signal linear ac circuit model. The circuit-averaging method leads to linear time-invariant (LTI) circuit models [9–33]. These models are relatively simple, provide good physical and intuitive insight into the converter behavior, can be used for deriving various transfer functions and step responses, and are compatible with general purpose electronic circuit simulators. In addition, control loops for PWM converters can be designed by applying well-known linear control techniques. Some nonlinear control methods have been proposed in [34–36]. In this chapter, the averaged nonlinear large-signal, dc, and ac small-signal LTI circuit models of the discrete switching network of PWM converters are developed for CCM and DCM, using current and voltage dependent sources and the law of conservation of energy [23–44]. The current- and voltage-dependent sources are used to model the ideal switching network and the law of conservation of energy is used to model parasitic components of switching devices, such as the transistor on-resistance, the diode forward resistance, and the diode offset voltage. The ideal switching network of single-ended transformerless PWM converters consists of two ideal switches. This network can be modeled for the dc components in steady state by two ideal dc dependent sources. The switched forward resistances of the switch and the diode are averaged, using the law of conservation of energy. The currents, voltages, and duty cycle are then perturbed in the average dc model. Hence, the dc dependent sources in the model are replaced by large-signal time-varying dependent sources. Consequently, large-signal currents, voltages, and duty cycle contain both dc and ac components. Therefore, the large-signal sources can be replaced by the dc dependent sources and the ac small-signal dependent sources. If the magnitudes of the small-signal components are low enough, the model can be linearized by neglecting products of the ac components. This leads to a linear circuit model, containing both dc- and ac-dependent sources. Since the model is linear, it can be split into a small-signal low-frequency ac circuit model and a dc circuit model. If the switching network in a PWM converter is replaced by its small-signal model, a small-signal model of the entire power stage is obtained. This model may be used to derive and simulate small-signal transfer functions and step responses of that converter. A good model should reproduce the characteristics of a real circuit. 9.2 Assumptions The models are derived under the following assumptions: (1) The transistor output capacitance and the diode capacitance are neglected; therefore, switching losses are neglected. (2) The transistor on-resistance rDS is linear and the transistor off-resistance is infinite. (3) The diode in the on-state is modeled by a linear battery VF and a linear forward resistance RF . In the off-state, the diode is modeled by an infinite resistance. (4) Passive components are linear, time invariant, and frequency independent. (5) Storage-time modulation of bipolar transistors is neglected. 9.3 Averaged Model of Ideal Switching Network for CCM A PWM converter consists of a nonlinear discrete part and a linear analog part. The nonlinear part consists of nonlinear semiconductor devices such as a transistor(s) and a diode(s) operated as switches, that is, as discrete components. The linear part consists of linear components, such as capacitors and inductors with their equivalent series resistances. The nonlinear part may be replaced by an average circuit model, which emulates its average Small-Signal Models of PWM Converters for CCM and DCM 367 low-frequency behavior. In the average circuit model, the average low-frequency voltages across the model terminals and the average low-frequency currents into its terminals are identical to those of the original switching network. The waveforms of the average current and voltage do not contain high-frequency components. The high-frequency components can be regarded as carriers. The average model is nonlinear and may be linearized for small ac signals. The linear part of a converter does not require averaging and linearization. The modeling strategy of PWM converters is similar to transistor modeling and is based on the following principles: (1) Replacement of the switching network (or components) by an analog (continuous) circuit model. (2) Leaving the analog part composed of linear components unchanged. Figure 9.1 shows four basic single-ended transformerless two-switch PWM converters: buck, boost, buck–boost, and Ćuk converters. All these converters have a common subcircuit that consists of two switching devices: a power MOSFET and a diode. This subcircuit is highly nonlinear and is referred to as a switching network. Figure 9.2(a) shows the switching network of single-ended transformerless two-switch PWM converters, and Figure 9.2(b) shows an equivalent circuit of the switching network. The ideal part of the switching network consists of two ideal switches. One ideal switch represents an ideal MOSFET whose on-resistance is zero, and the other ideal switch represents an ideal diode whose forward resistance and offset voltage are zero. The actual switching network consists of an ideal switching network and parasitic components. The MOSFET is represented by an ideal switch and a linear on-resistance rDS , and the diode is represented by an ideal switch, a linear forward resistance RF , and an offset voltage VF . Figure 9.3 shows the steady-state current and voltage waveforms in the ideal switching network for CCM. In this case, all ac external excitations, disturbances, and uncertainties are zero. There is no startup, shutdown, or sudden change in the input voltage and load resistance. Since the steady-state waveforms are periodic, all the current and voltage waveforms, their dc components, and the duty cycle D are the same in every cycle of the switching frequency fs = 1∕T. In general, the average value of any periodic waveform of any quantity x(t) in steady state over one cycle T is given by X = XDC = ⟨x(t)⟩T = 1 T ∫t 𝜔t+2𝜋 t+T x(t)dt = 1 2𝜋 ∫𝜔t x(𝜔t)d(𝜔t). (9.1) The waveforms of the inductor current iL and the voltage across the combination of the switch and the diode vSD are continuous, whereas the waveforms of the switch current iS and the diode reverse voltage vLD are pulsating. Averaging the high-frequency instantaneous values of converter waveforms is simply extracting the corresponding dc components over one cycle of the switching frequency fs . Note that averaging the steady-state waveforms (with zero ac excitations) over many cycles gives the same result. Let us neglect the parasitic components in the PWM converters shown in Figure 9.1. For the buck converter, VSD = VI , VSL = VI − VO , and VLD = VO . For the boost converter, VSD = VO , VSL = VI , and VLD = VO − VI . For the buck–boost converter, VSD = VI − VO = VI + |VO |, VSL = VI , and VLD = VO . For the Ćuk converter, VSD = VI − VO = VI + |VO |, VSL = VI , and VLD = VO . According to Figure 9.3, the steady-state waveform of the switch current can be approximated by { IL , for 0 < t ≤ DT iS ≈ (9.2) 0, for DT < t ≤ T. Hence, the dc component of the switch current is T IS = 1 1 i dt = T ∫0 S T ∫0 DT IL dt = DIL . (9.3) This expression describes an ideal dc current-controlled current source (CCCS) or current-dependent current source controlled by the dc component IL of the inductor current iL . An equivalent circuit representing this expression is an averaged model of an ideal switch and is shown in Figure 9.4(a). 368 Pulse-Width Modulated DC–DC Power Converters S′ L L VI C RL + VO > 0 C RL + VO > 0 C RL + VO < 0 C2 RL + VO < 0 D′ (a) S′ VI D′ L L (b) S′ D′ L VI L (c) S′ C1 VI D′ L L2 L1 (d) Figure 9.1 Single-ended transformerless two-switch PWM converters. (a) Buck converter. (b) Boost converter. (c) Buck–boost converter. (d) Ćuk converter. Referring to Figure 9.3, the steady-state waveform of the voltage across the ideal diode is given by { VSD , for 0 < t ≤ DT vLD = 0, for DT < t ≤ T (9.4) yielding its dc component T VLD = 1 1 v dt = T ∫0 LD T ∫0 DT VSD dt = DVSD . (9.5) Small-Signal Models of PWM Converters for CCM and DCM L S′ iS 369 L iL iD D′ (a) S′ rDS iS S L + + vSD Ideal Switching Network vLD L iL D Actual Switching Network iD RF VF D′ (b) Figure 9.2 Switching network and equivalent circuit of single-ended transformerless two-switch PWM converters. (a) Switching network. (b) Equivalent circuit. This expression describes an ideal dc voltage-controlled voltage source (VCVS) or voltage-dependent voltage source controlled by the dc component VSD of the switch–diode voltage vSD . Figure 9.4(b) shows an equivalent circuit representing an averaged model of an ideal diode. Using the averaged models of an ideal switch and an ideal diode, an averaged model of an ideal switching network of two-switch PWM converters is obtained, as depicted in Figure 9.4(c). This model describes the performance of an ideal switching network for the dc components under steady-state conditions. It does not contain information about the inductor ripple current as well as the pulsating nature of the switch and diode current and voltage waveforms. The model of the switching network for the dc components under steady-state operating conditions is referred to as the “dc model.” 9.4 Averaged Values of Switched Resistances The transistor on-resistance rDS and the diode forward resistance RF are in series with the ideal switches in the switching network of Figure 9.2(b). These resistances should be averaged. Other resistances of a converter, such as the ESR of the inductor and the ESR of the filter capacitor, need not be averaged because they are not connected in series with the switches. The law of conservation of energy is used to determine the average values of the switched resistances. 370 Pulse-Width Modulated DC–DC Power Converters iL IL 0 DT T DT T DT T t iS IL IS = DIL 0 t iD IL ID = (1− D)IL 0 t vSD VSD 0 t vLD VSD VLD = DVSD 0 Figure 9.3 DT T t Steady-state waveforms in the ideal switching network for CCM. The diode current can be approximated by { iD ≈ 0, IL , for 0 < t ≤ DT for DT < t ≤ T. (9.6) Thus, the dc component of the diode current is T ID = T 1 1 i dt = I dt = IL (1 − D). T ∫0 D T ∫DT L (9.7) Small-Signal Models of PWM Converters for CCM and DCM Switched Network 371 Averaged Network IS S S iS DIL IL L L (a) L S L + + + VSD vLD + DVSD D D VLD D (b) iS iL L S + vSD IL DIL L S + + vLD VSD + DVSD D D (c) Figure 9.4 Averaged model of ideal switch, ideal diode, and ideal switching network for the dc components in steady state for CCM. (a) Averaged model of an ideal switch. (b) Averaged model of an ideal diode. (c) Averaged model of an ideal switching network of two-switch PWM converters. From (9.3) and (9.7), IL = IS I = D . D 1−D Using (9.2) and (9.3), the rms value of the switch current is obtained as √ √ √ T DT √ IS ID D 1 1 2 2 ISrms = . i dt = IL dt = IL D = √ = T ∫0 S T ∫0 1−D D (9.8) (9.9) The power loss in the MOSFET on-resistance rDS is 2 = PrDS = rDS ISrms rDS 2 I . D S (9.10) 372 Pulse-Width Modulated DC–DC Power Converters S′ S′ IS S′ rDS iS S rDS iS D IL DIL L L L L (a) L L S L + VSD iD + D RF RF 1− D VF VF D′ DVSD D′ D′ (b) Figure 9.5 Averaged models of the actual MOSFET and the actual diode in steady state for CCM. (a) Averaged model of the actual MOSFET. (b) Averaged model of the actual diode. On the other hand, the power loss in the averaged MOSFET on-resistance rDSAV(S) in the switch branch is PrDSAV(S) = rDSAV(S) IS2 . (9.11) Using the law of conservation of energy, the energy dissipated in the switched MOSFET on-resistance rDS is the same as that in the averaged switch resistance rDSAV(S) . Hence, the equivalent averaged resistance (EAR) of rDS in the switch branch is r (9.12) rDSAV(S) = DS D as shown in Figure 9.5(a). The switch resistance may be also averaged by averaging the switch conductance over the period of the switching frequency T = 1∕fs . The switch conductance is approximated by { gDS = r1 , for 0 < t ≤ DT DS (9.13) gDS (t) ≈ 0, for DT < t ≤ T. The average switch conductance in the switch branch is T gDSAV(S) = 1 1 g dt = T ∫0 DS T ∫0 DT gDS dt = DgDS , (9.14) yielding the average switch resistance in the switch branch rDSAV(S) = 1 gDSAV(S) = r 1 = DS . DgDS D (9.15) Small-Signal Models of PWM Converters for CCM and DCM Using (9.6), the rms value of the diode current is obtained as √ √ √ T T √ IS 1 − D I 1 1 2 2 = √ D i dt = I dt = IL 1 − D = IDrms = T ∫0 D T ∫DT L D 1−D 373 (9.16) resulting in the power loss in the diode forward resistance RF 2 PRF = RF IDrms = RF 2 I . 1−D D (9.17) The power dissipated in the equivalent averaged diode forward resistance RFAV(D) in the diode branch is PRFAV(D) = RFAV(D) ID2 . (9.18) Consequently, the EAR of RF in the diode branch is obtained as RFAV(D) = RF 1−D (9.19) as shown in Figure 9.5(b). The diode forward resistance may be averaged by averaging the diode forward conductance over the period of the switching frequency. The diode forward resistance conductance can be approximated by { 0, for 0 < t ≤ DT gF (t) ≈ (9.20) gF = R1 , for DT < t ≤ T. F The average diode forward conductance in the diode branch is T gFSAV(D) = T 1 1 g dt = g dt = (1 − D)gF , T ∫0 F T ∫DT F (9.21) producing the average diode forward resistance in the diode branch RFAV(D) = 1 gFAV(D) = RF 1 . = (1 − D)gF 1−D (9.22) The power dissipated in the diode offset voltage source VF is PVF = VF ID (9.23) and the power dissipated in the equivalent averaged voltage VFAV(D) of the offset voltage source in the diode branch is PVFAV(D) = VFAV(D) ID . (9.24) Equating the right-hand sides of (9.23) and (9.24), one obtains the averaged diode offset voltage in the diode branch VFAV(D) = VF (9.25) as shown in Figure 9.5(b). Figures 9.6(a) and (b) depicts the actual switching network and its averaged dc model, respectively. If a bipolar junction transistor (BJT) or an insulated gate bipolar transistor (IGBT) is used as a switch, the offset voltage source can be averaged in a similar manner. The inductance L is not a part of the switching network model. 374 Pulse-Width Modulated DC–DC Power Converters rDS S′ iL S L + vSD D RF VF D′ (a) rDS S′ D DIL S IL L + VSD + D DVSD RF 1 D VF D′ (b) DIL IL S + VSD + DVSD (1− D )VF DrDS (1− D )RF rL L r D (c) Figure 9.6 Modeling of the actual switching network under steady-state conditions for two-switch PWM converters operating in CCM. (a) Actual switching network. (b) Averaged dc model of the actual switching network. (c) Simplified averaged dc model of the actual switching network with the averaged resistances moved to the inductor branch. Small-Signal Models of PWM Converters for CCM and DCM 375 9.5 Model Reduction The averaged model of the actual switching network shown in Figure 9.6(b) contains two resistors. This does not cause any problem if the model is used for converter simulation purposes, such as PSPICE. However, a simpler form of the model is desirable, if it is used to derive various transfer functions and impedances. Reflection rules are used to derive a simplified model of the actual switching network. Substitution of (9.8) into (9.10) yields PrDS = rDS 2 DrDS 2 I = DrDS IL2 = I . D S (1 − D)2 D Hence, the averaged MOSFET resistance in the MOSFET branch is r rDSAV(S) = DS D the averaged MOSFET resistance in the inductor branch is (9.26) (9.27) rDSAV(L) = DrDS (9.28) and the averaged MOSFET resistance in the diode branch is DrDS . (1 − D)2 (9.29) = D2 (9.30) = (1 − D)2 (9.31) rDSAV(D) = The ratios of these resistances are rDSAV(L) rDSAV(S) rDSAV(L) rDSAV(D) and rDSAV(S) rDSAV(D) ( = 1−D D )2 . (9.32) Thus, the relationship among the averaged MOSFET resistances in the different branches is rDSAV(L) = D2 rDSAV(S) = (1 − D)2 rDSAV(D) . (9.33) Substituting (9.8) into (9.17), one obtains PRF = RF ID2 1−D = (1 − D)RF IL2 = (1 − D)RF 2 IS D2 (9.34) which results in the averaged diode resistance in the diode branch RFAV(D) = RF 1−D (9.35) the averaged diode resistance in the inductor branch RFAV(L) = (1 − D)RF (9.36) and the averaged diode resistance in the MOSFET branch RFAV(S) = (1 − D)RF . D2 (9.37) 376 Pulse-Width Modulated DC–DC Power Converters The ratios of these resistances are RFAV(L) = D2 (9.38) = (1 − D)2 (9.39) RFAV(S) RFAV(L) RFAV(D) and RFAV(S) RFAV(D) ( = 1−D D )2 . (9.40) Hence, the relationship among the averaged diode forward resistances in the different branches is RFAV(L) = D2 RFAV(S) = (1 − D)2 RFAV(D) . (9.41) Substitution of (9.8) into (9.23) gives PVF = VF ID = (1 − D)VF IL = 1−D VF IS . D (9.42) This leads to the averaged offset diode voltage in the diode branch VFAV(D) = VF (9.43) the averaged offset diode voltage in the inductor branch VFAV(L) = (1 − D)VF (9.44) and the averaged offset diode voltage in the MOSFET branch VFAV(S) = (1 − D)VF . D (9.45) The ratios of these averaged voltages are VFAV(L) =D (9.46) =1−D (9.47) 1−D . D (9.48) VFAV(S) VFAV(L) VFAV(D) and VFAV(S) VFAV(D) = Finally, the relationship among the averaged diode offset voltages in the various branches is VFAV(L) = DVFAV(S) = (1 − D)VFAV(D) . (9.49) Using (9.12), (9.19), and (9.26)–(9.48), the general reflection rules are as follows: rl = D2 rs = (1 − D)2 rd (9.50) Vl = DVs = (1 − D)Vd (9.51) where rl , rs , and rd are the EARs in inductor branch, switch branch, and diode branch, respectively, and Vl , Vs , and Vd are the equivalent averaged voltage sources in the inductor branch, the switch branch, and the diode branch, respectively. Small-Signal Models of PWM Converters for CCM and DCM 377 The equivalent resistance of the inductor branch is given by r = rDSAV(L) + RFAV(L) + rL = DrDS + (1 − D)RF + rL . (9.52) A simplified averaged dc model of the actual switching network is shown in Figure 9.6(c). The reflection rules can be applied to move the parasitic components from one branch to another, yielding an averaged model, which is equivalent to that of Figure 9.6(b). 9.6 Large-Signal Averaged Model for CCM The actual switching network is shown in Figure 9.7(a). The dc quantities such as dc inductor current IL , dc voltage VSD , and constant duty cycle D in the averaged models shown in Figures 9.6(b) and (c) can be replaced by slowly varying, time-dependent, large-signal quantities such as the current iL , voltage vSD , and duty cycle dT . Relationships among the low-frequency large-signal variables can be approximated using the dc relationships (9.3) and (9.5) for the dc variables vLD = dT vSD (9.53) iS = dT iL . (9.54) and A large-signal, low-frequency, averaged model representing these equations is shown in Figures 9.7(b) and (c). It assumed that the relationships between the dc components and the large-signal time-dependent components remain the same. This assumption is satisfied when the time rate of change of the average values of all variables is sufficiently low. In particular, it assumed that the capacitive effects can be neglected. Example 9.1 Draw a large-signal low-frequency averaged model of the buck PWM converter with parasitic components. Simplify this model using a current source splitting theorem. Solution: Figure 9.8(a) shows a large-signal low-frequency averaged model of the buck converter. This model can be obtained by replacing the actual switching network with the large-signal model shown in Figure 9.7(c) in the buck converter. Note that vSD = vI for the buck converter. Using the current splitting theorem, the dependent current source can be split into two current sources, as shown in Figure 9.8(b). In general, the parallel combination of a current source and a voltage source is equivalent to the voltage source. Therefore, the model may be simplified by neglecting the dependent current source in parallel with the dependent voltage source, as depicted in Figure 9.8(c). Example 9.2 In the buck PWM converter, the duty cycle dT = D is held at a fixed value and the initial boundary conditions of the inductor L and the filter capacitor C are zero. The inductance L is high enough to operate the converter in CCM for steady state. At time t = 0, the dc input voltage source VI is turned on. Find the waveform of the output voltage vO without the switching-frequency component and its harmonics for 𝜉 = 0.3. Neglect parasitic elements. Solution: The large-signal low-frequency averaged model shown in Figure 9.8(c) with no parasitic elements may be used to find the output voltage. This voltage is a response to a step change of the input voltage, without the switching-frequency component. This model is linear when dT = D. The step change of the input voltage in the time domain is vI (t) = VI u(t). (9.55) 378 Pulse-Width Modulated DC–DC Power Converters rDS S′ iL S L + vSD D RF VF D′ (a) rDS S′ D S dT iL iL L + vSD + D d T vSD RF 1 D VF D′ (b) dT iL iL S + vSD + d T vSD (1− D )VF DrDS (1− D )RF rL L r D (c) Figure 9.7 Large-signal averaged models of the actual switching network for two-switch PWM converters for CCM. (a) Actual switching network. (b) Large-signal averaged model of the actual switching network. (c) Simplified largesignal averaged model of the actual switching network with the averaged resistances moved to the inductor branch. Small-Signal Models of PWM Converters for CCM and DCM dT iL vI ( 1− D) VF L C iL + + r 379 dT vI rC RL + vO RL + vO RL + vO (a) ( 1− D) VF r vI + L C iL dT iL dT iL + dT vI rC (b) ( 1− D) VF r vI + dT iL + iL + vA dT vI L C rC (c) Figure 9.8 Large-signal low-frequency model of the buck PWM converter with parasitic components for CCM. (a) Large-signal model with the dependent sources in the original branches. (b) Large-signal model with the dependent current source split into two sources. (c) Simplified large-signal model. Therefore, the average voltage at the input of the LCRL circuit is also a step change given by vA (t) = DvI (t) = DVI u(t) (9.56) which in the s-domain is vA (s) = DVI . s (9.57) The voltage transfer function of the LCRL circuit is 1 RL sC Av (s) = vO (s) = vA (s) 1 RL + sC 1 RL sC = 1 + sL RL + sC 1 1 . LC s2 + s 1 + 1 CR LC (9.58) L The undamped resonant frequency (or the natural frequency) is 1 𝜔0 = √ LC (9.59) 380 Pulse-Width Modulated DC–DC Power Converters and the damping factor is 𝜉= 1 2RL √ L . C (9.60) Hence, Av (s) = 𝜔20 s2 + 2𝜉𝜔0 s + 𝜔20 . (9.61) The output voltage in the s-domain is vO (s) = Av (s)vA (s) = [ DVI 𝜔20 s(s2 + 2𝜉𝜔0 s + 𝜔20 ) = DVI s + 2𝜉𝜔0 1 − 2 s s + 2𝜉𝜔0 s + 𝜔20 resulting in the output voltage in the time domain [ 1 vO (t) =  {vO (s)} = DVI 1 − √ e 1 − 𝜉2 −1 −𝜉𝜔0 t sin(𝜔0 √ ] (9.62) ] 1 − 𝜉 2 t + 𝜙) (9.63) where 𝜙 = arccos 𝜉. (9.64) Figure 9.9 shows the normalized output voltage waveform vO ∕(DVI ) without the switching-frequency component. The output voltage is the response of the second-order low-pass filter to a step change in the dc input voltage from zero to VI . vo DVI 1.4 1.3 1.2 1.1 Overshoot Error band + P% 1.0 0.9 0.8 0.7 0.6 ξ = 0.3 0.5 0.4 0.3 0.2 Rise time 0.1 0 tr td Delay time ts Settling time t Figure 9.9 Normalized output voltage vO ∕(DVI ) as a response to a step change in the dc input voltage at 𝜉 = 0.3, neglecting the switching-frequency component. Small-Signal Models of PWM Converters for CCM and DCM 381 9.7 DC and Small-Signal Circuit Linear Models of Switching Network for CCM 9.7.1 Large-Signal Circuit Model of Switching Network for CCM Consider the operation of a PWM converter under the external low-frequency excitation (also called a lowfrequency perturbation) superimposed on the dc component. Each of the waveforms in a PWM converter under the low-frequency excitation contains three components: (1) a dc component, (2) a low-frequency component of the frequency f = 𝜔∕(2𝜋) and its harmonics, and (3) a high-frequency component of the switching frequency fs and its harmonics. Only the dc components and the low-frequency components are of interest to study control aspects of PWM converters. This is because the control signals of the closed-loop PWM converters normally consist of the dc and low-frequency components. Consequently, the low-frequency components are used to characterize the dynamics of PWM systems. The purpose of the averaged low-frequency dynamic models is to emulate the average behavior (in particular, dynamics) of the open- and closed-loop PWM converters in the low-frequency range. In the simplest case, the low-frequency perturbation signals can be sinusoidal. They are especially useful for test purposes to study the frequency response of a PWM system. As an illustrative example, Figure 9.10 shows the waveforms of the input voltage and the inductor current under a sinusoidal low-frequency perturbation. Figure 9.10(a) shows the ac low-frequency sinusoidal component of the input voltage vi = Vim sin 𝜔t (9.65) superimposed on the dc component of the input voltage VI , resulting in the large-signal input voltage vI = VI + vi = VI + Vim sin 𝜔t. (9.66) The high-frequency waveform of the inductor current iLhf is depicted in Figure 9.10(b). Figure 9.10(c) shows the averaged low-frequency sinusoidal component of the inductor current il = Ilm sin 𝜔t (9.67) superimposed on the dc component IL , and the averaged low-frequency large-signal inductor current iL = IL + il = IL + Ilm sin 𝜔t. (9.68) The procedure for extracting the averaged dc and low-frequency components of the inductor current consists of two steps. First, the average values of the instantaneous high-frequency inductor current for every cycle of the switching frequency fs = 1∕T (also called local average values) are found as (k+1)T iL(av) (kT) = 1 T ∫kT iLhf dt (9.69) as shown in Figure 9.10(b) by the dashed lines. Second, the averaged low-frequency component of Figure 9.10(c) is obtained by connecting the average values in Figure 9.10(b), for example, in the middle or at the beginning of every cycle of the switching frequency fs = 1∕T. In reality, the low-frequency perturbation signal may be more complex. An example of such a signal is a ripple voltage of a frequency of 100 or 120 Hz on the rectified voltage obtained from a single-phase front-end bridge rectifier. According to Shannon’s sampling theorem, the frequency f of the perturbation signal must be less than or equal to one-half of the switching frequency fs , called the Nyquist frequency. As a result, the low-frequency dynamic models of PWM converters are valid only in the frequency range: 0 ≤ f ≤ fs ∕2. 382 Pulse-Width Modulated DC–DC Power Converters vI vi VI VI vI 0 (a) iL t hf 0 iL (b) t (c) t il IL IL iL 0 Figure 9.10 Waveforms of the input voltage and the inductor current under sinusoidal low-frequency small-signal perturbations for CCM. (a) Waveform of the input voltage. (b) Waveform of the high-frequency inductor current. (c) Waveform of the averaged low-frequency inductor current. If the dc independent external variables, such as the dc input voltage VI and/or the duty cycle D, are perturbed in a converter circuit at a low frequency f < fs ∕2, all other variables will vary around their corresponding dc levels at a low frequency f . As a result, the averaged voltages, currents, and duty cycle can be expressed as the sums of dc components and ac low-frequency components as follows: vSD = VSD + vsd (9.70) iS = IS + is (9.71) vLD = VLD + vld (9.72) iL = IL + il (9.73) vO = V O + vo (9.74) iD = ID + id (9.75) dT = D + d. (9.76) and The large-signal model shown in Figure 9.11(a) is nonlinear. Linearization of the large-signal averaged model at a given operating point can be performed by (1) expanding the large-signal nonlinear equations into a Taylor series Small-Signal Models of PWM Converters for CCM and DCM (1− D )VF dT iL S r + vSD + 383 iL dT vSD D (a) il d (1− D )VF ILd S Dil DIL + + vsdd + + VSDd + Dvsd + DVSD + D (b) r IL + iI D ILd (1− D )VF S Dil DIL (c) r IL + iI + + VSDd + + Dvsd + + DVSD D Figure 9.11 Averaged low-frequency large-signal and bilinear models of the actual switching network for two-switch PWM converters for CCM. (a) Averaged low-frequency large-signal nonlinear model. (b) Averaged low-frequency bilinear model. (c) Averaged dc and low-frequency small-signal model. 384 Pulse-Width Modulated DC–DC Power Converters about the operating point and (2) neglecting the higher-order terms. A linear small-signal model can be obtained by assuming small-signal perturbations, which allow us to take into account only the first-order terms. The assumption of the small-signal perturbation implies that the magnitudes of the ac low-frequency components are much lower than those of the corresponding dc components. Substituting (9.71), (9.73), and (9.76) into (9.54), one obtains a nonlinear equation IS + is = (D + d)(IL + il ) = DIL + Dil + IL d + il d. (9.77) The first term is the dc (or quiescent) component of the switch current IS , the second term is the time-varying switch current that is linearly related to the ac component of the inductor current il , and the third term is equal to the product of small-signal component of inductor current il and the small-signal component of the duty cycle d. The third term is a nonlinear term that produces nonlinear distortion,that is, harmonics of the switch current. For example, assume that il = Ilm sin 𝜔t and d = dm sin 𝜔t. Hence, ll d = Ilm dm sin2 𝜔t = 12 Ilm dm (1 − cos 2𝜔t). The operation given in (9.77) is equivalent to expanding (9.54) into a two-dimensional Taylor series around the dc operating point Q(D, IL ) and neglecting higher-order terms. Similarly, substitution of (9.70), (9.72), and (9.76) into (9.53) yields a nonlinear equation VLD + vld = (D + d)(VSD + vsd ) = DVSD + Dvsd + VSD d + vsd d. (9.78) The first term is the dc (or quiescent) component of the voltage across the diode VLD , the second term is the time-varying diode voltage that is linearly related to the ac component of the diode voltage vsd , and the third term is equal to the product of small-signal component of voltage vsd and the small-signal component of the duty cycle d. The last term is a nonlinear term that produces nonlinear distortion. Equations (9.77) and (9.78) can be represented by a circuit model of the actual switching network, shown in Figure 9.11(b). This model is nonlinear and is known as a bilinear model. 9.7.2 Linearization of Switching Network Model for CCM To linearize the nonlinear model of the converter switching network of Figure 9.11(b), let us assume that il d ≪ Dil (9.79) il d ≪ IL d (9.80) vsd d ≪ Dvsd (9.81) vsd d ≪ VSD d. (9.82) and Simplifying these inequalities, one obtains the small-signality conditions d≪D (9.83) il ≪ IL (9.84) vsd ≪ VSD . (9.85) and Neglecting the products of the small-signal components il d and vsd d in (9.77) and (9.78), one obtains a set of linear equations IS + is = DIL + Dil + IL d (9.86) VLD + vld = DVSD + Dvsd + VSD d. (9.87) and Small-Signal Models of PWM Converters for CCM and DCM 385 ILd r S + + VSDd + Dvsd il Dil vsd D (a) DIL (1− D)VF r S + VsD + DVSD IL D (b) Figure 9.12 Small-signal low-frequency and dc linear circuit models of the actual switching network for two-switch PWM converters for CCM. (a) Linear low-frequency small-signal circuit model of the actual switching network. (b) DC model of the actual switching network. This set of linear equations can be represented by a linear circuit model of the actual switching network for both dc and small-signal ac components depicted in Figure 9.11(c). Since this model is linear, the principle of superposition can be used to split the model of Figure 9.11(c) into a small-signal circuit model and a dc circuit model of the actual switching network, as shown in Figures 9.12(a) and (b), respectively. A circuit of the buck PWM converter is depicted in Figure 9.13(a). Figure 9.13(b) shows a small-signal lowfrequency model of the buck converter with parasitic components. This model can be obtained by replacing the actual switching network in the buck converter with the small-signal low-frequency model shown in Figure 9.12(a). For the buck converter, VSD = VI and vsd = vi . The dependent current sources can be split into two sets of current sources: one set in parallel with the input voltage source vi and the other set in parallel with the series combination of the dependent voltage sources, as shown in Figure 9.13(c). The parallel combination of the current sources and the voltage sources is equivalent to the voltage sources; therefore, the model may be simplified by neglecting the parallel dependent current sources, as shown in Figure 9.13(d). Figures 9.14 and 9.15 show small-signal models of the boost and buck–boost converters, respectively. For the boost converter, VSD = VO and vsd = vo . For the buck–boost converter, VSD = VI − VO and vsd = vi − vo , where VO < 0. 9.8 Block Diagram of Small-signal Model of PWM DC–DC Converters Figure 9.16 shows a block diagram of small-signal models for power stages of PWM dc–dc converters. There are three small-signal inputs d, vi , and io , where vi and io are disturbances and d is the control parameter used to 386 Pulse-Width Modulated DC–DC Power Converters S′ + vi L L ~ VI D′ ILd L r il + VI d ~ + VO + vo (a) Dil + vi RL C C + Dv i + vo RL rC (b) L r + vi + VI d ~ ILd Dil ILd Dil + il C RL rC Dvi + vo (c) L r + vi + ~ ILd VI d il Dil + Dvi C rC RL + vo (d) Figure 9.13 Small-signal low-frequency model of the buck PWM converter with parasitic components for CCM. (a) Circuit of the physical buck PWM converter. (b) Small-signal model of the buck converter. (c) Small-signal model of the buck converter with two sets of the dependent current sources. (d) Simplified small-signal model of the buck converter. control a converter against these disturbances. There are also two small-signal outputs vo and il . The small-signal ′ ′′ model may be described by six transfer functions: Tp = v′o ∕d, Mv = v′′o ∕vi , Zo = −v′′′ o ∕io , Tpi = il ∕d, Mvi = il ∕vi , and Ai = i′′′ ∕i . These transfer functions will be studied in subsequent chapters. o l 9.9 Family of PWM Converter Models for CCM The relationships among the averaged large-signal variables for the single-ended transformerless PWM converters operated in CCM are given by iL = iS iD = dT 1 − dT (9.88) Small-Signal Models of PWM Converters for CCM and DCM L + vi 387 S′ ~ C VI L RL + VO + vo RL + VO + vo D′ (a) S′ + vi ~ VI C L L D′ (b) S + vi C ~ Dil il L r ILd VO d Dvo + + rC RL + vo RL + vo D (c) L r Dvo VO d + + il + vi ~ C ILd Dil rC (d) Figure 9.14 Small-signal low-frequency model of the boost PWM converter with parasitic components for CCM. (a) Circuit of the physical boost PWM converter. (b) Alternative representation of the circuit of the physical boost PWM converter. (c) Small-signal model of the boost converter. (d) Simplified small-signal model of the boost converter. and vSD = vSL vLD = . dT 1 − dT (9.89) These relationships lead to six topologies of the averaged large-signal models of the ideal switching network for CCM, shown in Figure 9.17. Each topology contains one ideal current-dependent current source and one ideal voltage-dependent voltage source. Each current-dependent current source can be controlled by the current through one of the remaining branches. Similarly, each voltage-dependent voltage source can be controlled by one of the remaining interterminal voltages. Therefore, there are 24 pairs of descriptive combinations for the current and voltage dependent sources. These combinations are given in Table 9.1, and there are 24 averaged large-signal models of the ideal switching network. Only six of them are shown in Figure 9.17. The averaged resistances and the averaged offset voltage source can be added to each model to obtain an averaged large-signal model of the actual switching network. In each model, the large-signal quantities can be replaced by the dc component and the 388 Pulse-Width Modulated DC–DC Power Converters + Vsd + vsd S′ + + vi D′ L ~ VI C VO + vo RL IL + il L (a) S′ D′ + vsd + VSD d ≈(VI −VO) d Dil IL d vi Dvsd = D(vi − vo) + + ~ C + RL L il vo rC r (b) Figure 9.15 Small-signal low-frequency model of the buck–boost PWM converter with parasitic components for CCM. (a) Circuit of the physical buck-boost PWM converter. (b) Small-signal model of the buck–boost converter. Ai il′′′ Mvi il ′ ′ + il + il′ Tpi Zo io + vi vo′′′ Mv ~ d Figure 9.16 vo′′ + vo + vo′ Tp Block diagram of a small-signal model of PWM dc–dc converters. Small-Signal Models of PWM Converters for CCM and DCM vSL + S + vSD iS dT iL + iL + L vLD dT vSD vSL + S + + iL iS (1− dT) vSD vSD (1−dT) iL iD S + vSD D D (a) (b) + iS vSL 1− dT iD 1− dT iL + L S vLD vSL + + vSD iS + vSD iS vLD dT + L dT v 1− dT SL vLD dT i 1− dT D D D (c) (d) iS dT + vLD iD vSL + + iL iD S L iD vSL + + 389 iL + L S vLD vSL + + vSD iS + L + 1− dT iL v dT LD vLD 1− dT iS dT iD D (e) iD D (f) Figure 9.17 Family of averaged large-signal circuit models of the ideal switching network for basic two-switch PWM converters in CCM. ac component. Any of these models can be linearized to obtain an averaged small-signal model and a dc model in a similar manner to that shown in this chapter for the model of Figure 9.17(a). The same technique may also be used to derive models for transformer PWM converters (e.g., flyback or forward converters), multiple-switch converters (e.g., half-bridge, full-bridge, or push–pull converters), and for converters operating in the discontinuous conduction mode. 9.10 PWM Small-Signal Switch Model for CCM Figure 9.18 shows a PWM small-signal switch model for the switching network of all two-switch PWM converters [6,18]. The symbols a, p, and c denote the “active,” “passive,” and “common” terminals, respectively. In this model, D is the steady-state dc component of the on-duty cycle, Vap is the steady-state dc component of the voltage across 390 Pulse-Width Modulated DC–DC Power Converters Table 9.1 Descriptions of dependent sources in large-signal models of Figure 9.16 for CCM Model number Figure Current source Voltage source 1 2 9.16(a) dT iL dT i L dT vSD dT v 1−d SL dT i 1−dT D dT i 1−dT D 3 4 5 6 9.16(b) 1−dT i dT S 1−dT iS d 7 iD 1−dT iD 1−dT iS dT iS dT vSL 1−dT vLD dT vSL 1−dT vLD dT 9.16(d) dT iL dT iL dT vSD dT v 1−d SL 12 dT i 1−dT D dT i 1−dT D 15 16 vSL 1−dT vLD dT vSL 1−dT vLD dT 9.16(f) (1 − dT )iL (1 − dT )iL (1 − dT )vSD 1−dT vLD d 20 24 dT v 1−dT SL iD 1−dT iD 1−dT iS dT iS dT 19 23 T dT vSD 9.16(e) 18 21 22 T (1 − dT )vSD 9.16(c) 11 17 (1 − dT )vSD 1−dT vLD d 1−dT vLD dT 10 13 14 dT v 1−dT SL T 8 9 (1 − dT )iL (1 − dT )iL T dT vSD 1−dT i dT S 1−dT i dT S T (1 − dT )vSD 1−dT vLD dT the series combination of the active switch (a transistor) and the passive switch (a diode), that is, Vap = VSD , and IC is the steady-state dc component of the current flowing out of the common node, that is, the steady-state dc component of the inductor current IL . For a given operating point, Vap , D, and IC are constant quantities. The quantities d and ic are the small-signal duty cycle and the small-signal inductor current, respectively. As the frequency approaches zero, the transformer becomes a dc transformer, which is not a circuit-theory component. Substitution of the nonlinear switching network (a transistor and a diode) by its PWM small-signal model of Figure 9.18 gives the small-signal model of the entire power stage of a two-switch PWM converter. The small-signal model shown in Figure 9.18 and proposed in [18] has a different topology than that shown in Figure 9.12(a) and developed in [23, 24], even if the transformer in Figure 9.18 is replaced by dependent sources. Small-Signal Models of PWM Converters for CCM and DCM Vap d D a ic c + + IC d Vap 391 D 1 p Figure 9.18 A PWM small-signal switch model of the nonlinear switching network for basic two-switch PWM converters operating in CCM. 9.11 Modeling of Ideal Switching Network for DCM 9.11.1 Relationships Among DC Components for DCM Circuit models of PWM converters operated in DCM [19, 44] will be derived below. Let us consider the ideal switching network shown in Figure 9.2(b). Figure 9.19 shows the steady-state voltage waveforms in PWM converters for DCM. From Figure 9.1, the dc components of the terminal voltages (i.e., the average voltages) of the switching network can be expressed in terms of the converter dc input and output voltages VI and VO as follows: VSD = VI , VSL = VI − VO , and VLD = VO for the buck converter, VSD = VO , VSL = VI , VLD = VO − VI for the boost converter, and VSD = VI − VO = VI + |VO |, VSL = VI , VLD = −VO for the buck–boost and Ćuk converters. Referring to Figures 9.1 and 9.2, and neglecting the parasitic components rDS , RF , and VF , one can note that voltages vSL′ and vL′ D contain only dc components VSL′ and VL′ D , respectively, that is, vSL′ = VSL′ (9.90) vL ′ D = V L ′ D . (9.91) and Since the average inductor voltage VL(AV) = 0, the dc component of the voltage across the series combination of the switch and the inductor VSL′ is equal to the dc component of the switch voltage VSL VSL′ = VSL + VL(AV) = VSL . (9.92) The dc component of the voltage across the series combination of the diode and the inductor VDL′ is equal to the dc component of the diode voltage VLD VL′ D = VLD − VL(AV) = VLD . (9.93) By Kirchhoff’s voltage law (KVL), the inductor voltage can be expressed as vL = vSL′ − vSL = VSL′ − vSL = VSL − vSL (9.94) vL = vLD − vL′ D = vLD − VL′ D = vLD − VLD . (9.95) or For 0 < t ≤ DT, the switch is on, vSL = 0, and vL = VSL . (9.96) 392 Pulse-Width Modulated DC–DC Power Converters vSL VSD VSL 0 vLD DT D1T T t DT D1T T t DT D1T T t VSD VLD 0 vL VSL 0 −VLD Figure 9.19 Voltage waveforms in PWM converters for DCM. For DT < t ≤ (D + D1 )T, the diode is on, vLD = 0, and vL = −VLD . (9.97) For (D + D1 )T < t ≤ T, iL = 0, and therefore vL = 0. Hence, the voltage across the inductor can be summarized as follows: ⎧V , for ⎪ SL vL = ⎨−VLD , for ⎪0, for ⎩ 0 < t ≤ DT DT < t ≤ (D + D1 )T (D + D1 )T < t ≤ T (9.98) Small-Signal Models of PWM Converters for CCM and DCM 393 resulting in the inductor current t iL = V 1 v dt = SL t L ∫0 L L for 0 < t ≤ DT (9.99) from which the peak inductor current is found as ΔiL = iL (DT) = DVSL . fs L (9.100) Similarly, t iL = −VLD 1 (t − DT) vL dt = ∫ L DT L for DT < t ≤ (D + D1 )T. (9.101) The peak inductor current can also be calculated as follows: DT ΔiL = DT D V 1 1 iL dt = (−VLD )dt = 1 LD . ∫ ∫ L (D+D1 )T L (D+D1 )T fs L (9.102) Thus, V D1 = SL . D VLD (9.103) Figure 9.20 shows the steady-state current waveforms for DCM. The inductor current waveform is given by ⎧ ΔiL t, ⎪ DT iL = ⎨− ΔiL (t − DT), D T ⎪0, 1 ⎩ for for 0 < t ≤ DT DT < t ≤ (D + D1 )T for (D + D1 )T < t ≤ T (9.104) yielding the dc component of the inductor current T IL = D + D1 1 ΔiL . iL dt = ∫ T 0 2 The waveform of the switch current is described by { ΔiL t, for iS = DT 0, for 0 < t ≤ DT DT < t ≤ T (9.105) (9.106) which gives the dc component of the switch current T IS = 1 D i dt = ΔiL . T ∫0 S 2 (9.107) D2 VSL . 2fs L (9.108) Substitution of (9.100) into (9.107) yields IS = Similarly, the diode current waveform is given by ⎧0, ⎪ Δi iD = ⎨− D TL (t − DT), 1 ⎪0, ⎩ for for 0 < t ≤ DT DT < t ≤ (D + D1 )T for (D + D1 )T < t ≤ T (9.109) 394 Pulse-Width Modulated DC–DC Power Converters iL ΔiL IL 0 DT T D1 T t iS ΔiL IS 0 DT T t T t iD ΔiL ID 0 Figure 9.20 D1 T Current waveforms in PWM converters for DCM. resulting in the dc component of the diode current T ID = D 1 iD dt = 1 ΔiL . ∫ T 0 2 (9.110) Dividing (9.110) by (9.107), D ID = 1. IS D (9.111) Substituting (9.100) into (9.110), one obtains ID = D1 DVSL . 2fs L (9.112) Hence, using (9.103), one obtains 2 D2 VSL . (9.113) V D ID = SL = 1 . IS VLD D (9.114) ID = 2fs LVLD From (9.103) and (9.111), Small-Signal Models of PWM Converters for CCM and DCM 395 The voltage vSD across the series combination of the switch and the diode is not pulsating and is equal to its dc component VSD . Hence, the voltage across the switch is ⎧0, for ⎪ vSL = ⎨VSD , for ⎪VSL , for ⎩ 0 < t ≤ DT DT < t ≤ (D + D1 )T (D + D1 )T < t ≤ T (9.115) where VSL is the dc component of the voltage across the switch, and VSD is the dc component of the voltage across both the switch and the diode. This leads to the dc component of the voltage across the switch VSL = 1 (D + D1 )T ∫0 (D+D1 )T (D+D1 )T vSL dt = 1 (D + D1 )T ∫DT VSD dt = D1 V . D + D1 SD (9.116) The voltage across the diode is ⎧V , for ⎪ SD for vLD = ⎨0, ⎪VLD , for ⎩ 0 < t ≤ DT DT < t ≤ (D + D1 )T (D + D1 )T < t ≤ T (9.117) where VLD is the dc component of the voltage across the diode. The dc component of the diode voltage is VLD = 1 (D + D1 )T ∫0 (D+D1 )T vLD dt = 1 (D + D1 )T ∫0 DT VSD dt = D V . D + D1 SD (9.118) Dividing (9.118) by (9.116), one obtains V D1 = SL . D VLD (9.119) 9.11.2 Small-Signal Model of Ideal Switching Network for DCM Using relationship (9.108) for the dc components, one can write the identical relationship among the large-signal, slowly varying components iS = dT2 vSL 2fs L (9.120) where each large-signal component may be expressed as a sum of a dc component and an ac component iS = IS + is (9.121) vSL = VSL + vsl (9.122) dT = D + d. (9.123) and Substituting (9.121), (9.122), and (9.123) into (9.120), one obtains the switch current IS + is = (D + d)2 (VSL + vsl ) (D2 + 2Dd + d2 )(VSL + vsl ) = . 2fs L 2fs L (9.124) 396 Pulse-Width Modulated DC–DC Power Converters For d2 ≪ D2 , this equation can be approximated by IS + is ≈ (D2 + 2Dd)(VSL + vsl ) D2 VSL DVSL D2 D = + vsl + d+ v d. 2fs L 2fs L 2fs L fs L fs L sl (9.125) Neglecting the product of the small-signal component vsl d, one arrives at IS + is = D2 VSL DVSL V v D2 + v + d = Gi VSL + gi vsl + ki d = SL + sl + ki d 2fs L 2fs L sl fs L Ri ri (9.126) from which, one obtains the dc component of the switch current IS = V D2 VSL = SL 2fs L Ri (9.127) and the ac small-signal component of the switch current vsl + ki d ri (9.128) 2 VSL V 2f L V 1 ≡ SL = s2 = SL = Gi IS IS ID VLD D (9.129) 2 VSL v | 2f L V 1 ≡ sl || = s2 = SL = gi is |d=0 IS ID VLD D (9.130) 2I is || DVSL 2I V = S = D LD . = | d |vsl =0 fs L D DVSL (9.131) is = where Ri = ri = and ki ≡ Note that Ri = ri . Using (9.113), the relationship among the large-signal, slowly varying quantities is given by iD = dT2 v2SL (9.132) 2fs LvLD where each large-signal component can be expressed as a sum of a dc component and an ac component iD = ID + id (9.133) dT = D + d (9.134) vSL = VSL + vsl (9.135) vLD = VLD + vld . (9.136) Substitution of (9.133), (9.134), (9.135), and (9.136) into (9.132) yields ID + id = 2 + 2VSL vsl + v2sl ) (D2 + 2Dd + d2 )(VSL (D + d)2 (VSL + vsl )2 = . ( ) v 2fs L(VLD + vld ) 2f LV 1 + ld s LD VLD (9.137) Small-Signal Models of PWM Converters for CCM and DCM 397 Next, the following approximation can be made vld 1 vld ≈ 1 − VLD 1+ V for vld ≪ VLD . (9.138) LD Hence, for vsl ≪ VSL and d ≪ D, the terms d2 and v2sl can be neglected and relationship (9.137) can be approximated by ID + id ≈ 2 (D2 + 2Dd)(VSL + 2VSL vsl ) ( 1− 2fs LVLD vld VLD ) = 2 2 D2 VSL + 2D2 VSL vsl + 2DVSL d + 4DVSL vsl d 2fs LVLD ( 1− vld VLD ) . (9.139) Neglecting the small-signal component product vsl d, ID + id ≈ 2 D2 VSL 2fs LVLD + 2 2 2 DVSL D2 VSL DVSL D2 VSL D2 VSL vsl + d− v − v v − vsl d. ld sl ld 2 2 2 fs LVLD fs LVLD 2fs LVLD fs LVLD fs LVLD (9.140) Neglecting the terms containing the products of small-signal components vsl vld and vld d, one obtains ID + id ≈ = 2 D2 VSL 2fs LVLD 2 D2 VSL 2fs VLD + 2 2 DVSL D2 VSL D2 VSL vsl + d− vld 2 fs LVLD fs LVLD 2fs LVLD + gm vsl + ko d − go vld = 2 D2 VSL 2fs VLD + gm vsl + ko d − vld ro (9.141) from which ID = 2 D2 VSL (9.142) 2fs LVLD and id = gm vsl + ko d − vld ro (9.143) where gm ≡ id || D2 VSL 2I 2I = = D = S | vsl |d=0 and vld =0 fs LVLD VSL VLD (9.144) ko ≡ 2 DVSL 2I V id || 2I = = D = S SL d ||vsl =vld =0 fs LVLD D DVLD (9.145) 2 2 2fs LVLD VLD v | VLD 1 ≡ ld || = = = . 2 go id |d=0 and vsl =0 ID IS VSL D2 VSL (9.146) and ro = The combination of the dc and small-signal models of PWM converters for DCM described by (9.126) and (9.141) is shown in Figure 9.21(a). Figure 9.21(b) depicts a small-signal model of the PWM converters for DCM described by (9.128) and (9.143). Figure 9.21(c) shows a dc model of the PWM converters for DCM described by (9.127) and (9.142). 398 Pulse-Width Modulated DC–DC Power Converters S + VSL + vsl D D 2 VSL 2fs L + vsl ki d ri gmvsl D 2VSL2 ro ko d fs LVLD L r VF 1+ VLD VSL (a) D S + vsl gmvsl ki d ri ro ko d L r (b) S D + VSL D 2V SL 2fs L 2 D 2 VSL VLD 2fs LVLD + L r VF v 1 + LD vSL (c) Figure 9.21 model. Models of PWM converters for DCM. (a) DC and small-signal model. (b) Small-signal model. (c) DC 9.12 Averaged Parasitic Resistances for DCM Using (9.105), the rms values of the inductor, switch, and diode currents are √ √ √ T D + D1 1 4 2 = IL i dt = ΔiL ILrms = T ∫0 L 3 3(D + D1 ) √ √ √ T 1 D 4D 2 = IL i dt = ΔiL ISrms = T ∫0 S 3 3(D + D1 )2 (9.147) (9.148) Small-Signal Models of PWM Converters for CCM and DCM and √ IDrms = T 1 i2 dt = ΔiL T ∫0 D √ 399 √ D1 = IL 3 4D1 . 3(D + D1 )2 From (9.105) and (9.147), the power loss in the inductor resistance rL is ) ( D + D1 4 2 rL Δi2L = r I2. = PrL = rL ILrms 3 3(D + D1 ) L L (9.149) (9.150) The power loss in the inductor resistance rL may also be described in terms of the inductor average current IL and the averaged inductor resistance in the inductor branch rrLAV(L) PrLAV(L) = rLAV(L) IL2 . (9.151) Hence, using the law of conservation of energy, one arrives at the averaged inductor resistance connected in series with the inductor L rLAV(L) = 4rL . 3(D + D1 ) (9.152) The power loss in the switch on-resistance rDS is ( ) D 4D 2 PrDS = rDS ISrms r Δi2 = = r I2. 3 DS L 3(D + D1 )2 DS L (9.153) This power loss can also be expressed in terms of the dc inductor current IL as PrDSAV(L) = rDSAV(L) IL2 . (9.154) Thus, the switch averaged resistance in the inductor branch is rDSAV(L) = 4DrDS . 3(D + D1 )2 (9.155) The power loss in the diode forward resistance RF is ( ) 4D1 D1 2 RF Δi2L = R I2. PRF = RF IDrms = 3 3(D + D1 )2 F L (9.156) The power loss in the diode forward resistance can also be expressed in terms of the dc inductor current as PRFAV(L) = RFAV(L) IL2 . (9.157) Thus, the diode averaged resistance in the inductor branch is RFAV(L) = 4D1 RF . 3(D + D1 )2 (9.158) From (9.152), (9.155), and (9.158), one obtains the total averaged resistance connected in series with the inductor L 4 r = rLAV(L) + rDSAV(L) + RFAV(L) = 3(D + D1 ) ( Dr + D1 RF rL + DS D + D1 ) V ⎛ rDS + V SL RF ⎞ LD ⎟. = ( ) ⎜rL + V SL VSL ⎜ ⎟ + 1 3D V + 1 ⎝ ⎠ VLD LD 4 (9.159) 400 Pulse-Width Modulated DC–DC Power Converters L S + D+d ~ vi C VI RL + VO + vo io D (a) ki d ri + d vi ~ L r L S il + vsl gmvsl ko d ro C rC + RL vo io D (b) Figure 9.22 Small-signal model of PWM buck converter for DCM. (a) Buck converter. (b) Small-signal model for DCM. The power loss in the diode offset voltage is PVF = VF ID = D1 IL VF . D + D1 (9.160) On the other hand, this power may be written as PVFAV(L) = VFAV(L) IL . (9.161) Hence, the averaged diode offset voltage connected in series with the inductor L is VFAV(L) = D1 V V V = D F = V F . LD D + D1 F +1 +1 D1 (9.162) VSL Figures 9.22–9.24 depict small-signal models for buck, boost, and buck–boost converters for DCM operation, respectively. Figure 9.16 shows a block diagram of a small-signal model for a power stage of PWM dc–dc converters. 9.13 Summary r PWM converters are variable structure periodic systems. r The ideal switches can be replaced by dependent current or voltage sources. The strength of the dependent sources is determined by the dc components of the terminal currents, voltages, and duty cycle. r An ideal MOSFET can be modeled for dc components using an ideal dc current-dependent current source. r An ideal diode can be modeled for dc components using an ideal dc voltage-dependent voltage source. r An ideal switching network can be modeled for dc components using an ideal dc current-dependent current source and an ideal dc voltage-dependent voltage source. Small-Signal Models of PWM Converters for CCM and DCM 401 S + vi D+d ~ RL C VI + VO + vo io L L D (a) S + d vi + ~ vsl L ki d ri gmvsl C rC r d vi ~ RL vo io D (b) + vo ko d L L + RL ro gmvsl r ko d + vsl C ri ki d ro rC + io (c) Figure 9.23 Small-signal model of PWM boost converter for DCM. (a) Boost converter. (b) Small-signal model for DCM. (c) Small-signal model for boost converter with some components moved to the upper branches. r The MOSFET on-resistance r and the diode forward resistance R can be averaged using the law of conserDS F vation of energy. r The MOSFET on-resistance r and the diode forward resistance R can be also averaged by averaging the DS F MOSFET on-conductance gDS = 1∕rDS and the diode forward conductance GF = 1∕RF . r Large signal can be replaced by the dc and ac components. r The averaged transistor and diode resistances as well as the averaged offset voltage source can be moved to different branches using the reflection rules. r The averaged model of the actual switching network for the dc components can be transformed to a large-signal model by making all dc variables time dependent. r The large-signal model can be transformed into a bilinear model for both dc and small-signal ac components by neglecting nonlinear terms. 402 Pulse-Width Modulated DC–DC Power Converters S + vi D+d D ~ L C VI + VO + vo RL io L (a) D S + vsl + d vi ~ ri gmvsl ki d ko d ro C + RL L r vo io rC L (b) Figure 9.24 Small-signal model of PWM buck-boost converter for DCM. (a) Buck–boost converter. (b) Small-signal model for DCM. r The bilinear model can be simplified to a linear model for both dc and small-signal ac components. Since this model is linear, it can be split into a linear small-signal circuit model and a linear dc circuit model. r The small-signal model of PWM dc–dc converters is valid only at low frequencies ranging from dc to the Nyquist frequency fs ∕2. r The dc circuit model can be used to predict the open-loop and closed-loop converter behavior at dc. r The small-signal circuit model can be used to predict the open-loop and closed-loop small-signal dynamic performance and stability of a PWM dc–dc converter. r The dc and small-signal circuit models can be used in the design and simulation of PWM dc–dc power converters. References [1] G. W. Wester and R. D. Middlebrook, “Low-frequency characterization of switched dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-9, no. 3, pp. 376–385, May 1973. [2] R. D. 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Lischinsky-Arenas, “Differential algebra approach in non-linear dynamical compensator design for dc-to-dc power converters,” International Journal of Control, vol. 54, pp. 111–133, July 1991. [37] J. Sun, D. M. Mitchell, M. Greuel, P. T. Krein, and R. M. Bass, “Averaged modelling of PWM converters in discontinuous conduction mode: A reexamination,” IEEE Power Electronics Specialists Conference Record, pp. 615–622, June 1998. [38] J. Sun, D. M. Mitchell, M. Greuel, P. T. Krein, and R. M. Bass, “Averaged models of PWM converters in discontinuous conduction mode,” Proceedings of International High-Frequency Conversion Conference, November 1998, pp. 61–72. [39] V. A. Caliskin, G. C. Verghese, and A. M. Stanković, “Multifrequency averaging of dc/dc converters,” IEEE Transactions on Power Electronics, vol. 14, no. 1, pp. 124–133, January 1999. [40] A. Reatti and M. K. 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Small-Signal Models of PWM Converters for CCM and DCM 405 Review Questions 9.1 Draw an ideal switching network of single-ended PWM converters. 9.2 Draw an actual switching network of single-ended PWM converters. 9.3 Draw an averaged large-signal model of an ideal switch for CCM. 9.4 Draw an averaged large-signal model of an ideal diode for CCM. 9.5 Draw an averaged large-signal model of an ideal switching network for CCM. 9.6 Draw an averaged large-signal model of an actual switch for CCM. 9.7 Draw an averaged large-signal model of an actual diode for CCM. 9.8 Draw an averaged large-signal model of an actual switching network with all the components in original branches for CCM. 9.9 Draw a simplified averaged large-signal model of an actual switching network for CCM. 9.10 Draw a nonlinear (bilinear) model of an actual switching network for CCM. 9.11 Draw a small-signal model of an actual switching network for CCM. 9.12 Draw a dc model of an actual switching network for CCM. 9.13 What is the frequency range in which the averaged small-signal model of the switching network is valid? 9.14 Draw a PWM small-signal switch model for CCM. 9.15 Draw a dc model of the actual switching network for DCM. 9.16 Draw a small-signal model of the actual switching network for DCM. Problems 9.1 A single-ended transformerless PWM converter is operated under steady-state conditions in CCM. The duty cycle is D = 0.4. Find the components of an averaged model of the ideal switching network. 9.2 The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the original branches. 9.3 The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the inductor branch. 9.4 The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the switch branch. 9.5 The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the diode branch. 9.6 The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, rL = 0.2 Ω, and the duty cycle is D = 0.4. Find the total averaged parasitic resistance in the inductor branch. 406 Pulse-Width Modulated DC–DC Power Converters 9.7 The duty cycle of a single-ended transformerless PWM converter operated under steady-state conditions in CCM is D = 0.4 and the ESR of the inductor is rL = 0.2 Ω. Find the resistance of the inductor ESR in (a) the switch branch and (b) the diode branch. 9.8 A single-ended transformerless PWM converter operated under steady-state conditions in CCM has D = 0.4, VSD = 24 V, IL = 1.8 A, rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and rL = 0.2 Ω. Find the components of the small-signal model of the actual switching network with all parasitic elements in the inductor branch. 9.9 In the buck PWM converter with no parasitic components, the dc input voltage is turned on at t = 0. The inductance is high enough to operate the converter in CCM for steady state. Find the transient waveform of the inductor current without the switching-frequency component and its harmonics. 10 Small-Signal Characteristics of Buck Converter for CCM 10.1 Introduction In this chapter, small-signal characteristics are given for a power stage of the PWM buck converter operated in CCM [1–16]. A small-signal circuit model of the buck converter is developed using the small-signal model of the switching network. Subsequently, this model is used to derive a control law and open-loop transfer functions for the power stage of the buck converter, such as the control-to-output transfer function, the input-to-output transfer function, the input impedance, and the output impedance. In addition, the responses of the output voltage to step changes in the input voltage and the duty cycle are given. A dc circuit model is derived and is used to find the dc transfer functions and efficiency of the converter. All the converter performance characteristics are illustrated by examples. 10.2 Small-Signal Model of the PWM Buck Converter A circuit and a small-signal circuit model of the PWM buck converter for CCM operation are shown in Figure 10.1. This model can be obtained by (1) replacing the switching network in the complete circuit of the buck converter by the small-signal model and (2) reducing the dc components of the input voltage VI and the duty cycle D to zero. Notice that vsd = vi in the small-signal model of the switching network for the buck converter. From Figure 10.1, vo = 0 when VI d + Dvi = 0; therefore, the control law is d=− D v VI i (10.1) or d∕D = −vi ∕VI . Thus, the required relative change in the duty cycle d∕D is equal in magnitude and opposite in sign to the relative change in the input voltage vi ∕VI . Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 408 Pulse-Width Modulated DC–DC Power Converters L S + ~ vi D+d VI + RL C VO + vo io + vo io D (a) r + d + vi ~ Di I ILd + L il Dvi C RL rC VI d (b) Figure 10.1 Circuit and small-signal model of the open-loop PWM buck converter for CCM. (a) Circuit of the PWM buck converter. (b) Small-signal circuit model of the open-loop PWM buck converter for CCM. 10.3 Open-Loop Transfer Functions Figure 10.2 depicts a block diagram of the open-loop small-signal model of the PWM buck converter shown in Figure 10.1. It can be seen that both the small-signal model and the block diagram have three input variables d, vi , and io , and one output variable vo . Therefore, the converter is a multi-input single output (MISO) system. The small-signal duty cycle d is a control variable, whereas small-signal input voltage vi and the small-signal load current io are disturbances. The two transfer functions can be defined as the control-to-output transfer function Tp and the input-to-output transfer function Mv , respectively. In addition, two impedances can be defined: the input impedance Zi and the output impedance Zo . Zo io vi voIII MV ~ d Figure 10.2 + voII + vo voI Tp Block diagram of the open-loop small-signal model of the PWM converter. Small-Signal Characteristics of Buck Converter for CCM 409 The output voltage can be found using the principle of superposition. The responses from many excitations can be computed as the sum of the responses resulting from each excitation acting alone. Thus, vo = v′o + v′′o − v′′′ o = Tp d + Mv vi − Zo io . (10.2) Assuming a sinusoidal small-signal component of the duty cycle d(t) = dm cos(𝜔t + 𝜙d ) (10.3) v′o (t) = ∣ Tp (f ) ∣ dm cos[𝜔t + 𝜙Tp (f ) + 𝜙d ]. (10.4) the output voltage is Likewise, assuming a sinusoidal small-signal component of the input voltage vi (t) = Vim cos(𝜔t + 𝜙v ) (10.5) v′′o (t) = ∣ Mv (f ) ∣ Vim cos[𝜔t + 𝜙Mv (f ) + 𝜙v ]. (10.6) the output voltage is Assuming a sinusoidal small-signal component of the load current io (t) = Im cos(𝜔t + 𝜙i ) (10.7) v′′′ o (t) = − ∣ Zo (f ) ∣ Im cos[𝜔t + 𝜙Zo (f ) + 𝜙i ]. (10.8) the output voltage is Hence, the overall small-signal component of the output voltage is vo (t) = v′o (t) + v′′o (t) − v′′′ o (t) = ∣ Tp (f ) ∣ dm cos[𝜔t + 𝜙Tp (f ) + 𝜙d ] + ∣ Mv (f ) ∣ Vim cos[𝜔t + 𝜙Mv (f ) + 𝜙v ]− ∣ Zo (f ) ∣ Im cos[𝜔t + 𝜙Zo (f ) + 𝜙i ]. (10.9) The magnitudes |Tp (f )|, |Mv (f )|, and |Zo (f )| and the phases 𝜙Tp (f ), 𝜙Mv (f ), and 𝜙Zo (f ) are dependent on frequency. These magnitudes and phases are found in the subsequent analysis. 10.3.1 Open-Loop Control-to-Output Transfer Function Reducing the ac input voltage vi and the ac load current sink io to zero in the complete small-signal model of the buck converter of Figure 10.1, one obtains a small-signal model shown in Figure 10.3. This model is a single-input single-output (SISO) system and can be described by a control-to-output transfer function, also called a duty ratio-to-output voltage transfer function. The output voltage is vo (s) = VI d(s) Z2 (s) Z1 (s) + Z2 (s) (10.10) where Z1 (s) = r + sL (10.11) and Z2 (s) = 1 ) RL (rC + sC 1 RL + rC + sC . (10.12) 410 Pulse-Width Modulated DC–DC Power Converters vi = 0 Z1 io = 0 L r il d DiI ILd + VI d C + vo RL rC Z2 Figure 10.3 Small-signal model of the PWM converter for the derivation of the open-loop control-to-output transfer function Tp . Hence, one obtains the control-to-outputtransfer function of the PWM buck converter in the s-domain Tp (s) ≡ s + Cr1 v′ (s) VI RL rC vo (s) || Z2 (s) C = VI = = o | d(s) ||v =i =0 d(s) Z1 (s) + Z2 (s) L(RL + rC ) s2 + s C(RL rC +RL r+rC r)+L + i LC(RL +rC ) o 1 + 𝜔s s + 𝜔z VI RL rC VI RL s−z z = Tpx = = L(RL + rC ) (s − p1 )(s − p2 ) RL + r 1 + 2𝜉s + s2 s2 + 2𝜉𝜔0 s + 𝜔20 𝜔0 = Tpo RL +r LC(RL +rC ) (10.13) 𝜔20 1 + 𝜔s z 2 1 + Q𝜔s + 𝜔s 2 0 0 where Tpx = VI RL rC . L(RL + rC ) (10.14) The low-frequency value of Tp is Tpo = Tp (0) = VI RL 𝜔z L(RL + rC )𝜔20 = VI RL ≈ VI . RL + r (10.15) The angular natural frequency, also called the angular undamped frequency or the angular corner frequency, is √ √ RL + r 1 = √ = p1 p2 . (10.16) 𝜔0 = LC(RL + rC ) 𝜏C 𝜏L The time constants are 𝜏C = C(RL + rC ) (10.17) and 𝜏L = L . RL + r (10.18) Small-Signal Characteristics of Buck Converter for CCM 411 The damping ratio is L + C[RL (rC + r) + rC r] 𝜉= √ . 2 LC(RL + rC )(RL + r) The quality factor is (10.19) √ LC(RL + rC )(RL + r) 1 = . Q= 2𝜉 L + C[RL (rC + r) + rC r] (10.20) The ESR zero is z=− 1 . CrC (10.21) The angular frequency of the ESR zero is 𝜔z = −z = The poles are 1 . CrC (10.22) √ √ p1 , p2 = −𝜔0 𝜉 ± 𝜔0 𝜉 2 − 1 = −𝜔0 𝜉 ± j𝜔0 1 − 𝜉 2 = −𝜎 ± j𝜔d . (10.23) The damping factor is 𝜎 = 𝜔0 𝜉 = The angular damped frequency is 𝜔d = 𝜔0 √ √ 1 − 𝜉 2 = 𝜔0 1− 𝜔0 p + p2 =− 1 . 2Q 2 1 4Q2 (10.24) 𝜉 ≤ 1, for i.e., Q ≥ 1 . 2 (10.25) The converter model of Figure 10.3 is a low-pass filter. The time constants can be determined using the opencircuit time-constant method. Setting d = 0 and L = ∞ (i.e., an open circuit), one obtains an equivalent circuit comprised of the series combination of C, rC , and RL , whose time constant is 𝜏C = C(RL + rC ). Similarly, setting d = 0 and C = 0 (i.e., an open circuit) produces an equivalent circuit composed of a series combination of L, r, and RL , whose time constant is 𝜏L = L∕(RL + r). It can be seen that Tp is a second-order transfer function with two poles and one finite zero, all of which lie in the left-half of s-plane (LHP). The zero is real. The poles are real for 𝜉 ≥ 1 (i.e., for Q ≤ 12 ) or complex conjugates for 𝜉 < 1 (i.e., for Q > 12 ). Both poles are the same for 𝜉 = 1 (i.e., for Q = 12 ). The damping ratio 𝜉 decreases with increasing load resistance RL and increases with increasing parasitic resistances r and rC . The frequency of the zero fz is inversely proportional to rC . For rC = 0, fz = ∞. The frequency response can be found by setting 𝜎 = 0. In this case, s = j𝜔 and (10.13) becomes 1 + j 𝜔𝜔 z j𝜙 Tp (j𝜔) = Tpo ( )2 ( ) = ∣ Tp ∣ e Tp 𝜔 𝜔 1− 𝜔 + 2j𝜉 𝜔 (10.26) √ ( )2 √ √ 𝜔 √ 1 + √ 𝜔z ∣ Tp ∣ = Tpo √ √[ ( )2 ]2 ( )2 √ 1 − 𝜔𝜔 + 4𝜉 2 𝜔𝜔 (10.27) 0 where 0 0 0 412 Pulse-Width Modulated DC–DC Power Converters and ( 𝜙Tp = tan−1 𝜔 𝜔z ) ( ) ⎡ ⎤ 𝜔 2𝜉 ⎥ 𝜔0 −1 ⎢ − tan ⎢ ( )2 ⎥ ⎢1 − 𝜔 ⎥ ⎣ ⎦ 𝜔 for 𝜔 ≤1 𝜔0 (10.28) 0 or 𝜙Tp = −180◦ + tan−1 ( 𝜔 𝜔z ) ( ) ⎡ ⎤ 𝜔 2𝜉 ⎥ 𝜔0 −1 ⎢ − tan ⎢ ( )2 ⎥ ⎢1 − 𝜔 ⎥ ⎣ ⎦ 𝜔 for 𝜔 > 1. 𝜔0 (10.29) 0 Note that 𝜙Tp (0) = 0. For fz ≫ f0 , the peak of ∣ Tp ∣ is obtained by setting the derivative of the quantity under the square-root sign to zero. This peak occurs at √ √ 1 1 1 2 fpk = f0 1 − 2𝜉 = f0 1 − for 𝜉 < √ or Q > √ (10.30) 2Q2 2 2 and is equal to ∣ Tp(pk) ∣ = Tpo Tpo Q = √ . √ 2𝜉 1 − 𝜉 2 1 − 12 (10.31) 4Q At f = f0 for fz ≫ f0 , ∣ Tp (f0 ) ∣ = Tpo 2𝜉 = QTpo . (10.32) √ √ The frequency response does not exhibit a peak for 𝜉 ≥ 1∕ 2 ≈ 0.707 or Q ≤ 1∕ 2 ≈ 0.707 at fz ≫ f0 . Figure 10.4 shows idealized Bode plots of Tp . The decreasing slope of 𝜙Tpi due to the second-order term with two complex conjugate poles in the denominator is (−90◦ ∕𝜉)/decade. The increasing slope of 𝜙Tpi due to the first-order term in the nominator (i.e., a zero) is 45◦ /decade. Using expressions for L and C given in Chapter 2, we have for C = Cmin(on) ΔiLmax = VO (1 − Dmin ) fs Lmin (10.33) rCmax = fs Lmin Vr Vr = ΔiLmax (1 − Dmin )VO (10.34) D (1 − Dmin )VO Dmax = max 2 2fs rCmax 2fs Lmin Vr √ ( ) fs Vr 1 1 f0max(on) = = √ 𝜋 2Dmax (1 − Dmin ) VO 2𝜋 Lmin Cmin(on) √ ( ) √ fs √ Vr 1 = √ for C = Cmin(on) . ( ) ( ) √ V V 𝜋 2 VO O 1− O Cmin(on) = VImin VImax (10.35) (10.36) Small-Signal Characteristics of Buck Converter for CCM 413 Tp Tpo ≈ VI −40 dB/dec fz 0 f0 f −20 dB/dec (a) φTp f0 0 fz f0 10 ξ −90° f 10fz −180° 10 ξf0 fz 10 (b) Figure 10.4 Idealized Bode plots of the control-to-output transfer function Tp for the buck converter (without the delay). (a) ∣ Tp ∣ versus f . (b) 𝜙Tp versus f . The maximum frequency of the zero is fzmax(on) = fs 1 = . 2𝜋rCmax Cmin(on) 𝜋Dmax (10.37) Cmin(off ) = (1 − Dmin )2 VO 1 − Dmin = 2fs rCmax 2fs2 Lmin Vr (10.38) For C = Cmin(off ) , and √ fs f0max(off ) = = √ 𝜋(1 − Dmin ) 2𝜋 Lmin Cmin(off ) 1 Vr 2VO for C = Cmin(off ) . (10.39) Thus, the corner frequency f0 is directly proportional to the switching frequency fs . Typical values of f0 are in the range from 0.01fs to 0.02fs . The maximum frequency of the zero is fzmax(off ) = fs 1 . = 2𝜋rCmax Cmin(off ) 𝜋(1 − Dmin ) (10.40) Thus, fz is directly proportional to the switching frequency fs . Typical values of fz are in the range from 0.06fs to 0.08fs . 414 Pulse-Width Modulated DC–DC Power Converters Example 10.1 A buck converter has the following specifications: continuous conduction mode (CCM), nominal input voltage VInom = 28 V, minimum input voltage VImin = 24 V, maximum input voltage VImax = 32 V, output voltage VO = 14 V, minimum output current IOmin = 0.14 A, maximum output current IOmax = 1.4 A, switching frequency fs = 100 kHz, converter efficiency at full power 𝜂 = 90%, and the maximum peak-to-peak value of the ripple voltage on the dc output voltage to be Vr ∕VO ≤ 1%. Calculate r, Tpx , Tpo , fz , f0 , 𝜉, Q, |Tp(pk) |, |Tp (f0 )|, p1 , p2 , and fd at VInom , Dnom , and RLmin . Draw Bode plots of the control-to-output transfer function Tp . Solution: The calculated values of the minimum and the maximum load resistance are RLmin = 10 Ω and RLmax = 100 Ω. The calculated maximum, minimum, and nominal duty cycles are Dmax = 0.6481, Dmin = 0.4861, and Dnom = 0.555. For CCM, the minimum value of the inductor is Lmin = 256.95 μH. The inductor was made using a Phillips ferrite pot core 2616 PA A00 3C8 and using 15 turns of Belden solid copper magnet wire with AWG 26. The measured inductance was L = 301 μH and the measured dc ESR of the inductor was rL = 0.05 Ω. The maximum value of the ESR is rCmax = 0.5857 Ω. Pick rC = 0.4 Ω. The minimum calculated filter capacitance is Cmin = 8.1 μF. The standard value of 47 μF was chosen as the filter capacitance, and the measured capacitance was 51.2 μF with the ESR of rC = 0.391 Ω. The switching components used were an International Rectifier power MOSFET IRF 530 (200V/9A) with on-resistance rDS = 0.18 Ω and a Motorola power diode MUR 820 (200V/8A) with RF = 0.022 Ω and VF = 0.7 V. For Dnom = 0.555, rDS = 0.18 Ω, RF = 22 mΩ, and rL = 0.05 Ω, the equivalent resistance in series with inductor is r = Dnom rDS + (1 − Dnom )RF + rL = 0.555 × 0.18 + (1 − 0.555) × 0.022 + 0.05 = 0.1 + 0.01 + 0.05 = 0.16 Ω. (10.41) For VInom = 28 V, L = 301μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, Dnom = 0.555, and rC = 0.391 Ω, one obtains V R r 28 × 10 × 0.391 Tpx = Inom Lmin C = = 35, 003 V (10.42) L(RLmin + rC ) 301 × 10−6 (10 + 0.391) Tpo = Tp (0) = (10.44) 1 1 = = 7.95 kHz 2𝜋CrC 2 × 𝜋 × 51.2 × 10−6 × 0.391 (10.45) √ 1 f0 = 2𝜋 (10.43) 1 1 = −49.952 krad∕s =− CrC 51.2 × 10−6 × 0.391 z=− fz = VInom RLmin 28 × 10 = = 27.559 V = 28.8 dBV RLmin + r 10 + 0.16 RLmin + r 1 = LC(RLmin + rC ) 2𝜋 √ 10 + 0.16 = 1.2677 kHz 301 × 10−6 × 51.2 × 10−6 × (10 + 0.391) 𝜔0 = 2𝜋f0 = 2𝜋 × 1.2677 × 103 = 7.965 krad∕s (10.46) (10.47) C[R (r + r) + rC r] + L 51.2 × 10−6 [10 × (0.391 + 0.16) + 0.391 × 0.16] + 301 × 10−6 𝜉 = √ Lmin C = = 0.2298 √ 2 LC(RLmin + rC )(RLmin + r) 2 301 × 10−6 × 51.2 × 10−6 × (10 + 0.391)(10 + 0.16) (10.48) Small-Signal Characteristics of Buck Converter for CCM Q= 1 1 = = 2.1758 2𝜉 2 × 0.2298 (10.49) √ √ fpk = f0 1 − 2𝜉 2 = 1.2677 1 − 2 × 0.22982 = 1.2677 × 0.9457 = 1.199 kHz |Tp(pk) | = Tpo 27.599 = = 61.7 V = 35.8 dBV √ √ 2𝜉 1 − 𝜉 2 2 × 0.2298 1 − 0.22982 ∣ Tp (f0 ) ∣ = Tpo 2𝜉 415 (10.50) (10.51) = QTpo = 2.1758 × 27.599 = 60.05 V = 35.57 dBV (10.52) √ p1 , p2 = −𝜔0 𝜉 ± j𝜔0 1 − 𝜉 2 = −𝜎 ± j𝜔d = −2 × 𝜋 × 1.2677 × 103 × 0.2298 √ ±j2 × 𝜋 × 1.2677 × 103 × 1 − 0.22982 = −1830.4 ± j7752 rad∕s (10.53) √ √ fd = f0 1 − 𝜉 2 = 1.2677 × 103 1 − 0.22982 = 1.2338 kHz. (10.54) and Figures 10.5 and 10.6 show the Bode plots of the magnitude ∣ Tp ∣ and the phase shift 𝜙Tp of the control-to-output transfer function Tp for VInom = 28 V, Dnom = 0.555, L = 301μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. At low frequencies, the magnitude ∣ Tp ∣ is equal to 28.8 dB, next it increases to reach 35.8 dB at the frequency f = 1.23 kHz, and then it decreases at approximately −40 dB per decade up to fz = 7.95 kHz and at approximately −20 dB per decade for frequencies above fz . The magnitude ∣ Tp ∣ crosses 0 dB at f = 7.95 kHz. 40 30 | Tp| (dBV) 20 10 0 −10 −20 −30 1 10 Figure 10.5 2 10 3 10 f (Hz) 4 10 5 10 The magnitude of the control-to-output transfer function Tp for the buck converter without the delay. 416 Pulse-Width Modulated DC–DC Power Converters 0 −30 p φT (°) −60 −90 −120 −150 1 10 Figure 10.6 2 3 10 4 10 f (Hz) 10 5 10 The phase of the control-to-output transfer function Tp without the delay. The phase shift 𝜙Tp initially decreases from zero to reach a minimum value of −145.95◦ at f = 3.18 kHz and then increases to −90◦ . The −3dB bandwidth is BW = 1.8 kHz. The corner frequency f0 is almost independent of the load resistance RL . In contrast, the damping ratio 𝜉 and the quality factor Q strongly depend on the load resistance RL . The damping ratio 𝜉 decreases with increasing load resistance RL . At RLmax = 100 Ω, f0 = 1.2812 kHz, 𝜉 = 0.12553, and Q = 3.9831. √ The parasitic resistances rC and r slightly affect the value of f0 . At rC = 0 and r = 0, f0 = 1∕(2𝜋 LC) = 1.2827 kHz at any load resistance RL . Conversely, the damping ratio 𝜉 is significantly affected by the presence of √ the parasitic resistances. At rC = 0 and r = 0, 𝜉 = L∕C∕(2RL ) = 0.1212 and Q = 4.1254 at RLmin = 10 Ω and 𝜉 = 0.01212 and Q = 41.254 at RLmax = 100 Ω. At RLmin , 𝜉actual ∕𝜉approx = 0.2298∕0.1212 = 1.896. Therefore, the parasitic resistances cannot be neglected for calculating 𝜉 and Q. 10.3.2 Delay in Control-to-Output Transfer Function There is a delay td caused by power MOSFET, MOSFET driver, and pulse-width modulator. The delay can be represented by the function Td = e−std , which is not a rational function. It can be approximated by a first-order Padé function in the frequency range from dc to fs ∕2 st Td (s) = e −std ≈ 1 − 2d st 1 + 2d =− s − t2 d s + t2 d =− s − 𝜔zd s + 𝜔pd (10.55) where 𝜔zd = 𝜔pd = 2 td (10.56) Small-Signal Characteristics of Buck Converter for CCM 417 and fzd = fpd = 1 . 𝜋td (10.57) For s = j𝜔, j𝜔td 2 Td (j𝜔) = j𝜔t 1 + 2d 1− where = 1 − 𝜔j𝜔 zd 1 + 𝜔j𝜔 = |Td |ej𝜙Td (10.58) pd √ √ ( )2 √ √ 1 + 𝜔td √ 2 |Td | = √ ( )2 = 1 √ 𝜔td 1+ 2 and ( 𝜙Td = −2 arctan 𝜔td 2 ) ( = −2 arctan 𝜔 𝜔pd (10.59) ) ( = −2 arctan f fpd ) . (10.60) The magnitude of the delay transfer function is equal to 1 at all frequencies. The phase of this transfer function is zero at low frequencies, starts to decrease at fpd ∕10, crosses −90◦ at fpd , reaches −180◦ at 10fpd , and then is equal to −180◦ . For example, for td ∕Ts = td fs = 0.1, fpd = 10fs ∕𝜋 ≈ 3.18fs and the phase of Td starts to decrease at fpd ∕10 = fs ∕𝜋 ≈ 0.318fs . Figures 10.7 and 10.8 depict Bode plots of Td given by the first-order Padé approximation versus f for td ∕Ts = 0.1 and fs = 100 kHz. | Td | 2 1 0 1 10 Figure 10.7 2 10 3 10 4 f (Hz) 10 5 10 6 10 Magnitude of the delay function Td for td ∕Ts = 0.1 and fs = 100 kHz. 418 Pulse-Width Modulated DC–DC Power Converters 0 −30 d φT (°) −60 −90 −120 −150 −180 2 10 Figure 10.8 3 4 10 5 10 6 10 f (Hz) 10 7 8 10 10 Phase of the delay function Td for td ∕Ts = 0.1 and fs = 100 kHz. The control-to-output transfer function that takes into account the delay is given by Tp = −Tpx s + 𝜔z s − t2 d s2 + 2𝜉𝜔0 s + 𝜔20 s + 2 t = −Tpx d s + 𝜔z s − 𝜔zd . 2 s+𝜔 2 s + 2𝜉𝜔0 s + 𝜔0 pd (10.61) Figures 10.9 and 10.10 show Bode plots of Tp without and with the delay td = 1 μs. The phase of this transfer function has more negative values at high frequencies f > 0.1fpd as compared to that without the delay. 10.3.3 Open-Loop Input-to-Output Transfer Function Setting d = 0 and io = 0 in the complete small-signal model of the buck converter of Figure 10.1, one obtains a small-signal model shown in Figure 10.11. It is a single-input single-output (SISO) system and can be used to derive an input-to-output transfer function, also called a line-to-output voltage transfer function, or an audio susceptibility. Physically, this transfer function describes the input-to-output noise transmission. From Figure 10.11, the output voltage is vo (s) = Dvi (s) Z2 (s) . Z1 (s) + Z2 (s) (10.62) Hence, using (10.13), the input-to-output transfer function is derived as s + Cr1 v′′o (s) DRL rC vo (s) || Z2 (s) D C =D = T (s) = Mv (s) ≡ = | vi (s) ||d=i =0 vi (s) Z1 (s) + Z2 (s) VI p L(RL + rC ) s2 + s C(RL rC +RL r+rC r)+L + LC(RL +rC ) o = Mvx s + 𝜔z s2 + 2𝜉𝜔0 s + 𝜔20 = Mvo 1 + 𝜔s z 2 1 + 2𝜉s + 𝜔s 2 𝜔0 0 RL +r LC(RL +rC ) (10.63) Small-Signal Characteristics of Buck Converter for CCM 419 40 30 | T p| (dBV) 20 10 0 −10 −20 −30 1 10 2 3 10 10 f (Hz) 4 5 10 10 Figure 10.9 Bode plot of the magnitude of Tp without and with the delay for td = 1 μs and fs = 100 kHz, that is, for td ∕Ts = 0.1. 0 td = 0 t = 1 μs d −30 p φT (°) −60 −90 −120 −150 1 10 Figure 10.10 td ∕Ts = 0.1. 2 10 3 10 f (Hz) 4 10 5 10 Bode plot of the phase of Tp without and with the delay for td = 1 μs and fs = 100 kHz, that is, for 420 Pulse-Width Modulated DC–DC Power Converters d=0 io = 0 Z1 ii il + vi L r ~ Dil + Dvi Zi C rC Z + RL vo Z2 Figure 10.11 Small-signal model of the PWM converter for the derivation of the open-loop input-to-output transfer function Mv and the open-loop input impedance Zi . where DRL rC L(RL + rC ) Mvx = (10.64) and Mvo = Mv (0) = DRL ≈ D. RL + r (10.65) Notice that Mv is a second-order transfer function with two poles and one zero in the LHP. The magnitude |Mv | is independent of VI and increases with increasing D; therefore, the worst case occurs at the maximum value of D. Physically, this observation is obvious because the longer the switch is on, the larger the amount of noise is transmitted from the line to the converter output. Figure 10.12 shows idealized Bode plots of Mv . Example 10.2 For the buck converter specified in Example 10.1, calculate Mvo at VInom , Dnom , and RLmin . Also, draw Bode plots of Mv . Solution. At f = 0, Mvo = Mv (0) = Dnom RLmin 0.555 × 10 = = 0.5463 = −5.252 dB. RLmin + r 10 + 0.16 (10.66) Bode plots of Mv are shown in Figures 10.13 and 10.14 for VInom = 28 V, D = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The −3dB bandwidth is BW = 1.8 kHz. 10.3.4 Open-Loop Input Impedance The open-loop input impedance of the converter can be derived using the model of Figure 10.11. The current through the inductor is Dvi Z1 + Z2 (10.67) D2 vi D2 vi = Z Z1 + Z2 (10.68) il = resulting in the input current ii = Dil = Small-Signal Characteristics of Buck Converter for CCM 421 Mv fz f0 0 f Mvo −40 dB/dec −20 dB/dec (a) φM v 0 f0 fz f0 10 ξ −90° f 10 fz −180° 10 ξf0 fz 10 (b) Figure 10.12 Idealized Bode plots of the input-to-output transfer function Mv . (a) |Mv | versus f . (b) 𝜙Mv versus f . 10 0 | Mv| (dB) −10 −20 −30 −40 −50 −60 1 10 Figure 10.13 2 10 3 10 f (Hz) 4 10 5 10 Bode plot of the magnitude of the input-to-output transfer function Mv ∣ Mv ∣ ej𝜙Mv for the buck converter. 422 Pulse-Width Modulated DC–DC Power Converters 0 −30 v φM (°) −60 −90 −120 −150 1 10 Figure 10.14 2 3 10 4 10 f (Hz) 5 10 10 Bode plot of the phase of the input-to-output transfer function Mv ∣ Mv ∣ ej𝜙Mv for the buck converter. where Z = Z1 + Z2 . Hence, using (10.11) and (10.12), one obtains the open-loop input impedance of the buck converter s +s v (s) || Z +Z Z L = 2 = 1 2 2 = 2 Zi (s) ≡ i | ii (s) ||d=i =0 D D D 2 C(RL rC +RL r+rC r)+L R +r + LC(RL +r ) LC(RL +rC ) L C o L s + 2𝜉𝜔0 s + 𝜔0 = 2 = Zio s + 𝜔cr D 2 2 1 + 𝜔2𝜉 s + ( 0 s 𝜔0 )2 s + C(R 1+r ) L C 1 + 𝜔s (10.69) cr where Zio = Zi (0) = Rio (0) = L𝜔20 D2 𝜔cr = Z(0) RL + r = D2 D2 (10.70) and 𝜔cr = 1 . C(RL + rC ) (10.71) Example 10.3 For the converter specified in Example 10.1, calculate fcr and Zi (0) at VInom , Dnom , and RLmin . Draw the plots of Zi versus frequency. Solution: Using (10.71), fcr = 1 1 = 299 Hz. = 2𝜋C(RL + rC ) 2 × 𝜋 × 51.2 × 10−6 × (10 + 0.391) (10.72) At f = 0, Zio = Zi (0) = RL + r 10 + 0.16 = = 32.98 Ω. 2 D 0.5552 (10.73) Small-Signal Characteristics of Buck Converter for CCM 423 100 90 80 70 | Zi| (Ω) 60 50 40 30 20 10 0 1 10 Figure 10.15 resistance RL . 2 10 3 4 10 f (Hz) 5 10 10 The magnitude of the open-loop input impedance Zi of the buck converter loaded by the load Figures 10.15 and 10.16 show plots of Zi for VInom = 28 V, Dnom = 0.555, L = 301 μH, C = 51.2 μF, RL = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Notice that the equivalent circuit for the input impedance shown in Figure 10.11 contains a series resonant circuit. For this reason, the plots of the input impedance of the buck converter shown in Figure 10.15 are similar to those of the impedance for the series resonant circuit. At high frequencies, the input impedance is approximately equal to the reactance of the inductance, which increases with frequency. 10.3.5 Open-Loop Output Impedance Figure 10.17 shows a small-signal model for the derivation of the open-loop output impedance of the buck converter including the load resistance RL . This model is obtained by setting vi = 0, d = 0, and io = 0 in the complete smallsignal model of the buck converter of Figure 10.1. To find the output impedance, one can apply a test voltage source vt across the load resistance RL and determine the current it forced by the test voltage source. The ratio of the voltage vt to the current it is equal to the output impedance Zo . Thus, using (10.11) and (10.12), one arrives at the open-loop output impedance of the buck converter loaded by the load resistance RL r rC+L s2 + s Cr LC + r rLC RL rC v (s) || C C Zo (s) ≡ t | = Z1 ∥ Z2 = it (s) ||v =d=i =0 RL + rC s2 + s C(RL rC +RL r+rC r)+L + RL +r i LC(RL +rC ) o = LC(RL +r) ( )( ) s + r 1C s + Lr RL rC C RL + rC s2 + s C(RL rC +RL r+rC r)+L + LC(RL +rC ) RL +rC LC(RL +rC ) )( ) s 1 + (s + 𝜔z )(s + 𝜔rl ) RL r 𝜔rl z = Zox = ( )2 2 2 R + r s + 2𝜉𝜔0 s + 𝜔0 L 1 + 𝜔2𝜉 s + 𝜔s ( 1 + 𝜔s 0 0 (10.74) 424 Pulse-Width Modulated DC–DC Power Converters 90 60 i φZ (°) 30 0 −30 −60 1 10 Figure 10.16 2 3 10 4 10 f (Hz) 5 10 10 The phase of the open-loop input impedance Zi of the buck converter loaded by the load resistance RL . where Zox = RL rC RL + rC (10.75) r . L (10.76) and 𝜔rl = For s = 0, Zoo = Zo (0) = Ro (0) = RL ||r = RL r ≈r RL + r for r ≪ RL . (10.77) Z1 r vi = 0 d=0 io = 0 it L rC RL t C Z2 Figure 10.17 + ~ v Zo Small-signal model of the PWM converter for the derivation of the open-loop output impedance Zo . Small-Signal Characteristics of Buck Converter for CCM 425 At high frequencies, Zo (∞) = RL ||rC = RL rC ≈ rC RL + rC for rC ≪ RL . (10.78) Since vt = vo and it = −io , the output impedance is Zo (s) ≡ v (s) vt (s) =− o . it (s) io (s) (10.79) Example 10.4 For the buck converter specified in Example 10.1, calculate frl and Zo (0) at VInom , Dnom , and RLmin . Also, draw the plots of Zo versus frequency. Solution: From (10.76), frl = 0.16 r = = 84.6 Hz. 2𝜋L 2 × 𝜋 × 301 × 10−6 (10.80) At f = 0, Ro (0) = Zo (0) = Zoo = RLmin r 10 × 0.16 = = 157 mΩ. RLmin + r 10 + 0.16 (10.81) Figures 10.18 and 10.19 show plots of Zo for VInom = 28 V, Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The maximum value of the open-loop output impedance ∣ Zo ∣ occurs at frequency f0 = 1.2677 kHz and is equal to ∣ Zo ∣ = 5.2 Ω. At f = 100 Hz, ∣ Zo ∣ = 264 mΩ. It can be seen in Figure 10.17 that the output impedance is formed by a parallel resonant circuit. This is consistent with the plots shown in Figure 10.18. 6 5 | Zo| (Ω) 4 3 2 1 0 1 10 Figure 10.18 2 10 3 10 f (Hz) 4 10 5 10 The magnitude of the open-loop output impedance Zo of the buck converter. 426 Pulse-Width Modulated DC–DC Power Converters 90 60 o ϕZ (°) 30 0 −30 −60 1 10 Figure 10.19 2 3 10 10 f (Hz) 4 10 5 10 The phase of the open-loop output impedance Zo of the buck converter. 10.4 Open-Loop Step Responses 10.4.1 Open-Loop Response of Output Voltage to Step Change in Input Voltage Suppose that there is a step change in the input voltage of magnitude ΔVI at time t = 0 for fixed duty cycle D and load resistance RL . The total input voltage is described by vI (t) = VI (0− ) + ΔVI u(t) (10.82) where u(t) is the unit step function and VI (0− ) is the steady-state input voltage before the step change. The step change of the input voltage in the time domain is given by vi (t) = vI (t) − VI (0− ) = ΔVI u(t). (10.83) The step change of the input voltage in the s-domain is vi (s) = ΔVI . s (10.84) Using (10.63) and (10.84), one obtains the transient component of the output voltage of the open-loop buck converter in the s-domain vo (s) = Mv (s)vi (s) = 𝜔2 s + 𝜔z ΔVI Mv (s) . = ΔVI Mvo 0 s 𝜔z s(s2 + 2𝜉𝜔0 s + 𝜔20 ) (10.85) The pole of vo (s) at s = 0 produces a constant term and the two complex-conjugate poles produce a sinusoidal term in vo (t); therefore, vo (t) is composed of a constant and a sinusoid. The inverse Laplace transform of (10.85) gives Small-Signal Characteristics of Buck Converter for CCM 427 the transient component of the output voltage of the open-loop buck converter in the time domain vo (t) = −1 {vo (s)} √ ( ) ( )2 −𝜉𝜔 t ⎡ (√ )⎤ 𝜔0 𝜔0 e 0 ⎢ + sin 1 − 𝜉 2 𝜔0 t + 𝜙 ⎥ = ΔVI Mvo 1 + 1 − 2𝜉 √ ⎢ ⎥ 𝜔z 𝜔z 1 − 𝜉2 ⎣ ⎦ where ⎛ √1 − 𝜉 2 ⎞ ⎟ + tan−1 ⎜ 𝜔z − 𝜉 ⎟ ⎠ ⎝ 𝜔0 (√ ⎛ √1 − 𝜉 2 ⎞ ⎟ + tan−1 𝜙 = 2𝜋 + tan−1 ⎜ 𝜔z ⎟ ⎜ − 𝜉 ⎠ ⎝ 𝜔0 (√ −1 ⎜ 𝜙 = 𝜋 + tan and 1 − 𝜉2 𝜉 1 − 𝜉2 𝜉 ) for t≥0 (10.86) for fz ≥𝜉 f0 and 𝜉 ≤ 1 (10.87) for fz <𝜉 f0 and 𝜉 ≤ 1. (10.88) ) For f0 ≪ fz , the step response is critically damped for 𝜁 = 1. The total output voltage is vO (t) = VO (0− ) + vo (t), t≥0 for (10.89) (0− ) is the output voltage at time t = 0− , that is, just before the step change in the input voltage. where VO Taking the derivative of (10.86) with respect to 𝜔0 t and setting the result to zero, one obtains √ √ 𝜉 cos( 1 − 𝜉 2 𝜔0 t + 𝜙) − √ sin( 1 − 𝜉 2 𝜔0 t + 𝜙) = 0 1 − 𝜉2 √ √ sin 𝜃 sin( 1 − 𝜉 2 𝜔0 t + 𝜙) = 0 cos( 1 − 𝜉 2 𝜔0 t + 𝜙) − cos 𝜃 √ √ cos 𝜃 cos( 1 − 𝜉 2 𝜔0 t + 𝜙) − sin 𝜃 sin( 1 − 𝜉 2 𝜔0 t + 𝜙) = 0 √ cos( 1 − 𝜉 2 𝜔0 tm + 𝜙 + 𝜃) = 0 where ( 𝜃 = tan 𝜉 (10.90) (10.91) (10.92) (10.93) ) . (10.94) (2n + 1) 𝜋2 − 𝜙 − 𝜃 √ 1 − 𝜉2 (10.95) −1 √ 1 − 𝜉2 From (10.93), the maxima and minima of vo occur at 𝜔0 tm = where n is an integer. Since or ⎛ √1 − 𝜉 2 ⎞ 3𝜋 −1 ⎜ ⎟ + tan 𝛾 =𝜙+𝜃 = ⎜ 𝜔z − 𝜉 ⎟ 2 ⎠ ⎝ 𝜔0 for fz ≥ 𝜉, f0 (10.96) ⎛ √1 − 𝜉 2 ⎞ 5𝜋 −1 ⎜ ⎟ 𝛾 =𝜙+𝜃 = + tan ⎜ 𝜔z − 𝜉 ⎟ 2 ⎠ ⎝ 𝜔0 for fz < 𝜉, f0 (10.97) 428 Pulse-Width Modulated DC–DC Power Converters (10.95) becomes ⎡ ⎛ √1 − 𝜉 2 ⎞⎤ (2n + 1) 𝜋2 − 𝛾 1 −1 ⎜ ⎢ ⎟⎥ = (n − 1)𝜋 − tan √ √ ⎜ 𝜔z − 𝜉 ⎟⎥ 1 − 𝜉2 1 − 𝜉 2 ⎢⎣ ⎝ 𝜔0 ⎠⎦ for fz ≥𝜉 f0 (10.98) ⎡ ⎛ √1 − 𝜉 2 ⎞⎤ (2n + 1) 𝜋2 − 𝛾 1 −1 ⎜ ⎟⎥ ⎢ (n − 2)𝜋 − tan = √ 𝜔0 tm = √ ⎜ 𝜔z − 𝜉 ⎟⎥ 1 − 𝜉2 1 − 𝜉 2 ⎢⎣ ⎠⎦ ⎝ 𝜔0 for fz < 𝜉. f0 (10.99) 𝜔0 tm = or The first maximum of vo is the highest one and occurs for n = 2. Thus, 3𝜋 ⎡ ⎛ √1 − 𝜉 2 ⎞⎤ ⎡ ⎛ √1 − 𝜉 2 ⎞ ⎤ −𝛾 1 1 2 −1 −1 ⎟⎥ = √ ⎢− tan ⎜ ⎢tan ⎜ ⎟⎥ 𝜔0 tm = √ = √ ⎜ 𝜔z − 𝜉 ⎟⎥ ⎜ 𝜉 − 𝜔z ⎟⎥ 2 ⎢ 1 − 𝜉2 1 − 𝜉 2 ⎢⎣ 1 − 𝜉 𝜔 𝜔 ⎣ ⎠⎦ ⎝ 0 ⎝ 0 ⎠⎦ for fz <𝜉 f0 (10.100) or ⎡ ⎛ √1 − 𝜉 2 ⎞⎤ −1 ⎜ ⎟⎥ ⎢ 𝜔0 tm = √ 𝜋 − tan = √ ⎜ 𝜔z − 𝜉 ⎟⎥ 1 − 𝜉2 1 − 𝜉 2 ⎢⎣ ⎠⎦ ⎝ 𝜔0 5𝜋 −𝛾 2 1 for fz ≥ 𝜉. f0 Substitution of (10.100) or (10.101) into (10.86) gives ) √ (√ 1 − 𝜉 2 𝜔0 t + 𝜙 = 1 − 𝜉 2 sin and yields the highest maximum of vo √ ⎡ vomax = ΔVI Mvo ⎢1 + ⎢ ⎣ ( 1 − 2𝜉 𝜔0 𝜔z ) ( + 𝜔0 𝜔z (10.101) (10.102) )2 ⎤ e−𝜉𝜔0 tm ⎥ ⎥ ⎦ resulting in the maximum overshoot of the transient component of the output voltage vo √ ( ) ( )2 𝜔0 𝜔0 vomax vomax − vo (∞) + = Smax ≡ − 1 = 1 − 2𝜉 e−𝜉𝜔0 tm vo (∞) ΔVI Mvo 𝜔z 𝜔z (10.103) (10.104) where vo (∞) = ΔVI Mvo is the final steady-state value of the transient small-signal component of the output voltage vo after the transition. Figure 10.20 shows the percent maximum overshoot as a function of fz ∕f0 at fixed values of 𝜉. For fz ∕f0 > 3, Smax is nearly independent of fz ∕f0 . However, for fz ∕f0 ≤ 3, Smax increases as fz ∕f0 decreases. For fz ∕f0 ≫ 𝜉, the poles are dominant, ⎛ √1 − 𝜉 2 ⎞ ⎟≈0 ⎜ 𝜔z − 𝜉 ⎟ ⎠ ⎝ 𝜔0 −1 ⎜ tan (10.105) and (10.98) can be approximated by (n − 1)𝜋 𝜔0 tm ≈ √ . 1 − 𝜉2 (10.106) This approximation usually holds true for Tp and Mv of a buck converter. The highest maximum of vo occurs for n = 2 at 𝜋 𝜔0 tm ≈ √ . (10.107) 1 − 𝜉2 Small-Signal Characteristics of Buck Converter for CCM 429 1 10 ξ = 0.1 0 10 0.3 0.5 −1 Smax 10 0.7 −2 0.8 −3 0.9 10 10 −4 10 −1 0 10 Figure 10.20 1 10 fz/ f0 10 Maximum percent overshoot as a function of fz ∕f0 at fixed values of 𝜉. Substitution of (10.107) into (10.103) produces the maximum output voltage √ ( ) ( )2 ⎡ ⎤ √ fz 𝜔0 𝜔0 2 ⎢ + vomax = ΔVI Mvo 1 + 1 − 2𝜉 e−𝜋𝜉∕ 1−𝜉 ⎥ for >𝜉 ⎢ ⎥ 𝜔z 𝜔z f0 ⎣ ⎦ and 𝜉 ≤ 1 (10.108) yielding the maximum overshoot √ v − vo (∞) v Smax ≡ omax = omax − 1 = vo (∞) ΔVI Mvo ( 1 − 2𝜉 𝜔0 𝜔z ) ( + 𝜔0 𝜔z )2 √ 2 e−𝜋𝜉∕ 1−𝜉 for fz > 𝜉 and 𝜉 ≤ 1. (10.109) f0 This expression can be approximated by √ Smax ≈ e−𝜋𝜉∕ 1−𝜉 2 for fz ≫ f0 . (10.110) The maximum relative transient ripple of the total output voltage is defined as 𝛿max ≡ vomax − vo (∞) vOmax − vO (∞) = vO (∞) vO (∞) (10.111) where vO (∞) = VO (0− ) + vo (∞) = VO (0− ) + Mvo ΔVI is the final steady-state value of the total output voltage after the transition. The ±5% settling time is ( ( ) ) √ √ 1 1 ts = − ln 0.05 1 − 𝜉 2 = − ln 0.05 1 − 𝜉 2 . (10.112) 𝜔0 𝜉 𝜎 430 Pulse-Width Modulated DC–DC Power Converters The delay time is 1 + 0.7𝜉 𝜔0 (10.113) 0.8 + 2.5𝜉 . 𝜔0 (10.114) td ≈ and the rise time is tr ≈ Example 10.5 For the open-loop buck converter specified in Example 10.1, draw the waveform of the output voltage vO that is a response to the step change in the input voltage vI from 28 to 29 V. Calculate (a) the maximum overshoot of the transient component of the output voltage, (b) the steady-state values of the transient component and the total output voltage, and (c) the maximum relative transient ripple of the total output voltage. Solution: Figure 10.21 shows a step response of the output voltage vO to a step change in the input voltage vI from 28 to 29 V, which corresponds to a step change of vi from 0 to 1 V, for the buck converter without feedback at Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The output voltage increases from 14 to 14.8 V and reaches its final steady-state value of vO (∞) = 14.55 V after approximately 3 ms. From Example 10.1, 𝜉 = 0.2298, fz = 7.95 kHz, and f0 = 1.2677 kHz. Because fz ∕f0 = 6.27 ≫ 𝜉 = 0.2298, 𝜋 𝜋 𝜔0 tm ≈ √ = √ = 3.228 rad = 184.95◦ 2 1 − 𝜉2 1 − 0.2298 (10.115) 14.9 14.8 14.7 vO (V) 14.6 14.5 14.4 14.3 14.2 14.1 14 0 0.5 1 1.5 t (ms) 2 2.5 3 Figure 10.21 Step response of vO to a step change in vI from 28 to 29 V for the buck converter without feedback for Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Small-Signal Characteristics of Buck Converter for CCM 431 yielding tm = 3.228∕(2𝜋f0 ) = 3.228∕(2𝜋 × 1262.7) = 0.4053 ms. For the same reason, equation (10.109) can be used to calculate the maximum overshoot of the transient component of the output voltage vo √ ( ) ( )2 √ f f vomax − vo (∞) 2 = 1 − 2𝜉 0 + 0 e−𝜋𝜉∕ 1−𝜉 Smax ≡ vo (∞) fz fz √ ) ( ) ( √ 1.2677 2 −𝜋×0.2298∕ 1−0.22982 1.2677 + = 1 − 2 × 0.2298 e = 46.47%. (10.116) 7.95 7.95 Using (10.66), one obtains the steady-state value of the transient component of the output voltage vo (∞) = ΔVI Mvo = 1 × 0.5463 = 0.5463 V. (10.117) The maximum value of the transient component of the output voltage is vomax = (1 + Smax )vo (∞) = (1 + 0.4647) × 0.5463 = 0.8 V. (10.118) The steady-state value of the total output voltage is vO (∞) = VO (0− ) + vo (∞) = 14 + 0.5463 = 14.5463 V. (10.119) Hence, the maximum relative transient ripple of the output voltage is vomax − vo (∞) 0.8 − 0.5463 0.2537 = = = 1.74%. vO (∞) 14.5463 14.5463 (10.120) ts = − ) ( √ 1 ln 0.05 1 − 0.22982 = 1.65 ms. 1830.4 (10.121) td ≈ 1 + 0.7𝜉 1 + 0.7 × 0.2298 = 0.146 ms = 𝜔0 2𝜋 × 1, 267.7 (10.122) 0.8 + 2.5𝜉 0.8 + 2.5 × 0.2298 = 0.176 ms. = 𝜔0 2𝜋 × 1, 267.7 (10.123) 𝛿max = The ±5% settling time is The delay time is and the rise time is tr ≈ 10.4.2 Open-Loop Response of Output Voltage to Step Change in Duty Cycle Let us assume that there is a step change in the duty cycle ΔdT at time t = 0 for fixed input voltage VI and load resistance RL . The total duty cycle is dT (t) = D + ΔdT u(t). (10.124) The step change in the duty cycle in the time domain is given by d(t) = dT (t) − D = ΔdT u(t) (10.125) which results in d(s) = ΔdT . s (10.126) 432 Pulse-Width Modulated DC–DC Power Converters Hence, using (10.13), the transient component of the output voltage of the open-loop buck converter in the s-domain is vo (s) = Tp (s)d(s) = ΔdT Tp (s) s = ΔdT Tpo 𝜔20 s + 𝜔z . 2 𝜔z s(s + 2𝜉𝜔0 s + 𝜔20 ) (10.127) The inverse Laplace transform gives the output voltage of the open-loop buck converter in the time domain vo (t) = −1 {vo (s)} √ ( ) ( )2 −𝜉𝜔 t ⎤ ⎡ √ 𝜔0 𝜔0 e 0 + = ΔdT Tpo ⎢1 + 1 − 2𝜉 sin( 1 − 𝜉 2 𝜔0 t + 𝜙)⎥ √ ⎥ ⎢ 𝜔z 𝜔z 1 − 𝜉2 ⎦ ⎣ for t≥0 (10.128) where 𝜙 is given by (10.87). The total output voltage vO can be found from (10.89). The maximum overshoot of vo is given by (10.104) or (10.109). Example 10.6 For the open-loop buck converter specified in Example 10.1, draw the waveform of the output voltage vO that is a response to the step change in the duty cycle dT from 0.555 to 0.655. Solution: Figure 10.22 shows a step response of the output voltage vO to a step change in the control input dT from 0.555 to 0.655, for d = 0.1 for the buck converter without feedback at VI = 28 V, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The output voltage vO increases from 14 V to a peak value of 18.05 V and then reaches a final steady-state value of approximately 16.75 V after 3 ms. 18.5 18 17.5 vO (V) 17 16.5 16 15.5 15 14.5 14 0 0.5 1 1.5 t (ms) 2 2.5 3 Figure 10.22 Step response of vO to a step change in the duty cycle dT from 0.555 to 0.655 for the buck converter without feedback for VInom = 28 V, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Small-Signal Characteristics of Buck Converter for CCM 433 Since Tpo = 27.559 V, the final steady-state value of the transient component of the output voltage is vo (∞) = ΔdT Tpo = 0.1 × 27.559 = 2.7559 V. (10.129) The first maximum occurs at tm = 0.4053 ms. The maximum overshoot is given by (10.116) and is Smax = 0.4647. Therefore, the maximum value of the transient component of the output voltage is vomax = (1 + Smax )vo (∞) = (1 + 0.4647) × 2.7559 = 4.0366 V. (10.130) The final total output voltage is vO (∞) = VO (0− ) + vo (∞) = 14 + 2.7559 = 16.7559 V. (10.131) Thus, the maximum relative transient ripple of the output voltage is 𝛿max = vomax − vo (∞) 4.0366 − 2.7559 = = 7.64%. vO (∞) 16.7559 (10.132) 10.4.3 Open-Loop Response of Output Voltage to Step Change in Load Current Consider a step change in the load current ΔIO at time t = 0 for fixed input voltage VI and duty cycle D. The total load current is described by iO (t) = IO (0− ) + ΔIO u(t). (10.133) Hence, the step change in the load current in the time domain is io (t) = iO (t) − IO (0− ) = ΔIO u(t) (10.134) and in the s-domain is ΔIO . s This results in the transient component of the output voltage in the s-domain io (s) = vo (s) = −Zo (s)io (s) = − ΔIO RL rC (s + 𝜔z )(s + 𝜔rl ) RL + rC s(s2 + 2𝜉𝜔0 s + 𝜔20 ) (10.135) (10.136) and in the time domain vo (t) = −1 {vo (s)} for t ≥ 0. (10.137) The total output voltage vO (t) can be found from (10.89). Example 10.7 For the open-loop buck converter given in Example 10.1, draw the waveform of the output voltage vO that is a response to the step change in the load current IO from 1.4 to 1.5 A. Calculate the output voltage for steady state after the transition and the maximum relative transient ripple. Solution: Figure 10.23 shows a step response of the output voltage vO to a step change in the load current iO from 1.4 to 1.5 A for the buck converter without feedback at VI = 28 V, D = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The output voltage vO decreases from 14 V to a minimum value of 12.82 V and then reaches a final steady-state value of approximately 13.98 V after 3 ms. The dc output resistance is Zo (0) = Ro (0) = RLmin r∕(RLmin + r) = 0.157 Ω. The change in the steady-state output voltage is vo (∞) = −Ro (0)ΔIO = −0.157 × 0.1 = −15.7 mV (10.138) 434 Pulse-Width Modulated DC–DC Power Converters 14.1 14.05 vO (V) 14 13.95 13.9 13.85 13.8 0 0.5 1 1.5 t (ms) 2 2.5 3 Figure 10.23 Step response of vO to a step change in the load current IO from 1.4 to 1.5 A for the buck converter without feedback for VInom = 28 V, D = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. yielding the output voltage after the transition vO (∞) = VO (0− ) + vo (∞) = 14 − 0.0157 = 13.9843 V. (10.139) The step change of vo at t = 0 is Δvo (0) = −rC ΔIO = −0.391 × 0.1 = −0.0391 V. (10.140) From Figure 10.23, vomin = 190 mV, yielding the maximum undershoot of the output voltage Smax = |vomin | − |vo (∞)| 190 − 15.7 = = 11.1% |vo (∞)| 15.7 (10.141) and the maximum relative transient ripple of the output voltage 𝛿max = |vomin | − |vo (∞)| 0.19 − 0.0157 = = 1.25%. vO (∞) 13.9843 (10.142) 10.5 Open-Loop DC Transfer Functions Figure 10.24 shows a dc model of the buck converter, which is obtained by replacing the switching network in the complete buck converter circuit by a dc model, replacing the inductance L with a short circuit, and replacing the filter capacitor branch with an open circuit. Notice that VSD = VI . From Figure 10.24, the dc output voltage is [ ] ) ( V RL V RL RL 1 VF = VI D − (1 − D) F = VI D 1 + F − VO = [DVI − (1 − D)VF ] RL + r VI RL + r VI D VI RL + r (10.143) Small-Signal Characteristics of Buck Converter for CCM (1− D)VF II VI + DIL Figure 10.24 435 IL = IO r RL DVI + VO DC model of the PWM buck converter. which gives the dc input-to-output voltage transfer function of the lossy buck converter at fixed value of VI is ] [ V (1 − D)VF RL . (10.144) MVDC ≡ O = D − VI VI RL + r Hence, MVDC = 0 at Dmin = V 1 I +1 VF . (10.145) For D = 1, MMDC = RL < 1. RL + r (10.146) Substituting VI = VO ∕MVDC into (10.144), one obtains the dc voltage transfer function at a fixed value of the output voltage VO MVDC = D (1−D)V 1 + Rr + V F L O . (10.147) Since the dc input current is II = DIL and the output current is IO = IL , the dc current transfer function is obtained as MIDC ≡ IO 1 = . II D (10.148) This function is independent of r and VF . Using (10.147) and (10.148), the converter efficiency is obtained as 𝜂≡ VO IO M 1 = MVDC MIDC = VDC = . (1−D)VF r VI II D 1+ + RL (10.149) VO For D = 0, r = RF + rL and the efficiency is given by 𝜂= 1 1+ RF +rL V + VF RL O . (10.150) As D approaches 1, r = rDS + rL and the efficiency becomes 𝜂= 1 . r +r 1 + DSR L L (10.151) 436 Pulse-Width Modulated DC–DC Power Converters Equations (10.147) and (10.149) show that the dc voltage transfer function is MVDC = 𝜂D. (10.152) The dc duty cycle-to-output voltage transfer function is TPDC = VO ∕D = 𝜂VI . (10.153) Switching losses are neglected in the above equations. 10.6 Summary r A small-signal model of the PWM buck converter can be derived by replacing its switching network by a small-signal model, and reducing the dc component of the input voltage source VI and the dc component of the duty cycle D to zero. r A dc model of the PWM buck converter can be derived by replacing its switching network by a dc model, and reducing the ac component of the input voltage source vi and the ac component of the duty cycle d to zero. r The small-signal model has three inputs (the duty cycle d, the input voltage v , and the load current i ) and one i o output (the output voltage vo ). r A small-signal model of the buck converter can be simplified to obtain appropriate models to derive open-loop transfer functions and impedances. r The control-to-output transfer function of the PWM buck converter is a second-order low-pass function with two poles and one zero located in the left half of the s-plane. r The poles are real for 𝜉 ≥ 1 (i.e., Q ≤ 0.5), and the poles are complex conjugate for 𝜉 ≤ 1 (i.e., Q > 0.5). At 𝜉 = 1 (i.e., Q = 0.5), the poles are real and equal. √ √ r The magnitudes of the transfer functions |T | and |M | exhibit peaking for 𝜉 < 1∕ 2 (i.e., Q > 1∕ 2). p v r The maximum overshoot of step responses to step changes of d and v is zero for 𝜉 ≥ 1 (i.e., Q ≤ 0.5). i r The step responses exhibit ringing for 𝜉 < 1∕4 (i.e., Q > 2). References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched–Mode Power Conversion, vols. I and II. Pasadena, CA: TESLAco, 1981. [2] R. D. Middlebrook and S. Ćuk, “A general unified approach to modeling switching–converter power stages,” IEEE Power Electronics Specialists Conference Record, 1976, pp. 18–34. [3] W. M. Polivka, P. R. K. Chetty, and R. D. Middlebrook, “State–space average modeling of converters with parasitics and storage time modulation,” IEEE Power Electronics Specialists Conference Record, 1980, pp. 119–143. [4] R. P. Severns and G. Bloom, Modern DC–to–DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985, pp. 30–42 and 130–135. [5] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw–Hill, 1988, pp. 74–76. [6] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, ch. 10, 2nd Ed. New York: John Wiley and Sons, pp. 301–353. [7] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading: Addison–Wesley, 1991, pp. 251–402. [8] V. Vorpérian, “Simplified analysis of PWM converters using the PWM switch, Part I: Continuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES–26, pp. 497–505, May 1990. [9] D. Czarkowski and M. K. Kazimierczuk, “Circuit models of PWM dc-dc converters,” Proceedings of the IEEE National Aerospace and Electronics Conference (NEACON’92), Dayton, OH, May 8–22, 1992, pp. 407–413. Small-Signal Characteristics of Buck Converter for CCM 437 [10] D. Czarkowski and M. K. Kazimierczuk, “Linear circuit models of PWM flyback and buck/boost converters,” IEEE Transactions on Circuits and Systems, Part I, Fundamental Theory and Applications, vol. CAS-39, pp. 688-693 August 1992. [11] D. Czarkowski and M. K. Kazimierczuk, “A new and systematic method of modeling PWM dc-dc converters,” Proceedings of the International Conference on Systems Engineering, Kobe, Japan, September 17–19, 1992, pp. 628–631. [12] D. Czarkowski and M. K. Kazimierczuk, “Static- and dynamic-circuit models of PWM buck-derived dc-dc converters,” IEE Proceedings Part G: Circuits, Devices and Systems, vol. 139, no. 6, pp. 669–679 December 1992. [13] D. Czarkowski and M. K. Kazimierczuk, “Energy-conservation approach to modeling PWM dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-29, pp. 1059-1063 July 1993. [14] M. K. Kazimierczuk and D. Czarkowski, “Application of the principle of energy conservation to modeling the PWM converters,” Proceedings of the 2nd IEEE Conference on Control Applications, Vancouver, Canada, September 13–16, 1993, pp. 291–296. [15] M. K. Kazimierczuk, N. Sathappan, and D. Czarkowski, “A voltage-mode-control PWM buck dc-dc converter with a proportional controller,” Proceedings of the IEEE National Aerospace and Electronic Conference (NAECON’93), Dayton, OH, May 24–28, 1993, vol. 2, pp. 639–644. [16] A. Ayachit and M. K. Kazimierczuk, “Open-loop small-signal transfer functions of the quadratic buck PWM dc-dc converter in CCM,” 40th Annual Conference of the IEEE Industrial Electronics Society (IECON14), October 29-November 1, 2014, Dallas, TX, pp. 1643–1649. Review Questions 10.1 Draw a small-signal model of the PWM buck converter. 10.2 Draw a dc model of the PWM buck converter. 10.3 Derive a control law for the PWM buck converter. 10.4 Draw a small-signal model for the PWM buck converter for deriving the open-loop control-to-output transfer function. 10.5 Derive an open-loop small-signal control-to-output transfer function for the buck converter. 10.6 What is the order of the open-loop control-to-output transfer function? 10.7 What is the location of the poles and the zero of the open-loop control-to-output transfer function in the s-plane? 10.8 Draw a small-signal model of the PWM buck converter for deriving the open-loop input-to-output transfer function. 10.9 Derive an open-loop small-signal input-to-input transfer function for the buck converter. 10.10 What is the physical meaning of the input-to-output transfer function. 10.11 Draw a small-signal model of the PWM buck converter for deriving the open-loop input impedance. 10.12 Derive the open-loop input impedance for the buck converter. 10.13 Explain the behavior of the input impedance versus frequency. 10.14 Draw a small-signal model of the PWM buck converter for deriving the open-loop output impedance. 10.15 Derive the open-loop output impedance for the buck converter. 10.16 Explain the behavior of the output impedance versus frequency. 438 Pulse-Width Modulated DC–DC Power Converters Problems 10.1 An open-loop buck converter has VInom = 28 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 mΩ, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine z, fz , f0 , 𝜉, Q, p1 , p2 , and fd . 10.2 An open-loop buck converter has VImin = 24 V, VInom = 28 V, VImax = 32 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine Tpo . 10.3 An open-loop buck converter has VImin = 24 V, VInom = 28 V, VImax = 32 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine fpk and |Tp(pk) |. 10.4 An open-loop buck converter has VImin = 24 V, VInom = 28 V, VImax = 32 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine Mvo , fpk , and |Mv(pk) |. 10.5 An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine fcr and Zi (0). 10.6 An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine frl , Zo (0), and Zo (∞). 10.7 An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmax = 12 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine the approximate values of f0 , 𝜉, and Q. Find also the ratio of the actual to approximate values of 𝜉. 10.8 An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmax = 12 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine the values of f0 , 𝜉, Q, p1 , p2 , and fd . 10.9 An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmax = 12 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine the approximate values of 𝜉 and Q. Calculate also the ratio of the actual to approximate values of 𝜉. 10.10 An open-loop buck converter has VInom = 28 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 mΩ, VO = 12 V, RLmin = 100 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine Tpo , z, fz , f0 , 𝜉, Q, p1 , p2 , and fd . 10.11 An open-loop buck converter has VInom = 28 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 mΩ, VO = 12 V, RLmin = 100 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. There is a step change of the input voltage from 28 to 29 V. Determine Smax , vo (∞), vOmax , and 𝛿max . 11 Small-Signal Characteristics of Boost Converter for CCM 11.1 Introduction The aims of this chapter are: (1) to introduce dc and small-signal linear circuit models of the PWM boost dc–dc converter, taking into account parasitic resistances of reactive components and power switches and also the offset voltage of the power diode; (2) to derive and illustrate the dc voltage transfer function and efficiency using the dc model; and (3) to derive and illustrate the small-signal open-loop control-to-output transfer function, input-tooutput transfer function, input impedance, and output impedance using the small-signal model. Responses of the output voltage to step changes in the duty cycle, input voltage, and load current are also given. The dynamics of the PWM boost converter has been studied in [1–14]. 11.2 DC Characteristics A dc model of the boost converter is shown in Figure 11.1. This model can be derived by replacing switching devices in the boost converter with the dc model of the actual switching network, the inductance L with a short circuit, and the capacitance C with an open circuit. The equivalent resistance in the inductor branch is r = DrDS + (1 − D)RF + rL . (11.1) Since the battery representing the diode offset voltage VF is moved to the inductor branch, VSD = VO . (11.2) II = IL . (11.3) II − DII − IO = 0 (11.4) In addition, Using the KCL, Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 440 Pulse-Width Modulated DC–DC Power Converters DVSD = DVo (1 − D)VF r + IL D VI + VO DIL Figure 11.1 DC model of the PWM boost converter. which gives the dc current transfer function IO = 1 − D. II (11.5) VO IO = . 1 − D (1 − D)RL (11.6) MI DC ≡ Since IO = VO ∕RL , II = IL = Using the KVL, VI − VF (1 − D) − rIL + DVO − VO = 0 (11.7) which yields VO = [ VI ]. V r (1 − D) 1 + VF + (1−D) 2R O (11.8) L Hence, one obtains the dc input-to-output voltage transfer function MV DC ≡ VO 1 1 = VI 1 − D 1 + VF + VO (11.9) r (1−D)2 RL and the dc control-to-output transfer function TP DC ≡ VO VI = [ V D D(1 − D) 1 + F + VO r (1−D)2 RL ]. (11.10) From (11.5) and (11.9), the efficiency of the converter is 𝜂≡ IO VO 1 = MI DC MV DC = (1 − D)MV DC = V II VI 1+ F + VO r RL (1−D)2 . (11.11) Switching losses are neglected in this equation. Figures 11.2 and 11.3 show the dc voltage transfer function MV DC and the efficiency 𝜂 as a function of D at RL = 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω. 11.3 Open-Loop Control-to-Output Transfer Function A small-signal model of the PWM boost converter for CCM operation is shown in Figure 11.4(a). This model is obtained by replacing the switching network in the boost converter with a small-signal model. Figure 11.4(b) shows a block diagram of the open-loop boost converter. Setting vi = 0 and io = 0 in Figure 11.4(a), one obtains a Small-Signal Characteristics of Boost Converter for CCM 441 6 5 M VDC 4 3 2 1 0 0 0.2 0.4 D 0.6 0.8 1 Figure 11.2 DC voltage transfer function MV DC as a function of the duty cycle D at RL = 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω. 1 0.9 0.8 0.7 η 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 D 0.6 0.8 1 Figure 11.3 Efficiency 𝜂 as a function of the duty cycle D at RL = 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω. 442 Pulse-Width Modulated DC–DC Power Converters L r Dvo VO d + + il + vi d C ~ + vo RL ILd Dil rC io (a) Zo io vi vo″ MV ~ vo′′′ + vo + vo′ Tp d (b) Figure 11.4 Small-signal model and block diagram of the PWM boost converter for CCM. (a) Small-signal model. (b) Block diagram. small-signal model of the boost converter for determining the control-to-output transfer function shown in Figure 11.5. Note that vsd = vo . (11.12) The current through the parallel combination of the load resistance and the filter capacitance is v iZ2 = o Z2 (11.13) vi = 0 Z1 io = 0 L r Dvo VO d + + il C d Dil ILd rC RL + vo Z2 Figure 11.5 Small-signal model of the PWM boost converter for determining the control-to-output transfer function Tp . Small-Signal Characteristics of Boost Converter for CCM 443 and the current through the inductor is il = Dil + IL d + iZ2 = Dil + IL d + vo Z2 (11.14) which, from (11.6), produces il = VO d vo vo IL d = + . + 1 − D (1 − D)Z2 (1 − D)2 RL (1 − D)Z2 (11.15) Using the KVL, − il Z1 + Dvo + VO d − vo = 0. (11.16) VO dZ1 vo Z 1 − + VO d = vo (1 − D) 2 (1 − D) RL (1 − D)Z2 (11.17) Substituting (11.15) into (11.16) yields − which becomes [ vo (1 − D) 1 + ] [ ] Z1 Z1 = dV 1 − . O (1 − D)2 Z2 (1 − D)2 RL (11.18) Hence, using (11.6), one obtains the control-to-output transfer function Z 1 VO 1 − (1−D)2 RL v (s) || Tp (s) ≡ o | = . d(s) ||v =i =0 1 − D 1 + Z1 (11.19) Z1 = r + sL (11.20) i (1−D)2 Z2 o The impedances Z1 and Z2 are and Z2 = ( ) 1 RL rC + sC 1 RL + rC + sC . (11.21) Substitution of (11.20) and (11.21) into (11.19) gives the control-to-output transfer function (or the duty ratioto-output transfer function) in the s-domain ( ){ [ ]} s + Cr1 s − L1 RL (1 − D)2 − r VO rC vo (s) || C =− Tp (s) ≡ | d(s) ||v =i =0 (1 − D)(RL + rC ) s2 + s C[r(RL +rC )+(1−D)2 RL rC ]+L + r+(1−D)2 RL i o LC(R +r ) LC(R +r ) L = Tpx (s + 𝜔zn )(s − 𝜔zp ) s2 + 2𝜉𝜔0 s + 𝜔20 = Tpx C (s − zn )(s − zp ) = Tpx C (s + 𝜔zn )(s − 𝜔zp ) [s − (𝜎 + j𝜔0 )][s − (𝜎 − j𝜔0 )] ( )( ) s s 1 + 1 − (s + 𝜔zn )(s − 𝜔zp ) VO rC 𝜔zn 𝜔zp 𝜔zn 𝜔zp = = Tpx ( )2 [s − (−𝜉𝜔0 + j𝜔0 )][s − (−𝜉𝜔0 − j𝜔0 )] (1 − D)(RL + rC )𝜔20 1 + 𝜔2𝜉 s + 𝜔s 0 0 ( )( ) 1 + 𝜔s 1 − 𝜔s zn zp = Tpo (11.22) ( )2 s s 1 + Q𝜔 + 𝜔 0 0 (s − p1 )(s − p2 ) L 444 Pulse-Width Modulated DC–DC Power Converters where the magnitude of Tp at high frequencies Tpx = Tp (∞) = − rC VO 1 − D RL + rC (11.23) the magnitude of Tp at f = 0 is Tpo = Tp (0) = VO rC 𝜔zn 𝜔zp (1 − D)(RL + rC )𝜔20 = VO VO RL (1 − D)2 − r ≈ 2 1 − D RL (1 − D) + r 1−D the angular corner frequency or the angular natural undamped frequency is √ (1 − D)2 RL + r 1 = √ = p1 p2 𝜔0 = LC(RL + rC ) 𝜏C 𝜏L (11.24) (11.25) the time constants are 𝜏C = C(RL + rC ) 𝜏L = (11.26) L∕(1 − D)2 L = r + RL ∕(1 − D)2 RL + r∕(1 − D)2 (11.27) the damping ratio is 𝜉= 2 L + C[r(RL + rC ) + (1 − D) RL rC ] 𝜎 = √ 𝜔0 2 LC(R + r )[(1 − D)2 R + r] (11.28) L C Q= 1 2𝜉 (11.29) L the quality factor is the damping factor 𝜎 = 𝜉𝜔0 = 𝜔0 p + p2 =− 1 2Q 2 the angular damped frequency 𝜔d = 𝜔0 √ √ 1 − 𝜉 2 = 𝜔0 1− 1 4Q2 for (11.30) 𝜉<1 (11.31) the ESR zero, which is a left-half plane (LHP) or negative zero, is given by zn = − 1 CrC (11.32) the angular frequency of the ESR zero is 𝜔zn = −zn = 1 CrC (11.33) the right-half plane (RHP) or positive zero and its angular frequency are zp = 𝜔zp = and the poles are RL (1 − D)2 − r L √ √ p1 , p2 = −𝜉𝜔0 ± 𝜔0 𝜉 2 − 1 = −𝜉𝜔0 ± j𝜔0 1 − 𝜉 2 = −𝜎 ± j𝜔d . (11.34) (11.35) Small-Signal Characteristics of Boost Converter for CCM 445 The control-to-output transfer function Tp is a second-order low-pass function, which has two LHP poles, one LHP zero, and one RHP zero. The boost converter is a non-minimum phase system because it has RHP zero. The LHP zero zn is independent of D, whereas the poles and the RHP zero depend on D. As D is increased from 0 to 1, the RHP zero zp decreases from a maximum value of (RL − r)∕L, crosses zero when r = RL (1 − D)2 , becomes negative, and reaches a minimum value of −r∕L. In other words, zp is moving from a location in the right-hand plane to the origin, and then enters the left-hand plane at D = 1. When D is increased from 0 to 1, the corner frequency f0 decreases and the damping factor 𝜉 increases. The maximum value of zp occurs at RLmax and VImax , whereas the minimum value of zp occurs at RLmin and VImin . For D = 0, r = RF + rL and √ RL + rL + RF 1 𝜔0max = ≈ , (11.36) LC(RL + rC ) LC and for D = 1, r = rDS + rL and √ 𝜔0min = Hence, 𝜔0max = 𝜔0min rDS + rL ≈ 0. LC(RL + rC ) (11.37) √ RL + rL + RF . rDS + rL (11.38) Using the reflection rule, the resistance r can be moved from the inductor branch to the diode branch. This equivalent resistance is given by re = DrDS + (1 − D)RF + rL r = . 2 (1 − D) (1 − D)2 (11.39) As D is increased from 0 to 1, re increases from rL + RF to ∞. The equivalent inductance connected in series with the C-rC -RL circuit is Le = L . (1 − D)2 (11.40) Another method for deriving the equivalent inductance Le is based on the principle of energy conservation. The average inductor and diode currents are related by i iL = D . (11.41) 1−D The energy stored in the inductance L located in its original branch is WL = i2D 1 2 1 LiL = L 2 2 (1 − D)2 (11.42) and the energy stored in the equivalent inductance Le located in the diode branch is WLe = 1 2 Li . 2 eD (11.43) Hence, Le = L∕(1 − D)2 . Example 11.1 A boost converter has VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Calculate r, zn , fzn , zp , fzp , f0 , 𝜉, Q, p1 , p2 , and fd at RLmin = 40 Ω. Plot r, fzp , f0 , and 𝜉 versus D. 446 Pulse-Width Modulated DC–DC Power Converters 0.38 0.36 r (Ω) 0.34 0.32 0.3 0.28 0.26 Figure 11.6 0 0.2 0.4 D 0.6 0.8 1 Total parasitic resistance r as a function of D for rDS = 0.18 Ω, RF = 0.072 Ω, and rL = 0.19 Ω. Solution: The total parasitic resistance in series with the inductor at Dnom = 0.5 is r = Dnom rDS + (1 − Dnom )RF + rL = 0.5 × 0.18 + (1 − 0.5) × 0.072 + 0.19 = 0.09 + 0.036 + 0.19 = 0.316 Ω. (11.44) Figure 11.6 shows a plot of r versus D for rDS = 0.18 Ω, RF = 72 mΩ, and rL = 0.19 Ω. The LHP zero is 1 1 = −132.49 × 103 rad∕s =− zn = − CrC 68 × 10−6 × 0.111 (11.45) and the frequency of the LHP zero is fzn = 1 1 = 21.09 kHz. = 2𝜋CrC 2 × 𝜋 × 68 × 10−6 × 0.111 (11.46) The RHP zero is RLmin (1 − Dnom )2 − r 40 × (1 − 0.5)2 − 0.316 = = 62.08 × 103 rad∕s L 156 × 10−6 and the frequency of the RHP zero is zp = 𝜔zp = (11.47) RLmin (1 − Dnom )2 − r 40 × (1 − 0.5)2 − 0.316 = 9.88 kHz. (11.48) = 2𝜋L 2 × 𝜋 × 156 × 10−6 Figure 11.7 shows a plot of f0 versus D for rDS = 0.18 Ω, RF = 72 mΩ, rL = 0.19 Ω, rC = 111 mΩ, and RL = 40 Ω. The corner frequency is √ √ (1 − Dnom )2 RLmin + r (1 − 0.5)2 × 40 + 0.316 1 1 = 783.66 Hz. (11.49) f0 = = 2𝜋 LC(RLmin + rC ) 2𝜋 156 × 10−6 × 68 × 10−6 × (40 + 0.111) fzp = Small-Signal Characteristics of Boost Converter for CCM 447 45 40 35 fzp (kHz) 30 25 20 15 10 5 0 0 0.2 0.4 D 0.6 0.8 1 Figure 11.7 Frequency of the RHP zero fzp as a function of D for the boost converter at VO = 20 V, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω for RL = 40 Ω. Figure 11.8 shows a plot of fzp versus D for rDS = 0.18 Ω, RF = 72 mΩ, rL = 0.19 Ω, rC = 111 mΩ, and RL = 40 Ω. The damping ratio is 𝜉= = C[r(RLmin + rC ) + (1 − Dnom )2 RLmin rC ] + L √ 2 LC(RLmin + rC )[r + (1 − Dnom )2 RLmin ] 68 × 10−6 [0.316 × (40 + 0.111) + (1 − 0.5)2 × 40 × 0.111] + 156 × 10−6 = 0.261 √ 2 156 × 10−6 × 68 × 10−6 × (40 + 0.111)[0.316 + (1 − 0.5)2 × 40] (11.50) and the quality factor is Q= 1 1 = = 1.916. 2𝜉 2 × 0.261 (11.51) Figure 11.9 shows a plot of 𝜉 versus D for rDS = 0.18 Ω, RF = 72 mΩ, rL = 0.19 Ω, rC = 111 mΩ, and RL = 40 Ω. The poles are √ √ p1 , p2 = −𝜉𝜔0 ± j𝜔0 1 − 𝜉 2 = −𝜎 ± j𝜔d = −0.261 × 2 × 𝜋 × 783.66 ± j2 × 𝜋 × 783.66 1 − 0.2612 = −1285 ± j4753 (rad∕s) (11.52) and the damped frequency is √ √ fd = f0 1 − 𝜉 2 = 783.66 1 − 0.2612 = 756.5 Hz. (11.53) 448 Pulse-Width Modulated DC–DC Power Converters 1.6 1.4 1.2 f0 (kHz) 1 0.8 0.6 0.4 0.2 0 0 0.2 0.4 D 0.6 0.8 1 Figure 11.8 Corner frequency f0 as a function of D for the boost converter at VO = 20 V, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω for RL = 40 Ω. 1.5 1.25 ξ 1 0.75 0.5 0.25 0 0 0.2 0.4 D 0.6 0.8 1 Figure 11.9 Damping ratio 𝜉 as a function of D for RL = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Small-Signal Characteristics of Boost Converter for CCM 449 At r = rC = 0, the approximate equations give fzp ≈ RLmin (1 − Dnom )2 ∕(2𝜋L) = 20.4 kHz, f0 ≈ 1∕2𝜋 √ √ (1 − Dnom )2 ∕LC = 772.6 Hz, 𝜉 ≈ L∕C∕[2RLmin (1 − Dnom )] = 0.03787, Q = 1∕2𝜉 ≈ 13.2, p1 , p2 ≈ −184 ± j4848.44 rad/s, and fd ≈ 771.49 Hz. Note that 𝜉lossy ∕𝜉lossless = 0.261/0.03787 = 6.89. Therefore, the parasitic components cannot be neglected. Substitution of s = j𝜔 into (11.22) yields ( )( ) 1 + j 𝜔𝜔 1 − j 𝜔𝜔 zn zp j𝜙 Tp (j𝜔) = Tpo ( )2 ( ) = |Tp |e Tp 𝜔 𝜔 1− 𝜔 + j2𝜉 𝜔 0 (11.54) 0 where √[ √ ( )2 ] [ ( )2 ] √ 𝜔 √ 1+ 𝜔 1 + √ 𝜔zn 𝜔zp √ |Tp | = Tpo √ √[ ( )2 ]2 ( )2 √ + 4𝜉 2 𝜔𝜔 1 − 𝜔𝜔 0 (11.55) 0 and ( 𝜙Tp = tan−1 𝜔 𝜔zn ) ( − tan−1 𝜔 𝜔zp ) ( ) ⎡ ⎤ 𝜔 2𝜉 ⎥ 𝜔0 −1 ⎢ − tan ⎢ ( )2 ⎥ ⎢1 − 𝜔 ⎥ ⎣ ⎦ 𝜔 for 𝜔 ≤1 𝜔0 (11.56) 0 or 𝜙Tp = −180◦ + tan−1 ( 𝜔 𝜔zn ) ( − tan−1 𝜔 𝜔zp ) ( ) ⎡ ⎤ 2𝜉 𝜔𝜔 ⎥ ⎢ 0 −1 − tan ⎢ ( )2 ⎥ ⎢1 − 𝜔 ⎥ ⎣ ⎦ 𝜔 for 𝜔 > 1. 𝜔0 (11.57) 0 Figure 11.10 shows idealized Bode plots of the open-loop control-to-output transfer function Tp for the boost converter. 11.4 Delay in Open-Loop Control-to-Output Transfer Function The delay time td introduced by the power transistor, the power transistor driver, and the pulse-width modulator can be described by the function Td (s) = e−std or Td (j𝜔) = e−j𝜔td . Hence, |Td | = 1 and the phase due to the delay time is 𝜙Td = −𝜔td = −2𝜋td f . (11.58) The delay function Td (s) can be approximated by a first-order Padé rational function for frequencies from dc to fs ∕2 1 − 𝜔s s − 𝜔zd zd ≈ =− =− = st s + 𝜔pd 1+ s 1+ d s+ 2 1 − 2d s − t2 2 td st Td (s) = e −std d 𝜔pd (11.59) 450 Pulse-Width Modulated DC–DC Power Converters Tp Tpo −40 dB/dec fzp 0 fzn f0 f Tp (∞) −20 dB/dec (a) ϕ f0 Tp fzp fzn 0 f −90° −180° −270° (b) Figure 11.10 Idealized Bode plots of the open-loop control-to-output transfer function Tp for the boost converter (without the delay). (a) |Tp | versus f . (b) 𝜙Tp versus f . where 𝜔zd = 𝜔pd = 2∕td . For s = j𝜔, −j𝜔td Td (j𝜔) = e 1 − 𝜔j𝜔 zd ≈ 1 + 𝜔j𝜔 pd = |Td |ej𝜙Td (11.60) where |Td | = 1 and ( 𝜙Td = −2 arctan f fpd ) for f ≤ 0.5. fpd (11.61) Figure 11.11 shows the exact and approximate plots of the delay phase 𝜙Tp using the first-order Padé rational function. The difference between the first-order approximation and the exact plot is within 5◦ for f ∕fpd ≤ 0.5. The control-to-output transfer function with the delay is Tp (s) = Tpx (s + 𝜔zn )(s − 𝜔zp ) −st (s + 𝜔zn )(s − 𝜔zp ) s − 𝜔zd e d ≈ −Tpx . 2 2 s + 2𝜉𝜔0 s + 𝜔0 s2 + 2𝜉𝜔0 s + 𝜔20 s + 𝜔pd (11.62) If the ac component of the duty cycle is given by d = dm cos 𝜔t, the ac component of the output voltage is given by vo = Vm cos[𝜔(t − td ) + 𝜙Tp ] = |Tp |dm cos[𝜔(t − td ) + 𝜙Tp ]. (11.63) Small-Signal Characteristics of Boost Converter for CCM 451 0 First Order Approximate Exact −20 −40 −60 d ϕ T (°) −80 −100 −120 −140 −160 −180 −200 −2 10 −1 10 Figure 11.11 0 10 f/fpd 1 10 2 10 Exact and approximated delay phase 𝜙Td . Example 11.2 For the boost converter with VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, calculate Tpo and Tp (∞) at RLmin = 40 Ω. Draw the Bode plots of Tp for D = 0.5 at td = 0 and td = 1 μs. Solution: From (11.24), Tpo = Tp (0) = VO RLmin (1 − Dnom )2 − r 20 40 × (1 − 0.5)2 − 0.316 = = 37.55 V = 31.49 dBV. 1 − Dnom RLmin (1 − Dnom )2 + r 1 − 0.5 40 × (1 − 0.5)2 + 0.316 (11.64) The approximate equation gives Tpo ≈ VO ∕(1 − Dnom ) = 20∕(1 − 0.5) = 40 V = 32 dBV. From (11.23), Tpx = Tp (∞) = − VO rC 20 0.111 = −0.1106 V =− 1 − Dnom RLmin + rC 1 − 0.5 40 + 0.111 (11.65) which gives |Tpx | = |Tp (∞)| = −19 dBV. Figures 11.12 and 11.13 show Bode plots of Tp for the boost converter with and without the delay. The −3 dB bandwidth at D = 0.5 is BW = 1 kHz. 11.5 Open-Loop Audio Susceptibility Setting d = 0 and io = 0 in the small-signal model of the boost converter of Figure 11.4 gives a small-signal model shown in Figure 11.14 that can be used for deriving the input-to-output voltage transfer function Mv . From the KCL, v il = Dil + iZ2 = Dil + o (11.66) Z2 452 Pulse-Width Modulated DC–DC Power Converters 40 30 | Tp | (dB) 20 10 0 −10 −20 1 10 2 3 10 10 f (Hz) 4 5 10 10 Figure 11.12 Bode plot of the magnitude of the open-loop control-to-output transfer function Tp without and with the delay td = 1 μs for the boost converter. 0 t =0 d t = 1 μs −30 d −60 p ϕ T (°) −90 −120 −150 −180 −210 −240 1 10 2 10 3 10 f (Hz) 4 10 5 10 Figure 11.13 Bode plot of the phase of the open-loop control-to-output transfer function Tp for the boost converter without and with the delay td = 1 μs. Small-Signal Characteristics of Boost Converter for CCM d=0 453 Z1 io = 0 Dvo r L + il + vi C ~ Dil RL rC Zi Figure 11.14 + vo Z2 Small-signal model of the PWM boost converter for determining the input-to-output transfer function Mv . which can be rearranged to the form iZ2 vo . (1 − D)Z2 (11.67) vi − il Z1 + Dvo − vo = 0. (11.68) il = 1−D = From the KVL, Substitution of (11.67) into (11.68) produces [ vi = vo (1 − D) 1 + ] Z1 . (1 − D)2 Z2 (11.69) Thus, the open-loop input-to-output transfer function is obtained Mv (s) ≡ vo (s) || Z2 1 = | | vi (s) |d=i =0 1 − D Z + Z1 2 o . (11.70) (1−D)2 Substituting (11.20) and (11.21) into (11.70), one obtains the input-to-output voltage transfer function (also called the line-to-output voltage transfer function or the audio susceptibility) s + Cr1 s + 𝜔zn (1 − D)RL rC (1 − D)RL rC vo (s) || C Mv (s) ≡ = = | vi (s) ||d=i =0 L(RL + rC ) s2 + s C[r(RL +rC )+(1−D)2 RL rC ]+L + r+(1−D)2 RL L(RL + rC ) s2 + 2𝜉𝜔0 s + 𝜔20 o LC(RL +rC ) = Mvx s + 𝜔zn s2 + 2𝜉𝜔0 s + 𝜔20 = (1 − D)RL rC 𝜔zn (RL + rC )L𝜔20 LC(RL +rC ) 1 + 𝜔s 1 + 𝜔s zn zn ( )2 = Mvo ( )2 .(11.71) 2𝜉s s 2𝜉s 1+ 𝜔 + 𝜔 1 + 𝜔 + 𝜔s 0 0 0 0 Hence, Mvo = Mv (0) = (1 − D)RL rC 𝜔zn (RL + rC )L𝜔20 Mvx = = (1 − D)RL 1 1 = r 1−D1+ (1 − D)2 RL + r 2 (11.72) (1−D) RL (1 − D)RL rC L(RL + rC ) (11.73) 454 Pulse-Width Modulated DC–DC Power Converters and Mv (∞) = 0. (11.74) Notice that Mvo ≈ 1∕(1 − D) for r∕(1 − D)2 ≪ RL and is the same as the dc voltage transfer function MV DC for the lossless boost converter. For s = j𝜔, ( ) 1 + j 𝜔𝜔 zn j𝜙 Mv (j𝜔) = Mvo (11.75) ( )2 ( ) = |Mv |e Mv 𝜔 𝜔 1− 𝜔 + j2𝜉 𝜔 0 0 which gives √ [ √ ( )2 ] √ 𝜔 √ 1 + √ 𝜔zn √ . |Mv | = Mvo √ √[ ( )2 ]2 ( )2 √ 𝜔 𝜔 2 1− 𝜔 + 4𝜉 𝜔 0 (11.76) 0 Figure 11.15 shows idealized Bode plots of the open-loop input-to-output transfer function Mv for the boost converter. The slope of the phase is (−90◦ ∕𝜉)/decade Mv Mvo −40 dB/dec 0 f0 fzn f −20 dB/dec (a) ϕ Mv 0 −90° −180° f0 fzn f0 f 10 ξ 10fzn 10 ξf0 fzn 10 (b) Figure 11.15 Idealized Bode plots of the open-loop input-to-output transfer function Mv for the boost converter in CCM. (a) |Mv | versus f . (b) 𝜙Mv versus f . Small-Signal Characteristics of Boost Converter for CCM 455 20 10 0 −20 v | M | (dB) −10 −30 −40 −50 −60 −70 1 10 2 3 10 4 10 f (Hz) 10 5 10 Figure 11.16 Bode plot of the magnitude of the open-loop input-to-output transfer function |Mv | versus frequency for the boost converter. Example 11.3 The boost converter has VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, Calculate Mvo at RLmin = 40 Ω and draw the Bode plot of |Mv | at D = 0.5. Solution: From (11.72), Mvo = Mv (0) = 1 1 − Dnom 1 + 1 r (1−Dnom )2 RLmin = 1 1 − 0.5 1 + 1 0.316 (1−0.5)2 ×40 = 1.939 = 5.75 dB. (11.77) Figures 11.16 and 11.17 show the Bode plots of Mv . It can be seen that Mvo increases with increasing duty cycle D. In addition, |Mv | decreases with increasing frequency above f0 = 784 Hz at a rate of −40 dB/decade and above fzn = 21.09 kHz at a rate of −20 dB/decade. The −3 dB bandwidth is BW = 1 kHz at D = 0.5. 11.6 Open-Loop Input Impedance The equivalent circuit of Figure 11.14 can be used to derive the open-loop small-signal input impedance of the boost converter. Note that ii = il and iZ2 = vo ∕Z2 . Hence, using KCL, vo = ii − Dii = ii (1 − D). Z2 (11.78) vo = Z2 iZ2 = Z2 ii (1 − D). (11.79) Hence, the output voltage is 456 Pulse-Width Modulated DC–DC Power Converters 0 −30 v ϕM (°) −60 −90 −120 −150 −180 1 10 2 3 10 4 10 f (Hz) 10 5 10 Figure 11.17 Bode plot of the phase of the open-loop input-to-output transfer function |Mv | versus frequency for the boost converter. Using KVL, vi − ii Z1 + Dvo − vo = 0. (11.80) vi = ii [Z1 + (1 − D)2 Z2 ]. (11.81) Substitution of (11.79) into (11.80) yields Hence, the open-loop input impedance is ( ) 1 2R (1 − D) + r | L C v (s) | sC = Z1 + (1 − D)2 Z2 = r + sL + Zi (s) ≡ i | 1 ii (s) ||d=i =0 RL + rC + sC o = { } C[r(RL +rC )+(1−D)2 RL rC ]+L (1−D)2 RL +r + L s2 + s LC(R +r ) LC(R +r ) L C L C s + C(R 1+r ) L = L(s2 + 2𝜉𝜔0 s + 𝜔20 ) s + 𝜔rc (11.82) (11.83) C where 𝜔rc = 1 . C(RL + rC ) (11.84) From (11.83), Ri (0) = Zi (0) = (1 − D)2 RL + r (11.85) Zi (∞) = ∞. (11.86) and Small-Signal Characteristics of Boost Converter for CCM 457 100 90 80 70 i | Z | (Ω) 60 50 40 30 20 10 0 1 10 Figure 11.18 2 10 3 10 f (Hz) 4 10 5 10 The magnitude of the open-loop input impedance Zi for the boost converter. Example 11.4 For the boost converter with VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, calculate frc and Ri (0) at RLmin = 40 Ω. Draw the plots of Zi at D = 0.5. Solution: Using (11.84), frc = 1 1 = = 58.36 Hz. 2𝜋C(RLmin + rC ) 2 × 𝜋 × 68 × 10−6 × (40 + 0.111) (11.87) From (11.85), Ri (0) = Zi (0) = (1 − Dnom )2 RLmin + r = (1 − 0.5)2 × 40 + 0.316 = 10.316 Ω. (11.88) Figures 11.18 and 11.19 show the plots of Zi versus frequency. These plots are similar to those of a series resonant circuit. It can be seen that |Zi | decreases with increasing D and rapidly increases with frequency above 1 kHz. 11.7 Open-Loop Output Impedance A small-signal model of the boost converter for deriving the open-loop output impedance is shown in Figure 11.20. This model is obtained by reducing d, vi , and io to zero and applying an independent voltage source vt at the output of the model. The voltage source vt will force a current it . The open-loop output impedance is equal to the ratio of the voltage vt and the current it . From the KVL, vt − Dvt + il Z1 = 0 (11.89) v (1 − D) il = − t . Z1 (11.90) which gives 458 Pulse-Width Modulated DC–DC Power Converters 90 60 i ϕ (°) Z 30 0 −30 −60 −90 1 10 Figure 11.19 2 3 10 4 10 f (Hz) 5 10 10 The phase of the open-loop input impedance Zi for the boost converter. From the KCL, ib = Dil − il = −il (1 − D) = (1 − D)2 vt Z1 (11.91) and it = iZ2 + ib = [ ] vt (1 − D)2 vt (1 − D)2 1 . + = vt + Z2 Z1 Z2 Z1 (11.92) Z1 L Dvo r ib it + d =0 vi = 0 io = 0 il iZ 2 Dil + C rC Z2 Figure 11.20 ~v t RL Zo Small-signal model of the PWM boost converter for determining the output impedance Zo . Small-Signal Characteristics of Boost Converter for CCM 459 Hence, the open-loop output impedance (including the load resistance RL ) is ( ) 1 R + r | L C v (s) | Z1 sC 1 r + sL = = ∥ Z2 = ∥ . Zo (s) ≡ t | 2 2 1 1 (1−D)2 it (s) ||d=v =i =0 (1 − D) (1 − D) R + r + + L C i o sC Z Z 2 (11.93) 1 Thus, Zo (s) = ( )( ) s + Cr1 s + Lr RL rC RL rC (s + 𝜔zn )(s + 𝜔rl ) C = RL + rC s2 + s C[r(RL +rC )+(1−D)2 RL rC ]+L + r+(1−D)2 RL RL + rC s2 + 2𝜉𝜔0 s + 𝜔20 (11.94) r . L (11.95) LC(RL +rC ) LC(RL +rC ) where 𝜔rl = From (11.94), Ro (0) = Zo (0) = RL ∥ rRL r = (1 − D)2 r + (1 − D)2 RL (11.96) and Zo (∞) = RL rC ≈ rC RL + rC for rC ≪ RL . (11.97) Example 11.5 For the boost converter with VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, calculate frl , Zo (0), and Z(∞) at RLmin = 40 Ω. Draw the plots of Zo at Dnom = 0.5. Solution: From (11.95), frl = 0.316 r = = 322.55 Hz. 2𝜋L 2 × 𝜋 × 156 × 10−6 (11.98) rRLmin 0.316 × 40 = = 1.225 Ω. r + (1 − Dnom )2 RLmin 0.316 + (1 − 0.5)2 × 40 (11.99) From (11.96), Zoo = Ro (0) = Zo (0) = The output impedance at high frequencies is Z(∞) = rC ||RLmin = rC RLmin 0.316 × 40 = 0.314 Ω ≈ rC . = rC + RLmin 0.316 + 40 (11.100) Figures 11.21 and 11.22 show the plots of the output impedance Zo versus frequency. The plots of Zo are similar to those of a parallel resonant circuit. It can be seen that the dc output impedance is R(0) = 1.225 Ω. The magnitude of output impedance |Zo | is nearly constant for frequencies from 0 to frl = 322.55 Hz, then increases with increasing f , reaches a maximum value of about 6.2 Ω at f0 = 784 Hz, and finally decreases to rC ||RLmin with increasing f . The magnitude |Zo | increases with D at low frequencies because r∕(1 − D)2 increases with D. Pulse-Width Modulated DC–DC Power Converters 7 6 4 o | Z | (Ω) 5 3 2 1 0 1 10 Figure 11.21 2 3 10 10 f (Hz) 4 5 10 10 The magnitude of the open-loop output impedance Zo for the boost converter. 60 30 0 o ϕZ (°) 460 −30 −60 −90 1 10 Figure 11.22 2 10 3 10 f (Hz) 4 10 5 10 The phase of the open-loop output impedance Zo for the boost converter. Small-Signal Characteristics of Boost Converter for CCM 461 11.8 Open-Loop Step Responses 11.8.1 Open-Loop Response of Output Voltage to Step Change in Input Voltage Let us consider a step change in the input voltage of magnitude ΔVI at time t = 0. The total input voltage is given by vI (t) = VI (0− ) + ΔVI u(t) (11.101) where u(t) is the unit step function and VI (0− ) is the steady-state input voltage before the step change. The step change of the input voltage in the time domain is expressed by vi (t) = vI (t) − VI (0− ) = ΔVI u(t) (11.102) which gives the step change of the input voltage in the s-domain vi (s) = ΔVI . s (11.103) Hence, from (11.71) and (11.103), the transient component of the output voltage of the open-loop boost converter in the s-domain is obtained as vo (s) = Mv (s)vi (s) = 𝜔2 s + 𝜔zn ΔVI Mv (s) = Mvo ΔVI 0 . 2 s 𝜔zn s(s + 2𝜉𝜔0 s + 𝜔20 ) (11.104) This produces the transient component of the output voltage of the open-loop boost converter in the time domain √ ) ( ) ( ⎡ ⎤ 𝜔0 2 e−𝜉𝜔0 t 𝜔0 −1 + sin(𝜔d t + 𝜙)⎥ for t ≥ 0 (11.105) vo (t) =  {vo (s)} = Mvo ΔVI ⎢1 + 1 − 2𝜉 √ ⎢ ⎥ 𝜔zn 𝜔zn 1 − 𝜉2 ⎣ ⎦ where 𝜙 = 𝜋 + tan ⎛ √1 − 𝜉 2 ⎞ ⎟ + tan−1 ⎜ 𝜔zn − 𝜉 ⎟ ⎠ ⎝ 𝜔0 (√ ⎛ √1 − 𝜉 2 ⎞ ⎟ + tan−1 ⎜ 𝜔zn − 𝜉 ⎟ ⎠ ⎝ 𝜔0 (√ −1 ⎜ 1 − 𝜉2 𝜉 ) for 𝜉 < 1 and 𝜔zn ≥𝜉 𝜔0 (11.106) for 𝜉 < 1 and 𝜔zn < 𝜉. 𝜔0 (11.107) or −1 ⎜ 𝜙 = 2𝜋 + tan 1 − 𝜉2 𝜉 ) The final steady-state value of the small-signal output voltage after the transient is vo (∞) = lim vo (t) = Mvo ΔVI . t→∞ (11.108) The total output voltage is vO (t) = VO (0− ) + vo (t) for t≥0 (11.109) where VO (0− ) is the output voltage at time t = 0− . Setting the derivative of (11.105) to zero, one obtains the time instants at which the maximum and minimum values of vo occur 𝜔0 tm = √ n𝜋 1 − 𝜉2 (11.110) 462 Pulse-Width Modulated DC–DC Power Converters where n is an integer. The first maximum value of vo is the highest one and occurs for n = 1. Letting n = 1, tm = 𝜋 𝜋 = . √ 𝜔 2 d 𝜔0 1 − 𝜉 The highest maximum value of vo is given by √ ) ( ) ( ⎡ 𝜔0 2 −𝜋𝜉∕√1−𝜉 2 ⎤⎥ 𝜔0 + e vomax = ΔVI Mvo ⎢1 + 1 − 2𝜉 ⎢ ⎥ 𝜔zn 𝜔zn ⎣ ⎦ (11.111) (11.112) resulting in the maximum overshoot of the transient component of the output voltage vo √ ) ( ) ( 𝜔0 2 −𝜋𝜉∕√1−𝜉 2 𝜔0 vomax vomax vomax − vo (∞) = −1= + Smax ≡ − 1 = 1 − 2𝜉 e vo (∞) vo (∞) ΔVI Mvo 𝜔zn 𝜔zn √ ) ( ) ( √ 𝜔0 2 −𝜋∕ 12 −1 𝜔0 𝜉 + = 1 − 2𝜉 e (11.113) 𝜔zn 𝜔zn where vo (∞) = ΔVI Mvo is the final steady-state value of the transient component of the output voltage vo after the transition. For 𝜉 ≥ 1, the step response does not exhibit any overshoot, that is, vo (t) ≤ vo (∞). The maximum relative transient ripple of the total output voltage is defined as 𝛿max ≡ v − vO (∞) vomax − vo (∞) vOmax − vO (∞) = = Omax− vO (∞) vO (∞) VO (0 ) + vo (∞) (11.114) where vO (∞) = VO (0− ) + vo (∞) = VO (0− ) + Mvo ΔVI is the final steady-state value of the total output voltage after the transition. The 5% settling time is ( ( ) ) √ √ 1 1 ts = − ln 0.05 1 − 𝜉 2 = − ln 0.05 1 − 𝜉 2 . (11.115) 𝜔0 𝜉 𝜎 The delay time is 1 + 0.7𝜉 𝜔0 for 𝜉 < 0.69. (11.116) 0.8 + 2.5𝜉 𝜔0 for 𝜉 < 0.69. (11.117) td ≈ The rise time is tr ≈ Example 11.6 For the open-loop boost converter specified in Example 11.1, draw the waveform of the output voltage vO that is a response to the step change in the input voltage from 12 to 13 V. Calculate (a) the maximum overshoot of the transient component of the output voltage, (b) the final steady-state values of the transient component and the total output voltage, (c) the maximum relative transient ripple of the total output voltage. Solution: Figure 11.23 shows a step response of the transient component of the output voltage vo to a step change in the input voltage vI from 12 to 13 V, which corresponds to a step change in vi from 0 to 1 V, for the boost converter without feedback at Dnom = 0.5, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. The output voltage waveform vO obtained from the MATLAB® simulation shown in Figure 11.23 shows that the output voltage increases from 20 V to its peak value of 22.738 V and then reaches its final steady-state value of vO = 21.939 V after approximately 3 ms. Small-Signal Characteristics of Boost Converter for CCM 463 23 22.5 O v (V) 22 21.5 21 20.5 20 0 1 2 t (ms) 3 4 5 Figure 11.23 Response of the output voltage vO to a step change in vI from 12 to 13 V for the boost converter without feedback for Dnom = 0.5, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. From Examples 11.1 and 11.3, 𝜉 = 0.261, fzn = 21.09 kHz, f0 = 784 Hz, and Mvo = 1.939. The final steady-state value of the transient component of the output voltage is vo (∞) = Mvo ΔVI = 1.939 × 1 = 1.939 V. (11.118) Using (11.113), one can compute the maximum overshoot of the transient component of the output voltage vo √ ( ) ( )2 √ f0 f0 2 + Smax = 1 − 2𝜉 e−𝜋𝜉∕ 1−𝜉 fzn fzn √ ) ( ) ( √ 0.784 2 −𝜋×0.261∕ 1−0.2612 0.784 + = 1 − 2 × 0.261 × e = 42.39%. (11.119) 21.09 21.09 Hence, the maximum value of the transient component of the output voltage is vomax = (1 + Smax )vo (∞) = (1 + 0.4238) × 1.939 = 2.761 V. (11.120) The final steady-state value of the total output voltage after the transient is vO (∞) = VO (0− ) + vo (∞) = 20 + 1.939 = 21.939 V. (11.121) Thus, the maximum relative transient ripple of the output voltage is vomax − vo (∞) 2.761 − 1.939 0.822 = = = 3.75%. vO (∞) 21.939 21.939 (11.122) ( ( ) ) √ √ 1 1 ln 0.05 1 − 𝜉 2 = − ln 0.05 1 − 0.2612 = 4.14 ms. 𝜎 1285 (11.123) 𝛿max = The 5% settling time is ts = − 464 Pulse-Width Modulated DC–DC Power Converters The delay time is td ≈ 1 + 0.7𝜉 1 + 0.7 × 0.261 = 0.24 ms. = 𝜔0 2𝜋 × 784 (11.124) tr ≈ 1 + 2.5𝜉 1 + 2.5 × 0.261 = 0.295 ms. = 𝜔0 2𝜋 × 784 (11.125) The rise time is 11.8.2 Open-Loop Response of Output Voltage to Step Change in Duty Cycle Assume a step change in the duty cycle ΔdT at time t = 0. The total duty cycle is dT (t) = D + ΔdT u(t). (11.126) The step change in the duty cycle in the time domain is given by d(t) = dT (t) − D = ΔdT u(t) (11.127) which results in ΔdT . (11.128) s Hence, using (11.22), the transient component of the output voltage of the open-loop boost converter in the s-domain is d(s) = vo (s) = Tp (s)d(s) = ΔdT Tp (s) s = ΔdT Tpo 𝜔20 (s + 𝜔zn )(s − 𝜔zp ) 𝜔zn 𝜔zp s(s2 + 2𝜉𝜔0 s + 𝜔20 ) . (11.129) The ac component of the output voltage is given by vo (t) = −1 {vo (s)} for t ≥ 0. (11.130) The inverse Laplace transform of the output voltage of the open-loop boost converter in the time domain can be found using MATLAB® . The total output voltage is vO (t) = VO (0− ) + vo (t) for t ≥ 0. (11.131) Example 11.7 For the open-loop boost converter specified in Example 11.1, draw the waveform of the output voltage vO that is a response to the step change in the duty cycle dT from 0.5 to 0.6. Calculate the output voltage for steady state after the transition and the maximum relative transient ripple. Solution: Figure 11.24 shows a response of the transient component of the output voltage vo to a step change in the control input dT from 0.5 to 0.6 for d = 0.1 for the boost converter without feedback at VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. The output voltage vO increases from 20 V to a peak value of 25.35 V and then reaches a final steady-state value of approximately 23.755 V after 3 ms. From Example 11.2, the transient component of the output voltage is vo (∞) = Tpo ΔdT = 37.55 × 0.1 = 3.755 V. (11.132) Referring to Figure 11.24, vomax = 5.35 V and the maximum overshoot is Smax ≡ vomax − vo (∞) 5.35 − 3.755 = = 42.48%. vo (∞) 3.755 (11.133) Small-Signal Characteristics of Boost Converter for CCM 465 26 25 v (V) O 24 23 22 21 20 0 1 2 t (ms) 3 4 5 Figure 11.24 Response of the output voltage vO to a step change in the duty cycle dT from 0.5 to 0.6 for the boost converter without feedback for VInom = 12 V, RLmin = 40 Ω, rDS = 0.4 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. The total output voltage is vO (∞) = VO (0− ) + vo (∞) = 20 + 3.755 = 23.755 V. (11.134) Hence, the maximum relative transient ripple of the output voltage is 𝛿max = vOmax − vO (∞) 25.35 − 23.755 = = 6.71%. vO (∞) 23.755 (11.135) 11.8.3 Open-Loop Response of Output Voltage to Step Change in Load Current Let us assume a step change in the load current ΔIO at time t = 0 for fixed input voltage VI and duty cycle D. The total load current is given by iO (t) = IO (0− ) + ΔIO u(t) (11.136) resulting in the step change in the load current in the time domain io (t) = iO (t) − IO (0− ) = ΔIO u(t) (11.137) and in the s-domain io (s) = ΔIO . s (11.138) This leads to the transient component of the output voltage in the s-domain vo (s) = −Zo (s)io (s) = − ΔIO RL rC (s + 𝜔zn )(s + 𝜔rl ) RL + rC s(s2 + 2𝜉𝜔0 s + 𝜔20 ) (11.139) 466 Pulse-Width Modulated DC–DC Power Converters and in the time domain vo (t) = −1 {vo (s)} for t ≥ 0. (11.140) The total output voltage is vO (t) = VO (0− ) + vo (t). Example 11.8 For the open-loop boost converter given in Example 11.1, draw the waveform of the output voltage vO that is a response to the step change in the load current iO from 0.5 to 0.6 A. Find the output voltage for steady state after the transition and the maximum relative transient ripple. Solution: Figure 11.25 shows a step response of the output voltage vO to a step change in the load current iO from 0.5 to 0.6 A for the boost converter without feedback at VI = 28 V, D = 0.5, L = 156 μH, C = 68 μF, RLmin = 40 Ω, r = 0.316 Ω, and rC = 0.111 Ω. The output voltage vO decreases from 20 V to a minimum value of 19.69 V and then reaches a final steady-state value of approximately 19.9 V after 3 ms. The dc output resistance is Zo (0) = Ro (0) = RLmin r∕[(1 − Dnom )2 RLmin + r] = 1.225 Ω. The change in the steady-state output voltage is vo (∞) = ΔVO = −Ro (0)ΔIO = −1.225 × 0.1 = −0.1225 V. (11.141) Hence, the output voltage after the transition is vO (∞) = VO (0− ) + vo (∞) = 20 − 0.1225 = 19.8775 V. (11.142) From Figure 11.25, vomin = −0.3051 V, yielding the maximum undershoot of the output voltage Smax = |vomin | − |vo (∞)| 0.3051 − 0.1221 = = 150% |vo (∞)| 0.1221 (11.143) 20 19.95 v (V) O 19.9 19.85 19.8 19.75 19.7 19.65 0 1 2 t (ms) 3 4 5 Figure 11.25 Step response of vO to a step change in the load current IO from 0.5 to 0.6 A for the boost converter without feedback for VInom = 12 V, D = 0.5, L = 156 μH, C = 68 μF, RLmin = 40 Ω, r = 0.316 Ω, and rC = 0.111 Ω. Small-Signal Characteristics of Boost Converter for CCM 467 and the maximum relative transient ripple of the output voltage 𝛿max = |vomin | − |vo (∞)| 0.3051 − 0.1221 = = 0.92%. vO (∞) 19.8775 (11.144) 11.9 Summary r The small-signal model of the boost converter has two inputs: the small-signal duty cycle d and the small-signal input voltage vi . The small-signal duty cycle d is a control variable and the small-signal input voltage vi is a disturbance. r The small-signal model of the boost converter has one output, which is the small-signal component of the output voltage vo . r The open-loop control-to-output transfer function of the boost converter is a second-order low-pass function with two poles and two zeros. r The two poles and one zero are located in the LHP and one zero is located in the RHP for most values of the dc duty cycle D. As D is increased from 0 to 1, the zero moves from the RHP to the origin and enters the LHP as D approaches 1. r The open-loop input-to-output transfer function of the boost converter is a second-order low-pass transfer function. r The open-loop input-to-output transfer function of the boost converter has two simple or complex poles and one simple zero. r Both the poles and the zero of the open-loop input-to-output transfer function of the boost converter are located in the LHP. r The plots of the open-loop input impedance of the boost converter are similar to those of the series resonant circuit composed of a series combination of L∕(1 − D)2 and r∕(1 − D)2 in series with the C-rC -RL circuit. r The plots of the open-loop output impedance of the boost converter are similar to those of the parallel resonant circuit composed of a series combination of L∕(1 − D)2 and r∕(1 − D)2 in parallel with the C-rC -RL circuit. r The magnitude of the output impedance |Z | increases with increasing D at low frequencies. o References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I and II. Pasadena, CA: TESLAco, 1981, pp. 73–89. [2] D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. [3] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics, ch. 11.4. Reading, MA: AddisonWesley, 1991, pp. 274–280. [4] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed, New York: John Wiley and Sons, 2003. [5] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2nd Ed. Norwell, MA: Kluwer, 2001. [6] V. Vorpérian, “Simplified analysis of PWM converters using the model of the PWM switch, Part I: Continuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-26, pp. 497–505, May 1990. [7] D. Czarkowski and M. K. Kazimierczuk, “Circuit models of PWM dc-dc converters,” Proceedings of the IEEE National Aerospace Conf. (NAECON’92), Dayton, OH, May 18–22, 1992, pp. 407–413. [8] D. Czarkowski and M. K. Kazimierczuk, “Static- and dynamic-circuit models of PWM buck-derived dc-dc converters,” IEEE Proc., Pt. G, Circuits, Devices and Systems, vol. 139, pp. 669–679, December 1992. [9] D. Czarkowski and M. K. Kazimierczuk, “Energy-conservation approach to modeling PWM dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-29, pp. 1059–1063, July 1993. [10] M. K. Kazimierczuk and D. Czarkowski, “Application of the principle of energy conservation to modeling the PWM converters,” 2nd IEEE Conference on Control Applications, Vancouver, BC, Canada, September 13–16, 1993, pp. 291–296. 468 Pulse-Width Modulated DC–DC Power Converters [11] M. K. Kazimierczuk and R. Cravens, II, “Closed-loop input impedance of a voltage-mode-controlled PWM boost dcdc converter for CCM,” IEEE 37th Midwest Symposium on Circuits and Systems, Lafayette, LA, August 3–5, 1994, pp. 1253–1256. [12] M. K. Kazimierczuk and R. Cravens, II, “Closed-loop characteristics of voltage-mode-controlled PWM boost dc-dc converter with an integral-lead controller,” Journal of Circuits, Systems, and Computers, vol. 4, no. 4, pp. 429–458, December 1994. [13] M. K. Kazimierczuk and R. Cravens, II, “Input impedance of closed-loop PWM boost dc-dc converter for CCM,” IEEE International Conference on Circuits and Systems, Seattle, WA, April 30–May 3, 1995, pp. 2047–2050. [14] B. Bryant and M. K. Kazimierczuk, “Voltage-loop power-stage transfer functions with MOSFET delay for boost PWM converter operating in CCM,” IEEE Transactions on Industrial Electronics, vol. 54, pp. 347–353, February 2007. Review Questions 11.1 Draw a dc model for a boost converter for CCM. 11.2 Draw a small-signal model for a boost converter for CCM. 11.3 Draw a small-signal model for deriving the control-to-output transfer function of a boost converter for CCM. 11.4 What is the order of the control-to-output transfer function of the boost converter? 11.5 Where are the poles and zeros of the control-to-output transfer function of the boost converter located in the s-plane? 11.6 How does the location of the poles and zeros of the control-to-output transfer function change with increasing dc duty cycle D? 11.7 What is a non-minimal phase system? 11.8 Is the control-to-output transfer function of the boost converter minimal or non-minimal phase? 11.9 Sketch Bode plots for the control-to-output transfer function of the boost converter? 11.10 Draw a small-signal model for deriving the input-to-output transfer function of a boost converter. 11.11 Sketch the magnitude of the input-to-output transfer function for the boost converter. 11.12 Where are the poles and the zero of the input-to-output transfer function of the boost converter located in the s-plane? 11.13 Draw a small-signal model for deriving the input impedance of a boost converter. 11.14 Sketch the magnitude and the phase of the input impedance for the boost converter. 11.15 Draw a small-signal model for deriving the output impedance of a boost converter. 11.16 Sketch the magnitude and the phase of the output impedance for the boost converter. Problems 11.1 The boost converter designed in Chapter 3 has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, VF = 1.4 V, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, and rC = 1 Ω. Determine MV DC and 𝜂. Small-Signal Characteristics of Boost Converter for CCM 469 11.2 The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Calculate zn , fzn , zp , fzp , f0 , 𝜉, Q, p1 , p2 , and fd . 11.3 The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Tpo and Tp (∞). 11.4 The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Mvo . 11.5 The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 μH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Zi (0). 11.6 The boost converter has VInom = 28 V, VO = −12 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Zo (0) and Zo (∞). 11.7 The boost converter has RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Zo (0) for D = 0.1, 0.5, 0.8, and 0.9. 11.8 The boost converter has 𝜉lossy = 0.162, VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine 𝜉 and Q at all parasitic resistances equal to zero. Calculate the ratio of the actual to approximate values of 𝜉. 11.9 A boost PWM dc–dc converter has VImin = 1 V, VImax = 8 V, VO = 20 V, RL = 40 Ω, rDS = 120 mΩ, RF = 80 mΩ, L = 156 μH, rL = 50 mΩ, C = 68 μF, rC = 50 mΩ, and fs = 100 kHz. Find values of the zero and its frequency at VImin and VImax . Draw the location of the zero zp (root locus) of the zero in the s-plane for VImin and VImax . Find the value of D at which zp = 0. 11.10 A boost PWM dc–dc converter has VI = 10 V, VO = 20 V, RLmin = 40 Ω, RLmax = 200 Ω, rDS = 120 mΩ, RF = 80 mΩ, L = 156 μH, rL = 50 mΩ, C = 68 μF, rC = 50 mΩ, and fs = 100 kHz. Find values of the zero and its frequency at VImin and VImax . Draw the location of the zero zp (root locus) of the zero in the s-plane for VImin and VImax . Find the value of RL at which zp = 0. 11.11 A boost PWM dc–dc converter has VImin = 1 V, VImax = 8 V, VO = 20 V, RL = 40 Ω, rDS = 120 mΩ, RF = 80 mΩ, L = 156 μH, rL = 50 mΩ, C = 68 μF, rC = 50 mΩ, and fs = 100 kHz. (a) Find the values of the RHP zero zp and its frequencies at VImin and VImax . (b) Find the value of D at which zp = 0. (c) Draw the location of zp in the s-plane at VImin and VImax . (d) Sketch the Bode plots for zp only for VImin and VImax . 12 Voltage-Mode Control of PWM Buck Converter 12.1 Introduction Voltage-mode control of the PWM buck converter is explored in this chapter [1–4]. The control circuit of a power switch must decide when to turn the switch on and off. The basic blocks of the voltage-mode control system are described. One technique is known as voltage-mode control (or programming) or duty-cycle control because the output voltage is proportional to the duty cycle D. It is a single-loop control scheme. The transfer function of the pulse-width modulator is derived. The feedback network is represented by the two-port network hybrid h-parameters. The loading effect of the A-network by the 𝛽-network is considered. The criteria of the relative stability are discussed and the loop compensation procedure is explained. An integral-lead control circuit is analyzed and its design procedure is given. The loop gain is determined. The following closed-loop transfer functions and impedances of the buck converter are derived: the control-to-output transfer function, the input-to-output transfer function, the input impedance, and the output impedance. The responses of the output voltage to step changes in the input voltage and the duty cycle are also given. A physical power converter is unable to perform exactly according to the design in view of several practical considerations such as tolerance of circuit elements, environmental effects (temperature fluctuations, humidity, radiation, interference, etc.), and aging. One of the design objectives is to minimize the effect of parameter variations. Dc–dc power converters normally require a control circuit for the following reasons: r r r r To obtain a good dc voltage source. To regulate the output voltage against line voltage and load current (or load resistance) variations. To reduce the dc error. To reduce the sensitivity of the closed-loop voltage transfer function Tcl ≈ 1∕𝛽 to the component values in the forward path A over a wide range of operating conditions, such as temperature range and frequency range. r To reduce the closed-loop output impedance Z = Z ∕(1 + T). ocl o r To reduce the magnitude of the audio susceptibility M = M ∕(1 + T), especially to reduce the 100 or 120-Hz vcl v voltage ripple and other line disturbances such as transients. r The relative stability is a measure of how far the system is from instability. Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 Voltage-Mode Control of PWM Buck Converter xr + xe + 471 xo A xf β Figure 12.1 Block diagram of a single-loop negative feedback configuration. r To achieve a sufficient degree of relative stability, that is, a sufficient gain margin GM (usually, GM > 6–12 dB) and a sufficient phase margin PM (usually, PM > 45–60◦ ). r To increase the closed-loop bandwidth and thereby the speed of the transient responses to sudden changes in the input voltage and load current (or resistance). 12.2 Properties of Negative Feedback An open-loop circuit has the disadvantage of being subject to aging of components, drift of circuit parameters with temperature, time, etc. A block diagram of a single-loop negative feedback control circuit is shown in Figure 12.1. It consists of an A-network and a 𝛽-network. The A-network delivers an output signal xo = Axe to an external load. The feedback network 𝛽 produces a feedback signal xf = 𝛽xo that is subtracted from the reference signal xr to form an error signal xe = xr − xf . From Figure 12.1, xo = Axe = A(xr − xf ) = A(xr − 𝛽xo ). (12.1) Hence, the closed-loop gain is given by Af ≡ xo A 1 1 T 1 1 A 1 𝛽A = = = = = = . 1 xr 1 + 𝛽A 1 + T 𝛽 1 + 𝛽A 𝛽 1 + T 𝛽 𝛽+ 1+ 1 A (12.2) T where A = xo ∕xe is the open-loop gain, 𝛽 = xf ∕xo is the transfer function of the feedback network, T = xf ∕xe = 𝛽A is the loop gain or the loop transmission, D = 1 + 𝛽A is the amount of feedback, and T∕(1 + T) = 1∕(1 + 1∕T) is the correction factor. Let us assume initially that A and 𝛽 are frequency-independent real quantities. Pure negative feedback takes place for 𝛽A > 0 and pure positive feedback occurs for 𝛽A < 0. It follows from (12.2) that |Af | < |A| for negative feedback. From (12.2), Af = 1 1 1 1 = ≈ 1 𝛽 1+ 1 𝛽 𝛽+ T for 𝛽≫ 1 , A i.e., T = 𝛽A ≫ 1. (12.3) A Figure 12.2 shows a plot of Af as a function of A at a fixed value of 𝛽. It can be seen that Af approaches 1∕𝛽 as A increases to ∞. Therefore, the gain of negative feedback systems Af is practically independent of A and is almost entirely determined by the feedback network if the loop gain 𝛽A ≫ 1. Assuming that 𝛽 is constant and taking the derivative dAf ∕dA of (12.2), one obtains dAf = dA . (1 + 𝛽A)2 (12.4) Dividing (12.4) by (12.2) gives the relationship between the relative change in the closed-loop gain dAf ∕Af and the relative change in the open-loop gain dA∕A dAf Af = 1 dA 1 dA = . 1 + 𝛽A A 1+T A (12.5) 472 Pulse-Width Modulated DC–DC Power Converters Af 1 β A 0 (a) Af A A 1+A β 1 0 (b) Figure 12.2 Closed-loop gain Af as a function of the open-loop gain A and the transfer function of the feedback network 𝛽. (a) Af versus A at a fixed 𝛽. (b) Af versus 𝛽 at a fixed A. Thus, the fractional change in Af is (1 + 𝛽A) times lower than the fractional change in A. If 𝛽A ≫ 1, the negative feedback makes the closed-loop gain Af almost insensitive to variations in the A-network parameters. This is one of the key advantages of negative feedback. The open-loop gain A is a function of many parameters, some of which have large tolerances and uncertainties. The A-network contains active semiconductor devices whose parameters have a very wide range of tolerances (up to 100%) and depend on temperature, power supply voltages, etc. Passive elements have parasitic components that depend on frequency and temperature, and the range of their values is very wide, for example, for the ESR of filter capacitors. Figure 12.2(b) shows a plot of Af versus 𝛽 at a fixed value of A. Taking the derivative dAf ∕d𝛽 of (12.2) results in dAf = −A2f d𝛽 ≈ − d𝛽 . 𝛽2 (12.6) Dividing (12.6) by (12.2) yields the relationship between the relative changes in the closed-loop gain dAf ∕Af and the feedback network transfer function d𝛽∕𝛽 dAf Af =− 𝛽A d𝛽 d𝛽 T d𝛽 =− ≈− . 1 + 𝛽A 𝛽 1+T 𝛽 𝛽 (12.7) Voltage-Mode Control of PWM Buck Converter 473 Thus, the fractional change in Af is almost equal in magnitude and opposite in sign to the fractional change in 𝛽. To achieve predictable and accurate closed-loop gain, the feedback network should be built of precision passive components, such as resistors with low tolerances, usually less then or equal to 1%. The fractional change on Af in terms of fractional changes in A and 𝛽 is dAf Af = 𝛽A d𝛽 1 dA T d𝛽 1 dA − = − . 1 + 𝛽A A 1 + 𝛽A 𝛽 1+T A 1+T 𝛽 (12.8) 𝛽A x ≈ xr 1 + 𝛽A r (12.9) The feedback signal is given by xf = and the error signal is x e = xr − xf = xr . 1 + 𝛽A (12.10) If |𝛽A| ≫ 1, xe ≪ xr and xf ≪ xr . The magnitude of the open-loop gain |A| usually decreases with increasing frequency. Therefore, the magnitude of the loop gain |𝛽A| also decreases with frequency. Consequently, the desired condition |𝛽A| ≫ 1 is no longer satisfied at high frequencies. When the loop gain |𝛽A| becomes low, the advantages of negative feedback are significantly reduced. Example 12.1 A single-loop negative-feedback system has nominal values of A = 990 and 𝛽 = 0.1. The reference signal is xr = 1 V. It is known that dA∕A = 10% and d𝛽∕𝛽 = 10%. Calculate the nominal values of T, Af , xf , and xe . Find also dAf ∕Af at d𝛽 = 0, and dAf ∕Af at dA = 0. Solution: For the nominal values of A and 𝛽, one obtains the loop gain T = 𝛽A = 0.1 × 990 = 99 (12.11) D = 1 + T = 1 + 99 = 100 (12.12) 990 A = = 9.9. 1+T 1 + 99 (12.13) the amount of feedback and the closed-loop gain Af = The approximate value of the closed-loop gain is Af ≈ 1 1 = = 10. 𝛽 0.1 (12.14) The fractional change in the closed-loop gain due to the fractional change in the open-loop gain is dAf Af = 0.1 1 dA = = 0.001 = 0.1% 1 + 𝛽A A 100 (12.15) and the fractional change in the closed-loop gain due to the fractional change in the transfer function of the feedback network is dAf Af =− 𝛽A d𝛽 99 =− × 10% = −9.9%. 1 + 𝛽A 𝛽 100 (12.16) 474 Pulse-Width Modulated DC–DC Power Converters The total fractional change in the closed-loop gain is dAf Af = 𝛽A d𝛽 1 dA − = 0.1 − 9.9 = −9.8%. 1 + 𝛽A A 1 + 𝛽A 𝛽 (12.17) The output signal is xo = Af xr = 9.9 × 1 = 9.9 V (12.18) xr 1V = = 0.1 V. 1 + 𝛽A 100 (12.19) and the error signal is xe = 12.3 Stability The loop gain in the s-domain is T(s) = xf (s) xf (s) xo (s) = 𝛽A(s). xe (s) (12.20) xo (s) A(s) A(s) = = xr (s) 1 + 𝛽A(s) 1 + T(s) (12.21) A(j𝜔) A(j𝜔) = . 1 + 𝛽A(j𝜔) 1 + T(j𝜔) (12.22) xe (s) = xo (s) × The closed-loop gain in the s-domain is given by Af (s) = For s = j𝜔, the closed-loop gain is given by Af (j𝜔) = The condition for oscillation is T(j𝜔) = 𝛽A(j𝜔) = −1 (12.23) yielding A(j𝜔) = ∞. (12.24) 1−1 In this case, the circuit is marginally stable and produces sustained steady-state oscillations with a fixed amplitude of the output voltage. Equation (12.23) can be rewritten as Af (j𝜔) = ◦ T(j𝜔) = 𝛽A(j𝜔) = |T|ej𝜙T = −1 = 1e−j180 . (12.25) Hence, the amplitude condition for oscillation is |T(f−180 )| = 1 (12.26) 𝜙T (f0 dB ) = −180◦ (12.27) and the phase condition for oscillation is where f−180 is the phase crossover frequency at which 𝜙T = −180◦ and f0 dB is the gain crossover frequency at which |T| = 1 = 0 dB. If these two conditions are satisfied simultaneously at the same frequency fo = f0 dB = f−180 , termed the oscillation frequency fo , the circuit oscillates at a fixed amplitude of the output signal. Voltage-Mode Control of PWM Buck Converter 475 In order to achieve a stable circuit, either both conditions or one of the conditions for oscillations should not be satisfied. In addition, a sufficient degree of stability should be achieved. The relative stability is determined by the gain margin GM and the phase margin PM. The gain margin is defined as 1 GM = = −20 log |T(f−180 )| dB (12.28) |T(f−180 )| The phase margin is defined as PM = 180◦ + 𝜙T (f0dB ). For example, if |T(f−180 )| = 0.5 and 𝜙T (f0 dB 60◦ . In general, a circuit is unstable when (12.29) ) = −120◦ , then GM = 1∕0.5 = 2 = 6 dB and PM = 180◦ + (−120◦ ) = |T(f−180 )| ≥ 1 (12.30) 𝜙T (f0dB ) = −180◦ . (12.31) and In this case, the circuit produces initially growing oscillations. The stability margin is defined as the shortest distance from the Nyquist plot Re{T(f )} vs. Im{T(f )} to the point (−1,0) {√ } 2 2 SM = min (12.32) [|T(f )| cos 𝜙T (f ) + 1)] + [|T(f )| sin 𝜙T (f )] . The point (−1,0) is not encircled by the Nyquist plot. 12.4 Single-Loop Control of PWM Buck Converter A buck PWM converter with negative feedback is shown in Figure 12.3. This control scheme is called voltage-mode control because the duty cycle is proportional to the control voltage. It is a single-loop control circuit, in which L ~ . V vi + V vF + + . I V + + vE + VR vI vC RL io dT + + vAB Zi ′ Zf vt fs β RA + vF Figure 12.3 C + vO RB Circuit of closed-loop voltage-mode-controlled buck PWM converter. + vO 476 Pulse-Width Modulated DC–DC Power Converters L vi + V + VR vF + ~ RL C + VI io + vO V + + vE vI vC dT + + vAB Zi ′ Zf vt RA RB h11 + vF = β vO + + vO RA RB 1 h22 Figure 12.4 Closed-loop voltage-mode-controlled buck PWM converter with a feedback network 𝛽 represented by the h-parameters, where h21 = 0. the converter output voltage is sensed by a feedback network and used to develop an error voltage at the input of a control circuit. The output voltage of a control circuit controls the duty cycle. It is a series-shunt topology (also called a voltage-series topology) of negative feedback because the two-port networks are connected in series at the input and in parallel at the output. This topology reduces the output impedance, which is a desirable property of a good voltage source (i.e., a power supply). The magnitude of the output impedance is reduced because the A-network and the feedback network 𝛽 are connected in parallel at the converter output. The series connection of the two-port networks at the input compares the reference voltage VR and the feedback voltage vF and generates the error voltage vE = VR − vF . Figures 12.4 and 12.5 show the buck converter with rearrangements of the feedback network, using the h-parameters. The waveforms in the control circuit are depicted in Figure 12.6. The output voltage vO = VO + vo is reduced by a feedback network 𝛽 comprised of a resistive voltage divider RA and RB to generate a feedback voltage vF = VF + vf . The feedback voltage is compared to a reference voltage VR to develop an error voltage vE = VE + ve = VR − vF = VR − VF − vf , where VE = VR − VF is a dc error voltage and ve = −vf is an ac error voltage. The error voltage is applied to the input of a controller, which is a linear error amplifier in the form of an inverting closed-loop op amp. The controller produces a control voltage vC = VC + vc . The next stage is a pulse-width modulator, which is an inverting comparator. The control voltage vC is applied to the non-inverting input of the comparator and a sawtooth voltage vt of magnitude VTm and frequency fs is applied to the inverting input of the comparator. In most applications, the frequency of vt is constant, but it may also vary. The converter switching frequency fs is determined by the sawtooth generator frequency. In the comparator, v+ = vC and v− = vt . When vC < vt , (i.e., v+ < v− ), the output voltage of the comparator goes low. When vC > vt , (i.e., v+ > v− ), the output voltage of the comparator goes high. The output voltage vAB of the pulse-width modulator is a rectangular wave whose duty cycle dT depends on the value of the control voltage vC . The gate-to-source voltage of the power MOSFET vGS is of the same phase as the output voltage of the pulse-width modulator. Suppose the input voltage of the converter vI is increased as shown in Figure 12.6. Consequently, the output voltage vO increases, causing the feedback voltage vF to increase. Hence, the error voltage vE decreases and the control voltage vC also decreases. Therefore, the duty cycle dT of the comparator output voltage vAB decreases, Voltage-Mode Control of PWM Buck Converter 477 L ~ . V vi + vI vF + V + + vE h11 vC + RL C 1 h22 io + vO dT + vGS Zi ′ Zi vt Zf + vF = β vO + Figure 12.5 A-network. . I V + VR + + vO Closed-loop voltage-mode-controlled buck PWM converter with resistances h11 and 1∕h22 included in the vI ,vO vI vO 0 t vC ,vt vC vt VTm 0 t vAB 0 Figure 12.6 Ts 2Ts 3Ts t Waveforms in the closed-loop voltage-mode-control PWM buck converter with a negative feedback loop. 478 Pulse-Width Modulated DC–DC Power Converters causing the output voltage vO = dT vI to decrease. The switching frequency of the converter is equal to the frequency of the ramp voltage. Normally, the frequency of vt is constant. It is easier to reduce the electromagnetic interference (EMI) noise at a fixed frequency. Since VO ≈ (1∕𝛽)VR = (1 + RB ∕RA )VR , the tolerance of the resistors RA and RB in the feedback network should be low, for example, 1%. 12.5 Closed-Loop Small-Signal Model of Buck Converter A small-signal low-frequency model of the voltage-mode-controlled PWM buck converter is depicted in Figure 12.7(a). Figure 12.7(b) shows a block diagram of a closed-loop buck converter for small-signal operation. In this figure, Tp = v′o ∕d represents the small-signal open-loop control-to-output transfer function of the power stage of the buck converter, Mv = v′′o ∕vi is the open-loop input-to-output transfer function, Zo = −v′′′ o ∕io is the open-loop output impedance which includes the load resistance RL , Tm = d∕vc is the transfer function of the pulse-width modulator, Tc = vc ∕ve represents the voltage transfer function of the controller, 𝛽 = vf ∕vo is the voltage transfer function of the feedback network (or the feedback-path voltage transfer function), A = v′o ∕ve = Tc Tm Tp is the forward-path voltage transfer function, T = vf ∕ve = 𝛽A = 𝛽Tc Tm Tp is the loop gain, vc is the output voltage of the controller, ve is the ac component of the error voltage, and vr is the ac component of the reference voltage. The PWM regulator of Figure 12.7(a) is a multivariable system with three inputs, d, vi , and io , and a single output vo . The block diagram of Figure 12.7(b) can be simplified to the form shown in Figure 12.7(c). Applying superposition, one obtains the ac component of the output voltage Tc Tm Tp vo = Mv Zo v + v − i 1 + 𝛽Tc Tm Tp r 1 + 𝛽Tc Tm Tp i 1 + 𝛽Tc Tm Tp o = Mv Zo A vr + vi − i = Tcl vr + Mvcl vi − Zocl io 1+T 1+T 1+T o (12.33) Negative feedback reduces the magnitudes of the closed-loop audio susceptibility |Mvcl | and the closed-loop output impedance |Zocl | by a factor of (1 + |T|). However, |T| decreases with frequency and (1 + |T|) ≈ 1 at high frequencies, where negative feedback is no longer effective in improving the closed-loop converter performance. 12.6 Pulse-Width Modulator A circuit of a pulse-width modulator is shown in Figure 12.8(a). It is an inverting comparator based on an open-loop op amp. The control voltage is applied to the non-inverting input, and the ramp voltage vt is applied to the inverting input. Waveforms of the control voltage vC and the ramp voltage vt in the pulse-width modulator are shown in Figure 12.9. As the control voltage is increased from VC to VC + vc , the duty cycle is increased from D to D + d, causing an increase in the converter output voltage. From Figure 12.9, the slope of the ramp voltage waveform vt can be expressed in terms of the dc components of the control voltage VC and the duty cycle D M = tan 𝛾 = VC V = Tm . DTs Ts (12.34) Hence, the dc control voltage-to-duty cycle transfer function of the pulse-width modulator is Tm(dc) ≡ f D 1 1 = = = s. VC VTm MTs M (12.35) Using Figure 12.9(a), the slope of the ramp voltage vt can be described in terms of the small-signal components of the control voltage vc and the duty cycle d M = tan 𝛾 = V vc = Tm . dTs Ts (12.36) Voltage-Mode Control of PWM Buck Converter Z2 ii + vi L r + ~ il Dvi ILd DiI rC + ve + C ′ Zocl vc Tc + vo RL + VI d Zicl + vr 479 io Zocl d Tm vf ~ β + vf RA RB + vo (a) Zo io vi + vr ~ ve + Tc vf MV ~ vc Tm d Tp + vo′ vo′′ vo′′′ + + vo A β (b) Zo io vi vr ~ ~ MV vo′′ + vo′′′ + + vo′ A 1 1+ T vo (c) Figure 12.7 Closed-loop small-signal low-frequency representations of the buck PWM converter. (a) Small-signal model. (b) Block diagram. (c) Simplified block diagram. 480 Pulse-Width Modulated DC–DC Power Converters V vC = VC + vc + dT = D + d + vAB vt (a) VC Tm = 1 1 = MTs VTm D (b) vc Tm = 1 1 = MTs VTm d (c) Figure 12.8 Pulse-width modulator. (a) Circuit. (b) DC block diagram. (c) AC small-signal block diagram. vt ,vC vt vC γ VC vc VTm dTs M γ 0 DTs Ts t Ts t dTTs (a) vGS 0 (b) Figure 12.9 Waveforms in the pulse-width modulator. (a) Waveforms of the sawtooth voltage vt and the control voltage vC . (b) Waveforms of the gate-to-source voltage vGS . Voltage-Mode Control of PWM Buck Converter 481 Rearrangement of this equation leads to the ac control voltage-to-duty cycle transfer function of the pulse-width modulator Tm(ac) ≡ f d 1 1 = = = s. vc VTm MTs M (12.37) Note that Tm(dc) = Tm(ac) = Tm . Another method for deriving Tm(ac) is given below. It follows from Figure 12.9(a) and trigonometric considerations that the slope of the ramp voltage vt can be expressed in terms of the large-signal control voltage vC = VC + vc and the duty cycle dT = D + d M = tan 𝛾 = vC dT T s (12.38) which produces dT = vC . MTs (12.39) Hence, the small-signal control voltage-to-duty cycle transfer function of the pulse-width modulator can be derived as ( ) vC || d(dT ) || d 1 1 Tm(ac) ≡ = = = . (12.40) | | dvC ||d =D dvC MTs ||d =D MTs VTm T T Let us now assume that the control voltage vC contains a sinusoidal ac component as shown in Figure 12.10 vc = Vcm sin 𝜔t. vC ,vt (12.41) vt vC VC VTm 0 t vAB 0 t dT d D 0 Figure 12.10 dT t Waveforms in the pulse-width modulator for a sinusoidal ac component of the control voltage. 482 Pulse-Width Modulated DC–DC Power Converters The total control voltage is then given by vC = VC + vc = VC + Vcm sin 𝜔t. (12.42) Therefore, the total duty cycle is dT = D + d = vC V V = C + cm sin 𝜔t. VTm VTm VTm (12.43) Since VE ≪ VR , VF ≈ VR . It will be shown shortly that VC ≈ VR . Hence, one obtains the dc component of the duty cycle D= VC V V ≈ R ≈ F VTm VTm VTm (12.44) resulting in the dc transfer function of the pulse-width modulator Tm(dc) ≡ D 1 = . VC VTm (12.45) The ac component of the duty cycle is d = dm sin 𝜔t = Vcm sin 𝜔t VTm (12.46) where the amplitude of the ac component of the duty cycle is dm = Vcm . VTm (12.47) The ac control voltage-to-duty cycle transfer function of the pulse-width modulator is Tm(ac) ≡ d d 1 = m = . vc Vcm VTm (12.48) Notice that the dc and ac transfer functions of the pulse-width modulator are equal Tm = Tm(dc) = Tm(ac) = 1 1 = . VTm MTs (12.49) The ac transfer function of the pulse-width modulator may exhibit a pure delay 𝜙Tm = −𝜔to and is expressed by Tm =∣ Tm ∣ e𝜙Tm =∣ Tm ∣ e−j𝜔to = 1 −j𝜔to e . VTm (12.50) In subsequent analyses, the pure delay of the pulse-width modulator 𝜙Tm = −𝜔to will be neglected or combined with the delay of the power MOSFET. The op amp used as a comparator in the pulse-width modulator is required to have high enough slew rate SR. Assuming that the rise time tr and the fall time tf of the gate-to-source voltage are less than 5% of the period Ts = 1∕fs , the maximum rise and fall times are tr(max) = tf (max) = 0.05 Ts = Ts 1 = 20 20 fs (12.51) and the minimum slew rate of the op amp is SRmin = ΔVGS = 20 fs ΔVGS . tr(max) (12.52) Voltage-Mode Control of PWM Buck Converter 483 Example 12.2 A PWM buck converter has a dc reference voltage VR = 5 V and the nominal value of the dc component of the duty cycle Dnom = 0.555. Find the peak value of the ramp voltage at the input of the pulse-width modulator and the transfer function of the pulse-width modulator. Also calculate the minimum slew rate of the op amp used in the pulse-width modulator. Solution: The dc component of the control voltage VC is approximately equal to the reference voltage VR . From (12.35), VTm = VC V 5 = 9 V. ≈ R = Dnom Dnom 0.555 Pick VTm = 10 V. Hence, the voltage transfer function of the pulse-width modulator is ( ) 1 dB d 1 1 = 0.1 = −20 . Tm ≡ = = vc VTm 10 V V (12.53) (12.54) The period of the switching frequency is Ts = 1 1 = = 10 μs fs 100 × 103 (12.55) Ts = 0.5 μs. 20 (12.56) ΔVGS V 10 = 20 . = tr(max) 0.5 μs (12.57) and the maximum rise time is tr(max) = Assuming that ΔVGS = 10 V, the minimum slew rate is SRmin = 12.7 Feedback Network The feedback network is not an ideal voltage-controlled voltage source. It is a passive resistive voltage divider and therefore will load the A-network at the input and the output. Consequently, the gain, the input impedance, and the output impedance of the A-network are altered by the feedback network. In order to take into account the loading effect of the A-network by the feedback network, the feedback network can be represented by its h-parameters. This hybrid representation is compatible with the series-shunt topology of negative feedback because it contains a series network at the input and a parallel network at the output. Figure 12.11(a) shows a block diagram of a feedback network represented by a general two-port network excited by a current source I1 at the input and by a voltage source V2 at the output. Let us assume that the two-port network is time-invariant, linear, and does not contain independent sources. The two dependent variables (i.e., responses), the input voltage V1 and the output current I2 , can be expressed in terms of the independent variables (i.e., inputs) I1 and V2 and the hybrid h-parameters V1 = h11 I1 + h12 V2 (12.58) I2 = h21 I1 + h22 V2 . (12.59) Figure 12.11(b) shows an equivalent circuit, which represents these equations. 484 Pulse-Width Modulated DC–DC Power Converters I2 Linear Two-Port RB Network + I1 V1 + ~ V 2 (a) I2 h11 I1 + V1 h12V2 + + h21I1 h22 ~ V 2 (b) Figure 12.11 Block diagram and equivalent circuit of a linear two-port network represented by the h-parameters. (a) Block diagram of a general two-port network. (b) A two-port representation using the hybrid h-parameters. The feedback network used in the control circuit of Figure 12.7(a) is depicted in Figure 12.12(a). Its h-parameters are V || RA RB h11 = 1 | = (12.60) | I1 |V =0 RA + RB 2 𝛽 = h12 = vf V1 || v V RB = F = F = = | V2 ||I =0 vO VO vo RA + RB (12.61) 1 h21 = I2 || RB =− | I1 ||V =0 RA + RB (12.62) I2 || 1 = . | V2 ||I =0 RA + RB (12.63) 2 h22 = 1 The h-parameter equivalent circuit of the feedback network is shown in Figure 12.12(b). Note that h11 is the short-circuit input impedance, h12 is the open-circuit reverse voltage gain, h21 is the short-circuit forward current gain, and h22 is the open-circuit output admittance. Since the feedback network is passive, its forward transmission h21 is usually small and therefore can be neglected, as shown in Figure 12.12(c). In Figure 12.4, the feedback network is replaced by its h-parameter representation of Figure 12.12(c). The resistances h11 and 1∕h22 can be moved from the feedback network to the A-network, as shown in Figure 12.5. In this case, the feedback network is an ideal voltage-controlled voltage source. Observe that the error voltage vE is produced by two ideal voltage sources, VR and vF = 𝛽vO . Example 12.3 A closed-loop PWM buck converter has a dc reference voltage VR = 5 V and a dc output voltage VO = 14 V. Design a feedback network. The load resistance of the converter RL ranges from 10 to 100 Ω. The required input Voltage-Mode Control of PWM Buck Converter I2 RA I1 + + V1 ~ V RB 2 (a) h11 RA I2 RB I1 485 + h12V2 V1 + h21I1 RA RB ~ 1 h22 + V2 (b) h11 RA I2 RB I1 + h12V2 V1 + + V2 RA RB 1 h22 + ~ V 2 (c) Figure 12.12 Feedback network and its h-parameter equivalent circuit. (a) Feedback network. (b) Equivalent circuit of the feedback network represented by its h-parameters. (c) Equivalent circuit of the feedback network represented by h-parameters with h21 = 0. resistance of the control circuit is R1 = 6.8 kΩ. How significant is the loading effect of the A-network by the feedback network? Solution: Assuming that T(0) = 𝛽A(0) ≫ 1, the dc error voltage VE is much less than the reference voltage VR and the dc feedback voltage VF . Therefore, the dc component of the feedback voltage VF is approximately equal to the reference voltage VR . The voltage transfer function of the feedback network is vf V V RB v 5 = 0.3571 = −8.9432 dB. (12.64) = R = = 𝛽= F = F = vO VO vo VO RA + RB 14 Let RB = 5.1 kΩ/0.25 W/1%. Hence, ( ) ( ) 1 1 RA = − 1 RB = − 1 × 5.1 = 9.18 kΩ. 𝛽 0.3571 (12.65) Pick RA = 9.1 kΩ/0.25 W/1%. Thus, h11 = RA RB 5.1 × 9.1 = 3.2683 kΩ = RA + RB 5.1 + 9.1 (12.66) 486 Pulse-Width Modulated DC–DC Power Converters and 1 = RA + RB = 5.1 + 9.1 = 14.2 kΩ. h22 (12.67) Since 1∕h22 = 14.2 kΩ ≫ RLmax = 100 Ω, the equivalent load resistance of the A-network remains approximately equal to RL and the loading effect of the A-network by the feedback network at the output is negligible. 12.8 Transfer Function of Buck Converter with Modulator and Feedback Network From Figure 12.7(a), the control-to-output transfer function of the PWM buck converter and the pulse-width modulator (usually called a plant) is given by 1 + 𝜔s s + 𝜔z vo (s) z Tmp (s) ≡ = Tm Tp (s) = Tm Tpx = Tmpo (12.68) ∣ ( )2 vc (s) vi =io =0 s2 + 2𝜉𝜔0 s + 𝜔20 2𝜉s 1 + 𝜔 + 𝜔s 0 0 where Tmpo = Tmp (0) = VI RL . VTm RL + r (12.69) It can be seen from (12.69) that if the ratio VI ∕VTm is constant, the control-to-output transfer function of the converter and modulator is independent of the input voltage VI . A constant value of this ratio can be accomplished by means of a feed-forward loop. The feed-forward loop may be obtained in such a way that the supply voltage terminal of the sawtooth generator is connected to the converter dc input voltage VI using a resistive voltage divider. In this arrangement, VTm is directly proportional to VI , resulting in a constant ratio VI ∕VTm . Example 12.4 A PWM buck converter, studied in Chapter 11, has VR = 5 V, VTm = 10 V, VInom = 28 V, Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Draw Bode plots of the product of the transfer function of the pulse-width modulator and the control-to-output transfer function Tmp . Calculate Tmpo . Solution: From (12.54), the transfer function of the pulse-width modulator is Tm = 0.1 = −20 dB. Bode plots of Tmp are depicted in Figures 12.13 and 12.14. The magnitude |Tmp | crosses 0 dB at a frequency of 2.457 kHz. The minimum value of the phase 𝜙Tmp occurs at f = 3.18 kHz and is equal to −145.95◦ . From (12.69), Tmpo = VI RLmin 28 10 = = 2.75 = 8.786 dB. VTm RLmin + r 10 10 + 0.16 (12.70) The transfer function of the buck converter, the pulse-width modulator, and the feedback network is 1 + 𝜔s vf (s) s + 𝜔z z ∣ Tk ≡ = 𝛽Tm Tp (s) = 𝛽Tmp (s) = 𝛽Tm Tpx = Tko 2 2𝜉s vc (s) vi =io =0 s2 + 2𝜉𝜔0 s + 𝜔20 1 + 𝜔 + 𝜔s 2 0 where Tko = 𝛽|Tmp (0)| = 𝛽Tmpo = Setting s = j𝜔, 𝛽VI RL . VTm (RL + r) 0 (12.72) √ ( )2 √ √ f √ 1 + √ fz |Tk | = 𝛽 ∣ Tmp ∣= Tko √ √[ ( )2 ]2 ( )2 √ 1 − ff + 4𝜉 2 ff 0 (12.71) 0 (12.73) Voltage-Mode Control of PWM Buck Converter 20 10 | Tmp| (dB) 0 −10 −20 −30 −40 −50 1 10 2 3 10 10 f (Hz) Figure 12.13 4 5 10 10 Bode plot of the magnitude of Tmp . 0 −30 ϕT mp (°) −60 −90 −120 −150 1 10 2 10 Figure 12.14 3 10 f (Hz) 4 10 Bode plot of the phase of Tmp . 5 10 487 488 Pulse-Width Modulated DC–DC Power Converters and ( ) ⎡ ⎤ f ( ) 2𝜉 ⎥ f f0 −1 −1 ⎢ 𝜙Tk = tan − tan ⎢ ( )2 ⎥ fz f ⎢1 − ⎥ ⎣ ⎦ f0 for f ≤1 f0 (12.74) or ( ) ⎡ ⎤ f ( ) 2𝜉 ⎢ ⎥ f f0 𝜙Tk = −180◦ + tan−1 − tan−1 ⎢ ( )2 ⎥ fz ⎢1 − f ⎥ ⎣ ⎦ f0 for f > 1. f0 (12.75) Example 12.5 A PWM buck converter of Example 12.4 has VInom = 28 V, Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, rC = 0.391 Ω, VR = 5 V, and VTm = 10 V, 𝛽 = 0.3571, and VO = 14 V. Draw Bode plots of the transfer function of the PWM back converter along with the pulse-width modulator and the feedback network Tk . Find the frequency at which |Tk | crosses zero and the frequency at which the phase 𝜙Tk has a minimum value. Calculate Tko . Solution: Figures 12.15 and 12.16 show Bode plots of the magnitude |Tk | as a function of frequency. The magnitude |Tk | crosses 0 dB at f = 1.7 kHz. The minimum value of the phase 𝜙Tk occurs at fmin = 3.18 kHz. At f = 0, Tko = 𝛽|Tmp (0)| = 0.3571 × 2.75 = 0.982 = −0.158 dB. (12.76) 10 0 | Tk| (dB) −10 −20 −30 −40 −50 −60 1 10 2 10 Figure 12.15 3 10 f (Hz) 4 10 Bode plot of the magnitude of Tk . 5 10 Voltage-Mode Control of PWM Buck Converter 489 0 −30 k ϕT (°) −60 −90 −120 −150 1 10 2 3 10 Figure 12.16 10 f (Hz) 4 5 10 10 Bode plot of the phase of Tk . 12.9 Control Circuits 12.9.1 Error Amplifier A general circuit of an error amplifier and its control block diagram are shown in Figure 12.17(a) and (b), respectively. The error amplifier is also called a controller or a compensator. The feedback voltage consists of a dc component and an ac component vF = V F + vf . (12.77) vE = V E + ve = V R − vF = V R − V F − vf (12.78) Hence, the error voltage is given by where the dc component of the error voltage is VE = VR − VF (12.79) ve = −vf . (12.80) and the ac component of the error voltage is The current through the impedances Zi and Zf is iZ i = V − vC vF − V R = R . Zi Zf (12.81) Rearrangement of this equation gives the total control voltage v C = V C + vc = V R + Zf Zi (VR − vF ) = VR + Zf Zi (VR − VF − vf ) = VR + Zf Zi (VR − VF ) − Zf v. Zi f (12.82) 490 Pulse-Width Modulated DC–DC Power Converters ++ + vE = VE + ve VR vF AOL h11 ~v + vC = Vc + vc Zi ′ f Zi VF Zf iZi (a) VR + vE = VE + ve + Tc vC = Vc + vc vF = VF + vf (b) Figure 12.17 diagram. General circuit and control block diagram of an error amplifier. (a) General circuit. (b) Control block where the dc component of the control voltage is Zf (0) Zf (0) VC = VR + (VR − VF ) = VR + V ≈ VR Zi (0) Zi (0) E (12.83) and the ac component of the control voltage is vc = − Zf v. Zi f (12.84) Substitution of (12.80) into (12.84) yields vc = Zf v Zi e (12.85) which gives the ac voltage transfer function of the controller vc (s) Zf (s) = . ve (s) Zi (s) (12.86) Zf (s) v (s) vc (s) = c = −Tc (s) = − . vf (s) −ve (s) Zi (s) (12.87) Tc (s) ≡ The ac voltage gain of the op amp error amplifier is Av (s) ≡ 12.9.2 Proportional Controller Figure 12.18 shows a circuit of a proportional controller and its ac equivalent circuit. Assuming an ideal op-amp, The voltage transfer function of an ideal op-amp amplifier is given by Zf (s) v (s) R2 Av (s) ≡ c = Avo . (12.88) =− =− vf (s) Zi (s) R1 + h11 Voltage-Mode Control of PWM Buck Converter 491 R2 h11 vf + vF ~ R1 vE = VE + ve + VF + vC = VC + vc + VR (a) R2 h11 + vf ~ R1 ve + + + vc (b) Figure 12.18 component. Proportional controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac The ac voltage transfer function of the ideal proportional controller is Tc (s) ≡ Zf (s) vc (s) R2 = −Av (s) = = = −Avo = Tco . ve (s) Zi (s) R1 + h11 (12.89) Figure 12.19 shows Bode plots of the proportional controller. The control voltage vc is proportional to the error voltage ve . The proportional control increases the magnitude of the loop gain T and therefore reduces the error Tc 0 f (a) ϕT c 0 (b) Figure 12.19 𝜙Tc . f Bode plots of the ac voltage transfer function Tc of proportional controller. (a) Magnitude |Tc |. (b) Phase 492 Pulse-Width Modulated DC–DC Power Converters voltage. For most systems, there is an upper limit of the controller gain |Tc | in order to achieve a well-damped, stable response. In reality, a compensated op-amp is a first-order system. Therefore, the voltage transfer function of a practical op-amp proportional control circuit is Tc (s) ≡ vc (s) 𝜔H 𝜔1 R2 1 1 = Tco = Tco = = 𝜔1 sTco ve (s) R1 + h11 s + 𝜔H 1+ s s + 1+ 𝜔H 𝜔1 (12.90) Tco where f1 = |Avo |fH is the unity-gain frequency of an op-amp and fH is the upper 3-dB corner frequency. The controller magnitude |Tco | is approximately constant for f < fH and decreases with f for f > fH at the rate of 10 dB/dec. The controller phase 𝜙Tc ≈ 0◦ for f ≤ fH ∕10, decreases with f at the rate of −45◦ /dec for fH ∕10 < f < 10fH , and 𝜙c ≈ −90◦ for f ≥ 10fH . 12.9.3 Integral Controller Figure 12.20 show a circuit of an integral controller and its ac equivalent circuit. The voltage transfer function is 1 Zf (s) v (s) 𝜔 K sC2 1 Av (s) ≡ c =− =− =− =− I =− 1 vf (s) Zi (s) R1 + h11 s(R1 + h11 )C1 s s (12.91) where KI = 1 = 𝜔1 . (R1 + h11 )C1 (12.92) The ac voltage transfer function of the integral controller is 1 Zf (s) v (s) K 𝜔 sC2 1 = = I = 1 = −Av (s) = = Tc (s) ≡ c ve (s) Zi (s) R1 + h11 s(R1 + h11 )C1 s s (12.93) C1 h11 + vF vf ~ R1 vE = VE + ve + VF + vC = VC + vc + VR (a) C1 h11 + vf ~ ve + R1 + + vc (b) Figure 12.20 component. Integral controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac Voltage-Mode Control of PWM Buck Converter 493 Tc 0 f (a) ϕT c 0 f −90° (b) Figure 12.21 Bode plots of the ac voltage transfer function Tc of integral controller. (a) Magnitude |Tc |. (b) Phase 𝜙Tc . where KI = 1∕(R1 + h11 )C1 . Figure 12.21 shows Bode plots of the integral controller. The integral control provides a finite value of the control voltage vc with no error voltage ve . It is no longer necessary for the error signal ve to be finite to produce a finite control voltage vc . Ideally, an integral controller reduces or eliminates the steady-state error. This benefit typically comes at the cost of reduced stability because the integral controller introduces a phase shift equal to −90◦ at all frequencies. The dc voltage gain of an op-amp is limited by the open-loop dc gain AOL . In addition, an op-amp may saturate when the gain is very large. Therefore, a band resistor Rb is usually connected in parallel with the capacitor C1 . This reduces the low-frequency controller voltage gain to Tco = Rb ∕(Rb + R1 + h11 ). In reality, an op-amp is a first-order system. Therefore, the voltage transfer function of the integral control circuit is v (s) K = ( I ). (12.94) Tc (s) ≡ c ve (s) s 1 + s 𝜔H Therefore, KI ∕2𝜋 should be much lower than the unity gain frequency of op-amp f1 . The high-frequency phase of the real integral control circuit is −180◦ . 12.9.4 Proportional-Integral Controller Figure 12.22 shows a circuit of a proportional-integral (PI) controller and its ac equivalent circuit. The ac voltage transfer function of the amplifier shown in Figure 12.22(b) is given by [ ) ] ( R2 + sC1 Zf (s) vc (s) R2 K 1 1 Av (s) ≡ =− + =− =− = − KP + I vf (s) Zi (s) R1 + h11 R1 + h11 s(R1 + h11 )C1 s (12.95) 494 Pulse-Width Modulated DC–DC Power Converters R2 R1 h11 + vF vf ~ vE = VE + ve + VF C1 + vC = VC + vc + VR (a) R2 h11 + vf ~ C1 R1 ve + + + vc (b) Figure 12.22 Proportional-integral (PI) controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component. where R2 R1 + h11 (12.96) 1 . (R1 + h11 )C1 (12.97) KP = and KI = The ac voltage transfer function of the PI controller is 1 Zf (s) R2 + sC1 vc (s) R2 1 = −Av (s) = = = + Tc (s) ≡ ve (s) Zi (s) R1 + h11 R1 + h11 s(R1 + h11 )C1 ( ) KI K s + P KP (s + 𝜔z ) K s + KI K KP = = = KP + I = P s s s s (12.98) where KI 1 = KP R2 C1 (12.99) 𝜔z KI 1 = = . 2𝜋 2𝜋KP 2𝜋R2 C1 (12.100) 𝜔z = 2𝜋fz = −z = and fz = Figure 12.23 shows Bode plots of the ac voltage transfer function Tc of the PI controller. Figures 12.24 and 12.25 show Bode plots of Tc for KP = 10 and fz = 10 Hz. The PI controller is a low-pass filter and reduces switching noise. However, it also reduces the bandwidth, increases the rise time, and increases the setting time. Voltage-Mode Control of PWM Buck Converter 495 Tc 0 f (a) ϕT c 0 f −90° (b) Figure 12.23 Bode plots of the ac voltage transfer function Tc of proportional-integral (PI) controller. (a) Magnitude |Tc |. (b) Phase 𝜙Tc . 60 55 50 | Tc | (dB) 45 40 35 30 25 20 1 10 2 10 3 10 f (Hz) 4 10 5 10 Figure 12.24 Bode plot of the magnitude |Tc | of the ac voltage transfer function Tc of proportional-integral (PI) controller at KP = 10 and fz = 1 kHz. 496 Pulse-Width Modulated DC–DC Power Converters 0 −10 −20 −40 c ϕ T (°) −30 −50 −60 −70 −80 −90 1 10 2 3 10 10 f (Hz) 4 10 5 10 Figure 12.25 Bode plot of the phase 𝜙Tc of the ac voltage transfer function Tc of proportional-integral (PI) controller at KP = 10 and fz = 1 kHz. A design procedure of the PI controller is as follows. At the gain-crossover frequency fc , the magnitude of the loop gain is |T(fc )| = |Tk (fc )||Tc (fc )| = |Tk (fc )|KP = 1. (12.101) where Tk is the uncompensated loop gain. Hence, the gain of the proportional part of the controller is KP = |Tk (fc )| 1 = 20 log |Tk (fc )|(dB) = 10− 20 . |Tk (fc )| (12.102) If fz ≤ fc ∕10, the phase lag of the PI controller has a negligible effect on the phase of the compensated loop gain near the gain-crossover frequency fc . The corner frequency fz should not be too low because the bandwidth BW will be narrow, increasing the rise time and the settling time. The frequency of the controller zero fz should be at least one decade lower than the gain-crossover frequency fc . Thus, the coefficient of the integral part of the controller is 𝜔c KI = 10 10KP (12.103) 𝜔c 2𝜋fc K = K . 10 P 10 P (12.104) 𝜔z = producing KI = Assuming a standard value of capacitance C1 , we obtain R1 = RA RB 1 1 − h11 = − KI C1 KI C1 RA + RB (12.105) Voltage-Mode Control of PWM Buck Converter 497 and R2 = KP R1 . (12.106) 12.9.5 Integral-Single-Lead Controller To avoid excessive oscillations in closed-loop converters when load and input voltage change, integral, proportional, or PI controllers are used. Derivative controllers are not used to avoid the differentiation of the switching actions. When integral controllers are used, a low dc error is achieved by sacrificing the speed of the transient response because of a narrow bandwidth. On the other hand, when proportional controllers are used, a fast transient response is achieved by sacrificing the dc steady-state error because the dc gain is low. When proportional-integral (PI) controllers are used with the proportional gain set to a low level, the dc error will be reduced, the oscillations can be avoided, and a comparatively slower system will result. An integral-single lead (or type II) controller, also called the type II controller [4], is shown in Figure 12.26(a). The circuit has a pole at the origin and a single pole–zero pair. The pole at the origin forms the integral part of the controller and the pole–zero pair forms the lead part of the controller. Since the magnitude of the controller transfer function has two slopes, the circuit is called the type II controller. An integral circuit is called the type I controller. The controller is an inverting op amp with a dc reference voltage source VR . Setting the dc reference voltage VR to zero, one obtains an equivalent circuit for the ac component, as depicted in Figure 12.26(b). The controller is used to obtain a low steady-state (dc) error and fast transient responses. The primary reason for using an integral controller is to obtain very high values of the gain at low frequencies and therefore reduce the dc error, but this benefit typically comes at the expense of reduced stability. This is because the integral controller introduces a phase lag of −90◦ at all frequencies. The phase lag can partially be compensated (reduced) by means of a lead controller. The task for the lead controller is to reduce the phase lag and therefore achieve a high crossover frequency fc , C2 C1 R2 h11 + vF vf ~ R1 vE = VE + ve + VF + vC = VC + vc + VR (a) C2 R2 h11 + vf ~ ve + C1 R1 + + vc (b) Figure 12.26 Integral-single-lead controller (type II controller). (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component. 498 Pulse-Width Modulated DC–DC Power Converters while maintaining a specified phase margin PM. The crossover frequency fc is defined as the frequency at which the magnitude of the loop gain |T| crosses 1 or 0 dB. A high crossover frequency fc normally results in a wide bandwidth of the closed-loop system, yielding a fast response. The crossover frequency is usually equal to fs ∕5. The capacitor C2 and the resistance R1 + h11 form the integral part of the controller, which ideally introduces a pole at the origin. The capacitor C1 and the resistor R2 introduce a zero. The resistor R2 and the series combination of C1 and C2 introduce a pole. The capacitance C1 is usually much higher than the capacitance C2 , and therefore the frequency of the pole fpc is much higher than the frequency of the zero fzc . Let us assume that the operational amplifier is ideal, that is, its open-loop dc gain and bandwidth are infinite. The voltage transfer function of the amplifier shown in Figure 12.26(a) is given by ( ) 1 R2 + sC1 s + R 1C Zf (s) vc (s) sC2 1 1 2 1 Av (s) ≡ =− =− ( ( ) =− ) . (12.107) C1 +C2 1 1 vf (s) Zi (s) C (R + h ) 2 1 11 (R1 + h11 ) R2 + sC + sC s s+ R C C 1 2 2 Since ve = vr − vf = −vf at vr = 0, the voltage transfer function of the integral-lead controller is ( ) ) ( s s 1 + B𝜔 B 1 + zc B(s + 𝜔zc ) 𝜔zp v (s) 𝜔zc Tc (s) ≡ c = −Av (s) = = ( ( ) = ) s ve (s) s(s + 𝜔pc ) 𝜔 s 1+ K2s 1 + s pc 𝜔pc 1 2 (12.108) 𝜔pc where B= 1 C2 (R1 + h11 ) (12.109) 1 R2 C1 (12.110) ) C1 + 1 𝜔zc = K 2 𝜔zc C2 (12.111) 𝜔zc = C + C2 = 𝜔pc = 1 R2 C1 C2 and √ K= ( 𝜔pc 𝜔zc √ = C1 + 1. C2 (12.112) It can be seen from (12.108) that the integral-lead controller introduces a pole at the origin in addition to a pole–zero pair. The pole at the origin provides a very high gain at low frequencies like an integral controller and the zero–pole pair provides a constant gain and a reduced phase shift between the zero frequency fzc and the pole frequency fpc like a lead controller. Therefore, the controller provides a very high gain at low frequencies as an integral controller and a reduced phase lag between the zero and pole frequencies. Substitution of s = j𝜔 into (12.108) yields the frequency response of the integral-lead controller ( ) B 1 + j 𝜔𝜔 zc Tc (j𝜔) = (12.113) ) = |Tc |ej𝜙Tc ( 𝜔 2 K j𝜔 1 + j 𝜔 pc where √ ( )2 √ √ √1 + 𝜔 𝜔zc B √ √ ∣ Tc ∣= ( )2 𝜔K 2 √ 1 + 𝜔𝜔 pc (12.114) Voltage-Mode Control of PWM Buck Converter 499 and 𝜔 𝜔 ⎛𝜔 −𝜔 ⎞ zc pc 𝜋 ⎟. 𝜙Tc = − + tan−1 ⎜ ⎜ 1 + 𝜔2 ⎟ 2 ⎝ 𝜔zc 𝜔pc ⎠ (12.115) The integral part of |Tc | occurs for f ≪ fzc , which can be approximated by B (12.116) |Tc | ≈ 2 . K 𝜔 This means that |Tc | for an integral-lead controller is K 2 times lower than that for a standard integral controller at f < fzc . Figure 12.27 shows the idealized Bode plots for the voltage transfer function of the integral-lead controller. The magnitude |Tc | decreases with frequency at a rate of −20 dB/dec at low frequencies like for an integral controller, it is constant and equal to |Tcm | = R2 ∕(h11 + R1 ) at mid-frequencies like for a proportional controller, and decreases with frequency again at a rate of −20 dB/dec at high frequency like for an integral controller. This last part of |Tc | is useful in switching power supply applications because it reduces the magnitudes of the switching frequency and its harmonics. The phase shift starts from −90◦ at low frequencies like for an integral controller, reaches its maximum value at frequency fm like for a lead controller, and decreases back to −90◦ at high frequencies like for an integral controller. Setting the derivative of the term in the parenthesis of (12.115) to zero and using (12.112), one obtains the frequency at which the phase shift 𝜙Tc reaches a maximum value 𝜔pc √ K 𝜔m = 𝜔zc 𝜔pc = = K𝜔zc = . (12.117) K R2 C1 Thus, the maximum value of the phase 𝜙Tc(max) = 𝜙Tc (fm ) occurs at the geometrical mean value of the zero and pole frequencies. Substitution of (12.117) into (12.115) gives √ √ ⎛ fpc fzc ⎞ − ) ( 2 ( 2 ) ⎜ fzc fpc ⎟ 𝜋 K −1 K −1 𝜋 𝜋 −1 −1 ⎜ −1 ⎟ = − + tan . (12.118) 𝜙Tc (fm ) = − + tan = − + sin ⎟ ⎜ 2 2 2 2K 2 K2 + 1 ⎟ ⎜ ⎠ ⎝ Tc −20 dB/dec −20 dB/dec 0 ϕ Tc 0 −45° fpc fzc fzc = fm K fm f fpc = Kfm f ϕm −90° Figure 12.27 Idealized Bode plots for the integral-lead controller (type II controller). 500 Pulse-Width Modulated DC–DC Power Converters Hence, the maximum amount of the phase shift reduction, also called a phase boost, is ) ( 2 ( 2 ) ) ( 𝜋 𝜋 K −1 K −1 −1 −1 𝜙m = 𝜙Tc (fm ) − − = 𝜙Tc (fm ) + = tan = sin 2 2 2K K2 + 1 from which ( ) [ ] 𝜙m 𝜙Tc (fm ) ◦ K = tan + 45 = cot . 2 2 (12.119) (12.120) Hence, 𝜋 + 2 arctan K. (12.121) 2 Figure 12.28 illustrates the relationship between 𝜙m and K. It can be seen that the phase boost 𝜙m increases from 0 to 90◦ as K is increased from 0 to ∞. The required amount of phase boost 𝜙m can be achieved by adjusting the spread of the zero and pole frequencies K 2 = fpc ∕fzc . Substitution (12.117) into (12.114) yields the magnitude of the controller voltage transfer function at the frequency fm B ∣ Tc (fm ) ∣= . (12.122) K𝜔m Substituting (12.109) into (12.122) and using (12.111) and (12.117) produces ( ) R2 1 1 = 1− 2 . (12.123) |Tc (fm )| = 𝜔m KC2 (R1 + h11 ) R1 + h11 K The crossover frequency fc is the frequency at which the loop-gain magnitude |T| is equal to unity 𝜙m = − |T(fc )| = 1 = 0 dB. (12.124) It indicates the frequency range, in which negative feedback is effective in attenuating audio susceptibility and output impedance. 90 80 70 ϕm (°) 60 50 40 30 20 10 0 0 Figure 12.28 10 20 K 30 40 50 Plot of phase 𝜙m versus K for the integral-lead controller (type II controller). Voltage-Mode Control of PWM Buck Converter 501 Relative stability of closed-loop linear systems is measured by two criteria: the gain margin GM and the phase margin PM. The gain margin GM is defined as the reciprocal of the loop-gain magnitude at the frequency f−180 at which the loop-gain phase angle reaches −180◦ GM ≡ 1 = −20 log |T(f−180 )|. |T(f−180 )| (12.125) It indicates how many times the loop-gain magnitude can be increased before the system becomes unstable. Typical gain margins range from 6 to 12 dB. The phase margin PM is defined as the amount of the loop-gain phase lag at the crossover frequency fc that is required to bring the system to the verge of instability PM ≡ 180◦ + 𝜙T (fc ). (12.126) Typical phase margins range from 45◦ to 75◦ . A lower phase margin gives faster transient response and shorter settling time, but more peaking in the closed-loop transfer function and higher ringing and overshoot in transient responses. The integral-lead controller is usually designed in such a way that the gain crossover frequency fc is equal to the frequency fm . The magnitude of the loop gain at the crossover frequency fc is |T(fc )| = |Tc (fc )||Tk (fc )| = |Tc (fc )||Tmp (fc )|𝛽 = 1. (12.127) Hence, using (12.123), one obtains the required value of the controller transfer function magnitude at the crossover frequency fc |Tc (fc )| = 1 1 1 = = . |Tk (fc )| 𝛽|Tmp (fc )| 𝜔c KC2 (R1 + h11 ) (12.128) Using (12.119), the phase of the loop gain at the crossover frequency fc is given by 𝜙T (fc ) = 𝜙Tk (fc ) + 𝜙Tc (fc ) = 𝜙Tk (fc ) − 90◦ + 𝜙m . (12.129) Hence, the phase margin can be expressed as PM ≡ 180◦ + 𝜙T (fc ) = 180◦ + 𝜙Tk (fc ) + 𝜙Tc (fc ) = 90◦ + 𝜙Tk (fc ) + 𝜙m (12.130) which leads to the required phase boost 𝜙m = PM − 𝜙Tk (fc ) − 90◦ . (12.131) Example 12.6 Design an integral-lead controller for the buck converter given in Example 12.5 with |Tko | = 0.998, h11 = 3.2683 kΩ, 𝜉 = 0.2298, f0 = 1.2677 kHz, and fz = 7.95 kHz. The required phase margin is PM = 45◦ . Draw Bode plots of the controller transfer function Tc . Solution: Let us assume that fc = fm = 8 kHz. Substitution of f0 = 1.2677 kHz, fz = 7.95 kHz, and 𝜉 = 0.2298 into (12.75) yields ( ) ( ) fc ⎡ ⎤ ⎡ ⎤ 8 ( ) 2𝜉 2 × 0.2298 × ) ( fc ⎥ f0 1.2677 ⎥ 8 ◦ −1 −1 ⎢ ◦ −1 −1 ⎢ 𝜙Tk (fc ) = −180 + tan − tan ⎢ − tan ⎢ ⎥ ( )2 ⎥ = −180 + tan ( )2 fz 7.95 8 ⎢ 1 − fc ⎥ ⎢ ⎥ 1 − ⎣ ⎦ ⎣ ⎦ f 1.2677 0 ◦ ◦ ◦ ◦ = −180 + 45.18 + 4.27 = −130.55 . (12.132) Since the required phase margin is PM = 45◦ , 𝜙m = PM − 𝜙Tk (fc ) − 90◦ = 45◦ + 130.55◦ − 90◦ = 85.55◦ . (12.133) 502 Pulse-Width Modulated DC–DC Power Converters Hence, ( K = tan 𝜙m + 45◦ 2 ) ( = tan 85.55◦ + 45◦ 2 ) = 25.738. (12.134) From (12.73) and (12.76), √ ( )2 √ √ fc √ 1 + √ fz |Tk (fc )| = 𝛽 ∣ Tmp (fc ) ∣= Tko √ √[ ( )2 ]2 ( )2 √ f f 1 − fc + 4𝜉 2 fc 0 0 √ √ ( )2 √ 8 √ 1 + √ 7.95 = 0.998√ = 0.03635 = −28.79 dB. √[ ( ( )2 ]2 )2 √ 8 8 1 − 1.2677 + 4 × 0.22982 × 1.2677 (12.135) The magnitude of the voltage transfer function of the controller at the crossover frequency fc is |Tc (fc )| = 1 1 = = 27.51 = 28.79 dB. |Tk (fc )| 0.03635 (12.136) Using (12.122) and (12.117), B = 𝜔c K|Tc (fc )| = 2𝜋 × 8000 × 25.738 × 27.495 = 35.59 × 106 ( rad sec ) (12.137) f f 8 × 103 fzc = m = c = = 310.82 Hz K K 25.738 (12.138) fpc = Kfm = Kfc = 25.738 × 8 × 103 = 205.9 kHz. (12.139) and Bode plots of Tc of the designed controller are shown in Figure 12.29. Assuming R1 = 1 k∕0.25 W∕1%Ω and using (12.128), C2 = ∣ Tk (fc ) ∣ 0.03637 = = 6.568 pF. 𝜔c K(h11 + R1 ) 2 × 𝜋 × 8 × 103 × 25.738 × (3.2683 + 1) × 103 (12.140) Pick C2 = 6.8 pF/12 V. Using (12.112), C1 = C2 (K 2 − 1) = 6.8 × 10−12 × (25.7382 − 1) = 4.5 nF. (12.141) Pick C1 = 4.7 nF/24 V. From (12.117), R2 = K 25.738 = = 108.8 kΩ. 𝜔c C1 2 × 𝜋 × 8 × 103 × 4.7 × 10−9 (12.142) Pick R2 = 110 kΩ/0.25 W/1%. Bode plots of Tc of the designed controller are shown in Figures 12.29 and 12.30. At low frequencies, the controller behaves like an integrator. As the frequency f is increased from zero, the magnitude ∣ Tc ∣ decreases with a slope of −20 dB/decade, then remains almost constant between fzc and fpc , and finally decreases again with a slope of −20 dB/decade. A high gain ∣ Tc ∣ at f = 0 enables the converter to achieve a low dc error. As the frequency is increased, the phase shift 𝜙Tc is −90◦ for f < fzc ∕10, reaches its maximum value at a frequency fm , and is −90◦ for f > 10fpc . The controller behaves like a lead controller for frequencies ranging from fzc to fpc . Voltage-Mode Control of PWM Buck Converter 503 60 50 | Tc| (dB) 40 30 20 10 1 10 Figure 12.29 2 3 10 4 10 f (Hz) 5 10 6 10 10 Bode plot of the magnitude of Tc for fzc = 310.82 kHz, fzp = 205.9 kHz, and B = 35.57 × 106 rad/s. 0 −15 c ϕT (°) −30 −45 −60 −75 −90 1 10 Figure 12.30 2 10 3 10 4 f (Hz) 10 5 10 6 10 Bode plot of the phase of Tc for fzc = 310.82 kHz, fzp = 205.9 kHz, and B = 35.57 × 106 rad/s. 504 Pulse-Width Modulated DC–DC Power Converters In reality, the pure integral control concept cannot be implemented because of a finite dc open-loop voltage gain of op-amps, voltage and current offsets of op-amps, and noise level. The maximum achievable magnitude of the controller dc gain without a bound resistor is Tc (0) = AOL (12.143) where AOL is the dc open-loop gain of op-amps. For example, AOL = 200, 000 for a 741 op-amp. Furthermore, the dc voltage gain of the controller should be made lower than AOL because of voltage and current offsets of an op-amp and noise level. If the dc gain is not limited, the dc offset voltage would be integrated and eventually saturate the operation amplifier. The dc gain of the op-amp can be reduced by connecting a resistor Rb (called a bound resistor) in parallel with the capacitor C2 . The dc gain of the controller in this case is Tco = Tc (0) = Rb . R1 + h11 (12.144) Usually, Tco is limited to the range from 1000 to 3000. For example, to obtain Tco = 1000, Rb = Tco (R1 + h11 ) = 1000(1 + 3.2683) = 4.2368 MΩ. Pick Rb = 4.3 MΩ/0.25 W/1%. 12.9.6 Loop Gain Using (12.71) and (12.108), one obtains the loop gain T(s) ≡ = vf (s) || = 𝛽A(s) = 𝛽Tc (s)Tmp (s) = 𝛽Tc (s)Tm Tp (s) | ve (s) ||v =i =0 i o 𝛽BVI RL 𝜔20 s + 𝜔z s + 𝜔z s + 𝜔zc s + 𝜔zc = Tx 2 2 2 (RL + r)VTm 𝜔z s(s + 𝜔pc ) s + 2𝜉𝜔0 s + 𝜔0 s(s + 𝜔pc ) s + 2𝜉𝜔0 s + 𝜔20 (12.145) where Tx = 𝛽BTm Tpx = 𝛽BVI RL rC . VTm L(RL + rC ) (12.146) Note that if R1 = 0, then 𝛽B = 1∕(C2 RA ). Example 12.7 Draw Bode plots of the loop gain T for the buck converter of Example 12.5 with the controller of Example 12.6. What is the gain crossover frequency fc and the phase margin PM? Find the dc loop gain To = T(0) if Tc (0) = AOL = 200,000. Solution: Plots of T are shown in Figures 12.31 and 12.32. The gain crossover frequency fc is 8 kHz, and the phase margin is approximately 45◦ . Hence, fs ∕fc = 100∕8 = 12.5. The dc loop gain is To = T(0) = Tc (0)Tko = AOL Tko = 200,000 × 0.998 = 199,600 = 106 dB. (12.147) 12.9.7 Closed-Loop Control-to-Output Voltage Transfer Function The closed-loop control-to-output transfer function is given by Tcl (s) ≡ Tc (s)Tm Tp (s) vo (s) || T(s) A = = = | vr (s) ||v =i =0 𝛽[1 + T(s)] 1 + 𝛽A 1 + 𝛽Tc (s)Tm Tp (s) i o (s + 𝜔zc )(s + 𝜔z ) T . = x ) ( 𝛽 s(s + 𝜔pc ) s2 + 2𝜉𝜔0 s + 𝜔2 + Tx (s + 𝜔zc )(s + 𝜔z ) 0 (12.148) Voltage-Mode Control of PWM Buck Converter 60 40 | T| (dB) 20 0 −20 −40 1 10 2 3 10 Figure 12.31 10 f (Hz) 4 5 10 10 Bode plot of the magnitude of loop gain T. −30 −60 ϕ T (°) −90 −120 −150 −180 1 10 2 10 Figure 12.32 3 10 f (Hz) 4 10 Bode plot of the phase of loop gain T. 5 10 505 506 Pulse-Width Modulated DC–DC Power Converters 20 | Tcl| (dB) 10 0 −10 −20 1 10 Figure 12.33 2 10 3 10 f (Hz) 4 10 5 10 Bode plot of the magnitude of closed-loop transfer function Tcl . Example 12.8 Draw Bode plots of the closed-loop control-to-output transfer function Tcl for the converter of Example 12.7. What is the 3-dB bandwidth of the closed-loop converter? Find the dc closed-loop voltage control-to-output voltage transfer function. Solution: Figures 12.33 and 12.34 show Bode plots of Tcl . The 3-dB bandwidth of the closed-loop converter BW is approximately 10 kHz. The dc closed-loop voltage control-to-output transfer function is Tclo = Tcl (0) ≈ 1 1 = = 2.8 = 8.9432 dB. 𝛽 5∕14 (12.149) 12.9.8 Closed-Loop Input-to-Output Transfer Function The closed-loop input-to-output voltage transfer function is Mvcl (s) ≡ s(s + 𝜔pc )(s + 𝜔z ) Mv (s) vo (s) || = Mvx = . | ) ( vi (s) ||v =i =0 1 + T(s) s(s + 𝜔pc ) s2 + 2𝜉𝜔0 s + 𝜔2 + Tx (s + 𝜔zc )(s + 𝜔z ) r o (12.150) 0 Example 12.9 Draw Bode plots of the closed-loop input-to-output transfer function Mvcl for the converter of Example 12.8. Find the dc closed-loop input-to-output transfer function if Mvo = Mv (0) = 0.5463 and To = 199,600. Find a change in the output voltage if the dc change in the input voltage is ΔVI = 1 V. Solution: Figures 12.35 and 12.36 show Bode plots of Mvcl . The dc closed-loop input-to-output transfer function is Mvclo = Mvcl (0) = Mvo 0.5463 = 2.737 × 10−6 = −111.25 dB. = 1 + To 1 + 199,600 (12.151) Voltage-Mode Control of PWM Buck Converter 0 cl ϕT (°) −30 −60 −90 −120 1 10 Figure 12.34 2 10 3 10 f (Hz) 4 10 5 10 Bode plot of the phase of closed-loop transfer function Tcl . −30 | Mvcl| (dB) −40 −50 −60 −70 1 10 Figure 12.35 2 10 3 10 f (Hz) 4 10 5 10 Bode plot of the magnitude of the closed-loop input-to-output transfer function Mvcl . 507 508 Pulse-Width Modulated DC–DC Power Converters 90 60 30 vcl ϕM (°) 0 −30 −60 −90 −120 1 10 Figure 12.36 2 3 10 4 10 f (Hz) 10 5 10 Bode plot of the phase of the closed-loop input-to-output transfer function Mvcl . The change in the dc output voltage is ΔVO = Mvclo ΔVI = 2.737 × 10−6 × 1 = 2.7 μV. (12.152) 12.9.9 Closed-Loop Input Impedance Referring to the block diagram shown in Figure 12.7(b) and setting vr = 0, v o = T p d + Mv v i (12.153) d = −𝛽vo Tc Tm = −(Tp d + Mv vi )𝛽Tc Tm = −𝛽Tc Tm Tp d − 𝛽Tc Tm Mv vi (12.154) and from which d=− 𝛽Tc Tm Mv v =− 1 + 𝛽Tc Tm Tp i ( Mv Tp )( ) T v. 1+T i (12.155) From the small-signal analysis, Mv D = Tp VI (12.156) and therefore (12.155) becomes ( d=− D VI )( ) T v. 1+T i (12.157) Voltage-Mode Control of PWM Buck Converter 509 From the dc model of the buck converter of Figure 10.24, IL = DVI DVI − (1 − D)VF ≈ . RL + r RL + r (12.158) Referring to Figure 12.7(a) and using the relationship Zi = (Z1 + Z2 )∕D2 , the current through the inductor is il = Dvi + VI d Dvi + VI d = . Z1 + Z2 D2 Zi (12.159) Using (12.157), (12.158), and (12.159), one arrives at the closed-loop input admittance ( ) i Di + IL d Vd 1 1 d 1+ I + IL ≡ i ∣vr =io =0 = l = Yicl = Zicl vi vi Zi Dvi vi = DI 1 1 D2 1 1 T T − L = − . Zi 1 + T VI 1 + T Zi 1 + T R L + r 1 + T (12.160) Hence, the closed-loop input impedance is Zicl = ( ) s(s + 𝜔pc ) s2 + 2𝜉𝜔0 s + 𝜔20 + Tx (s + 𝜔zc )(s + 𝜔z ) 2 D2 s(s + 𝜔pc )(s + 𝜔rc ) − RD+r Tx (s + 𝜔zc )(s + 𝜔z ) L L . (12.161) For s = 0, |T| ≫ 1, yielding 1∕(1 + T) ≈ 0 and T∕(1 + T) ≈ 1. Hence, the closed-loop input resistance is negative at dc and low frequencies RL + r ≈ −Zi (0) = −Ri (0). (12.162) D2 For f ≫ fc , |T| ≪ 1 and therefore the closed-loop input impedance at high frequencies can be approximated by Zicl (0) = Ricl (0) = − Zicl ≈ Zi (1 + T) ≈ Zi . (12.163) Example 12.10 Calculate the closed-loop input impedance Zicl at f = 0, RLmin = 10 Ω, r = 0.16 Ω, and Dnom = 0.555. Draw Bode plots of the closed-loop input impedance Zicl for the converter of Example 12.8. Solution: The closed-loop input impedance is Zicl (0) = Ricl (0) = − RLmin + r 10 + 0.16 =− = −32.98 Ω. D2nom 0.5552 (12.164) Figures 12.37 and 12.38 depict plots of Zicl . The phase 𝜙Zicl is −180◦ at low frequencies. Thus, the input resistance is negative in this frequency range. This may cause instability leading to oscillations. 12.9.10 Closed-Loop Output Impedance The closed-loop output impedance is s(s + 𝜔pc )(s + 𝜔z )(s + 𝜔rl ) v (s) || Zo (s) Zocl (s) ≡ t | = Zox = ) ( it (s) ||v =v =0 1 + T(s) s(s + 𝜔pc ) s2 + 2𝜉𝜔0 s + 𝜔20 + Tx (s + 𝜔zc )(s + 𝜔z ) r i (12.165) where vt is a test voltage applied at the output of the converter and it is a current developed by the voltage vt . The closed-loop output impedance excluding the load resistance RL is 1 1 1 = − . ′ Zocl RL Zocl ′ ≈ Zocl . Since ∣ Zocl ∣≪ RL , Zocl (12.166) Pulse-Width Modulated DC–DC Power Converters 100 90 80 icl | Z | (Ω) 70 60 50 40 30 20 1 10 Figure 12.37 2 3 10 10 f (Hz) 4 5 10 10 Magnitude of the closed-loop input impedance Zicl . 30 0 −30 −60 icl ϕZ (°) 510 −90 −120 −150 −180 1 10 Figure 12.38 2 10 3 10 f (Hz) 4 10 Phase of the closed-loop input impedance Zicl . 5 10 Voltage-Mode Control of PWM Buck Converter 511 0.8 0.7 0.6 | Zocl| (Ω) 0.5 0.4 0.3 0.2 0.1 0 1 10 2 3 10 10 f (Hz) Figure 12.39 4 10 5 10 Magnitude of Zocl . Example 12.11 Draw Bode plots of the closed-loop output impedance Zocl for the converter of Example 12.8. Find the dc output resistance if Ro = 0.157 Ω and To = 199,600. Solution: Plots of Zocl are displayed in Figures 12.39 and 12.40. It can be seen that negative feedback considerably reduces the output impedance magnitude of the converter at low frequencies, where |T| ≫ 1. For example, the closed-loop output impedance |Zocl | = 1.9 mΩ at frequency f = 100 Hz. The maximum value of the magnitude of the closed-loop output impedance |Zocl | occurs at frequency f = 7.2 kHz and is equal to 0.74 Ω. Note that the output impedance of an ideal voltage-source power supply should be zero at all frequencies. The dc output resistance is Rocl = Ro 0.157 = 78.657 μΩ. = 1 + To 1 + 199,600 (12.167) 12.10 Closed-Loop Step Responses 12.10.1 Response to Step Change in Input Voltage If there is a step change in the input voltage ΔVI at time t = 0 and the steady-state input voltage before the step change is VI (0− ), the total input voltage is given by vI (t) = VI (0− ) + ΔVI u(t) (12.168) resulting in a step change in the input voltage vi (t) = vI (t) − VI (0− ) = ΔVI u(t) (12.169) and vi (s) = ΔVI . s (12.170) 512 Pulse-Width Modulated DC–DC Power Converters 150 120 ϕZ ocl (°) 90 60 30 0 −30 1 10 2 3 4 10 10 f (Hz) 10 Figure 12.40 Phase of Zocl . 5 10 The transient component of the output voltage is vo (s) = Mvcl (s)vi (s) = ΔVI Mv (s) ΔVI Mvcl (s) = . s s[1 + T(s)] (12.171) Taking the inverse Laplace transform, one obtains the transient component of the output voltage vo (t) = −1 {vo (s)} for t≥0 (12.172) vO (t) = VO (0− ) + vo (t) for t ≥ 0. (12.173) and the total output voltage Example 12.12 Draw the total output voltage vO (t) of the closed-loop buck converter of Example 12.8 as a response to the step change in the input voltage from 28 to 29 V. Find the maximum transient ripple of the total output voltage vO . Solution: Figure 12.41 shows a step response of the output voltage vO to a step change in the input voltage vI from 28 to 29 V for the buck converter with negative feedback. The output voltage increases from 14 to 14.02451 V and then returns to VO = 14 V after 3 ms. The maximum relative transient ripple of the output voltage is 𝛿max = vOmax − vO (∞) 14.0245 − 14 0.0245 = = = 0.175%. vO (∞) 14 14 (12.174) Voltage-Mode Control of PWM Buck Converter 513 14.025 14.02 O v (V) 14.015 14.01 14.005 14 Figure 12.41 0 0.5 1 1.5 t (ms) 2 2.5 3 Step response of vO to a step change in vI from 28 to 29 V for the buck converter with negative feedback. 12.10.2 Response to Step Change in Reference Voltage Let us now consider a step change in the reference voltage ΔVR starting at VR (0− ) at time t = 0. The total reference voltage can be described by vR (t) = VR (0− ) + ΔVR u(t) (12.175) vr (t) = vR (t) − VR (0− ) = ΔVR u(t) (12.176) from which and vr (s) = ΔVR . s (12.177) The transient component of the output voltage is given by vo (s) = Tcl (s)vr (s) = ΔVR Tcl (s) ΔVR A(s) = . s s[1 + T(s)] (12.178) Taking the inverse Laplace transform, one obtains the transient component of the output voltage vo (t) = −1 {vo (s)} for t≥0 (12.179) vO (t) = VO (0− ) + vo (t) for t ≥ 0. (12.180) and the total output voltage 514 Pulse-Width Modulated DC–DC Power Converters 18 17.5 17 vO (V) 16.5 16 15.5 15 14.5 14 Figure 12.42 0 0.25 0.5 t (ms) 0.75 1 Step response of vO to a step change in vR from 5 to 6 V for the buck converter with negative feedback. Example 12.13 Draw the total output voltage vO (t) of the closed-loop buck converter of Example 12.8 as a response to the step change in the reference voltage from 5 to 6 V. Find the maximum overshoot and the maximum transient ripple. Calculate also an increase in the steady-state output voltage. Solution: Figure 12.42 shows the step response of the output voltage vO to a step change in the reference voltage vR from 5 to 6 V, which corresponds to a step change in the ac component of the reference voltage vr from 0 to 1 V, for the buck converter with negative feedback. The total output voltage vO increase from 14 to 17.74 V and reaches a steady-state value of 16.8 V after 0.3 ms. The maximum overshoot is vomax − vo (∞) 3.74 − 2.8 0.94 = = = 33.57%. vo (∞) 2.8 2.8 (12.181) vOmax − vO (∞) 17.74 − 16.8 0.94 = = = 5.59%. vO (∞) 16.8 16.8 (12.182) Smax = The maximum transient ripple is 𝛿max = When the reference voltage is VR = 5 V and the output voltage is VO = 14 V, the dc closed-loop voltage transfer function is Tclo = VO 14 = 2.8 V. = VR 5 (12.183) The increase of the reference voltage VR from 5 to 6 V causes the output voltage VO to increase to VO = Tclo VR = 2.8 × 6 = 16.8 V (12.184) Voltage-Mode Control of PWM Buck Converter 515 or VO = Tclo VR ≈ VR 6 = = 16.8 V. 𝛽 0.3571 (12.185) Thus, the increase in the steady-state output voltage is ΔVO = Tclo ΔVR = 2.8 × 1 = 2.8 V. (12.186) Consequently, the output voltage vO increases from 14 V to approximately 16.8 V. 12.10.3 Closed-Loop Response to Step Change in Load Current The load current with a step change ΔIO at t = 0 can be expressed by iO (t) = IO (0− ) + ΔIO u(t). (12.187) Therefore, the step change in the load current in the time domain is io (t) = iO (t) − IO (0− ) = ΔIO u(t) (12.188) and the s-domain is ΔIO . s Hence, using (12.165), one obtains the transient component of the output voltage in the s-domain io (s) = vo (s) = −Zocl (s)io (s) = − s(s + 𝜔pc )(s + 𝜔z )(s + 𝜔rl ) ΔIO L . ) ( 2 D s2 (s + 𝜔pc ) s2 + 2𝜉𝜔0 s + 𝜔20 + Tx (s + 𝜔zc )(s + 𝜔z ) (12.189) (12.190) The inverse Laplace transform of vo (s) gives the transient component of the output voltage vo (t), which leads to the total output voltage vO (t) = VO (0− ) + vo (t). Example 12.14 Draw the total output voltage vO (t) of the closed-loop buck converter of Example 12.8 as a response to the step change in the load current IO from 1.4 to 1.5 A. Find the maximum transient ripple. Solution: Figure 12.43 shows the step response of the output voltage vO to a step change in the load current IO from 1.4 to 1.5 A, which corresponds to a step change in the ac component of the load current io from 0 to 0.1 A, for the buck converter with negative feedback. The total output voltage vO decreases from 14 to 13.96 V and reaches a steady-state value of 14 V after 0.4 ms. The maximum transient zero-to-peak ripple of the output voltage is 𝛿max = |vOmin − vO (∞)| |13.96 − 14| = = 0.286%. vO (∞) 14 (12.191) The step change in the output voltage at t = 0 is ΔVO = rC ||RL ΔIO ≈ −rC ΔIO = −0.391 × 0.1 = −39.1 mV. The value of the filter capacitor ESR rC has a significant influence on the output voltage response to a step change in the load current. 12.10.4 Closed-Loop DC Transfer Functions Figure 12.44 shows a closed-loop model and control block diagrams. The dc forward-path voltage transfer function is Ao = A(0) = Tco Tm Tpo . (12.192) To = T(0) = 𝛽Ao = 𝛽Tco Tm Tpo . (12.193) The dc loop gain is 516 Pulse-Width Modulated DC–DC Power Converters 14.02 14.01 vO (V) 14 13.99 13.98 13.97 13.96 13.95 0 0.25 0.5 0.75 t (ms) 1 1.25 1.5 Figure 12.43 Step response of vO to a step change in the load current IO from 1.4 to 1.5 A for the buck converter with negative feedback. (1− D)VF r IL VI + VD I ILD + + VR VE TC VC RL Tm + VO D VF β + VF Figure 12.44 RB RA + VO Closed-loop dc model of the PWM buck converter. Voltage-Mode Control of PWM Buck Converter 517 The dc closed-loop control-to-output gain is Tclo = Ao . 1 + 𝛽Ao (12.194) Roclo = Ro . 1 + 𝛽Ao (12.195) Mvclo = Mv o . 1 + 𝛽Ao (12.196) The dc closed-loop output impedance is The dc closed-loop input-to-output gain is Example 12.15 For the buck converter given in Example 12.8 with VInom = 28 V and VO = 14 V, calculate Tclo , VO , VE , and Roclo if Tco = 1000, Tpo = 27.559 V, 𝛽 = 5∕14, VR = 5 V, and Ro = 0.157 Ω. Solution: The dc forward-path voltage transfer function is Ao = VO 1 × 27.559 = 2755.9. = Tco Tm Tpo = 1000 × VE 10 (12.197) The dc loop gain is 5 × 2755.9 = 984.25. 14 The dc closed-loop control-to-output voltage transfer function is Tclo = To = T(0) = 𝛽Ao = (12.198) VO Ao 2755.9 = 2.7972 = 8.93 dB. = = VR 1 + 𝛽Ao 1 + 984.25 (12.199) The dc output voltage is VO = Tclo VR = 2.7972 × 5 = 13.986 V (12.200) the dc error voltage is VE = VO 13.986 = 5.075 mV = Ao 2755.9 (12.201) the dc feedback voltage is VF = VR − VE = 5 − 0.005 = 4.995 V (12.202) VC = Tco VE = 1000 × 5.075 × 10−3 = 5.075 V. (12.203) and the dc control voltage is If the reference voltage has a step change from 5 to 6 V, then ΔVR = 1 V. The change in the dc output voltage is ΔVO = Tclo ΔVr = 2.7972 × 1 = 2.7972 V. (12.204) VO (∞) = VO (0− ) + ΔVO = 13.986 + 2.7972 = 16.7832 V. (12.205) Hence, the dc output voltage is The dc closed-loop input-to-output gain is Mvclo = Mvo 0.5463 = 0.5543 × 10−3 = −65 dB. = 1 + 𝛽Ao 1 + 984.25 (12.206) 518 Pulse-Width Modulated DC–DC Power Converters If the dc input voltage has a step change from 28 to 30 V, then ΔVI = 2 V. The change in the dc output voltage is ΔVO = Mclo ΔVI = 0.5543 × 10−3 × 2 = 1.1086 mV. (12.207) VO (∞) = VO (0− ) + ΔVO = 14 + 1.1086 × 10−3 = 14.001086 V. (12.208) Thus, the dc output voltage is The line regulation is LNR = ΔVO 1.1086 = 0.5543 mV∕V. = ΔVI 2 (12.209) The percentage line regulation is PLNR = ΔVO × 100 VOnom ΔVI = 0.5543×10−3 × 100 14 2 = 0.007918%∕V. (12.210) The dc closed-loop output resistance is Rocl (0) = Ro (0) 0.157 = 0.159 mΩ. = 1 + To 1 + 984.25 (12.211) If the load current has step change ΔIO = 0.2 A, then the change in the dc output voltage is ΔVO = −Rocl (0)ΔIO = −0.159 × 0.2 = −0.0318 mV. (12.212) VO (∞) = VO (0− ) + ΔVO = 14 − 1.1086 × 10−3 = 13.999682 V. (12.213) The dc output voltage is The load regulation is LOR = ΔVO 0.0318 × 10−3 = 0.159 mV∕A. = ΔIO 2 (12.214) The dc output-to-reference voltage transfer function is PVDC = Vo ∕VR = TPDC × Tm(dc) = 𝜂VI ∕VTm = 0.9 × 28∕10 = 2.52. 12.11 (12.215) Summary r The percentage change in the closed-loop transfer function A is (1 + 𝛽A) times lower than that of the f A-network. Therefore, if the loop gain T = 𝛽A ≫ 1, the closed-loop transfer function Af is almost independent of the A-network parameters. r The percentage change of the closed-loop transfer function A is almost equal in magnitude and is of the f opposite sign to the percentage change in the transfer function of the feedback network. r If the loop gain T = 𝛽A ≫ 1, the closed-loop transfer function A is almost entirely determined by the feedback f network transfer function 𝛽. r The feedback network should be made up of precision resistors to achieve an accurate output voltage V . O Voltage-Mode Control of PWM Buck Converter 519 r The closed-loop buck converter has three inputs (dc reference voltage V , input voltage v , and load current i ) R I O and one output (the output voltage vO ). r A series-shunt topology of negative feedback is used in the voltage-mode-controlled PWM buck converter. This topology of negative feedback stabilizes the voltage transfer function and reduces the output impedance of the closed-loop converter. r There is a loading effect of the forward A-network by the feedback network, which may change the transfer function of the controller. r The hybrid h-parameters can be used to describe the series-shunt feedback network. r Negative feedback reduces the magnitude of the audio susceptibility by a factor |1 + T|. r Negative feedback reduces the magnitude of the output impedance by a factor |1 + T|. r Negative feedback is effective at low frequencies, where |T| ≫ 1. r Negative feedback is not effective at high frequencies, where |T| ≪ 1. r The voltage-mode control circuit of the buck converter consists of a control circuit, PWM modulator, power stage of the buck converter, and feedback network. r The pulse-width modulator is made of an open-loop op-amp with a ramp voltage applied to the inverting input and the control voltage applied to the non-inverting input. r The op-amp used for the pulse-width modulator should have a high slew rate. r The integral controller is attractive because its gain at low frequencies is high. However, it introduces a phase lag of −90◦ at all frequencies, which may cause instability. r The lead controller is attractive because its phase lag is reduced in some frequency range. r The integral-single-lead controller provides the phase lag reduction theoretically between 0 and 90◦ and practically between 0 and 80◦ . r The magnitude of the audio susceptibility |M | is lower than the magnitude of the open-loop audio susceptibility vcl |Mv | by a factor of |1 + T|. r The closed-loop input resistance of the buck converter is negative at low frequencies. r The magnitude of the closed-loop output impedance |Z | is lower than the magnitude of the open-loop output ocl impedance |Zo | by a factor of |1 + T|. References [1] M. K. Kazimierczuk, N. Sathappan, and D. Czarkowski, “A voltage-mode-control PWM buck dc-dc converter with a proportional controller,” Proceedings of the IEEE National Aerospace and Electronic Conference (NAECON’93), Dayton, OH, May 24–28, 1993, vol. 2, pp. 639–644. [2] M. K. Kazimierczuk, R. C. Cravens, II, and A. Reatti, “Closed-loop input impedance of the PWM buck converter,” Proceedings of the IEEE International Symposium on Circuits and Systems, London, UK, May 30–June 3, 1994, pp. 61–64. [3] R. D. Midddlebrook, “The general feedback theorem: a final solution for feedback system,” IEEE Microwave Magazine, pp. 50–61, April 2006. [4] H. D. Venable, “The K factor: a new mathematical tool for stability analysis and synthesis,” Proceedings of the Powercon 10, 1983, H-1, pp. 1–12. Review Questions 12.1 Draw the circuit of the voltage-mode-controlled PWM buck converter. 12.2 Draw a block diagram of the closed-loop PWM buck converter for small-signal operation. 12.3 Draw a simplified block diagram of the closed-loop PWM buck converter for small-signal operation. 12.4 Derive an expression for the loop gain for the buck converter. 520 Pulse-Width Modulated DC–DC Power Converters 12.5 Derive an expression for the closed-loop small-signal control-to-input transfer function Tcl for the buck converter with an integral-single-lead controller. 12.6 What is the order of the closed-loop control-to-output transfer function Tcl ? 12.7 What is the location of the poles and the zero of the closed-loop control-to-output transfer function Tcl in the s-plane? 12.8 Draw a small-signal model of the PWM buck converter for deriving the closed-loop input-to-output transfer function Mvcl . 12.9 Derive a closed-loop small-signal input-to-input transfer function Mvcl for the buck converter. 12.10 What is the physical meaning of the input-to-output transfer function Mvcl ? 12.11 Draw a small-signal model of the PWM buck converter for deriving the closed-loop input impedance Zicl . 12.12 Derive an expression for the closed-loop input impedance Zicl for the buck converter. 12.13 Draw a small-signal model of the PWM buck converter for deriving the closed-loop output impedance Zocl . 12.14 Derive an expression for the closed-loop output impedance Zocl for the buck converter. 12.15 Explain the behavior of the closed-loop susceptibility Mvcl versus frequency. 12.16 Explain the behavior of the closed-loop output impedance Zocl versus frequency. Problems 12.1 Determine the transfer function of the pulse-width modulator if VTm = 5 V. 12.2 Determine the reference voltage if Dnom = 0.5 and VTm = 5 V. 12.3 A buck converter has VO = 12 V and VR = 5 V. Design a feedback network. 12.4 A buck converter has Tpo = 25 V, Tm = 0.4 1/V, 𝛽 = 0.2, 𝜉 = 0.3549, fz = 31.8 kHz, and f0 = 2.6 kHz. Design a control circuit such that PM ≥ 60◦ . 12.5 At f = 120 Hz, |Mv | = 0.5, |T| = 34 dB, and the ripple input voltage is Vr(in) = 1 V. Find the output ripple voltage. 13 Voltage-Mode Control of Boost Converter 13.1 Introduction The objective of this chapter is to present a small-signal analysis of a closed-loop voltage-mode-controlled PWM boost dc–dc converter with an integral-lead controller, also called an integral-double-lead (IDL) controller [1–13]. The circuit of the controller is analyzed. Its design procedure is developed. Loop gain, closed-loop transfer functions, and closed-loop input and output impedances are found. In addition, step responses of the closed-loop circuit are computed for changes in the input voltage and the reference voltage. A design example is given. 13.2 Circuit of Boost Converter with Voltage-Mode Control A boost converter with a single-loop control circuit is shown in Figure 13.1. This circuit has a series-shunt negative feedback topology. The duty cycle is directly controlled by the voltage derived from the reference voltage VR and the feedback voltage vF . This method of control is called voltage-mode control. The feedback network can be represented by h-parameters as shown in Figure 13.2. The resistances h11 = RA RB ∕(RA + RB ) and 1∕h22 = RA + RB can be moved from the feedback network to the A-circuit [13] as shown in Figure 13.3. Since usually 1∕h22 ≫ RL , it can be neglected. Figure 13.4(a) shows a small-signal model of the boost converter and various stages related to the control of the output voltage. A block diagram of a closed-loop boost converter with voltage-mode-control is shown in Figure 13.4(b). In this figure, Tp is the small-signal control-to-output transfer function of the power stage of the boost converter, Mv is the input-to-output voltage transfer function, Zo is the open-loop output impedance, Tm is the transfer function of the pulse-width modulator, Tc is the voltage transfer function of the controller, 𝛽 is the transfer function of the feedback network, vf is the ac component of the feedback voltage, vc is the ac component of the output voltage of the controller, ve is the ac component of the error voltage, and vr is the ac component of the reference voltage. The control block diagram is a three-input and a single-output system driven by three independent sources, vr , vi , and io . The ac component of the input voltage vi can be viewed as a disturbance caused by a low-frequency ripple voltage and/or variations of the line voltage. For a constant dc output voltage, vr = 0. The voltage gain of the forward path for the ac components is v A ≡ o = Tc Tm Tp (13.1) ve Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 522 Pulse-Width Modulated DC–DC Power Converters L vi + vI V + VR vF + C VI RL io + vO V + + vE ~ vC dT + + vGS Zi ′ vt Zf β RA + vF Figure 13.1 + vO RB Boost PWM converter with voltage-mode control. and the loop gain is T≡ vf = 𝛽A = 𝛽Tc Tm Tp . (13.2) Mv Zo A 1 A v + v = v + v − i = Tcl vr + Mvcl vi − Zocl io 1 + T(s) r 1 + T d 1 + T r 1 + T i 1 + T o (13.3) ve The ac component of the output voltage is given by vo = L vi + V + VR vF + ~ C VI RL io + vO V + + vE vI vC dT + + vGS Zi ′ Zf vt RA RB h11 Figure 13.2 + vF = β vO + + vO RA RB 1 h22 Closed-loop boost PWM converter with a feedback network 𝛽 represented by h-parameters. Voltage-Mode Control of Boost Converter 523 L + vI V vF + VI vC + 1 h22 RL io + vO dT + vGS Zi ′ h11 Zi vt Zf + vF = β vO Figure 13.3 C V + + vE + VR ~ vi + vO + Closed-loop boost PWM converter with resistances h11 and 1∕h22 moved to the A-network. where vd = v′′o − v′′′ o is the total disturbance voltage. Using this equation, the block diagram of Figure 13.4(b) can be simplified to the form shown in Figure 13.4(c). 13.3 Transfer Function of Modulator, Boost Converter Power Stage, and Feedback Network The transfer function of the pulse-width modulator and the boost converter power stage is Tp (s) vo (s) |vi =io =0 = Tm Tp (s) = vc (s) VTm ( } ){ s + Cr1 s − L1 [(1 − D)2 RL − r] VO rC C =− VTm (1 − D)(RL + rC ) s2 + s C[r(RL +rC )+(1−D)2 RL rC ]+L + r+(1−D)2 RL LC(R +r ) LC(R +r ) Tmp (s) ≡ L C L C (s + 𝜔zn )(s − 𝜔zp ) VO rC VTm (1 − D)(RL + rC ) s2 + 2𝜉𝜔0 s + 𝜔20 ( )( ) ( )( ) s s s s 1 + 1 − 1 + 1 − VO rC 𝜔zn 𝜔zp 𝜔zn 𝜔zp 𝜔zn 𝜔zp = ( )2 = Tmpo ( )2 2 VTm (1 − D)(RL + rC )𝜔0 1 + 2𝜉s + 𝜔s 1 + 2𝜉s + 𝜔s 𝜔 𝜔 =− 0 0 0 (13.4) 0 where Tmpo = Tmp (0) = Tm Tpo = VO rC 𝜔zn 𝜔zp VO (1 − D)2 RL − r . = VTm (1 − D) (1 − D)2 RL + r VTm (1 − D)(RL + rC )𝜔20 (13.5) 524 Pulse-Width Modulated DC–DC Power Converters Z1 ii L Z2 r iI vi ~ + + Dvo VO d Dil C ILd RL rC Zicl + ~ ve vc Tc io ′ Zocl + vo′′ + vo Zocl + + vr + vo d Tm vf β + vo RA RB + vf (a) Zo io + vr ~ ve + Tc vo′′′ MV ~ vi vc d Tm Tp vf vo′ + A β (b) Zo io vo′′′ vi ~ vr ~ + MV vo′′ A + + vo′ 1 1+T vo (c) Figure 13.4 Closed-loop small-signal low-frequency model of the boost converter. (a) Small-signal model. (b) Block diagram. (c) Simplified block diagram. Voltage-Mode Control of Boost Converter 525 30 20 0 |T mp | (dB) 10 −10 −20 −30 −40 1 10 2 3 10 10 f (Hz) 4 10 5 10 Figure 13.5 Bode plot of the magnitude of the modulator and the control-to-output transfer function Tmp = Tm Tp for the boost converter. Example 13.1 A boost converter has VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and VTm = 5 V. Calculate Tmpo and draw Bode plots of Tmp for D = 0.5. Solution: The transfer function of the pulse-width modulator is Tm = dB 1 1 1 = −14 . = VTm 5 V V (13.6) The frequency of the LHP zero is fzn = 21.09 kHz. At RLmin , Tpo = 37.55 V, 𝜉 = 0.261, f0 = 784 Hz, and fzp = 9.88 kHz. The transfer function of the pulse-width modulator and the boost converter at f = 0 is Tmpo = Tm Tpo = 0.2 × 37.55 = 7.51 = 17.52 dB. (13.7) Figures 13.5 and 13.6 show Bode plots of Tmp = Tm Tp . Since VC ≈ VR and D = VC ∕VTm ≈ VR ∕VTm , the reference voltage can be found as VR ≈ VC = Dnom VTm . (13.8) The voltage transfer function of the feedback network is 𝛽= vf V RB vF = F = = . vO VO vo RA + RB (13.9) 526 Pulse-Width Modulated DC–DC Power Converters 0 −30 −90 ϕ T mp (°) −60 −120 −150 −180 −210 1 10 2 3 10 4 10 f (Hz) 5 10 10 Figure 13.6 Bode plot of the phase of the modulator and the control-to-output transfer function Tmp = Tm Tp for the boost converter. The transfer function of the pulse-width modulator, the boost converter, and the feedback network (i.e., the transfer function of the uncompensated loop) is (s + 𝜔zn )(s − 𝜔zp ) 𝛽VO rC vc (s) VTm (1 − D)(RL + rC ) s2 + 2𝜉𝜔0 s + 𝜔20 ( )( ) ( )( ) 1 + 𝜔s 1 − 𝜔s 1 + 𝜔s 1 − 𝜔s 𝛽VO rC 𝜔zn 𝜔zp zn zp zn zp = ( )2 = Tko ( )2 VTm (1 − D)(RL + rC )𝜔20 1 + 2𝜉s + 𝜔s 1 + 2𝜉s + 𝜔s 𝜔 𝜔 Tk (s) ≡ vf (s) = 𝛽Tm Tp (s) = 𝛽Tmp (s) = − 0 0 0 (13.10) 0 where Tko = 𝛽Tmpo = 𝛽Tm Tpo = 𝛽VO rC 𝜔zn 𝜔zp 𝛽VO (1 − D)2 RL − r . = VTm (1 − D) (1 − D)2 RL + r VTm (1 − D)(RL + rC )𝜔20 (13.11) Substituting s = j𝜔, we get the transfer function of the uncompensated loop ( )( ) 1 + 𝜔𝜔 1 − 𝜔𝜔 zn zp Tk (j𝜔) = 𝛽Tmp (j𝜔) = Tko = |Tk |ej𝜙Tk ( )2 𝜔 2𝜉𝜔 1− 𝜔 +j 𝜔 0 0 (13.12) Voltage-Mode Control of Boost Converter where √ ( 1+ |Tk | = |𝛽Tmp | = Tko √ [ 1− and ( 𝜙Tk = tan−1 𝜔 𝜔zn ) ( ) − tan−1 𝜔 𝜔zp ) ( 𝜙Tk = −180◦ + tan−1 𝜔 𝜔zn − tan−1 ( )2 √ 𝜔 𝜔0 ( 1+ )2 ]2 ( + )2 𝜔 𝜔zp 2𝜉𝜔 𝜔0 𝜔 𝜔zp ) (13.13) )2 ( ) ⎡ ⎤ 2𝜉𝜔 ⎥ 𝜔0 −1 ⎢ − tan ⎢ ( )2 ⎥ ⎢1 − 𝜔 ⎥ ⎣ ⎦ 𝜔0 or ( 𝜔 𝜔zn 527 for ( ) ⎡ ⎤ 2𝜉𝜔 ⎥ 𝜔0 −1 ⎢ − tan ⎢ ( )2 ⎥ 𝜔 ⎢1 − ⎥ ⎣ ⎦ 𝜔0 𝜔 ≤1 𝜔0 for 𝜔 > 1. 𝜔0 (13.14) (13.15) Example 13.2 A boost converter has VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, Tmpo = 7.51, and 𝛽 = 0.125. Calculate Tko . Draw Bode plots of Tk for D = 0.5. Solution: The dc reference voltage is VR ≈ VC = Dnom VTm = 0.5 × 5 = 2.5 V. (13.16) The voltage transfer function of the feedback network is 𝛽= V VF 2.5 = 0.125 = −18 dB. ≈ R = VO VO 20 (13.17) Thus, Tko = 𝛽Tmpo = 0.125 × 7.51 = 0.9388 = −0.549 dB. (13.18) Figures 13.7 and 13.8 show Bode plots of Tk . The phases of Tmp and Tk are the same as the phase of Tp . Figure 12.20 shows a circuit of an integral controller and its KP = 10 and fz = 10 Hz. 13.4 Integral-Double-Lead Controller An IDL compensator, also called a third-order integral-lead controller or the type III controller [4], is shown in Figure 13.9(a). The circuit is loaded by the feedback network in the form of h11 = RA ||RB [13]. The controller has a pole at the origin and two zero–pole pairs. Since the magnitude of the transfer function of the controller has three slopes, the circuit is called the type III controller. An equivalent circuit of the controller for the ac component is depicted in Figure 13.9(b). The Miller integral part of this controller is used to achieve a large low-frequency gain and, therefore, to reduce both the dc error and the closed-loop output impedance at low frequencies. However, an integral controller introduces a phase lag of –90◦ at all frequencies. The phase lag can be reduced by means of a lead controller in a limited frequency range. This allows a wider closed-loop bandwidth and, therefore, a faster step response. The phase boost 𝜙m of this controller is theoretically 180◦ and in practice less than 160◦ . The task 528 Pulse-Width Modulated DC–DC Power Converters 10 0 | T | (dB) k −10 −20 −30 −40 −50 −60 1 10 2 3 10 10 f (Hz) 4 5 10 10 Figure 13.7 Bode plot of the magnitude of the modulator, the control-to-output transfer function, and the feedback network Tk = 𝛽Tmp = 𝛽Tm Tp for the boost converter. 0 −30 −90 ϕ Tk (°) −60 −120 −150 −180 −210 1 10 2 10 3 10 f (Hz) 4 10 5 10 Figure 13.8 Bode plot of the magnitude of the modulator, the control-to-output transfer function, and the feedback network Tk = 𝛽Tmp = 𝛽Tm Tp for the boost converter. Voltage-Mode Control of Boost Converter 529 C2 R3 C1 C3 R2 h11 + vF R1 + vC + VR (a) C2 R3 C1 C3 R2 h11 + vf R1 + vc + (b) Figure 13.9 Third-order integral-double-lead controller with two zero–pole pairs (type III controller). (a) Circuit. (b) Equivalent circuit for the ac component. for the lead controller is to achieve a high crossover frequency fc of the control-to-output gain, while maintaining a specified phase margin PM. The impedances of the controller are ( ) 1 1 R + s + R 1C 2 sC2 sC1 2 1 Zf = = (13.19) ( ) 1 1 C1 +C2 R2 + sC + sC sC s + 2 1 2 R C C 2 Zi = h11 + ( ) R1 R3 + sC1 3 R1 + R3 + sC1 1 2 R1 +h11 ) s+ ( R1 R3 C3 [R3 (R1 +h11 )+h11 R1 ] = h11 + 1 R1 + R3 s+ (13.20) C3 (R1 +R3 ) 3 where h11 = RA RB . RA + RB (13.21) Assume that the open-loop dc gain and the bandwidth of the operational amplifier are infinite. Hence, from (13.19) and (13.20), the voltage transfer function of the controller for the ac component is Av (s) ≡ Zf vc (s) =− vf (s) Zi ( )[ ] 1 1 s + s + R1 + R3 R 2 C1 C3 (R1 +R3 ) =− ( ){ }. R1 +h11 C2 [R1 R3 + h11 (R1 + R3 )] s s + C1 +C2 s + R C C C [R R +h (R +R )] 2 1 2 3 1 3 11 1 3 (13.22) 530 Pulse-Width Modulated DC–DC Power Converters At vr = 0, ve = −vf and therefore the voltage transfer function of the IDL controller is Tc (s) ≡ B(s + 𝜔zc1 )(s + 𝜔zc2 ) vc (s) v (s) =− c = −Av (s) = ve (s) vf (s) s(s + 𝜔pc1 )(s + 𝜔pc2 ) (13.23) R1 + R3 C2 [R1 R3 + h11 (R1 + R3 )] (13.24) 1 R2 C1 (13.25) 1 C3 (R1 + R3 ) (13.26) where B= 𝜔zc1 = 𝜔zc2 = ( ) 𝜔pc1 = C1 + C2 = 𝜔zc1 R2 C1 C2 𝜔pc2 = R1 + h11 . C3 [R1 R3 + h11 (R1 + R3 )] C1 +1 C2 (13.27) and (13.28) The voltage transfer function of the controller is Av (s) ≡ vc (s)∕ve (s) = −Tc (s). Assuming that 𝜔zc1 = 𝜔zc2 = 𝜔zc and 𝜔pc1 = 𝜔pc2 = 𝜔pc and using (13.25) and (13.26), K= 𝜔pc1 𝜔zc1 = 𝜔pc2 𝜔zc2 = 𝜔pc 𝜔zc = (R1 + h11 )(R1 + R3 ) C1 . +1= C2 R1 R3 + h11 (R1 + R3 ) (13.29) Hence, (13.23) becomes ( ( )2 )2 s 2 1+ s B𝜔 B 1 + zc v (s) B(s + 𝜔zc 𝜔zc 𝜔zc Tc (s) ≡ c = = ( ( )2 = )2 . ve (s) s(s + 𝜔pc )2 s s 2 2 𝜔pc s 1 + 𝜔 K s 1+ 𝜔 (13.30) [ ( )]2 )2 ( 2 B 1 + 𝜔 𝜔𝜔 + j 𝜔𝜔 − 𝜔𝜔 B 1 + j 𝜔𝜔 zc pc zc pc zc = |Tc (𝜔)|ej𝜙Tc (𝜔) Tc (j𝜔) = )2 = ( [ ( )2 ]2 𝜔 K 2 j𝜔 1 + j 𝜔 K 2 j𝜔 1 + 𝜔 (13.31) )2 pc pc For s = j𝜔, 𝜔pc pc where the magnitude of Tc is |Tc (𝜔)| = [ ( )2 ] B 1 + 𝜔𝜔 zc [ K2𝜔 ( 1+ 𝜔 𝜔pc ( ) )2 ] (13.32) and the phase shift of Tc is 𝜋 𝜙Tc (𝜔) = − + 2 arctan 2 ( 𝜔 𝜔zc ) − 2 arctan 𝜔 𝜔pc 𝜔 𝜔 ⎛𝜔 −𝜔 ⎞ zc pc 𝜋 ⎟. = − + 2 arctan ⎜ ⎜ 1 + 𝜔2 ⎟ 2 ⎝ 𝜔zc 𝜔pc ⎠ (13.33) Voltage-Mode Control of Boost Converter 531 The maximum value of phase 𝜙Tc occurs at the geometric mean value of the zero frequency and the pole frequency and from (13.25), (13.28), and (13.29) is given by √ √ 𝜔pc R1 + h11 K √ 𝜔m = 𝜔c = 𝜔zc 𝜔pc = K𝜔zc = = √ = √ . (13.34) R2 C1 K C K[R R + h (R + R )] 3 1 3 11 1 3 √ Substitution of (13.34) into (13.33) and using the relationship arctan x = arcsin x∕ x2 + 1 yields the phase shift at f = fm ( ) ( ) 𝜋 𝜋 K−1 K−1 . (13.35) 𝜙Tc (fm ) = − + 2 arctan = − + 2 arcsin √ 2 2 K+1 2 K Thus, the maximum amount of the phase shift reduction is ( ) ) ( 𝜋 K−1 K−1 𝜙m = 𝜙Tc (fm ) + = 2 arctan = 2 arcsin √ 2 K+1 2 K from which ( 1 + sin ( K= 1 − sin 𝜙m 2 𝜙m 2 ) ( ) = tan2 Hence, 𝜙m = −𝜋 + 4 arctan 𝜙m 𝜋 + 4 4 √ (13.36) ) . K. (13.37) (13.38) Figure 13.10 shows 𝜙m versus K. Note that 𝜙m increases from 0 to about 160◦ as K is increased from nearly 0 to 100. Substituting (13.34) into (13.32) and using (13.24) and (13.29), one obtains the magnitude of the controller voltage transfer function at the frequency f = fm |Tc (fm )| = R1 + R3 1 B = = . 𝜔m K 𝜔m KC2 [R1 R3 + h11 (R1 + R3 )] 𝜔m C2 (R1 + h11 ) (13.39) The magnitude of the loop gain at the crossover frequency fc = fm is |T(fc )| = |Tc (fc )||Tk (fc )| = |Tc (fc )||Tmp (fc )|𝛽 = 1. (13.40) Assuming that fc = fm and using (13.39) and (13.40), one arrives at |Tc (fc )| = 1 1 1 = = . |Tk (fc )| 𝛽|Tmp (fc )| 𝜔c C2 (R1 + h11 ) (13.41) The phase shift of the loop gain at the crossover frequency fc is 𝜙T (fc ) = 𝜙Tk (fc ) + 𝜙Tc (fc ). (13.42) 𝜙m = 90◦ + 𝜙Tc (fc ) (13.43) 𝜙Tc (fc ) = 𝜙m − 90◦ . (13.44) The phase boost is yielding 532 Pulse-Width Modulated DC–DC Power Converters 180 150 m ϕ (°) 120 90 60 30 0 0 10 20 30 40 50 K 60 70 80 90 100 Figure 13.10 Maximum phase boost 𝜙m versus K for the integral-double-lead controller with two zero–pole pairs (type III controller). Using (13.35), the phase margin is obtained as PM = 180◦ + 𝜙T (fc ) = 180◦ + 𝜙Tk (fc ) + 𝜙Tc (fc ) = 180◦ + 𝜙Tk (fc ) + 𝜙m − 90◦ = 90◦ + 𝜙Tk (fc ) + 𝜙m = 90◦ + 𝜙Tk (fc ) + 𝜙m . (13.45) Hence, the required phase boost is 𝜙m = PM − 90◦ − 𝜙Tk (fc ). (13.46) 13.5 Design of Integral-Double-Lead Controller A boost PWM converter has VInom = 12 V, VO = 20 V, VR = 2.5 V, RLmin = 40 Ω, RLmax = 200 Ω, Dnom = 0.5, 𝜉 = 0.261, f0 = 784 Hz, fzp = 9.88 kHz, fzn = 21.09 kHz, VTm = 5 V, and Tko = 0.9388. Design a control circuit such that GM ≥ 10 dB and PM = 60◦ . The voltage transfer function of the feedback network is 𝛽= VF V RB 2.5 = 0.125 = −18.06 dB. ≈ R = = VO VO RA + RB 20 Assuming RB = 620 Ω/0.25 W/1%, one obtains ) ( ( ) 1 1 − 1 = 0.62 − 1 = 4.34 kΩ. R A = RB 𝛽 0.125 (13.47) (13.48) Pick RA = 4.3 Ω/0.25 W/1%. Hence, h11 = RA RB 0.62 × 4.3 = 542 Ω. = RA + RB 0.62 + 4.3 (13.49) Voltage-Mode Control of Boost Converter 533 Note that 1∕h22 = RA + RB = 0.62 + 4.3 = 4.92 kΩ ≫ RLmax = 200 Ω and therefore (1∕h22 )||RLmax = 192 Ω. Assume that fc = fm = 2 kHz. From (13.15), ( ) 2𝜉fc ⎡ ⎤ ( ) ( ) fc fc ⎥ f0 ◦ −1 −1 −1 ⎢ − tan − tan ⎢ 𝜙Tk (fc ) = −180 + tan ( )2 ⎥ fzn fzp ⎢ 1 − fc ⎥ ⎣ ⎦ f0 ) ( ⎡ 2×0.261×2 ⎤ ) ) ( ( ⎢ ⎥ 0.784 2 2 − tan−1 − tan−1 ⎢ = −180◦ + tan−1 ( )2 ⎥ 21.09 9.88 2 ⎢1 − ⎥ ⎣ ⎦ 0.784 = −180◦ + 5.42◦ − 11.44◦ + 13.59◦ = −172.43◦ . (13.50) Since the specified phase margin is PM = 60◦ , one obtains the required phase boost 𝜙m = PM − 𝜙Tk (fc ) − 90◦ = 60◦ + 172.43◦ − 90◦ = 142.43◦ and the K factor ( K = tan2 𝜙m + 45◦ 4 ) = tan2 ( ) 142.43◦ + 45◦ = 36.547. 4 (13.51) (13.52) The frequencies of the poles and the zeros of the controller are f 2000 fzc = √c = √ = 330.851 Hz K 36.547 and √ √ fpc = fc K = 2000 36.547 = 12.09 kHz. From (13.13), √ ( 1+ |Tk (fc )| = 𝛽|Tmp (fc )| = Tko √ )2 √ 𝜔c 𝜔zn ( 1+ 𝜔c 𝜔zp ( 1+ (13.54) )2 [ ( )2 ]2 ( )2 𝜔 2𝜉𝜔 1 − 𝜔c + 𝜔c 0 √ (13.53) 2 21.09 ) √ 0 ( 2 1+ 2 9.88 )2 = 0.9388 √ = 0.1696 = −15.4 dB. [ ( )2 ]2 ( )2 2 1 − 0.784 + 2×0.261×2 0.784 (13.55) Next, |Tc (fc )| = 1 1 1 = = = 5.8955 = 15.4 dB |Tk (fc )| 𝛽|Tmp (fc )| 0.1696 (13.56) and B = 𝜔c K|Tc (fc )| = 2𝜋 × 2000 × 36.547 × 5.895 = 2.7076 × 106 ( rad∕s). (13.57) Bode plots of Tc of the controller are shown in Figures 13.11 and 13.12. From these plots, GM = 11 dB and PM = 60◦ . If GM is too low, fc should be reduced and the entire procedure should be repeated. 534 Pulse-Width Modulated DC–DC Power Converters 30 20 c | T | (dB) 25 15 10 5 1 10 2 3 10 10 f (Hz) 4 5 10 10 Figure 13.11 Bode plot of the magnitude of the voltage transfer function Tc for the designed integral-double-lead controller with two zero–pole pairs (type III converter). 60 30 ϕ Tc (°) 0 −30 −60 −90 1 10 2 10 3 10 f (Hz) 4 10 5 10 Figure 13.12 Bode plot of the phase of the voltage transfer function Tc for the designed integral-double-lead controller with two zero–pole pairs (Type III). Voltage-Mode Control of Boost Converter 535 Assuming R1 = 100 kΩ/0.25 W/1% and using (13.29), one obtains R1 [R1 − h11 (K − 1)] 100[100 − 0.542(36.547 − 1)] = = 2.259 kΩ. (K − 1)(R1 + h11 ) (36.547 − 1)(100 + 0.542) R3 = (13.58) Pick R3 = 2.2 kΩ∕0.25 W/1%. Hence, from (13.41), C2 = |Tk (fc )| 0.1696 = = 134 pF. 𝜔c (R1 + h11 ) 2 × 𝜋 × 2 × 103 × (100 + 0.542) × 103 (13.59) Pick C2 = 150 pF/12 V. From (13.29), C1 = C2 (K − 1) = 0.15 × (36.547 − 1) = 5.33 nF. (13.60) Pick C1 = 4.7 nF/12 V. Using (13.34), √ √ K 36.547 = = 102.36 kΩ. R2 = 𝜔c C1 2 × 𝜋 × 2 × 103 × 4.7 × 10−9 (13.61) Pick R2 = 100 kΩ/0.25 W/1%. From (13.34), C3 = = √ R1 + h11 𝜔c K[R1 R3 + h11 (R1 + R3 )] √ (100 + 0.542) × 103 = 4.8 nF. (13.62) = 2.474 × 106 (rad∕s). (13.63) 2 × 𝜋 × 2 × 103 36.547[100 × 2.2 + 0.542 × (100 + 2.2)] × 106 Pick C3 = 4.7 nF/12 V. From (13.24), B= = R1 + R3 C2 [R1 R3 + h11 (R1 + R3 )] (100 + 2.2) × 103 0.15 × 10−9 × [100 × 2.2 + 0.542 × (100 + 2.2)] × 106 The frequencies of the poles and the zeros of the controller with standard resistors and capacitors are 1 1 = = 318.31 Hz 2𝜋R2 C1 2 × 𝜋 × 100 × 103 × 5 × 10−9 (13.64) 1 1 = 311.46 Hz = 2𝜋C3 (R1 + R3 ) 2 × 𝜋 × 5 × 10−9 (100 + 2.2) × 103 (13.65) fzc1 = fzc2 = ( fpc1 = fzc1 C1 +1 C2 ) ( = 318.31 5 +1 0.15 ) = 10.929 kHz (13.66) and fpc2 = = R1 + h11 2𝜋C3 [R1 R3 + h11 (R1 + R3 )] (100 + 0.542)103 = 12.36 kHz. 2 × 𝜋 × 4.7 × 10−9 [100 × 2.2 + 0.542(100 + 2.2)] × 106 (13.67) 536 Pulse-Width Modulated DC–DC Power Converters 13.6 Loop Gain The loop gain of the converter is T(s) ≡ vf (s) | = Tc (s)Tmp (s)𝛽 = Tc (s)Tm Tp (s)𝛽 ve (s) vi =io =0 = Tx (s + 𝜔zc )2 (s + 𝜔zn )(s − 𝜔zp ) ( ) s(s + 𝜔pc )2 s2 + 2𝜉𝜔0 s + 𝜔20 (13.68) 𝛽BVO rC . VTm (1 − D)(RL + rC ) (13.69) where Tx = − Example 13.3 A boost converter has VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, 𝛽 = 0.125, Tm = 0.2 1/V, fzn = 21.09 kHz, fzp = 9.88 kHz, f0 = 784 Hz, 𝜉 = 0.261, B = 2.7079 × 106 rad/s, fzc = 330.829 Hz, and fpc = 12.09 kHz. Draw Bode plots for the loop gain T of the boost converter for D = 0.5. Solution: Figures 13.13 and 13.14 show Bode plots of the loop gain T for D = 0.5. The crossover frequency is fc = 2 kHz at Dnom = 0.5. The phase margin is PM = 60◦ . The phase crosses −180◦ at f−180◦ = 8.5 kHz and the gain margin is GM = 14 dB. 30 20 | T | (dB) 10 0 −10 −20 −30 −40 1 10 Figure 13.13 2 10 3 10 f (Hz) 4 10 5 10 Bode plot of the magnitude of the loop gain T for the boost converter. Voltage-Mode Control of Boost Converter 537 0 −30 −60 −120 T ϕ (°) −90 −150 −180 −210 −240 −270 1 10 2 10 Figure 13.14 3 10 f (Hz) 4 10 5 10 Bode plot of the phase of the loop gain T for the boost converter. 13.7 Closed-Loop Control-to-Output Voltage Transfer Function The closed-loop control-to-output transfer function is found as Tcl (s) ≡ = Tc (s)Tm Tp (s) vo (s) A(s) 1 T(s) |vi =io =0 = = = vr (s) 𝛽 1 + T(s) 1 + 𝛽A(s) 1 + 𝛽Tc (s)Tm Tp (s) (s + 𝜔zc )2 (s + 𝜔zn )(s − 𝜔zp ) Tx . ( ) 𝛽 s(s + 𝜔pc )2 s2 + 2𝜉𝜔0 s + 𝜔2 + Tx (s + 𝜔zc )2 (s + 𝜔zn )(s − 𝜔zp ) (13.70) 0 It is a fifth order function. Example 13.4 A boost converter has 𝛽 = 0.125, Tm = 0.2 (1/V), VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, and C3 = 5 nF. Calculate Tclo = Tcl (0). Draw Bode plots for the closed-loop control-tooutput transfer function Tcl of the boost converter for D = 0.5. Solution: The closed-loop control-to-output transfer function at f = 0 is Tclo = Tcl (0) ≈ 1 1 = = 8 = 18 dB. 𝛽 0.125 (13.71) Figures 13.15 and 13.16 show Bode plots of Tcl . The bandwidth of the closed-loop control-to-output transfer function is BWf = 2 kHz at D = 0.5. 538 Pulse-Width Modulated DC–DC Power Converters 20 15 10 | T cl | (dB) 5 0 −5 −10 −15 −20 −25 1 10 Figure 13.15 converter. 2 3 10 10 f (Hz) 4 5 10 10 Bode plot of the magnitude of the closed-loop control-to-output transfer function Tcl for the boost 0 −30 −60 −120 ϕ T cl (°) −90 −150 −180 −210 −240 −270 1 10 Figure 13.16 2 10 3 10 f (Hz) 4 10 5 10 Bode plot of the phase of the closed-loop control-to-output transfer function Tcl for the boost converter. Voltage-Mode Control of Boost Converter 539 0 −10 | Mvcl | (dB) −20 −30 −40 −50 −60 −70 1 10 Figure 13.17 converter. 2 10 3 4 10 f (Hz) 10 5 10 Bode plot of the magnitude of the closed-loop input-to-output transfer function Mvcl for the boost 13.8 Closed-Loop Audio Susceptibility The closed-loop input-to-output voltage transfer function, called the audio susceptibility, is given by Mvcl (s) ≡ = Mv (s) vo (s) |vr =io =0 = vi (s) 1 + T(s) s(s + 𝜔pc )2 (s + 𝜔zn ) (1 − D)RL rC × . ( ) L(RL + rC ) s(s + 𝜔pc )2 s2 + 2𝜉𝜔0 s + 𝜔2 + Tx (s + 𝜔zc )2 (s + 𝜔zn )(s − 𝜔zp ) (13.72) 0 Example 13.5 A boost converter has 𝛽 = 0.125, VTm = 5 V, VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, and C3 = 5 nF. Draw Bode plots for the closed-loop input-to-output transfer function Mvcl of the boost converter for D = 0.5. Solution: Figures 13.17 and 13.18 show Bode plots of Mvcl . 13.9 Closed-Loop Input Impedance Referring to the block diagram shown in Figure 13.4(a) and setting vr = 0, d = −𝛽Tc Tm vo . (13.73) Using tKCL and assuming that RA + RB ≫ RL , one obtains il = Dil + IL d + vo Z2 (13.74) 540 Pulse-Width Modulated DC–DC Power Converters 90 60 30 ϕ Mvcl (°) 0 −30 −60 −90 −120 −150 −180 1 10 Figure 13.18 2 3 10 10 f (Hz) 4 10 5 10 Bode plot of the phase of the closed-loop input-to-output transfer function Mvcl for the boost converter. which gives il = vo I d + L . Z2 (1 − D) 1 − D (13.75) ] IL 𝛽Tc Tm 1 − . Z2 (1 − D) 1−D (13.76) IO . 1−D (13.77) ] IO 𝛽Tc Tm 1 − . Z2 (1 − D) (1 − D)2 (13.78) Substitution of (13.73) into (13.74) yields [ il = vo A dc analysis of the boost converter leads to IL = Substituting (13.77) into (13.75) gives [ il = vo Dividing both sides by vi gives the closed-loop input admittance ] [ I 𝛽T T v i 1 − O c m2 o Yicl (s) ≡ l |vr (r)=0 = vi Z2 (1 − D) (1 − D) vi (13.79) which, after substitution of (13.72), simplifies to Yicl (s) = I 𝛽T T Mv Mv 1 − O c m . Z2 (1 − D) 1 + T (1 − D)2 1 + T (13.80) Voltage-Mode Control of Boost Converter 541 Dividing Mv by Tp gives RL (1 − D)2 T . VO L(s − 𝜔zp ) p (13.81) Mv 𝛽A(s) 1 1 + . L(s − 𝜔zp ) 1 + T Z2 (1 − D) 1 + T (13.82) Mv = − Substitution of (13.81) into (13.80) produces Yicl (s) = The impedance Z2 is given by Z2 = ( ) 1 RL rC + sC 1 RL + rC + sC s + r 1C RL rC C = 1 RL + rC s + C(RL +rC ) = RL rC s + 𝜔zn RL + rC s + 𝜔rc (13.83) where 1 rC C (13.84) 1 . C(RL + rC ) (13.85) 𝜔zn = and 𝜔rc = Hence, one arrives at the closed-loop input admittance Yicl (s) = Mvcl (R + rC )(s + 𝜔rc )Mvcl 𝛽Tcl 𝛽Tcl + = + L L(s − 𝜔zp ) Z2 (1 − D) L(s − 𝜔zp ) RL rC (1 − D)(s + 𝜔zn ) (13.86) and the closed-loop input impedance ( ) L[s(s + 𝜔pc )2 s2 + 2𝜉𝜔0 s + 𝜔20 + Tx (s + 𝜔zc )2 (s + 𝜔zn )(s − 𝜔zp )] 1 = Zicl (s) = . Yicl (s) s(s + 𝜔pc )2 (s + 𝜔rc ) + Tx (s + 𝜔zc )2 (s + 𝜔zn ) (13.87) At low frequencies, |T| ≫ 1 and therefore |T|∕|1 + T| ≈ 1, |Mvcl | ≪ 1, and the low-frequency closed-loop input impedance can be approximated by Zicl (s) ≈ L(s − 𝜔zp ) (13.88) [ ] Ricl (0) = Zicl (0) = −𝜔zp L = − (1 − D)2 RL − r . (13.89) and the dc closed-loop input resistance The dc closed-loop input resistance can be expressed in terms of the dc voltage transfer function MV DC = 1∕(1 − D) as Ricl (0) ≈ −(1 − D)2 RL = − RL R = − 2L . 2 1∕(1 − D) MV DC (13.90) The closed-loop output impedance can also be represented as the closed-loop input resistance and the closed-loop reactance Zicl = |Zicl | cos 𝜙Zicl + j|Zicl | sin 𝜙Zicl = Ricl + jXicl , where Ricl = |Zicl | cos 𝜙Zicl and Xicl = |Zicl | sin 𝜙Zicl . (13.91) 542 Pulse-Width Modulated DC–DC Power Converters 100 90 80 60 50 |Z icl | (Ω) 70 40 30 20 10 0 1 10 Figure 13.19 2 10 3 10 f (Hz) 4 10 5 10 The magnitude of the closed-loop input impedance Zicl versus frequency for the boost converter. Example 13.6 A boost converter has 𝛽 = 0.125, VTm = 5 V, VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, r = 0.316 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, and C3 = 5 nF. Calculate Ricl (0). Draw the plots for the closed-loop input impedance Zicl as the magnitude and the phase and also as the real and imaginary parts for the boost converter. Solution: The closed-loop input resistance is Ricl (0) = −[(1 − Dnom )2 RLmin − r] = −[(1 − 0.5)2 × 40 − 0.316] = −9.684 Ω. (13.92) Figures 13.19 and 13.20 show plots of Zicl = |Zicl |ej𝜙Zicl versus frequency. Note that the phase 𝜙Zicl is close to −180◦ at low frequencies. Figures 13.21 and 13.22 depict plots of Zicl = Ricl + jXicl versus frequency. The input resistance Ricl is negative at low frequencies from 0 to 400 Hz. This may cause instability. 13.10 Closed-Loop Output Impedance The closed-loop output impedance including the load resistance RL is Zocl (s) ≡ = vt (s) Zo (s) | = it (s) vr (s)=0 and vi (s)=0 1 + T(s) s(s + 𝜔pc )2 (s + 𝜔zn )(s + 𝜔rl ) RL rC ( ) RL + rC s(s + 𝜔pc )2 s2 + 2𝜉𝜔0 s + 𝜔2 + Tx (s + 𝜔zc )2 (s + 𝜔zn )(s − 𝜔zp ) 0 where vt and it are the test voltage and the test current, respectively. (13.93) Voltage-Mode Control of Boost Converter 543 90 60 30 0 ϕ Zicl (°) −30 −60 −90 −120 −150 −180 1 10 Figure 13.20 2 10 3 10 f (Hz) 4 10 5 10 The phase of the closed-loop input impedance Zicl versus frequency for the boost converter. 2 0 Ricl (Ω) −2 −4 −6 −8 −10 1 10 Figure 13.21 converter. 2 10 3 10 f (Hz) 4 10 5 10 The input resistance of the closed-loop input impedance Zicl = Ricl + jXicl versus frequency for the boost 544 Pulse-Width Modulated DC–DC Power Converters 100 80 40 X icl (Ω) 60 20 0 −20 1 10 Figure 13.22 converter. 2 10 3 10 f (Hz) 4 10 5 10 The input reactance of the closed-loop input impedance Zicl = Ricl + jXicl versus frequency for the boost The closed-loop output impedance excluding the load resistance RL is given by 1 1 1 = − . ′ Zocl RL Zocl (13.94) ′ ′ Since |Zocl | ≪ RL , Zocl ≈ Zocl . The magnitude of the output impedance |Zocl | of an ideal voltage source should be zero at all frequencies. Example 13.7 A boost converter has 𝛽 = 0.125, VTm = 5 V, VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, C3 = 5 nF. Calculate Ricl (0). Draw the plots for the closed-loop output impedance Zocl versus frequency for the boost converter for D = 0.4, 0.5, and 0.6. Solution: Figures 13.23 and 13.24 show the plots of Zocl for the boost converter. 13.11 Closed-Loop Step Responses 13.11.1 Closed-Loop Response to Step Change in Input Voltage Assume that the step change in the input voltage is ΔVI at time t = 0 and the steady-state input voltage before the step change is VI (0− ). Therefore, the total input voltage is given by vI (t) = VI (0− ) + ΔVI u(t) (13.95) Voltage-Mode Control of Boost Converter 545 1.5 1.25 | Zocl | (Ω) 1 0.75 0.5 0.25 0 1 10 Figure 13.23 2 10 3 10 f (Hz) 4 10 5 10 Plot of the magnitude of the closed-loop output impedance Zocl versus frequency for the boost converter. 90 60 0 ϕ Zocl (°) 30 −30 −60 −90 1 10 Figure 13.24 2 10 3 10 f (Hz) 4 10 5 10 Plot of the magnitude of the closed-loop output impedance Zocl versus frequency for the boost converter. 546 Pulse-Width Modulated DC–DC Power Converters which results in a step change in the input voltage in the time domain vi (t) = vI (t) − VI (0− ) = ΔVI u(t) (13.96) and in the s-domain ΔVI . s Hence, one obtains a transient component of the output voltage in the s-domain (13.97) vi (s) = vo (s) = Mvcl (s)vi (s) = ΔVI Mv (s) ΔVI Mvcl (s) = s s[1 + T(s)] (13.98) the transient component of the output voltage in the time domain vo (t) = −1 {vo (s)} for t≥0 (13.99) vO (t) = VO (0− ) + vo (t) for t ≥ 0. (13.100) and the total output voltage Example 13.8 Draw the waveform of the total output voltage vO (t) of the closed-loop boost converter of Example 13.1 as a response to the step change in the input voltage from 12 to 13 V. Find the maximum relative transient ripple of the total output voltage vO . Solution: Figure 13.25 shows the step response of the output voltage vO to the step change in the input voltage vI from 12 to 13 V for the boost converter with negative feedback at 𝛽 = 0.125, VTm = 5 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, 20.7 20.6 20.4 O v (V) 20.5 20.3 20.2 20.1 20 Figure 13.25 feedback. 0 1 2 3 4 t (ms) 5 6 7 8 Response of vO to a step change in input voltage vI from 12 to 13 V for the boost converter with negative Voltage-Mode Control of Boost Converter 547 R2 = 100 kΩ, C1 = 5 nF, C2 = 0.15 nF, C3 = 5 nF, and D = 0.5. The output voltage increases from 20 to 20.63 V and then returns back to VO = 20 V after 6 ms. The maximum relative transient ripple of the output voltage is 𝛿max = vOmax − vO (∞) 20.63 − 20 0.63 = = = 3.15%. vO (∞) 20 20 (13.101) 13.11.2 Closed-Loop Response to Step Change in Reference Voltage Assume that the step change in the reference voltage is ΔVR at time t = 0 and the reference voltage is VR (0− ). The total reference voltage can be described by vR (t) = VR (0− ) + ΔVR u(t). (13.102) Hence, the ac component of the reference voltage in the time domain is vr (t) = vR (t) − VR (0− ) = ΔVR u(t) (13.103) and in the s-domain is ΔVR . s The transient component of the output voltage in the s-domain can be expressed as vr (s) = vo (s) = Tpcl (s)vr (s) = ΔVR Tcl (s) ΔVR A(s) = . s s[1 + T(s)] (13.104) (13.105) The inverse Laplace transform of vo (s) produces the transient component of the output voltage vo (t) = −1 {vo (s)} for t≥0 (13.106) vO (t) = VO (0− ) + vo (t) for t ≥ 0. (13.107) and the total output voltage Example 13.9 Draw the total output voltage vO (t) of the closed-loop boost converter of Example 13.1 as a response to the step change in the reference voltage vR from 2.5 to 3 V. Find the maximum overshoot and the maximum transient ripple. Also, calculate an increase in the steady-state output voltage. Solution: Figure 13.26 shows the step response of the output voltage vO to a step change in the reference voltage vR from 2.5 to 3 V, which corresponds to the step change in the ac component of the reference voltage vr from 0 to 0.5 V at D = 0.5 for the boost converter with negative feedback. The total output voltage vO initially decreases from 20 to 19.8 V, then increases to 23.8 V, decreases again, and finally reaches a steady-state value of 24 V after 5 ms. Notice that output voltage initially decreases because of the presence of the RHP zero in the transfer function Tcl . The peak value of vO is lower than the steady-state value. Therefore, the overshoot can be considered to be zero. At the reference voltage VR = 2.5 V and the output voltage VO = 20 V, the closed-loop control-to-output voltage transfer function should be V 20 = 8 = 18.062 dB. (13.108) Tclo = Tcl (0) = O = VR 2.5 The increase of the reference voltage VR from 2.5 to 3 V causes the output voltage VO to increase to VO = Tclo VR = 8 × 3 = 24 V (13.109) or VO = Tclo VR ≈ VR 3 = = 24 V. 𝛽 0.125 (13.110) 548 Pulse-Width Modulated DC–DC Power Converters 24 23.5 23 22 O v (V) 22.5 21.5 21 20.5 20 19.5 0 1 2 3 t (ms) 4 5 6 Figure 13.26 Response of vO to a step change in reference voltage vR from 2.5 to 3 V for the boost converter with negative feedback. Thus, the increase in the steady-state output voltage is ΔVO = Tclo ΔVR = 8 × 0.5 = 4 V. (13.111) The dc output voltage VO increases from 20 V to approximately 24 V. 13.11.3 Closed-Loop Response to Step Change in Load Current The load current contains a step change ΔIO at t = 0 is described by iO (t) = IO (0− ) + ΔIO u(t). (13.112) Hence, the small-signal step change in the load current is io (t) = iO (t) − IO (0− ) = ΔIO u(t). (13.113) which gives ΔIO . s Therefore, the transient component of the output voltage is given by io (s) = vo (s) = −Zocl (s)io (s) = s(s + 𝜔pc )2 (s + 𝜔zn )(s + 𝜔rl ) ΔIO RL rC . ( ) RL + rC s2 (s + 𝜔pc )2 s2 + 2𝜉𝜔0 s + 𝜔2 + Tx s(s + 𝜔zc )2 (s + 𝜔zn )(s − 𝜔zp ) (13.114) (13.115) 0 The transient component of the output voltage in the time domain vo (t) = −1 {vo (s)} for t≥0 (13.116) Voltage-Mode Control of Boost Converter 549 and the total output voltage vO (t) = VO (0− ) + vo (t) t ≥ 0. for (13.117) Example 13.10 Draw the waveform of the total output voltage vO (t) of the closed-loop boost converter of Example 13.1 as a response to the step change in the load current iO from 0.5 to 0.6 A. Find the maximum relative transient ripple of the total output voltage vO . Solution: Figure 13.27 shows a step response of the output voltage vO to a step change in the load current iO from 0.5 to 0.6 A for the boost converter with negative feedback at 𝛽 = 0.125, VTm = 5 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, R2 = 100 kΩ, C1 = 5 nF, C2 = 0.15 nF, C3 = 5 nF, and D = 0.5. The output voltage decreases from 20 to 19.893 V and then returns back to VO = 20 V after 5 ms. The maximum relative transient ripple of the output voltage is 𝛿max = |vOmin − vO (∞)| |19.893 − 20| 0.107 = = = 0.535%. vO (∞) 20 20 (13.118) 13.12 Closed-Loop DC Transfer Functions The dc voltage transfer function of the forward path is Ao = A(0) = VO = Tco Tm Tpo VE (13.119) 20 19.98 O v (V) 19.96 19.94 19.92 19.9 19.88 Figure 13.27 feedback. 0 1 2 t (ms) 3 4 5 Response of vO to a step change in load current iO from 0.5 to 0.6 A for the boost converter with negative 550 Pulse-Width Modulated DC–DC Power Converters where Tco = Tc (0) is the dc gain of the control circuit. The dc loop gain is expressed by To = T(0) = VF = 𝛽Ao = 𝛽Tco Tm Tpo . VE (13.120) The dc closed-loop control-to-output voltage gain is Tclo = Tcl (0) = VO Ao = . VR 1 + 𝛽Ao (13.121) If 𝛽Ao ≫ 1, then Tclo = Ao 1 ≈ 1 + 𝛽Ao 𝛽 (13.122) VR . 𝛽 (13.123) and the dc output voltage is VO = Tclo VR ≈ To ensure that the dc output voltage VO remains constant and equal to a desired value, the loop gain 𝛽Ao must be very high and the feedback network voltage transfer function 𝛽 and the reference voltage VR must be accurate. An accurate value of 𝛽 is achieved by using precision resistors, for example, 1%. The dc closed-loop audio susceptibility is Mvclo = Mvo 1 + 𝛽Ao (13.124) and the dc closed-loop output resistance is Roclo = Rocl (0) = Ro . 1 + 𝛽Ao (13.125) Example 13.11 For the boost converter given in Example 13.1, calculate Tclo , VO , VE , Zoclo , and Mvclo if Tco = 1000, Tpo = 37.55, 𝛽 = 1∕8, VTm = 5 V, Mvo = 1.939, and Zoo = 1.225 Ω. Solution: The bound resistor is Rb = Tco (R1 + h11 ) = 1000 × (100 + 0.542) = 100.542 MΩ. (13.126) Pick Rb = 100 MΩ/0.25 W/5%. The dc voltage transfer function of the forward path is 1 × 37.55 = 7510. 5 (13.127) ( ) 1 × 7510 = 938.75 = 59.45 dB. 8 (13.128) Ao = A(0) = Tco Tm Tpo = 1000 × The dc loop gain is To = T(0) = 𝛽Ao = The dc closed-loop control-to-output gain is Tclo = Ao Ao 7510 = 7.9915 = 18 dB. = = 1 + To 1 + 𝛽Ao 1 + 938.75 (13.129) The dc output voltage is VO = Tclo VR = 7.9915 × 2.5 = 19.9787 V (13.130) VF = 𝛽VO = 0.125 × 19.9787 = 2.4973 V (13.131) the dc feedback voltage is Voltage-Mode Control of Boost Converter 551 and the dc error voltage is VE = VR − VF = 2.5 − 2.4973 = 2.7 mV. (13.132) The dc closed-loop input-to-output voltage transfer function is Mvclo = Mvo Mvo 1.939 = 2.0633 × 10−3 = −53.7 dB. = = 1 + To 1 + 𝛽Ao 1 + 938.75 (13.133) When the reference voltage VR is increased from 2.5 to 3 V, ΔVR = 0.5 V. The increase in the dc output voltage is The dc output voltage is ΔVO = Tclo ΔVR = 7.9915 × 0.5 = 3.99575 ≈ 4 V. (13.134) VO (∞) = VO (0− ) + ΔVO = 20 + 4 = 24 V. (13.135) The dc output voltage is Assuming that the dc input voltage will have a step change from 12 to 13 V, then ΔVI = 1 V. The change in the dc output voltage is ΔVO = Mvclo ΔVI = 0.00020633 × 1 = 2.00633 mV. (13.136) VO (∞) = VO (0− ) + ΔVO = 20 + 0.002 = 20.002 V. (13.137) The dc output voltage is The line regulation at IO = 0.5 A is LNR = ΔVO 0.002 = 0.002 = 2 mV∕V. = ΔVI 1 (13.138) The percentage line regulation is PLNR = ΔVO × 100 VOnom ΔVI = 0.002 × 100 20 1 = 0.01%∕ V. (13.139) The dc closed-loop output impedance is Roclo = Rocl (0) = Ro (0) Zoo 1.225 = 1.3 mΩ. = = 1 + To 1 + 𝛽Ao 1 + 938.75 (13.140) Assuming that the dc output current has a step change from 0.5 to 0.6 mA, then ΔIO = 0.1 A. This causes a change in the dc output voltage ΔVO = −Rocl (0)ΔIO = −1.3 × 103 × 0.1 = −0.13 mV. (13.141) VO (∞) = VO (0− ) − ΔVO = 20 − 0.0013 = 19.9987 V. (13.142) The dc output voltage is The load regulation is LOR = ΔVO −0.13 = −0.26 mV∕A. = ΔIO 0.5 (13.143) The dc reference-to-output voltage transfer function is TVDC = VO ∕VR = VI ∕[D(1 − D)VTm ] = 12∕[0.5(1 − 0.5)5] = 9.6. (13.144) 552 13.13 Pulse-Width Modulated DC–DC Power Converters Summary r The closed-loop boost converter consists of feedback network, control circuit, pulse-width modulator, and boost converter power stage. r It is difficult to achieve good gain and phase margins of the boost converter because of the RHP zero. r The bandwidth of the boost converter with voltage-mode control is usually narrow. r The input resistance of the closed-loop boost converter is negative. References [1] R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I and II. Pasadena, CA, TESLAco, 1981. [2] R. D. Middlebrook, “Measurement of loop gain in feedback systems,” International Journal of Electronics, vol. 38, no 4, pp. 485–512, April 1975. [3] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits, New York: Van Nostrand, 1985, pp. 30–42 and 130–135. [4] H. D. Venable, “The K factor: A new mathematical tool for stability analysis and synthesis,” Proceedings of the Powercon 10, 1983, H-1, pp. 1–12. [5] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2003. [6] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics, Reading, MA: Addison-Wesley, 1991. [7] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2nd Ed. Norwell, MA: Kluwer, 2001. [8] V. Vorpérian, “Simplified analysis of PWM converters using the model of the PWM switch, Part I: Continuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-26, pp. 497–505, May 1990. [9] D. Czarkowski and M. K. Kazimierczuk, “Energy conservation approach to modeling PWM dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. 29, pp. 1059–1063, July 1993. [10] M. K. Kazimierczuk and D. Czarkowski, “Application of the principle of energy conservation to modeling the PWM converters,” 2nd IEEE Conference on Control Applications, Vancouver, Canada, September 13–16, 1993, pp. 291–296. [11] M. K. Kazimierczuk and R. C. Cravens, II, “Close-loop characteristics of voltage-mode controlled PWM boost dc-dc converter with integral-lead controller,” Journal of Circuits, Systems, and Computers, vol. 4, no. 4, pp. 429–458, 1994. [12] M. K. Kazimierczuk and R. C. Cravens, II, “Experimental results for the small-signal study of PWM boost dc-dc converter with an integral-lead controller,” Journal of Circuits, Systems, and Computers, vol. 5, no. 4, pp. 747–755, 1995. [13] A. Aminian and M. K. Kazimierczuk, Electronic Devices, A Design Approach, ch. 12. Upper Saddle River, NJ: Prentice Hall, 2003, pp. 523–564. Review Questions 13.1 Draw the boost converter along with other stages that form a single-loop negative feedback control circuit. 13.2 Draw a single-loop control circuit for the boost converter with the feedback network replaced by h-parameters. 13.3 Draw a single-loop control circuit for the boost converter with the resistances of the feedback network moved to the A-circuit. 13.4 Derive an expression for the closed-loop gain of the boost converter Tcl . 13.5 Is it easy to ensure the stability of the boost converter? 13.6 What is the effect of negative feedback on the audio susceptibility Mvcl ? 13.7 What is the effect of negative feedback on the input impedance Zicl ? 13.8 What is the effect of negative feedback on the output impedance Zocl ? Voltage-Mode Control of Boost Converter 553 Problems 13.1 A pulse-width modulator has a ramp output voltage with a peak value VTm = 5 V. Find a transfer function of the modulator. 13.2 A boost PWM converter has VInom = 156 V, Dnom = 0.65, and the pulse-width modulator VTm = 5 V. Determine the dc reference voltage for a control circuit. 13.3 A boost PWM converter has VO = 400 V and the reference voltage is VR = 3.25 V. Design a feedback network. 13.4 A boost PWM converter has Tpo = 1114.27 V, a feedback network has 𝛽 = 1∕123, and a pulse-width modulator has Tm = 0.2 (1/V). Determine the overall voltage transfer function Tko of the three stages at f = 0. 13.5 A boost PWM converter has VI = 156 V, VO = 400 V, VR = 3.25 V, Tko = 1.8118, 𝛽 = 1∕123, 𝜉 = 0.162, fzn = 159 kHz, fzp = 1.17 kHz, and f0 = 322 Hz. Design a control circuit such that PM ≥ 55◦ . 13.6 The transfer function of the feedback network in a boost converter is 𝛽 = 1∕123. Find the value of the closed-loop control-to-input voltage transfer function at f = 0. 13.7 A closed-loop boost converter has Dnom = 0.65, RLmin = 1.778 kΩ, RLmax = 17.78 kΩ, and r = 2.756 Ω. Find the values of the dc closed-loop input resistance at RLmin and RLmax . 14 Current-Mode Control 14.1 Introduction The control circuit of a power dc–dc converter must decide when to turn the switch (or switches) on and off. Voltage-mode control (VMC), also called duty-cycle control, contains a single loop and adjusts the duty cycle directly in response to the change in output voltage. Current-mode control (CMC) [1–84], also called currentprogrammed mode (CPM) or current-injected control (CIC), is a multiple-loop control method that contains two loops: the inner-current loop and the outer voltage loop. The inner-current loop controls the inductor peak current, while the outer-voltage loop controls the output voltage. The technique is called CMC because the inductor current is directly controlled, whereas the output voltage is controlled only indirectly by the current loop. The inductor peak current is close to the inductor average current. The inductor average current is related to the load current. In buck and buck-derived converters, the load current is equal to the average current. In the boost converter (often used as a power-factor corrector), the average input current is equal to the average inductor current. The inner-current loop initially adjusts the duty cycle in response to the changes in inductor current, and the outer voltage loop produces a reference voltage for the current loop in response to the changes in the converter output voltage. The duty cycle is determined by the time instants at which the inductor or switch current reaches a threshold level determined by a control signal. This threshold level becomes the input to the inner loop. The key feature of the CMC is that the inner loop changes the inductor into a voltage-dependent current source at frequencies lower than the crossover frequency of the current loop. The action of the current loop is similar to that of a sample-and-hold circuit, which is a nonlinear, time-varying (NTV) system. There are seven known types of CMC methods. They, in turn, fall into two categories: constant-frequency and variable-frequency control methods. In the first group, the switching frequency is constant and synchronized to a clock signal fs = fCLK . This group contains peak-current-mode control (PCM), valley-current-mode control, the PWM-conductance control with triangle-wave compensation, and average current-mode control (ACM). The second group contains self-oscillating converters, including constant on-time, constant-off time, and hysteretic methods. The most popular method is fixed-frequency peak-current-mode control with fixed-slope compensation ramp. In this chapter, we shall study in detail the principle of operation of the peak-current-mode control, stability of the current loop, slope compensation, the block diagram of PWM converters with CMC, and key characteristics of current-mode controlled converters. The inner-current loop has a tendency to instability, resulting in subharmonic oscillation (also called period doubling). The required relative stability of the inner loop can be accomplished by means of an artificial ramp current either subtracted from the control current or added to the inductor current Pulse-Width Modulated DC–DC Power Converters, Second Edition. Marian K. Kazimierczuk. © 2016 John Wiley & Sons, Ltd. Published 2016 by John Wiley & Sons, Ltd. Companion Website: www.wiley.com/go/kazimierczuk/modulatedpower2 Current-Mode Control 555 waveform. CMC can also be used in constant-current dc-dc converters. There are IC control circuits, for example, UC3843. 14.2 Principle of Operation of PWM Converters with Peak CMC The circuits of the PWM buck, boost, and buck–boost converters with fixed-frequency peak-current-mode control are shown in Figures 14.1, 14.2, and 14.3, respectively. Each circuit contains two loops: an inner-current loop and an outer voltage loop. The inner-current loop contains an op-amp voltage comparator, an S–R (set–reset) latch, a clock CLK, and a current sensor, for example, a current transformer or a noninductive sense resistor Rs , which senses the inductor current iL or the switch current iS . In general, Rs represents the transfer function from the inductor or switch current to the sensor output voltage. It is current-to-voltage gain of the sensor. It may be a transfer function of a current transformer, which has corner frequencies in the low-frequency and high-frequency ranges. The latch S input sets (or presets) the Q output to 1, and the latch R input resets (or clears) the Q output to 0. The op-amp comparator, the S–R latch, and the clock CLK form an inductor current modulator. The analog control voltage vC is applied to the comparator inverting input, and the voltage Rs iL (proportional to the inductor current iL ) or the voltage Rs iS (proportional to the switch current iS ) is applied to the comparator non-inverting input. If a non-inductive resistor Rs is connected between the comparator non-inverting input and ground (as shown in Figure 14.1), the current through the resistor Rs is iC = v+ ∕Rs ≈ vC ∕Rs . This current can be regarded as a control current (or a reference current) for the inner-current loop. Figure 14.4 depicts the waveforms explaining the principle of operation of PWM converters with CMC. The clock generates voltage pulses at a constant clock frequency fCLK equal to the switching frequency fs = 1∕Ts . When the clock output voltage vCLK = vS goes high, the latch Q output vQ goes high (i.e., it sets the Q output to 1). Therefore, the gate-to-source voltage vGS also goes high, turning the switch on. This event initiates the transistor on-time and starts the cycle Ts of the switching frequency fs . Since the turn-on times are periodically clocked, a constant-frequency operation is obtained. While the switch is on, the inductor current iL and the switch current iS increase linearly. The inductor current iL , or the switch current iS , is sensed by a current probe (or current CT L V vF + VI . vC Zi ′ vR + Zf vS Rs iL Rs + vF Figure 14.1 + V + + vE + VR ~ . vi + vI β RQ S CLK RA iL iL C RL io dT + vQ + vO RB Circuit of a PWM buck converter with peak-current-mode control. + vO 556 Pulse-Width Modulated DC–DC Power Converters L iL vI Rs vC vR vF + RL io + vO iS V + + vE C VI V + VR ~ vi + + Zi ′ Zf vS Rs iS dT RQ + S vQ CLK β RA + vF Figure 14.2 + vO RB Circuit of a PWM boost converter with peak-current-mode control. transformer). The currents iL and iS are equal during the transistor on-time. The sensed inductor current iL (or the switch current iS ) flows through the resistor Rs and develops a voltage Rs iL . When the voltage Rs iL = v+ is lower than the control voltage vC = v− , the comparator output voltage vR is low. When the voltage Rs iL reaches the control voltage vC , the comparator output voltage vR goes high, resetting the latch Q output to 0. Therefore, the gate-to-source voltage vGS goes low, turning the switch off for the remaining time of the switching period. As a ~ . V vi + vI V vF + vC Zi ′ vR + Zf vS Rs iL β + vF Figure 14.3 RQ S CLK RA iL L . I V + + vE + VR + C io RL Rs dT + vQ + vO + vO RB Circuit of a PWM buck–boost converter with peak-current-mode control. + vO Current-Mode Control 557 vCLK Ts 0 2Ts t 3Ts vC , Rs iL v vC v+ Rs iL 0 t 0 t 0 t 0 t vR vQ dT 1 Figure 14.4 control. Waveforms of PWM converters with constant-frequency, trailing-edge modulation, peak-current-mode result, the inductor current iL decreases. Since Rs iL < vC , the comparator output voltage vR goes low. In summary, the clock sets the latch and turns the transistor on at the beginning of the cycle Ts . The comparator resets the latch and turns the transistor off when the inductor current iL reaches the control current iC . Consequently, the peak inductor current ILpk and the peak switch current ISpk follow the control current iC = vC ∕Rs . Thus, the amplitude modulation (AM) of the inductor current iL takes place, where the control current iC or the control voltage vC is the modulating signal. The average inductor current is ΔiL . (14.1) 2 Since the peak inductor current is directly controlled, this method is called a peak-current-mode control. It can be regarded as an amplitude modulation of the inductor current by the control current. The inner-current loop is capable of responding very rapidly to control voltage (or control current) changes on a cycle-by-cycle or pulse-bypulse basis. This control strategy is referred to as constant-frequency trailing-edge modulation peak-current-mode control or constant-frequency peak-current-mode on-time control because a fixed-frequency clock signal is used to turn on the switch, and the intersection of the voltage Rs iL (proportional to the inductor current iL ) with the control voltage vC is used to turn the switch off. The control decision is taken in each cycle. In other words, the clock initiates the on-time interval ton and the control voltage initiates the off-time interval toff . Thus, the switch on-time is controlled at a fixed frequency. This method requires inductor current information during the switch on-time. The average value of the inductor current is lower than the peak value of the inductor current by one-half IL ≈ ILpk − 558 Pulse-Width Modulated DC–DC Power Converters of the inductor peak-to-peak current ripple ΔiL ; therefore, the average inductor current is controlled indirectly. The outer voltage loop senses the output voltage and develops a control voltage vC , which serves as a reference voltage for the inner-current loop; thus, the outer voltage loop adjusts the control voltage vC . The inductor current is fed back through a sensing resistor Rs and the resulting voltage Rs iL is compared with the control voltage vC . The output voltage is fed back through a resistive voltage divider RA –RB , is compared with the reference voltage VR , and sets the control voltage vC . The input to the current loop is the control voltage vC , which is compared to the sensed inductor current iL (or voltage Rs iL ) and sets the duty cycle. In turn, the duty cycle produces a corresponding inductor current and output voltage. As a first-order approximation, the current loop causes the inductor to act like a voltage-controlled (or current-controlled) current source vC ∕Rs . A dual modulation strategy uses a constant-frequency clock signal to turn the transistor off and the intersection of the inductor or diode current to turn on the transistor. Thus, the switch off-time is controlled at fixed frequency. This control strategy is referred to as a constant-frequency leading-edge modulation valley current-mode control or constant-frequency valley current-mode off-time control. There are also three variable-frequency modulation strategies. The first is constant on-time control, the second is constant off-time control, and the third is hysteretic control. In hysteretic control, the inductor current waveform is used to turn on and turn off the switch, resulting in free-running operation. In addition to CMC based on instantaneous inductor current, there is also an average CMC method, where inductor current waveform is integrated by a low-pass filter placed at the output of the sense resistor Rs . The advantage of this method is the ability to directly control the average inductor current and increase the noise immunity. The constant-frequency trailing-edge modulation control strategy is the most widely used in practice with a large number of control ICs in the market and, therefore, is studied here in detail. CMC exhibits a feedforward control feature. When the converter input voltage VI is increased, the slope of the rising inductor current also increases. Therefore, the switch turns off sooner, yielding nearly constant volt-second balance and making the converter output voltage VO less dependent on the input voltage VI . In general, basic PWM converters (buck, boost, and buck–boost) are second-order systems, in which one state variable is the inductor current and the other state variable is the capacitor voltage (which is approximately equal to the output voltage). The converter dynamic performance can be improved by controlling both state variables. When CMC is used, the reference signal for the inner loop and the inductor current depends on the converter output voltage. As a result, one variable controls the other. Consequently, there is only one true state variable (i.e., the capacitor voltage), resulting in a system that behaves approximately as a first-order system. CMC offers several advantages over VMC. Firstly, if the maximum value of the control current iC is limited, then the maximum value of switch current iS is also limited. Since the inductor peak current is approximately equal to the inductor average current, which in turn is related to the load current, the output current can be limited simply by clamping the control voltage. The transistor turns off whenever its current becomes too high. Therefore, transistor and diode failures due to excessive currents can be prevented and the load current can be held below a predetermined maximum level. Thus, CMC inherently provides a fast pulse-by-pulse short-circuit and overcurrent load protection, enhancing the converter reliability. In addition, the transient peak values of the inductor, switch, and diode currents are limited. A Zener diode may be connected between the comparator inverting input and ground to limit the maximum value of the control voltage. Secondly, it is easy to connect power converters with CMC in parallel in order to increase current capability and/or redundancy without load current-sharing problems. This is because the output current of each unit is determined by the control signal. If all the units receive the same control signal, then all of them will deliver the same amount of current. Thirdly, CMC is a perfect solution to transformer imbalance in symmetrical converters, such as full-bridge and push-pull converters. The imbalance may be caused by the volt-second differences between the positive and negative pulses applied to the transformer. A series capacitor, which is usually used in full-bridge converters to remedy the transformer imbalance, should be removed if CMC is used. A disadvantage of peak-current-mode control is its inherent instability of the inner-current loop when D > 0.5, resulting in subharmonic oscillations. For a duty ratio greater than 0.5, slope compensation is required. Moreover, this control scheme is susceptible to noise, especially when the inductor ripple is small. This noise may corrupt the control voltage, the inductor current or switch current, generating a false signal for the non-inverting comparator Current-Mode Control 559 input. Current spikes caused by the diode reverse recovery may have a detrimental effect. The CMC scheme requires a current sensor, which is usually a resistor Rs connected in series with the inductor L or the MOSFET source. Current flow through this resistor causes power loss. In addition, the sense resistor connected in series with the MOSFET source causes a degradation of the transistor current capability and may require a larger transistor size [64]. In the average-current-mode control [6–55], the inductor current is sensed and fed to a two-pole and one-zero compensation network, which averages the inductor current. Consequently, the average inductor current follows the control reference current. The advantage of this control scheme is good immunity of a converter to switching noise because the average current is sensed. In addition, there is no need for slope compensation. With charge control [56], the inductor current is sensed and used to charge a capacitor. The capacitor voltage is compared to a control voltage, which represents the current to be controlled. As soon as the capacitor voltage reaches the control voltage, the active switch is turned off and the capacitor is quickly discharged to zero by an auxiliary switch connected in parallel with the capacitor. In this technique, the inductor current is indirectly controlled by regulating the peak capacitor voltage, which is proportional to the integral of the inductor current within one cycle. The advantage of this control scheme is good noise immunity due to the integration of the inductor current. 14.3 Relationship Between Duty Cycle and Inductor-Current Slopes Let us assume that a PWM converter is operated in steady state with constant input voltage VI , output voltage VO , load resistance RL , and duty cycle D. Figure 14.5 shows the inductor voltage and current waveforms under these conditions for CCM. The rising and falling slopes of the inductor current waveform are given by M1 = tan 𝛼 = ΔiL DTs (14.2) vL VL ON 0 Ts t VL OFF iL Δ iL M1 β α DTs Figure 14.5 M2 (1 D)Ts Ts t Steady-state waveforms of the inductor voltage and current in PWM converters for CCM. 560 Pulse-Width Modulated DC–DC Power Converters and M2 = tan 𝛽 = ΔiL . (1 − D)Ts (14.3) Hence, the ratio of the absolute values of the inductor-current slopes for all basic PWM converters in steady state is given by M2 D . = M1 1−D (14.4) Thus, the on-time slope M1 is equal to the off-time slope M2 at D = 0.5, M2 < M1 for D < 0.5, and M2 > M1 for D > 0.5. In general, the rising and falling slopes of the inductor current are M1 = VL ON L (14.5) M2 = VL OFF . L (14.6) M1 = VI − VO L (14.7) M2 = VO . L (14.8) M1 = VI L (14.9) VI − VO . L (14.10) M1 = VI L (14.11) M2 = VO . L (14.12) and For the buck converter, and For the boost converter, and M2 = − For the buck–boost converter, and 14.4 Instability of Closed-Current Loop A perturbation theory will be used to investigate the stability of the current loop. Consider a PWM converter with constant-frequency, trailing-edge modulation, peak-current-mode control operated in CCM, in which the inner-current loop is closed and the outer voltage loop is open. Assume that there is a small perturbation in iL (0). Figure 14.6 shows two inductor current waveforms: one for steady state and the other after small perturbation |ΔiL0 | at the beginning of the transistor on-time interval at t = 0. The difference between the steady-state inductor current waveform iLssn and the perturbated inductor current waveform iLpertn is the small-signal component of the inductor current iln = iLssn − ILpertn . The perturbation causes a series of changes in the small-signal component of the inductor Current-Mode Control i C , iL 561 dTs iC M1 M2 M1 α α ΔiL1 M2 iL iL β dTs ΔiL0 ΔiL2 dTs DTs 0 Ts 2Ts t Ts 2Ts t vGS dTs 0 DTs Figure 14.6 Steady-state and perturbed (transient) waveforms of inductor current in PWM converters with currentmode control in CCM. current ΔiLn from the steady-state waveform in successive cycles in the form of an alternating geometric progression, also known as an alternating geometric sequence, whose common ratio is rp = ΔiLn ∕ΔiL(n−1) = −D∕(1 − D) = −a. Each new term is equal to the previous term multiplied by the common ratio rp = −D∕(1 − D), and its magnitude may decrease, remain constant, or increase with time. Since the common ratio is negative (rp < 1), the geometric sequence is alternating, whose terms alternate from negative to positive and from positive to negative. Initially assume that the input voltage VI and the output voltage VO are constant, i.e., their ac components are zero. Therefore, the slopes of the inductor current waveform M1 = VL ON ∕L and M2 = VL OFF ∕L are also constant, where VL ON and VL OFF are the voltages across the inductor during the transistor on-time and off-time intervals, respectively. These slopes are obtained from geometric considerations as M1 = tan 𝛼 = |ΔiL0 | dTs (14.13) M2 = tan 𝛽 = |ΔiL1 | dTs (14.14) and where |ΔiL0 | is the absolute value (or the magnitude) of the inductor current change at t = 0 and |ΔiL1 | is the absolute value of the inductor current change at t = Ts . Using (14.4), (14.13), and (14.14), one obtains the perturbation ratio defined as the ratio of the inductor current change after one cycle |ΔiL1 | to the inductor current change at the beginning of the cycle |ΔiL0 | a= |ΔiLn | M |ΔiL1 | D = = 2 = = |rp |. |ΔiL0 | |ΔiL(n−1) | M1 1−D (14.15) 562 Pulse-Width Modulated DC–DC Power Converters The perturbation coefficient, defined as the ratio of the inductor current change after n cycles ΔiLn to the initial inductor current change ΔiL0 , is given by ( )n ( )n |ΔiL(n−1) | |ΔiLn | |ΔiLn | |ΔiL1 | M2 D an = = lim × ×⋯× = a2 = = (14.16) |ΔiL0 | n→∞ |ΔiL(n−1) | |ΔiL(n−2) | |ΔiL0 | M1 1−D where a = a2 ∕a1 = an ∕an−1 . Hence, )n ( |ΔiLn | D = lim = 0, n→∞ |ΔiL0 | n→∞ 1 − D for D < 0.5 (14.17) ( )n |ΔiLn | D = lim = 1, n→∞ |ΔiL0 | n→∞ 1 − D for D = 0.5 (14.18) )n ( |ΔiLn | D = lim = ∞, n→∞ |ΔiL0 | n→∞ 1 − D for D > 0.5. (14.19) lim an = lim n→∞ lim an = lim n→∞ and lim an = lim n→∞ It follows from (14.15) that: (1) The inner-current loop is stable if a= |ΔiL1 | M2 D = <1 = |ΔiL0 | M1 1−D (14.20) which occurs for M1 > M2 . (14.21) The condition of stability of the inner-current loop is satisfied for D < 0.5. In this case, |ΔiL1 | < |ΔiL0 |, the perturbation magnitude |ΔiLn | decays with time to zero as n approaches infinity, and the converter returns to its initial state. (2) The inner-current loop is marginally stable if a= |ΔiL1 | M2 D = =1 = |ΔiL0 | M1 1−D (14.22) which occurs for M1 = M2 . (14.23) This condition is satisfied at D = 0.5, for which |ΔiLn | = |ΔiL0 |, that is, the magnitude of oscillations remains constant, and the converter does not return to its initial state. In this case, the geometric progression is a sequence of constant terms equal to 1. (3) The inner-current loop is unstable if a= |ΔiL1 | M2 D = >1 = |ΔiL0 | M1 1−D (14.24) which occurs for M1 < M2 . (14.25) The instability condition of the inner-current loop is satisfied for D > 0.5. In this case, |ΔiL1 | > |ΔiL0 |, the magnitude of oscillations increases with time, and the converter does not return to its initial state. This leads to subharmonic oscillations at half the switching frequency f fosc = s . 2 (14.26) Current-Mode Control iL 563 D < 0.5 iC 0 Ts 2Ts 3Ts 4Ts t 3Ts 4Ts t 3Ts 4Ts t (a) iL D = 0.5 iC 0 Ts 2Ts (b) iL D > 0.5 iC 0 Ts 2Ts (c) Figure 14.7 Steady-state (solid line) and perturbed (dashed line) waveforms of inductor current iL for PWM converters with current-mode control. (a) For a stable current loop (D < 0.5). (b) For a marginally stable current loop (D = 0.5). (c) For an unstable current loop (D > 0.5). Figure 14.7 shows the steady-state and perturbed (transient) inductor current waveforms for a stable inner-current loop (D < 0.5), a marginally stable current loop (D = 0.5), and an unstable current loop (D > 0.5). For D < 0.5, the perturbed inductor current waveform is convergent to the steady-state waveform. Conversely, for D > 0.5, the perturbed inductor current waveform is divergent and does not return to the steady-state waveform. To achieve a sufficient margin of stability, Dmax should be lower than 0.5, for example, Dmax = 0.2. Figure 14.8 shows smallsignal inductor current waveforms il for PWM converters with CMC for a stable current loop (a < 1), for an unstable current loop (a > 1), and for a marginally stable current loop (a = 1). The small-signal inductor current 564 Pulse-Width Modulated DC–DC Power Converters il 0 D < 0.5 a<1 i lpk 0 t Tosc = 2Ts Ts (a) il 0 D = 0.5 a=1 Ts i lpk = Const t Tosc = 2Ts (b) il 0 D > 0.5 a>1 Ts ∞ i lpk Tosc = 2Ts t (c) Figure 14.8 Small-signal inductor current waveforms il for PWM converters with current-mode control. (a) For a stable current loop (D < 0.5). (b) For a marginally stable current loop (D = 0.5). (c) For an unstable current loop (D > 0.5). il is equal to the difference between the steady-state inductor current iL and the perturbed inductor current iL(pert) , that is, il = iL − iL(pert) . 14.5 Slope Compensation 14.5.1 Analysis of Slope Compensation in Time Domain The instability of the current loop can be eliminated by subtracting an artificial periodic ramp waveform from the control signal waveform, or by adding an artificial ramp waveform to the inductor or switch current waveform. We will consider a fixed-slope compensation ramp case. Figure 14.9 shows an implementation of slope compensation, using a differential amplifier. Figure 14.10 shows the waveforms illustrating the slope compensation, where an artificial periodic ramp current waveform iA is subtracted from the control current iC ; consequently, the slope M2 is reduced, and the switch turns off when iL (DTs ) = iC (DTs ) − iA (DTs ) = iC (DTs ) − M3 DTs . (14.27) Consider the steady-state and perturbed waveforms of the inductor current, depicted in Figure 14.11. The slope of the inductor current waveform iL during the switch on-time interval 0 < t ≤ DTs is M1 = tan 𝛼 = BC dTs (14.28) Current-Mode Control 565 R R vA vc vA R vc + R Figure 14.9 Implementation of slope compensation, using a differential amplifier. and the slope of the ramp current iC –iA is M3 = tan 𝛾 = AB dTs (14.29) producing the magnitude of the inductor current perturbation at t = 0 ΔiL0 = AC = AB + BC = (M1 + M3 )dTs . (14.30) The slope of the inductor current waveform iL during the switch off-time interval DTs < t ≤ Ts is M2 = tan 𝛽 = Δi AC = L0 dTs dTs (14.31) resulting in the magnitude of the inductor current perturbation at t = Ts ΔiL1 = BC = AC − AB = (M2 − M3 )dTs . (14.32) iL , iA ,iC ,iC − iA iC iC iA M3 iL M2 M1 iA 0 M3 DTs Ts t Figure 14.10 Steady-state waveforms of the inductor current iL , the control current iC , an artificial ramp current iA , and iC –iA illustrating slope compensation by subtracting a ramp current iA from the control current iC in PWM converters with current-mode control for CCM. 566 Pulse-Width Modulated DC–DC Power Converters iL , iC , iC iA iC γ M3 γ iL α A B β dTs M1 iC iA C M2 M1 M2 α ΔiL1 β ΔiL0 α DTs 0 dTTs Ts t Ts t vGS 0 Figure 14.11 Waveforms of the inductor current iL , the control current iC , and iC –iA used to derive the stability condition for the current loop with slope compensation. From (14.30) and (14.32), one obtains the perturbation ratio expressed as the ratio of the absolute values of the inductor current changes at t = Ts and t = 0 a= M − M3 ΔiL1 = 2 . ΔiL0 M1 + M3 (14.33) The current loop with slope compensation is stable if a<1 (14.34) M2 − M1 . 2 (14.35) which happens when M3 > Substitution of (14.4) into (14.33) produces a in terms of M1 , M3 , and D a= M M2 − M3 M1 1 M 1 + M3 1 = M D − M3 1−D 1 M 1 + M3 1 < 1. (14.36) Current-Mode Control 567 The maximum duty cycle Dlim below which the current loop is stable for a given slope ratio M3 ∕M1 is given by M Dlim = 1 − 0.5 M = 0.5 + M3 1 + M3 1 for M 1 + M3 1 D > 0.5. (14.37) 1 As the normalized compensating ramp slope M3 ∕M1 increases, the range of the duty cycle, in which the innercurrent loop is stable, increases above 0.5. For example, for M3 ∕M1 = 0.5, the inner loop is stable for 0 < D < 2∕3. From (14.37), D′lim = 1 − Dlim = 0.5 . (14.38) D > 0.5. (14.39) M 1 + M3 1 The condition of stability can be also expressed by [45] M3 D − 0.5 > M1 1−D for At the boundary between unstable and stable operation of the inner loop, M3 D − 0.5 = . M1 1−D (14.40) Figure 14.12 shows the plot of M3 ∕M1 as a function of D. As D is increased from 0.5 to 1, M3 ∕M1 increases from 0 to ∞. The minimum value of the compensating slope is M3min = M1min (Dlim − 0.5) . 1 − Dlim (14.41) 5 4.5 4 3.5 3 M /M 1 3 2.5 2 1.5 1 0.5 0 0 0.2 Figure 14.12 0.4 D 0.6 0.8 Plot of M3 ∕M1 as a function of D. 1 568 Pulse-Width Modulated DC–DC Power Converters At Dlim = 0.5, M3min = 0 as expected. As the maximum duty cycle Dlim is increased from 0.5 to 1, M3min increases from 0 to ∞. To achieve relative stability, one should select M3 sufficiently higher than M3min . Example 14.1 A boost converter has the following specifications: 4 V ≤ VI ≤ 6 V, VO = 10 V, and L = 100 μH. Find the required compensation slope to achieve marginal stability. Solution: The worst case occurs at the minimum input voltage at which the duty cycle reaches its maximum value. The maximum duty cycle is VImin 4 = 0.6. =1− VO 10 Dmax = 1 − (14.42) The maximum perturbation ratio is amax = Dmax M1 0.6 = 1.5. = = M2 1 − Dmax 1 − 0.6 (14.43) The minimum slope of the rising inductor current is VImin 4 A A = . = 40,000 = 40 L s ms 100 × 106 Hence, the compensation slope to achieve marginal stability is ( ) ( ) Dmax − 0.5 A A 0.6 − 0.5 M3min = M1min = 40,000 = 10,000 = 10 . 1 − Dmax 1 − 0.6 s ms M1min = (14.44) (14.45) Using (14.4), (14.33) can be expressed in terms of the slopes M2 and M3 and the duty cycle D as M M 1 − M3 1 − M3 M2 − M3 2 2 = M = 1−D M <1 a= M3 1 M1 + M3 + + 3 M2 M2 M3 1 >1− M2 2D for D (14.46) M2 yielding the condition of stability [45] D > 0.5. (14.47) At the boundary between stable and unstable operation of the inner loop, M3 1 . =1− M2 2D (14.48) Figure 14.13 shows M3 ∕M2 as a function of D. As D is increased from 0.5 to 1, the ratio M3 ∕M2 increases from 0 to 0.5. The minimum compensating slope at a maximum duty cycle Dmax is given by ( ) 1 . (14.49) M3min = M2max 1 − 2Dlim For the worst case, which occurs at D = 1, (14.46) becomes a= M2 −1<1 M3 (14.50) and the condition of stability at any duty cycle D is given by M3 > M2 . 2 (14.51) Current-Mode Control 569 0.5 0.45 0.4 2 0.25 M /M 0.3 3 0.35 0.2 0.15 0.1 0.05 0 0 0.2 0.4 Figure 14.13 D 0.6 0.8 1 Plot of M3 ∕M2 as a function of D. Note that the falling slope M2 approaches infinity as the duty cycle D approaches 1. This requires an infinite value of M3 . From (14.46), a = 0, when the compensating slope M3 is equal to the inductor current falling slope M2 , resulting in M3(DB) = M2 , (14.52) as illustrated in Figure 14.14. In this case, the inductor current waveform reaches steady state in exactly one cycle, yielding the fastest possible response of the inner loop. A perturbation ends within the same cycle in which it starts. Operation at M3 = M2 is called dead-beat control. Note that if M3 = 0, then (14.46) reduces to M2 ∕M1 < 1. From (14.36), the slope of the compensation waveform can be expressed in terms of D and a as ( ) M3 D − a M1 − a M3 1−D M = . (14.53) = 1 M1 1+a a+1 14.5.2 Boundary of Slope Compensation for Buck and Buck–Boost Converters The maximum value of the inductor current on-slope corresponding to Dmax for the buck and buck–boost converters is M1min = VO (1 − Dmax ) . LDmax (14.54) Hence, the critical value of slope compensation corresponding to the marginally stable converter is M3cr = M1min Dmax − 0.5 VO Dmax − 0.5 = . 1 − Dmax L Dmax (14.55) 570 Pulse-Width Modulated DC–DC Power Converters iL , iC , iC iA iC iC iA M3 = M2 M1 iL M2 Δ iL0 Ts 0 t Figure 14.14 Elimination of perturbation in the inductor current waveform in closed-inner loop during one cycle at M3 = M2 (dead-beat control). Figure 14.15 shows a boundary between the stable and unstable regions for the buck and buck–boost converters. The limiting value of the duty cycle for the buck and buck–boost converters is Dlim = 0.5 M 3 1 − V ∕L . (14.56) O 14.5.3 Boundary Slope Compensation for Boost Converter The maximum value of the inductor current on-slope corresponding to Dmax for the boost converters is M1min = VO (1 − Dmax ) . L (14.57) Hence, the critical value of slope compensation is VO (Dmax − 0.5) . (14.58) L Figure 14.16 shows a boundary between the stable and unstable regions for the boost converter. The limiting value of the duty cycle for the boost converter is M3cr = Dlim = 0.5 + M3 . VO ∕L (14.59) 14.6 Sample-and-Hold Effect on Current Loop Modeling the current-mode controlled converters involve discrete-time signals and nonlinear, time-varying (NTV) circuits. Operation of the closed-current loop is similar to that of sample-and-hold circuits. “Sampling” the analog, continuous-time control current iC (or control voltage vC ) occurs once in a switching cycle Ts at the instant when Current-Mode Control 571 0.5 0.4 / (V /L) Stable M 3cr O 0.3 0.2 Unstable 0.1 0 0.5 0.6 0.7 D 0.8 0.9 1 max Figure 14.15 Normalized critical slope compensation M3cr ∕(VO ∕L) as a function of the maximum duty cycle Dmax for the buck and buck–boost converters. This plot forms a boundary between stable and unstable regions. 0.5 0.4 0.3 M 3cr O / (V /L) Stable 0.2 Unstable 0.1 0 0.5 0.6 0.7 D 0.8 0.9 1 max Figure 14.16 Normalized critical slope compensation M3cr ∕(VO ∕L) as a function of the maximum duty cycle Dmax for the boost converter. This plot constitutes a boundary between stable and unstable regions. 572 Pulse-Width Modulated DC–DC Power Converters the inductor current iL reaches the control current iC , turning the switch off and setting the duty cycle for that switching cycle. Only the control current values at the sampling instants (i.e., sampled-data information) are used to control the inner loop. The changes in the inductor current waveform and the changes in the average values of the inductor current in successive cycles can be described by the zero-order-hold (ZOH) function. The waveforms of the duty cycle and changes in the duty cycle in successive cycles by their nature are “staircase” (or discrete in magnitude) functions and are similar to the waveforms in the ZOH circuit. Therefore, some waveforms in the current loop are discrete-time signals and can be described in the z-domain. Figure 14.17 shows the waveforms in the inner-current loop. A review of sample-and-hold modeling is given in the Appendix to this chapter. 14.6.1 Natural Response of Inductor Current to Small Perturbation in Closed-Current Loop The complete response of a system is equal to the sum of the natural response and the forced response. The natural response, also called initial condition response, zero-input response, or source-free response) is caused by energy stored in a system. The forced response, also called zero-state response, is the particular solution of the differential equation and the natural solution is the homogeneous solution. We will use this principle to derive the control voltage-to-inductor current transfer function of the closed-current loop, which describes how the inductor current il (k) depends on the control voltage vc (k). Figure 14.18(a) shows a natural response of the inductor current in the closed-current loop [31]. The zero-input response is obtained when all the inputs are identically zero. The zero-input response is zero if all initial conditions are zero. At t = kTs , a small perturbation in the inductor current iL is introduced when the control voltage with slope compensation remains unchanged and other perturbations are zero, that is, vi = 0 and io = 0. This perturbation causes propagation of inductor current changes over subsequent cycles. The sampling occurs at the intersections of waveforms Rs iL and vC − vA . The difference between the perturbed (transient) inductor current waveform iLtr and the steady-state inductor current waveform iLss is equal to the exact waveform of the small-signal inductor current il = iLtr − iLss , shown in Figure 14.18(b). The exact waveform of the small-signal inductor current il can be approximated by a continuous-time “staircase” function depicted in Figure 14.18(c), where the finite slope after the sampling instant t = kTs is replaced by an infinite slope. The difference between the exact and approximate waveforms is very small and can be neglected. The instantaneous inductor current changes can be seen as the average inductor current changes. The approximate waveform of the small-signal inductor current il is the same as the ZOH waveform. The time intervals between the sampling instants are not constant, but the differences between them are small enough to be neglected. Figure 14.19 shows an enlarged part of the natural response depicted in Figure 14.18(a). From geometry, M1 = tan 𝛼 = BC Δtk (14.60) M3 = tan 𝛾 = AB Δtk (14.61) and resulting in the small-signal component of the inductor current at the time of the perturbation t = kTs Rs iln (k) = −(AB + BC) = −(M1 + M3 )Δtk . (14.62) Similarly, M2 = tan 𝛽 = AC Δtk (14.63) Current-Mode Control iC , i − i , i C A L Δ i L1 Δ i L0 d1 Δ i L2 d2 0 DTs ( D + d1)Ts Ts ( 2 D _ d2 ) Ts 2DTs 2Ts t 0 DTs ( D + d1)Ts Ts ( 2 D _ d2 ) Ts 2DTs 2Ts t ic* il Δ i L1 0 Δ i L0 t Δ i L2 Δ i L1 il 0 0 Δ i L0 t Δ i L2 vGS 0 DTs ( D + d1)Ts Ts ( 2 D _ d2 ) Ts 2DTs 2Ts t d1 d 0 t d2 dT D + d1 D _ d2 0 DTs ( D + d1)Ts Figure 14.17 Ts ( 2 D _ d2 ) Ts 2DTs Waveforms in the inner-current loop. 2Ts t 573 574 Pulse-Width Modulated DC–DC Power Converters Δ t k +1 vC , Rs iL vC M1 Rs il −M3 −M2 Rs iL 0 t (a) il Ts′ 0 ( k +1)Ts k Ts t (b) il ( k +1)Ts k Ts 0 t Ts (c) Figure 14.18 Natural response (zero-input response or source-free response) of the inductor current in the closedcurrent loop. The zero-input response is obtained when all the inputs are identically zero. The zero-input response is zero if all initial conditions are zero. Waveforms of the inductor current in the inner-current loop after a small perturbation in the inductor current iL introduced at time t = kTs . (a) Waveforms of steady-state control voltage vC , steady-state normalized inductor current Rs iL (solid line), and perturbed (transient) normalized inductor current Rs (iL + il ) (dashed line). (b) Exact waveform of the difference between the steady-state and perturbed waveforms, resulting in a small-signal inductor current il . (c) Approximate waveform of the small-signal inductor current il . yielding the small-signal component of the inductor current after one cycle from the beginning of the perturbation t = (k + 1)Ts Rs iln (k + 1) = AC − AB = (M2 − M3 )Δtk . (14.64) Rs iln (k + 1) (M − M3 )Δtk M − M3 =− 2 =− 2 = −a Rs iln (k) (M1 + M3 )Δtk M1 + M3 (14.65) Thus, where M M M D 2 − M3 − M3 M − M3 M 1−D 1 a= 2 = 1 M1 = . M3 3 M1 + M3 1+ 1+ M1 (14.66) M1 Hence, the discrete-time natural response of the approximate small-signal inductor current from one sampling instant to the next is given by iln (k + 1) = −ailn (k). (14.67) Current-Mode Control 575 Rs iL , vC , vC vA Δt k vC γ M3 γ Rs iL α A B β vC vA C M2 M1 M1 M2 α β Rs il (k +1) Rs il (k) α kTs (k +1)Ts t vGS t Figure 14.19 Enlarged waveforms of natural response depicted in Figure 14.18(a). 14.6.2 Forced Response of Inductor Current to Step Change in Control Voltage in Closed-Current Loop Figure 14.20(a) illustrates a forced response (or zero-state response) of the inductor current to a step change in the control voltage in the closed-current loop [7, 31]. The zero-state response is due to an arbitrary input and it is obtained when all initial conditions are zero, that is, when the initial state is zero. At time t = kTs , there is a step change (a step perturbation) in the control voltage vC from VC to VC + vc , causing a perturbation in the inductor current waveform iL . It is assumed that the converter input voltage VI and the output voltage VO remain constant, which implies that the inductor rising slope M1 and the inductor falling slope M2 also remain constant. The sampling occurs at the intersection of the compensated control voltage waveform vC − vA and the voltage waveform Rs iL , proportional to the inductor current iL . Figure 14.21 the enlarged part of the forced response is shown in Figure 14.20(a). From geometry, M1 = tan 𝛼 = AB Δtk (14.68) M3 = tan 𝛾 = BC Δtk (14.69) and yielding the step change of the control voltage vc (k + 1) = AB + BC = (M1 + M3 )Δtk . (14.70) 576 Pulse-Width Modulated DC–DC Power Converters vC , Rs iL Δtk Δt k + 1 VC + vc −M3 Rs il M1 Rs iL −M 2 0 (a) il 0 (k +1)Ts k Ts t (b) il 0 k Ts t (k +1)Ts (c) Figure 14.20 Forced response of the inductor current in the closed-current loop. Waveforms of the control voltage and the inductor current in the inner-current loop after a step change in the control voltage vC from VC to VC + vc at time t = kTs , causing a perturbation of the inductor current iL . (a) Waveforms of control voltage vC = VC + vc , steady-state inductor current Rs iL (solid line), and perturbed normalized inductor current Rs (iL + il ) (dashed line). (b) Exact waveform of the difference between the steady-state and perturbed waveforms, resulting in a small-signal inductor current il . (c) Approximate waveform of the small-signal inductor current il . Likewise, M2 = tan 𝛽 = BD Δtk (14.71) producing the small-signal component of the inductor current after one cycle at t = (k + 1)Ts Rs ilf (k + 1) = AB + BD = (M1 + M2 )Δtk . (14.72) (M1 + M2 )Δtk+1 M − M3 M + M2 = 1 =1+ 2 = 1 + a. (M1 + M3 )Δtk+1 M1 + M3 M1 + M3 (14.73) Hence, Rs ilf (k + 1) vc (k + 1) = The discrete-time forced response is given by ilf (k + 1) = 1+a v (k + 1). Rs c (14.74) The total response is equal to the sum of the natural response and the forced response. The discrete-time relationship between the control voltage and the inductor current is [31] il (k + 1) = iln (k + 1) + ilf (k + 1) = −ail (k) + 1+a v (k + 1). Rs c (14.75) Current-Mode Control Rs iL ,vC, vC vA vC Δtk vC vA VC 577 vc (k + 1) γ M3 M3 A α γ Rs iL vc (k + 1) B C D β Rs il (k + 1) M1 α Rs il (k + 1) β kTs (k + 1) Ts t vGS t Figure 14.21 Enlarged waveforms of the forced response shown in Figure 14.20(a). 14.6.3 Relationship Between s-Domain and z-Domain The relationship between the s-plane and the z-plane is useful to understand the relationship between continuous and discrete systems. Using s = 𝜎 + j𝜔, the z-transform is defined as ( ) 𝜎 j2𝜋 f fs z = esTs = e(𝜎+j𝜔)Ts = e𝜎Ts ej𝜔Ts = e fs e { [ ( )] [ ( )]} 𝜎 f f + j sin 2𝜋 = rej𝜙 = r(cos 𝜙 + j sin 𝜙). = e fs cos 2𝜋 fs fs (14.76) 𝜎 This equation describes a circle with a radius r = |z| = e fs and 𝜙 = 𝜔Ts = 2𝜋f ∕fs . For Re {s} = 𝜎 = 0, |z| = r = 1, resulting in a unity circle. This circle constitutes the stability boundary, where the close-inner loop is marginally stable. For Re{s} = 𝜎 < 0, |z| = r < 1 and the closed-inner loop is stable. For Re {s} = 𝜎 > 0, |z| = r > 1 and the closed-inner loop is unstable. For example, the pole of a second-order polynomial of the form s2 + 2𝜉𝜔n s + 𝜔2n = 0 is √ (14.77) p1 = −𝜉𝜔n + j𝜔n 1 − 𝜉 2 , yielding z = esT = e−𝜉𝜔n T ej𝜔n T √ 1−𝜉 2 [ ( ) ( )] √ √ = e−𝜉𝜔n T cos 𝜔n T 1 − 𝜉 2 + j sin 𝜔n T 1 − 𝜉 2 . (14.78) 578 Pulse-Width Modulated DC–DC Power Converters 14.6.4 Transfer Function of Closed-Current Loop in z-Domain From the definition of the z-transform, the sampled inductor current in the z-domain is {il (k)} = il (z) = ∞ ∑ il (k)z−k = il (0) + il (1)z−1 + il (2)z−2 + ⋯ + il (k)z−k + ⋯ . (14.79) k=0 From the shifting theorem, {il (k + 1)} = zil (z) (14.80) {vc (k + 1)} = zvc (z). (14.81) and Hence, the z-transform of (14.75) is 1+a zvc (z) Rs (14.82) (1 + a)z vc (z). Rs (14.83) zil (z) = −ail (z) + which gives (z + a)il (z) = Thus, the discrete-time control voltage-to-inductor current transfer function of the closed-current loop is given by Hicl (z) = il (z) 1+a z 1+a z = = , vc (z) Rs z + a Rs z − p (14.84) where p = −a. Figure 14.22 shows the response of the inductor current to the step change in the control voltage ΔVC = vc = 0.1 V at a = 0.7. 3.55 iL0 iL 0 iL, iL (A) 3.5 3.45 3.4 3.35 Figure 14.22 0 20 40 t (μs) 60 80 100 Step response of the inductor current to a step change in the control voltage ΔVC = vc = 0.1 V at a = 0.7. Current-Mode Control Im il*(t) 1 x a 579 1 Re 0 t (a) Im a il*(t) 1 x 1 Re 0 t (b) il*(t) Im x a 1 1 Re 0 t (c) Figure 14.23 Locations of the pole p = −a of the discrete-time control voltage-to-inductor current transfer function Hicl (z) of the closed-current loop in the complex plane and sequence of samples. (a) For −1 < p < 0, the current loop is stable. (b) For p = −1, the current loop is marginally stable. (b) For −∞ < p < −1, the current loop is unstable. The transfer function Hicl (z) contains a pole p = −a. The following three locations of the pole are possible: (1) For a < 1, the discrete transfer function Hicl (z) has a pole located inside the unit circle as shown in Figure 14.23(a), and therefore the closed-current loop is stable. (2) For a = 1, the pole is located on the unit circle, as shown in Figure 14.23(b), resulting in the marginally stable current loop and the steady-state oscillations. (3) For a > 1, the discrete transfer function Hicl (z) has a pole located outside the unit circle as shown in Figure 14.23(c), and therefore the closed-current loop is unstable, causing growing oscillations of the inductor current at fs ∕2, called subharmonic oscillation. This situation takes place, for example, for M1 < M2 at M3 = 0, that is, for D > 0.5 and no ramp compensation. The margin of stability of discrete systems is determined by the belt margin BM or the ring margin defined as BM = 1 − amin = 1 − M2 − M3 M − M2 + 2M3 M − M3 = 1 =1− 2 . M1 + M3 M1 + M3 M1 + M3 (14.85) 580 Pulse-Width Modulated DC–DC Power Converters Im 1 BM x 1 a 1 0 Re 1 Figure 14.24 Margin of stability of discrete systems. where |a| corresponds to the required gain margin GM or the required phase margin PM. The belt margin BM for discrete systems is illustrated in Figure 14.24. 14.7 Closed-Loop Control Voltage-to-Inductor Current Transfer Function in s-Domain Figure 14.25 shows a block diagram for converting the closed-loop transfer function from the z-domain into the sdomain. The closed-loop discrete-time control voltage-to-inductor current transfer function Hicl (z) in the z-domain can be transformed to a continuous closed-loop control voltage-to-inductor current transfer function Hicl (s) in the s-domain. The transfer function of an ideal sampler can be approximated by Hs (s) = v∗c (s) vc (s) = 1 = fs . Ts (14.86) Using the definition of the z-transform z = esTs (which is the relationship between the z-domain and the sampledLaplace s-domain), the discrete closed-loop control voltage-to-inductor current transfer function is | i∗ (s) 1+a 1 + a esTs 1 | ∗ = = (s) = Hicl (z)| = l∗ . Hicl sTs + a −sTs | sTs v (s) R R e 1 + ae s s c |z=e (14.87) ∗ Figures 14.26 and 14.27 show Bode plots of Hicl (s). The ZOH transfer function (which is the relationship between the sampled-Laplace domain and the continuoustime domain) is given by i0 (s) 1 − e−sTs HZOH (s) = ∗l = . il (s) s v∗c (s) vc (s) ∗ (s) Hicl il∗(s) HZOH (s) (14.88) il0(s) ≈ il (s) Ts Figure 14.25 Block diagram for converting the closed-loop control voltage-to-inductor current transfer function from z-domain into s-domain. Current-Mode Control 581 1.45 1.4 1.35 icl | H* | 1.3 1.25 1.2 1.15 1.1 1.05 1 Figure 14.26 0 0.5 1 1.5 f / fs 2 2.5 3 Magnitude of closed-current loop |H∗icl | as a functions of f ∕fs for a = 0.1712 for a wide frequency range. 10 8 6 4 icl H ϕ * (°) 2 0 −2 −4 −6 −8 −10 Figure 14.27 0 0.5 1 1.5 f / fs 2 2.5 3 Phase of closed-current loop Hicl as a functions of f ∕fs for a = 0.1712 for a wide frequency range. 582 Pulse-Width Modulated DC–DC Power Converters 1.2 1 | Hicl | (A / V) 0.8 0.6 0.4 Exact Padé Modified Padé 0.2 0 −2 10 −1 10 0 f / fs 10 1 10 Figure 14.28 Exact and approximate plots of the magnitude of closed-current loop Hicl as a functions of f ∕fs for a = 0.1712 for a wide frequency range, using the second-order Padé and modified Padé approximations. The closed-current loop transfer function is given by Hicl (s) = = i0 (s) v∗ (s) i∗l (s) i (s) il (s) ∗ ≈ l = c × ∗ × ∗l = Hs (s)Hicl (s)HZOH (s) vc (s) vc (s) vc (s) vc (s) il (s) 1 − e−sTs 1 + a 1 − e−sTs 1 + a esTs − 1 1 1 + a esTs × = = × . Ts Rs esTs + a s Rs sTs esTs + a Rs sTs 1 + ae−sTs (14.89) Figures 14.28 and 14.29 show the magnitude and the phase of Hicl for a wide frequency range. Figures 14.30 and 14.31 depict exact and approximate Bode plots of Hicl as functions of f ∕fs at a = 0.1712 in linear scale. 14.7.1 Approximation of Hicl by Rational Transfer Function In PWM converters with peak CMC, the sampling frequency is equal to the switching frequency fs of the power stage. The transfer functions of the inner loop should be described accurately up to the Nyquist frequency fs ∕2, that is, in the frequency range of 0 ≤ f ≤ fs ∕2. In order to convert transfer functions from the z-domain to the s-domain, z is replaced by esTs , which leads to transfer functions that are not rational functions. Exact calculations of transfer functions with esTs terms can be made. To obtain rational transfer functions, approximations of esTs are required. A Taylor series approximation of esTs leads to transfer functions with zeroes and no poles, resulting in improper transfer functions. The transfer function is improper if m > n. The transfer function is a strictly proper function if the order of the denominator polynomial n is greater than the order of the numerator polynomial m (i.e., n > m). If n = m, the transfer function is a proper transfer function. To obtain strictly proper transfer functions, Padé approximations can be used. Current-Mode Control 583 0 −20 −40 −60 ϕ H icl (°) −80 −100 −120 Exact Padé Modified Padé −140 −160 −180 −2 10 −1 10 0 f / fs 1 10 10 Figure 14.29 Exact and approximate plots of the phase of closed-current loop Hicl as a functions of f ∕fs for a = 0.1712 for a wide frequency range, using the second-order Padé and modified Padé approximations. 1.2 Exact Padé Modified Padé 1 | Hicl | (A / V) 0.8 0.6 0.4 0.2 0 Figure 14.30 0 0.5 1 1.5 f / fs 2 2.5 3 Exact and approximate plots of the magnitude of Hicl as a functions of f ∕fs for a = 0.1712. 584 Pulse-Width Modulated DC–DC Power Converters 0 Exact Padé Modified Padé −20 −40 −60 ϕ H icl (°) −80 −100 −120 −140 −160 −180 Figure 14.31 0 0.5 1 1.5 f / fs 2 2.5 3 Exact and approximate plots of the phase of Hicl as a functions of f ∕fs for a = 0.1712. The transfer function in (14.89) is not a rational function, that is, it is not a ratio of two polynomials. Using the second-order Padé approximation, we obtain )2 ( s s s s2 √ sTs (sTs )2 1 + + 1 + 2f + 12f 2 𝜔s ∕𝜋 1 + 2 + 12 3𝜔s ∕𝜋 s s esTs ≈ = = (14.90) )2 . ( 2 2 sTs (sTs ) s s 1 − 2f + 12f 2 1 − 2 + 12 s s √ s 1 − 𝜔 ∕𝜋 + s 3𝜔s ∕𝜋 s Substitution of the second-order approximation of esTs given by (14.90) into (14.89) gives the control voltage-toinductor current transfer function of the closed-current loop approximated by a rational function [65] Hicl (s) = il (s) 1 1 1 1 = ≈ vc (s) Rs 1 + 1−a sTs + (sTs )2 Rs 1 + 1−a s + 1+a 2 = 1+a 2fs 12 𝜔2i 1 1 = 2 Rs s + 2𝜉i 𝜔i s + 𝜔2i Rs 1 𝜔i = √ 12fs2 = 12fs2 1 Rs s2 + 1−a 6fs s + 12f 2 1+a s ( )2 (14.91) 3𝜔s ≈ 0.5513 𝜔s 𝜋 (14.92) 2𝜉 1 + 𝜔i s + i where the corner frequency is s2 s 𝜔i √ 12fs = the damping factor is √ 𝜉i = 3 (1 − a) 2 1+a (14.93) Current-Mode Control 585 1.2 1 | (A / V) 0.8 |H icl 0.6 0.4 0.2 Exact Padé Modified Padé 0 −2 10 Figure 14.32 −1 0 10 f / fs 10 Exact and approximate plots of the magnitude of Hicl as a functions of f ∕fs for a = 0.1712. the quality factor is Qi = 1 1 = √ 2𝜉i 3 ( 1+a 1−a ) (14.94) and the poles are pi1 , pi2 = −𝜉i 𝜔i ± j𝜔i √ 1−a 3f ± j2 1 − 𝜉i2 = − 1+a s √ √ 3fs 1− 3 4 ( 1−a 1+a )2 . (14.95) Figures 14.32 and 14.33 show exact and approximate Bode plots of Hicl for a = 0.1712, using the second-order Padé and the second-order modified Padé approximations. Figure 14.34 shows √ √ 𝜉i as a function of a. As a increases from 0 to 1, 𝜉i decreases from 3∕2 ≈ 0.866 to 0 and Qi increases from 1∕ 3 ≈ 0.577 to ∞. Figure 14.35 shows the root locus of the closed-current-loop transfer function Hicl (s) at fs = 100 kHz when a increases from 0 to 10. For a < 1, a pair of complex conjugate poles is located in the LHP, which indicates that the inner-loop is stable. For a = 1, a pair of complex conjugate poles is located on the imaginary axis, which indicates that the inner loop is marginally stable. For a > 1, a pair of complex conjugate poles is located in the RHP, which indicates that the inner loop is unstable. Figures 14.36 and 14.37 show Bode plots of Hicl (s) for selected values of a at Rs = 1 Ω. The closed-loop gain of the inner loop Hicl (s) represents a second-order low-pass filter transfer function and depends only on fs , a, and Rs . At s = 0, Hiclo = Hicl (0) = 1 . Rs (14.96) Pulse-Width Modulated DC–DC Power Converters 0 −20 −40 −60 ϕ H icl (°) −80 −100 −120 −140 −160 Exact Padé Modified Padé −180 −2 10 Figure 14.33 −1 0 10 f / fs 10 Exact and approximate plots of the phase of Hicl as a functions of f ∕fs for a = 0.1712. 0.9 0.8 0.7 0.6 i 0.5 ξ 586 0.4 0.3 0.2 0.1 0 0 0.2 Figure 14.34 0.4 a 0.6 0.8 Damping factor 𝜉i as a function of a. 1 Current-Mode Control 587 400 300 200 j ω (krad/s) 100 0 −100 −200 −300 −400 −300 −100 0 σ (krad/s) 100 200 300 Root locus of the closed-current-loop transfer function Hicl (s) at fs = 100 kHz for variations of a from 0 25 a = 0.1 20 a = 0.5 a = 0.9 15 ⏐ Hicl ⏐ (dB A/V) Figure 14.35 to 10. −200 10 5 0 −5 −10 −15 −3 10 Figure 14.36 −2 10 −1 f / fs 10 Bode plot of the magnitude of Hicl for selected values of a. 0 10 588 Pulse-Width Modulated DC–DC Power Converters 0 −20 a = 0.1 a = 0.5 a = 0.9 −40 icl −80 ϕ H (°) −60 −100 −120 −140 −160 −180 −3 10 −2 10 Figure 14.37 −1 f / fs 10 0 10 Bode plot of the phase of Hicl for selected values of a. The maximally flat magnitude response of |Hicl | occurs for √ 3 (1 − a) 1 = √ 𝜉i = 2 1+a 2 resulting in the critical perturbation ratio, which produces the maximally flat magnitude |Hicl | √ √ 3− 2 acr = √ √ ≈ 0.1. 3+ 2 √ For a > 0.1, 𝜉 < 1∕ 2 and |Hicl | exhibits peaking. For a = 1, |Hicl | approaches ∞ at f ≈ fs ∕2. (14.97) (14.98) 14.7.2 Step Responses of Closed-Inner Loop Figures 14.38 through 14.40 show the responses of the inductor current to ΔVc = 0.1 V at a = 0.7, 1, and 1.2, respectively. As expected, the magnitude of the inductor current waveform decays at a = 0.7, has a constant amplitude at a = 1, and increases at a = 1.2. The current loop is stable for a = 0.7, is marginally stable for a = 1, and is unstable for a = 1.2. 14.8 Loop Gain of Current Loop 14.8.1 Loop Gain of Inner Loop in z-Domain Figure 14.41 shows a block diagram of the inner loop. The closed-loop transfer function in the z-domain is Hicl (z) = Tf (z) Tf (z) il (z) = = vc (z) 1 + Ti (z) 1 + Rs Tf (z) (14.99) Current-Mode Control 3.54 3.52 3.5 iL (A) 3.48 3.46 3.44 3.42 3.4 3.38 3.36 Figure 14.38 0 10 20 30 t (μs) 40 50 60 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 0.7. 3.6 3.55 iL (A) 3.5 3.45 3.4 3.35 Figure 14.39 0 10 20 30 t (μs) 40 50 60 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 1. 589 590 Pulse-Width Modulated DC–DC Power Converters 3.9 3.8 3.7 3.5 L i (A) 3.6 3.4 3.3 3.2 3.1 3 Figure 14.40 0 10 20 30 t (μs) 40 50 60 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 1.2. resulting the forward-path gain Tf (z) = ) ( Hicl (z) il (z) 1 z 1 = =− . 1+ vei (z) 1 − Rs Hicl (z) Rs a z−1 (14.100) 14.8.2 Loop Gain of Inner Loop in s-Domain The closed-loop transfer function in the s-domain is Hicl (s) = Tf (s) Tf (s) T (s)∕Rs il (s) = = = i vc (s) 1 + Ti (s) 1 + Rs Tf (s) 1 + Ti (s) (14.101) Hicl (s) il (s) = vei (s) 1 − Rs Hicl (s) (14.102) resulting in the forward-path gain Tf (s) = vei (s) + vc (s) Rs il (s) Tf (s) il (s) Ti (s) Rs Figure 14.41 Block diagram of the inner loop. Current-Mode Control 591 60 40 |Ti | (dB) 20 0 −20 −40 Exact Padé Modified Padé −60 −3 10 −2 −1 10 Figure 14.42 10 f / fs 0 1 10 10 Bode plot of the magnitude of the inner loop gain Ti at a = 0.1712. and the loop gain Ti (s) = Rs il (s) Rs Hicl (s) = Rs Tf (s) = . vei (s) 1 − Rs Hicl (s) (14.103) The loop gain of the current loop of all converters with peak CMC operating in CCM is Ti (s) = Hicl (s)Rs Rs il (s) (1 + a)(esTs − 1) = = . vei (s) 1 − Hicl (s)Rs sTs (esTs + a) − (1 + a)(esTs − 1) (14.104) Bode plots of the loop gain Ti of the inner loop are shown in Figures 14.42 through 14.45. Substituting (14.91) into (14.103), we obtain the loop gain of the inner loop in the form of rational transfer function for all PWM converters operating in CCM Ti (s) = 𝜔2i 𝜔2i 𝜔2i Rs il (s) = = = ( ) vei (s) s(s + 2𝜉i 𝜔i ) s(s + 𝜔sh ) 𝜔 s 1 + s sh = 𝜔sh 2f (1 + a) 𝜔1 1 1 = s = ( ) s 1+ s s(s + 𝜔sh ) 1−a s 1+ s (14.105) ( ) 3 1 − a√ 𝜔s = 3 𝜔i 𝜋 1+a (14.106) 12fs2 𝜔sh 𝜔sh where 𝜔sh = 2𝜉i 𝜔i = f1 = 1−a 1−a 6f = 1+a s 1+a 𝜔1 = 2𝜋 ( ) fs 1 + a fs ( 1 + a )2 = 𝜋 1−a 6 1−a (14.107) Pulse-Width Modulated DC–DC Power Converters 0 −30 i T ϕ (°) −60 −90 −120 −150 Exact Padé Modified Padé −180 −3 10 −2 −1 10 0 10 1 10 10 f / fs Figure 14.43 Bode plot of the phase of the inner loop gain Ti at a = 0.1712. 60 40 20 | T i | (dB) 592 0 −20 −40 Exact Padé Modified Padé −60 −3 10 −2 −1 10 10 0 10 f / fs Figure 14.44 Enlarged Bode plot of the magnitude of the inner loop gain Ti at a = 0.1712. Current-Mode Control 593 −90 −105 Ti ϕ (°) −120 −135 −150 −165 Exact Padé Modified Padé −180 −3 10 Figure 14.45 −2 −1 10 0 10 f / fs 10 Enlarged Bode plot of the phase of the inner loop gain at a = 0.1712. and 1−a 6f . (14.108) 1+a s The loop gain Ti is converter independent. For a = 0, psh = −6 fs . For a = 1, psh = 0. For a > 1, psh is located in the RHP. Figures 14.46 and 14.47 show Bode plots of the loop gain of inner loop Ti . The loop gain of the inner loop is independent of converter topology; it depends only on the switching frequency fs and a. One pole of Ti is located at the origin, and therefore the current-loop gain Ti behaves like the transfer function of an integrator. The location of the second pole psh = −𝜔sh is dependent on a. The second pole is located in the LHP, and the current loop is stable. For a = 1, the second pole is located at the origin and the current loop is marginally stable. For a > 1, the second pole is located in the RHP, and therefore the current loop is unstable. For a = 0, f1 = fs ∕𝜋. For a = 0.1712, f1 = 0.45 fs . For a = 0.5, f1 = (3∕𝜋)fs = 0.955 fs . For a = 0, fsh = 3fs ∕𝜋 = 0.955 fs . For a = 0.1712, fsh = 0.676 fs . For a = 0.5, fsh = 0.318 fs . For s = j𝜔, the loop gain of the inner loop becomes ( ) ( ) 𝜔1 f1 1 1 = −j = |Ti |ej𝜙Ti (14.109) Ti (j𝜔) = j𝜔 1 + j𝜔 f 1 + jf 𝜔 f psh = −𝜔sh = − sh where |Ti | = ( ) f1 √ f 3 1 = 2 ( )2 𝜋 1 + ff sh ( )2 fs √ f sh and 𝜙Ti = −90◦ − arctan ( 𝜔 𝜔sh ) = −180◦ + arctan (𝜔 ) sh 𝜔 1 + 𝜋92 1 ( )2 ( )2 1−a 1+a = −180◦ + arctan (14.110) fs f [ 3(1 − a) 𝜋(1 + a) ( )] fs . (14.111) f Pulse-Width Modulated DC–DC Power Converters 100 a = 0.1 a = 0.5 a = 0.9 80 60 20 i | T | (dB) 40 0 −20 −40 −60 −4 10 Figure 14.46 −3 10 −2 10 −1 f / fs 10 0 1 10 10 Bode plot of the magnitude of the current-loop gain Ti for selected values of a. −90 a = 0.1 a = 0.5 a = 0.9 −105 T i −120 ϕ (°) 594 −135 −150 −165 −180 −4 10 Figure 14.47 −3 10 −2 10 −1 f / fs 10 0 10 1 10 Bode plot of the phase of the current-loop gain Ti for selected values of a. Current-Mode Control 595 2 1.5 2 a=5 1 1 i Im {T ( jω)} 0.5 0 −0.5 −1 0.5 −1.5 −2 −2 0.2 −1.5 −1 Re {T ( jω)} 0 −0.5 0 i Figure 14.48 Nyquist plot of the loop gain of current loop Ti (j𝜔) at fs = 100 kHz for selected values of a. In the last equation, the trigonometric identity is used arctan x = ( ) 𝜋 1 − arctan . 2 x (14.112) Figure 14.48 shows Nyquist plots of the loop gain of current loop Ti (j𝜔) at fs = 100 kHz for selected values of a. It can be seen that the gain margin GM = ∞ at any value of a because the Nyquist plots never cross the negative part of the real axis Re{Ti (j𝜔)}. As a increases from 0 to 1, the phase margin PM decreases from 72◦ to 0◦ . For a > 1, the phase margin PM is negative. 14.9 Gain-Crossover Frequency of Inner Loop At the gain-crossover frequency fci , the magnitude of the current-loop gain becomes ( )2 ( )2 fs fs 3 3 1 1 |Ti (fci )| = 2 = = 1. √ √ 2 ( )2 ( )2 ( )2 fci f 𝜋 𝜋 ci fsh fs 9 1−a 1+ f 1 + 𝜋 2 1+a f ci (14.113) ci Hence, the normalized crossover frequency of the current loop is √ fci 2 1 = √ √ fs 𝜋 ( ) ( 1−a 1+a 2 + 1−a 1+a )4 . + 49 (14.114) 596 Pulse-Width Modulated DC–DC Power Converters 0.6 0.55 ci f /f s 0.5 0.45 0.4 0.35 0.3 0 0.2 0.4 Figure 14.49 0.6 a 0.8 1 Plot of fci ∕fs as a function of a. √ √ Figure 14.49 shows a plot of fci ∕fs as a function of a. For a = 0, fci ∕fs = 6∕(3 + 3)∕𝜋 = 0.3034. For a = 1, √ fci ∕fs = 3∕𝜋 ≈ 5513. The ratio of fci ∕fs at a = 1 is higher than 0.5, which was predicted in the time-domain analysis. This difference is caused by the second-order Padé approximation of esTs . 14.10 Phase Margin of Inner Loop The phase 𝜙Ti at the gain-crossover frequency fci is ( )] ( ) [ f 3(1 − a) fs 𝜙Ti (fci ) = −180◦ + arctan sh = −180◦ + arctan fci 𝜋(1 + a) fci √ √ ⎤ ⎡ ) ( ) ) ( ( 3 1−a 1−a 2 1 − a 4 4⎥ ◦ ⎢ . + + = −180 + arctan √ ⎢ 2 1+a 1+a 1+a 9⎥ ⎦ ⎣ The phase margin of the current loop is given by ⎡ ) ( 3 1−a PM = 180◦ + 𝜙Ti (fci ) = arctan ⎢ √ ⎢ 2 1+a ⎣ Hence, 3 tan PM = √ 2 ( 1−a 1+a ) √ ( 1−a 1+a √ ( 1−a 1+a √ )2 + ( √ ( )2 + 1−a 1+a )4 1−a 1+a 4 + . 9 )4 ⎤ 4 + ⎥. 9⎥ ⎦ (14.115) (14.116) (14.117) Current-Mode Control 597 1 0.9 0.8 0.7 a 0.6 0.5 0.4 0.3 0.2 0.1 0 Figure 14.50 0 10 20 30 40 PM (°) 50 60 70 80 Perturbation ratio a as a function of phase margin PM for the inner-current loop. Rearrangement of this equation gives the relationship between a and the phase margin PM √ 4 a= √ 4 9(1 + tan2 PM) − tan PM = 9(1 + tan2 PM) + tan PM M2 − M3 . M1 + M3 (14.118) For PM = 45◦ , the perturbation ratio is √ 4 a= √ 4 18 − 1 ≈ 0.344. (14.119) 18 + 1 For PM = 60◦ , the perturbation ratio is √ a= √ √ √ 2−1 1 = = √ ≈ 0.1716. √ √ 6+ 3 2+1 2 2+3 6− 3 (14.120) Figure 14.50 shows a plot of a as a function of PM. Once a is known for a given value of PM, the required amount of slope compensation can be calculated. Figure 14.51 shows the locations of the pole and belt margins BM for the phase margins PM = 45◦ and PM = 60◦ . The crossover frequency fci normalized with respect to the switching frequency fs as a function of the phase margin PM is given by √ 4 fci 1 + tan2 PM = √ √ fs 2 tan PM 1 . √ 4(1+tan2 PM) 1 + 1 + tan4 PM (14.121) 598 Pulse-Width Modulated DC–DC Power Converters PM = 0° 1 0.8 Im 0.6 ° 0.4 45 0.2 60° 0 −1 −0.35 −0.17 −1 −0.5 −0.2 −0.4 −0.6 −0.8 −1 Figure 14.51 0 Re 0.5 1 Belt margins at the phase margins PM = 0, PM = 45◦ , and PM = 60◦ . For the phase margin PM = 45◦ , fci 1 = √ ≈ 0.42. 4 fs 2 2 (14.122) fci 1 = √ ≈ 0.3536. fs 2 2 (14.123) For the phase margin PM = 60◦ , Figure 14.52 shows a plot of fci ∕fs as a function of PM. Figure 14.52 shows a plot of fci ∕fs as a function of phase margin PM for the current loop. 14.11 Maximum Duty Cycle for Converters Without Slope Compensation For PWM converters without slope compensation (M3 = 0), a = D∕(1 − D) and the maximum duty cycle for a given phase margin PM is Dmax = 1 tan PM a . = − √ 1 + a 2 2 4 9(1 + tan2 PM) (14.124) Figure 14.53 shows a plot of Dmax as a function of a. As a decreases from 1 to 0, Dmax decreases from 0.5 to 0. The maximum duty cycle Dmax as a function of the phase margin PM is shown in Figure 14.54. As PM increases from 0 to 72.5◦ , the maximum duty cycle Dmax decreases from 0.5 to 0. For PM = 45◦ , Dmax = 1 1 1 1 = − √ = 0.2576. − √ 2 2 4 9(1 + 1) 2 2 4 18 (14.125) Current-Mode Control 0.6 Padé Modified Padé 0.55 0.5 0.45 fci / f s 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 Figure 14.52 0 10 20 30 40 50 PM (°) 60 70 80 90 Normalized crossover frequency fci ∕fs a function of phase margin PM for the current loop. 0.5 0.4 Dmax 0.3 0.2 0.1 0 Figure 14.53 0 0.2 0.4 a 0.6 0.8 1 The maximum duty cycle Dmax as a function of a without slope compensation. 599 600 Pulse-Width Modulated DC–DC Power Converters 0.5 0.4 D max 0.3 0.2 0.1 0 Figure 14.54 0 10 20 30 40 PM (°) 50 60 70 80 The maximum duty cycle Dmax as a function of phase margin PM without slope compensation. For PM = 60◦ , √ 3 1 1 1 Dmax = = √ = − √ = 0.1465. 2 2 4 9(1 + 3) 2 2 2 (14.126) Thus, PWM converters without slope compensation may have sufficient degree of relative stability only at low values of duty cycle. 14.12 Maximum Duty Cycle for Converters with Slope Compensation Using (14.36), the normalized slope compensation is given by M 2 a D −a − a Dmax − a+1 M3 M1 1−D = = = M1 1+a 1+a 1 − Dmax (14.127) The minimum compensation slope occurs at the minimum on-slope of the inductor current and is given by a Dmax − a+1 M3min = . M1min 1 − Dmax (14.128) The maximum duty cycle is M a + (a + 1) M3min 1min Dmax = ( ). M3min (a + 1) 1 + M 1min (14.129) Current-Mode Control 601 1 M /M = 3 3 1 0.8 1 0.6 Dmax 0.5 0.4 0 0.2 0 Figure 14.55 0 0.2 0.4 a 0.6 0.8 1 The maximum duty cycle Dmax as a function of a at selected values of M3 ∕M1 . For a = 1, we obtain the duty cycle for the marginally stable converters M 1 + 2 M3 1 1 DMS = ( ) =1− ( ). M3 M 2 1+ M 2 1 + M3 1 (14.130) 1 Figure 14.55 shows Dmax as a function of a at fixed values of M3 ∕M1 . Plots of the maximum duty cycle Dmax as a function of M3 ∕M1 at selected values of a are depicted in Figure 14.56. Substitution of (14.118) into (14.129) produces Dmax = M3 + 0.5 M1 M3 +1 M1 ( − 2 M3 +1 M1 tan PM . )√ 4 9(1 + tan2 PM) (14.131) Figure 14.57 shows plots of Dmax as a function of relative compensation M3 ∕M1 at fixed values of phase margin PM. Plots of Dmax as a function of PM at fixed values of M3 ∕M1 are shown in Figure 14.58. From (14.131), one obtains the normalized slope compensation required for achieving the required phase margin at a given maximum duty cycle Dmax Dmax − 12 M3min = + M1min 1 − Dmax 2 (1 − D tan PM . )√ 4 9(1 + tan2 PM) max (14.132) Pulse-Width Modulated DC–DC Power Converters 0.9 0.8 a=1 0.7 Dmax 0.6 0.2 0.5 0 0.4 0.3 0.2 0.1 0 0 0.5 1 M /M 3 Figure 14.56 1.5 2 2.5 1 The maximum duty cycle Dmax as a function of M3 ∕M1 at selected values of a. 0.9 0.8 PM = 0° 0.7 45° max 0.6 D 602 60° 0.5 0.4 0.3 0.2 0.1 0 0.5 1 M /M 3 Figure 14.57 1.5 2 2.5 1 The maximum duty cycle Dmax as a function of M3 ∕M1 at selected values of phase margin PM. Current-Mode Control 603 1 M3/M1 = 3 0.8 1 max 0.6 D 0.5 0.4 0 0.2 0 Figure 14.58 0 10 20 30 40 50 PM (°) 60 70 80 90 The maximum duty cycle Dmax as a function of PM at selected values of M3 ∕M1 . The first term in this equation represents the required amount of slope compensation to achieve the marginal stability at a given Dmax and the second term represents the amount of slope compensation for achieving the required phase margin PM at a fixed value of Dmax . For PM = 45◦ , M3 1 = M1 1 − Dmax ) ( 1 1 Dmax − + √ 2 2 4 18 ≈= ( ) 1 Dmax − 0.2573 . 1 − Dmax (14.133) ≈= ( ) 1 Dmax − 0.1464 . 1 − Dmax (14.134) For PM = 60◦ , M3 1 = M1 1 − Dmax ) ( 1 1 Dmax − + √ 2 2 2 Figure 14.59 shows plots of the required amount of compensation M3 ∕M1 as a function of Dmax at selected values of phase margin PM. The normalized crossover frequency fci ∕fs as a function of the normalized slope compensation M3 ∕M1 is given by √ fci 2 1 1 = ( )√ √ M3 √ fs 𝜋 1 + 2M3 − 2D [ √ √ max 1 + M √ M1 √ 1 √1 + √1 + 4 2M3 9 ]4 . (14.135) 1 ( ) M 1+ M −2Dmax 1+ M3 1 1 Figure 14.60 shows plots of fci ∕fs as a function of M3 ∕M1 at fixed values of the maximum duty cycle Dmax . 604 Pulse-Width Modulated DC–DC Power Converters 3 2.5 3 M /M1 2 PM = 60° 1.5 45° 1 0° 0.5 0 0.5 0.6 0.7 D 0.8 0.9 1 max Figure 14.59 The required slope compensation M3 ∕M1 as a function of the maximum duty cycle Dmax at selected values of phase margin PM. 0.6 0.5 f /f ci s Dmax = 0.8 0.75 0.4 0.6 0.7 0.3 0.2 0.5 0.2 0.1 0 0 1 2 M3 / M1 3 4 5 Figure 14.60 Normalized crossover frequency fci ∕fs as a function of the normalized slope compensation M3 ∕M1 at selected values of the maximum duty cycle Dmax . Current-Mode Control 605 14.13 Minimum Slope Compensation for Buck and Buck–Boost Converter The dc voltage transfer function of the buck converter is MV DC = VO = D. VI (14.136) The rising slope of the inductor current for the buck converter is V (1 − D) VI − VO = O . (14.137) L LD Substitution of this equation into (14.132) yields the minimum slope compensation for the buck converter at a given phase margin PM of the inner loop M1 = M3min = VO Dmax − 0.5 VO + L Dmax L D tan PM = M3cr + M3PM . √ 4 2 max 1 + tan PM (14.138) The dc voltage transfer function of the buck–boost converter is MV DC = VO D . = VI 1−D (14.139) The rising slope of the inductor current for the buck–boost converter is V (1 − D) VI = O , (14.140) L LD which is the same as for the buck converter. Figure 14.61 shows plots of M3min ∕(VO ∕L) as a function of Dmax for the buck and boost converters. M1 = 1 PM = 60° 0.8 M 3min / (VO /L) 45° 0.6 30° 0.4 0° 0.2 0 0 0.2 0.4 D 0.6 0.8 1 max Figure 14.61 Normalized slope compensation M3min ∕(VO ∕L) as a function of the maximum duty cycle Dmax at selected values of the phase margin PM for the buck and buck–boost converters. 606 Pulse-Width Modulated DC–DC Power Converters Example 14.2 A buck converter has the following specifications: 16 V ≤ VI ≤ 24 V, VO = 10 V, 0.14 A ≤ IO ≤ 1.4 A, and fs = 100 kHz. The required phase margin is PM ≥ 60◦ . Calculate the compensation slope. Solution: The minimum, nominal, and maximum values of the duty cycle are VO 10 = 0.4167, = VImax 24 (14.141) Dnom = VO 10 = 0.5, = VInom 20 (14.142) Dmax = VO 10 = 0.625. = VImin 16 (14.143) VO 10 = 71.429 Ω. = IOmin 0.14 (14.144) Dmin = and The maximum load resistance is RLmax = The inductance required for CCM operation for the buck converter is RLmax (1 − Dmin ) 71.429 × (1 − 0.4167) = = 208.32 μH. 2fs 2 × 100 × 103 Lmin = (14.145) Pick a standard inductance L = 220 μH. The on-slope of the inductor current at VImin = 16 V, that is, at Dmax = 0.625, is given by VImin − VO 16 − 10 = = 27.3 A∕ms. L 220 × 10−6 The minimum normalized compensation slope to obtain PM = 0 at Dmax = 0.625 is M1min = M3PM0 D − 0.5 0.625 − 0.5 = 0.333. = max = M1min 1 − Dmax 1 − 0.625 (14.146) (14.147) Hence, the compensation slope to achieve PM = 0 at Dmax = 0.625 is M3PM0 = 0.333M1min = 0.333 × 27.3 = 9.0909 A∕ms. (14.148) The normalized compensation slope to obtain PM = 60◦ at Dmax = 0.625 is 0.625 − 0.5 tan 60◦ tan PM = = 1.2761. + √ √ 4 4 1 − 0.625 2 PM) 2 60◦ ) ) 2(1 − 0.625) 9(1 + tan 9(1 + tan max M3min Dmax − 0.5 = + M1min 1 − Dmax 2(1 − D (14.149) The slope of the compensating ramp current is M3min = 1.2761M1min = 1.2761 × 27.3 A∕ms = 34.84 A∕ms. (14.150) The amplitude of the control current ramp is IRamp = M3min 34.84 × 103 × 103 = = 0.3484 A. fs 105 (14.151) Assuming Rs = 1 Ω, the amplitude of the control voltage ramp is VAramp = Rs IAramp = 1 × 0.3484 = 0.3484 V. (14.152) Current-Mode Control 607 1 PM = 60° 0.8 30° 0.6 O M3min / (V /L) 45° 0° 0.4 0.2 0 0 0.2 0.4 D 0.6 0.8 1 max Figure 14.62 Normalized slope compensation M3min ∕(VO ∕L) as a function of the maximum duty cycle Dmax at selected values of the phase margin PM for the boost converter. 14.14 Minimum Slope Compensation for Boost Converter The dc voltage transfer function of the boost converter is MV DC = VO 1 = . VI 1−D (14.153) The rising slope of the inductor current for the boost converter is M1 = V (1 − D) VI = O . L L (14.154) Substitution of (14.154) into (14.132) produces the minimum slope compensation for the boost converter at a given phase margin PM of the inner loop M3min = VO V tan PM (Dmax − 0.5) + O √ = M3cr + M3PM . L L 4 1 + tan2 PM (14.155) Figure 14.62 shows plots of M3min ∕(VO ∕L) as a function of Dmax for the boost converter. Example 14.3 A boost converter has the following specifications: 100 V ≤ VI ≤ 200 V, VO = 400 V, 0.1 A ≤ IO ≤ 0.225 A, and fs = 100 kHz. The required phase margin is PM ≥ 60◦ . Calculate the compensation slope. 608 Pulse-Width Modulated DC–DC Power Converters Solution: The minimum, nominal, and maximum values of the duty cycle are VImax 200 = 0.5, =1− VO 400 (14.156) VInom 150 = 0.625, =1− VO 400 (14.157) VImin 100 =1− = 0.75. VO 400 (14.158) Dmin = 1 − Dnom = 1 − and Dmax = 1 − The maximum load resistance is RLmax = VO IOmin = 400 = 4 kΩ. 0.1 (14.159) The minimum inductance for CCM operation is Lmin = RLmax Dmin (1 − Dmin )2 4 × 103 × 0.5 × (1 − 0.5)2 = = 2.5 mH. 2fs 2 × 100 × 103 (14.160) Pick a standard inductance L = 2.7 mH. The on-slope of the inductor current at VImin = 100 V, that is, at Dmax = 0.75, is given by M1min = VImin 100 = = 37 A∕ms. L 2.7 × 10−3 (14.161) The minimum normalized compensation slope to obtain PM = 0 at Dmax = 0.75 is M3PM0 D − 0.5 0.75 − 0.5 = 1. = max = M1min 1 − Dmax 1 − 0.75 (14.162) Hence, the compensation slope to achieve PM = 0 at Dmax is M3MP0 = 1 × M1min = 1 × 37 = 37 A∕ms. (14.163) The normalized compensation slope to obtain PM = 60◦ at Dmax = 0.75 is 0.75 − 0.5 tan 60◦ tan PM = = 2.414. + √ √ 4 4 1 − 0.75 2 2(1 − 0.75) 9(1 + tan2 60◦ ) max ) 9(1 + tan PM) M3min D − 0.5 = max + M1min 1 − Dmax 2(1 − D (14.164) The slope of the compensating ramp current is M3min = 2.414M1min = 2.414 × 37 A∕ms = 89.318 A∕ms. (14.165) The amplitude of the ramp current is IAramp = M3min 89.318 × 103 = = 0.89318 A. fs 105 (14.166) Assuming Rs = 1 Ω, the compensating voltage ramp is VAramp = Rs IAramp = 1 × 0.89318 = 0.89318 V. (14.167) Current-Mode Control 609 Example 14.4 A buck–boost converter has the following specifications: 20 V ≤ VI ≤ 36 V, VO = 28 V, 1 A ≤ IO ≤ 2 A, and fs = 100 kHz. The required phase margin is PM ≥ 60◦ . Find the compensation slope. Solution: The minimum, nominal, and maximum values of the duty cycle are Dmin = VO 28 = = 0.4375, VImax + VO 36 + 28 (14.168) Dnom = VO 28 = 0.625, = VInom + VO 28 + 28 (14.169) VO 28 V = = 0.5833. VImin O 20 + 28 (14.170) VO 28 = 28 Ω. = IOmin 1 (14.171) and Dmax = The maximum load resistance is RLmax = The minimum inductance required for CCM operation of the buck–boost converter is Lmin = RLmax (1 − Dmin )2 28 × (1 − 0.4375)2 = = 44.29 μH. 2fs 2 × 100 × 103 (14.172) Pick L = 51 μH. The on-slope of the inductor current at VImin = 20 V, that is, at Dmax = 0.5833, is given by VImin 20 = = 392.15 A∕ms. L 51 × 10−6 The minimum normalized compensation slope to obtain PM = 0 is M1min = (14.173) M3PM0 D − 0.5 0.5833 − 0.5 = 0.2. = max = M1min 1 − Dmax 1 − 0.5833 (14.174) Hence, the compensation slope to achieve PM = 0 at Dmax is M3PM0 = 0.2M1min = 0.2 × 392.15 = 78.43 mA∕μs. (14.175) The normalized compensation slope to obtain PM = 60◦ at Dmax = 0.5833 is 0.5833 − 0.5 tan PM tan 60◦ = = 1.0485. + √ √ 4 4 1 − 0.5833 2 2 9(1 − 0.625)(1 + tan2 60◦ ) max ) 9(1 + tan PM) M3min Dmax − 0.5 = + M1min 1 − Dmax 2(1 − D (14.176) The slope of the compensating ramp current is M3min = 1.0485M1min = 1.0485 × 392.15 A∕ms = 411.16 A∕ms. (14.177) The amplitude of the control ramp current is IRamp = M3min 0.41112 = = 0.411 A. fs 105 (14.178) Assuming Rs = 1 Ω, the amplitude of the control ramp voltage is VAamp = Rs IRamp = 1 × 0.411 = 0.411 mV. (14.179) 610 Pulse-Width Modulated DC–DC Power Converters vc + vei d Tms Tpi vfi il Ti Rs (a) vc vc vA + + vA vei d Tms Tpi vfi il Ti Rs (b) Figure 14.63 Block diagram of the closed-current loop showing the transfer function from the control voltage-to-the inductor current il , used for determining Tms = d∕vei . No disturbances are present, that is, vi = 0 and io = 0. (a) Without slope compensation. (b) With slope compensation. 14.15 Error Voltage-to-Duty Cycle Transfer Function Figure 14.63 shows a block diagram of the closed-current loop with the inductor current il as an output. This loop will be used to find the error voltage-to-duty cycle transfer function Tms . Figure 14.64 shows a block diagram of the closed-current loop with the duty cycle d as an output. The duty cycle drives the duty cycle-to-output voltage transfer function Tp in the voltage loop. The control voltage-to-inductor current transfer function of the closed-current loop can be expressed by [65] Hicl (s) = Tms Tpi il (s) = . vc (s) 1 + Tms Tpi Rs vc vei + (14.180) d Tms vfi Ti il Rs Tpi (a) vc vc vA + vA vei + d Tms vfi Ti Rs il Tpi (b) Figure 14.64 Block diagram of the closed-current loop showing the transfer function from control voltage to the duty cycle d, as in actual converters. The disturbances are zero (i.e., vi = 0 and io = 0.) (a) Without slope compensation. (b) With slope compensation. Current-Mode Control 611 where the duty cycle-to-inductor current transfer function of the converter power stage is i (s) Tpi = l . d(s) (14.181) Equating the right-hand sides of (14.89) and (14.180), Hicl (s) = Tms Tpi = 1 + Tms Tpi Rs 1 + a esTs − 1 Rs sTs esTs + a (14.182) yields the sample-and-hold error voltage-to-duty cycle transfer function [65] Tms (s) = Hicl (s) d(s) 1 = = ( 1 vei (s) 1 − Rs Hicl (s) R T ) = −1 R H (s) s pi s [ Rs Tpi icl 1 sTs (esTs +a) −1 (1+a)(esTs −1) ]. (14.183) Using the second-order Padé approximation given by (14.90), one obtains [65] Tms (s) ≈ 12fs2 12fs2 ( ) = ) ( Rs Tpi s s + 𝜔sh Rs Tpi s s + 1−a 6f 1+a s (14.184) ( ) 3 1 − a√ 𝜔s = 3𝜔i 𝜋 1+a (14.185) where 𝜔sh = 1−a 1−a 6f = 1+a s 1+a and 1−a 6f . (14.186) 1+a s The sample-and-hold error voltage-to-duty cycle transfer can be also determined using the loop gain Ti psh = −𝜔sh = − Tms (s) = 12fs2 𝜔2i Ti d(s) = = = ). ( vei (s) Rs Tpi Rs Tpi s(s + 𝜔sh ) R T s s + 1−a 6f s pi 1+a (14.187) s Thus, the transfer function Tms is converter-dependent because it depends on Tpi . As a increases from 0 to 1, fsh decreases from 3fs ∕𝜋 to 0. Using the relationship, Tmsp (z) = {Tmsp (s)HZOH (s)} (14.188) and the substitution z = esTs , we obtain Tmsp (s, z) = 12fs2 12fs2 1 − e−sTs 1 = (1 − z−1 ) 2 . s Rs Tpi s(s + 𝜔sh ) Rs Tpi s (s + 𝜔sh ) (14.189) For high frequencies, Tpi (s) = M1 + M2 s (14.190) and (M1 + M2 )Ts . z−1 The transfer function Tms can be converted into the z-domain as { } 12fs2 12fs2 𝜔sh z−1 1 − e−𝜔sh Ts  = Tms (z) = . Rs (M1 + M2 )𝜔sh z s(s + 𝜔sh Rs (M1 + M2 )𝜔sh z − e−𝜔sh Ts Tpi (z) = (14.191) (14.192) 612 Pulse-Width Modulated DC–DC Power Converters 0.68 0.66 0.64 d, d 0 0.62 0.6 0.58 0.56 0.54 Figure 14.65 d d 0 20 40 60 t (μs) 80 0 100 Waveforms of d(t) and d 0 (t) as responses to a step change in the duty cycle from 0.55 to 0.65. The waveforms of the response to a step change in the duty cycle from 0.55 to 0.65 using a continuous function d(t) and and discrete-time function d0 (t) are illustrated in Figure 14.65. It will be shown in the subsequent chapters that the duty cycle-to-inductor current transfer function Tpi for simple transformerless PWM converters, such as buck, boost, and buck–boost converters, is expressed by the equation of the same form s + 𝜔zi1 i (s) = Tpix Tpi (s) = l . 2 d(s) s + 2𝜉𝜔0 s + 𝜔20 (14.193) For different converters, parameters Tpix , 𝜔zi1 , 𝜉, and 𝜔0 are described by different equations. The error voltage-to-duty cycle transfer function, which is equal to the forward gain of the current loop, is given by [65] Tms (s) = 12fs2 12fs2 d(s) ≈ ) = ) ( ( vei (s) R T s s + 1−a 6f Rs Tpi s s + 𝜔sh s pi = 1+a s ( ) 12fs2 s2 + 2𝜉𝜔0 s + 𝜔20 s2 + 2𝜉𝜔0 s + 𝜔20 = Tmsx 3 Rs Tpix s(s + 𝜔sh )(s + 𝜔zi1 ) s + (𝜔sh + 𝜔zi1 )s2 + 𝜔sh 𝜔zi1 s (14.194) where Tmsx = 12fs2 Rs Tpix . Figures 14.66 and 14.67 show Bode plots of Tms at various values of a. (14.195) Current-Mode Control 613 100 a = 0.1 a = 0.5 a = 0.9 80 40 |T ms | (dB/V) 60 20 0 −20 −4 10 Figure 14.66 values of a. −3 10 −2 10 −1 f / fs 10 0 1 10 10 Bode plot of the magnitude of the error voltage-to-duty cycle transfer function Tms for selected 0 −30 a = 0.1 a = 0.5 a = 0.9 ϕ T ms (°) −60 −90 −120 −150 −4 10 Figure 14.67 −3 10 −2 10 −1 f / fs 10 0 10 1 10 Bode plot of the phase of the error voltage-to-duty cycle transfer function Tms for selected values of a. 614 Pulse-Width Modulated DC–DC Power Converters The loop gain of the current loop is Ti (s) = 12fs2 12fs2 12fs2 𝜔1 1 1 1+a . = Tms Tpi Rs = ( = ( ( )= ) = 2fs )= 1−a s s vei (s) s(s + 𝜔 ) 1 − a s 1+ s sh s s + 1+a 6fs 𝜔sh s 1 + 𝜔 s 1+ 𝜔 𝜔sh sh sh (14.196) vfi (s) Substitution of (14.193) into (14.184) yields the normalized sample-and-hold transfer function for any basic converter ( ) 12fs2 s2 + 2𝜉𝜔0 s + 𝜔20 Tms (s) (14.197) ≈ Hsh (s) = Tm Rs Tm Tpix s(s + 𝜔sh )(s + 𝜔zi1 ) where Tm = fs ∕(M1 + M3 ). 14.16 Closed-Loop Control Voltage-to-Duty Cycle Transfer Function of Current Loop Figure 14.64 shows a block diagram of the closed-current loop with the duty cycle as an output, as it is the case in actual converters. Using (14.196), the control voltage-to-duty cycle transfer function of the closed-current loop is Ticl (s) = Tms T Tms d(s) = = ms = 12fs2 vc (s) 1 + Tms Tpi Rs 1 + Ti 1+ s(s+𝜔sh ) = Tms s(s + 𝜔sh ) . 2 s + 𝜔sh s + 12fs2 (14.198) Substitution of (14.184) into this equation yields ( ) 12fs2 s2 + 2𝜉𝜔0 s + 𝜔20 Ticl (s) = [ ] = ( ) Rs Tpi s(s + 𝜔sh ) + 12fs2 Rs Tpix s2 + 𝜔sh s + 12fs2 (s + 𝜔zi1 ) (2 ) s + 2𝜉𝜔0 s + 𝜔20 s2 + 2𝜉𝜔0 s + 𝜔20 = Ticlx ( = Ticlx ( ) ) 3 s + (𝜔sh + 𝜔zi1 )s2 + 12fs2 + 𝜔sh 𝜔zi1 s + 12fs2 𝜔zi1 2 (s + 𝜔 ) s2 + 1−a 6f s + 12f s zi1 s 1+a 12fs2 (14.199) where Ticlx = 12 fs2 Rs Tpix . (14.200) The two poles of Ticl are √ √ ( ) √ 1−a 3 1−a 2 2 pi1 , pi2 = −𝜉i 𝜔i ± j𝜔i 1 − 𝜉i = − . 3 fs ± j2 3 fs 1 − 1+a 4 1+a (14.201) The closed-current loop transfer function depends on converter topology, slope compensation, and samplingand-hold effect. Figures 14.68 and 14.69 show Bode plots of Ticl over a wide frequency range for a = 0.1712. Figures 14.70 and 14.71 show these same plots over a narrow frequency range. Figures 14.72 and 14.73 show Bode plots for the closed-current loop Ticl at selected values of a for a buck–boost converter as an example. It can be seen that the magnitude of Ticl exhibits peaking at fs ∕2 for a = 0.5 and 0.9. For a = 1, |Ticl | approaches infinity at f = fs ∕2. For a > 1, Ticl has two poles in the RHP, making the current loop unstable. The phase 𝜙Ticl has positive values close to 90◦ at high frequencies, and therefore the closed-current loop acts like a partial lead compensator for the outer voltage loop, helping to offset the negative phase of Tp introduced, for example, by the RHP zero for the boost and buck–boost converters, which are non-minimal phase circuits. Alternatively, the positive phase 𝜙Ticl of the closed-current loop may partially offset the negative phase introduced by the poles in all converters, for example, a buck converter. Current-Mode Control 615 30 25 Exact Padé Modified Padé 15 10 |T icl | (dB/V) 20 5 0 −5 −10 −3 10 Figure 14.68 −2 10 −1 10 f / fs 0 10 1 10 Bode plot of the magnitude of the closed-current loop Ticl (s) for the buck PWM converter at 0.1712. 90 60 0 ϕ T icl (°) 30 −30 −60 −90 −3 10 Figure 14.69 Exact Padé Modified Padé −2 10 −1 10 f / fs 0 10 1 10 Bode plot of the phase of the closed-current loop Ticl (s) for the buck PWM converter at a = 0.1712. 616 Pulse-Width Modulated DC–DC Power Converters 30 25 Exact Padé Modified Padé 15 10 icl | T | (dB/ V) 20 5 0 −5 −10 −3 10 −2 10 −1 f / fs 10 0 10 Bode plot of the magnitude of the closed-current loop Ticl (s) for the buck converter at a = 0.1712. Figure 14.70 90 60 0 ϕ T icl (°) 30 −30 −60 −90 −3 10 Figure 14.71 Exact Padé Modified Padé −2 10 −1 f / fs 10 0 10 Bode plot of the phase of the closed-current loop Ticl (s) for the buck converter at a = 0.1712. Current-Mode Control 50 a = 0.1 a = 0.5 a = 0.9 40 | Ticl | (dB/ V) 30 20 10 0 −10 −20 −4 10 −3 10 −2 10 −1 f / fs 10 0 10 1 10 Bode plot of the magnitude of the closed-current loop Ticl (s) for selected values of a. Figure 14.72 90 a = 0.1 a = 0.5 a = 0.9 60 (°) 30 ϕ T icl 0 −30 −60 −90 −4 10 Figure 14.73 −3 10 −2 10 −1 f / fs 10 0 10 1 10 Bode plot of the phase of the closed-current loop Ticl (s) for selected values of a. 617 618 Pulse-Width Modulated DC–DC Power Converters vc Figure 14.74 14.17 il H icl 1 Tpi d Block diagram for the alternative representation of Ticl . Alternative Representation of Current Loop An alternative method of representation of current loop is shown in Figure 14.74. The closed-loop transfer function of the current loop is ( ) 12fs2 s2 + 2𝜉𝜔0 s + 𝜔20 il (s) d(s) d(s) 1 = × = Hicl (s) × = Ticl (s) = ( ) vc (s) vc (s) il (s) Tpi (s) Rs Tpix s2 + 𝜔sh s + 12fs2 (s + 𝜔zi1 ) (2 ) s + 2𝜉𝜔0 s + 𝜔20 . (14.202) = Ticlx ( ) 2 (s + 𝜔 ) 6f s + 12f s2 + 1−a s zi1 s 1+a 14.18 Current Loop with Disturbances Figure 14.75 depicts a block diagram of the current loop with disturbances by the input voltage vi and the load current io . Figure 14.76 shows block diagram for determining the transfer function from the input voltage to the duty cycle for the closed-current loop. The inductor current is given by il = il ′ + il ′′ = Tpi d + Mvi vi (14.203) d = Tms (−Rs il ) = −Tms Rs Tpi d − Tms Rs Mvi vi (14.204) and the duty cycle is vc vc vA + vei + vA Tms Ti Rs il + + M vi + vi ~ + vi ~ il′ Tpi il′′′ il′′ Figure 14.75 d Rs il Ai io Block diagram of current loop with disturbances. Mvi il′′ + + il il′ Rs Rs il Tms d Tpi Figure 14.76 loop. Block diagram for determining the input voltage-to-duty cycle transfer function Mvd for the closed-current Current-Mode Control il′′ Ai io il Rs i l′ + Rs il Tms 619 d Tpi Figure 14.77 loop. Block diagram for determining the load-current-to-duty cycle transfer function Aid for the closed-current resulting in d(1 + Tms Rs Tpi ) = −Tms Rs Mvi vi . (14.205) Hence, the input voltage-to-duty cycle transfer function is RT M d(s) || Mvd (s) ≡ = − s ms vi . | vi (s) ||v =i =0 1 + Ti c o (14.206) Figure 14.77 shows a block diagram for determining the transfer function from the load current to the duty cycle for the closed-current loop. From this block diagram, we obtain the inductor current il = i′l − il ′′ = Tpi d − Ai io (14.207) d = −Tms Rs il = −Tms Rs Tpi d + Tms Rs Ai io (14.208) d(1 + Tms Rs Tpi ) = Tms Rs Ai io . (14.209) and the duty cycle yielding Hence, we obtain the load current-to-duty cycle transfer function RT A d(s) || Aid (s) ≡ = s ms i . | io (s) ||v =v =0 1 + Ti c i (14.210) 14.18.1 Modified Approximation of Current Loop A modified Padé approximation [31] can be obtained by placing the corner frequency fh at half the switching frequency fs , yielding ( ) ( )2 2 1 s s sT (sT )2 1 − 2∕𝜋 + 1 − 2fs + (𝜋fs )2 1 − 2 s + 𝜋s2 𝜔 ∕2 𝜔 ∕2 s s s s e−sTs ≈ = . (14.211) ( ) ( )2 = s s2 sTs (sTs )2 1 s s 1 + + 1 + + 2 1 + 2∕𝜋 𝜔 ∕2 + 𝜔 ∕2 2fs (𝜋fs ) 2 𝜋2 s s Hence, (14.89) becomes Hiclm (s) = = il (s) 1 ≈ vc (s) Rs 1 1 + 1−a 1+a 2∕𝜋 ( 1 s 𝜔s ∕2 ) ( + s 𝜔s ∕2 1 )2 = R 𝜋 1−a 𝜔 s + (𝜔s ∕2)2 s s2 + 4 1+a s 𝜔2h 𝜋 2 fs2 1 1 = Rs s2 + 𝜋 2 fs 1−a s + 𝜋 2 f 2 Rs s2 + 2𝜉h 𝜔h s + 𝜔2h 2 1+a s (𝜔s ∕2)2 (14.212) 620 Pulse-Width Modulated DC–DC Power Converters where 𝜔s = 𝜋fs 2 ( ) 𝜋 1−a 𝜉h = 4 1+a ( ) 2 1+a Qh = 𝜋 1−a 𝜔h = (14.213) (14.214) (14.215) and √ √ ( ) 𝜋 2 fs 1 − a 𝜋2 1 − 𝛼 2 2 ± j𝜋fs 1 − p1 , p2 = −𝜔h 𝜉h ± j𝜔h 1 − 𝜉h = − . 4 1+a 16 1 + 𝛼 Substitution of (14.211) into (14.183) gives the normalized sample-and-hold transfer function Hshm (s) ≈ (14.216) 𝜋 2 fs2 𝜋 2 fs2 = ( ) 2 Rs Tm Tpi s(s + 𝜔shm ) Rs Tm Tpi s s + 𝜋2 1−a f 1+a s (14.217) where ( ) ( ) 𝜋2 1 − a 𝜋 1−a 𝜋 1−a fs = 𝜔s = 𝜔 . 2 1+a 4 1+a 2 1+a h The normalized sample-and-hold transfer function for any converter is obtained as ( ) 𝜋 2 fs2 s2 + 2𝜉𝜔0 s + 𝜔20 Hsh (s) ≈ . Rs Tm Tpix s(s + 𝜔zi1 )(s + 𝜔shm ) 𝜔shm = (14.218) (14.219) The error voltage-to-duty cycle transfer function of the current loop is ( ) 𝜋 2 fs2 s2 + 2𝜉𝜔0 s + 𝜔20 d(s) Tms (s) = ≈ . vei (s) Rs Tpix s(s + 𝜔zi1 )(s + 𝜔shm ) (14.220) The loop gain of the current loop is given by Tim (s) = 𝜋 2 fs2 𝜋 2 fs2 𝜋 2 fs2 = Tms Tpi Rs ≈ ( = = ( ) ) ). ( 𝜋2 s vei (s) s s + 𝜔shm s s + 1−a f 𝜔 s 1 + sh 1+a 2 s 𝜔 vfi (s) (14.221) sh The magnitude of the current-loop gain is |Tim | = 𝜋 2 fs2 1 1 = √ 𝜔 4 2 𝜔2 + 𝜔shm ( )2 fs √ f 1 ( 1+ fshm f )2 = 1 4 ( )2 fs √ f 1 . ( )2 ( )2 4 1 + 𝜋16 1−a 1+a At the crossover frequency fcim , the magnitude of the current-loop gain becomes ( ( ) ) fs 2 fs 2 1 1 1 1 = = 1. |Tim (fcim )| = √ √ ( )2 ( )2 ( )2 4 fcim 4 f cim fsh fs 𝜋4 1−a 1+ f 1 + 16 1+a f cim (14.222) fs f (14.223) cim Thus, the normalized crossover frequency of the current loop is fcim 1 . = √ √ ( ) fs ( ) 2 4 2 4 2 𝜋8 1−a + 𝜋64 1−a +1 1+a 1+a (14.224) Current-Mode Control 621 0.6 fci / fs fcim / fs 0.55 ci f / fs , fcim / fs 0.5 0.45 0.4 0.35 0.3 0.25 0 0.2 Figure 14.78 0.4 0.6 a 0.8 1 Crossover frequencies fci ∕fs and fcim ∕fs as functions of a. For a = 1, fcim ∕fs = 1∕2, the current loop is unstable, and it oscillates at half of the switching frequency, as predicted in the time domain. Figure 14.78 shows plots of fci ∕fs and fcim ∕fs . As a increases from 0 to 1, fcim ∕fs increases from 0.3 to 0.5. The phase of the current-loop gain is 𝜙Ti = −90◦ − arctan ( 𝜔 𝜔shm ) = −180◦ + arctan (𝜔 shm ) = −180◦ + arctan 𝜔 [ 𝜋(1 − a) 4(1 + a) ( )] fs . f (14.225) The phase 𝜙Ti at the crossover frequency fcim is 𝜙Ti (fcim ) = −180◦ + arctan ( fshm fci ) = −180◦ + arctan ⎡ 𝜋(1 − a) = −180◦ + arctan ⎢ ⎢ 2(1 + a) ⎣ √ 𝜋2 8 ( 1−a 1+a [ √ )2 ( 𝜋(1 − a) 4(1 + a) + 𝜋4 64 ( )] fs fcim 1−a 1+a )4 ⎤ + 1⎥ . ⎥ ⎦ (14.226) The phase margin of the current loop is defined as PM = 180◦ + 𝜙Ti (fcim ). (14.227) Thus, √ 𝜋(1 − a) tan PM = 2(1 + a) 𝜋2 2 ( 1−a 1+a √ )2 + 𝜋4 4 ( 1−a 1+a )4 +1 (14.228) 622 Pulse-Width Modulated DC–DC Power Converters 1 Original Padé approximation Modified approximation 0.8 a 0.6 0.4 0.2 0 −0.2 Figure 14.79 0 10 20 30 40 PM (°) 50 60 70 80 a as a function of phase margin PM for the Padé approximation and for modified approximation. yielding the relationship between a and PM √ 4 1 + tan2 PM − 𝜋2 tan PM . a= √ 4 1 + tan2 PM + 𝜋2 tan PM (14.229) Figure 14.79 shows a as a function of PM for the Padé approximation and for modified approximation. The location of the pole is shown in Figure 14.80 for PM = 45◦ and PM = 60◦ . The maximum duty cycle Dmax as a function of the relative slope compensation M3 ∕M1 at a given phase margin PM is Dmax = M3 + 0.5 M1 M3 +1 M1 − 𝜋 ( tan PM . )√ 4 1 + tan2 PM M3 +1 M1 (14.230) Figure 14.81 shows plots of Dmax as a function of M3 ∕M1 at selected values of the phase margin PM. The required normalized slope compensation M3 ∕M1 for achieving a given maximum duty cycle Dmax at a desired phase margin PM is tan PM √ Dmax − 0.5 + 4 M3 𝜋 1+tan2 PM = . M1 1 − Dmax (14.231) Figure 14.82 shows plots of M3 ∕M1 as a function of Dmax at selected values of phase margin PM. The normalized slope compensation required for achieving a sufficient phase margin PM at a given maximum duty cycle Dmax is Dmax − 12 M3 tan PM = + . √ M1 1 − Dmax 𝜋 (1 − D ) 4 1 + tan2 PM max (14.232) Current-Mode Control 623 PM = 0° 1 0.8 Im 0.6 0.4 45° 0.2 60° 0 −1 −0.3 −0.12 −0.2 −0.4 −0.6 −0.8 −1 −1 Figure 14.80 −0.5 0 Re 0.5 1 Location of the pole for phase margin PM = 0, PM = 45◦ , and PM = 60◦ using the Padé approximation. 0.9 0.8 PM = 0° 0.7 D max 0.6 45° 60° 0.5 0.4 0.3 0.2 0.1 Figure 14.81 0 0.5 1 M3 /M1 1.5 2 2.5 Maximum duty cycle Dmax as a function M3 ∕M1 at selected values of phase margin PM. 624 Pulse-Width Modulated DC–DC Power Converters 3 2.5 2 3 M /M 1 PM = 60° 1.5 45° 1 0° 0.5 0 0.5 Figure 14.82 0.6 0.7 Dmax 0.8 0.9 1 M3 ∕M1 as a function of maximum duty cycle Dmax at selected values of phase margin PM. The first term represents the required compensation to achieve the marginal stability at a desired maximum duty cycle Dmax and the second term represents the required slope compensation to achieve the desired phase margin PM at a given maximum duty cycle Dmax . The normalized crossover frequency fcim ∕fc as a function of the slope compensation M3 ∕M1 is given by √ fcim 2 1 1 = ( )√ √ M3 √ fs 𝜋 1 + 2M3 − 2D [ √ √ max 1 + M √ M1 √ 1 √1 + √1 + 64 2M3 𝜋2 ]4 . (14.233) 1 ( ) M 1+ M −2Dmax 1+ M3 1 1 The control voltage-to-duty cycle transfer function of the closed-current loop is given by ( ) 𝜋 2 fs2 s2 + 2𝜉𝜔0 s + 𝜔20 Hm (s) . Ticlm (s) = = ( ) Tpi (s) Rs Tpix s2 + 𝜔shm s + 𝜋 2 fs2 (s + 𝜔zi1 ) 14.19 (14.234) Voltage Loop of PWM Converters with Current-Mode Control 14.19.1 Control-to-Output Transfer Function for Buck Converter Block diagrams for determining the control-to-output transfer function of the buck converter are shown in Figure 14.83. In general, the output signal of the closed-current loop is il . In the buck converter, the inductor Current-Mode Control vei + vc il Tf Rs il Z2 Ti il Rs 625 (a) vc il Hicl vo Z2 (b) Figure 14.83 Block diagram for determining the control-to-output transfer function Tco for the buck converter. (a) Block diagram. (b) Simplified block diagram. current flows into the output circuit C–rC –RL . The impedance of the output filter of the buck converter is ( ) 1 + r R ( ) L C RL rC s + 𝜔z v (s) sC 1 = RL || + rC = = (14.235) Z2 (s) = o 1 il (s) sC RL + rC s + 𝜔zi RL + rC + sC where 𝜔zi = 1 (RL + rC )C (14.236) 1 . rC C (14.237) and 𝜔z = The control-to-output transfer function for the buck converter is Tco (s) = RL rC 𝜔2h s + 𝜔z vo (s) i (s) vo (s) = l = Hicl (s)Z2 (s) = ( ) vc (s) vc (s) il (s) Rs (RL + rC ) s2 + 𝜔sh s + 𝜔2i (s + 𝜔zi ) where 𝜔sh = 1−a 1−a 6f = 1+a s 1+a 𝜔i = √ ( ) 3 𝜔s 𝜋 (14.239) 12 fs and √ 1−a pi1 , pi2 = − 3 fs ± j2 3 fs 1+a (14.238) (14.240) √ 1− 3 4 ( 1−a 1+a )2 . (14.241) At low frequencies, Tco (0) = RL . Rs (14.242) Figures 14.84 and 14.85 show plots of the magnitude and phase of the control-to-output transfer function for the buck converter with D = 0.5, L = 256 μH, rL = 36 mΩ, C = 68 μF, rC = 0.52 mΩ, RL = 10 Ω, and r = 0.286 mΩ at selected values of perturbation ratio a. Pulse-Width Modulated DC–DC Power Converters 25 20 15 co | T | (dB) 10 5 0 −5 −10 −15 a = 0.95 a = 0.5 a = 0.29 −20 −25 1 10 Figure 14.84 10 2 3 10 f (Hz) 4 5 10 10 Magnitude of the control-to-output transfer function Tco for the buck converter. 20 0 −20 −40 Tco (°) −60 −80 ϕ 626 −100 −120 −140 −160 −180 1 10 Figure 14.85 a = 0.95 a = 0.5 a = 0.29 10 2 3 10 f (Hz) 4 10 10 5 Phase of the control-to-output transfer function Tco for the buck converter. Current-Mode Control 627 Ai Mvi il ′′ + il′′′ + il′ il Tpi Zo io + vi Mv vo′′′ + vo′ ~ d Figure 14.86 vo′′ + vo Tp Block diagram of the power stage of PWM converters. 14.19.2 Block Diagram of Power Stages of PWM Converters Figure 14.86 shows a block diagram of open-loop PWM converters. Figure 14.87 shows a block diagram of PWM converters with CMC without feedforward gains, where il is the small-signal component of the average inductor current, Tpi = il ∕d is the open-loop duty cycle-to-inductor current transfer function, Mvi = il ∕vi is the open-loop input voltage-to-inductor current transfer function, Tp = vo ∕d is the open-loop duty cycle-to-output voltage transfer function, and Mv = vo ∕vi is the open-loop input voltage-to-output voltage transfer function. Figure 14.87 shows a block diagram of PWM converters with CMC without feedforward gains, where Tc = vc ∕ve is the voltage transfer function of the control circuit. Figure 14.88 depicts a block diagram of PWM converters with peak CMC for the critical paths only without disturbances, that is, for vi and io = 0, where the peak inductor Zo io Ai + vr ~ ve vf Tc vc vi ~ vei + vfi Rs Tms il′′′ d Mv + + Tp vo Ti il + + il′ + il′′ Tpi T Mvi β Figure 14.87 Current-mode control block diagram of PWM converters without feedforward gains. 628 Pulse-Width Modulated DC–DC Power Converters vi = 0 and io = 0 + ve vf vr ~ vc Tc + vei d Tms vfi Tp vo Ti il Rs Tpi T β Figure 14.88 and io = 0. Block diagram for the critical path of closed-loop PWM converters with current-mode control at vi = 0 current is controlled along with the output voltage. The current loop Ti controls the peak inductor current and the voltage loop T controls the output voltage. 14.19.3 Closed-Voltage Loop Transfer Function of PWM Converters with Current-Mode Control The closed-loop transfer function from the reference voltage vr to the output voltage vo is Tcl ≡ Tc Ticl Tp vo || = . | vr ||v =i =0 1 + Tc Ticl Tp 𝛽 i (14.243) o 14.19.4 Closed-Loop Audio Susceptibility of PWM Converters with Current-Mode Control Figure 14.89 shows a block diagram for determining the closed-loop audio susceptibility, which can be obtained by setting vr = 0 and io = 0. The derivation of this transfer function is as follows: i′l = Tpi d (14.244) i′′l = Mvi vi (14.245) vi ve = vf + vr = 0 vf Tc vc vei + d Tms vfi Rs ~ Mv Tp vo′ + vo′′ + vo il′ il + Tpi + il′′ Mvi β Figure 14.89 Block diagram of PWM converters with current-mode control for determining the closed-loop audio susceptibility. Current-Mode Control 629 il = i′l + i′′l = Tpi d + Mvi vi (14.246) vfi = Rs il = Rs Tpi d + Rs Mvi vi (14.247) vei = vc − vfi = vc − Rs Tpi d − Rs Mvi vi (14.248) vf = 𝛽vo (14.249) ve = −vf = −𝛽vo (14.250) vc = Tc ve = −𝛽Tc vo (14.251) vei = vc − vfi = −𝛽Tc vo − Rs Tpi d − Rs Mvi vi (14.252) d = Tms vei = −𝛽Tc Tms vo − Rs Tpi Tms d − Rs Mvi Tms vi (14.253) d=− 𝛽Tc Tms Rs Mvi Tms vo − v 1 + Rs Tpi Tms 1 + Rs Tpi Tms i v′o = Tp d = − 𝛽Tc Tms Tp 1 + Rs Tpi Tms vo − Rs Mvi Tms Tp v 1 + Rs Tpi Tms i v′′o = Mv vi vo = v′o + v′′o = − 𝛽Tc Tms Tp Rs Mvi Tms Tp v − v + Mv vi 1 + Rs Tpi Tms o 1 + Rs Tpi Tms i (14.254) (14.255) (14.256) (14.257) vo (1 + Ti + Tv ) = [Mv + Ti Mv − Rs Tms Tp Mvi ]vi (14.258) vo (1 + Ti + Tv ) = [Mv + Ti Mv − Tms Tpi Rs Tp Mvi ∕Tpi ]vi (14.259) vo (1 + Ti + Tv ) = [Mv + Ti (Mv − Ti Tp Mvi ∕Tpi )]vi (14.260) Tv = Tc Tms Tp 𝛽. (14.261) where Finally, the closed-loop audio susceptibility is given by ( ) M M Mv + Tp Ti T v − T vi | + T M − R T T M M v | v i v s ms p vi p pi = = . Mvcl ≡ o | vi ||v =i =0 1 + Ti + Tv 1 + Ti + Tv r o (14.262) The derivation of an expression for the audio susceptibility for the inner loop only with the outer loop open and vc = 0 is as follows: vei = −vfi = −Rs Tpi d − Rs Mvi vi (14.263) d = Tms vei = −Rs Tms Tpi d − Rs Tms Mvi vi (14.264) d(1 + Rs Tms Tpi ) = −Rs Tms Mvi vi (14.265) 630 Pulse-Width Modulated DC–DC Power Converters Zo io Ai + vr = 0 ve = − vf Tc vc + vei vfi vf Tms il Rs vo′ d + vo Ti il″ + i l′ Tp vo″ + Tpi T β Figure 14.90 impedance. Block diagram of PWM converters with current-mode control for determining the closed-loop output d=− Rs Tms Mvi v 1 + Rs Tms Tpi i v′o = Tp d = − (14.266) Rs Tp Tms Mvi v 1 + Rs Tms Tpi i (14.267) v′′o = Mv vi ( vo = v′o + v′′o = Mvc = Mv − Rs Tp Tms Mvi (14.268) ) 1 + Rs Tms Tpi vi Rs Tp Tms Mvi vo || = Mv − . | vi ||v =0 1 + Rs Tms Tpi (14.269) (14.270) c 14.19.5 Closed-Loop Output Impedance of PWM Converters with Current-Mode Control Figure 14.90 shows a block diagram for determining the closed-loop output impedance, obtained by setting vr = 0 and vi = 0. The derivation of this impedance is as follows: i′l = Tpi d (14.271) i′′l = Ai io (14.272) il = i′l + i′′l = Tpi d + Ai io (14.273) vfi = Rs il = Rs Tpi d + Rs Ai io (14.274) vf = 𝛽vo (14.275) ve = −vf = −𝛽vo (14.276) vc = Tc ve = −𝛽Tc vo (14.277) Current-Mode Control 631 vei = vc − vfi = −𝛽Tc vo − Rs Tpi d − Rs Ai io (14.278) d = Tms vei = −Tms 𝛽Tc vo − Tms Tpi Rs d − Rs Ai Tms io (14.279) d(1 + Tms Tpi Rs ) = −Tms 𝛽Tc vo − Rs Ai Tms io (14.280) Rs Tms Ai Tms 𝛽Tc v − i 1 + Tms Tpi Rs o 1 + Tms Tpi Rs o (14.281) d=− v′o = Tp d = − Tms 𝛽Tc Tp 1 + Tms Tpi Rs vo − Rs Tms Ai Tp i 1 + Tms Tpi Rs o v′′o = −Zo io vo = v′o + v′′o = − Tms 𝛽Tc Tp 1 + Tms Tpi Rs vo − (14.282) (14.283) Rs Tms Ai Tp i − Zo io 1 + Tms Tpi Rs o vo (1 + Ti + Tv ) = −[Zo (1 + Ti ) + Rs Tms Ai Tp ]io . (14.284) (14.285) Finally, the closed-loop output impedance is Zo (1 + Ti ) + Rs Tms Ai Tp v || =− . Zocl ≡ − o | | io |v =v =0 1 + Ti + Tv r i (14.286) 14.20 Feedforward Gains in PWM Converters with Current-Mode Control without Slope Compensation The preceding analysis was performed under the assumption of fixed converter input voltage VI and output voltage VO . Let us relax this assumption and consider the case for which the input and output voltages consist of dc and small-signal ac components: vI = VI + vi and vO = VO + vo . The slopes of the inductor current waveform depend on the input and/or output voltages. We will also assume that the duty cycle D is lower than 0.5 so that the inner loop is stable. When the input and output voltages contain small-signal ac components, the slopes also contain dc and small-signal components: mT1 = M1 + m1 and mT2 = M2 + m2 . Figure 14.91 shows the waveforms in PWM converters with CMC and without slope compensation, where the control voltage VC is held constant and the slope of the rising inductor current waveform is increased by a small change m1 from the steady-state value M1 to M1 + m1 . This causes the duty cycle to decrease from D to dT = D + d, where d < 0. The slopes of the rising inductor current waveforms before and after perturbation are M1 = tan 𝛼 = Rs ΔiL DTs (14.287) and M1 + m1 = tan 𝛿 = Rs ΔiL Rs ΔiL = . dT T s (D + d)Ts (14.288) These two equations produce M1 D = (M1 + m1 )(D + d) (14.289) 632 Pulse-Width Modulated DC–DC Power Converters Rs iL ,VC VC Rs iL Rs iL M1 + m1 M1 α Rs Δ iL dTs δ dT Ts 0 DTs t (a) vGS t 0 (b) Figure 14.91 Waveforms of the inductor current with steady-state slope M1 and with perturbed slope M1 + m1 at fixed control voltage VC in PWM converter with current-mode control and without slope compensation. (a) Waveforms of the inductor and control currents. (b) Waveform of the gate-to-source voltage. from which M1 D = M1 D + M1 d + Dm1 + m1 d. (14.290) If m1 d ≪ M1 d and m1 d ≪ Dm1 , that is, if the small-signality conditions m1 ≪ M1 and d ≪ D are satisfied, the product of the small-signal components m1 d can be neglected. Hence, one obtains a general and a linear relationship between m1 and d given by [45] d=− D m . M1 1 (14.291) For the buck converter, M1 + m1 = (V + vi ) − (VO + vo ) VI − VO vi − vo vI − v O = I = + L L L L (14.292) where m1 = vi − v o L (14.293) and M1 is given by (14.7). As a result, (14.291) becomes [45] d=− D D D (v − vo ) = − v + v = Ki vi + Ko vo . VI − VO i VI − VO i VI − VO o (14.294) Current-Mode Control 633 Using D = VO ∕VI , the input feedforward gain is given by Ki ≡ d || D D2 =− =− | vi ||v =0 and v =0 VI − VO (1 − D)VO c (14.295) o and the output feedforward gain is given by d || D D2 = = = −Ki Ko ≡ | vo ||v =0 and v =0 VI − VO (1 − D)VO c i (14.296) yielding d = Ki (vi − vo ) = − D2 (v − vo ). (1 − D)VO i (14.297) For the boost and buck–boost converters, M1 + m1 = V + vi v V vI = I = I + i L L L L (14.298) where vi L (14.299) D v = Ki vi VI i (14.300) d || D =− | vi ||v =0 VI (14.301) m1 = and M1 is given by (14.9). Thus, from (14.291), d=− where the input feedforward gain is Ki ≡ c and the output feedforward gain is Ko = 0. For the boost converter, VI = (1 − D)VO and (14.301) becomes Ki = − D D =− . VI (1 − D)VO (14.302) For the buck–boost converter, VI = VO (1 − D)∕D and (14.301) becomes Ki = − D D2 =− . VI (1 − D)VO (14.303) Figure 14.92 shows a block diagram of the current-mode pulse-width modulator, in which the feedforward gains Ki and Ko are included. A block diagram of the current loop with feedforward gains and disturbances is shown in Figure 14.93. vi vei Ki T ms + + d + Ko Figure 14.92 vo Block diagram of the current modulator that includes feedforward gains. 634 Pulse-Width Modulated DC–DC Power Converters vi vc vc vA + vei + vA vi ~ + + vo d + Rs il + 14.21 Ko Tms Ti il Rs Figure 14.93 Ki + + Mvi Tpi Ai io Block diagram of current loop with disturbances and feedforward gains. Feedforward Gains in PWM Converters with Current-Mode Control and Slope Compensation Figure 14.94 shows the waveforms in PWM converters with CMC and with slope compensation, where the control voltage VC is held constant, the slope of the voltage VC − vA remains constant, and the slope of the rising inductor current waveform is increased by a small change m1 from the steady-state value M1 to M1 + m1 . Note that (D + d)Ts < DTs ; therefore, dTs < 0. The slopes of the rising inductor current waveforms are M1 = tan 𝛼 = M1 + m1 = tan 𝛿 = Rs ΔiL0 DTs (14.304) Rs ΔiL1 Rs ΔiL1 = dT T s (D + d)Ts (14.305) and the slope of the compensating ramp voltage vC –vA is Rs (ΔiL1 − ΔiL0 ) . dTs (14.306) − M3 d = (M1 + m1 )(D + d) − M1 D (14.307) − M3 d = M1 d + Dm1 + m1 d. (14.308) − M3 = tan 𝛾 = Hence, which simplifies to the form If the small-signality conditions m1 ≪ M1 and d ≪ D are satisfied, the product of the small-signal components m1 d can be neglected. Hence, one obtains [45] d=− D D m =− ( ) m1 . M M1 + M3 1 M 1+ 3 1 (14.309) M1 Substitution of (14.7) and (14.293) into (14.309) produces d for the buck converter D D D d = −( (vi − vo ) = − ( vi + ( vo = Ki vi + Ko vo ) ) ) M3 M3 M3 1 + M (VI − VO ) 1 + M (VI − VO ) 1 + M (VI − VO ) 1 1 1 (14.310) Current-Mode Control Rs iL , vC γ 635 VC vC − vA −M3 γ Rs (ΔiL1 − ΔiL0) Rs iL M1 + m1 dTs Rs Δ iL0 Rs ΔiL1 M1 δ α dTTs 0 DTs Ts t Ts t vGS 0 Figure 14.94 Waveforms of the inductor current with steady-state slope M1 and with perturbed slope M1 + m1 for fixed control voltage VC and compensating slope M3 in PWM converter with current-mode control and with slope compensation. where the input feedforward gain is given by Ki ≡ d || D D2 = −( = −( | ) ) M3 M3 vi ||v =0 and v =0 1+ (V − V ) 1+ (1 − D)V c o I M1 O M1 (14.311) O and the output feedforward gain is given by Ko ≡ d || D D2 = ( = −Ki . = ( | ) ) M M vo ||v =0 and v =0 1 + 3 (V − V ) 1 + 3 (1 − D)V c i M1 I O M1 (14.312) O Using (14.9), (14.299), and (14.309), one arrives at d for the boost and buck–boost converters D d = −( ) vi = Ki vi M 1 + M3 VI 1 (14.313) 636 Pulse-Width Modulated DC–DC Power Converters Zo io vi Mv ~ Ki Ai + vr ~ ve Tc vc vei + vfi vf Mvi + + d vo Ko Tpi il + + Tp + Ti + + Rs + Tms T β Figure 14.95 included. Control block diagram of a PWM converter with current-mode control, where the feedforward gains are where the input feedforward gain is Ki ≡ d || D = −( | ) M vi ||v =0 1+ 3 V c M1 (14.314) I and the output feedforward gain is Ko = 0. For the boost converter, VI = (1 − D)VO and (14.314) becomes Ki = − ( M 1 + M3 1 D . ) (1 − D)VO (14.315) For the buck–boost converter, VI = VO (1 − D)∕D and (14.314) becomes D2 . Ki = − ( ) M 1 + M3 (1 − D)VO (14.316) 1 Figure 14.95 shows a control block diagram of a PWM converter with CMC, in which feedforward gains Ki and Ko are included. 14.22 Control-to-Output Voltage Transfer Function of Inner Loop with Feedforward Gains The inductor current with vi = 0 is given by il = Hicl vc + Tpi Ko v . 1 + Ti o (14.317) The output voltage is vo = Tio il = Tio Hicl vc + Tio Tpi Ko v 1 + Ti o (14.318) Current-Mode Control resulting in ( ) Tpi Ko 1 − Tio vo = Hicl Tio vc . 1 + Ti 637 (14.319) Hence, the control-to-output voltage transfer function of the inner loop is Tco = vo || Hicl Tio = . | | vc |v =0 1 − Ko Tpi Tio i (14.320) 1+Ti 14.23 Audio-Susceptibility of Inner Loop with Feedforward Gains The derivation of the audio-susceptibility is as follows: vei = −vfi = −Rs il = −Rs (Tpi d′ + Mvi vi ) = −Rs Tpi d′ − Rs Mvi vi (14.321) d′ = −Rs vvi = Tms (−Rs Tpi d′ − Rs Mvi vi ) + Ki vi + Ko vo = −Rs Tms Tpi d′ − Rs Tms Mvi vi (14.322) (1 + Rs Tms Tpi )d′ = −Rs Tms Mvi vi (14.323) −Rs Tms Mvi v 1 + Rs Tms Tpi i (14.324) d′′ = Ki vi (14.325) d′′′ = Ko vo (14.326) −Rs Tms Mvi v + Ki vi + Ko vo 1 + Rs Tms Tpi i (14.327) v′o = Tp d (14.328) v′′o = Mv vi (14.329) d′ = d = d′ + d′′ + d′′′ = ( vo = v′o + v′′o = Tp d + Mv vi = −Rs Tms Mvi Tp 1 + Rs Tms Tpi ( (1 − Ko Tp )vo = Mv − ) + Ki Tp + Mv vi + Ko Tp vo Rs Tms Mvi Tp (14.330) ) vi 1 + Rs Tms Tpi (14.331) RT M T v Mvc = o = vi s ms vi p Mv + Ki Tp − 1+R T T s ms pi 1 − Ko Tp . (14.332) For the boost converter, Ko = 0, and therefore Mvc = Rs Tms Mvi Tp vo = Mv + Ki Tp − . vi 1 + Rs Tms Tpi (14.333) 638 14.24 Pulse-Width Modulated DC–DC Power Converters Closed-Loop Transfer Functions with Feedforward Gains The loop gains are: Tc Tms Tp 𝛽, Tms Tpi Rs , and Ko Tp . For the buck converter, the closed-loop transfer functions with feedforward gains are Tc Ticl Tp v || = (14.334) Tcl = o | vr ||v =i =0 1 + Tc Ticl Tp 𝛽 + Ko Tp i o Mv + Ki Tp vo || = | | vi |v =i =0 1 + Ti + Tv + Ko Tp (14.335) Zo (1 + Ti ) + Rs Tms Ai Tp vo || = . | −io ||v =v =0 1 + Ti + Tv + Ko Tp (14.336) Mvcl = r o and Zocl = i r Since |Ko Tp | ≪ |Ti |, Ko Tp in the denominator of the above equations can be neglected. For the boost and buck–boost converters, Ko = 0 and the transfer functions with feedforward gains are Tc Ticl Tp v || Tcl = o | (14.337) = | vi |v =i =0 1 + Tc Ticl Tp 𝛽 i o ( ) M M Mv + Tp Ti T v − T vi + Ki Tp | v | p pi Mvcl = o | = vi ||v =i =0 1 + Ti + Tv r o (14.338) and Zocl = Zo (1 + Ti ) + Rs Tms Ai Tp vo || = . | | −io |v =v =0 1 + Ti + Tv i (14.339) r Thus, only Mvcl is affected by the feedforward gains for the boost and buck–boost converters. 14.25 Slope Compensation by Adding a Ramp to Inductor Current Waveform Slope compensation can also be accomplished by adding an external periodic ramp current waveform to the inductor current waveform, as shown in Figure 14.96. It can be seen that both slopes of the waveform iL + iA are changed. Figure 14.96 shows steady-state and perturbed waveforms of iL + iA in PWM converters with slope compensation obtained by adding a ramp to the inductor current. The slopes of the waveform iL + iA are M1 + M3 = tan 𝛼 = Δ(iL0 + iA ) dTs (14.340) M2 − M3 = tan 𝛽 = Δ(iL1 + iA ) dTs (14.341) Δ(iL1 + iA ) M2 − M3 = . Δ(iL0 + iA ) M1 + M3 (14.342) and resulting in the current gain a≡ This equation is the same as that in (14.33). Current-Mode Control 639 iL , iA , iC , iL + iA iC M3 + M1 M3 − M2 iL+ iA M1 iL − M2 iA M3 0 Figure 14.96 D2Ts D1Ts Ts t Slope compensation by adding an external periodic ramp current iA to the inductor current waveform iL . 14.26 Relationships for Constant-Frequency Current-Mode On-Time Control A similar analysis reveals that, in constant-frequency current-mode scheme, where the clock initiates the switch on-time, and the control and inductor current intersection initiates the switch-off time, the following relation holds true for the circuit without a slope compensation a= |ΔiL1 | M1 1−D = . = |ΔiL0 | M2 D (14.343) In this case, the inner-current loop is stable for D > 0.5 and is unstable for D < 0.5. If slope compensation is used, a= |ΔiL1 | M1 − M3 = |ΔiL0 | M1 + M3 (14.344) 1 . (M2 + M3 )Ts (14.345) and Tm = 14.27 Summary r r r r r r PWM converters with CMC are nonlinear, time-varying circuits. Modeling the current-mode-controlled converters involves discrete-time signals. CMC scheme contains two loops: a inner-current loop and a voltage outer loop. In CMC architecture, the peak inductor current is controlled along with the output voltage. In CMC, the peak inductor current and the peak switch current are equal to the instantaneous control current iC . In CMC, the control decision is made in each cycle when the inductor or switch current becomes equal to the control current. r PWM converters with CMC have inherently short-circuit protection and over-current protection. Since the peak and average current of the inductor is proportional to the control voltage, the output current can be limited by clamping the control voltage. r Since the inductor current is controlled by sensing the peak current in the power switch or the inductor, the current can be limited on a cycle-by-cycle basis, resulting in a fast response of the current loop. 640 Pulse-Width Modulated DC–DC Power Converters r The inner-current loop is unstable for D > 0.5 for CCM. The instability of the current loop does not occur for DCM. r Slope compensation may be used to achieve stability of the inner-current loop. One method of slope compensation is to subtract a ramp voltage from the control voltage. Another method is to add a ramp to the sensed inductor or switch current. r As the compensating ramp slope M increases, the range of the duty cycle, in which the inner loop is stable, is 3 increased above 0.5. r The inner-current loop is stable at any duty cycle D for M > 0.5M . 3 2 r The inner-current loop recovers from a perturbation within one cycle if M = M (i.e., for dead-beat control). 3 2 r CMC offers several advantages, such as the ease of compensation of the voltage loop, fast dynamic response, inherent line feedforward, low audio susceptibility, good line regulation, automatic overload and short-circuit protection, and easy paralleling of multiple converters. r The continuous-time domain transfer function H ∗ (s) can be obtained from the discrete-time domain transfer function H(z) using the equation: | 1 − esT | H(z)| . (14.346) H ∗ (s) = | sT sT |z=e r As a increases from 0 to 1, f ∕f increases from 0.3 to 0.5. ci s r The current loop is wide band with the crossover frequency f ≈ 0.4f at PM ≈ 60◦ . ci s r The current loop acts like a partial lead compensator for the voltage loop. r Due to sensing the instantaneous inductor current or switch current, the peak CMC scheme is susceptible to noise, especially when the inductor current ripple is low or when the duty cycle is low. r VMC is more immune to noise than CMC. r The constant-off time CMC has many advantages. r CMC can be used in constant-current dc–dc converters. r The unity-gain frequency of PWM converters with peak CMC is about three to four times higher than that with VMC. References [1] T. A. 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Review Questions 14.1 What is the basic topology of a current-mode control system? 14.2 Explain the principle of operation of current-mode control. 14.3 What event turns the transistor on in PWM converters with current-mode control? 14.4 What event turns the transistor off in PWM converters with current-mode control? 14.5 How many loops are in the current-mode control scheme? 14.6 What are the advantages of current-mode control? 14.7 When is the current loop without slope compensation stable? 14.8 Explain the principle of slope compensation. 14.9 When is the current loop with slope compensation stable? 14.10 What amount of slope compensation will guarantee stability of the current loop under any conditions? 14.11 What amount of slope compensation will guarantee optimum compensation of the current loop? 14.12 What is the oscillation frequency of the unstable current loop? 14.13 Is the peak current-mode control susceptible to noise? Problems 14.1 A lossless buck converter with constant-frequency peak CMC and without slope compensation has VO = 5 V. What is the range of the input voltage VI , in which the inner loop is stable? 14.2 A lossy buck converter with constant-frequency peak CMC and without slope compensation has VO = 5 V and the efficiency 𝜂 = 0.9. What is the range of the input voltage VI , in which the converter is stable? 14.3 A lossy buck converter with constant-frequency peak CMC and without slope compensation has VI = 28 V, VO = 5 V, L = 301 μH, the switching frequency fs = 100 kHz, and the efficiency 𝜂 = 0.9. Does the converter require slope compensation? 14.4 A buck converter with constant-frequency peak CMC has VI = 28 ± 4 V, VO = 20 V, L = 301 μH, fs = 100 kHz, and the efficiency 𝜂 = 1. Is the converter stable? Is slope compensation required in this converter? 14.5 A buck converter with constant-frequency peak CMC has VInom = 28 V, VO = 20 V, L = 301 μH, fs = 100 kHz, and the efficiency 𝜂 = 1. Find the ramp slope for the optimum compensation and the peak compensating voltage. Current-Mode Control 645 14.6 A buck–boost converter with constant-frequency peak CMC has VInom = 42 V, VO = −28 V, L = 334 μH, fs = 100 kHz, and the efficiency 𝜂 = 0.85. Find M3nom and the peak value of the compensation ramp slope at which a = 0.3. 14.7 A PWM converter with constant-frequency peak CMC has Rs = 0.1 Ω, a = 0.3, and fs = 100 kHz. Find Hicl (z), Hicl (s), and Ti (s). 14.8 A buck–boost converter has D = 0.407, VI = 48 V, VO = −28 V, M1 = 0.144 A/s, M3 = 0.0986 A/s, and ΔVI = 1 V. Find Ki and ΔD. Assuming that the voltage loop is open and the feedforward voltage is the only change in the circuit, calculate the output voltage VO . 14.9 A boost converter has the following specs: VI = 1.5 ± 0.5 V, VO = 5 V, IO = 0.2 to 4 A, and fs = 250 kHz. Find Dmax , a, and M3min to achieve PM = 50◦ . 14.10 The inner loop of the boost converter has fs = 250 kHz, a = 0.292, and Rs = 0.2 Ω. Determine fi , 𝜉i , and the poles of Hicl . Give a specific expression for a rational closed-loop transfer function Hicl (s). 14.11 The inner loop of the boost converter has fs = 250 kHz, a = 0.292, and Rs = 0.2 Ω. Determine f1 , fsh , and expression for Ti (s). 14.28 Appendix: Sample-and-Hold Modeling 14.28.1 Sampler of the Control Voltage The control voltage at the input of the inner loop vc (t) is an analog, continuous-time function. The control voltage is sampled when the sensed inductor current Rs iL intersects with the controlled voltage, producing a sequence of vc (kTs ). The modeling of control voltage sampling is as follows. The train of unit impulses 𝛿(t − kTs ) with the period Ts = 1∕fs is given by 𝛿T (t) = ∞ ∑ 𝛿(t − kTs ) = ⋯ + 𝛿(t + Ts ) + 𝛿(t) + 𝛿(t − Ts ) + ⋯ . (14.347) k=−∞ The sampler can be modeled by a multiplier of the analog, continuous-time control voltage vc (t) and the train of unit impulses 𝛿T (t), as shown in Figure 14.97. The sampled control voltage at the sampler output can be represented vc* (t) vc (t) fs (a) vc*(t) vc (t ) δ T ( t – kTs ) (b) Figure 14.97 Sampler. (a) Circuit. (b) Model. 646 Pulse-Width Modulated DC–DC Power Converters by a sequence (i.e., a train) of amplitude-modulated (AM) impulses v∗c (t) = ∞ ∑ vc (kTs )𝛿(t − kTs ) = vc (0)𝛿(t) + vc (Ts )𝛿(t − Ts ) + vc (2Ts )𝛿(t − 2Ts ) + ⋯ . (14.348) k=0 The expression (14.348) can be simplified to the following discrete-time function of time v∗c (t) = ∞ ∑ vc (t)𝛿(t − kTs ) = vc (t) k=0 ∞ ∑ 𝛿(t − kTs ) = vc (t)𝛿T (t) (14.349) k=0 because 𝛿(t − kTs ) = 0 for t ≠ kTs and 𝛿(t − kTs ) = 1 for t = kTs . The impulse-sampled control voltage is represented by the product of the continuous-time control voltage vc (t) and the train of unit impulses 𝛿T (t − kTs ). The strength of each impulse is equal to the value of the control voltage at the sampling instant vc (kTs ). Therefore, an ideal sampler can be regarded as an AM 𝛿-modulator, in which the analog control voltage vc (t) is the modulating signal, the train of unit impulses 𝛿T (t) with the switching frequency fs = 1∕Ts is the carrier, and the sampler output voltage v∗c (t) is the train of the AM modulated impulses. Since the train of unit impulses is a periodic function with the angular frequency 𝜔s = 2𝜋∕Ts , it can be represented by an exponential Fourier series 𝛿T (t) = ∞ ∑ Ck ejk𝜔s t (14.350) k=−∞ where the exponential Fourier series coefficients are T Ck = T s s 1 1 1 𝛿T (t)e−jk𝜔s t dt = 𝛿(t)e−jk𝜔s t dt = . Ts ∫0 Ts ∫0 Ts (14.351) Hence, 𝛿T (t) = ∞ 1 ∑ jk𝜔s t 1 1 1 1 e = ⋯ + e−j𝜔s t + + ej𝜔s t + ej2𝜔s t + ⋯ Ts k=−∞ Ts Ts Ts Ts (14.352) Thus, the sampled control voltage at the sampler output can be described by v∗c (t) = vc (t)𝛿T (t) = vc (t) ∞ ∑ vc (t) ∑ jk𝜔 t e s. Ts k=−∞ ∞ Ck ejk𝜔s t = k=−∞ (14.353) Taking the Fourier transform of v∗c (t) and using the shifting theorem of the Fourier transform,  {f (t)ej𝜔o t } = F(𝜔 − 𝜔o ) (14.354) we obtain the frequency spectrum of the sampled control voltage v∗c (j𝜔) =  {v∗c (t)} = ∞ 1 ∑ 1 1 1 v [j(𝜔 + k𝜔s )] = ⋯ + vc [j(𝜔 − 𝜔s )] + vc (j𝜔) + vc [j(𝜔 + 𝜔s )] + ⋯ . Ts k=−∞ c Ts Ts Ts (14.355) The frequency spectrum of the impulse-sampled control voltage is amplified by a factor of fs = 1∕Ts and reproduced an infinite number of times at DC, fs , 2fs , 3fs , etc. The spectrum of the sampled control voltage contains the components at nfs ± f , where n = 1, 2, 3, ... . The sampling process produces the replicas of the input-frequency spectrum centered at DC and the multiples of the switching frequency. The Laplace transform of v∗c (j𝜔) in (14.355) is v∗c (s) = ∞ 1 ∑ v (s + jk𝜔s ). Ts k=−∞ c (14.356) Current-Mode Control 647 If we assume that the spectrum of the control voltage v∗c does not contain significant components above the Nyquist frequency fs ∕2 (i.e., |vc (f )| ≈ 0 for f ≥ fs ∕2) and therefore there is no aliasing, then we can write v∗c (s) ≈ 1 v (s). Ts c (14.357) Hence, the transfer function of an ideal sampler is Hs (s) ≡ v∗c (s) vc (s) ≈ 1 = fs . Ts (14.358) For example, assume that the control voltage is a sine wave of frequency f vc (t) = Vm sin(2𝜋ft). (14.359) The sampled control voltage is v∗c (t) = vc (t)𝛿T (t) ∞ ∑ Vm sin(2𝜋fkTs )𝛿(t − kTs ). (14.360) k=−∞ The spectrum of the sampled control voltage is v∗c (f ) = fs Vm ∞ ∑ [𝛿(kfs − f ) + 𝛿(kfs + f )]. (14.361) k=−∞ Figure 14.98 shows the spectrum of a sine wave before and after sampling for f < fs ∕2. For f < fs ∕2, fs − f > fs ∕2. For f = fs ∕2, fs − f = fs − fs ∕2 = fs ∕2. In this case, the frequencies f and fs − f are superimposed. For f > fs ∕2, fs − f < fs ∕2. Thus, any control voltage of frequency f > fs ∕2 will reflect into the frequency range 0 ≤ f ≤ fs ∕2, causing the frequency aliasing effect or folding effect. The reflected voltage will be interpreted as low-frequency information and will corrupt the applied control voltage. Therefore, the maximum frequency fmax of the control voltage vc should be lower than the Nyquist frequency fs ∕2 so that |vc (f )| ≈ 0 for f ≥ fs ∕2. Vm 0 f f (a) fsVm 0 f fs f fs fs + f 2f s f 2f s 2f s + f f (b) Figure 14.98 Spectrum of a sine wave. (a) Before sampling. (b) After sampling for f < fs ∕2. 648 Pulse-Width Modulated DC–DC Power Converters ∗ The transfer function Hicl (s) = i∗ (s)∕v∗c (s) from the small-signal control voltage v∗c (s) to the small-signal inductor ∗ current il (s) in the sampled-Laplace s-domain is given by (14.87). 14.28.2 Zero-Order Hold of Inductor Current The transfer function of the ZOH of the small-signal component of the inductor current il can be derived as follows. Assume that the small-signal component of inductor current il (t) = 0 for t < 0. This component at the output of the ZOH i0l (t) is the step reconstruction and is related to the sample sequence il (kTs ) by i0l (t) = il (0)[u(t) − u(t − Ts )] + il (Ts )[u(t − Ts ) − u(t − 2Ts )] + il (2Ts )[u(t − 2Ts ) − u(t − 3Ts )] + ⋯ = ∞ ∑ il (kTs ){u(t − kTs ) − u[t − (k + 1)Ts ]}. (14.362) k=0 The difference between the perturbed inductor current and the steady-state inductor current is a continuous-time function with a “staircase” waveform. The Laplace transform of i0l (t) is ) ) ) ( ( −sT ( −s2T 1 e−sTs e s e−s2Ts e s e−s3Ts i0l (s) = {i0l (t)} = il (0) − + il (Ts ) − + il (2Ts ) − +⋯ s s s s s s ) ∞ ) ( ( ] 1 − e−sTs [ 1 − e−sTs ∑ 1 − e−sTs ∗ = il (0) + il (Ts )e−sTs + il (2Ts )e−2sTs + ⋯ = il (s) il (kTs )e−ksTs = s s s k=0 (14.363) where the starred transform of the small-signal component of the inductor current is i∗l (s) = ∞ ∑ il (kTs )e−ksTs . (14.364) k=0 In this equation, i∗l (s) is a function of the small-signal component of the inductor current and the switching (sampling) period Ts . From (14.363), the ZOH transfer function is given by i0 (s) 1 − e−sTs HZOH (s) ≡ ∗l = . il (s) s (14.365) Figures 14.99 and 14.100 show Bode plots of the ZOH transfer function. The transfer function of an ideal sampler and a ZOH is 1 − e−sTs . sTs Hsh (s) = Hs (s)HZOH (s) = (14.366) The frequency response of the sampler and ZOH can be found as follows. Setting s = j𝜔, 𝜔Ts 𝜔Ts 𝜔Ts sin 2 𝜔Ts 1 − e−j𝜔Ts j𝜔T2 s − j𝜔T2 s ej 2 − e−j 2 −j 𝜔T2 s e e = e = e−j 2 = Hsh (j𝜔) = 𝜔Ts 𝜔Ts j𝜔Ts 2j 2 2 sin 𝜋ff s 𝜋f fs e −j 𝜋f f s = |Hsh |ej𝜙Hsh (14.367) where | sin 𝜋f | | | f | | |Hsh | = | 𝜋f s | | | | fs | | | (14.368) 𝜋f +𝜃 fs (14.369) and 𝜙Hsh = − Current-Mode Control −5 1 x 10 0.9 0.8 0.7 | HZOH | 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 f/f 2 2.5 3 s Figure 14.99 Magnitude of the zero-order hold transfer function |HZOH | as a function of frequency. 0 −20 −40 (°) −60 ϕ H ZOH −80 −100 −120 −140 −160 −180 0 0.5 1 1.5 f/f 2 2.5 3 s Figure 14.100 Phase of the zero-order hold transfer function 𝜙ZOH as a function of frequency. 649 650 Pulse-Width Modulated DC–DC Power Converters 1 0.9 0.8 0.7 | H sh |

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