Assignment on Sequential Circuits
Course: Digital Electronics
Submission Due date 18.03.2025 by 10.00 am
1. Analyze and describe the operation of the circuit in Figure
2. True or false: A J-K flip-flop can be used as an S-R flip-flop, but an S-R flip-flop cannot be
used as a J-K flip-flop.
3. Describe how a D latch operates differently from an edge-triggered D flip-flop.
4. True or false: A D latch is in its transparent mode when EN=0
5. True or false: In a D latch, the D input can affect Q only when EN = 1.
6. True or false: A FF that has an rating of Fmax = 25 MHz can be reliably triggered by any
CLK pulse waveform with a frequency below 25 MHz.
7. True or false: Synchronous data transfer requires less circuitry than asynchronous
transfer.
8. True or false: The fastest method for transferring data from one register to another is
parallel transfer.
9. A 20-kHz clock signal is applied to a J-K flip-flop with J=K=1. What is the frequency of
the FF output waveform?
10. What is the frequency of the output of the eighth FF when the input clock frequency is
512 kHz?
11. A retriggerable OS can be used as a pulse-frequency detector that detects when the
frequency of a pulse input is below a predetermined value. A simple example of this
application is shown in Figure
12. The operation begins by momentarily closing switch SW1.
(a)
Describe how the circuit responds to input frequencies above 1 kHz.
(b)
Describe how the circuit responds to input frequencies below 1 kHz.
(c)
How would you modify the circuit to detect when the input frequency drops below
50 kHz?
13. Explain the significance of the following terms.
a.
Asynchronous inputs
b.
Edge-triggered
c.
Shift register
d.
Frequency division
e.
Asynchronous (jam) transfer
f.
State transition diagram
g.
Parallel data transfer
h.
Serial data transfer
i.
Retriggerable one-shot
j.
Schmitt-trigger inputs
14. Illustrate significance of the following terms.
a)
Full adder
b)
2’s complement
c)
Arithmetic/logic unit
d)
Sign bit
e)
Overflow
f)
Accumulator
g)
Parallel adder
h)
Look-ahead carry
i)
Negation
j)
register
15. A counter is needed that will count the number of items passing on a conveyor belt. A
photocell and light source combination is used to generate a single pulse each time an
item crosses its path. The counter must be able to count as many as one thousand
items. How many FFs are required?
16. Explain why a ripple counter’s maximum frequency limitation decreases as more FFs are
added to the counter.
17. A certain J-K flip-flop has tpd = 12 ns. What is the largest MOD counter that can be
constructed from these FFs and still operate up to 10 MHz?
18. What is the advantage of a synchronous counter over an asynchronous counter? What
is the disadvantage?
19. How many logic devices are required for a MOD-64 parallel counter?
20. Why is it desirable to avoid having asynchronous controls on counters?
21. What tool is useful in the analysis of synchronous counters?
22. What determines the count sequence for a counter circuit?
23. What counter characteristic is described by saying that it is self-correcting?
24. True or false: A serial in/parallel out register can have all of its bits displayed at one
time.
25. What kind of register can have a complete binary number loaded into it in one
operation, and then have it shifted out one bit at a time?
26. What type of register can have data entered into it only one bit at a time, but has all
data bits available as outputs?
27. In what type of register do we store data one bit at a time and have access to only one
output bit at a time?
28. How does the parallel data entry differ for the 74165 and the 74174?
29. Which shift-register counter requires the most FFs for a given MOD number?
30. Which shift-register counter requires the most decoding circuitry?
31. How can a ring counter be converted to a Johnson counter?
32. True or false:
(a)
The outputs of a ring counter are always square waves.
(b)
The decoding circuitry for a Johnson counter is simpler than for a binary
counter.
(c)
Ring and Johnson counters are synchronous counters.
33. How many FFs are needed in a MOD-16 ring counter? How many are needed in a MOD16 Johnson counter?
34. Draw the circuit diagram for a MOD-32 synchronous counter. Determine fmax for this
counter if each FF has tpd = 20 ns and each gate has tpd = 10 ns.
35. Draw the circuit diagram for a MOD-64 synchronous counter. Determine fmax for this
counter if each FF has tpd = 20 ns and each gate has tpd = 10 ns.
36. Complete the timing diagram in Figure below for a 74ALS190 with the indicated input
waveforms applied. The DCBA input is 0101.
37. For each of the following statements, indicate the type(s) of counter being described.
(a) Each FF is clocked at the same time.
(b) Each FF divides the frequency at its CLK input by 2.
(c) The counting sequence is 111, 110, 101, 100, 011, 010, 001, 000.
(d) The counter has 10 distinct states.
(e) The total switching delay is the sum of the individual FFs’ delays.
(f) This counter requires no decoding logic.
(g) The MOD number is always twice the number of FFs.
(h) This counter divides the input frequency by its MOD number.
(i) This counter can begin its counting sequence at any desired starting state.
(j) This counter can count in any direction.
(k) This counter can suffer from decoding glitches due to its propagation delays.
(l) This counter only counts from 0 to 9.
(m) This counter can be designed to count through arbitrary sequences by determining
the logic circuit needed at each flip-flop’s.
38. Which LED segments will be on for a decoder/driver input of 1001?
39. True or false: More than one output of a BCD-to-7-segment decoder/driver can be
active at one time.
40. Indicate which of the following statements refer to LCD displays and which refer to LED
displays. (a) Emit light (b) Reflect ambient light (c) Are best for low-power applications
(d) Require an ac voltage (e) Use a 7-segment arrangement to produce digits (f) Require
current-limiting resistors
41. What form of data is sent to each of the following? (a) A 7-segment LCD display with a
decoder/driver (b) An alphanumeric LCD module (c) An LCD computer display\
42. Can more than one decoder output be activated at one time?
43. What is the function of a decoder’s enable input(s)?
44. How does the 7445 differ from the 7442?
45. The 74154 is a 4-to-16 decoder with two active-LOW enable inputs. How many pins
(including power and ground) does this IC have?
46. Draw the circuit diagram for a MOD-64 synchronous counter.
47. Determine fmax for this counter if each FF has tpd = 20 ns and each gate has tpd = 10
ns.
48. Design and implement a synchronous counter that will output a 10-kHz signal when a 1MHz clock is applied.
49. Design and draw a synchronous, MOD-16, up/down counter. The count direction is
controlled by dir(dir= A four-bit ripple counter is driven by a 20-MHz clock signal. Draw
the waveforms at the output of each FF if each FF has tpd = 20 ns.
Determine which counter states, if any, will not occur because of the propagation
delays. What is the maximum clock frequency that can be used with the counter.
What would fmax be if the counter were expanded to six bits?
50. Design and implement a synchronous counter that will output a 10-kHz signal when a 1MHz clock is applied.
51. What is the advantage of loading a counter synchronously?
52. What is the advantage of loading the counter asynchronously?
53. What two pieces of information are necessary to detect an edge?
54. What does it mean for a ring counter to self-start?
55. Which shift-register counter requires the most FFs for a given MOD number?
56. Which shift-register counter requires the most decoding circuitry?
57. How can a ring counter be converted to a Johnson counter?
58. True or false : (a) The outputs of a ring counter are always square waves. (b) The
decoding circuitry for a Johnson counter is simpler than for a binary counter. (c) Ring
and Johnson counters are synchronous counters.
59. How many FFs are needed in a MOD-16 ring counter? How many are needed in a MOD16 Johnson counter?
60. What kind of register can have a complete binary number loaded into it in one
operation, and then have it shifted out one bit at a time?
61. True or false:A serial in/parallel out register can have all of its bits dis- played at one
time.
62. What type of register can have data entered into it only one bit at a time, but has all
data bits available as outputs?
63. In what type of register do we store data one bit at a time and have access to only one
output bit at a time?
64. How does the parallel data entry differ for the 74165 and the 74174?
65. Compare Combinational and Sequential Cicuits.
66. What is race around condition? Why does it occurs in FF?
67. What is the significance of excitation table in FFs?
68. Which FF is called universal FF? How can you realize all other FFs using universal FFs?
69. Explain the significance of the following w.r.t.
a) Set up time
b) Hold time
c) Propagation delay
d) Maximum clock frequency
70. How can you design bounce elimination switch?
71. What are different applications of FFs? Elaborate and justify.
72. Compare synchronous and asynchronous counter
73. Explain timing diagram of 5 bit ripple counter.
74. Design and realize 5 bit programmable UP/DOWN asynchronous and synchronous
counter.
75. Design BCD Counter?
76. What are advantages and disadvantages of ripple counters?
77. Why cascading of counters is required? Justify.
78. In a 4 stage ripple counter, the propagation delay of a FF is 50 ns. If the pulse width of
the strobe is 30 ns. Find the maximum frequency at which the counter operates reliably.
79. A binary ripple counter is required to count upto 16,383. How many FFs are required? If
the clock frequency is 8.192 MHz, what is the frequency at the output of MSB?
80. For what minimum value of propagation delay in each FF will a 10-bit ripple counter skip
a count when it is clocked at 10 MHz?
81. What are various asynchronous counter ICs available? Comment on specification sheet
of those counter ICs.
82. Why glitches occurs in synchronous counters? Elaborate. How to handle the same issue?
83. What is lock out condition in counters? How it is eliminated?
84. Design a J-K counter that goes through states 3, 4, 6, 7, and 3, … Is the counter self
starting?. Design a J-K counter that goes through states 3, 4, 6, 7, and 3, … Is the counter
self starting?. Modify the circuit such that whenever it goes to an invalid state, it should
come back to state 3.
85. Design a pulse train generator for the following sequence
011101110……
86. What are various synchronous counter ICs available? Comment on specification sheet of
those counter ICs.
87. How will you design and realize digital clock?
88. What is frequency counter? How will you design and use it in practical applications?
89. How will you classify shift register? Elaborate and justify with proper illustration.
90. What are various Shift registers ICs available? Comment on specification sheet of those
counter ICs.
91. How will you design and realize 5 bit bidirectional shift register?
92. What is ring counter? Design and realize 5 bit ring counter? What are practical
applications of ring counters?
93. What is Johnson counter? Design and realize 5 bit Johnson counter? What are practical
applications of Johnson counters?
94. How will you design a pulse train generator using shift register approach?
95. Design a sequence generator to generate the sequence ….1101011….use shift register
approach.
96. What is state machine and FSM?
97. What is Moore and Mealy state Machine? Where is it required? How and why?
98. Differentiate Mealy Machine vs. Moore Machine
99. Design and realize 2 bit multiplier.
100.
Design and realize 2 bit divider.