Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan DFT method for mixed-signal circuits: Analog test bus Adhoc Good design practices learnt through experience are used as guidelines: Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. Consider ATE requirements (tristates, etc.) Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. Boundary Scan Developed for testing chips on a printed circuit board (PCB). A chip with BS can be accessed for test from the edge connector of PCB. BS hardware added to chip: Test Access port (TAP) added Four test pins A test controller FSM A scan flip-flop added to each I/O pin. Standard is also known as JTAG (Joint Test Action Group) standard. Scan Design Techniques The set of design for testability guidelines presented above is a set of ad hoc methods to design random logic in respect with testability requirements. The scan design techniques are a set of structured approaches to design (for testability) the sequential circuits. The major difficulty in testing sequential circuits is determining the internal state of the circuit. Scan design techniques are directed at improving the controllability and observability of the internal states of a sequential circuit. By this the problem of testing a sequential circuit is reduced to that of testing a combinational circuit, since the internal states of the circuit are under control. 8.8.1 Scan Path The goal of the scan path technique is to reconfigure a sequential circuit, for the purpose of testing, into a combinational circuit. Since a sequential circuit is based on a combinational circuit and some storage elements, the technique of scan path consists in connecting together all the storage elements to form a long serial shift register. Thus the internal state of the circuit can be observed and controlled by shifting (scanning) out the contents of the storage elements. The shift register is then called a scan path. The storage elements can either be D, J-K, or R-S types of flip-flops, but simple latches cannot be used in scan path. However, the structure of storage elements is slightly different than classical ones. Generally the selection of the input source is achieved using a multiplexer on the data input controlled by an external mode signal. This multiplexer is integrated into the D-flip-flop, in our case; the D-flip-flop is then called MD-flip-flop (multiplexed-flip-flop). The sequential circuit containing a scan path has two modes of operation : a normal mode and a test mode which configure the storage elements in the scan path. In the normal mode, the storage elements are connected to the combinational circuit, in the loops of the global sequential circuit, which is considered then as a finite state machine. In the test mode, the loops are broken and the storage elements are connected together as a serial shift register (scan path), receiving the same clock signal. The input of the scan path is called scan-in and the output scan-out. Several scan paths can be implemented in one same complex circuit if it is necessary, though having several scan-in inputs and scan-out outputs. A large sequential circuit can be partitioned into sub-circuits, containing combinational subcircuits, associated with one scan path each. Efficiency of the test pattern generation for a combinational sub-circuit is greatly improved by partitioning, since its depth is reduced. Before applying test patterns, the shift register itself has to be verified by shifting in all ones i.e. 111...11, or zeros i.e. 000...00, and comparing. The method of testing a circuit with the scan path is as follows: 1. Set test mode signal, flip-flops accept data from input scan-in 2. Verify the scan path by shifting in and out test data 3. Set the shift register to an initial state 4. Apply a test pattern to the primary inputs of the circuit 5. Set normal mode, the circuit settles and can monitor the primary outputs of the circuit 6. Activate the circuit clock for one cycle 7. Return to test mode 8. Scan out the contents of the registers, simultaneously scan in the next pattern 8.8.2 Boundary Scan Test (BST) Boundary Scan Test (BST) is a technique involving scan path and self-testing techniques to resolve the problem of testing boards carrying VLSI integrated circuits and/or surface mounted devices (SMD). Printed circuit boards (PCB) are becoming very dense and complex, especially with SMD circuits, that most test equipment cannot guarantee a good fault coverage. [Click to enlarge image] Figure-8.27: BST consists in placing a scan path (shift register) adjacent to each component pin and to interconnect the cells in order to form a chain around the border of the circuit. The BST circuits contained on one board are then connected together to form a single path through the board. The boundary scan path is provided with serial input and output pads and appropriate clock pads which make it possible to : Test the interconnections between the various chip Deliver test data to the chips on board for self-testing Test the chips themselves with internal self-test The advantages of Boundary scan techniques are as follows : No need for complex testers in PCB testing Test engineers work is simplified and more efficient Time to spend on test pattern generation and application is reduced Fault coverage is greatly increased. BS Techniques are grouped by the IEEE Standard Organization in a "standard test access port and boundary scan architecture", namely IEEE P1149.1-1990. The Joint Test Action Group (JTAG), formed basically in 1986 at Philips, is an international committee composed of IC manufacturers who have set the technical development of the IEEE P1149 standard and promoted its use by all sectors of electronics industry. There are a number of different fault models that are commonly used. Stuck-At Test The most basic and common is the “stuck-at” fault model, which checks each node location in the design for either stuck-at-1 or stuck-at-0 logic behavior. For example, if a NAND gate in the design had an input pin shorted to ground (logic value 0) by a defect, the stuck-at-0 test for that node would catch it. The stuck-at model can also detect other defect types like bridges between two nets or nodes. The stuck-at model is classified as a static model because it is a slow speed test and is not dependent on gate timing (rise and fall times and propagation delay). At-Speed Test A second common type of fault model is called the “transition” or “at-speed” fault model, and is a dynamic fault model, i.e., it detects problems with timing. It is similar to the stuck-at model in that there are two faults for every node location in the design, classified as slow-torise and slow-to-fall faults. The transition fault model uses a test pattern that creates a transition stimulus to change the logic value from either 0-to-1 or from 1-to-0. The time allowed for the transition is specified, so if the transition doesn’t happen, or happens outside the allotted time, a timing defect is presumed. Path Delay Test The “path delay” model is also dynamic and performs at-speed tests on targeted timing critical paths. While stuck-at and transition fault models usually address all the nodes in the design, the path delay model only tests the exact paths specified by the engineer, who runs static timing analysis to determine which are the most critical paths. These paths are specified to the ATPG tool for creating the path delay test patterns. The theory is that if the most critical timing paths can pass the tests, then all the other paths with longer slack times should have no timing problems. In a way, path delay testing is a form of process check (e.g., showing timing errors if a process variable strays too far), in addition to a test for manufacturing defects on individual devices. IDDQ Test The IDDQ test relies on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values). Test patterns are used to place the DUT in a variety of selected states. By performing current measurements at each of these static states, the presence of defects that draw excess current can be detected. The value of Iddq testing is that many types of faults can be detected with very few patterns. The drawback is the additional test time to perform the current measurements. Toggle Test Toggle fault testing ensures that a node can be driven to both a logical 0 and a logical 1 value, and indicates the extent of your control over circuit nodes. Because the toggle fault model is faster and requires less overhead to run than stuck-at fault testing, you can experiment with different circuit configurations and get a quick indication of how much control you have over your circuit nodes. Because the toggle fault model only excites fault sites and does not propagate the responses to capture points, it cannot be used for defect detection. This fault model is sometimes used for burn-in testing to cause high activity in the circuit. Scan and ATPG Scan is the internal modification of the design’s circuitry to increase its test-ability. ATPG stands for Automatic Test Pattern Generation; as the name suggests, this is basically the generation of test patterns. In other words, we can say that Scan makes the process of pattern generation easier for detection of the faults we discussed earlier. Figure 3: A typical sequential circuit (before scan insertion) To test a fault we need to initialize the flops to the required values as we had shown while discussing about stuck-at faults and at-speed faults. In a bigger sequential circuit (without scan), it is difficult to control the flop’s value through primary inputs and observe the captured response in primary outputs. To solve this issue we do ‘Scan Insertion’ during synthesis. The goal of ‘Scan Insertion’ is to make a difficult-to-test sequential circuit behave (during testing process) like an easier-to-test combinational circuit. Achieving this goal involves two steps – 1. Converting Regular Flop to Scan Flop All the flops in the design are converted into scan flops (as shown in Figure 4), except – • The ones that are excluded by user. These are called non-scan flops. • The ones that have DFT DRC violation(s). Figure 4: Regular flop vs Scan flop 2. Stitching the Scan Flops to form Scan Chains The scan flops are stitched to form scan chain(s) (as shown in Figure 5). The number of scan chains depends upon various user inputs like – • Length of scan chain • Clock domain mixing • Power domain mixing • Voltage domain mixing Figure 5: A typical sequential circuit compatible for Scan and ATPG (after scan insertion) To initialize any flop to a value (refer the Figure 5), we simply make the SE = 1, such that SI to Q path is activated and we shift in the required values serially through a top level primary input called Scan-Input. Once the required values are loaded to the flops, we capture the values from combinational circuit by making SE = 0. And to observe the captured response we make the SE = 1 and serially shift out the captured data through a primary output called Scan-Output. Thus in a way, we can say the scan flop’s output (Q) act as pseudo primary output of the design and the scan flop’s input (D) act as pseudo primary inputs to the design, thereby making it a pseudo combination circuit. Once the patterns are generated, the expected response of the circuit for each pattern is obtained in pre-silicon. The expected responses along with the patterns are then stored in the memory of Automatic Test Equipment (ATE). In post-silicon, the manufactured chip is tested using the ATE, which loads the pattern and compares it with the expected response for pass or fail status.
0
You can add this document to your study collection(s)
Sign in Available only to authorized usersYou can add this document to your saved list
Sign in Available only to authorized users(For complaints, use another form )