TPDN65LPNV2OD3
TSMC 65nm
Standard I/O Library
Databook
Version 200A
December 21, 2009
Copyright c 2009 Taiwan Semiconductor Manufacturing Company Ltd.
All Rights Reserved
No part of this publication may be reproduced in whole or part by any means without the prior
written consent.
NOTICE
Taiwan Semiconductor Manufacturing Company Ltd. reserves the right to make changes in the
contents of this document without notice. No responsibility is assumed by Taiwan Semiconductor
Manufacturing Company Ltd. for any infringements of patents or other rights of the third parties
that may result from its use. Taiwan Semiconductor Manufacturing Company Ltd. assumes no
responsibility for any error that appears in this document.
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1.1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1.2
Characterization Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Timing Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.2.1
Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.2.2
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3
Cell Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
4
Simultaneously Switching Output Driving Factors . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
4.1
4.2
5
Terminologies and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.1
Simultaneously Switching Output (SSO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2
Simultaneously Switching Noise (SSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.3
Driving Index (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.4
Driving Factor (DF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DF Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Datasheet Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Cell Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
Leakage Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6
Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Design Kits Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Contact Us . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Datasheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1
PCLAMP1ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2
PCLAMP2ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.3
PDDW0204CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.4
PDDW0204SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.5
PDDW0408CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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8.6
PDDW0408SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.7
PDDW0812CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.8
PDDW0812SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.9
PDDW1216CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.10
PDDW1216SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.11
PDUW0204CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.12
PDUW0204SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.13
PDUW0408CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.14
PDUW0408SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.15
PDUW0812CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.16
PDUW0812SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.17
PDUW1216CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.18
PDUW1216SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.19
PRCUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.20
PRDW0204CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.21
PRDW0204SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.22
PRDW0408CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.23
PRDW0408SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.24
PRDW0812CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.25
PRDW0812SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.26
PRDW1216CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.27
PRDW1216SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.28
PRUW0204CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.29
PRUW0204SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.30
PRUW0408CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.31
PRUW0408SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.32
PRUW0812CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8.33
PRUW0812SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.34
PRUW1216CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.35
PRUW1216SCDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.36
PVDD1ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.37
PVDD1CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.38
PVDD2ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.39
PVDD2CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.40
PVDD2POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.41
PVSS1ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.42
PVSS1CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.43
PVSS2ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.44
PVSS2CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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8.45
PVSS3CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.46
PXOE1CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.47
PXOE2CDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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1
Introduction
This Databook provides basic information about the TPDN65LPNV2OD3 Standard I/O library.
The TPDN65LPNV2OD3 library is designed to optimize I/O performance with a core voltage of
1.2V, I/O voltage of 3.3V (typical case) in the TSMC 65nm 1.2V/2.5V Logic Low Power process.
Design engineers can refer to this book for DC characteristics, cell availability, cell descriptions,
datasheets, and so on.
Table 1.1 provides physical specifications about the TPDN65LPNV2OD3 library.
Table 1.1: Physical Specifications of Standard I/O
Design Dimension
Physical Dimension
I/O Height
120.0µm
I/O Width
50.0µm
Note: Please obtain the bonding pads from the TPBN65V bond pad library.
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2
Electrical Characteristics
2.1
DC Characteristics
The following tables summarize the DC characteristics and characterization conditions of the
TPDN65LPNV2OD3 Library.
2.1.1
Recommended Operating Conditions
Warning: Permanent damage could occur if the operation exceeds the ranges
listed in Table 2.1.
Table 2.1: Recommended Operating Conditions
Parameter
Min.
Nom.
Max.
Units
V
VDD
Pre-Driver Voltage
1.08
1.2
1.32
VDDP ST
Post-Driver Voltage
3.0
3.3
3.6
V
125
o
3.6
V
TJ
Junction Temperature
VIM AX
Maximum Input Voltage
-40
25
C
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2 Electrical Characteristics
Table 2.2: DC Characteristics
Parameter
Min.
VIL
Input Low Voltage
VIH
Max.
Units
-0.3
0.8
V
Input High Voltage
2
3.6
V
VT
Threshold Point
1.35
1.46
1.59
V
VT +
Schmitt Trigger Low to High Threshold Point
1.56
1.68
1.8
V
VT −
Schmitt Trigger High to Low Threshold Point
1.12
1.23
1.36
V
VTP U
Threshold Point with Pull-up Resistor Enabled
1.31
1.42
1.56
V
VTP D
Threshold Point with Pull-down Resistor Enabled
1.38
1.49
1.62
V
VT +
Schmitt Trigger Low to High Threshold Point with
Pull-up Resistor Enabled
1.53
1.64
1.76
V
VT −
Schmitt Trigger High to Low Threshold Point with
Pull-up Resistor Enabled
1.08
1.19
1.32
V
VT +
Schmitt Trigger Low to High Threshold Point with
Pull-down Resistor Enabled
1.58
1.71
1.84
V
VT −
Schmitt Trigger High to Low Threshold Point with
Pull-down Resistor Enabled
1.15
1.25
1.38
V
II
Input Leakage Current @ VI =3.3V or 0V
±10µ
A
IOZ
Tri-state Output Leakage Current @ VO =3.3V or 0V
±10µ
A
RP U
Pull-up Resistor
26K
38K
60K
Ω
RP D
Pull-down Resistor
28K
40K
69K
Ω
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage
IOL
Low Level Output Current @VOL (max)
PU
PU
PD
PD
IOH
Nom.
2.4
V
0204:02mA
3.6
5.5
7.4
mA
0204:04mA
7.3
11.1
14.8
mA
0408:04mA
7.3
11.2
15.0
mA
0408:08mA
10.9
16.7
22.4
mA
0812:08mA
11.0
16.8
22.5
mA
0812:12mA
14.6
22.3
29.9
mA
1216:12mA
14.7
22.4
30.0
mA
1216:16mA
18.3
27.9
37.4
mA
0204:02mA
5.6
11.3
19.3
mA
0204:04mA
11.1
22.5
38.6
mA
0408:04mA
11.1
22.5
38.6
mA
0408:08mA
16.7
33.8
57.9
mA
0812:08mA
16.6
33.7
57.8
mA
0812:12mA
22.2
45.0
77.1
mA
1216:12mA
22.2
45.0
77.0
mA
High Level Output Current @VOH (min)
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2 Electrical Characteristics
1216:16mA
TSMC Standard I/O TPDN65LPNV2OD3 Databook
27.8
56.2
96.3
mA
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2 Electrical Characteristics
2.1.2
Characterization Conditions
Timing information is characterized under conditions listed in Table 2.3.
Table 2.3: Characterization Conditions
Corner
Condition
TC
VDDcore = 1.2V
VDDIO = 3.3V
Temperature = 25o C
Device Name = TT, TT 33, TT hvt, TT na25, TT RES, TT DIO, TT DIO 33,
TT DIO ESD
BC
VDDcore = 1.32V
VDDIO = 3.6V
Temperature = 0o C
Device Name = FF, FF 33, FF hvt, FF na25, FF RES, FF DIO, FF DIO 33,
FF DIO ESD
WC
VDDcore = 1.08V
VDDIO = 3.0V
Temperature = 125o C
Device Name = SS, SS 33, SS hvt, SS na25, SS RES, SS DIO, SS DIO 33,
SS DIO ESD
LT
VDDcore = 1.32V
VDDIO = 3.6V
Temperature = -40o C
Device Name = FF, FF 33, FF hvt, FF na25, FF RES, FF DIO, FF DIO 33,
FF DIO ESD
WCZ
VDDcore = 1.08V
VDDIO = 3.0V
Temperature = 0o C
Device Name = SS, SS 33, SS hvt, SS na25, SS RES, SS DIO, SS DIO 33,
SS DIO ESD
WCL
VDDcore = 1.08V
VDDIO = 3.0V
Temperature = -40o C
Device Name = SS, SS 33, SS hvt, SS na25, SS RES, SS DIO, SS DIO 33,
SS DIO ESD
ML
VDDcore = 1.32V
VDDIO = 3.6V
Temperature = 125o C
Device Name = FF, FF 33, FF hvt, FF na25, FF RES, FF DIO, FF DIO 33,
FF DIO ESD
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2 Electrical Characteristics
2.2
Timing Information
2.2.1
Transition Time
Characterization is based on a “10-90” method; that is, the 10% and 90% points of the full output
swing are used to define the rise and fall transition as illustrated in Figure 2.1. Please refer to the
Synopsys .lib file for details.
90%
In
Out
10%
Full Output Swing
Rise Transition
Figure 2.1: The Transition Time
2.2.2
Propagation Delay
Two different propagation delays, tpLH and tpHL, represent the state change delay for low to high
and from high to low transitions.
The propagation delay is measured from the 50% point of the input waveform to the 50% point of
the output waveform as shown in Figure 2.2.
In
50%
tpHL
Out
50%
Figure 2.2: The Propagation Delay
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3
Cell Descriptions
This chapter provides cell list along with cell descriptions of I/O cells and power cut cells (if
available) of the TSMC TPDN65LPNV2OD3 library.
Table 3.1: Cell Descriptions
Cell Name
Functional Description
PCLAMP1ANA
ESD Clamp Cell for Core Voltage
PCLAMP2ANA
ESD Clamp Cell for I/O Voltage
PDDW0204CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
PDDW0204SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
PDDW0408CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
PDDW0408SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
PDDW0812CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
PDDW0812SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
PDDW1216CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
PDDW1216SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
PDUW0204CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PDUW0204SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
PDUW0408CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PDUW0408SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
PDUW0812CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PDUW0812SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
PDUW1216CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PDUW1216SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
Continued. . .
7 of 101
3 Cell Descriptions
Cell Name
Functional Description
PRCUT
Power-Cut Cell between Digital Domain A and Digital Domain B with
VSS Shorted and the Rest of Rails Cut
PRDW0204CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Down Resistor
PRDW0204SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Down Resistor
PRDW0408CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Down Resistor
PRDW0408SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Down Resistor
PRDW0812CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Down Resistor
PRDW0812SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Down Resistor
PRDW1216CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Down Resistor
PRDW1216SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Down Resistor
PRUW0204CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Up Resistor
PRUW0204SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PRUW0408CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Up Resistor
PRUW0408SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PRUW0812CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Up Resistor
PRUW0812SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PRUW1216CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and
Enable-Controlled Pull-Up Resistor
PRUW1216SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output,
Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PVDD1ANA
Dedicated Power Supply to Internal Macro with Core Voltage
PVDD1CDG
Vdd Pad for Core Power Supply
PVDD2ANA
Dedicated Power Supply to Internal Macro with I/O Voltage
PVDD2CDG
Power Pad for I/O Power Supply
PVDD2POC
Power-on Control Power Pad for I/O Power Supply
PVSS1ANA
Dedicated Ground Supply for PVDD1ANA
PVSS1CDG
Vss Pad for Core Ground Supply
PVSS2ANA
Dedicated Ground Supply for PVDD2ANA
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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3 Cell Descriptions
Cell Name
Functional Description
PVSS2CDG
Ground Pad for I/O Ground Supply
PVSS3CDG
Ground Pad for I/O and Core Ground Supply
PXOE1CDG
Crystal Oscillator Cell (High Enable, without Feedback Resistor)
PXOE2CDG
Crystal Oscillator Cell (High Enable, with Feedback Resistor)
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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4
Simultaneously Switching Output Driving
Factors
This chapter provides information about simultaneously switching output driving factors of the
TSMC TPDN65LPNV2OD3 library.
4.1
Terminologies and Definitions
This section describes basic terminologies and definitions of simultaneously switching output driving
factors.
4.1.1
Simultaneously Switching Output (SSO)
Simultaneously switching output (SSO) means that a certain number of I/O buffers switching at
the same time with the same direction (H → L, HZ → L or L → H, LZ → H), which would result
in noise on the power/ground lines because of the large dI/dt value and the parasitic inductance
of the bonding wire on the I/O power/ground cells.
4.1.2
Simultaneously Switching Noise (SSN)
SSN means the noise produced by the simultaneously switching output buffers. It would change the
voltage levels of power/ground nodes, so-called “Ground Bounce Effect”. Ground Bounce Effect is
tested at the device output by keeping one stable output at low “0” or high “1”, while all other
outputs of the device switch simultaneously. The noise occurred at the stable output node is called
“Quiet Output Switching“ (QOS). If the input low voltage is defined as Vil, the QOS of Vil is taken
to be the maximum noise that the system can endure.
4.1.3
Driving Index (DI)
DI is the maximum copies of the specific I/O cell switching from high to low simultaneously without
making the voltage on the quiet output “0” higher than “Vil ” when single ground cell is applied.
We take the QOS of “Vil ” as a criterion in defining DI because “1” has more noise margin than
“0”. For example, in LVTTL specification, the margin of “Vih ” (2.0V) to VD33 (3.3V) is 1.3V in
typical corner, which is higher than the margin of “Vil ” (0.8V) to ground (0V).
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4 Simultaneously Switching Output Driving Factors
4.1.4
Driving Factor (DF)
DF is the amount of how the specific output buffer contributes to the SSN on the power/ground
rail. The DF value of an output buffer is proportional to dI/dt, the derivative of the current on
the output buffer. We can obtain DF as follows:
DF = 1/DI
4.2
DF Values
This section provides circuit model parameters and DF values of the TPDN65LPNV2OD3 library.
Illustration of simulation model and calcuation instruction can be referenced from the TSMC
Universal Standard I/O Library General Application Note, which provides general information and
is available to download at TSMC Online.
Table 4.1 and Table 4.2 describe wire model and capacitive load of SSO simulations.
Table 4.1: R, L, C Wire Model
R(ohm)
L(nH)
C(pF)
0.3
2.1
4
0.3
5.2
4
0.3
7.8
4
0.3
10.5
4
Table 4.2: Capacitive Load
I/O Type
Cload (pF)
0204:02mA
5 15 30 50
0204:04mA
5 15 30 50
0408:04mA
5 15 30 50
0408:08mA
5 15 30 50
0812:08mA
5 15 30 50
0812:12mA
5 15 30 50
1216:12mA
5 15 30 50
1216:16mA
5 15 30 50
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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4 Simultaneously Switching Output Driving Factors
The following tables provide SSO DF value with respect to the bond wire inductance and the
capacitive load.
Characterization Corner: LT
Table 4.3: DF Table for Non-Slew-Rate Control Cell
I/O Type
0204:02mA
0204:04mA
0408:04mA
0408:08mA
0812:08mA
0812:12mA
1216:12mA
1216:16mA
C
5pF
H
HH
2.1nH
0.116
HH
L
15pF
30pF
50pF
0.073
0.054
0.043
5.2nH
0.243
0.137
0.096
0.075
7.8nH
0.324
0.182
0.125
0.095
10.5nH
0.397
0.225
0.151
0.114
2.1nH
0.289
0.169
0.117
0.090
5.2nH
0.570
0.334
0.215
0.158
7.8nH
0.727
0.440
0.285
0.206
10.5nH
0.873
0.543
0.352
0.251
2.1nH
0.328
0.185
0.127
0.097
5.2nH
0.609
0.353
0.225
0.166
7.8nH
0.772
0.464
0.297
0.213
10.5nH
0.921
0.561
0.364
0.257
2.1nH
0.496
0.289
0.188
0.141
5.2nH
0.900
0.559
0.364
0.256
7.8nH
1.223
0.715
0.485
0.341
10.5nH
1.381
0.853
0.580
0.413
2.1nH
0.539
0.311
0.200
0.148
5.2nH
0.951
0.581
0.375
0.263
7.8nH
1.263
0.734
0.498
0.347
10.5nH
1.418
0.870
0.591
0.419
2.1nH
0.675
0.423
0.271
0.194
5.2nH
1.292
0.774
0.528
0.370
7.8nH
1.619
0.984
0.674
0.491
10.5nH
2.629
1.251
0.798
0.586
2.1nH
0.728
0.442
0.282
0.203
5.2nH
1.333
0.794
0.537
0.374
7.8nH
1.657
1.119
0.683
0.496
10.5nH
2.685
1.262
0.805
0.589
2.1nH
0.857
0.556
0.364
0.255
5.2nH
1.648
0.991
0.680
0.498
7.8nH
3.224
1.319
0.869
0.634
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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4 Simultaneously Switching Output Driving Factors
I/O Type
HH C 5pF
HH
L
15pF
30pF
50pF
10.5nH
1.605
1.149
0.755
H
4.314
Table 4.4: DF Table for Slew-Rate Control Cell
I/O Type
0204:02mA
0204:04mA
0408:04mA
0408:08mA
0812:08mA
0812:12mA
1216:12mA
1216:16mA
C
5pF
H
HH
2.1nH
0.057
HH
L
15pF
30pF
50pF
0.044
0.037
0.032
5.2nH
0.146
0.096
0.072
0.058
7.8nH
0.210
0.132
0.095
0.074
10.5nH
0.269
0.167
0.116
0.089
2.1nH
0.176
0.107
0.078
0.063
5.2nH
0.389
0.239
0.161
0.123
7.8nH
0.541
0.341
0.227
0.167
10.5nH
0.666
0.435
0.291
0.211
2.1nH
0.071
0.051
0.039
0.033
5.2nH
0.184
0.127
0.090
0.074
7.8nH
0.274
0.185
0.132
0.111
10.5nH
0.356
0.246
0.182
0.150
2.1nH
0.180
0.105
0.071
0.058
5.2nH
0.365
0.235
0.171
0.141
7.8nH
0.499
0.341
0.267
0.218
10.5nH
0.614
0.449
0.365
0.295
2.1nH
0.063
0.048
0.038
0.033
5.2nH
0.160
0.123
0.100
0.084
7.8nH
0.239
0.186
0.154
0.130
10.5nH
0.314
0.253
0.211
0.178
2.1nH
0.198
0.118
0.076
0.057
5.2nH
0.371
0.240
0.171
0.136
7.8nH
0.494
0.332
0.252
0.207
10.5nH
0.595
0.421
0.337
0.281
2.1nH
0.085
0.068
0.055
0.046
5.2nH
0.221
0.170
0.141
0.122
7.8nH
0.325
0.254
0.216
0.186
10.5nH
0.424
0.340
0.292
0.252
2.1nH
0.202
0.127
0.086
0.066
5.2nH
0.378
0.260
0.200
0.168
7.8nH
0.505
0.365
0.296
0.254
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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4 Simultaneously Switching Output Driving Factors
I/O Type
HH C 5pF
HH
L
15pF
30pF
50pF
10.5nH
0.475
0.393
0.343
H
0.616
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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5
Datasheet Contents
This chapter provides information about the contents of the TSMC Standard I/O library datasheet.
5.1
Truth Table
The truth table lists all possible combinations of input and output signals for a cell. Table 5.1
defines all the symbols used in the datasheet truth table.
Table 5.1: Truth Table Symbols
Symbol
Definition
0
Logic Low
1
Logic High
0/1
Don’t care
-
Not Applicable
X
Unknown
Z
High Impedance
H
Pull-High
L
Pull-Low
The regular universal standard I/O Library contains dual driving cells. The driving ability of these
cells is controlled by DS pin. Table 5.2 defines the truth table of DS.
Table 5.2: Truth Table of DS pin
5.2
DS
Definition
0
Low-drive
1
High-drive
Cell Information
The cell information section provides information about the number of pads required.
15 of 101
5 Datasheet Contents
5.3
Leakage Power
The Leakage power section provides information about the standby leakage power from core power
and I/O power respectively.
5.4
Pin Capacitance
The pin capacitance table describes the typical loading at each pin of the cell (pF), corresponding
to each driving strength.
5.5
Propagation Delay
The propagation delay is a non-linear function of the loads. Using the 5 x 6 look-up table of the
Synopsys .lib file, three piece-wise linear functions are created to calculate propagation delays for
various load conditions. Each linear function has a dedicated linear equation, and three linear
equations are provided to model the delay. Each group equation in the table of propagation delay
is based on values extracted from the third row of the 5 x 6 look-up table for your reference. Three
groups of linear equations are defined as follows:
Group 1: Based on the first and second points of the load index, if a cell has a load that is less
than or equal to the second point of the load index, use the linear equation in Group 1 to calculate
the propagation delay.
Group 2: Based on the third and fourth points of the load index, if a cell has a load that is more
than the second point and less than the fifth point of the load index, use the linear equation in
Group 2 to calculate the propagation delay.
Group 3: Based on the fifth and sixth points of the load index, if a cell has a load that is more
than or equal to the fifth point of the load index, use the linear equation in Group 3 to calculate
the propagation delay.
A linear equation is formed in the following format:
D = Di + K ∗ Cload
where
D = propagationdelay(ns)
Di = cellintrinsic(unloaded)delay(ns)
K = delayf actor(ns/pF )
Cload = valueof outputload(pF )
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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5 Datasheet Contents
5.6
Example
The following is an example of datasheet.
PDIDGZ - (1)
Input Pad, High-Volt Tolerant - (2)
PAD
C
- (3)
Truth Table - (4)
INPUT OUTPUT
PAD
C
0
0
1
1
Cell Information - (5)
Value Unit
Pad Number
1
-
Leakage Power - (6)
Value Unit
VDD
1.4944 nW
VDDPST 1.1191 nW
Pin Capacitance - (7)
Value
Unit
PAD 3.4718
pF
Propagation Delay - (8)
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL 1.0140+0.2000*Cload 1.0170+0.1400*Cload 1.0250+0.100*Cload
PAD C TP LH 0.7023+0.2000*Cload 0.7034+0.1720*Cload 0.7065+0.1515*Cload
(1) Cell Name
(4) Truth Table
(7) Pin Capacitance
(2) Cell Description (5) Cell Information (8) Propagation Delay
(3) Cell Schematic
(6) Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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6
Design Kits Support
The following design kits/packages are delivered in a standard library release
Table 6.1: Deliverable Design Kits
Abbreviation
Description
rln
Release note
doc
Databook
nldm
Non-linear delay model
vlg
VerilogTM model
vit
VHDL/VitalTM model
ctc
CeltIC cdB view
mdt
MentorTM DFTAdvisorTM and FastscanTM model
apf/apt
Astro/ICC frame view, layout view and runset files
sef
SoC EncounterTM frame view, layout view and runset files
gds
GDSII layout views
spi
LVS netlists in CDLTM format
lpe
Layout parasitic extracted spice netlist
ibs
IBIS model
*cdk
Cell design kit
*vcn
MagamaTM VolcanoTM database
*cdk and vcn kits are only provided in N90 and more advanced technologies.
18 of 101
7
Contact Us
The TSMC standard I/O libraries are released under the supervision of the TSMC standard
quality assurance (QA) procedure. If you find any errors or encounter any problems with the
TPDN65LPNV2OD3 library, please contact your library distributor or TSMC regional application
engineers for immediate assistance.
19 of 101
8
Datasheets
20 of 101
PCLAMP1ANA
8.1
PCLAMP1ANA
ESD Clamp Cell for Core Voltage
VDDESD
PCLAMP
VSSESD
Cell Information
Value
Unit
1
-
Value
Unit
25.2402
nW
Pad Number
Leakage Power
VDDESD
Pin Capacitance
Value
Unit
VDDESD
4.0253
pF
VSSESD
7.8829
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PCLAMP2ANA
8.2
PCLAMP2ANA
ESD Clamp Cell for I/O Voltage
VDDESD
PCLAMP
VSSESD
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
VDDESD
Value
Unit
1.1583
nW
Pin Capacitance
Value
Unit
VDDESD
2.6471
pF
VSSESD
5.7931
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PDDW0204CDG
8.3
PDDW0204CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5046
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
23 of 101
PDDW0204CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0824
pF
OEN
0.0390
pF
PAD
2.4698
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1650*Cload
0.9648+0.1300*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.9650+0.0843*Cload
0.9690+0.0841*Cload
0.9760+0.0840*Cload
I PAD TP HL {DS}
0.9130+0.0422*Cload
0.9150+0.0421*Cload
0.9210+0.0420*Cload
I PAD TP LH {!DS}
0.9930+0.0657*Cload
0.9950+0.0656*Cload
1.0010+0.0655*Cload
I PAD TP LH {DS}
0.9750+0.0330*Cload
0.9790+0.0328*Cload
0.9790+0.0328*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5271
0.5271
0.5271
OEN PAD TP HZ {DS}
0.5910
0.5912
0.5913
OEN PAD TP LZ {!DS}
0.5823
0.5823
0.5823
OEN PAD TP LZ {DS}
0.6118
0.6118
0.6118
OEN PAD TP ZH {!DS}
1.0090+0.0657*Cload
1.0110+0.0656*Cload
1.0090+0.0656*Cload
OEN PAD TP ZH {DS}
0.9930+0.0329*Cload
0.9950+0.0328*Cload
0.9940+0.0328*Cload
OEN PAD TP ZL {!DS}
0.9630+0.0842*Cload
0.9660+0.0841*Cload
0.9650+0.0841*Cload
OEN PAD TP ZL {DS}
0.9130+0.0421*Cload
0.9160+0.0420*Cload
0.9180+0.0420*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6789+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
24 of 101
PDDW0204SCDG
8.4
PDDW0204SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Down
Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
25 of 101
PDDW0204SCDG
VDDPST
Value
Unit
5.6074
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0824
pF
OEN
0.0390
pF
PAD
2.4521
pF
PE
0.0462
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9783+0.1280*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1950*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.9670+0.0842*Cload
0.9660+0.0842*Cload
0.9690+0.0841*Cload
I PAD TP HL {DS}
0.9120+0.0423*Cload
0.9190+0.0420*Cload
0.9210+0.0420*Cload
I PAD TP LH {!DS}
0.9930+0.0657*Cload
0.9950+0.0656*Cload
1.0010+0.0655*Cload
I PAD TP LH {DS}
0.9750+0.0330*Cload
0.9790+0.0328*Cload
0.9790+0.0328*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5271
0.5271
0.5271
OEN PAD TP HZ {DS}
0.5910
0.5912
0.5913
OEN PAD TP LZ {!DS}
0.5823
0.5823
0.5823
OEN PAD TP LZ {DS}
0.6118
0.6118
0.6118
OEN PAD TP ZH {!DS}
1.0090+0.0657*Cload
1.0110+0.0656*Cload
1.0090+0.0656*Cload
OEN PAD TP ZH {DS}
0.9930+0.0329*Cload
0.9950+0.0328*Cload
0.9940+0.0328*Cload
OEN PAD TP ZL {!DS}
0.9640+0.0842*Cload
0.9660+0.0841*Cload
0.9660+0.0841*Cload
OEN PAD TP ZL {DS}
0.9130+0.0421*Cload
0.9130+0.0421*Cload
0.9180+0.0420*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9044+0.1280*Cload
0.9095+0.0970*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
26 of 101
PDDW0408CDG
8.5
PDDW0408CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5046
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
27 of 101
PDDW0408CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4523
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1650*Cload
0.9648+0.1300*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.8770+0.0420*Cload
0.8820+0.0418*Cload
0.8830+0.0418*Cload
I PAD TP HL {DS}
0.8870+0.0281*Cload
0.8890+0.0280*Cload
0.8950+0.0279*Cload
I PAD TP LH {!DS}
0.9300+0.0329*Cload
0.9330+0.0328*Cload
0.9340+0.0328*Cload
I PAD TP LH {DS}
0.9540+0.0221*Cload
0.9590+0.0219*Cload
0.9580+0.0219*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5692
0.5692
0.5692
OEN PAD TP HZ {DS}
0.6304
0.6305
0.6306
OEN PAD TP LZ {!DS}
0.6088
0.6088
0.6088
OEN PAD TP LZ {DS}
0.6372
0.6372
0.6373
OEN PAD TP ZH {!DS}
0.9480+0.0328*Cload
0.9490+0.0328*Cload
0.9500+0.0328*Cload
OEN PAD TP ZH {DS}
0.9710+0.0221*Cload
0.9750+0.0219*Cload
0.9740+0.0219*Cload
OEN PAD TP ZL {!DS}
0.8760+0.0419*Cload
0.8790+0.0418*Cload
0.8800+0.0418*Cload
OEN PAD TP ZL {DS}
0.8860+0.0281*Cload
0.8870+0.0280*Cload
0.8920+0.0279*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6789+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
28 of 101
PDDW0408SCDG
8.6
PDDW0408SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Down
Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
29 of 101
PDDW0408SCDG
VDDPST
Value
Unit
5.6074
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4877
pF
PE
0.0462
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9783+0.1280*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1950*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.8770+0.0420*Cload
0.8820+0.0418*Cload
0.8840+0.0418*Cload
I PAD TP HL {DS}
0.8870+0.0281*Cload
0.8890+0.0280*Cload
0.8950+0.0279*Cload
I PAD TP LH {!DS}
0.9300+0.0329*Cload
0.9330+0.0328*Cload
0.9340+0.0328*Cload
I PAD TP LH {DS}
0.9540+0.0221*Cload
0.9590+0.0219*Cload
0.9580+0.0219*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5692
0.5692
0.5692
OEN PAD TP HZ {DS}
0.6304
0.6305
0.6306
OEN PAD TP LZ {!DS}
0.6088
0.6088
0.6088
OEN PAD TP LZ {DS}
0.6372
0.6372
0.6373
OEN PAD TP ZH {!DS}
0.9480+0.0328*Cload
0.9490+0.0328*Cload
0.9500+0.0328*Cload
OEN PAD TP ZH {DS}
0.9710+0.0221*Cload
0.9750+0.0219*Cload
0.9740+0.0219*Cload
OEN PAD TP ZL {!DS}
0.8760+0.0419*Cload
0.8760+0.0419*Cload
0.8810+0.0418*Cload
OEN PAD TP ZL {DS}
0.8860+0.0281*Cload
0.8870+0.0280*Cload
0.8920+0.0279*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9044+0.1280*Cload
0.9095+0.0970*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
30 of 101
PDDW0812CDG
8.7
PDDW0812CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5046
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
31 of 101
PDDW0812CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4521
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9637+0.1650*Cload
0.9651+0.1280*Cload
0.9700+0.0980*Cload
IE C TP LH
0.7941+0.1950*Cload
0.7956+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8630+0.0279*Cload
0.8680+0.0278*Cload
0.8690+0.0278*Cload
I PAD TP HL {DS}
0.8860+0.0210*Cload
0.8900+0.0209*Cload
0.8910+0.0209*Cload
I PAD TP LH {!DS}
0.9240+0.0220*Cload
0.9270+0.0219*Cload
0.9270+0.0219*Cload
I PAD TP LH {DS}
0.9610+0.0164*Cload
0.9630+0.0164*Cload
0.9640+0.0164*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6095
0.6095
0.6095
OEN PAD TP HZ {DS}
0.6704
0.6705
0.6706
OEN PAD TP LZ {!DS}
0.6346
0.6346
0.6346
OEN PAD TP LZ {DS}
0.6644
0.6644
0.6644
OEN PAD TP ZH {!DS}
0.9430+0.0219*Cload
0.9430+0.0219*Cload
0.9430+0.0219*Cload
OEN PAD TP ZH {DS}
0.9750+0.0165*Cload
0.9790+0.0164*Cload
0.9800+0.0164*Cload
OEN PAD TP ZL {!DS}
0.8630+0.0278*Cload
0.8650+0.0278*Cload
0.8660+0.0278*Cload
OEN PAD TP ZL {DS}
0.8850+0.0210*Cload
0.8880+0.0209*Cload
0.8890+0.0209*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6789+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
32 of 101
PDDW0812SCDG
8.8
PDDW0812SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Down
Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
33 of 101
PDDW0812SCDG
VDDPST
Value
Unit
5.6074
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4521
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9769+0.1650*Cload
0.9783+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8116+0.1900*Cload
0.8131+0.1540*Cload
0.8171+0.1280*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8630+0.0279*Cload
0.8680+0.0278*Cload
0.8690+0.0278*Cload
I PAD TP HL {DS}
0.8860+0.0210*Cload
0.8900+0.0209*Cload
0.8910+0.0209*Cload
I PAD TP LH {!DS}
0.9240+0.0220*Cload
0.9270+0.0219*Cload
0.9270+0.0219*Cload
I PAD TP LH {DS}
0.9610+0.0164*Cload
0.9630+0.0164*Cload
0.9640+0.0164*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6095
0.6095
0.6095
OEN PAD TP HZ {DS}
0.6704
0.6705
0.6706
OEN PAD TP LZ {!DS}
0.6346
0.6346
0.6346
OEN PAD TP LZ {DS}
0.6644
0.6644
0.6644
OEN PAD TP ZH {!DS}
0.9430+0.0219*Cload
0.9430+0.0219*Cload
0.9430+0.0219*Cload
OEN PAD TP ZH {DS}
0.9750+0.0165*Cload
0.9790+0.0164*Cload
0.9800+0.0164*Cload
OEN PAD TP ZL {!DS}
0.8630+0.0278*Cload
0.8650+0.0278*Cload
0.8660+0.0278*Cload
OEN PAD TP ZL {DS}
0.8850+0.0210*Cload
0.8820+0.0210*Cload
0.8890+0.0209*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9044+0.1280*Cload
0.9095+0.0970*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
34 of 101
PDDW1216CDG
8.9
PDDW1216CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5046
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
35 of 101
PDDW1216CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4523
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1700*Cload
0.9650+0.1280*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8640+0.0209*Cload
0.8640+0.0209*Cload
0.8620+0.0209*Cload
I PAD TP HL {DS}
0.8900+0.0168*Cload
0.8960+0.0167*Cload
0.8970+0.0167*Cload
I PAD TP LH {!DS}
0.9360+0.0164*Cload
0.9380+0.0164*Cload
0.9390+0.0164*Cload
I PAD TP LH {DS}
0.9680+0.0132*Cload
0.9750+0.0131*Cload
0.9770+0.0131*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6495
0.6495
0.6495
OEN PAD TP HZ {DS}
0.7112
0.7113
0.7113
OEN PAD TP LZ {!DS}
0.6585
0.6585
0.6585
OEN PAD TP LZ {DS}
0.6905
0.6905
0.6905
OEN PAD TP ZH {!DS}
0.9520+0.0164*Cload
0.9540+0.0164*Cload
0.9550+0.0164*Cload
OEN PAD TP ZH {DS}
0.9850+0.0132*Cload
0.9910+0.0131*Cload
0.9930+0.0131*Cload
OEN PAD TP ZL {!DS}
0.8650+0.0208*Cload
0.8680+0.0208*Cload
0.8700+0.0208*Cload
OEN PAD TP ZL {DS}
0.8920+0.0167*Cload
0.8940+0.0167*Cload
0.8950+0.0167*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6788+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
36 of 101
PDDW1216SCDG
8.10
PDDW1216SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Down
Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
37 of 101
PDDW1216SCDG
VDDPST
Value
Unit
5.6074
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4522
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9782+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1950*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8640+0.0209*Cload
0.8640+0.0209*Cload
0.8730+0.0208*Cload
I PAD TP HL {DS}
0.8900+0.0168*Cload
0.8960+0.0167*Cload
0.8970+0.0167*Cload
I PAD TP LH {!DS}
0.9360+0.0164*Cload
0.9380+0.0164*Cload
0.9390+0.0164*Cload
I PAD TP LH {DS}
0.9680+0.0132*Cload
0.9750+0.0131*Cload
0.9770+0.0131*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6495
0.6495
0.6495
OEN PAD TP HZ {DS}
0.7112
0.7113
0.7113
OEN PAD TP LZ {!DS}
0.6585
0.6585
0.6585
OEN PAD TP LZ {DS}
0.6905
0.6905
0.6905
OEN PAD TP ZH {!DS}
0.9520+0.0164*Cload
0.9540+0.0164*Cload
0.9550+0.0164*Cload
OEN PAD TP ZH {DS}
0.9850+0.0132*Cload
0.9910+0.0131*Cload
0.9930+0.0131*Cload
OEN PAD TP ZL {!DS}
0.8650+0.0208*Cload
0.8680+0.0208*Cload
0.8600+0.0209*Cload
OEN PAD TP ZL {DS}
0.8900+0.0168*Cload
0.8940+0.0167*Cload
0.8950+0.0167*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9042+0.1300*Cload
0.9096+0.0965*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
38 of 101
PDUW0204CDG
8.11
PDUW0204CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5216
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
39 of 101
PDUW0204CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0824
pF
OEN
0.0390
pF
PAD
2.4521
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1650*Cload
0.9648+0.1300*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.9650+0.0843*Cload
0.9690+0.0841*Cload
0.9690+0.0841*Cload
I PAD TP HL {DS}
0.9130+0.0422*Cload
0.9190+0.0420*Cload
0.9210+0.0420*Cload
I PAD TP LH {!DS}
0.9930+0.0657*Cload
0.9950+0.0656*Cload
1.0010+0.0655*Cload
I PAD TP LH {DS}
0.9750+0.0330*Cload
0.9790+0.0328*Cload
0.9790+0.0328*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5271
0.5271
0.5271
OEN PAD TP HZ {DS}
0.5910
0.5912
0.5913
OEN PAD TP LZ {!DS}
0.5823
0.5823
0.5823
OEN PAD TP LZ {DS}
0.6118
0.6118
0.6118
OEN PAD TP ZH {!DS}
1.0090+0.0657*Cload
1.0110+0.0656*Cload
1.0090+0.0656*Cload
OEN PAD TP ZH {DS}
0.9930+0.0329*Cload
0.9950+0.0328*Cload
0.9940+0.0328*Cload
OEN PAD TP ZL {!DS}
0.9630+0.0842*Cload
0.9660+0.0841*Cload
0.9650+0.0841*Cload
OEN PAD TP ZL {DS}
0.9130+0.0421*Cload
0.9160+0.0420*Cload
0.9180+0.0420*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3469+0.1950*Cload
0.3485+0.1540*Cload
0.3525+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
40 of 101
PDUW0204SCDG
8.12
PDUW0204SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.6244
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
41 of 101
PDUW0204SCDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0824
pF
OEN
0.0390
pF
PAD
2.4698
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9783+0.1280*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1900*Cload
0.8130+0.1540*Cload
0.8170+0.1280*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.9670+0.0842*Cload
0.9700+0.0841*Cload
0.9690+0.0841*Cload
I PAD TP HL {DS}
0.9120+0.0423*Cload
0.9160+0.0421*Cload
0.9210+0.0420*Cload
I PAD TP LH {!DS}
0.9930+0.0657*Cload
0.9950+0.0656*Cload
1.0010+0.0655*Cload
I PAD TP LH {DS}
0.9750+0.0330*Cload
0.9790+0.0328*Cload
0.9790+0.0328*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5271
0.5271
0.5271
OEN PAD TP HZ {DS}
0.5910
0.5912
0.5913
OEN PAD TP LZ {!DS}
0.5823
0.5823
0.5823
OEN PAD TP LZ {DS}
0.6118
0.6118
0.6118
OEN PAD TP ZH {!DS}
1.0090+0.0657*Cload
1.0110+0.0656*Cload
1.0090+0.0656*Cload
OEN PAD TP ZH {DS}
0.9930+0.0329*Cload
0.9950+0.0328*Cload
0.9940+0.0328*Cload
OEN PAD TP ZL {!DS}
0.9640+0.0842*Cload
0.9660+0.0841*Cload
0.9660+0.0841*Cload
OEN PAD TP ZL {DS}
0.9130+0.0421*Cload
0.9130+0.0421*Cload
0.9180+0.0420*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
42 of 101
PDUW0408CDG
8.13
PDUW0408CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5216
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
43 of 101
PDUW0408CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4522
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1650*Cload
0.9648+0.1300*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.8770+0.0420*Cload
0.8820+0.0418*Cload
0.8840+0.0418*Cload
I PAD TP HL {DS}
0.8870+0.0281*Cload
0.8890+0.0280*Cload
0.8950+0.0279*Cload
I PAD TP LH {!DS}
0.9300+0.0329*Cload
0.9330+0.0328*Cload
0.9340+0.0328*Cload
I PAD TP LH {DS}
0.9540+0.0221*Cload
0.9590+0.0219*Cload
0.9590+0.0219*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5692
0.5692
0.5692
OEN PAD TP HZ {DS}
0.6304
0.6305
0.6306
OEN PAD TP LZ {!DS}
0.6088
0.6088
0.6088
OEN PAD TP LZ {DS}
0.6372
0.6372
0.6373
OEN PAD TP ZH {!DS}
0.9470+0.0329*Cload
0.9490+0.0328*Cload
0.9500+0.0328*Cload
OEN PAD TP ZH {DS}
0.9710+0.0221*Cload
0.9750+0.0219*Cload
0.9740+0.0219*Cload
OEN PAD TP ZL {!DS}
0.8760+0.0419*Cload
0.8790+0.0418*Cload
0.8810+0.0418*Cload
OEN PAD TP ZL {DS}
0.8860+0.0281*Cload
0.8870+0.0280*Cload
0.8920+0.0279*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3469+0.1950*Cload
0.3485+0.1540*Cload
0.3525+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
44 of 101
PDUW0408SCDG
8.14
PDUW0408SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.6244
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
45 of 101
PDUW0408SCDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4522
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9783+0.1280*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1900*Cload
0.8130+0.1540*Cload
0.8170+0.1280*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
0.8770+0.0420*Cload
0.8790+0.0419*Cload
0.8840+0.0418*Cload
I PAD TP HL {DS}
0.8870+0.0281*Cload
0.8890+0.0280*Cload
0.8950+0.0279*Cload
I PAD TP LH {!DS}
0.9300+0.0329*Cload
0.9330+0.0328*Cload
0.9340+0.0328*Cload
I PAD TP LH {DS}
0.9540+0.0221*Cload
0.9590+0.0219*Cload
0.9580+0.0219*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
0.5692
0.5692
0.5692
OEN PAD TP HZ {DS}
0.6304
0.6305
0.6306
OEN PAD TP LZ {!DS}
0.6088
0.6088
0.6088
OEN PAD TP LZ {DS}
0.6372
0.6373
0.6373
OEN PAD TP ZH {!DS}
0.9480+0.0328*Cload
0.9490+0.0328*Cload
0.9500+0.0328*Cload
OEN PAD TP ZH {DS}
0.9710+0.0221*Cload
0.9750+0.0219*Cload
0.9740+0.0219*Cload
OEN PAD TP ZL {!DS}
0.8760+0.0419*Cload
0.8760+0.0419*Cload
0.8810+0.0418*Cload
OEN PAD TP ZL {DS}
0.8860+0.0281*Cload
0.8870+0.0280*Cload
0.8920+0.0279*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
46 of 101
PDUW0812CDG
8.15
PDUW0812CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5216
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
47 of 101
PDUW0812CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4521
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9637+0.1650*Cload
0.9651+0.1280*Cload
0.9700+0.0980*Cload
IE C TP LH
0.7941+0.1900*Cload
0.7956+0.1540*Cload
0.7996+0.1280*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8630+0.0279*Cload
0.8680+0.0278*Cload
0.8690+0.0278*Cload
I PAD TP HL {DS}
0.8860+0.0210*Cload
0.8900+0.0209*Cload
0.8910+0.0209*Cload
I PAD TP LH {!DS}
0.9240+0.0220*Cload
0.9270+0.0219*Cload
0.9270+0.0219*Cload
I PAD TP LH {DS}
0.9610+0.0164*Cload
0.9630+0.0164*Cload
0.9640+0.0164*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6095
0.6095
0.6095
OEN PAD TP HZ {DS}
0.6704
0.6705
0.6706
OEN PAD TP LZ {!DS}
0.6346
0.6346
0.6346
OEN PAD TP LZ {DS}
0.6644
0.6644
0.6644
OEN PAD TP ZH {!DS}
0.9430+0.0219*Cload
0.9430+0.0219*Cload
0.9430+0.0219*Cload
OEN PAD TP ZH {DS}
0.9750+0.0165*Cload
0.9790+0.0164*Cload
0.9800+0.0164*Cload
OEN PAD TP ZL {!DS}
0.8630+0.0278*Cload
0.8650+0.0278*Cload
0.8660+0.0278*Cload
OEN PAD TP ZL {DS}
0.8850+0.0210*Cload
0.8880+0.0209*Cload
0.8890+0.0209*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3469+0.1950*Cload
0.3485+0.1540*Cload
0.3525+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
48 of 101
PDUW0812SCDG
8.16
PDUW0812SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.6244
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
49 of 101
PDUW0812SCDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4521
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9769+0.1650*Cload
0.9783+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8116+0.1900*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8630+0.0279*Cload
0.8680+0.0278*Cload
0.8690+0.0278*Cload
I PAD TP HL {DS}
0.8860+0.0210*Cload
0.8900+0.0209*Cload
0.8910+0.0209*Cload
I PAD TP LH {!DS}
0.9240+0.0220*Cload
0.9270+0.0219*Cload
0.9270+0.0219*Cload
I PAD TP LH {DS}
0.9610+0.0164*Cload
0.9630+0.0164*Cload
0.9640+0.0164*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6095
0.6095
0.6095
OEN PAD TP HZ {DS}
0.6704
0.6705
0.6706
OEN PAD TP LZ {!DS}
0.6346
0.6346
0.6346
OEN PAD TP LZ {DS}
0.6644
0.6644
0.6644
OEN PAD TP ZH {!DS}
0.9430+0.0219*Cload
0.9430+0.0219*Cload
0.9430+0.0219*Cload
OEN PAD TP ZH {DS}
0.9750+0.0165*Cload
0.9790+0.0164*Cload
0.9800+0.0164*Cload
OEN PAD TP ZL {!DS}
0.8630+0.0278*Cload
0.8650+0.0278*Cload
0.8670+0.0278*Cload
OEN PAD TP ZL {DS}
0.8850+0.0210*Cload
0.8820+0.0210*Cload
0.8890+0.0209*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
50 of 101
PDUW1216CDG
8.17
PDUW1216CDG
Dual-Driving Regular I/O Cell with Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.5216
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
51 of 101
PDUW1216CDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4523
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1700*Cload
0.9650+0.1280*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8640+0.0209*Cload
0.8640+0.0209*Cload
0.8620+0.0209*Cload
I PAD TP HL {DS}
0.8900+0.0168*Cload
0.8960+0.0167*Cload
0.8970+0.0167*Cload
I PAD TP LH {!DS}
0.9360+0.0164*Cload
0.9380+0.0164*Cload
0.9390+0.0164*Cload
I PAD TP LH {DS}
0.9680+0.0132*Cload
0.9750+0.0131*Cload
0.9770+0.0131*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6495
0.6495
0.6495
OEN PAD TP HZ {DS}
0.7112
0.7113
0.7113
OEN PAD TP LZ {!DS}
0.6585
0.6585
0.6585
OEN PAD TP LZ {DS}
0.6905
0.6905
0.6905
OEN PAD TP ZH {!DS}
0.9520+0.0164*Cload
0.9540+0.0164*Cload
0.9550+0.0164*Cload
OEN PAD TP ZH {DS}
0.9850+0.0132*Cload
0.9910+0.0131*Cload
0.9930+0.0131*Cload
OEN PAD TP ZL {!DS}
0.8650+0.0208*Cload
0.8680+0.0208*Cload
0.8700+0.0208*Cload
OEN PAD TP ZL {DS}
0.8900+0.0168*Cload
0.8940+0.0167*Cload
0.8950+0.0167*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3470+0.1900*Cload
0.3485+0.1540*Cload
0.3526+0.1280*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
52 of 101
PDUW1216SCDG
8.18
PDUW1216SCDG
Dual-Driving Regular I/O Cell with Schmitt Trigger Input, and Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
VDD
13.0572
nW
VDDPST
5.6244
nW
Pad Number
Leakage Power
TSMC Standard I/O TPDN65LPNV2OD3 Databook
53 of 101
PDUW1216SCDG
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0481
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4522
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9782+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1900*Cload
0.8131+0.1520*Cload
0.8167+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
0.8640+0.0209*Cload
0.8640+0.0209*Cload
0.8730+0.0208*Cload
I PAD TP HL {DS}
0.8900+0.0168*Cload
0.8960+0.0167*Cload
0.8970+0.0167*Cload
I PAD TP LH {!DS}
0.9360+0.0164*Cload
0.9380+0.0164*Cload
0.9390+0.0164*Cload
I PAD TP LH {DS}
0.9680+0.0132*Cload
0.9750+0.0131*Cload
0.9770+0.0131*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
0.6495
0.6495
0.6495
OEN PAD TP HZ {DS}
0.7112
0.7113
0.7113
OEN PAD TP LZ {!DS}
0.6585
0.6585
0.6585
OEN PAD TP LZ {DS}
0.6905
0.6905
0.6905
OEN PAD TP ZH {!DS}
0.9520+0.0164*Cload
0.9540+0.0164*Cload
0.9550+0.0164*Cload
OEN PAD TP ZH {DS}
0.9850+0.0132*Cload
0.9910+0.0131*Cload
0.9930+0.0131*Cload
OEN PAD TP ZL {!DS}
0.8650+0.0208*Cload
0.8680+0.0208*Cload
0.8600+0.0209*Cload
OEN PAD TP ZL {DS}
0.8900+0.0168*Cload
0.8940+0.0167*Cload
0.8950+0.0167*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
54 of 101
PRCUT
8.19
PRCUT
Power-Cut Cell between Digital Domain A and Digital Domain B with VSS Shorted and the Rest
of Rails Cut
TSMC Standard I/O TPDN65LPNV2OD3 Databook
55 of 101
PRDW0204CDG
8.20
PRDW0204CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled PullDown Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
56 of 101
PRDW0204CDG
VDDPST
Value
Unit
5.5046
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4520
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1700*Cload
0.9650+0.1280*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7941+0.1900*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.3660+0.0849*Cload
1.3800+0.0842*Cload
1.3840+0.0841*Cload
I PAD TP HL {DS}
1.0930+0.0434*Cload
1.1230+0.0421*Cload
1.1290+0.0420*Cload
I PAD TP LH {!DS}
1.4750+0.0684*Cload
1.5290+0.0660*Cload
1.5490+0.0656*Cload
I PAD TP LH {DS}
1.1500+0.0361*Cload
1.2080+0.0336*Cload
1.2410+0.0329*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
1.4460
1.4460
1.4460
OEN PAD TP HZ {DS}
1.4800
1.4800
1.4800
OEN PAD TP LZ {!DS}
1.4310
1.4310
1.4310
OEN PAD TP LZ {DS}
1.4540
1.4540
1.4540
OEN PAD TP ZH {!DS}
1.4840+0.0686*Cload
1.5400+0.0661*Cload
1.5640+0.0656*Cload
OEN PAD TP ZH {DS}
1.1490+0.0366*Cload
1.2150+0.0337*Cload
1.2540+0.0329*Cload
OEN PAD TP ZL {!DS}
1.3480+0.0853*Cload
1.3730+0.0842*Cload
1.3780+0.0841*Cload
OEN PAD TP ZL {DS}
1.0600+0.0442*Cload
1.1040+0.0423*Cload
1.1130+0.0421*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6789+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
57 of 101
PRDW0204SCDG
8.21
PRDW0204SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
58 of 101
PRDW0204SCDG
VDDPST
Value
Unit
5.6074
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4697
pF
PE
0.0462
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9782+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1950*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.3660+0.0849*Cload
1.3840+0.0841*Cload
1.3840+0.0841*Cload
I PAD TP HL {DS}
1.0930+0.0434*Cload
1.1200+0.0422*Cload
1.1290+0.0420*Cload
I PAD TP LH {!DS}
1.4750+0.0684*Cload
1.5290+0.0660*Cload
1.5490+0.0656*Cload
I PAD TP LH {DS}
1.1500+0.0361*Cload
1.2080+0.0336*Cload
1.2410+0.0329*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
1.4460
1.4460
1.4460
OEN PAD TP HZ {DS}
1.4800
1.4800
1.4800
OEN PAD TP LZ {!DS}
1.4310
1.4310
1.4310
OEN PAD TP LZ {DS}
1.4540
1.4540
1.4540
OEN PAD TP ZH {!DS}
1.4840+0.0686*Cload
1.5400+0.0661*Cload
1.5640+0.0656*Cload
OEN PAD TP ZH {DS}
1.1490+0.0366*Cload
1.2150+0.0337*Cload
1.2540+0.0329*Cload
OEN PAD TP ZL {!DS}
1.3470+0.0854*Cload
1.3700+0.0843*Cload
1.3790+0.0841*Cload
OEN PAD TP ZL {DS}
1.0590+0.0443*Cload
1.1010+0.0424*Cload
1.1140+0.0421*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9044+0.1280*Cload
0.9095+0.0970*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
59 of 101
PRDW0408CDG
8.22
PRDW0408CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled PullDown Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
60 of 101
PRDW0408CDG
VDDPST
Value
Unit
5.5042
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4520
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1650*Cload
0.9648+0.1300*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.8150+0.0467*Cload
1.8950+0.0431*Cload
1.9560+0.0419*Cload
I PAD TP HL {DS}
1.4290+0.0346*Cload
1.5440+0.0296*Cload
1.6160+0.0281*Cload
I PAD TP LH {!DS}
1.8980+0.0429*Cload
2.0210+0.0376*Cload
2.2090+0.0340*Cload
I PAD TP LH {DS}
1.4300+0.0320*Cload
1.5670+0.0261*Cload
1.7150+0.0233*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
2.8180
2.8180
2.8180
OEN PAD TP HZ {DS}
2.8480
2.8480
2.8480
OEN PAD TP LZ {!DS}
2.6880
2.6880
2.6880
OEN PAD TP LZ {DS}
2.7100
2.7100
2.7100
OEN PAD TP ZH {!DS}
1.6930+0.0483*Cload
1.9080+0.0391*Cload
2.1530+0.0344*Cload
OEN PAD TP ZH {DS}
1.2070+0.0357*Cload
1.3810+0.0283*Cload
1.6120+0.0239*Cload
OEN PAD TP ZL {!DS}
1.5180+0.0530*Cload
1.6890+0.0456*Cload
1.8510+0.0424*Cload
OEN PAD TP ZL {DS}
1.1380+0.0387*Cload
1.2880+0.0322*Cload
1.4570+0.0289*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6789+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
61 of 101
PRDW0408SCDG
8.23
PRDW0408SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
62 of 101
PRDW0408SCDG
VDDPST
Value
Unit
5.6074
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4874
pF
PE
0.0462
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9783+0.1280*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1950*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.8150+0.0467*Cload
1.8950+0.0431*Cload
1.9570+0.0419*Cload
I PAD TP HL {DS}
1.4310+0.0345*Cload
1.5480+0.0295*Cload
1.6160+0.0281*Cload
I PAD TP LH {!DS}
1.8980+0.0429*Cload
2.0210+0.0376*Cload
2.2090+0.0340*Cload
I PAD TP LH {DS}
1.4300+0.0320*Cload
1.5670+0.0261*Cload
1.7150+0.0233*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
2.8180
2.8180
2.8180
OEN PAD TP HZ {DS}
2.8480
2.8480
2.8480
OEN PAD TP LZ {!DS}
2.6880
2.6880
2.6880
OEN PAD TP LZ {DS}
2.7100
2.7100
2.7100
OEN PAD TP ZH {!DS}
1.6930+0.0483*Cload
1.9080+0.0391*Cload
2.1530+0.0344*Cload
OEN PAD TP ZH {DS}
1.2070+0.0357*Cload
1.3810+0.0283*Cload
1.6120+0.0239*Cload
OEN PAD TP ZL {!DS}
1.5180+0.0530*Cload
1.6890+0.0456*Cload
1.8510+0.0424*Cload
OEN PAD TP ZL {DS}
1.1380+0.0387*Cload
1.2920+0.0321*Cload
1.4570+0.0289*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9044+0.1280*Cload
0.9095+0.0970*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
63 of 101
PRDW0812CDG
8.24
PRDW0812CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled PullDown Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
64 of 101
PRDW0812CDG
VDDPST
Value
Unit
5.5046
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.5050
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9637+0.1650*Cload
0.9651+0.1280*Cload
0.9700+0.0980*Cload
IE C TP LH
0.7941+0.1950*Cload
0.7956+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.6110+0.0335*Cload
2.8150+0.0291*Cload
2.8930+0.0282*Cload
I PAD TP HL {DS}
2.0720+0.0276*Cload
2.2920+0.0229*Cload
2.4350+0.0213*Cload
I PAD TP LH {!DS}
2.7030+0.0313*Cload
2.9440+0.0261*Cload
3.1170+0.0242*Cload
I PAD TP LH {DS}
2.0150+0.0264*Cload
2.2810+0.0207*Cload
2.4680+0.0186*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
4.5050
4.5050
4.5050
OEN PAD TP HZ {DS}
4.5340
4.5340
4.5340
OEN PAD TP LZ {!DS}
4.2480
4.2480
4.2480
OEN PAD TP LZ {DS}
4.2690
4.2690
4.2690
OEN PAD TP ZH {!DS}
2.0640+0.0381*Cload
2.4930+0.0289*Cload
2.8170+0.0253*Cload
OEN PAD TP ZH {DS}
1.3570+0.0314*Cload
1.7270+0.0235*Cload
2.0330+0.0201*Cload
OEN PAD TP ZL {!DS}
1.8520+0.0401*Cload
2.2110+0.0324*Cload
2.4540+0.0297*Cload
OEN PAD TP ZL {DS}
1.3210+0.0327*Cload
1.6430+0.0258*Cload
1.8840+0.0231*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6789+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
65 of 101
PRDW0812SCDG
8.25
PRDW0812SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
66 of 101
PRDW0812SCDG
VDDPST
Value
Unit
5.6074
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4518
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9769+0.1650*Cload
0.9783+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8116+0.1900*Cload
0.8131+0.1540*Cload
0.8171+0.1280*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.6110+0.0335*Cload
2.8150+0.0291*Cload
2.8930+0.0282*Cload
I PAD TP HL {DS}
2.0720+0.0276*Cload
2.2920+0.0229*Cload
2.4350+0.0213*Cload
I PAD TP LH {!DS}
2.7030+0.0313*Cload
2.9440+0.0261*Cload
3.1170+0.0242*Cload
I PAD TP LH {DS}
2.0150+0.0264*Cload
2.2810+0.0207*Cload
2.4680+0.0186*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
4.5050
4.5050
4.5050
OEN PAD TP HZ {DS}
4.5340
4.5340
4.5340
OEN PAD TP LZ {!DS}
4.2480
4.2480
4.2480
OEN PAD TP LZ {DS}
4.2690
4.2690
4.2690
OEN PAD TP ZH {!DS}
2.0640+0.0381*Cload
2.4930+0.0289*Cload
2.8170+0.0253*Cload
OEN PAD TP ZH {DS}
1.3570+0.0314*Cload
1.7270+0.0235*Cload
2.0330+0.0201*Cload
OEN PAD TP ZL {!DS}
1.8520+0.0401*Cload
2.2110+0.0324*Cload
2.4550+0.0297*Cload
OEN PAD TP ZL {DS}
1.3210+0.0327*Cload
1.6430+0.0258*Cload
1.8840+0.0231*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9044+0.1280*Cload
0.9095+0.0970*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
67 of 101
PRDW1216CDG
8.26
PRDW1216CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled PullDown Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
68 of 101
PRDW1216CDG
VDDPST
Value
Unit
5.5046
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4519
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1700*Cload
0.9650+0.1280*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.8930+0.0277*Cload
3.1090+0.0231*Cload
3.2780+0.0212*Cload
I PAD TP HL {DS}
2.4040+0.0239*Cload
2.6050+0.0197*Cload
2.7940+0.0176*Cload
I PAD TP LH {!DS}
2.9670+0.0278*Cload
3.2170+0.0225*Cload
3.4240+0.0202*Cload
I PAD TP LH {DS}
2.3180+0.0241*Cload
2.5620+0.0189*Cload
2.7790+0.0165*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
5.8540
5.8540
5.8540
OEN PAD TP HZ {DS}
5.8800+0.0001*Cload
5.8830
5.8830
OEN PAD TP LZ {!DS}
4.9380+0.0001*Cload
4.9410
4.9410
OEN PAD TP LZ {DS}
4.9610
4.9610
4.9610
OEN PAD TP ZH {!DS}
2.1230+0.0364*Cload
2.6030+0.0261*Cload
2.9910+0.0218*Cload
OEN PAD TP ZH {DS}
1.3650+0.0317*Cload
1.7880+0.0227*Cload
2.1590+0.0186*Cload
OEN PAD TP ZL {!DS}
1.8090+0.0342*Cload
2.1680+0.0265*Cload
2.4300+0.0236*Cload
OEN PAD TP ZL {DS}
1.3440+0.0296*Cload
1.6750+0.0225*Cload
1.9360+0.0196*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6788+0.1650*Cload
0.6804+0.1280*Cload
0.6857+0.0965*Cload
PAD C TP LH
0.3464+0.1950*Cload
0.3479+0.1560*Cload
0.3519+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
69 of 101
PRDW1216SCDG
8.27
PRDW1216SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Down Resistor
IE
C
PE
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
L
0
0/1
1
0/1
Z
1
1
L
L
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
70 of 101
PRDW1216SCDG
VDDPST
Value
Unit
5.6075
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.5227
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9782+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1950*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.8930+0.0277*Cload
3.1160+0.0230*Cload
3.2780+0.0212*Cload
I PAD TP HL {DS}
2.4020+0.0240*Cload
2.6050+0.0197*Cload
2.7940+0.0176*Cload
I PAD TP LH {!DS}
2.9670+0.0278*Cload
3.2170+0.0225*Cload
3.4240+0.0202*Cload
I PAD TP LH {DS}
2.3180+0.0241*Cload
2.5620+0.0189*Cload
2.7790+0.0165*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
5.8540
5.8540
5.8540
OEN PAD TP HZ {DS}
5.8800+0.0001*Cload
5.8830
5.8830
OEN PAD TP LZ {!DS}
4.9380+0.0001*Cload
4.9410
4.9410
OEN PAD TP LZ {DS}
4.9610
4.9610
4.9610
OEN PAD TP ZH {!DS}
2.1220+0.0364*Cload
2.6030+0.0261*Cload
2.9910+0.0218*Cload
OEN PAD TP ZH {DS}
1.3650+0.0317*Cload
1.7880+0.0227*Cload
2.1590+0.0186*Cload
OEN PAD TP ZL {!DS}
1.8090+0.0342*Cload
2.1680+0.0265*Cload
2.4310+0.0236*Cload
OEN PAD TP ZL {DS}
1.3440+0.0296*Cload
1.6750+0.0225*Cload
1.9360+0.0196*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9028+0.1650*Cload
0.9042+0.1300*Cload
0.9096+0.0965*Cload
PAD C TP LH
0.5776+0.1900*Cload
0.5792+0.1520*Cload
0.5828+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
71 of 101
PRUW0204CDG
8.28
PRUW0204CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled Pull-Up
Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
72 of 101
PRUW0204CDG
VDDPST
Value
Unit
5.5216
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4520
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1700*Cload
0.9650+0.1280*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.3660+0.0849*Cload
1.3840+0.0841*Cload
1.3840+0.0841*Cload
I PAD TP HL {DS}
1.0930+0.0434*Cload
1.1230+0.0421*Cload
1.1290+0.0420*Cload
I PAD TP LH {!DS}
1.4750+0.0684*Cload
1.5260+0.0661*Cload
1.5490+0.0656*Cload
I PAD TP LH {DS}
1.1500+0.0361*Cload
1.2080+0.0336*Cload
1.2410+0.0329*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
1.4460
1.4460
1.4460
OEN PAD TP HZ {DS}
1.4800
1.4800
1.4800
OEN PAD TP LZ {!DS}
1.4310
1.4310
1.4310
OEN PAD TP LZ {DS}
1.4540
1.4540
1.4540
OEN PAD TP ZH {!DS}
1.4830+0.0687*Cload
1.5400+0.0661*Cload
1.5640+0.0656*Cload
OEN PAD TP ZH {DS}
1.1490+0.0366*Cload
1.2150+0.0337*Cload
1.2540+0.0329*Cload
OEN PAD TP ZL {!DS}
1.3480+0.0853*Cload
1.3730+0.0842*Cload
1.3780+0.0841*Cload
OEN PAD TP ZL {DS}
1.0600+0.0442*Cload
1.1040+0.0423*Cload
1.1210+0.0420*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3469+0.1950*Cload
0.3485+0.1540*Cload
0.3525+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
73 of 101
PRUW0204SCDG
8.29
PRUW0204SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
74 of 101
PRUW0204SCDG
VDDPST
Value
Unit
5.6244
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4697
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9782+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1900*Cload
0.8130+0.1540*Cload
0.8170+0.1280*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.3660+0.0849*Cload
1.3840+0.0841*Cload
1.3840+0.0841*Cload
I PAD TP HL {DS}
1.0930+0.0434*Cload
1.1200+0.0422*Cload
1.1290+0.0420*Cload
I PAD TP LH {!DS}
1.4750+0.0684*Cload
1.5290+0.0660*Cload
1.5490+0.0656*Cload
I PAD TP LH {DS}
1.1500+0.0361*Cload
1.2080+0.0336*Cload
1.2410+0.0329*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
1.4460
1.4460
1.4460
OEN PAD TP HZ {DS}
1.4800
1.4800
1.4800
OEN PAD TP LZ {!DS}
1.4310
1.4310
1.4310
OEN PAD TP LZ {DS}
1.4540
1.4540
1.4540
OEN PAD TP ZH {!DS}
1.4840+0.0686*Cload
1.5400+0.0661*Cload
1.5640+0.0656*Cload
OEN PAD TP ZH {DS}
1.1490+0.0366*Cload
1.2150+0.0337*Cload
1.2540+0.0329*Cload
OEN PAD TP ZL {!DS}
1.3470+0.0854*Cload
1.3700+0.0843*Cload
1.3790+0.0841*Cload
OEN PAD TP ZL {DS}
1.0590+0.0443*Cload
1.1010+0.0424*Cload
1.1140+0.0421*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
75 of 101
PRUW0408CDG
8.30
PRUW0408CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled Pull-Up
Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
76 of 101
PRUW0408CDG
VDDPST
Value
Unit
5.5212
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4520
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1650*Cload
0.9648+0.1300*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.8150+0.0467*Cload
1.8950+0.0431*Cload
1.9560+0.0419*Cload
I PAD TP HL {DS}
1.4310+0.0345*Cload
1.5440+0.0296*Cload
1.6160+0.0281*Cload
I PAD TP LH {!DS}
1.8980+0.0429*Cload
2.0210+0.0376*Cload
2.2090+0.0340*Cload
I PAD TP LH {DS}
1.4300+0.0320*Cload
1.5670+0.0261*Cload
1.7150+0.0233*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
2.8180
2.8180
2.8180
OEN PAD TP HZ {DS}
2.8480
2.8480
2.8480
OEN PAD TP LZ {!DS}
2.6880
2.6880
2.6880
OEN PAD TP LZ {DS}
2.7100
2.7100
2.7100
OEN PAD TP ZH {!DS}
1.6930+0.0483*Cload
1.9080+0.0391*Cload
2.1530+0.0344*Cload
OEN PAD TP ZH {DS}
1.2070+0.0357*Cload
1.3810+0.0283*Cload
1.6120+0.0239*Cload
OEN PAD TP ZL {!DS}
1.5180+0.0530*Cload
1.6890+0.0456*Cload
1.8510+0.0424*Cload
OEN PAD TP ZL {DS}
1.1380+0.0387*Cload
1.2880+0.0322*Cload
1.4570+0.0289*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3469+0.1950*Cload
0.3485+0.1540*Cload
0.3525+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
77 of 101
PRUW0408SCDG
8.31
PRUW0408SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
78 of 101
PRUW0408SCDG
VDDPST
Value
Unit
5.6245
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4874
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9783+0.1280*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1900*Cload
0.8130+0.1540*Cload
0.8170+0.1280*Cload
Timing Arc
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
I PAD TP HL {!DS}
1.8150+0.0467*Cload
1.8950+0.0431*Cload
1.9570+0.0419*Cload
I PAD TP HL {DS}
1.4310+0.0345*Cload
1.5480+0.0295*Cload
1.6160+0.0281*Cload
I PAD TP LH {!DS}
1.8980+0.0429*Cload
2.0210+0.0376*Cload
2.2090+0.0340*Cload
I PAD TP LH {DS}
1.4300+0.0320*Cload
1.5670+0.0261*Cload
1.7150+0.0233*Cload
(< 20.0000)pf
(20.0000-70.0000)pf
(> 70.0000)pf
OEN PAD TP HZ {!DS}
2.8180
2.8180
2.8180
OEN PAD TP HZ {DS}
2.8480
2.8480
2.8480
OEN PAD TP LZ {!DS}
2.6880
2.6880
2.6880
OEN PAD TP LZ {DS}
2.7100
2.7100
2.7100
OEN PAD TP ZH {!DS}
1.6930+0.0483*Cload
1.9080+0.0391*Cload
2.1530+0.0344*Cload
OEN PAD TP ZH {DS}
1.2070+0.0357*Cload
1.3810+0.0283*Cload
1.6120+0.0239*Cload
OEN PAD TP ZL {!DS}
1.5180+0.0530*Cload
1.6890+0.0456*Cload
1.8510+0.0424*Cload
OEN PAD TP ZL {DS}
1.1380+0.0387*Cload
1.2920+0.0321*Cload
1.4570+0.0289*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
79 of 101
PRUW0812CDG
8.32
PRUW0812CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled Pull-Up
Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
80 of 101
PRUW0812CDG
VDDPST
Value
Unit
5.5216
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4518
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9637+0.1650*Cload
0.9651+0.1280*Cload
0.9700+0.0980*Cload
IE C TP LH
0.7941+0.1900*Cload
0.7956+0.1540*Cload
0.7996+0.1280*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.6110+0.0335*Cload
2.8150+0.0291*Cload
2.8930+0.0282*Cload
I PAD TP HL {DS}
2.0720+0.0276*Cload
2.2920+0.0229*Cload
2.4350+0.0213*Cload
I PAD TP LH {!DS}
2.7030+0.0313*Cload
2.9440+0.0261*Cload
3.1170+0.0242*Cload
I PAD TP LH {DS}
2.0150+0.0264*Cload
2.2810+0.0207*Cload
2.4680+0.0186*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
4.5050
4.5050
4.5050
OEN PAD TP HZ {DS}
4.5340
4.5340
4.5340
OEN PAD TP LZ {!DS}
4.2480
4.2480
4.2480
OEN PAD TP LZ {DS}
4.2690
4.2690
4.2690
OEN PAD TP ZH {!DS}
2.0640+0.0381*Cload
2.4930+0.0289*Cload
2.8170+0.0253*Cload
OEN PAD TP ZH {DS}
1.3570+0.0314*Cload
1.7270+0.0235*Cload
2.0330+0.0201*Cload
OEN PAD TP ZL {!DS}
1.8520+0.0401*Cload
2.2110+0.0324*Cload
2.4540+0.0297*Cload
OEN PAD TP ZL {DS}
1.3210+0.0327*Cload
1.6430+0.0258*Cload
1.8840+0.0231*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3469+0.1950*Cload
0.3485+0.1540*Cload
0.3525+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
81 of 101
PRUW0812SCDG
8.33
PRUW0812SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
82 of 101
PRUW0812SCDG
VDDPST
Value
Unit
5.6244
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4518
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9769+0.1650*Cload
0.9783+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8116+0.1900*Cload
0.8130+0.1540*Cload
0.8169+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.6110+0.0335*Cload
2.8150+0.0291*Cload
2.8930+0.0282*Cload
I PAD TP HL {DS}
2.0720+0.0276*Cload
2.2920+0.0229*Cload
2.4350+0.0213*Cload
I PAD TP LH {!DS}
2.7030+0.0313*Cload
2.9440+0.0261*Cload
3.1170+0.0242*Cload
I PAD TP LH {DS}
2.0150+0.0264*Cload
2.2810+0.0207*Cload
2.4680+0.0186*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
4.5050
4.5050
4.5050
OEN PAD TP HZ {DS}
4.5340
4.5340
4.5340
OEN PAD TP LZ {!DS}
4.2480
4.2480
4.2480
OEN PAD TP LZ {DS}
4.2690
4.2690
4.2690
OEN PAD TP ZH {!DS}
2.0640+0.0381*Cload
2.4930+0.0289*Cload
2.8170+0.0253*Cload
OEN PAD TP ZH {DS}
1.3570+0.0314*Cload
1.7270+0.0235*Cload
2.0330+0.0201*Cload
OEN PAD TP ZL {!DS}
1.8520+0.0401*Cload
2.2110+0.0324*Cload
2.4550+0.0297*Cload
OEN PAD TP ZL {DS}
1.3210+0.0327*Cload
1.6430+0.0258*Cload
1.8840+0.0231*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
83 of 101
PRUW1216CDG
8.34
PRUW1216CDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, and Enable-Controlled Pull-Up
Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
84 of 101
PRUW1216CDG
VDDPST
Value
Unit
5.5216
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.4519
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9634+0.1700*Cload
0.9650+0.1280*Cload
0.9698+0.0985*Cload
IE C TP LH
0.7940+0.1950*Cload
0.7955+0.1540*Cload
0.7994+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.8930+0.0277*Cload
3.1090+0.0231*Cload
3.2780+0.0212*Cload
I PAD TP HL {DS}
2.4020+0.0240*Cload
2.6050+0.0197*Cload
2.7940+0.0176*Cload
I PAD TP LH {!DS}
2.9670+0.0278*Cload
3.2170+0.0225*Cload
3.4240+0.0202*Cload
I PAD TP LH {DS}
2.3180+0.0241*Cload
2.5620+0.0189*Cload
2.7790+0.0165*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
5.8540
5.8540
5.8540
OEN PAD TP HZ {DS}
5.8800+0.0001*Cload
5.8830
5.8830
OEN PAD TP LZ {!DS}
4.9380+0.0001*Cload
4.9410
4.9410
OEN PAD TP LZ {DS}
4.9610
4.9610
4.9610
OEN PAD TP ZH {!DS}
2.1230+0.0364*Cload
2.6030+0.0261*Cload
2.9910+0.0218*Cload
OEN PAD TP ZH {DS}
1.3650+0.0317*Cload
1.7880+0.0227*Cload
2.1590+0.0186*Cload
OEN PAD TP ZL {!DS}
1.8090+0.0342*Cload
2.1680+0.0265*Cload
2.4310+0.0236*Cload
OEN PAD TP ZL {DS}
1.3440+0.0296*Cload
1.6750+0.0225*Cload
1.9360+0.0196*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.6794+0.1650*Cload
0.6807+0.1300*Cload
0.6861+0.0965*Cload
PAD C TP LH
0.3470+0.1900*Cload
0.3485+0.1540*Cload
0.3526+0.1280*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
85 of 101
PRUW1216SCDG
8.35
PRUW1216SCDG
Dual-Driving Regular I/O Cell with Slew Rate Controlled Output, Schmitt Trigger Input, and
Enable-Controlled Pull-Up Resistor
PE
IE
C
PAD
DS
I
OEN
Truth Table
INPUT
OUTPUT
DS
OEN
I
PAD
PE
IE
PAD
C
0/1
0
0
-
0/1
0
0
0
0/1
0
0
-
0/1
1
0
0
0/1
0
1
-
0/1
0
1
0
0/1
0
1
-
0/1
1
1
1
0/1
1
0/1
0
0/1
0
-
0
0/1
1
0/1
0
0/1
1
-
0
0/1
1
0/1
1
0/1
0
-
0
0/1
1
0/1
1
0/1
1
-
1
0/1
1
0/1
Z
0
0
-
0
0/1
1
0/1
Z
0
1
-
X
0/1
1
0/1
Z
1
0
H
0
0/1
1
0/1
Z
1
1
H
H
Cell Information
Value
Unit
1
-
Value
Unit
13.0572
nW
Pad Number
Leakage Power
VDD
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
86 of 101
PRUW1216SCDG
VDDPST
Value
Unit
5.6245
nW
Pin Capacitance
Value
Unit
DS
0.0462
pF
I
0.0480
pF
IE
0.0825
pF
OEN
0.0390
pF
PAD
2.5227
pF
PE
0.0414
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
IE C TP HL
0.9768+0.1650*Cload
0.9782+0.1300*Cload
0.9845+0.0950*Cload
IE C TP LH
0.8115+0.1900*Cload
0.8131+0.1520*Cload
0.8167+0.1285*Cload
Timing Arc
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
I PAD TP HL {!DS}
2.8940+0.0277*Cload
3.1160+0.0230*Cload
3.2780+0.0212*Cload
I PAD TP HL {DS}
2.4020+0.0240*Cload
2.6050+0.0197*Cload
2.7940+0.0176*Cload
I PAD TP LH {!DS}
2.9670+0.0278*Cload
3.2170+0.0225*Cload
3.4240+0.0202*Cload
I PAD TP LH {DS}
2.3180+0.0241*Cload
2.5620+0.0189*Cload
2.7790+0.0165*Cload
(< 40.0000)pf
(40.0000-100.0000)pf
(> 100.0000)pf
OEN PAD TP HZ {!DS}
5.8540
5.8540
5.8540
OEN PAD TP HZ {DS}
5.8800+0.0001*Cload
5.8830
5.8830
OEN PAD TP LZ {!DS}
4.9380+0.0001*Cload
4.9410
4.9410
OEN PAD TP LZ {DS}
4.9610
4.9610
4.9610
OEN PAD TP ZH {!DS}
2.1230+0.0364*Cload
2.6030+0.0261*Cload
2.9910+0.0218*Cload
OEN PAD TP ZH {DS}
1.3650+0.0317*Cload
1.7880+0.0227*Cload
2.1590+0.0186*Cload
OEN PAD TP ZL {!DS}
1.8090+0.0342*Cload
2.1680+0.0265*Cload
2.4310+0.0236*Cload
OEN PAD TP ZL {DS}
1.3440+0.0296*Cload
1.6750+0.0225*Cload
1.9360+0.0196*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
PAD C TP HL
0.9033+0.1650*Cload
0.9048+0.1280*Cload
0.9102+0.0965*Cload
PAD C TP LH
0.5779+0.1950*Cload
0.5795+0.1540*Cload
0.5834+0.1285*Cload
Timing Arc
TSMC Standard I/O TPDN65LPNV2OD3 Databook
87 of 101
PVDD1ANA
8.36
PVDD1ANA
Dedicated Power Supply to Internal Macro with Core Voltage
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
AVDD
Value
Unit
19.7594
nW
Pin Capacitance
AVDD
Value
Unit
3.6778
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVDD1CDG
8.37
PVDD1CDG
Vdd Pad for Core Power Supply
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
VDD
Value
Unit
19.7594
nW
Pin Capacitance
VDD
Value
Unit
3.7159
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVDD2ANA
8.38
PVDD2ANA
Dedicated Power Supply to Internal Macro with I/O Voltage
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
AVDD
Value
Unit
0.5488
nW
Pin Capacitance
AVDD
Value
Unit
3.5310
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVDD2CDG
8.39
PVDD2CDG
Power Pad for I/O Power Supply
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
VDDPST
Value
Unit
1.7934
nW
Pin Capacitance
VDDPST
Value
Unit
2.3348
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVDD2POC
8.40
PVDD2POC
Power-on Control Power Pad for I/O Power Supply
Cell Information
Value
Unit
1
-
Value
Unit
15813.6000
nW
Pad Number
Leakage Power
VDDPST
Pin Capacitance
VDDPST
Value
Unit
2.2581
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVSS1ANA
8.41
PVSS1ANA
Dedicated Ground Supply for PVDD1ANA
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
VDDPST
Value
Unit
0.1814
nW
Pin Capacitance
AVSS
Value
Unit
1.9292
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVSS1CDG
8.42
PVSS1CDG
Vss Pad for Core Ground Supply
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
Value
Unit
VDD
0.0261
nW
VDDPST
0.1944
nW
Pin Capacitance
VSS
Value
Unit
2.3522
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVSS2ANA
8.43
PVSS2ANA
Dedicated Ground Supply for PVDD2ANA
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
VDDPST
Value
Unit
0.1814
nW
Pin Capacitance
AVSS
Value
Unit
1.9292
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
95 of 101
PVSS2CDG
8.44
PVSS2CDG
Ground Pad for I/O Ground Supply
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
VDDPST
Value
Unit
0.1944
nW
Pin Capacitance
VSSPST
Value
Unit
0.7556
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PVSS3CDG
8.45
PVSS3CDG
Ground Pad for I/O and Core Ground Supply
VSS
Cell Information
Value
Unit
1
-
Pad Number
Leakage Power
VDDPST
Value
Unit
0.1944
nW
Pin Capacitance
VSS
Value
Unit
1.1084
pF
TSMC Standard I/O TPDN65LPNV2OD3 Databook
97 of 101
PXOE1CDG
8.46
PXOE1CDG
Crystal Oscillator Cell (High Enable, without Feedback Resistor)
XE
XC
XI
XO
Truth Table
INPUT
OUTPUT
XE
XI
XO
XC
0
0/1
1
0
1
0
1
0
1
1
0
1
Cell Information
Value
Unit
2
-
Pad Number
Leakage Power
Value
Unit
VDD
5.4791
nW
VDDPST
5.3683
nW
Pin Capacitance
Value
Unit
XE
0.0427
pF
XI
2.2505
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 10.0000)pf
(10.0000-25.0000)pf
(> 25.0000)pf
XE XO TP HL
1.8050+0.0260*Cload
1.8070+0.0258*Cload
1.8070+0.0258*Cload
XE XO TP LH
1.1960+0.2000*Cload
1.2170+0.1982*Cload
1.2260+0.1978*Cload
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
98 of 101
PXOE1CDG
Group1
Group2
Group3
Timing Arc
(< 10.0000)pf
(10.0000-25.0000)pf
(> 25.0000)pf
XI XO TP HL
0.6566+0.0295*Cload
0.7060+0.0252*Cload
0.7220+0.0244*Cload
XI XO TP LH
0.9460+0.0274*Cload
0.9920+0.0234*Cload
1.0140+0.0224*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
XO XC TP HL
0.4968+0.2400*Cload
0.4992+0.1800*Cload
0.5077+0.1265*Cload
XO XC TP LH
0.5661+0.2900*Cload
0.5691+0.2140*Cload
0.5823+0.1355*Cload
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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PXOE2CDG
8.47
PXOE2CDG
Crystal Oscillator Cell (High Enable, with Feedback Resistor)
XE
XC
XI
XO
Truth Table
INPUT
OUTPUT
XE
XI
XO
XC
0
0/1
1
0
1
0
1
0
1
1
0
1
Cell Information
Value
Unit
2
-
Pad Number
Leakage Power
Value
Unit
5.4791
nW
7594.8238
nW
VDD
VDDPST
Pin Capacitance
Value
Unit
XE
0.0427
pF
XI
2.2656
pF
Propagation Delay
Group1
Group2
Group3
Timing Arc
(< 10.0000)pf
(10.0000-25.0000)pf
(> 25.0000)pf
XE XO TP HL
1.8050+0.0260*Cload
1.8080+0.0258*Cload
1.8080+0.0258*Cload
XE XO TP LH
1.1980+0.1998*Cload
1.2140+0.1984*Cload
1.2260+0.1978*Cload
Continued. . .
TSMC Standard I/O TPDN65LPNV2OD3 Databook
100 of 101
PXOE2CDG
Group1
Group2
Group3
Timing Arc
(< 10.0000)pf
(10.0000-25.0000)pf
(> 25.0000)pf
XI XO TP HL
0.6568+0.0295*Cload
0.7100+0.0250*Cload
0.7220+0.0244*Cload
XI XO TP LH
0.9460+0.0274*Cload
0.9920+0.0234*Cload
1.0140+0.0224*Cload
Timing Arc
(< 0.0300)pf
(0.0300-0.3000)pf
(> 0.3000)pf
XO XC TP HL
0.4968+0.2400*Cload
0.4992+0.1800*Cload
0.5078+0.1265*Cload
XO XC TP LH
0.5661+0.2900*Cload
0.5691+0.2140*Cload
0.5823+0.1355*Cload
TSMC Standard I/O TPDN65LPNV2OD3 Databook
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