Chapter 7 Solutions
7.1.
E
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Subtract
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
OutE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Z
D2 + D0
Z
D2 - D0
Z
D2 + D0
Z
D2 - D0
Z
D3 + D0
Z
D3 - D0
Z
D2 + D1
Z
D2 - D1
7.5.
a)
32 clock cycles
b) 11 clock cycles
module Summation (
input Clock, Reset,
output reg [7:0] Output
);
parameter s0=0, s1=1; // Declare state encodings
reg [2:0]state;
reg [7:0]sum;
reg [7:0]i;
always @ (posedge Clock or posedge Reset) begin
if (Reset == 1) begin
sum <= 0;
i <= 1;
Output <= 0;
state <= s0;
end
else begin
case (state)
s0: begin
sum <= sum + i;
i <= i + 1;
Output <= 0;
if (i != 10)
state <= s0;
else
101
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state <= s1;
end
s1: begin
Output <= sum;
state <= s1;
end
default: begin
Output <= 0;
state <= s0;
end
endcase
end
end
endmodule
7.6.
1
2
3
4
5
i = 0
WHILE (i ≠ 10){
i = i + 1
OUTPUT i
}
Algorithm
'1'
+
iLoad
Clear
Clock
D3-0
Load 4-bit Register
Clear
i
Clock Q3-0
i3
(i ≠ 10)
4
i0
Out
Output
Datapath
102
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Control
Word
1
2
3
Instruction
iLoad
Clear
Out
i=0
i=i+1
OUTPUT i
0
1
0
1
0
0
0
0
1
Control words
Control Word 1
i=0
(i ≠ 10)
Control Word 2
i=i+1
Current State
Q 1Q 0
s0
s0 00
s1 01
s2 10
s3 11
(i ≠ 10)'
s1
(i ≠ 10)
Next State
Q1next Q0next
(i ≠ 10)' (i ≠ 10)
s3 11
s1 01
s2 10
s2 10
s3 11
s1 01
s3 11
s3 11
Next-state table
Control Word 3
OUTPUT i
s2
Current State
Q 1Q 0
(i ≠ 10)'
Halt
00
01
10
11
s3
State diagram
Implementation
D1 D0
(i ≠ 10)' (i ≠ 10)
11
01
10
10
11
01
11
11
Implementation table
D0
D1
(i ≠ 10)
0
Q1Q0
(i ≠ 10)
0
1
(i ≠ 10)'
00
1
Q0
01
Q1Q0
1
00
1
01
1
1
11
1
1
10
1
1
Q0'
11
1
1
10
1
1
Q1
Q0next D0 = Q1 + Q0'
Q1next = D1 = (i ≠ 10)' + Q0
K-maps and Next-state equations
Q 1Q 0
00
01
10
11
iLoad
0
1
0
0
Clear
1
0
0
0
Out
0
0
1
0
iLoad = Q1'Q0
Clear = Q1'Q0'
Out = Q1Q0'
Output table
Output equations
103
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Status Signal from
the Datapath
Next-state
Logic
State
Memory
Output Logic and
Control Signals to the Datapath
(i ≠ 10)
D1
Q1
iLoad
Clk
Clear
Clear
Q'1
Out
D0
Q0
Clk
Clear
Clock
Reset
Q'0
Control unit circuit
7.7.
1
2
3
4
5
6
7
sum = 0
INPUT n
WHILE (n ≠ 0){
sum = sum + n
n = n - 1
}
OUTPUT sum
Algorithm
Control
Word
1
2
3
4
5
Instruction
sum = 0
INPUT n
sum = sum + n
n=n–1
OUTPUT sum
IE
15
0
1
0
0
×
WE
14
1
1
1
1
0
WA1,0
13–12
00
01
00
01
××
RAE
11
1
0
1
1
1
RAA1,0
10–9
00
××
00
01
00
RBE
8
1
0
1
0
0
RBA1,0
7–6
00
××
01
××
××
ALU2,1,0
5–3
101 (subtract)
×××
100 (add)
111 (decrement)
000 (pass)
SH1,0
2–1
00
××
00
00
00
OE
0
0
0
0
0
1
Control words
104
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Current State
Q 2Q 1Q 0
Start'
Control Word 1
sum = 0
s0
Start
Control Word 2
INPUT n
s1
(n ≠ 0)'
(n ≠ 0)
000
001
010
011
100
101
110
111
(n ≠ 0)'
Control Word 5
OUTPUT sum
s4
State diagram
Implementation table
D2
Q2 = 0
Start, (n ≠ 0)
Q1Q0
00
01
11
D1
Q2 = 1
10
00
Implementation
D2 D1 D0
Start, (n ≠ 0)
00
01
10
11
000 000 001 001
100 010 100 010
011 011 011 011
100 010 100 010
100 100 100 100
000 000 000 000
000 000 000 000
000 000 000 000
Current State
Q 2Q 1Q 0
Control Word 4
n=n−1
s3
00
01
11
10
1
1
1
1
Q2 = 0
Start, (n ≠ 0)
Q1Q0
00
01
11
Q2 = 1
10
00
01
11
00
01
1
1
01
1
1
11
1
1
11
1
1
1
1
10
10
Q2'Q0(n ≠ 0)'
11
s1 001
s2 010
s3 011
s2 010
s4 100
s0 000
s0 000
s0 000
Next-state table
Control Word 3
sum = sum + n
s2
(n ≠ 0)
00
s0 000
s4 100
s3 011
s4 100
s4 100
s0 000
s0 000
s0 000
s0 000
s1 001
s2 010
s3 011
s4 100
Unused 101
Unused 110
Unused 111
Next State
Q2next Q1next Q0next
Start, (n ≠ 0)
01
10
s0 000 s1 001
s2 010 s4 100
s3 011 s3 011
s2 010 s4 100
s4 100 s4 100
s0 000 s0 000
s0 000 s0 000
s0 000 s0 000
Q2Q1'Q0'
1
Q2'Q1Q0'
Q2next = D2 = Q2Q1'Q0' + Q2'Q0(n ≠ 0)'
1
Q2'Q0(n ≠ 0)
Q1next = D1 = Q2'Q1Q0' + Q2'Q0(n ≠ 0)
105
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10
D0
Q2 = 0
Start, (n ≠ 0)
Q1Q0
00
01
11
10
1
1
1
1
00
Q2 = 1
00
01
11
10
01
11
10
1
1
Q2'Q1Q0'
Q2'Q0'Start
Q0next = D0 = Q2'Q1Q0' + Q2'Q0'Start
K-maps and Next-state equations
State
Q 2Q 1Q 0
000
001
010
011
100
101
110
111
IE
WE
WA1
WA0
RAE
RAA1
RAA0
RBE
RBA1
RBA0
ALU2
ALU1
ALU0
SH1
SH0
OE
15
0
1
0
0
×
0
0
0
14
1
1
1
1
0
0
0
0
13
0
0
0
0
×
0
0
0
12
0
1
0
1
×
0
0
0
11
1
0
1
1
1
0
0
0
10
0
×
0
0
0
0
0
0
9
0
×
0
1
0
0
0
0
8
1
0
1
0
0
0
0
0
7
0
×
0
×
×
0
0
0
6
0
×
1
×
×
0
0
0
5
1
×
1
1
0
0
0
0
4
0
×
0
1
0
0
0
0
3
1
×
0
1
0
0
0
0
2
0
×
0
0
0
0
0
0
1
0
×
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Output table
IE
= Q2'Q1'Q0
WE = Q2'
WA1 = 0
WA0 = Q2'Q0
RAE = Q2'Q1 + Q1'Q0'
RAA1 = 0
RAA0 = Q2'Q1Q0
RBE = Q2'Q0'
RBA1 = 0
RBA0 = Q2'Q1Q0'
ALU2 = Q2'Q0' + Q2'Q1
ALU1 = Q2'Q1Q0
ALU0 = Q2'Q1'Q0' + Q2'Q1Q0
SH1 = 0
SH0 = 0
OE = Q2Q1'Q0'
Output equations
106
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Next-state
Logic
Start
State
Memory
Output Logic and
Control Signals to the Datapath
Control
Input
RBE
IE
D2
Q2
0
Clk
Clear
WA1
ALU2
WA0
ALU1
RAE
ALU0
Q1
Clk
Clear
D0
Q'1
Q0
0
Clk
Clear
Clock
Reset
RBA0
Q'2
0
D1
RBA1
WE
0
RAA1
Q'0
RAA0
SH1
SH0
OE
(n ≠ 0)
Status Signal from
the Datapath
Done
Control
Output
Control unit circuit
7.8.
Input
8
LoadX
LoadY
Clear
Clock
(X>Y)
SelX
D7-0
Load 8-bit register
Clear
X
Q7-0
D7-0
Load 8-bit register
Clear
Y
Q7-0
>
1
0
OutE
Output
107
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7.18.
Input_N
8
Shift_N
Load_N
Clear
Clock
Shift
D
Load 8-bit shifter
Clear with load
N
8
Neq0
8
N0eq1
N0
4-bit
Count
Clear up counter
Q3 Q2 Q1 Q0
Count
Output
Datapath
000 input N
001
(N = 0)' &
(N(0) = 1)
Count = Count + 1 010
N = N >> 1
(N = 0)
100 output (Count = 4)
(N = 0)' &
(N(0) = 1)'
011
N = N >> 1
State diagram
Current State
Q 2Q 1Q 0
000
001
010
011
100
Next State Q2next Q1next Q0next
(N=0), (N(0)=1)
00
01
10
11
001
001
001
001
011
010
100
100
001
001
001
001
001
001
001
001
100
100
100
100
Next-state table
108
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D2
Q2 = 0
(N=0),(N(0)=1)
Q1Q0
00 01 11 10
Q2 = 1
00
01
11
10
1
1
1
1
00
01
1
Q2Q1'Q0'
Q2'Q1'Q0 (N=0)
1
11
10
Q2next = D2 = Q2Q1'Q0' + Q2'Q1'Q0 (N=0)
D1
Q2 = 0
(N=0),(N(0)=1)
Q1Q0
00 01 11 10
Q2 = 1
00
01
11
10
00
01
1
Q2'Q1'Q0 (N=0)'
1
11
10
Q1next = D1 = Q2'Q1'Q0 (N=0)'
D0
Q2 = 0
(N=0),(N(0)=1)
Q1Q0
00 01 11 10
00
1
01
1
11
1
1
1
1
10
1
1
1
1
1
1
Q2 = 1
00
01
11
10
1
Q2'Q0'
Q2' (N=0)' (N(0)=1)'
Q2'Q1
Q0next = D0 = Q2'Q0' + Q2' (N=0)' (N(0)=1)' + Q2'Q1
K-maps and Next-state equations
Control
Word
0
1
2
3
4
State
Q2 Q1 Q0
000
001
010
011
100
Instruction
Input N
none
Count = Count + 1, N = N >> 1
N = N >> 1
Output (Count = 4)
Load_N
1
0
0
0
0
Shift_N
0
0
1
1
0
Count
0
0
1
0
0
Done
0
0
0
0
1
Control words and Output table
Load_N = Q2'Q1'Q0'
Shift_N = Q1
Count = Q2'Q1Q0'
Done = Q2
Output equations
109
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D2
Load_N
Q2
Shift_N
Clk
Clr Q'2
Count
Done
D1
Q1
Clk
Clr
Q'1
D0
Q0
Clk
Clr
Clock
Reset
Q'0
Neq0
N0eq1
Control unit circuit
Input X
8
Input_N
Shift_N
Load_N
Count
Control
Signals
Shift_N
Load_N
Count
CU
Clock
Reset
Clock
Reset
DP
Neq0
N0eq1
Status
Signals
Neq0
N0eq1
Clock
Reset
Done
Output
Done
Output
Dedicated microprocessor
7.19.
Excitation equations / Next-state equations:
Q1next = D1 = Q0 + (Z≠0)'
Q0next = D0 = Q1 + Q0'
110
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Output equations:
ClrX = LoadY = inZ = Q1'Q0'
LoadX = stat1 = Q1'Q0
LoadZ = Q0'
subtract = Q1Q0'
Next-state table / Output table:
Current
State
Q 1Q 0
00
01
10
11
Next State
Q1next Q0next
(Z≠0) = 0
(Z≠0) = 1
11
01
10
10
11
01
11
11
Outputs
ClrX
1
0
0
0
LoadX
0
1
0
0
LoadY
1
0
0
0
LoadZ
1
0
1
0
inZ
1
0
0
0
stat1
0
1
0
0
subtract
0
0
1
0
State diagram:
0
(Z≠0)
ClrX=0
LoadX=1
LoadY=0
LoadZ=0
inZ=0
stat1=1
subtract=0
ClrX=1
LoadX=0
LoadY=1
LoadZ=1
inZ=1
stat1=0
subtract=0
(Z≠0)'
1
3
(Z≠0)
(Z≠0)'
2
ClrX=0
LoadX=0
LoadY=0
LoadZ=1
inZ=0
stat1=0
subtract=1
ClrX=0
LoadX=0
LoadY=0
LoadZ=0
inZ=0
stat1=0
subtract=0
State 0:
X=0
Y=4
input Z
State 1:
X=X+Y
State 2:
Z=Z–1
State 3:
none
111
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Algorithm: Outputs 4 × Z, where Z is an input value.
X = 0
Y = 4
input Z
while (Z ≠ 0){
X = X + Y
Z = Z – 1
}
7.20.
input
1
zMux
zLoad
yLoad
xLoad
wLoad
Clear
Clock
8
0
D7-0
Load 8-bit register
Clear
z
Clock Q7-0
D7-0
Load 8-bit register
Clear
y
Clock Q7-0
D7-0
Load 8-bit register
Clear
x
Clock Q7-0
8
D7-0
Load 8-bit register
Clear
w
Clock Q7-0
8
8
8
(z ≠ 0)
z0
(z is odd)
'1' '2'
3 2 1 0
LOp1-0
1
s1-0
0
ROp
8
8
+/-
Subtract
Control
Word
1
2
3
4
5
6
Instruction
w = 0, x = 0, y = 0
INPUT z
w=w–2
x=x+2
y=y+1
z=z–1
zMux
zLoad
yLoad
xLoad
wLoad
Clear
LOp1-0
ROp
Subtract
×
1
×
×
×
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
××
××
00
01
10
11
×
××
0
0
1
1
×
×
1
0
0
1
112
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7.23.
A possible datapath:
swSet
jClear
1-bit
register
jCount
4-bit
counter
swapped
AddrSel
swClear
j
swapped
0
(j<10)
ASel
4
Address
memWr
<10
0
memory
A
j-1Wr
4-bit
register
j-1
A[j-1]Wr
4-bit
register
A[j]Wr
A[j-1]
(A[j-1] > A[j]
4-bit
register
A[j]
>
A possible state diagram:
AddrSel = 0
A[j]Wr = 1
AddrSel = 1
A[j-1]Wr = 1
s3
s4
(A[j-1] > A[j])
AddrSel = 0
s5
ASel = 1
memWr = 1
(A[j-1] > A[j])'
(j<10)' &
(swapped)'
(j<10)
s1
s2
jClear = 1
swClear = 1
s6
j-1Wr = 1
jCount = 1
AddrSel = 1
ASel = 0
memWr = 1
swSet = 1
(j<10)' &
(swapped)
s7
113
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114
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