2023 Second International Conference On Smart Technologies For Smart Nation (SmartTechCon) | 979-8-3503-0541-8/23/$31.00 ©2023 IEEE | DOI: 10.1109/SmartTechCon57526.2023.10391333
High-Speed Communication in Memory Controller
by Novel Pipeline Register Design
T. R. Dinesh Kumar
Department of Electronics and
Communication Engineering,
VelTech HighTech Dr.Rangarajan
Dr.Sakunthala Engineering College,
Chennai, Tamil Nadu, India
trdineshkumar@velhightech.com
S. Sivasaravana Babu
Department of Electronics and
Communication Engineering,
VelTech HighTech Dr.Rangarajan
Dr.Sakunthala Engineering College,
Chennai, Tamil Nadu, India
sivasaravanababu@velhightech.com
M. Sherrif
Department of Electronics and
Communication Engineering,
VelTech HighTech Dr.Rangarajan
Dr.Sakunthala Engineering College,
Chennai, Tamil Nadu, India
msherrif@velhightech.com
Konda Mahendra Babu
Department of Electronics and
Communication Engineering,
VelTech HighTech Dr.Rangarajan
Dr.Sakunthala Engineering College,
Chennai, Tamil Nadu, India
mahendrababu13185@gmail.com
S. Nagarjuna Reddy
Department of Electronics and
Communication Engineering,
VelTech HighTech Dr.Rangarajan
Dr.Sakunthala Engineering College,
Chennai, Tamil Nadu, India
sunkireddynagarjuna123@gmail.com
Akumalla.Tharunkumar
Department of Electronics and
Communication Engineering,
VelTech HighTech Dr.Rangarajan
Dr.Sakunthala Engineering College,
Chennai, Tamil Nadu, India
tharunakkumalla2001@gmail.com
Abstract— Synchronous Dynamic Random Access Memory
(SDRAM) can transmit data much quicker than asynchronous
RAM. It is very important for data flow; a memory controller
with high speed is required. High-performance digital circuits
may be designed using an optimization approach called
parallel pipeline register architecture. This work proposes a
novel pipeline register design for high-speed communication.
The structure consists of many stages, each responsible for
executing a unique function in concert with the others. The
data is saved in the pipeline register while it is being processed
in the different phases of the pipeline. The user module and the
memory controllers communicate with each other by a rapid
memory link connection and data connection. Results show
that the FPGA design of the proposed design is possible, and
the Xilinx 13.1 ISE simulator's performance show that the
proposed design improves the performance of digital circuits
with less latency and high throughput.
Keywords—High-speed communication, Memory controller,
Pipeline register, Random access memory.
I. INTRODUCTION
The design of efficient shared memory is becoming an
increasingly important consideration for network processing
systems as greater emphasis is placed on developing multicore processing architectures [1]. The SDRAM memory is
placed under the control of the memory controller to
communicate with the CPU. Because the standard SDRAM
memory controller sequentially handles instructions, the next
instruction may not be received from the buffer register until
the current one has completed processing. Nevertheless,
because of recent developments in multi-core processing,
network processing performance may need to be improved
by a straightforward method that does not maximize
efficiency and is implemented in the IP core of generic
memory controllers [2]. The traditional memory controller
optimizes bank interleaving to boost data throughput and
decrease access latency [3].
A multi-core network processing system that forms the
basis of a pipeline memory controller is described [4]. The
controller was developed according to network processing
requirements, which require frequent access to the shared
memory from both the main processing and certain associate
processing. The communication between the processor and
the shared memory may be facilitated effectively by using
this pipeline controller [5]. Because the instructions are
979-8-3503-0541-8/23/$31.00 ©2023 IEEE
processed in pipelines, and multiple instructions can appear
simultaneously, the controller may use the address
information of two consecutive instructions to determine
which memory access policy is preferred before
implementing the instructions [6]. This occurs because
several instructions might arrive at once (CPA) and are
processed in pipelines [7]. This dynamic memory access
method permits using a single memory controller for bank
interleaving and page hit optimization.
Almost every modern computer uses some kind of
memory device, and this need has only increased in recent
years. The clock frequency of the controllers should be
somewhere in the megahertz region to achieve higher
throughputs and faster speeds. The increasing controller
clock speed is accompanied by a rise in the complexity of the
design challenges [8]. Therefore, the next generation of
memory devices needs fast controllers, such as double and
quad data rate memory controllers. In this project, we show
how to build a dual-data-rate SDRAM controller on an
FPGA. The SDRAM controller, which sits between the
SDRAM and the bus master, simplifies communication,
making it much simpler to manipulate the SDRAM memory.
This reduces the amount of work required to manage the
SDRAM storage.
SDRAMs may be subdivided into variants with varying
data-transfer rates [9]. The throughput of SDR SDRAM,
which only sends data on the rising edge of the clock, is
doubled by DDR SDRAM, which transports data on both the
rising and falling edges of the clock. This is in contrast to the
transfer of data that occurs in a single data rate SDRAM.
DDR SDRAM Controllers are superior in both speed and
effectiveness to their contemporaries. They make it possible
to transport data at a quicker pace without requiring a
significant increase in either the clock frequency or the bus
width [ 10].
With this design, we can boost the memory's data
throughput and decrease the time it takes to access it. When
using DRAM (Dynamic Random Access Memory), memory
accesses are often directed via a solitary off-chip memory
interface. This offers crucial storage capacity at low prices
when utilizing DRAM. The performance bottleneck is the
access to the system's memory, not the chip. The design's
difficulty is accommodating the enormous bandwidth needs
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with off-chip memory while simultaneously managing the
accesses of several channels.
timing and stability play a significant role in the system's
operation.
The DDR SDRAM memory standard is an improvement
over its predecessor, the SDRAM memory standard. This is
because it enables a greater bus speed and consumes less
power than its predecessor since its internal clock operates at
a speed that is one-fourth that of the data bus. Even though
new-generation memories rapidly evolve, DDR SDRAM is
still widely used in FPGA-based embedded systems. The
DDR SDRAM controller, which allows for easy access to
external memories, is essential in designing such systems.
The data in DDR SDRAM is accessed at a fast clock rate and
uses a large bandwidth. A DDR SDRAM controller is often
built to finish the data access process for memory. This is
necessary since SDRAM control commands might be
sophisticated. Reputable FPGA vendors like Xilinx have
presented a significant proportion of today's DDR SDRAM
controllers. Users still run into issues while dealing with
external DDR SDRAM memory due to the interface signals'
complexity and the controllers' latency. This is particularly
the case with high-speed embedded systems, where accurate
The optimization of power consumption has become an
increasingly important concern in the complex electronic
systems of today, including mobile, embedded, and wireless
devices. Because of the ongoing efforts to enhance processor
speed and memory density, there has been a rise in the
quantity of power that has been used. The increasing need for
increased performance is directly related to the expanding
number of cores squeezed into a single chip for enhanced
data access, storage capacity, and calculation. This is because
more cores allow more efficient data access, storage
capacity, and computation. Power management in this
subsystem has become an important and pressing matter due
to the fact that this component is accountable for the
dissipation of such a big proportion of the system's total
power consumption. These computational elements were
identified as the requester of the service to the program
memory. DDR-SDRAM management is examined as a
potential issue. The memory controller under examination is
shown in schematic form in Figure 1.
Cache Line
Column
DDR SDRAM
Memory Controller
Channel
DDR SDRAM
Memory
Memory
Controller
Channel
row
bank
DDR SDRAM
Tank
Controller
Fig. 1. Schematic form of the proposed memory controller
The architecture of synchronous DRAM is laid out using
columns, rows, banks, and ranks as its basic building blocks.
The dynamic random access memory (DRAM) cells
constituting the bank are laid out in a two-dimensional array
[11]. A Rank has many banks, and each of these banks'
power conditions may be altered individually. The bank and
row decoder selection are the first steps in addressing a cell.
The methodology includes the use of test benches, which are
used to simulate different operating conditions and to
generate test vectors to validate the controller's functionality,
and the importance of timing constraints and signal integrity
considerations in the design of the memory controller, and
they present a design flow for implementing the controller in
an FPGA.
The column decoder will first select the required column,
then select the required row, and finally fetch the row buffer.
A row is selected inside a bank during the ACTIVE state and
then moved to the row buffer to wait for the next
PRECHARGE. The row buffer will conduct burst
READ/WRITE operations once the status is set to
READ/WRITE. After a burst READ/WRITE operation,
DDR SDRAM transitions into the ACTIVE state, awaiting
the subsequent instruction. Before fetching the next row, the
PRECHARGE instruction puts the current row from the row
buffer into RAM to be ready for the following row.
In [13], the author describes using SystemVerilog for
more thorough coverage throughout the design and
verification of a DDR SDRAM controller. The verification
methodology includes functional verification using
SystemVerilog and coverage-driven random testing. The
DDR SDRAM controller is designed using a finite state
machine approach, and the verification process involves
creating functional test cases and generating random stimulus
to achieve higher coverage, and the importance of code
coverage and functional coverage in the verification process
shows how the coverage results can be used to evaluate the
effectiveness of the verification methodology.
II.
LITERATURE SURVEY
The validation of a DDR SDRAM memory controller for
Field Programmable Gate Array (FPGA) synthesis is
discussed in [12]. The present validation methodology
involves using a hardware simulator and software tools to
test and verify the functionality of the memory controller.
Designs for DDR SDRAM memory controllers in
embedded System-on-Chip (SoC) implementations are
explored in [14]. The authors describe a design technique
that uses a pipelined architecture for the memory controller
and a Finite State Machine (FSM) approach. Memory
controller implementation is done in Verilog HDL, and
2023 Second International Conference on Smart Technologies for Smart Nation (SmartTechCon 2023)
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design issues for timing, signal integrity, and power
consumption are discussed. The summary also includes
simulation data proving the memory controller works as
intended and can reach the required specifications.
An embedded System-on-Chip (SoC) uses a DDR
SDRAM memory controller constructed in the same manner
described in [15]. The design process includes a pipelined
architecture for the memory controller and a Finite State
Machine (FSM) approach. We address the significance of
timing restrictions, signal integrity, and power consumption
as they relate to the design process and the use of Verilog
HDL in implementing the memory controller.
Power-efficient high-speed DDR SDRAM memory
controller architecture and implementation are provided in
[16]. They suggest a design approach based on a pipelined
architecture and a power management technique dubbed
Adaptive Body Biasing (ABB) to lower the memory
controller's power consumption. Memory controller
implementation is done in Verilog HDL, and the authors
highlight the significance of timing analysis and signal
integrity checks.
digital circuitry. Data in a pipeline register is broken down
into progressively smaller chunks before being processed by
several circuits working in parallel. Data is saved in the
pipeline register before moving on to the next processing
step. Tasks are first decomposed into smaller, more
manageable chunks to achieve peak pipeline performance
before being executed in parallel. This increases throughput
while decreasing latency, improving the system as a whole.
The use of registers inside a pipeline may also improve its
performance. A register is a temporary storage space used to
hold information between processing steps. Registers are
often referred to as register slots. The output of one stage
may be saved in a register and utilized as the input for the
following step if a register is used between the stages. This
eliminates the need for any extra data transfers to take place.
Because of this, the time necessary to do a job is decreased
while the system's throughput is increased. Performance may
be enhanced by optimizing the pipeline design itself, which
can then lead to better results. This may be accomplished by
finding a happy medium between the number of steps and
the amount of processing time allotted to each stage and
maximizing the efficiency of the pipeline's timing and
synchronization.
III. PROPOSED METHOD
An optimized parallel pipeline register is a technique
used in computer architecture to increase the efficiency of
Control Unit
Data in
R1
C1
R2
C2
Rm
Cm
Dataout
Stage 1
Stage 2
Stage m
Fig. 2. Structure Of a Pipeline Processor
The framework comprises many levels, each accountable
for carrying out a certain activity in combination with the
other levels. As indicated in Figure 2, the pipeline register is
where the data is stored and processed via various steps.
There are nine stages in total, each with a register
corresponding to it in this block diagram. The data is
processed first in Stage 1, then transferred to Stage 2, where
it is processed in tandem with the output of Stage 1. The
results of Stage 2 are sent on to Stage 3, and the process
continues from there. Registers are put in between each step
to hold interim findings and reduce the required data
transmission. Stage 9 is responsible for producing the
ultimate output at the very end of the pipeline. The pipeline
circuits are synchronized so that they will always work in
perfect unison with one another. The pipeline design may be
optimized via feedback loops by monitoring the system's
performance and altering the pipeline stages following the
findings. Memory controllers have the capability of using an
optimized parallel pipeline register design, which has the
effect of improving the speed of memory access operations.
Memory controllers are the components of a computer that
are in charge of controlling the flow of data between the
central processing unit (CPU) and memory. A common
602
memory controller uses a sequential approach to transfer data
between the central processing unit and the memory, which
might result in substantial latency. The memory controller
may partition access into many phases to facilitate parallel
processing. This is made possible by a set of registers
organized in a parallel pipeline that has been fine-tuned. As a
result, system-wide latency is lowered while throughput is
increased. These are the most crucial features of a welldesigned parallel pipeline register:
To guarantee that each phase in the pipeline completes its
duty at the same pace, the processing times of each stage
should be distributed appropriately. As a result, the
efficiency of the pipeline is increased, and the total
processing time is decreased. A pipeline's intermediate
results may be saved in a register and fed into the following
iteration. As a result, less information has to be sent, which
improves the system's throughput. Pipelining is a method
that helps break down a process into its parts so that they
may be worked on simultaneously. This contributes to a
reduction in the system's overall latency and helps to boost
the throughput of the system.
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To do one job concurrently, many circuits are operated
in parallel. This decreases the amount of time required to do
a job while simultaneously increasing the system's
throughput. The pipeline circuits are synchronized so that
they will always work in perfect unison with one another.
This helps prevent timing problems and guarantees that the
data is handled properly. The pipeline design may be
optimized with the help of feedback loops by monitoring the
system's performance and altering the pipeline stages
following the findings.
IV. RESULTS AND DISCUSSIONS
RTL description in VHDL is used to execute the
architecture of the pipeline DDR SDRAM memory
controller, and this technique is then implemented on Xilinx
ise 13.1 through the use of the Spartan 7 FPGA device
environment that is platform-based. Also, have the ability to
develop a few computations on optimized parallel pipeline
register DDR SDRAM controllers and traditional SDRAM
memory controllers using this platform. The difference in
execution time between the optimized parallel pipeline
register DDR SDRAM controllers and traditional SDRAM
memory controllers is shown in Figure 3.
parallel optimized pipeline
Cycles(T)
conventional
1400
1200
1000
800
600
400
200
0
10
20
30
40
50
Fig. 3 Latency analysis
It can be seen from Figure 3 that the execution time of
optimized parallel pipeline register DDR SDRAM
controllers is better than traditional SDRAM memory
controllers. Figure 4 shows the throughput analysis of the
proposed design with the conventional approach.
conventional
parallel optimized pipeline
4000
Mbit/s
3000
2000
1000
0
200us 400us 600us 800us 100us
Fig. 4. Throughput analysis
It is collected for some predetermined time intervals. It is
possible to significantly boost the throughput of the SDRAM
memory by using the pipeline memory controller, which is
suitable for the high-performance requirements of system
processing.
V. CONCLUSION
This article presents a new method of parallel pipeline
registration for high-speed communication. It can reduce the
latency and give an advanced address connection for two
instructions next to one another. After then, the controller
can use the address connection to implement a dynamic
approach to the access policy for the memory. In contrast to
the conventional memory controller, the parallel pipeline
register memory controller can do both bank interleaving and
page hit optimization inside the same memory system. This
allows for the utilization of the memory data bus to be
maximized while simultaneously reducing the amount of
time it takes to access memory. The performance study based
on execution time and throughput demonstrates that the
parallel pipeline register design can significantly enhance the
throughput and reduce the memory access latency.
REFERENCES
[1]
Jin, Wenjing, Wonsuk Jang, Haneul Park, Jongsung Lee, Soosung
Kim, and Jae W. Lee. "DRAM Translation Layer: SoftwareTransparent DRAM Power Savings for Disaggregated Memory." In
Proceedings of the 50th Annual International Symposium on
Computer Architecture, pp. 1-13. 2023.
[2] V .Chavan, and M. B. Veena. “Power Efficient High-Speed DDR
SDRAM Controller,” Journal for the Study of Research, vol. 12, no.
8, pp 7-14, 2020.
[3] Cho, Jungseok, Jonghee M. Youn, and Doosan Cho. "An Automatic
Array Distribution Technique for Multi-Bank Memory of High
Performance IoT Systems." World , vol. 3, no. 1,pp. 15-20, 2019.
[4] S. S Parihar, and S. Nemade, “VHDL Design and Implementation of
High-Speed Double Data Rate 3 Memory Controller with AXI 2.0
compliant,” International Journal of Innovative Research in
Technology and Management, vol. 5, no. 1, pp. 36–42, 2021.
[5] M. Xie, D. Tong, Y. Feng, K. Huang, and X. Cheng, “Page policy
control with memory partitioning for DRAM performance and power
efficiency,” in International Symposium on Low Power Electronics
and Design, pp. 298–303, 2013.
[6] M. Jung, and N. Wehn, “A Lean, Low Power, Low Latency DRAM
Mem- ory Controller for Trans precision Computing,” in Embedded
Computer Systems: Architectures, Modeling, and Simulation: 19th
International Conference, vol. 11733, pp. 429–429, 2019.
[7] Koc, Hakduran, Mounika Garlapati, and Pranitha P. Madupu. "Data
Compression and Re-computation Based Performance Improvement
in Multi-Core Architectures." In 2020 10th Annual Computing and
Communication Workshop and Conference (CCWC), pp. 0390-0395.
IEEE, 2020.
[8] C. Sudarshan, J. Lappas, C. Weis, D.M. Mathew, M. Jung, and N.
Wehn, “A lean, low power, low latency DRAM memory controller
for trans precision computing,” in International Conference on
Embedded Computer Systems, pp. 429–441, 2019.
[9] C.Y. Lai, G.Y. Pan, H.K. Kuo, and J.Y. Jou, “A read-write aware
DRAM scheduling for power reduction in multi-core systems,” in In
2014 19th Asia and South Pacific Design Automation Conference, pp.
604–60, 2014.
[10] I. Hur, and C. Lin, “A comprehensive approach to DRAM power
management,” International Symposium on High Performance
Computer Architecture. IEEE, pp. 305–316. 2008
[11] V.Jai Ganesh, S. Murugan ” PC based heart rate monitor implemented
in xilinx fpga and analysing the heart rate,” Proceedings of the Third
IASTED International Conference on Circuits, Signals, and Systems,
pp. 319–323, 2005.
[12] A.C. Bonatto, A.B. Soares, and A. Altamiro, A. Susin. “DDR
SDRAM Memory Controller Validation for FPGA Synthesis,” In
LATW2008: Proceedings of the 9th IEEE Latin-American Test
Workshop, pp. 177-182, 2008.
[13] M. P, Pavan Kumar, and Subodh Kumar Panda. “Design and
Verification of DDR SDRAM Memory Controller Using
SystemVerilog For Higher Coverage,” In 2019 International
Conference on Intelligent Computing and Control Systems, pp. 689694, 2019.
2023 Second International Conference on Smart Technologies for Smart Nation (SmartTechCon 2023)
603
Authorized licensed use limited to: Sogang University Loyola Library. Downloaded on February 08,2025 at 08:37:59 UTC from IEEE Xplore. Restrictions apply.
[14] B. Naresh, S. Rambabu, and G. Lakshmi Narayana. “Implementation
of DDR SDRAM Memory Controller for embedded SOC,”
International Journal of Advanced Trends in Computer Science and
Engineering, vol.5 , no.1, pp. 101 -105, 2016.
[15] M. Sanwatsarkar, and J. Nagar. “Implementation of DDR SDRAM
Controller using Verilog HDL,” IOSR Journal of Electronics and
Communication Engineering, vol. 10, no. 2, pp. 69-74, 2015.
604
[16] V. Chavan, and M. B. Veena. “Power Efficient High-Speed DDR
SDRAM Controller.” Journal for the Study of Research, vol. 12, no.
8, pp 7-14, 2020.
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