Clarifying the Role of Ferroelectric in Expanding
the Memory Window of Ferroelectric FETs with
Gate-Side Injection: Isolating Contributions from
Polarization and Charge Trapping
Yixin Qin1*, Saikat Chakraborty2*, Zijian Zhao1*, Kijoon Kim3, Suhwan Lim3, Jongho Woo3, Kwangsoo Kim3,
Wanki Kim3, Daewon Ha3, Xiao Gong4, Asif Khan5, Vijaykrishnan Narayanan6, Jaydeep P. Kulkarni2, and Kai Ni1
1
University of Notre Dame; 2University of Texas, Austin; 3Samsung Electronics; 4National University of
Singapore; 5Georgia Institute of Technology; 6The Pennsylvania State University;
*Equal contribution; (email: yqin4@nd.edu)
Abstract—In this work, we performed a comprehensive
experimental and modeling study, clarifying the role of
ferroelectric materials in boosting the memory window of
FeFETs with gate-side charge injection for the first time.
We separated the ferroelectric contributions to the
memory window into remnant polarization and top charge
trap layer (CTL) trapping. Our findings demonstrate that:
(i) Ferroelectric materials enhance the memory window in
two ways: by switched more polarization when CTL traps
more, which provides screening charges, and through their
super-linear Q-V relationship that boosts the CTL electric
field and enhances charge trapping; (ii) The contributions
from polarization and CTL trapping mutually reinforce
each other, resulting in a larger memory window compared
to a ferroelectric + dielectric stack or a high-ț&7/VWDFN
where only one factor is active; (iii) Combined
experimental data and TCAD simulations confirm that
approximately one-third of the memory window is due to
increased polarization, while two-thirds result from CTL
trapping; (iv) The memory window can be further
enhanced with a blocking oxide on top of the CTL,
achieving up to a 16V window with an ONO blocking oxide.
I. INTRODUCTION
The insatiable appetite for high density storage, especially
in the era of data generation at an exponential rate and the large
language models exploding, calls for higher capacity and lower
power storage. Vertical NAND flash has been fueling this
paradigm shift due to its cost efficiency and clear scalable path.
However, such a scaling is met with significant challenges
related with the poor write efficiency of Flash. Because of the
inefficient tunneling process, flash memory write pulse voltage
and pulse width are excessive, posing significant challenges in
further scaling along the XY and Z dimensions. To address this
challenge, recently, FeFET, has been shown to be highly
promising by incorporating gate side injection (Fig.1(a)). It is
known that in the conventional FeFET, the channel side charge
injection causes many reliability concerns, as the charge
trapping counteracts the polarization induced VTH shift.
However, if the gate side injection can be induced, rather than
the channel side injection, the charge trapping can help boost
the memory window [1]. There have been many promising
reports that show a large memory window suitable for vertical
NAND application (Fig.1(b)). Fig.1(c) summarizes the reported
FeFET memory window including the conventional ones (i.e.,
follow a linear dependence on the ferroelectric thickness) and
the ones exploit the gate side injection. Though this memory
window boost is intuitive, the exact role that ferroelectric plays
has not been clarified, which is critical for future memory
optimization and reliability improvement. This work aims at
clarifying the ferroelectric role and provides the insights.
There are two components in the memory window, one
from the remnant polarization and one from the gate side charge
trapping. Though polarization is present in all kinds of FeFET,
the FeFET with top charge trap layer (CTL) boosts the
switchable polarization, compared with the FeFET with only
top dielectric without any trapping (Fig.2(a)). This is because
the trapped charge in the gate side acts as screening charge,
which can help polarization switching. To identify the role of
ferroelectric in inducing charge trapping, it is important to
compare with the stack with high-N (HK) dielectric and the top
CTL, in which case, no polarization is present. Looking at the
Q-V relationship, the super-linear Q-V of FE can help reduce
the required FE voltage drop compared with the HK for the
same charge or induce more charge switching for the same
voltage drop. From this analysis, it is clear that polarization and
gate side charge trapping reinforce each other, thus jointly
enhancing the window. In this work, we are clarifying such an
interaction and separating each component in memory window.
II. FARBICATION PROCESS
For a comprehensive study of the impact of gate stack
layers on FeFET performance, experimental investigations
were conducted in this work. Fig.3(a) demonstrates the control
sample with10-nm-thick HZO and other three stacks: 10nm
HZO with 5nm SiNx on top (FE+CT), 10nm HfO2 with 5nm
SiNx on top (HK+CT), and 10nm HZO with 5nm Al2O3 on top
(FE+DE). The integration fabrication process flow is depicted
in Fig.3(b). The fabrication is carried out on a P-type silicon.
After phosphorus ion implantation and activation, the isolation
oxide in the gate area is removed. The gate dielectric HZO,
HfO2, SiNx, Al2O3 are deposited through atomic layer
deposition (ALD) at 250qC. As for the FE+CT gate stack,
additional 1nm and 2nm Al2O3 and 2nm SiO2 are deposited to
study the effect of blocking oxide. Moreover, the common
flash structure SiO2/SiNx/SiO2 (ONO) is fabricated as well.
Tungsten (W) layer is sputtered serve as source, drain, and gate
metal, followed by RTP annealing in forming gas (N2+H2,
350qC) and N2 (500qC). Fig.3(c) shows the top view scanning
electron microscopy (SEM). Fig.3(d) shows the transmission
electron microscopy (TEM) of cross-sections of the four gate
stacks of FeFET, and the energy-dispersive x-ray spectroscopy
(EDS) line scans are shown in Fig.3(e), respectively. These
TEM and elemental profiles confirm the intended thickness
and material in the gate stack designs. The pulse ID-VG of top
charge trapping layer and bottom ferroelectric layer were
shown in Fig.3(f) and (g). The experimental results
demonstrated FeFET with CTL is larger than dielectric layer
(i.e., weaker charge trapping) and that with ferroelectric layer
is larger than that with high-N dielectric.
III. CLARIFYING THE ROLE OF FERROELECTRICS
For detailed study, TCAD models are first built and
calibrated based on the 2nm blocking oxide structure
(Fig.4(a)). Ferroelectric Preisach model and SiNx charge trap
layer parameters are also given. The TCAD simulation can
well reproduce experimental results (Fig.4(b)). With such
models, the two contributors are studied: 1) Remnant
polarization (PFE), and 2) the super-linear Q-V. To study the
first factor, TCAD simulations comparing the scenarios of
enabling or disabling the top CTL trapping are conducted.
Fig.5 (a) shows the average polarization at VG=0V after write.
It shows that the switched polarization is enhanced 3.3x with
the CTL trapping compared with the one without trapping. As
a result, MW can be enhanced due to οܲிா /‫ܥ‬ிா component.
Fig.5(b) shows two cycles of program/erase waveforms
(±15V, 10Ps) and the corresponding trapped electron/hole
density. In Fig. 5(c), experimental ID-VG characteristics of
10nm HZO control FeFET (±4V, 10Ps) and FE+CT with 2nm
Al2O3 (±15V, 10Ps) are compared, where MWs are 1.6V and
approximately 12V, respectively. TCAD simulated ID-VG (Fig.
5(d)) are consistent with the experiments. Using the simulated
results, the pure PFE contribution is estimated to be 3.6V and
the remaining 8.4V memory window comes from the CTL
charge trapping (Fig.5(d)). This clarifies the pure remnant
polarization PFE provides around 1/3 contribution in the
enlarged MW, whereas 2/3 MW is due to the charge
trapping effect.
To show that the super-linear Q-V of ferroelectric can boost
MW, a hypothetical nonlinear dielectric (Fig.6(a)) was
implemented in TCAD. Fig.6(b) presents the Q-V
implemented in TCAD with different nonlinearity. When the
same voltage is applied, super-linear dielectric can gain a
larger amount of charge ('QNL) than linear dielectric charge
('QL). This obviously induces higher injected charge in CTL
to increase MW. And the experimental pulse ID-VG between
FE+CT and HK+CT was shown in Fig. 6(c), which verifies the
FE could achieve higher MW compared to HK. But the
experiment also includes the polarization contribution (~4V in
Fig.5(c) and (d)), excluding which the pure charge trapping
contribution is about 4.7V, 1.7x of the HK+CT device.
Fig.6(d) shows trapped electron density in the CTL during 15V program and electron loss after program. It shows that the
larger the nonlinearity, the higher the trapped electrons. This
charge trapping enhancement is originated from the enhanced
electric field in the CTL (Fig.6(e)) as the FE field reduces with
stronger nonlinearity.
After clarifying the role of ferroelectric, next with the help
of TCAD simulations, the two components are further
investigated by comparing the FE+CT and HK+CT stacks and
cross-validated with prior analysis. The electric field in the
CTL during both program (Fig.7(a)) and erase (Fig.7(b))
shows an enhanced CTL field and reduced FE field compared
with HK case. The corresponding band diagrams for program
(Fig.7(c)) and erase (Fig.7(d)) also shows the reduced FE field
compared with HK. As a result, the trapped electrons during
program (Fig.7(e)) and trapped holes during erase (Fig.7(f)).
Fig.7(g) summarizes the trapped electrons/holes/space charges
during programming/erase. From these results, it can be
estimated that the HK+CT will exhibit around 4.6V window
while the trapped contributed window is 8V for the FE+CT
case, again 1.7x of the HK case, consistent with experiment.
IV. CHARACTERISTICS OF GATE SIDE INJECTION FEFETS
WITHOUT AND WITH BLOCKING OXIDE
Further analysis of the fabricated devices is first conducted
on the devices without a block oxide. Fig.8(a) and (b) shows
the ID-VG curves with different programming voltages when
initialized at the low-VTH (LVT) and high-VTH (HVT) state,
respectively. The corresponding VTH as a function of
programming voltages are summarized in Fig.8(c) and (d),
respectively for three different stacks, i.e., FE+CT, FE+DE,
and HK+CT. It clearly shows that the slope of the incremental
step pulse programming (ISPP) (Fig.8(e) and (f)) of the
HK+CT is below 1, typically present for flash-based device,
indicating that the VTH increase is theoretically below the step
size of programming pulse [2]. However, with the mutual
reinforcement of the polarization and charge trapping, the ISPP
slope can be well above 1, suggesting superior tuning
efficiency of the FE+CT device. Fig.9(a) and (b) shows the
band diagrams during zero bias convention for FE+CT and
HK+CT. Due to the presence of polarization, the electric field
can help retain the trapped charges (Fig.9(c)), thus slowing the
charge loss during retention compared with HK+CT. Fig.9(d)
compares the retention between the two stacks, consistent with
the theoretical picture shown in Fig.9(a) and (b).
Next the impact of blocking oxides on the FeFET memory
window is presented. Fig.10(a)-(c) shows the TEM, elemental
mapping, and atomic composition along the gate stack with
2nm Al2O3 blocking oxide, respectively. The corresponding
DC and pulsed ID-VG curves of different blocking oxide
thicknesses shows that the MW increases with the blocking
oxide thickness that 2nm Al2O3 has about 12V window with
±15V, 10Ps programming pulses. In all the devices, an ISPP
slope larger than 1 is observed. When comparing different
blocking oxides (Al2O3 vs. SiO2 vs. SiO2/SiNx/SiO2), Al2O3
shows a similar window as SiO2 while the ONO has a larger
window, but also need a larger write voltage (Fig.10(i) and (j)).
V. CONCLUSION
This work firstly clarifies ferroelectric material and charge
trapping mechanisms contributing to boosting MW in gateside-injection FeFET through simulation and experimental
results. This helps the better understanding and guide in FeFET
design in 3D NAND with higher storage. With ±15V, 10Ps
pulse, FE+CT+2nmAl2O3 gate stack can reach to 12V memory
window. Optimizing the gate stack (such as ONO structure)
could potentially achieve better performance in future memory
applications.
Acknowledgement: This work was partially supported by SUPREME and
PRSIM, two of the SRC/DARPA JUMP2.0 centers, NSF 2344819, and
Singapore MOE Tier 1 A-8001168-00-00 and A-8002027-00-00. References:
[1] S. R. Rajwade et.al, TED 2012;[2] D. Verreck et.al, TED 2024;
Understanding the Role of Ferroelectric in Boosting the Memory Window of FeFET with Gate Side Injection
(a) Conventional FeFET
Top
functional
layer,CTop
Gate
PFE+
FE
Qtc-
n+
Gate
Qtg+
FE
PFE+
n+
n+
n+
∆Qtg=Qtg+-Qtg-
n+
Qtc+
n+
∆𝑃
− ∆𝑄
𝐶
∆PFE=PFE+-PFE∆Qtc=Qtc+-Qtc-
𝑀𝑊 =
+
(c)
n+
𝑀𝑊 =
∆𝑃
∆𝑄
− ∆𝑄
𝐶
− ∆𝑄
𝐶
With additional gate side injection(GSI),
MW can be greater than ideal pure FeFET:
𝑀𝑊
> 𝑀𝑊
=2 𝐸
FE+CT
QFE
QFE
Gate
CT
Q0
QFE
QFE
QMOS
@VG=0V
+
Pr
+
Q FE
FE
Gate
CT
What is the role
of ferroelectric in
MW boosting?
Flash
8
Q
Trapping
enhances
PFE
FE
n+
QFE
+
tg
+
Q FE
n+
-
Q FE
𝑡
Q
QHK
Gate
CT
Q0
QHK
QHKVHK
VHK
V0
VHK
n+
tg
QFE > QHK due to FE
nonlinearity. With the same
voltage drop, FE can induce
more CT charge trapping.
VHK > VFE due to FE
nonlinearity. To induce the
same CT trapping, FE can
reduce write voltage.
Comparing HK with
FE allow to
understand the
effect of Q-V shape
Trapping in the CT layer also facilitates
more PFE switching, thus boosting window
beyond the FE only stack and FE+DE stack
5 10 15 20 25 30
Ferroelectric thickness (nm)
HK+CT
n+
-
V0 VFE
VFE VFE
n+
HK
VFE
4
0
0
n+
FE+DE
Pr- FE only
FE+CT (strong trapping)
12
FE
VFE
-
Q FE
n+
Qtg-
FE
PFE-
Qtc+
n+
FE+DE (weak trapping)
n+
Memory window (V)
FE
PFE-
Contribution 2: super-linear Q-V of FE improves charge trapping efficiency
Gate
DE
Gate
Gate
(b)
Contribution 1: remnant PFE enhanced with trapping
Promising for
vertical NAND
storage
Qtc-
Contributions of FE to MW Boosting
(a)
(b) Vertical NAND with FeFET
Gate side injection FeFET
Fig.1. (a) Compared to conventional FeFET, MW can be Fig.2. (a) Remnant polarization in ferroelectric can facilitate charge trapping, and vice
enhanced by gate-side-injection (GSI) FeFET. (b) 3D Vertical versa to facilitate FE switching. (b) The super-linear Q-V curve in FE requires less
NAND structure with GSI FeFET. (c) It is unclear what the applied voltage than high- stack to trap the same mount of charge, or more trapped
role FE plays in boosting the GSI FeFET and studied here.
charge under the same voltage, which improves the trapping efficiency.
Different Stacks Fabricated to Identify the Role of Ferroelectrics in Boosting the Window
FE+DE
SiNx (5nm)
SiNx (5nm)
Al2O3 (5nm)
HZO (10nm)
HfO2 (10nm)
HZO (10nm)
Control
n+
Gate
Gate
DE
FE: 10nm
SiO2: 1nm
FE
SiO2: 1nm
n+
n+
10nm HZO ALD (250°C)
Control
10nm HZO ALD + SiNX ALD
FE+CT
10nm HfO2 ALD + SiNX ALD
HK+CT
10nm HZO ALD + Al2O3 ALD
n+
5nm
FE+DE (e)
0nm, 1nm, 2nm Al2O3 blocking oxide
2nm SiO2 blocking oxide
Gate
1
Drain
W
W
SiNx
W
SiNx
W
AlOx
HZO
HZO
HfO2
HZO
SiO2
Si
SiO2
Si
SiO2
Si
SiO2
Si
100
For FE+CT
(c)
(f) 10−3 Control: ±4V, 10s;
(d)
S/D ion implantation (P31) and activation
Gate etch (BOE) and clean
2nm SiO2/ 5nm SiNx / 2nm SiO2 ONO
Open via (RIE+BOE)
Source
Tungsten sputtering for S/D/G contacts
50µm
RTP annealing (FGA 350°C+N2 500°C)
Control
O
Si
W
Hf
Zr
N
FE+CT
80
60
FE+DE
O
Si
W
Hf
N
O
Si
W
Hf
Zr
40
20
0
0
10 20 30
Position (nm)
10−5
Weak DE
trapping
10−6
MW CT>MW DE
10−7
10−8
−4
−2
0
2
4
6
Gate Voltage (V)
(g) 10−3
HK+CT
Experimental
result shows:
MW DE>MWcontrol
FE+CT: ±11V, 10s;
10−4 FE+DE: ±10V,10s;
Drain Current (A)
HK+CT
Control: ±4V, 10s;
FE+CT: ±11V, 10s;
10−4 HK+CT: ±11V,10s;
O
Si
W
Hf
Zr
Al
Drain Current (A)
(b)
FE+CT
Atomic Fraction (%)
(a)
Strong CT
trapping
10−5
Experimental
result shows:
10−6
MW FE>MWHK
10−7
0
10
20
30
Position (nm)
10
20
30 0
Position (nm)
0
10−8
10
20
30
Position (nm)
−4
−2
0
2
4
6
Gate Voltage (V)
Fig.3. (a) FeFET gate stacks with HZO control sample, and three different FeFET stacks. (b) Integration process flow of proposed FeFETs. (c) SEM
top view of fabricated FeFET. (d) Cross-sectional TEM images of proposed FeFETs. (e) Atomic composition of the gate stack cross-sectional direction.
(f) Pulsed ID-VG comparison between FeFET with top CTL and dielectric layer, and CT stack shows improved MW. (g) Pulsed ID-VG comparison
between ferroelectric and high- with CTL, which shows that FE improves MW. The AlOx DE shows weak trapping comparing the control.
Identifying and Separating the Window Enhancement to Increased Remnant Polarization and Boosted CTL Trapping
EC-2.5eV
(1.5 - 2)x1020 cm-3
Acceptor trap energy EC-1.0eV
Acceptor trap density (1.5 - 2)x1020 cm-3
Tunneling me, mh
15
(b)
10-13cm2,
10-17cm-3
0.16m0, 0.38m0
Pr
EC
23.8μC/cm2
1.2MV/cm
τE, τP
402.5ns, 50ns
FE+CT+Al2O3(2nm)
MW (V)
9
6
3
0
6
Exp.
8
10
12
14
Write voltage (V)
16
Fig.4. (a) TCAD calibration
of FeFET structure and the
modeling parameters table.
(b) The TCAD models are
well calibrated with and
experimental results.
0
(d) 10
Trapping enabled
14.4C/cm2
0
4.4C/cm2
Trapping
disabled
−10
(b)
12 10µs pulse
TCAD
@VG=0V after write
−15
3x more PFE
switching
−10
−5
0
Position (nm)
5
1
−2
0
2
VG (V)
4
6
8
(a)
Trapping enabled
TCAD
Trapping disabled
Just boosted PFE induced window
Q
TCAD with a
hypothetical QNL
NL dielectric
QL
10
10−8
V1 V2 V
12V
−6
CTL
hole
trapping
−6 −4 −2
3.6V
1.2V
0
2
VG (V)
CTL
electron
trapping
4
6
8
electron
1020cm-3
• Pure PFE contribution to MW is
1
of overall window (i.e., 3.6V in
3
1020cm-3
hole
12V)
0
2
window comes from
3
CTL trapping.
HK
−10
• The rest
0
40
Time(s)
80
Fig.5. (a) Extracted polarization with and without charge
trapping activated after write. (b) Extracted electron and
hole charge density under program and erase versus time.
(c) Pulsed ID-VG of control sample and FE+CT+Al2O3
FeFET. (d) ID-VG simulation comparison with and without
charge trapping, and the separated contribution of PFE.
−20
−3
−2
−1
Voltage (V)
0
PFE contribution: 1.6V*3=4.8V
Control: ±4V, 10s; CTL contribution: 4.0V
FE+CT: ±11V, 10s; CTL in FE+CT = 4/2.7
HK+CT: ±11V,10s; =1.7x HK+CT
8.7V
10−6
2.0
(e)
25
Dielectric with super-linear Q-V induces
higher injected charge under the same voltage.
0
10
10−8
(d)
10−4
• CTL trapping boosts PFE by
providing screening charge.
0
−15
2
10−2
−4
−4
 The contribution to MW is
related to the nonlinear curvature.
(b) 10
15
Trapped Charge
(1020cm-3)
Trap cross-section
volume
VG (V)
Donor trap energy
Donor trap density
= 14.4𝜇𝐶/𝑐𝑚 with trapping
10
Average PFE (C/cm2)
(a)
10−8
−6
10−2
2.7V
−4
−2
0
2
VG (V)
4
6
NL decrease
0
−5
1.0
−10
HK
Voltage (V)
Value
1.6V
12V
10−6
(c)
−15
0.0
0
5
10
15
20
Time (s)
Electric Field (MV/cm)
∆𝑃
Trap & FE parameters
without trapping
 Super-linear Q-V dielectric
(such as ferroelectric) can induce
higher electric filed in CTL, and
excite more charge injection.
10−4 Exp.
Trapped electron (1020cm-3)
= 4.4𝜇𝐶/𝑐𝑚
Contribution 2: super-linear Q-V boosts CTL field and increases the charge injection
Control (±4V,10s;)
FE+CT+Al2O3 (2nm) (±15V,10s)
Charge (C/cm2)
∆𝑃
ID (A)
Al2O3 (2 nm)
SiNx (CTL – 5 nm)
HZO (10 nm)
SiO2 (1 nm)
ID (A/m)
Nonlocal
tunneling
10−2
(c)
Trapping in CTL helps screen the
PFE, thus increases PFE, hence MW
contributed by PFE itself, through
∆𝑃
𝐶
ID (A)
Contribution 1: remnant PFE boosted by CTL trapping
TCAD Calibration
(a)
@ Program(-15V) 10s
NL
decrease
20
15
HK
10
5
−16
CTL: -16nm ~ -11nm
−14
−12
Gate Stack Depth (nm)
Fig.6. (a) Comparison between linear and super-linear
dielectric Q-V. (b) Different curvature of non-linear
dielectric Q-V in TCAD. (c) Pulse ID-VG of FE+CT and
HK+CT gate stack. (d) Extracted trapped electron in
different curvature of non-linear Q-V dielectric and HK
stack. (e) Extracted electric field in CTL after program .
Detailed Analysis of Both Window Contributors Through Comparative Study of FE+CT and HK+CT Stacks
5
0
0
CTL
−16
(b)
20
CTL
−5
−20
−10
FE/HK
Si
−15
−10
−5
0
BO: blocking oxide Gate stack depth (nm)
(d) 5
Erase (+15V) @10s
0
Erase (+15V)
30
BO
FE/HK
−14
−12
Gate stack depth (nm)
1µs
(f)
−5
−10
10
0s
0
CTL
−16
Efp
−15
−20
−10
FE+CT
0
3
0s
10µs
1µs
CTL
0
−16
2
1
0
3
FE/HK
−14
−12
Gate stack depth (nm)
Erase (+15V)
−10
10µs
1µs
1
CTL
0
−16
FE/HK
−14
−12
Gate stack depth (nm)
HK+CT, space charge
2
electron
𝑄
𝐶
= 0.45 × 10 𝑐𝑚
= 0.69 × 10 𝑐𝑚
= 1𝜇𝐹/𝑐𝑚
𝑀𝑊
𝑀𝑊
= 4.6𝑉
= 𝑀𝑊 = 4.6𝑉
hole
0
Solid line: FE, Dash line: HK
Space charge
FE+CT, space charge
𝑄
1020cm-3
6.9x1019cm-3
0
-4.5x1019cm-3
0
= 10 𝑐𝑚
= 10 𝑐𝑚
= 1𝜇𝐹/𝑐𝑚
𝑄
𝐶
𝑀𝑊
𝑀𝑊
-1020cm-3
−2
−10
𝑄
1
2
0s
FE+CT
2 HK+CT
−15
−10
−5
0
Gate stack depth (nm)
0
−15
1
3
FE+CT stack has boosted
higher electric field distribution
in the CTL than HK+CT stack,
therefore improving the charge
injection efficiency.
HK+CT
2
−20
FE/HK
−14
−12
Gate stack depth (nm)
1
VG (V)
Efn
10
15
Program (-15V)
2
Trapped Charge
(1020cm-3)
0s
15
Solid line: FE+CT
Dash line: HK+CT
CTL trapped charges comparing FE & HK
(g)
Space charge
(1020cm-3)
10µs
10
Electric Field (MV/cm)
Electron density (1020cm3)
20
Energy (eV)
1µs
3
Hole density (1020/cm3)
20 Program (-15V) @10s
Program (-15V)
Solid line: FE+CT
Dash line: HK+CT
Energy (eV)
Electric Field (MV/cm)
(e)
(c)
30
Stronger CTL field leads to more
trapping for FE+CT
Also shown up in band diagram
CTL electric field boosted
(a)
40
Time(s)
= 8.0𝑉 = 1.7𝑥 𝑜𝑓 𝐻𝐾
= 𝑀𝑊 + 𝑀𝑊
= 3.6𝑉 𝐹𝑖𝑔5 𝑑 + 8.0𝑉
80
≈ 12𝑉 (𝑇𝐶𝐴𝐷 𝑝𝑟𝑒𝑑𝑖𝑐𝑡𝑖𝑜𝑛)
Fig.7. In program (-15V, 10s), FE+CT and HK+CT comparison on (a) electric field on CTL, (c) energy band diagram, (e) trapped electron density. In
erase (+15V, 10s), FE+CT and HK+CT comparison on (b) electric field on CTL, (d) energy band diagram, (f) trapped hole density. (g) Waveforms of
applied program/erase cycles, extracted electron and hole density, and total space charge in FE+CT and HK+CT in program/erase process.
Experimental Studies on High-/Ferroelectric Impact on Charge Trapping Layer (CTL)
−2
0
2
4
VG (V)
FE+CT
−8
Vapplied (V)
10−6
0
2
4
−6
−8
Vapplied (V)
(f) 10
Depolarization
field
0
−4
0
4
6
8
Vapplied (V)
(b) 8
6
4
2
Flash Limit: Slope1
−2
4
10
6
FE/CT program _No bias
HK/CT program _No bias
4
0
FE+CT stacks
Efield helps CTL
charge retention
−15
−10
−5
−8
0
−15
Gate Stack Depth (nm)
0
VG (V)
8
−4
HK+CT(Solid), HVT not stable
FE+CT(Dash), HVT more stable
−8
−20
−10
EFE
Electric Field (MV/cm)
ECTL
4
8
2
6
2
Flash Limit: Slope1
−2
−2
4
−2
−4
−10
4
−5
−4
−6
(d) 6
Intial: -11V, 10s
6
(c)
GND after -15V program
0
−4
6
(a) 8
to joint reinforcement between
PFE and CTL trapping.
Energy (eV)
ISPP slope
0
VTH (V)
ID (A)
2
−2
−4
10
8
ECTL
0
Depolarization
field
Pulse：
±11V, 10s
4
−15
−10
@RT
HK+CT
2
0
FE+CT
−2
−8
−20
8
10
Vapplied (V)
−5
6
EFE
−4
8
(d)
GND after +15V erase
4
−10
Gate Stack Depth (nm)
VTH (V)
10−6
10−4
FE+CT
HK+CT
FE+DE
4
10−5
(b)
(e) 10 ferroelectric can exceed 1 due
(c) 6
Energy (eV)
FE+CT
ISPP slope
ID (A)
10−4
Intial: +11V, 10s
VTH (V)
(a)
−5
−4 −7
10
0
10−5
10−3
10−1
101
103
Time (s)
Gate Stack Depth (nm)
Fig.8. Switching dynamics ID-VG of FE+CT stack under initialization of (a) Fig.9. Band diagram of FE+CT and HK+CT (a) after program bias
+11V, 10s, (b)-11V,10s. Extracted (c) low VTH, and (d) high VTH and the removed, (b) after erase bias removed. (c) Electric field after program
bias removed. (d) Retention comparison FE+CT and HK+CT.
corresponding (e), (f) ISPP slope of three different gate stacks.
The Impact of Blocking Oxides on the FeFET Characteristics
(b)
20
0
0
Si
5
Position (nm)
(d)
10−2
ID (A)
10
10 15 20 25 30 35
−4
ISPP slope
40
10
8
6
4
2
0
0
w/o Al2O3
1nm Al2O3
2nm Al2O3
(e)10
4
6
10−4
10−8
10−12
−6
2nm Al2O3
1nm Al2O3
FE+CT
−4
−2
0
VG (V)
2
4
n+
2
0
8 10 12 14 16
4
6
FE:10nm
SiO2: 1nm
n+
n+
FE:10nm
SiO2: 1nm
n+
n+
SiOGate
2: 2nm
SiO2: 2nm
SiNx: 5nm
SiO2: 2nm
FE:10nm
SiO2: 1nm
n+
(i) 10
w/o Al2O3 (±11V, 10s)
10−6
4
6
8 10 12 14
−2
10−4
2nm Al2O3 (±15V, 10s)
10−5
2
Voltage Amplitude (V)
1nm Al2O3 (±13V, 10s)
10−6
Gate
SiO2: 2nm
SiNx: 5nm
Gate
Al2O3: 2nm
SiNx: 5nm
0
2
−3
10−10
6
Voltage Amplitude (V)
Ring FeFET (Diameter:51m)
VD=50mV, DC Sweep
(h)
8 FE+CT+Al2O3
2nm Al2O3
2nm SiO2
ONO
FeFET: W/L=50m/1m;
VD=50mV, DC Sweep
10−6
10−8
10−10
−6 −4 −2 0
2
VG (V)
4
6
8
10−12
−8 −6 −4 −2 0
2
VG (V)
4
6
(j)
Drain Current (A)
5nm
SiO2
O
Si
W
Hf
Zr
N
Al
FE+CT+Al2O3
ID (A)
HZO
80
60
(g) 10 Pulse width: 10s; W/L=40m/4m
(f) 14
Pulse width: 10s; W/L=40m/4m
12
2nmAl2O3/5nmSiNx/10nmHZO
100
MW (V)
AlOx
SiNx
(c)
ID (A)
W
Atomic Fraction (%)
(a)
8
10−4
10−6
10−8
2nm Al2O3 2nm Block oxi.: ±15V, 10s
ONO: ±20V, 10s
2nm SiO2
ONO
11.94V
−8 −6 −4 −2 0 2 4 6 8 10
Voltage (V)
Fig.10. (a) TEM image of FE+CT+2nm Al2O3 structure. (b) Elemental mapping of the gate stack with blocking oxide. (c) Atomic
composition of the gate stack cross-sectional direction. (d) DC ID-VG with different blocking oxide thickness. (f) Pulse ID-VG with different
blocking oxide thicknesses. (f) switching dynamics and (g) ISPP slope of different blocking oxide thickness. (h) Comparison between
different blocking oxide layers: Al2O3, SiO2, ONO structures in (i) DC ID-VG, (j) Pulse ID-VG measurement results.