EGEE 281: VHDL & Digital System Design
Fall 2024
Lab 4: VHDL Structural Modeling
Student Name:
Lab Objectives: The main purpose of this lab project is to help students learn how to
construct and implement the architecture of a digital system’s entities that are based on
structural modeling process.
Evaluation: Grade for lab will be based on 1) In-lab activities, and 2) Lab report.
Lab Duration: 3 lab sessions
Lab Report: Lab report based on this instruction sheet will be collected on Friday, Dec
6th. The completed lab report shall be emailed to lannguyen@fullerton.edu. Name your
lab report as LAB1_EE281_YourName.doc, e.g., LAB1_EE281_DoeJohn.doc.
Note: No pdf allowed and points deduction if file name is not shown as above
Please ask the instructor to verify your simulation results for the questions after you
finish each one of them.
Q1) Design a 1-bit full-adder
Based on the following diagram, design a 1-bit full-adder using the structural modeling.
Please design the entity as well as the test bench for this 1-bit full adder.
Your entity design is:
****Full Adder ****
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (In1, In2,c_in: in std_logic;
sum, c_out: out std_logic);
end entity full_adder;
architecture structural of full_adder is
component half_adder is
port(x,y: in std_logic;
sum, carry: out std_logic);
end component half_adder;
component or_2 is
port(x,y: in std_logic;
z: out std_logic);
end component or_2;
signal s1, s2, s3: std_logic;
begin
H1: half_adder port map (x => In1, y=> In2, sum=> s1, carry=> s3);
H2: half_adder port map (x => s1, y=> c_in, sum=> sum, carry=> s2);
Or1: or_2 port map (x=>s2, y=> s3, z=> c_out);
end architecture structural;
**** Half Adder****
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (x,y: in std_logic;
sum, carry: out std_logic);
end entity half_adder;
architecture structural of half_adder is
begin
sum <= x xor y;
carry <= x and y;
end architecture structural;
**** Or2 ****
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (x,y: in std_logic;
sum, carry: out std_logic);
end entity half_adder;
architecture structural of half_adder is
begin
sum <= x xor y;
carry <= x and y;
end architecture structural;
Your test bench design is:
In your test bench design, please let In1, In2, and C_in go through all eight combinations
(000, 001, 010, 011, 100, 101, 110 and 111) each at 100 ns.
library ieee;
use ieee.std_logic_1164.all;
entity TESTBNCH is
end TESTBNCH;
architecture stimulus of TESTBNCH is
component full_adder
port (In1, In2, c_in: in std_logic;
sum, c_out: out std_logic);
end component;
constant PERIOD: time := 100 ns;
signal In1, In2, c_in: std_logic:='0';
signal sum, c_out: std_logic:='0';
signal done: boolean := false;
begin
DUT: full_adder port map (
In1 => In1, In2 => In2, c_in => c_in,
sum => sum, c_out => c_out);
STIMULUS1: process
begin
In1 <= '0'; In2 <= '0'; c_in <= '0';
wait for PERIOD;
assert(sum = '0' and c_out = '0')
report "FA failed at 0" severity error;
In1 <= '0'; In2 <= '0'; c_in <= '1';
wait for PERIOD;
assert(sum = '1' and c_out = '0')
report "FA failed at 1" severity error;
In1 <= '0'; In2 <= '1'; c_in <= '0';
wait for PERIOD;
assert(sum = '1' and c_out = '0')
report "FA failed at 2" severity error;
In1 <= '0'; In2 <= '1'; c_in <= '1';
wait for PERIOD;
assert(sum = '0' and c_out = '1')
report "FA failed at 3" severity error;
In1 <= '1'; In2 <= '0'; c_in <= '0';
wait for PERIOD;
assert(sum = '1' and c_out = '0')
report "FA failed at 4" severity error;
In1 <= '1'; In2 <= '0'; c_in <= '1';
wait for PERIOD;
assert(sum = '0' and c_out = '1')
report "FA failed at 5" severity error;
In1 <= '1'; In2 <= '1'; c_in <= '0';
wait for PERIOD;
assert(sum = '0' and c_out = '1')
report "FA failed at 6" severity error;
In1 <= '1'; In2 <= '1'; c_in <= '1';
wait for PERIOD;
assert(sum = '1' and c_out = '1')
report "FA failed at 7" severity error;
done <= true;
wait;
end process;
end stimulus;
The result waveforms are:
Please select the signals to be simulated in the following order: In1, In2, C_in, C_out, Sum.
Q2) Design an 8 channel Switching Unit
For this part, design an 8 channel switching unit based on the diagram given below,
I7 to I0
8-to-1
1-to-8
Multiplexer
Demultiplexer
S1(2:0)
O7 to O0
S2(2:0)
According to this diagram, the S1 selection signal will decide which input channel goes
through the 8-to-1 Multiplexer; and the S2 selection signal will decide which output channel
the signal will be sent to by the 1-to-8 DeMultiplexer.
Please design the entity as well as the test bench for this memory circuit.
Your entity design is:
**** Main Entity****
library ieee;
use ieee.std_logic_1164.all;
entity SWITCH is
port(I7, I6, I5, I4, I3, I2, I1, I0: in std_logic;
Sel1, Sel2: in std_logic_vector(2 downto 0);
O7, O6, O5, O4, O3, O2, O1, o0: out std_logic);
end entity SWITCH;
architecture structural of SWITCH is
component MUX8 is
port (Sel:in std_logic_vector(2 downto 0);
I7, I6, I5, I4, I3, I2, I1, I0: in std_logic;
Out1: out std_logic);
end component MUX8;
component DEMUX8 is
port (Sel:in std_logic_vector(2 downto 0);
In0 : in std_logic;
O7, O6, O5, O4, O3, O2, O1, O0: out std_logic);
end component DEMUX8;
signal connect:std_logic;
begin
M1: MUX8 port map (Sel=>Sel1, I7=>I7, I6=>I6, I5=>I5, I4=>I4,
I3=>I3, I2=>I2, I1=>I1, I0=>I0, Out1=>connect);
M2: DEMUX8 port map (Sel=>Sel2, In0=>connect, O7=>O7, O6=>O6,
O5=>O5, O4=>O4, O3=>O3, O2=>O2, O1=>O1, O0=>O0);
end architecture structural;
**** MUX8****
library ieee;
use ieee.std_logic_1164.all;
entity MUX8 is
port (Sel:in std_logic_vector(2 downto 0);
I7, I6, I5, I4, I3, I2, I1, I0: in std_logic;
Out1: out std_logic);
end MUX8;
architecture behavior of MUX8 is
begin
process(Sel, I7, I6, I5, I4, I3, I2, I1, I0)is
variable zout: std_logic;
begin
if sel = "000" then zout:= I0;
elsif sel= "001" then zout:= I1;
elsif sel= "010" then zout:= I2;
elsif sel= "011" then zout:= I3;
elsif sel= "100" then zout:= I4;
elsif sel= "101" then zout:= I5;
elsif sel= "110" then zout:= I6;
elsif sel= "111" then zout:= I7;
else zout:= '0';
end if;
Out1 <= zout;
end process;
end architecture behavior;
**** DEMUX8****
library ieee;
use ieee.std_logic_1164.all;
entity DEMUX8 is
port (Sel:in std_logic_vector(2 downto 0);
In0 : in std_logic;
O7, O6, O5, O4, O3, O2, O1, O0: out std_logic);
end DEMUX8;
architecture behavior of DEMUX8 is
begin
process(Sel, In0)is
variable zout: std_logic;
begin
O0 <='0';
O1 <='0';
O2 <='0';
O3 <='0';
O4 <='0';
O5 <='0';
O6 <='0';
O7 <='0';
if sel = "000" then O0<= In0;
elsif sel= "001" then O1<= In0;
elsif sel= "010" then O2<= In0;
elsif sel= "011" then O3<= In0;
elsif sel= "100" then O4<= In0;
elsif sel= "101" then O5<= In0;
elsif sel= "110" then O6<= In0;
elsif sel= "111" then O7<= In0;
end if;
end process;
end architecture behavior;
Your test bench design is:
In your test bench design, please go through the following test sequence.
1. Enable inputs from I0 (go through 0 and 1 for 100 ns each), send this signal to
output O4.
2. Enable inputs from I2 (go through 0 and 1 for 100 ns each), send this signal to
output O6.
3. Enable inputs from I5 (go through 0 and 1 for 100 ns each), send this signal to
output O7.
4. Enable inputs from I7 (go through 0 and 1 for 100 ns each), send this signal to
output O0.
Library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBNCH is
end TESTBNCH;
architecture stimulus of TESTBNCH is
component SWITCH
port(I7, I6, I5, I4, I3, I2, I1, I0: in std_logic;
Sel1, Sel2: in std_logic_vector(2 downto 0);
O7, O6, O5, O4, O3, O2, O1, O0: out std_logic);
end component;
constant PERIOD: time := 100 ns;
signal Sel1, Sel2: std_logic_vector(2 downto 0):="000";
signal I7, I6, I5, I4, I3, I2, I1, I0: std_logic:='0';
signal O7, O6, O5, O4, O3, O2, O1, O0: std_logic:='0';
signal done : boolean := false;
begin
DUT: SWITCH port map (I7 => I7, I6 => I6, I5 => I5, I4 => I4,
I3 => I3, I2 => I2, I1 => I1, I0 => I0,
Sel1 => Sel1, Sel2 => Sel2,
O7 => O7, O6 => O6, O5 => O5, O4 => O4,
O3 => O3, O2 => O2, O1 => O1, O0 => O0);
STIMULUS1: process
begin
I0 <= '0'; Sel1 <= "000"; Sel2 <= "100";
wait for PERIOD;
I0 <= '1'; Sel1 <= "000"; Sel2 <= "100";
wait for PERIOD;
I2 <= '0'; Sel1 <= "010"; Sel2 <= "110";
wait for PERIOD;
I2 <= '1'; Sel1 <= "010"; Sel2 <= "110";
wait for PERIOD;
I5 <= '0'; Sel1 <= "101"; Sel2 <= "111";
wait for PERIOD;
I5 <= '1'; Sel1 <= "101"; Sel2 <= "111";
wait for PERIOD;
I7 <= '0'; Sel1 <= "111"; Sel2 <= "000";
wait for PERIOD;
I7 <= '1'; Sel1 <= "111"; Sel2 <= "000";
wait for PERIOD;
done <= true;
wait;
end process;
end stimulus;
The result waveforms are:
Please select the signals to be simulated in the following order: I7, I6, I5, I4, I3, I2, I1, I0, S1,
S2, O7, O6, O5, O4, O3, O2, O1 and O0.
Q3) Design a Generic N-bit Register
For this part, please design a generic N-bit register that has the following behavior,
When the ‘Reset’ input is high, the N-bit output Q will become all ‘0’ after 10 ns.
When the ‘Set’ input is high, the N-bit output Q will become all ‘1’ after 10 ns.
Otherwise, when the rising edge of the clock signal ‘Clk’ arrives, the value of the Nbit input ‘Input’ will be directly transmitted to the output Q after 10 ns.
Please design the entity as well as the test bench for this generic N-bit Register.
Your entity design is:
library ieee;
use ieee.std_logic_1164.all;
entity generic_reg is
generic (n: positive:=2);
port (Clk, Reset, Set: in std_logic;
Input: in std_logic_vector (n-1 downto 0);
Q: out std_logic_vector (n-1 downto 0));
end entity generic_reg;
architecture behavioral of generic_reg is
begin
reg_process: process (Clk, Reset, Set) is
begin
if Reset='1' then
Q <= (others => '0') after 10 ns;
elsif Set='1' then
Q <= (others => '1') after 10 ns;
elsif (rising_edge(Clk)) then
Q <= Input after 5 ns;
end if;
end process reg_process;
end architecture behavioral;
Your test bench design is:
In your test bench design, please set up the clock signal to run at a period of 100 ns.
Then, setup a 16-bit Register in the test bench.
First, Reset this register by letting the ‘Reset’ signal to be high for 200 ns, then become low.
Next, Set the register by letting the ‘Set’ signal to be high for 200 ns, then become low.
After that, let the following inputs: $4321, $8765, $BA09, $FEDC go through the 16-bit
Register, each at 100 ns.
library ieee;
use ieee.std_logic_1164.all;
entity TESTBNCH is
end TESTBNCH;
architecture stimulus of TESTBNCH is
component generic_reg
generic (n: positive:=2);
port (Clk, Reset, Set: in std_logic;
Input: in std_logic_vector (n-1 downto 0);
Q: out std_logic_vector (n-1 downto 0));
end component;
constant PERIOD: time := 100 ns;
constant PERIOD1: time := 200 ns;
signal Clk, Reset, Set: std_logic :='0';
signal Input: std_logic_vector (15 downto 0):=x"0000";
signal Q: std_logic_vector (15 downto 0):=x"0000";
signal done: boolean := false;
begin
DUT: generic_reg
generic map (n=>16)
port map (Clk => Clk, Reset => Reset, Set => Set, Input => Input, Q => Q);
clock_process: process is
begin
clk <= '0','1' after 50 ns;
wait for PERIOD;
end process clock_process;
STIMULUS1: process
begin
Reset <= '1';
wait for PERIOD1;
Reset <= '0';
Set <= '1';
wait for PERIOD1;
Set <= '0';
Input <= x"4321";
wait for PERIOD;
Input <= x"8765";
wait for PERIOD;
Input <= x"BA09";
wait for PERIOD;
Input <= x"FEDC";
wait for PERIOD;
done <= true;
wait;
end process;
end stimulus;
The result waveforms are:
Please select the signals to be simulated in the following order: Clk, Reset, Set, Input, Q.
library ieee;
use ieee.std_logic_1164.all;
entity TESTBNCH is
end TESTBNCH;
architecture stimulus of TESTBNCH is
component generic_reg
generic (n: positive:=2);
port (Clk, Reset, Set: in std_logic;
Input: in std_logic_vector (n-1 downto 0);
Q: out std_logic_vector (n-1 downto 0));
end component;
constant PERIOD: time := 100 ns;
constant PERIOD1: time := 200 ns;
signal Clk, Reset, Set: std_logic :='0';
signal Input: std_logic_vector (15 downto 0):=x"0000";
signal Q: std_logic_vector (15 downto 0):=x"0000";
signal done: boolean := false;
begin
DUT: generic_reg
generic map (n=>16)
port map (Clk => Clk, Reset => Reset, Set => Set, Input => Input, Q => Q);
clock_process: process is
begin
clk <= '0','1' after 50 ns;
wait for PERIOD;
end process clock_process;
STIMULUS1: process
begin
Reset <= '1';
wait for PERIOD1;
Reset <= '0';
Set <= '1';
wait for PERIOD1;
Set <= '0';
Input <= x"4321";
wait for PERIOD;
Input <= x"8765";
wait for PERIOD;
Input <= x"BA09";
wait for PERIOD;
Input <= x"FEDC";
wait for PERIOD;
done <= true;
wait;
end process;
end stimulus;
Q4) Design a Sequential Circuit
A 4-bit decade counter is one type of sequential circuit that will count through each of the
ten states as driven by a clock. The following shows the state transition diagram for a 4bit decade counter using Excess-3 code.
Based on this state transition diagram, 4 T Flip Flops can be used to implement the circuit
as their inputs given by,
T1 = Q1Q2 + Q2Q3Q4; T2 = Q1Q2+Q3Q4; T3 = Q1Q2+Q1’Q2’+Q4; and T4 = 1.
The behavior of the T-Flip Flops (TFF) can be described as below:
When the ‘Reset’ input is high, the output Q will become ‘0’. When the ‘Set’ input is
high, the output Q will become ‘1’. Otherwise, when the rising edge of the clock
signal ‘Clk’ arrives, the value of the output Q will be determined by an Exlusive-OR
operation between the ‘T’ input and current state Q.
Furthermore, the structural view of the whole circuit is given below:
Please design the entity as well as the test bench for this 4-bit decode counter.
Your entity design is:
****MAIN****
library ieee;
use ieee.std_logic_1164.all;
entity SEQ is
port (Clk, Reset, Set: in std_logic;
Q1, Q2, Q3, Q4: buffer std_logic);
end entity SEQ;
architecture structural of SEQ is
component TFF is
port (T, Clk, Reset, Set: in std_logic;
Q: buffer std_logic);
end component TFF;
component TCOMB is
port (Q1, Q2, Q3, Q4: in std_logic;
T1, T2, T3, T4: out std_logic);
end component TCOMB;
signal T1, T2, T3, T4 : std_logic;
begin
TFF1: TFF port map(Reset => Reset, Set => Set, Clk => Clk, T => T1, Q => Q1);
TFF2: TFF port map(Reset => Reset, Set => Set, Clk => Clk, T => T2, Q => Q2);
TFF3: TFF port map(Reset => Reset, Set => Set, Clk => Clk, T => T3, Q => Q3);
TFF4: TFF port map(Reset => Reset, Set => Set, Clk => Clk, T => T4, Q => Q4);
COMB1: TCOMB port map(T1 => T1, T2 => T2, T3 => T3, T4 => T4,
Q1 => Q1, Q2 => Q2, Q3 => Q3, Q4 => Q4);
end architecture structural;
****TFF****
library ieee;
use ieee.std_logic_1164.all;
entity TFF is
port (T, Clk, Reset, Set: in std_logic;
Q: buffer std_logic);
end entity TFF;
architecture behavioral of TFF is
begin
output: process(T, Reset, Set, Clk) is
begin
if Reset = '1' then
Q <= '0';
elsif Set = '1' then
Q <= '1';
elsif (rising_edge(Clk)) then
Q <= (T xor Q);
end if;
end process output;
end architecture behavioral;
**** TCOMB****
library ieee;
use ieee.std_logic_1164.all;
entity TCOMB is
port (Q1, Q2, Q3, Q4: in std_logic;
T1, T2, T3, T4: out std_logic);
end entity TCOMB;
architecture combinational of TCOMB is
begin
T1 <= (Q1 and Q2) or (Q2 and Q3 and Q4);
T2 <= (Q1 and Q2) or (Q3 and Q4);
T3 <= (Q1 and Q2) or ((not Q1) and (not Q2)) or Q4;
T4 <= '1';
end architecture combinational;
Your test bench design is:
In your test bench design, please set up the clock signal to run at a period of 100 ns.
Then, clear the values in the 4 T Flip-flops by letting the ‘Reset’ signal to be high for 100 ns,
then become low. After that, let the clock run freely.
Library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBNCH is
end TESTBNCH;
architecture stimulus of TESTBNCH is
component SEQ
port (Reset, Set, Clk: in std_logic;
Q4, Q3, Q2, Q1: buffer std_logic);
end component;
constant PERIOD: time := 100 ns;
signal Reset, Set, Clk: std_logic:='0';
signal Q4, Q3, Q2, Q1: std_logic;
signal done: boolean := false;
begin
DUT: SEQ port map (Reset => Reset, Set => Set,
Clk => Clk, Q4 => Q4, Q1 => Q1, Q2 => Q2, Q3 => Q3);
clock_process: process is
begin
Clk <= '0','1' after 50 ns;
wait for PERIOD;
end process clock_process;
STIMULUS1: process
begin
Reset <= '1';
Wait for PERIOD;
Reset <= '0';
Wait for PERIOD;
wait;
end process;
end stimulus;
The result waveforms are:
Please select the signals to be simulated in the following order: Clk, Reset, Q1, Q2, Q3, and
Q4.