CSE 332: Computer Architecture and Organization
Assignment #1
Spring 2025
1. BJT, MOSFET
Definition:
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BJT (Bipolar Junction Transistor): A semiconductor device that uses both electron and
hole charge carriers. It has three terminals: emitter, base, and collector.
MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor): A transistor used
for switching and amplifying signals, controlled by voltage rather than current.
Elaboration:
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BJTs need a small current at the base to control a larger current between the emitter and
collector, making them current-controlled devices.
MOSFETs work by applying voltage to the gate, which controls the flow of current
between the source and drain, making them voltage-controlled.
MOSFETs are widely used in modern electronics because they consume less power and
switch faster compared to BJTs.
2. Diode and LED (Light Emitting Diode)
Definition:
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Diode: A semiconductor device that allows current to flow in one direction only.
LED: A type of diode that emits light when current flows through it.
Elaboration:
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Diodes act like one-way valves, allowing electricity to flow in only one direction. They
are commonly used in power supplies to convert AC to DC.
LEDs are special diodes that emit light when electricity passes through them. They are
used in indicators, screens, and lighting because they are energy-efficient and longlasting.
Figure: (Include a diagram of a diode and an LED symbol.)
3. pMOS, nMOS, CMOS
Definition:
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pMOS (P-type MOSFET): Uses holes as charge carriers.
nMOS (N-type MOSFET): Uses electrons as charge carriers.
CMOS (Complementary Metal-Oxide-Semiconductor): Combines pMOS and nMOS
to reduce power consumption.
Elaboration:
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CMOS technology is used in microprocessors due to low static power consumption.
Figure: (Include a CMOS inverter circuit diagram.)
4. Universal Logic Gate
Definition:
A logic gate that can be used to implement any Boolean function. The two universal gates are
NAND and NOR.
Elaboration:
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NAND and NOR gates can be combined to create any other logic gate.
Used in digital circuit design for optimization.
Figure: (Include NAND and NOR truth tables.)
5. CMOS 3-input NAND Logic
Definition:
A NAND gate with three inputs built using CMOS technology.
Elaboration:
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Requires both pMOS and nMOS transistors.
Outputs LOW only when all inputs are HIGH.
Flowchart: (Include a transistor-level diagram of a 3-input NAND gate.)
6. Process Node Technology
Definition:
Refers to the manufacturing process of semiconductor devices, denoted in nanometers (e.g.,
7nm, 5nm).
Elaboration:
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Smaller nodes improve power efficiency and performance.
Used in microprocessors and GPUs.
Figure: (Include a diagram showing different process nodes over time.)
7. Edge Triggered D Flip-Flop
Definition:
A sequential circuit that stores data on a clock edge (rising or falling).
Elaboration:
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Captures the input value only at the edge of the clock signal.
Used in register designs.
Figure: (Include a D flip-flop circuit and timing diagram.)
8. Clock Edge
Definition:
The transition of a clock signal, either from low to high (rising edge) or high to low (falling
edge).
Elaboration:
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Used to synchronize operations in sequential circuits.
Figure: (Include a waveform illustrating rising and falling edges.)
9. Combinational Logic
Definition:
A type of digital circuit where the output depends only on the current inputs.
Elaboration:
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Does not use memory elements.
Examples: Adders, Multiplexers.
Flowchart: (Include a simple combinational logic block diagram.)
10. Sequential Logic
Definition:
A digital circuit where the output depends on both current and past inputs.
Elaboration:
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Uses memory elements like flip-flops.
Examples: Counters, Shift Registers.
Flowchart: (Include a sequential logic block diagram.)
11. Moore State Machine
Definition:
A finite state machine where the output depends only on the current state, not on the input
signals.
Elaboration:
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Outputs change only on state transitions.
Used in control units and digital logic design.
Flowchart: (Include a Moore state machine diagram.)
12. Register Transfer Level (RTL)
Definition:
A design abstraction that represents a digital circuit in terms of registers and transfer operations.
Elaboration:
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Used in digital design and synthesis.
Describes how data moves between registers.
Figure: (Include an RTL design example.)
13. Timing Diagram
Definition:
A graphical representation of signals in a digital circuit over time.
Elaboration:
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Shows relationships between different signals.
Used for debugging and analysis.
Figure: (Include a sample timing diagram.)
14. Karnaugh Map
Definition:
A diagram used to simplify Boolean algebra expressions.
Elaboration:
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Groups minterms to minimize logic functions.
Reduces circuit complexity.
Figure: (Include a 4-variable K-map example.)
15. Multiplexer (MUX)
Definition:
A digital circuit that selects one input from multiple inputs based on control signals.
Elaboration:
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Used in data selection and routing.
Reduces circuit complexity.
Figure: (Include a MUX circuit diagram.)
16. Demultiplexer (DEMUX)
Definition:
A digital circuit that takes a single input and routes it to one of several outputs based on control
signals.
Elaboration:
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Used in data routing and distribution.
Commonly found in memory and communication systems.
Figure: (Include a DEMUX circuit diagram.)
17. Decoder
Definition:
A circuit that converts binary input into a unique output line.
Elaboration:
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Used in address decoding and instruction decoding.
Helps in memory selection and data processing.
Figure: (Include a decoder truth table and circuit diagram.)
18. Encoder
Definition:
A circuit that converts multiple input lines into a smaller number of output lines.
Elaboration:
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Opposite of a decoder.
Used in communication systems and data compression.
Figure: (Include an encoder truth table and circuit diagram.)
19. Full Bit Adder
Definition:
A combinational circuit that adds three binary inputs (A, B, and Carry-in) to produce a sum and a
carry-out.
Elaboration:
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Used in arithmetic circuits and ALUs.
Essential for multi-bit binary addition.
Figure: (Include a full adder circuit diagram and truth table.)
20. Ripple Carry Adder
Definition:
A multi-bit adder formed by cascading full adders, where the carry propagates through each
stage.
Elaboration:
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Simple but slow due to carry propagation delay.
Used in ALUs for binary addition.
Figure: (Include a ripple carry adder circuit diagram.)
31. Photolithography in Chip Fabrication
Definition:
A process used in semiconductor manufacturing to transfer circuit patterns onto a silicon wafer
using light.
Elaboration:
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Uses masks and photoresists to define microchip structures.
Essential for fabricating transistors and interconnects in modern processors.
Figure: (Include a photolithography process diagram.)
32. RTL Synthesis
Definition:
A process of converting Register Transfer Level (RTL) descriptions into a gate-level netlist for
hardware implementation.
Elaboration:
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Converts high-level HDL descriptions into circuit components.
Used in ASIC and FPGA design workflows.
Figure: (Include an RTL synthesis flowchart.)
33. HDL (Hardware Description Language)
Definition:
A programming language used to describe and simulate digital circuits. Examples include VHDL
and Verilog.
Elaboration:
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Enables hardware design before physical implementation.
Used for FPGA, ASIC, and custom digital logic design.
Figure: (Include an example HDL code snippet.)
34. EDA (Electronic Design Automation) Example
Definition:
A category of software tools used to design, verify, and simulate electronic systems.
Elaboration:
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Examples include Synopsys, Cadence, and Mentor Graphics.
Used for circuit layout, timing analysis, and verification.
Figure: (Include a diagram showing the EDA workflow.)
35. VHDL, Verilog
Definition:
VHDL and Verilog are two widely used Hardware Description Languages (HDLs) for digital
circuit design.
Elaboration:
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VHDL is more verbose and strongly typed, commonly used in academia.
Verilog is simpler and preferred in industry for FPGA and ASIC development.
Figure: (Include a table comparing VHDL and Verilog features.)
36. FPGA (Field-Programmable Gate Array)
Definition:
A reconfigurable integrated circuit that can be programmed to perform various digital logic
functions.
Elaboration:
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Used in prototyping, low-volume production, and specialized applications.
Consists of logic blocks, interconnects, and I/O interfaces.
Figure: (Include an FPGA architecture diagram.)
37. CPLD (Complex Programmable Logic Device)
Definition:
A programmable logic device with a more rigid structure than an FPGA but higher density than
simple PLDs.
Elaboration:
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Offers predictable timing and lower power consumption than FPGAs.
Used in control systems, industrial applications, and simple digital logic.
Figure: (Include a CPLD block diagram.)
38. ASIC (Application-Specific Integrated Circuit)
Definition:
A custom-designed semiconductor chip optimized for a specific application.
Elaboration:
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Offers higher performance and lower power consumption compared to FPGAs.
Used in smartphones, GPUs, and networking hardware.
Figure: (Include an ASIC design workflow diagram.)
39. Gate-Level Design
Definition:
A low-level digital circuit representation based on logic gates.
Elaboration:
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Derived from RTL synthesis.
Used in timing and power optimization stages of chip design.
Figure: (Include an example gate-level circuit diagram.)
40. Testbench
Definition:
A simulation environment used to verify the correctness of a hardware design written in HDL.
Elaboration:
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Defines stimulus and expected responses for digital circuits.
Used in FPGA and ASIC verification processes.
Figure: (Include an example testbench code snippet.)
41. DFT (Design for Testability)
Definition:
A design methodology that incorporates features to facilitate testing of integrated circuits.
Elaboration:
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Enhances fault detection and diagnosis in chip design.
Used in scan chains, built-in self-test (BIST), and boundary scan techniques.
Figure: (Include a DFT architecture diagram.)
42. Logic Synthesis
Definition:
The process of converting a high-level hardware description into an optimized gate-level
representation.
Elaboration:
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Converts HDL code into logic gates using EDA tools.
Optimizes for area, power, and performance.
Figure: (Include a logic synthesis workflow diagram.)
43. Power Optimization
Definition:
Techniques used to minimize power consumption in digital circuits.
Elaboration:
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Includes clock gating, voltage scaling, and power gating.
Essential for battery-powered and energy-efficient systems.
Figure: (Include a power optimization techniques chart.)
44. Heterogeneous Multicore Processor
Definition:
A processor that integrates different types of cores optimized for various tasks.
Elaboration:
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Combines high-performance and energy-efficient cores.
Used in smartphones, gaming consoles, and embedded systems.
Figure: (Include a heterogeneous multicore architecture diagram.)
45. Cache
Definition:
A small, fast memory located close to the CPU to store frequently accessed data.
Elaboration:
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Reduces access time compared to main memory.
Operates in levels (L1, L2, L3) for better performance.
Figure: (Include a cache memory hierarchy diagram.)
46. Main Memory
Definition:
The primary storage used by a computer to hold active programs and data.
Elaboration:
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Includes RAM (volatile) and ROM (non-volatile) types.
Acts as an interface between cache and secondary storage.
Figure: (Include a memory hierarchy diagram.)
47. Name Five Steps Between Sand to Chip
Definition:
The semiconductor manufacturing process converts raw silicon into functional microchips.
Elaboration:
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Steps: Silicon extraction, wafer fabrication, photolithography, etching, and packaging.
Requires high precision and cleanroom environments.
Figure: (Include a semiconductor fabrication process flowchart.)
48. Name Five Stages Between HDL to Chip Layout
Definition:
The process of converting HDL designs into a physical chip layout.
Elaboration:
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Steps: RTL design, synthesis, place & route, verification, and fabrication.
Ensures correctness before production.
Figure: (Include a chip design flow diagram.)
49. RISC, CISC
Definition:
Two types of processor architectures: Reduced Instruction Set Computing (RISC) and Complex
Instruction Set Computing (CISC).
Elaboration:
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RISC uses simple, fixed-length instructions for efficiency.
CISC uses complex, variable-length instructions for flexibility.
Found in ARM (RISC) and x86 (CISC) architectures.
Figure: (Include a RISC vs CISC comparison chart.)
50. Wafer, Die, Chip Packaging
Definition:
Key steps in semiconductor manufacturing from silicon wafers to final chip products.
Elaboration:
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Wafer: Thin slice of semiconductor material used for fabrication.
Die: Individual circuit extracted from a wafer.
Packaging: Protects and connects the die to external circuits.
Figure: (Include a wafer-to-chip packaging process diagram.)