B.E/ B.TECH DEGREE EXAMINATIONS:APRIL 2014
Subject:Digital logic circuits
ANSWER KEY
PART A
1) Given that (456)r = (237)10. Find r
(456)r = (237)10
2
4 r + 5 r + 6 = 237
4 r2 + 5 r - 231 = 0
r = 7, -8.25 & -8.25 is invalid.
r =7.
2) subtract the unsigned number (10100)2 from (11011)2 using 1’s
complement & 2’s compliment method.
Let x = (11011)2 = (27)10,
Y = (10100)2 = (20)10
________
(7)10
x = 11011
1’s compliment of y = 01011(+)
_________
sum= 100110
end around carry =
1 (+)
_______
x – y = 00111
x = 11011
2’s compliment of y = 01100
_________
sum= 100111
(+)
discard end carry
answer x – y = 00111
3) Express f(a,b,c)= a+bc’ as sum of minterms
To form sum of minterms:
a=a(b+b’)(c+c’)
=(ab+ab’)(c+c’)
=abc+abc’+ab’c+ab’c’
b’c=(a+a’)b’c
=ab’c+a’b’c
f(a,b,c) =abc+abc’+ab’c+ab’c’+ ab’c+a’b’c
f(a,b,c)=∑(1,4,5,6,7)
4) Distinguish TTL&CMOS logic family
TTL
CMOS
1) TTL IC’s are designed to
operate on 5v supply.
2) High power supply current
is required.
3) High speed of operation &
high power dissipation.
4) Lesser packing density &
fabrication
process
is
complex.
1) CMOS IC’s work with any
power supply from 5V to
1V.
2) Very low power supply
current is required.
3) Low speed of operation and
love power dissipation.
4) Greater packing density
and fabrication process is
simpler.
5) Realize the half adder circuit using decoder?
X
0
0
1
1
Y
0
1
0
1
S
0
1
1
0
C
0
0
0
1
S(x,y) =  m(1, 2) C(x,y) =  m(3)
6) What is a multiplexer?
A
Multiplexer is a combinational circuit
that selects binary
information from one of many input lines & directs it to a single output
line .There are 2n input lines & n selection lines whose bit
combinations determine which input is selected.
7) Implement the following Boolean function using three half adder
circuits?
F1=
F2=x’yz+x y’z
F3=xyz’+(x’+y’)z=
F4=xyz
8) what is priority encoder?
A priority is an encoder circuit that includes the priority function.
In priority encoder, if 2 or more inputs are equal to 1 at the same
time, the input having the highest priority will take procedure.
9) what is a sequential logic circuit?
It is a logic circuit whose output at any time are determined
from the present input and past output. It requires a memory element
to store the previous output.
Ex: flipflops, counters and shift registers.
10) what is state reduction?
The reduction of number of flipflop in a sequential circuit us
referred to as the state reduction. Generally state reduction algorithm
is concerned with procedures for reducing the number of states in a
state while keeping the external input- output requirements
unchanged.
11) How many flipflops are needed to design a mod 60 counter?
Number of flipflops required to design a mod 60 counter are
six. (since 26 = 64)
12) what are fundamental mode circuits?
Fundamental mode circuit is a type of asynchronous sequential
circuit, in which the input variable can change at any one time & the
time between two input changes must be longer than the time it takes
the circuit to reach a stable state.
13) Compare RAM and ROM
ROM
RAM
ROM is a read only memory
RAM is a random access memory
It can perform only read operation It can perform both write and read
operation
It is a non volatile memory
It is a volatile memory
14) Distinguish PAL&PLA
PAL
PLA
It is a combinational PLD and It has programmable AND array
has a programmable AND array and a programmable OR array
and fixed OR array
15) What is SRAM & DRAM
SRAM: static RAM consist of internal latches that store the
binary information. The stored information remains valid as long as
power is applied to the unit.
DRAM: Dynamic RAM stores the binary information in the form
of electric charges on capacitors.
16) What is FPGA?
A field programmable gate array (FPGA) is a VLSI circuit that can be
programmed in the user’s location. It consist of an array of hundreds
or thousands of logic blocks, surrounded by programmable input and
output blocks and connected together via programmable
interconnection.
17) What is static and dynamic Hazard?
Hazard exists in a combinational circuit realizing a Boolean function.
Static hazard:
It causes the output to go to 0 or 1, when it should remain a 1 or 0.
dynamic Hazard:
It causes the output to change three or more times when it should
change from 1 to 0 or from 0 to 1
18) what are advantages of IDDQ testing?
i) It is a simple and direct test than can identify physical defects.
ii) The area and design time overhead are low.
iii)Test generation is fast.
iv)Test application time is fast since the vector sets are small.
v)It catches some defects that other tests, particularly stuck at logic
tests do not.
19)Mention the various techniques of design for Testability(DFT)
 ad hoc technology
 scan based design
 Boundary scan
20)what is ATPG (automatic test pattern generation)
It is a process used in semiconductor electrical testing wherein
the vectors or patterns required to check a device for faults are
automatically generated by a program. The vectors are sequentially
applied to the device under test & the device’s response to each set
of inputs is compared with the expected response from a good
circuit. An error in the response of the device means that it is faulty.
PART B (5X12 = 60 marks)
ANSWER ANY FIVE QUESTIONS
21)a)Reduce the following Boolean expression to indicated number of
literals.
i)A’B(D’+C’D)+B(A+A’CD) to one literal
(3)
=A’BD+A’BC’D+AB+A’BCD
=A’BD’+AB+A’BD(C+C’)
=A’B(D+D’)+AB
=B(A+A’)
=B
ii)AB’C+B+BD’+ABD’+A’C
to two literals (3)
=AB’C+B(1+D’)+ABD’+A’C
=AB’C+B(1+AD’)+A’C
=AB’C+B+A’C
=C(AB’+A’)+B
=C[(B’+A’)(A+A’)]+B
=C[B’+A’]+B=CB’+B+CA’
=C+B+CA’=C(1+A’)+B=C+B
b) Explain the working of a 2 input TTL NAND gate
(6)
circuit diagram:
When VBE is 0.7V (or) more +ve than emitter ,the transistor is turned
ON . When VBE is < 0.7V,the transistor is turned OFF.
Inputs Transistor condition
A
B Q2
Q3
Q4
L
L
H
H
L
H
L
H
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
output
H
H
H
L
22)a)Express the following function in sum of minterms &product of
maxterms
F(A,B,C,D)=B’D+A’D+BD
(6)
Sum of minterms:
B’D=B’D(A+A’)(C+C’)
=AB’CD+A’B’CD+AB’C’D+A’B’C’D
A’D=A’D(B+B)(C+C’)
=A’BCD+A’B’CD+A’BC’D+A’B’C’D
BD=BD(A+A’)(C+C’)
=ABCD+ABC’D+A’BCD+A’BC’D
F(A,B,C,D)=  m(1,3,5, 7,9,11,13,15)
Product of max terms:
F=D(A’+B’+B)=D(A’+1)=D
F=D+AA’+BB’+CC’
=(A+D)(A’+D)+BB’+CC’
=(A+B+D)(A’+B+D)(A+B’+D)(A’+B’+D)+CC’
=(A+B+C+D) (A’+B+C+D) (A+B’+C+D) (A’+B’+C+D)
(A+B+C’+D) (A’+B+C’+D) (A+B’+C’+D) (A’+B’+C’+D)
F(A,B,C,D)=  m(2, 4,6,8,10,12,14)
b) Explain the working of a 2 input CMOS NAND gate
(6)
circuit diagram:
A two input NAND gate consists of two p-type units in parallel
and two n-type Units in series. If all inputs are high, both p-channel
transistors turn off and both n-channel transistors turn on. The output
has a low impedance to ground and produces a low state. If any input
is low, the associated n-channel transistor is turned off and the
associated p-channel transistor is turned on. The output
is coupled to Vdd and goes to the high state.
Inputs
Transistor condition
A
B Q1 Q2
Q3
Q4
output
L
L
H
H
H
H
H
L
L
H
L
H
ON
ON OFF
OFF ON OFF
ON
ON
ON
OFF OFF ON
OFF
ON
OFF
ON
23) Design and construct excess-3 to BCD code converter
EXCESS-3 TO BCD CONVERTER
K-Map for A:
K-Map for B:
A = X1 X2 + X3 X4 X1
K-Map for C:
EXCESS-3 TO BCD CONVERTOR
K-Map for D:
(12)
TRUTH TABLE:
Excess – 3 Input
X1
0
0
0
0
0
1
1
1
1
1
X2
0
1
1
1
1
0
0
0
0
1
X3
1
0
0
1
1
0
0
1
1
0
X4
1
0
1
0
1
0
1
0
1
0
BCD Output
A
0
0
0
0
0
0
0
0
1
1
B
0
0
0
0
1
1
1
1
0
0
C
0
0
1
1
0
0
1
1
0
0
|
D
0
1
0
1
0
1
0
1
0
1
24) Simplify the following using Quine Mccluskey method.
F (w,x,y,z)=  m(1,3, 4,5,9,10,11)   d (6,8)
Solution:
I) Grouping minterms for different number of 1’s.
(12)
Number
of 1’s
minterms
1
1
4
8
Variables
w x y
z
0 0 0 0
0 1 0 0
1 0 0 0
2
3
5
6
9
10
11
0
0
0
1
1
1
3
0
1
1
0
0
0
1 1
0 1
1 0
0 1
1 0
1 1
2 Cell Combinations:
Combination
(1,3)
(1,5)
(1,9)
(4,5)
(4,6)
(8,9)
(8,10)
(3,11)
(9,11)
(10,11)
W
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
0
0
0
Y
0
0
0
0
1
1
Z
1
1
1
0
0
1
1
-
W
1
X
0
0
Y
-
Z
1
-
4 Cell Combinations:
Combination
(1,3,9,11)
(8,9,10,11)
Prime Implicant Chart:
PI
1
11
X
(1,5)
(4,5)
(4,6)
(1,3,9,11) x
(8,9,10,11)
Minterms
4
5
9
3
10
X
X
X
X
x
X
X
X

X
x

From the PI chart the min terms(1,3,9,11) & (8,9,10,11) are the
essential prime implicants(EPI). Therefore in order to cover the
remaining minterms 4&5 the prime implicant (4,5) can be selected in
addition to EPI, for obtaining minimal sum of product expression.
F(w,x,y,z)= x’ z+ w x’+ w’ x y’
25) a)Describe the working of JK FF with diagram. Give its excitation
table
JK FLIP FLOP:
The indeterminate state in the SR Flip-Flop is defined in the JK
Flip Flop. JK inputs behave like S and R inputs to set and reset the
Flip Flop. The output Q is ANDed with K input and the clock pulse,
similarly the output Q’ is ANDed with J input and the Clock pulse.
When the clock pulse is zero both the AND gates are disabled and
the Q and Q’ output retain their previous values. When the clock
pulse is high, the J and K inputs reach the NOR gates. When both
the inputs are high the output toggles continuously.
excitation table:
Q
Q(next)
J
K
0
0
0
X
0
1
1
X
1
0
X
1
1
1
X
0
b) A sequential circuit has two JK flip-flops A and B and one input x.
The circuit is described by the following flip-flop input equations:
JA = x
K A = B'
JB = x
KB = A
i)Derive the state equations.
ii) Draw the state diagram of the circuit.
solution
i)The state equation for JK FF
QA(n+1) = JA QA’ + KA’ QA= x A’ + A B
QA(n+1) = JBQB’ + KB’ QB = x B’ + A’ B
(2)
(4)
state table:
Present state input Next state
QA
QB
x
QA(n+1) QB(n+1)
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
JA
0
0
x
x
FF inputs
KA JB
KB
x 0
x
x x
0
1 0
x
0 x
1
0
0
1
1
1
1
x
x
x
x
1
0
0
1
0
1
1
1
1
1
1
1
0
1
1
1
1
0
1
x
1
x
x
0
x
1
Reduced state table:
PS
QA
0
0
1
1
QB
0
1
0
1
NS
QA(n+1) QB(n+1)
x =0
x =1
0
0
1
1
0
1
1
1
0
0
0
1
1
0
1
0
State diagram:
26)An Asynchronous sequential circuit is described by the following
excitation &output functions
Y=x1x2’+(x1+x2’)y
Z=y
i)Draw the logic diagram of the circuit
(2)
ii)Derive the transition table & output map
(4)
iii)Obtain two state flow table
(2)
iv)Describe the behavior of circuit
(4)
Logic diagram:
Present
Next
Total state Total
state
x1 x2 y X1 X2
Stable
state
Output
Y yes/no
Z=Y
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
YES
YES
YES
YES
YES
YES
YES
YES
Transition table:
Plot of y
Map for z
2- state flow table
When the input is 01,the output is 0,when the input is 10,the output is
1,Whenever the input assumes one of the other two combinations,
the output retains its previous value.
27) Implement the given functions using PLA
A(x,y,z)=  m(1, 2, 4, 6)
B(x,y,z)=  m(0,1, 6, 7)
C(x,y,z)=  m(2, 6)
combining 0’s A=(xz+yz+x’y’z’)’
combining 1’s A=(yz’+xz’+x’y’z)
Combining 0’s B=(xy’+x’y)’
Combining 1’s B=(x’y’+xy)
(12)
Combining 0’s C=(y’+z’)’
Combining 1’s C=yz’
PLA programming table:
Product term
yz’
xz’
x’y’z
xy’
x’y
1
2
3
4
5
Input
X
Y
1
1
0
0
1
0
0
1
Z
0
0
1
-
Output
A(T) B(C)
1
1
1
1
1
C(T)
1
-
28) a) Find a circuit that has no static hazards Implements the
Boolean function F (A,B,C,D)=  m(0, 2, 6, 7,8,10,12)
(6)
f=A’BC+AC’D’+B’D’+A’CD’
K map simplification ------- 4 mark
Draw the hazard free circuit --------------- 2 mark
28) b) Explain the concept built in self list. Mention its advantages
and disadvantages
(6)
Built-in Self Test, or BIST, is the technique of designing additional
hardware and software features into integrated circuits to allow them
to perform self-testing, i.e., testing of their own operation
(functionally, parametrically, or both) using their own circuits, thereby
reducing dependence on an external automated test equipment
(ATE).
BIST is a Design-for-Testability (DFT) technique, because it makes
the electrical testing of a chip easier, faster, more efficient, and less
costly. The concept of BIST is applicable to just about any kind of
circuit, so its implementation can vary as widely as the product
diversity that it caters to. As an example, a common BIST approach
for DRAM's includes the incorporation onto the chip of additional
circuits for pattern generation, timing, mode selection, and go-/no-go
diagnostic tests.
The main drivers for the widespread development of BIST
techniques are the fast-rising costs of ATE testing and the growing
complexity of integrated circuits. It is now common to see complex
devices that have functionally diverse blocks built on different
technologies inside them. Such complex devices require high-end
mixed-signal testers that possess special digital and analog testing
capabilities. BIST can be used to perform these special tests with
additional on-chip test circuits, eliminating the need to acquire such
high-end testers.
BIST is also the solution to the testing of critical circuits that have no
direct connections to external pins, such as embedded memories
used internally by the devices. In the near future, even the most
advanced tester may no longer be adequate for the fastest chip, a
situation wherein self-testing may be the best solution for.
Advantages of implementing BIST include: 1) lower cost of test,
since the need for external electrical testing using an ATE will be
reduced, if not eliminated; 2) better fault coverage, since special test
structures can be incorporated onto the chips; 3) shorter test times if
the BIST can be designed to test more structures in parallel; 4)
easier customer support; and 5) capability to perform tests outside
the production electrical testing environment. The last advantage
mentioned can actually allow the consumers themselves to test the
chips prior to mounting or even after these are in the application
boards.
Disadvantages of implementing BIST include: 1) additional silicon
area and fabrication processing requirements for the BIST circuits;
2) reduced access times; 3) additional pin (and possibly bigger
package size) requirements, since the BIST circuitry need a way to
interface with the outside world to be effective; and 4) possible
issues with the correctness of BIST results, since the on-chip testing
hardware itself can fail.
Issues that need to be considered when implementing BIST are: 1)
faults to be covered by the BIST and how these will be tested for; 2)
how much chip area will be occupied by the BIST circuits; 3) external
supply and excitation requirements of the BIST; 4) test time and
effectiveness of the BIST; 5) flexibility and changeability of the BIST
(i.e., can the BIST be reprogrammed through an on-chip ROM?); 6)
how the BIST will impact the production electrical test processes that
are already in place.
BIST techniques are classified in a number of ways, but two
common classification of BIST are the Logic BIST (LBIST) and the
Memory BIST (MBIST). LBIST, which is designed for testing random
logic, typically employs a pseudo-random pattern generator (PRPG)
to generate input patterns that are applied to the device's internal
scan chain, and a multiple input signature register (MISR) for
obtaining the response of the device to these test input patterns. An
incorrect MISR output indicates a defect in the device.
MBIST, as its name implies, is used specifically for testing
memories. It typically consists of test circuits that apply, read, and
compare test patterns designed to expose defects in the memory
device. There now exists a variety of industry-standard MBIST
algorithms, such as the "March" algorithm, the checkerboard
algorithm, and the varied pattern background algorithm.
One may also encounter the acronym "ABIST", which stands for two
totally different BIST techniques: the Array BIST, which is a form of
MBIST used for embedded memories, and the Analog BIST, which is
a BIST approach for analog circuits.
BIST is fast becoming an alternative solution to the rising costs of
external electrical testing and increasing complexity of devices. This
approach will find greater deployment in a wider variety of
circumstances as more and better BIST techniques are developed.
This does not mean, however, that BIST will eventually replace
external electrical testing altogether. Still, BIST proponents are
optimistic that BIST will someday be the preferred mode of testing,
instead of being merely an alternative to external ATE testing as it is
today.