EECS 3100 Embedded Systems
Homework #4 Solutions
Questions
1. Suppose r0 = 0x8000, and the memory layout is as follows:
Address
0x8007
0x8006
0x8005
0x8004
0x8003
0x8002
0x8001
0x8000
Data
0x79
0xCD
0xA3
0xFD
0x0D
0xEB
0x2C
0x1A
a) What is the value of r1 after running LDR r1, [r0] if the system is little endian or big endian?
Solution: r1 = 0x0DEB2C1A for little endian, and 0x1A2CEB0D for big endian
b) Suppose the system is set as little endian. What are the values of r1 and r0 if the instructions are
executed separately?



LDR r1, [r0, #4]
LDR r1, [r0], #4
LDR r1, [r0, #4]!
Solution:



LDR r1, [r0, #4]
LDR r1, [r0], #4
LDR r1, [r0, #4]!
; r1 = 0x79CDA3FD, r0 = 0x8000
; r1 = 0x0DEB2C1A, r0 = 0x8004
; r1 = 0x79CDA3FD, r0 = 0x8004
2. Suppose r0 = 0x20000000 and r1 = 0x12345678. All bytes in memory are initialized to 0x00. Suppose
the following assembly program has been executed successfully. Draw a table to show the memory
values if the processor uses little endian.
STR r1, [r0], #4
STR r1, [r0, #4]!
STR r1, [r0, 4]
Solution:
STR r1, [r0], #4
STR r1, [r0, #4]!
STR r1, [r0, 4]
; save to 0x20000000, r0 updated to 0x20000004
; save to 0x20000008, r0 updated to 0x20000008
; save to 0x2000000C, r0 is not updated
Memory Address
0x2000,0013
Memory Content
0x2000,0012
0x2000,0011
0x2000,0010
0x2000,000F
0x2000,000E
0x2000,000D
0x2000,000C
0x2000,000B
0x2000,000A
0x2000,0009
0x2000,0008
0x2000,0007
0x2000,0006
0x2000,0005
0x2000,0004
0x2000,0003
0x2000,0002
0x2000,0001
0x2000,0000
0x12
0x34
0x56
0x78
0x12
0x34
0x56
0x78
0x12
0x34
0x56
0x78
3. What is the memory value of Question 2 if the processor uses big endian?
Solution:
Memory Address
0x2000,0013
0x2000,0012
0x2000,0011
0x2000,0010
0x2000,000F
0x2000,000E
0x2000,000D
0x2000,000C
0x2000,000B
0x2000,000A
0x2000,0009
0x2000,0008
0x2000,0007
0x2000,0006
0x2000,0005
0x2000,0004
0x2000,0003
0x2000,0002
0x2000,0001
0x2000,0000
Memory Content
0x78
0x56
0x34
0x12
0x78
0x56
0x34
0x12
0x78
0x56
0x34
0x12
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4. Complete the following arithmetic operations in two’s complement representation. What are the values
5.
of the carry flag and overflow flag? (Assume a six-bit system)
 -7 + (-29)
 31 + 11
 15 – 19
Solution: When adding or subtracting two binary numbers, the process does not know
whether they are signed or unsigned. Therefore, the processor sets up the overflow flag by
assuming the binary operands are signed, and at the same time sets up the carry flag by
assuming the binary operands are unsigned.
 (-7) + (-29) = 111001 + 100011 = 011100
Carry = 1, Overflow = 1
 31 + 11 = 011111 + 001011 = 101010
Carry = 0, Overflow = 1
 15 – 19 = 001111 – 010011 = 111100
Carry = 0 (i.e., Borrow = 1), Overflow = 0
6. What are the overflow and carry flags of the following operations? (Assume a four-bit system.)
Carry
Overflow
1101 + 1100
1101 - 1100
1100 + 1010
0100 - 0110
0100 + 0010
0100 + 0110
1100 - 0110
Solution:
1101 + 1100
1101 - 1100
Result
1001
0001
Carry
13 + 12, Carry = 1
No Borrow, Carry = 1
Overflow
(-3) + (-4) = -7, Overflow = 0
Overflow = 0
1100 + 1010
0100 - 0110
0110
1110
Carry = 1
Borrow occurred. Carry = 0
Overflow = 1
Overflow = 0
0100 + 0010
0100 + 0110
0110
1010
Carry = 0
Carry = 0
Overflow = 0
Overflow = 1
1100 - 0110
0110
No Borrow. Carry = 1
Overflow = 1
7. Suppose r0 = 0x0F0F0F0F and r1 = 0xFEDCBA98, find the result of the following operations. Note
that the below instructions are not part of a program. Each instruction runs independently, without
influencing each other.
(1)
(2)
(3)
(4)
EOR r3, r1, r0
ORR r3, r1, r0
AND r3, r1, r0
BIC r3, r1, r0
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(5) MVN r3, r1
(6) MVN r3, r0
(7) ADD r3, r1, r0
Solution: Note that the above codes are not a program. Each instruction runs independently,
without influencing each other.
(1) EOR r3, r1, r0
R3 = 0xF1D3B597
(2) ORR r3, r1, r0
R3 = 0xFFDFBF9F
(3) AND r3, r1, r0
R3 = 0x0E0C0A08
(4) BIC r3, r1, r0
R3 = 0xF0D0B090
(5) MVN r3, r1
R3 = 0x01234567
(6) MVN r3, r0
R3 = 0xF0F0F0F0
(7) ADD r3, r1, #0
R3 = 0xFEDCBA98
8. Suppose r0 = 0x56789ABC, find the result of the following operation. Note that the below instructions
are not part of a program. Each instruction runs independently, without influencing each other.
(1)
(2)
(3)
(4)
RBIT r1, r0
REV
r1, r0
REV16 r1, r0
REVSH r1, r0
Solution: Note that the above codes are not a program. Each instruction runs independently,
without influencing each other.
(1) RBIT r1, r0
R1 = 0x3D591E6A
(2) REV
r1, r0
R1 = 0xBC9A7856
(3) REV16 r1, r0
R1 = 0x7856BC9A
(4) REVSH r1, r0
R1 = 0xFFFFBC9A
9. Translate the following C statement into an assembly program, assuming 16-bit signed integers x, y
and z (i.e. signed short) are stored in 32-bit registers r0, r1, and r2, respectively.
𝑥 = 𝑥 ∗ 𝑦 + 𝑧 − 𝑥;
Solution:
; r0 = x, r1 = y, r2 = z
MLA r2, r0, r1, r2
;
r2 = r2 + r0 * r1,
z = x*y + z
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SUB r0, r2, r0
;
x = z - x
10. Translate the following C statement into an assembly program, assuming 16-bit unsigned integers x
and y (i.e. unsigned short) are stored in register r0 and r1, respectively.
𝑥 = 𝑥 % 𝑦;
Solution:
; r0 = x, r1 = y
UDIV r2, r0, r1
MLS r0, r1, r2, r0
; r2 = floor(r0/r1)
; r0 = r0 – r1*r2
11. Write an assembly program that calculates the value of the following given polynomial, assuming
signed integers x and y are stored in registers r0 and r1, respectively.
𝑦 = 3𝑥 3 − 7𝑥 2 + 10𝑥 − 11.
; r0 = x, r1 = y
ADD
r2, r0, r0, LSL #1
SMUL
r2, r2, r0
SMUL
r2, r2, r0
RSB
r3, r0, r0,LSL #3
SMUL
r3, r3, r0
SUB
r2, r2, r3
MOV
r3, #10
SMUL
r3, r0, r3
ADD
r2, r3, r2
SUB
r2, r2, #11
MOV
r0, r2
; r2 = x + 2x = 3x
; r2 = 3x^2
; r2 = 3x^3
; r3 = 7x
; r2 = 7x^2
; r2 = 3x^3 - 7x^2
; r3 = 10x
; r2 = 3x^3 - 7x^2 + 10x
; r2 = 3x^3 - 7x^2 + 10x – 11
12. Write an assembly program that calculates the remainder of the division between two unsigned
integers.
Solution:
; r0 = y, r1 = x, x = y % x
UDIV r2, r0, r1
MLS
r0, r1, r2, r0
13. Explain why Cortex-M4 processors do not provide any rotation left instructions. They only provide
ROR (rotate right) and RRX (rotate right extended).
Solution: Rotating left n bits can be implemented by rotating right 32-n bits.
14. Write an assembly program that reverses the byte order of a register without using the REV instruction.
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Solution:
; Input in r1
; Result in r0
LSR r0,r1,#24
AND r2,r1,#0xFF0000
ORR r0,r0,r2,LSR #8
AND r2,r1,#0xFF00
ORR r0,r0,r2,LSL #8
ORR r0,r0,r1,LSL #24
; MSB in r1[7:0]
; Next to MSB in r2[23:16]
; Next to MSB in r0[15:8]
; Next to LSB in r2[15:8]
; Next to LSB in r0[23:16]
; LSB in r0[31:24]
15. Write an assembly program that swaps the upper half-word and the lower half-word of a register.
Solution:
; Assume: Input stored in r0, output stored in r1
LSR r1, r0, #16
ORR r1, r1, r0, LSL #16
16. Implement the BFC (bit field clear) instruction by using other assembly instructions.
Solution: There are many options for this; below is one.
; consider the following BFC version
MOV R7,#0xFFFFFFFF
BFC R7,#5,#11
;equivalent instruction sequence
MOV R0,#0xFFFFFFFF
MOV R1,#0xFFFFFFFF
LSR R3,R0,#27
LSL R4,R1,#16
ORR R5,R4,R3
MOV R6,#0xFFFFFFFF
AND R6,R6,R5
17. Suppose Mask = 0x00000F0F and P = 0xABCDABCD. What are the results of the following bitwise
operations? Consider each one separately and independently operating on its operands.
(1)
(2)
(3)
(4)
(5)
Q = P & Mask;
Q = P | Mask;
Q = P ^ Mask;
Q = ~Mask;
Q = P & ~Mask;
Solution:
(1) Q = P & Mask;
Q = 0x00000B0D
(2) Q = P | Mask;
Q = 0xABCDAFCF
(3) Q = P ^ Mask;
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Q = 0xABCDA4C2
(4) Q = ~Mask;
Q = 0xFFFFF0F0
(5) Q = P & ~Mask;
Q = 0xABCDA0C0
18. Suppose r0 = 0xFFFFFFFF, r1 = 0x00000001, r2 = 0x00000000 Initially N, Z, C, V flags are zero. Find
the value of the N, Z, C, V flags of the following instructions. (Assume each instruction runs
individually, i.e. these instructions are not part of a program.) Do NOT use the debugger as you are
expected to reason and conclude values for the flags.
(1)
(2)
(3)
(4)
(5)
(6)
ADD r3, r0, r2
SUBS r3, r0, r0
ADDS r3, r0, r2
LSL r3, r0, #1
LSRS r3, r1, #1
ANDS r3, r0, r2
Solution:
Keil/uVision simulator sets the NZCV=0000 to TM4C123GH6PM MCU after reset/startup.
The actual MCU on Tiva board also sets its NZCV flags to all zeros following startup/reset.
(1) r3=0xFFFFFFFF,
(2) r3=0x00000000,
(3) r3=0xFFFFFFFF,
(4) r3=0xFFFFFFFE,
(5) r3=0x00000000,
(6) r3=0x00000000,
NZCV = 0000 (add instruction does not affect flags)
NZCV = 0110 (result is zero and no borrow)
NZCV = 1000 (result is negative)
NZCV = 0000 (flags not affected)
NZCV = 0110 (carry gets bit 0 value & result zero)
NZCV = 0100 (result is zero)
19. Suppose we have a hypothetical processor, of which each register has only five bits. r0 = 0b11101 and
r1 = 0b10110. What are the N, Z, C, V flags of the following instructions? Assume initially N = 0, Z
= 0, C = 1, V = 0, and these instructions are executed independently (i.e. they are NOT part of a
program). Do NOT use the debugger!
(1)
(2)
(3)
(4)
ADDS r3, r0, r1
SUBS r3, r0, r1
EOR r3, r0, r1
ANDS r3, r1, r1, LSL #3
Solution:
r0 = 0b11101
r1 = 0b10110
(-3)
(-10)
(1) ADDS r3, r0, r1
r3 = 10011 (-13), NZCV = 1010
(2) SUBS r3, r0, r1
r3 = 00111 (7), NZCV = 0010
(3) EOR
r3, r0, r1
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r3 = 01011, NZCV = 0010
(4) ANDS r3, r1, r1, LSL #3
r3 = 10000 (-13), NZCV = 1010
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