Mixed Placer Flow – Concurrent
Placement of Macros and Standard Cells
Product Version: Innovus 20.1
June 2020
Copyright Statement
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registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
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Mixed Placer Flow
Contents
What’s new in 20.1............................................................................................................ 5
Purpose ............................................................................................................................. 6
Overview............................................................................................................................ 6
Licenses............................................................................................................................. 6
Flows.................................................................................................................................. 7
Main Flow....................................................................................................................... 7
Incremental flow ............................................................................................................ 8
ECO flow ........................................................................................................................ 9
Cadence Placement Guidance (CPG) flow ............................................................... 10
Concurrent I/O Mixed Placement Flow ...................................................................... 12
Physical Cell and Power Routing ................................................................................... 13
Physical cell modeling................................................................................................. 13
Power routing density modeling ................................................................................. 13
Physical cells insertion and power routing ................................................................. 14
Design styles support and limitations............................................................................. 15
Best design configuration............................................................................................ 15
Limitations .................................................................................................................... 15
Interface Commands Reference .................................................................................... 17
place_design -concurrent_macros ............................................................................. 17
setPlaceMode –place_opt_run_global_place {none seed full} ................................. 17
place_design –concurrent_macros -incremental....................................................... 18
refine_macro_place..................................................................................................... 18
set_macro_place_constraint, reset_macro_place_constraint,
write_macro_place_constraint, check_macro_place_constraint .............................. 19
Mixed Place Constraints ................................................................................................. 20
Macro array placement constraint .............................................................................. 20
Group constraints ........................................................................................................ 21
Spacing constraints ..................................................................................................... 22
Macro orientation constraint ....................................................................................... 24
Macro maximum stacking length ................................................................................ 24
Fixed macro location ................................................................................................... 25
I/O pin keep-out ........................................................................................................... 25
Macro placement halo................................................................................................. 26
Mixed place constraints support list ........................................................................... 27
Sample Tcl Script in Innovus 20.1.................................................................................. 28
Q&A ................................................................................................................................. 33
What is the benefit of mixed place flow?.................................................................... 33
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Mixed Placer Flow
Is MSV design supported?.......................................................................................... 33
Is ILM design supported?............................................................................................ 33
Is early clock flow supported? .................................................................................... 34
How to save intermediate DB for debugging ............................................................. 34
Too many detour paths in macro channels................................................................ 34
What happens if I restart the flow with all macros fixed? .......................................... 35
Support ............................................................................................................................ 35
Feedback ......................................................................................................................... 35
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Mixed Placer Flow
What’s new in 20.1
•
Concurrent I/O Mixed Placement Flow (page 12)
•
Macro spacing constraint (page 23)
It is now possible to specify different values for vertical and horizontal directions.
• ILM design limitation removed (page 30)
• Better congestion handling
Mixed-placer can now handle congested design. You can turn on high effort congestion
mode using setPlaceMode -place_global_cong_effort high.
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Mixed Placer Flow
Purpose
This application note is for users who want to run mixed placement flow. It will describe
details of the flow, recommended usage, new commands and options used, how to tune
the flow for good QoR, and answers to common questions.
Overview
In the traditional digital backend implementation flow, creating floorplan is a single stage
and the main target is to place the macros that can get a routable floorplan with
minimized wire-length and good timing. It always takes design engineers much effort to
achieve these tasks and many design iterations are needed, which is like a trial-anderror approach. Especially in advanced technology nodes, a good floorplan is more
important and critical to ensure the QoR convergence. In the mixed placement
implementation flow, the macros and standard cells are placed concurrently by a
powerful engine, which is driven by congestion, wire-length, and timing. It can reduce a
lot of manual work and effort to achieve faster TAT with comparable or better QoR than
the traditional flow.
The flow chart: Floorplanning stage is integrated to the placement stage, while the
other stages are same as the traditional flow.
Licenses
Using Innovus 18.1, the Innovus_GigaPlace_XL_Opt license is needed. Your script
must contain the following specific setting in addition to the license:
setLimitedAccessFeature invsMacroPlace 1
Since Innovus 19.1, the limited access control is removed.
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Mixed Placer Flow
Flows
In this section, the following will be covered:
•
•
•
The main flow of mixed placement
How to tune the design by using the incremental flow
ECO flow for the new version netlist
Main Flow
The flow can start with or without a reference floorplan. The advantage of starting with a
reference floorplan is that you can extract the power routing density file even before
running the mixed placement flow for the first time. This file is used to generate a better
congestion and wire-length modeling while placing the macros. Starting without the
reference floorplan in the first run will be needed to generate the power routing. This
first run can also be used to start analyzing the QoR and refining the constraints setting.
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Mixed Placer Flow
For large and complex designs containing hundreds of macros, the mixed placement
flow cannot guarantee the perfect floorplan in one pass. Sometimes, a few iterations are
needed.
How to judge if the mixed placement result is good or not
A first analysis can be done at the end of place_opt_design. If timing or congestion
is bad and it confirms that the root cause is a non-optimal macro placement, the
recommendation is to refine the constraints (set_macro_place_constraints,
setPlaceMode, setRouteMode, etc.) and restart the flow. If only a few macros must
be refined, an incremental flow can be used.
Incremental flow
If the result from the place_opt_design step is good, but you think that it can be
improved by tuning the placement by significant moves (movement of at least the size
of the macro) of a few macros, you can use the “incremental flow”. Starting from the
mixed place DB, do the following:
•
•
•
“Unfix” the macros you want to move.
Update the constraints (set_macro_place_constraint, setPlaceMode…).
Call place_design -concurrent_macros -incremental.
This incremental flow can be called several times if needed. Manual placement tuning
can help for some corner cases. After macro placement tuning, you can go back to the
“physical cell insertion and power routing” stage of the main flow as described in the
following flowchart:
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Mixed Placer Flow
ECO flow
The ECO flow can be used for an updated Verilog netlist with a few modifications. The
idea is to keep the floorplan elaborated using the previous netlist so that you do not
need to redo the macro placement and the power routing. The DB containing the
previous floorplan is coming from the intermediate DB saved during place_opt_design.
If the netlist size between the two netlists increases, the increase must be less than 3%.
Depending of the impact of this new netlist on the critical timing paths, the “place_opt_run_global_place” variable must be set differently:
•
With “none” if critical timing paths have not been modified. In that case, the new
standard cells will be placed directly during ecoPlace.
•
With “seed” if critical timing paths have been modified. In that case, the new
standard cells will be placed incrementally by place_opt_design.
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Mixed Placer Flow
If the new netlist size is increased by more than 3% or impacts a lot of critical paths, the
recommendation is to rerun the full mixed placement flow or run the CPG flow.
Cadence Placement Guidance (CPG) flow
Generally, the more the netlist changes, the more different the mixed placement result
can be. For a netlist change less than 3%, the ECO flow that does not touch the
floorplan is a good approach to consider (see the previous section). For a netlist change
with more than 3%, if you want to get a similar floorplan as with the previous netlist, the
CPG flow is a potential solution. The idea of this flow is to keep the macro placement of
the previous floorplan (through a guide file) as much as possible but let the tool move
the macros, if necessary, to solve any new congestion or timing issue. A typical usage
of the CPG flow is to support the insertion of DFT modules inside the netlist, assuming
the DFT has been elaborated considering the macro placement of the pre-DFT
floorplan. If the netlist change is due to new critical modules or functions, the CPG flow
is not recommended. A new mixed placement flow from scratch is expected to provide
better results.
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Mixed Placer Flow
To run the CPG flow, you need to dump a guide file from the old-version DB and read it
during the mixed placement flow on the new-version netlist. Take the pre-DFT and postDFT netlists, for example, you have already run mixed placement flow on the pre-DFT
netlist and push the QoR to be converged. When receiving the post-DFT netlist, you can
run the CPG flow as follows:
Innovus session 1
1. Restore the placement DB for pre-DFT.
2. write_macro_place_constraint -sections {cpg} -cpg_scope
{macro_only} -out_file macroLocs.tcl
# This command will write out CPG guide file from DB with Tcl format:
set_macro_place_constraint -cpg {<instName> <x> <y>
orientation}
Innovus session 2
3. Restore the initial DB for post-DFT.
4. setPlaceMode -place_global_cpg_file macroLocs.tcl
# Specify the CPG guide file and CPG flow will be turned on for mixed-placer
5. place_design -concurrent_macros
The other settings are same as the default mixed placement flow. Note that
refine_macro_place does not honor the CPG guide. It is recommended to keep the
same setting of macro placement constraints as the old version DB when running the
CPG flow (see the following flowchart).
In innovus 19.1, the CPG flow has been enhanced with an “effort” option:
setPlaceMode -place_global_cpg_effort {low|medium|high}”
Default is low.
The higher the level, the more the placement will increase the force to push instances to
the guided locations (macro placement of the previous floorplan). But a high effort also
means less flexibility for the tool and so, a potential degradation of the QoR and the
wireLength as compared to low effort. That’s why the low effort is the default.
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Mixed Placer Flow
Concurrent I/O Mixed Placement Flow
In innovus 20.10, the mixed placement implementation flow has been enhanced to
place I/O pins to optimize their locations and reduce the wire length and the congestion.
You can use the createPinGroup and createPinGuide commands to guide mixedplacer where to put IO pins.
It is a beta feature in 20.1. You need to contact Cadence AE for support.
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Mixed Placer Flow
Physical Cell and Power Routing
Physical cell modeling
In channels between macros, there are endcap cells and eventually, wellTap and
powerSwitch cells. In these macro channels, the impact of having these cells can be
significant. This is why it is important to model them while placing the macros. The
recommended modeling is to increase macro halos to “reserve some space” for these
physical cells before the placement and come back to a regular halo distance after the
placement. For example:
# Additional halo to model physical insts before placement:
addHaloToBlock -allBlock {2 2 2 2}
# Reset the macro halo to the regular size after place_design concurrent_macros:
addHaloToBlock -allBlock {1 1 1 1}
Power routing density modeling
In Innovus 19.1 and newer builds, the power density modeling is
generated automatically from a reference floorplan by the following
command:
“create_pg_model_for_macro_place -pg_resource_model
-file golden_mimic_power_mesh.tcl”
The information is saved into a Tcl file, “golden_mimic_power_mesh.tcl”, which is
read later in the flow by the “source golden_mimic_power_mesh.tcl” command.
This file contains only one value per layer, modelling the power density both over the
standard cells area and macros. It means mixed placer will remove the available routing
tracks by the ratio for each layer. Because the number and the type of macros are
different for each design, this power density modelling is design dependent.
In case of “no reference floorplan”, the recommended flow is to run the mixed
placement the first time without this power modeling file, apply your power stripes script
and then, generate the power modelling file. Before restarting the flow, the
recommendation is to check the QoR of this first run and update your constraints as
necessary, like the spacing constraint between macros.
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Mixed Placer Flow
Physical cells insertion and power routing
When all macros are placed in legal locations (after
refine_macro_place) and fixed in the floorplan, it is time to
insert physical cells and create power stripes. These scripts are
usually provided by the customer. If you do not have them, refer
to the documentation and look for commands like addEndCap,
addWellTap, addPowerSwitch, addStripes,
editPowerVia, etc.
Example:
The following command adds stripes in the vertical direction for the vdd and gnd nets:
addStripe -direction vertical -nets {vdd gnd} -width 10 -spacing
1 -layer METAL6 -start_offset 50 -set_to_set_distance 50
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Mixed Placer Flow
Design styles support and limitations
About the main design styles:
•
•
•
•
Flatten design: Yes. It is fully supported from 17.13.
Hierarchical design with partitions defined: No. It is not ready in 20.1.
MSV (Multiple Supply Voltage) designs with fences defined: Yes (see the “Is
MSV design supported?” section for details).
ILM designs: Yes (see the “Is ILM design supported?” section for details).
There can be many other design styles depending on parameters like the boundary
shape, the macros shape and size, the density, the number of layers, and others.
Following are the best design configuration supported and some limitations.
Best design configuration
•
•
•
•
•
Design with a rectangle boundary
No large macros (see the definition in the following section)
Macros with almost uniform sizes
Macro density (macro area / design area) < 60%
Enough routing resource over macros (at least two routing layers for H and
V)
Examples: GPU, networking, smart phone, AI chips
Limitations
1. Macro density
The QoR may be degraded when the density becomes larger than 60%. In this
case, some iterations may be necessary to improve it. When macro density is
more than 80%, it is quite complicated to get a good QoR. When running the
mixed placement flow, macro density is printed in the log file for information.
Example: Average macro density = 0.25 (means a macro density of 25%)
2. Large macros (definition)
a. The area of the macro is larger than 20% of the total design area.
b. The width or the height of the macro is longer than 50% of the design’s
width or height.
Large macros have a significant impact on the floorplan feasibility. If the design
has a few large macros, it is recommended to preplace the large macros
manually.
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Mixed Placer Flow
3. Limited routing resources over macros
This flow may place the macros in the middle of the design like standard cells to
get an optimal QoR. With this placement, the wire length is optimized as much as
possible and is usually much better compared to the placement with macro
placement close to the design boundary. To handle long nets more easily, which
could cross partially, the design would need to have nets routed over the macros.
It is preferred to have at least two free routing layers per direction over the
macros. If two free routing layers are not available, you need to push the macros
to the design boundary after completing the mixed placement flow.
4. Design rectilinear shapes
It can support different shapes of designs such as rectangle and simple L shape,
without long 90 degrees outside corner edges, etc. But it is difficult to support a
complex shape of the design with more than six inner corners, for example, a U
shape design with very long 90 degrees outside corner edges, where QoR may
not be optimal.
5. Macro rectilinear shapes
Rectilinear macros are not fully supported. It is recommended to preplace them if
there are only a few such macros.
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Mixed Placer Flow
Interface Commands Reference
place_design -concurrent_macros
There is a new option, -concurrent_macros, created for the place_design
command. When this option is enabled, place_design will do concurrent timingdriven placement of macros and standard cells.
Note: The standard cell placement is not completely finished after place_design concurrent_macros. Standard cells are overlapped and not in legal positions. In a
few cases, you can see standard cells placed outside of the core area. However, it is
not an issue. The next command, place_opt_design, will complete the standard cell
placement and preCTS optimization in the later stages. Example:
source init.enc
setLimitedAccessFeature invsMacroPlace 1 (needed before Innovus 19.1)
set_macro_place_constraint …
place_design –concurrent_macros
(mixed placement)
setPlaceMode –place_opt_run_global_place {none seed full}
The new option, setPlaceMode –place_opt_run_global_place {none seed
full}, is used to change the Global Placement behavior inside place_opt_design.
The default value is full. place_opt_design will run full Global Placement and
preCTS optimization as the general flow. When this option value is set to seed,
place_opt_design will use the output of the concurrent placement or other sources
as seed placement and run incremental standard cell placement followed by full preCTS
optimization. When this option value is set to none, place_opt_design will skip the
place_design step and run only preCTS optimization.
Note: “place_design –concurrent_macros” will set the option value to “seed”
automatically.
Example to run seed placement:
# Start from the mixed placed DB.
# Set this option if there is a user plugin, with setPlaceMode -reset.
setPlaceMode -place_opt_run_global_place seed
place_opt_design
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Mixed Placer Flow
place_design –concurrent_macros -incremental
When the concurrent_macros and incremental options are used together,
place_design will run the mixed placement flow incrementally. This “incremental”
parameter works only when the design is already placed.
If the “incremental standard cell placement” result is congested or preCTS QoR is not
good, you can modify the macro constraints and run the incremental mixed placement
flow. Read the “Incremental Flow” section for more information on how to tune the
design.
Example:
place_design –concurrent_macros
saveDesign concurrentMacro.enc
…
place_opt_design
# QoR is not good, in another INNOVUS session
restoreDesign concurrentMacro.enc.dat top
# Modify macro constraints, etc.
place_design –concurrent_macros -incremental
refine_macro_place
Legalize macros to avoid macro-overlapping and honor macro placement constraints
with limited macro displacement. Command ‘refine_macro_place’ by default is called in
“place_design –concurrent_macros” after global placement. You can change the
mixed place constraint and then call the standalone refine_macro_place to honor it.
Example:
set_macro_place_constraint \
-forbidden_space_to_core 2 -min_space_to_core 5 \
–forbidden_space_to_macro 2 –min_space_to_macro 5
refine_macro_place
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Mixed Placer Flow
set_macro_place_constraint, reset_macro_place_constraint,
write_macro_place_constraint, check_macro_place_constraint
See Innovus 20.1 Text Command Reference.
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Mixed Placer Flow
Mixed Place Constraints
Macro array placement constraint
This constraint can be specified by set_macro_place_constraint.
Syntax:
set_macro_place_constraint
-array <array_name> {<array_element> [ <spacing> <array_element>] +}
[-place_order <horizontal|vertical>] [-valid_group_orientations
<orientation_list>]
[- common_hier <common_path>]
<array_element>
# Specify instance members information of a
row or column in format: <inst_name>:<orientation> [ <spacing>
<inst_name>:<orientation>] +
<inst_name>
# Specify an instance name. It can be specified in a
short-hand format variable.
-place_order
# specify the place order in horizontal or
vertical or column first. Default is horizontal.
-valid_group_orientations
# valid orientations for the whole group
-common_hier
# Specify common hierarchical path. It can be
combined with instance name with short-hand format
Example of setting the macro array constraint:
set_macro_place_constraint -array ram_array
{{ip1/dma/r0_irx:R0 4.66 ip1/dma/r1_irx:MY 8.0
ip1/dma/r2_irx:MY}
2.33
{ip1/dma/r3_irx:R0 4.66 ip1/dma/r_irx:MY}}
-valid_group_orientations {R0 MY}
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Mixed Placer Flow
Group constraints
The group constraints are used to:
•
Specify that some macros should be placed closer
•
Provide soft and hard constraints for macro groups
•
Provide align group for macros
How to define the group constraints:
o Guide/Region/Fence

These three constraints are same as the traditional flow. Fixed bounding
box is needed by user input.
o softGuide

The macros inside a group will be placed closely. No bounding box is
defined.
o align_group

Specify the macros to be an align group in which the macros should be
aligned.

The group elements should only be macros with the same size. The
alignment will be automatically done by the tool with soft constraint.
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Mixed Placer Flow
Examples:
createInstGroup pipe1 –softGuide
#doesn’t support box
addInstToInstGroup pipe1 {ip1/regbank1 ip1/dma/ramI2
ip1/alu/adderI3}
set_macro_place_constraint -align_group group1 {ip2/dma/ram2A
ip2/dma/ram2B}
Spacing constraints
Spacing constraints are used to specify the minimum spacing and forbidden spacing of
macro-to-macro and macro-to-core boundaries. You can specify a unified value for
vertical and horizontal spacing or different values.
Example 1:
set_macro_place_constraint -forbidden_space_to_core 2 min_space_to_core 5
refine_macro_place
Example 2:
set_macro_place_constraint -parallel_run_length 3 \
-forbidden_space_to_macro 2 –min_space_to_macro 5
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Mixed Placer Flow
refine_macro_place
Notes:
1. When the parallel run length of macros is larger than the specified parallel run
length value, macro-to-macro spacing checking will be enabled.
2. If the macros have face-to-face pins, the macros will not be abutted by default,
even when the space between macros is less than the forbidden space.
In 20.1, the spacing constraint has been enhanced to support different values for
vertical and horizontal directions.
Commands to use:
set_macro_place_constraint \
–forbidden_space_to_core {unified_value | horizontal_value
vertical_value}
–forbidden_space_to_macro {unified_value | horizontal_value
vertical_value}
–min_space_to_core
{unified_value | horizontal_value
vertical_value}
–min_space_to_macro
{unified_value | horizontal_value
vertical_value}
refine_macro_place
If only one value (unified value) is specified, both horizontal and vertical spacing use the
same value. If two values are specified, the first value is for horizontal spacing and the
second value is for vertical spacing.
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Mixed Placer Flow
Macro orientation constraint
This constraint is used to specify the legal orientations for macro instances. It is a local
restriction to refine the solution and is stricter than LEF symmetry definition.
Note: The constraint is instanced-based, not cell-based.
Example:
set_macro_place_constraint –insts {ip2/dma/ram2A ip2/dma/ram2B}
–orientation {R0 MX}
•
The specified orientations should be legal in LEF.
•
The specified macros can be placed as R0, MX.
Macro maximum stacking length
When long nets travel across the stacking macros, the optimizer cannot add buffers to
fix DRV or timing violation if there is no channel between them. This constraint is to
define the maximum stacking length for macros.
Example:
set_macro_place_constraint
–horizontal_stacking {max_macro_stack_length
min_space_between_macro_stack min_space_between_macro} parallel_run_length {PRL}
Note: Only when the macro spacing is less than the specified
“min_space_between_macro”, the macros will be counted in the stacking length
constraint. The value of “min_space_between_macro_stack” in the stacking length
constraint should be bigger than the option value of “min_space_between_macro”.
And parallel_run_length is mandatory for stacking condition checking. The tool
does not consider that the macros are stacked when PRL <=0, since there is no
channel-less problem.
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Mixed Placer Flow
Fixed macro location
If you want to fix the macro location and not allow placer to move it, the solution is to
preplace the instance and change the status to fixed.
Example:
placeInstance my/ip1/rom_512i2 102.33 2022.39 MY
setInstancePlacementStatus -name my/ip1/rom_512i2 –status fixed
I/O pin keep-out
This constraint is to prevent macros from being placed near I/O.
Example:
set_macro_place_constraint -max_io_pin_group_keep_out 20
•
The tool will add macro-only blockages to I/O pins and reserve keep-out space
for pin routing. It automatically coordinates the size of macro-only blockages
based on the pin density and the number for each group of IO pins.
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Mixed Placer Flow
Macro placement halo
This constraint can be used to keep the instance-based macro spacing and model
EndCap, WellTap, and PSW cell areas at the mixed placement stage.
Example:
addHaloToBlock {10.0 20.0 40.0 30.0} –cell {ram1 ram2} –ori R0
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Mixed Placer Flow
Mixed place constraints support list
placeDesign –
concurrent_macro refine_macro_place check_macro_place_constraint
1. Macro array placement constraint Yes
Yes
No
Yes
No
No
Yes
No
No
Yes
Yes
Check Region/Fence
3. Spacing Constraints
No (plan 20.2)
Yes
Yes
4. Orientation Constraint
5. Over Macro Pow er Routing
Modeling
Yes
No
Yes
Yes
No
No
6. Maximum Stacking Length
No
Yes
Yes
7. Fixed Location
Yes
Yes
No
8. IO Pin Keep Out
Yes
Yes
No
9. Macro Placement halo
Yes
Yes
Check overlap
align_group
2. Grouping softGuide
constraints
Guide/Region/Fence
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Mixed Placer Flow
Sample Tcl Script in Innovus 20.1
#############################################################################
### DATA PREPARATION
#load golden floorplan DB including power mesh
source testcase.tcl
# Create power mesh modeling file from golden FPlan:
# In case the power mesh is the same over the macros and the
stdcell areas, use the following command:
create_pg_model_for_macro_place -pg_resource_model -file
golden_mimic_power_mesh.tcl
# In case there are special stripes over macros (vs the stdcell
area), and ONLY IN THIS CASE,
# you can use the following command:
# create_pg_model_for_macro_place -pg_resource_model pg_model_over_macros -file golden_mimic_power_mesh.tcl
# Remove all floorplan objects
# remove routing blockages, placement blockages,
relative_floorplan constraints
# unplace placed instances, routing wires, boundary_constraints
# delete physical instances
cleanup_floorplan_for_macro_place -remove {route_blockage
place_blockage relative_floorplan insts_place wire
boundary_constraint physical_inst}
# if there are large size macros (>20% in total area) or
rectilinear macros keep them fixed when cleaning up floorplan
#cleanup_floorplan_for_macro_place -remove {route_blockage
place_blockage relative_floorplan insts_place wire
boundary_constraint physical_inst} -keep_fixed_insts <inst1
inst2 ...>
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Mixed Placer Flow
###########################################################################
### ADD CONSTRAINTS
#add IO buffers here if they are needed
## additional halo to model physical like endcaps cells. This
additional halo will be
## removed layer. Ex: here we define a halo of 2 instead of 1
because of the endcap width = 1um
addHaloToBlock -allBlock {2 2 2 2}
# Mixed Placer Constraints
# Recommendations:
#
- set the min_space_to_macro as the minimum width you need
for a channel between
#
macros to insert all the needed power stripes and power
cells
#
- set the forbidden_space_to_macro as half of the
min_space_to_macro
#
- set the min/forbidden_space_to_core similarly as the
min/forbidden_space_to_macros
#
- set the max_io_pin_group_keep_out distance considering
your biggest group of pins
set_macro_place_constraint -min_space_to_core 10 forbidden_space_to_core 5 -min_space_to_macro 10 forbidden_space_to_macro 5 -max_io_pin_group_keep_out 20
# General constraints
# set all pre-placed setting (placement, clock... routing) like
you use to do in regular flow
#set_db -place...
#set_db -opt...
#set_db route_early_global_...
#set_path_group_options ...
source pre_place.tcl ; # pre_place.tcl is supposed to contain
all your pre-placed settings
# source the power mesh modelling file that has been generated
previously by the command create_pg_model_for_macro_place
source golden_mimic_power_mesh.tcl
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Mixed Placer Flow
#############################################################################
### RUN MIXED PLACER
# by default refine_macro_place is called automatically after
the mixed placement in order
# to legalize the macro placement. Using the option no_refine_macro the command refine_macro_place
# is not called. This gives us the possibility to:
#
- see the "brut" mixed placer result (before legalization)
#
- Call in incremental Mixed Placement if needed (see
documentation for this)
#disable refine_macro_place in place_design for halo adjustment
place_design -concurrent_macros -no_refine_macro
saveDesign myDB_local/macroPlace.enc
#Optionally, run incremental concurrent macro placement (see
documentation)
#place_design -concurrent_macros -incremental
## re-set the macro halo to the original size after concurrent
mixed placement
addHaloToBlock -allBlock {1 1 1 1}
refine_macro_place
##optional post concurrent macro place process: snap macro pins
to track, colorize macro pin if no color, etc
#setFPlanMode -snapBlockGrid LayerTrack
#snapFPlan -macroPin
##current behavior: macros may be off finfet-manufacture-grid by
"snapFPlan -macroPin", it's a limitation
## change the macro status to fixed after refine_macro_place
dbSet [dbget top.insts.cell.baseClass block -p2].pstatus fixed
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Mixed Placer Flow
##############################################################################
### FLOORPLAN FINISHING
## add placement blockages to channel
setFinishFPlanMode -activeObj {macro macroHalo hardBlkg softBlkg
partialBlkg core iopad iocell fence} -direction xy
#add hard blockage into very small channels if any
finishFloorplan -fillPlaceBlockage hard [expr
[get_macro_place_constraint -min_space_to_macro] / 2.0]
#Optionally add following blockages in case of congestion:
#finishFloorplan -fillPlaceBlockage soft
9.7
; #
value a little bit less than min_space_to_macro
#finishFloorplan -fillPlaceBlockage partial 9.7 -density 30 ; #
value a little bit less than min_space_to_macro
#finishFloorplan -fillPlaceBlockage partial 15 -density 60
# add physical instances
source add_physical_inst.tcl
saveDesign myDB_local/macroPlace_noPowerMesh.dat
#reset the PG modeling constraint and do power routing
reset_macro_place_constraint -cell_obs -pg_resource_model
## unplace standard cells temporary for power routing
defOutBySection -compPlacement -noNets
myDB_local/temp_placement.def
# Add power stripes
unplaceAllInsts
editDelete
# check the placement density if there are too many placement
blockages added by finishFloorplan
checkFPlan -reportUtil
# start power routing
source PP.tcl ; # PP.tcl is supposed to be your script to
create all power stripes
## should colorize power mesh and macro pins
#colorizePowerMesh
defIn myDB_local/temp_placement.def
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Mixed Placer Flow
##############################################################################
### RUN PLACE_OPT_DESIGN
setPlaceMode -place_opt_run_global_place seed
#set post_place script, such as save init placement DB,
addTieHiLo ...
setPlaceMode -place_opt_post_place_tcl post_place.tcl
place_opt_design
saveDesign myDB_local/place.enc
##############################################################################
### CHECK POWER AND CONGESTION
report_power -outfile mp_prects_power.rpt
# Need to specify the power view if it has been defined,
example:
#report_power -view functional_hold_ffgnp125_cworst -outfile
mp_prects_power.rpt
#earlyGlobalRoute
reportCongestion -hotspot -includeBlockage
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Mixed Placer Flow
Q&A
What is the benefit of mixed place flow?
It can reduce manual work and reduce TAT for the project. It is difficult and very timeconsuming for designers to manually tune a floorplan with hundreds or thousands of
macros. Compared with user’s tuned floorplan, it always achieves ~5% wire-length gain,
even 37% wire-length gain in some cases. Wire-length minimization will reduce the chip
power consumption and routing congestion.
Is MSV design supported?
Yes. If the power domain fences are already defined, each macro will be placed
respectively in its power domain fence as expected. If the power domain fences are not
defined, the mixed placement flow can be used so it can help you define them. The
macro placement will give the first idea where each power domain should be placed
inside the floorplan. From this placement, you can then draw the power domain fences
manually. Refer to the “Floorplanning the design” section of the Innovus User Guide for
more information. Once the power domain fences are defined, you can rerun the mixed
placement to place each macro in their power domain fences.
The power switching cells are inserted in the flow simultaneously with physical cells and
power stripes. Isolation cells are placed by the incremental standard cell placement.
Do I need to put some macro-only blockage close to the boundaries
of two power domains that are communicating together?
By default, no. But this is a solution in case of congestion.
Is ILM design supported?
Yes. You need to preplace all ILM blocks into core area and flattenIlm as follows:
1. Preplace ILM blocks anywhere inside core area.
2. flattenIlm
3. place_design -concurrent_macros
4. unflattenIlm
5. refine_macro_place
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Mixed Placer Flow
Is early clock flow supported?
Yes. You must enable the earlyClock flow (using the regular setting) after
place_design -concurrent_macros.
How to save intermediate DB for debugging
By default, place_opt_design will run an incremental placement followed by the
optimization step. An intermediate DB can be saved by executing a Tcl script containing
a saveDesign between these two main steps as follows:
setPlaceMode -place_opt_post_place_tcl post_place.tcl
place_opt_design
and
saveDesign in post_place.tcl
Too many detour paths in macro channels
Possible reasons:
1. You have forgotten to add placement blockages to macro narrow channels after
“place_design -concurrent_macros”. Many instances may be pushed into
the channels at the later stages.
2. Too many hard or soft placement blockages are added to the macro channels,
which have many standard cells placed inside after “place_design concurrent_macros”.
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Mixed Placer Flow
3. The value of min_space_to_macro is too big, which makes large macro
movements during refine_macro_place, and more standard cells are pushed
into the channels, which is not expected.
What happens if I restart the flow with all macros fixed?
place_design -concurrent_macros will error out with the following message:
**ERROR: (IMPSP-455):
No placeable macro is found, please
check the floorplan and unplace the macros that need to be
placed by place_design -concurrent_macros
Support
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knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.
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