TSN28HPCPDPSRAM
TSMC 28nm High Performance Compact Mobile
Computing Plus
Dual Port SRAM Databook
Version 20120200 130a
May 2016
Copyright © 2015, Taiwan Semiconductor Manufacturing Company, Ltd. All Rights Reserved. No part of this
publication may be reproduced in whole or in part by any means without prior written consent.
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Taiwan Semiconductor Manufacturing Company Ltd. reserves the right to make changes in the contents of this
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Table of Contents
Revision History of Databook
6
About this Databook
7
1 Overview of Compiler Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Product Family, Naming Convention and Application . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 General Features of Compiler Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8
8
9
2 Compiler Profile
2.1 Naming Convention and IP Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Compiler Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Compiler Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 Compiler Range Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5 Logic Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.6 Hazard Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.7 Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.8 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.9 Characterization Corners & Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.10 Power Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.11 Metal Layer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.12 Poly Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.13 Scramble Diagram and Mapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.14 Power/Ground Connection Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Reference Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Release Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Quick Reference Table (QRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3 Compiler In-Output File Structure
3.1 Input file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Output file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
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4 Views of Compiler Design Kits
4.1 Design kit and associated tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Verilog model usage note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
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5 Compiler Installation and Execution
40
5.1 Memory Compiler Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2 Installation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 License Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.1 Evaluation license (Front-End kit and LEF only) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.2 Formal license (include Front-End & Back-End kits) . . . . . . . . . . . . . . . . . . . . . . . . 41
5.4 Memory Macro Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4.1 Batch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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6 References
6.1 Abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Quick Troubleshooting for MC2 License Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Other Related Problems and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures
2.1 Block diagram of Dual Port SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Internal Function Block Diagram of Dual Port SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Timing protocol of SRAM Read-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Timing protocol of SRAM Write-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Timing protocol of BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Timing protocol of Asynchronous Write Through (AWT) . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Timing protocol of the sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Timing protocol of the shut down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 N28HPCP SRAM Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 DPSRAM compiler scramble diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.1
Example file structure of generated kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
4.1
Example Verilog model header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables
1
Chapter Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
1.1
1.2
Product Family and Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8
2.1 Example of Instance Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Configuration Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Test Pin default settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Active Pins in Normal Function Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Dual Port Contention Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Active Pins in Sleep and Shut down Functional Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Active Pins in BIST mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Active Pin in Asynchronous Write Through mode (AWT) . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 SRAM hazard conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Timing Specification Symbols and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 Timing Specification for Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13 Timing Specification for Shut Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 PVT Corner and Input Slew of Single Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15 For word-depth=384, Mux = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16 For word-depth=128, Mux = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.17 Terms and Description (used in QRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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22
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4.1
Compiler design kit deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
6.1
Abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
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Revision History of Databook
Date
07/22/2015
05/18/2016
Document
Version
20120200 110a
20120200 130a
Description
first created
No update for Databook
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About this Databook
This databook describes both the overview and details of a TSMC memory compiler family. Profiles, features, options, directory structures, front-end and back-end design kits, user modes and user-specified configurable files will be
described.
Reader and User
The intention of this databook is to provide design engineers with information about TSMC memory IP products
and to help supporting engineers understand the perspective of this product family. Features, functionality, benefits,
options and usage for SOC silicon implementation are described.
How to use this Databook
This databook is organized into the following chapters. Users can refer to the chapter of interest.
Section
Chapter 1 Overview of Compiler
Family Product
Chapter 2 Compiler Profile
Chapter 3 Compiler IN-OUTPUT file
structure
Chapter 4 Views of Compiler Design
Kits
Chapter 5 Compiler Installation and
Execution
Chapter 6 References
Description
Introduction of the common key features of this compiler family
Specification and features of this particular compiler
Input and output files for the compiler execution
Design kit offerings
How to run memory compiler to generate macros
Useful information of compiler installation, general guideline and
license issue debugging
Table 1: Chapter Organization
Reference Documents
In addition to this databook, a PPA (Performance, Power and Area) overview of each compiler will be provided in the
delivery package. Additionally a release note is included where tech files used for compiler development and revision
history will be described. Please see Chapter 2 for details
Compiler Product Online Release
The latest revision of each TSMC SRAM compiler portfolio can be found on TSMC-Online under Design Portal. The
databook and release note are available for review as well. TSMC-9000 Compliance Status provides reference for the
TSMC-9000 validation results and the IP alert information. Risk level will be given in the pop-up window if there
is an IP problem identified. An email notice will be sent to users who have downloaded compilers whenever there is
revised release. Users must take action to update the compiler with the latest version, or mask tape-out could be put
on hold if an old version is used.
Technical Support
For technical support, please contact Field Technical Support (FTS) at a TSMC regional office near you. Contact
information can be checked out from the TSMC website.
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Chapter 1
Overview of Compiler Family
1.1
Introduction
TSMC Memory Compiler family provides a total system solution of embedded memory IP for short turn-around time
of design process and a fast reliable path to market for leading SOC companies. The family is developed with 28nm
High Performance Compact Mobile Computing Plus (HPCP) process and provides memory instances based on a
variety of parameters, aspect ratio and support views of corresponding EDA tools. The family includes 1PRF, 2PRF,
SPSRAM, UHDSPSRAM, DPSRAM, UHDDPSRAM, Via ROM, L1 Cache and L2 Cache. Each compiler will be
described in the following.
1.1.1
Product Family, Naming Convention and Application
Refer to Table 1.1 for product family and naming convention
Refer to Table 1.2 for application
Type
Compiler Name
Foundry
Name
1PRF
tsn28hpcp1prf
ts
2PRF
tsn28hpcp2prf
ts
SPSRAM
tsn28hpcpd127spsram
ts
UHDSPSRAM tsn28hpcpuhdspsram
ts
DPSRAM
tsn28hpcpdpsram
ts
UHDDPSRAM tsn28hpcpuhddpsram
ts
ROM
tsn28hpcprom
ts
L1 Cache
temn28hpcphssrammacros tem
L2 Cache
tsn28hpcpl2spsrammacros ts
Prefix of
Instance
5n
6n
1n
1n
dn
dn
3n
5n
1n
Bitcell
(um2 )
0.155
0.24
0.127
0.127
0.315
0.127
0.044
0.155
0.127
Description
One Port Register File
Two Port Register File
High Density Single Port SRAM
Ultra High Density Single Port SRAM
Dual Port SRAM
Ultra High Density Dual Port SRAM
ROM
L1 Cache
L2 Cache
Table 1.1: Product Family and Naming Convention
Type
1PRF
2PRF
SPSRAM
UHDSPSRAM
DPSRAM
UHDDPSRAM
ROM
L1 Cache
L2 Cache
Featuring
One port read/write function with highest speed
One port read and one port write function
One port read/write function with wider supporting range
One port read/write function with highest area utilization
Dual port read/write function
Dual port read/write operation with ultra high density area utilization
Non-volatile read only memory
Macros customized for L1 cache applications
Macros customized for L2 cache applications
Table 1.2: Application
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1.1.2
General Features of Compiler Family
ˆ Pins and metal layer
– Support power pin with top metal M4 option
– Allow M4 channel routing through M4 power mesh
– All input and output pins on one side of macro
ˆ Compilation option :
– Bit line segment selection for performance and area optimization
– MUX selection for the desired macro aspect ratio
– Bit-write mask function (BWEB pin) that allows write to designated bits in a word
– Input MUX interface for BIST function
– Asynchronous write through (AWT) function
– Row repair
ˆ Power management :
– Sleep mode for greater leakage reduction with data retention
– Shut down mode to achieve highest leakage reduction without data retention
– Long channel devices for leakage reduction
ˆ General :
– Synchronous read and write operations with clock rising edge except AWT function
– Frequently used EDA models support
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Chapter 2
Compiler Profile
TSMC 28nm High Performance Compact Mobile Computing Plus Synchronous Dual Port SRAM compiler operates
within a voltage range from 0.81V to 0.99V and a junction temperature range from -40C to 125C. The available
supported macro size is configured from 32 bits to 72K bits. The compiled Dual Port SRAM is divided into 4 groups
according to their column-selected numbers (Mux=4,8,16).
2.1
Naming Convention and IP Tag
Compiler name tsn28hpcpdpsram 20120200 contains technology and compiler type, followed by the tiling tool MC2
version. Instance naming follows below format which indicates the selected features of the generated macro:
tsdn28hpcp{VT}a{W}x{N}m{CM}{SEG}{BWEB}{BIST}{AWT}{SLP}{SD}{BIST SIMPLIFIED} {Version}
Refer to Table 2.1 for example of instance naming.
Naming
W
N
CM
SEG
BWEB
BIST
AWT
SLP
SD
tsdn28hpcpa1984x7m16fwso 130a
tsdn28hpcpa1984x7m16fwbso 130a
tsdn28hpcpa1984x7m16fwsoay 130a
1984
1984
1984
7
7
7
16
16
16
f
f
f
w
w
w
b
-
a
s
s
s
o
o
o
BIST
Simplified
y
Version
130a
130a
130a
Note1 : For tsdn28hpcpa : ”a” stands for cell type
Note2 : Sleep mode option must be selected if shut down mode option is to be selected
Note3 : BWEB option must be selected if AWT option is to be selected
Table 2.1: Example of Instance Naming
IP tag is important for TSMC to identify IP name and version for wafer volume monitoring, silicon debugging and IP
quality system detection. Customer shall NOT remove the tag during tapeout. The tag is drawn on layers OD/NW
and 63;63. The tag string starts with ”&” for each of the major tags: vendor, product, version and instance tag.
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2.2
Compiler Features
TSMC 28nm High Performance Compact Mobile Computing Plus Dual Port SRAM compiler contains the following
features:
ˆ Pins and metal layer :
– 4 metal layers used
– Power mesh with M4 pins support
– Allow M4 channel routing through M4 power mesh
– All input and output pins on one side of macro
– This compiler is not compatible with 1P5M metal scheme at full chip level, users need to choose at least 6
layers metal scheme (eg. 1P6M 4X1Z) for chip T/O
ˆ Compilation option :
– Bit line segment selection for performance and area optimization
– MUX selection for the desired macro aspect ratio
– Bit-write mask function (BWEB pin) that allows write to designated bits in a word
– Input MUX interface for BIST function with a BIST Simplified option
ˆ Power management :
– Sleep mode for greater leakage reduction with data retention
– Shut down mode to achieve highest leakage reduction without data retention
– Long channel devices for leakage reduction
ˆ General :
– Synchronous read and write operations with clock rising edge
– Frequently used EDA models support
– High current with dual port 8T 0.315 um2 SRAM bit cell
– Synchronous read and write operations with clock rising edge except AWT function
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2.3
Compiler Options
Compiler provides below options which can be turned on or off during compilation based on user’s application:
ˆ Basic options ( always available for all combinations )
– Macro naming convention: user or default naming
– Bus type: bit blast mode or bus mode
– Ground name: ”GND” or ”VSS”
– Periphery Vt : SVT
ˆ Physical options
– BIST interface function
– Bit write (BWEB) function
– Sleep option
– Shut down option
– AWT (Asynchronous write through)
– BIST Simplified
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2.4
Specification
2.4.1
Block Diagram
Figure 2.1: Block diagram of Dual Port SRAM
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Figure 2.2: Internal Function Block Diagram of Dual Port SRAM
2.4.2
Function
The Dual Port SRAM is synchronized and triggered by a clock rising edges, CLKA/CLKB. Input address AA/AB,
input data DA/DB, chip enable CEBA/CEBB, and write enable WEBA/WEBB are latched by the rising edge of the
clock. The following sections explain major operation of the Dual Port SRAM.
Read Operation
The chip enable, CEBA/CEBB must be low and WEBA/WEBB stays high at CLKA/CLKB rising edge. Data is
read and then transmitted to output bus QA/QB[N-1:0] from memory location specified by AA/AB[M-1:0].
Write Operation
The chip-enable, CEBA/CEBB and write-enable, WEBA/WEBB must be low at CLKA/CLKB rising edge. Data
DA/DB[N-1:0] is written into memory location specified by address AA/AB[M-1:0]. The bit-write feature is controlled
by BWEBA/BWEBB[N-1:0].
Address Contention in General
Since CLKA and CLKB can be independent clocks whose edges may not be synchronized to each other, address
contentions between ports A and B can not always be resolved. Address contention occurs in this design when the
same address is latched with both rising edges of CLKA and CLKB during the following operations: write port A
and write port B, write port A and read port B, or read port A and write port B. Simultaneous reading of the same
address from ports A and B is allowed because this type of contention operation can always be resolved. If an address
contention occurs during write operations on both ports, indeterminate results can be written to the memory array.
If an address contention occurs during a write to one port and a read from the other port, indeterminate results can
be read from the array. The timing specification, tcc relates the minimum time required between CLKA and CLKB
in order for same address operations to successfully occur.
Address Contention with Read Operation Followed by Read Operation
Simultaneous reading of the same address from ports A and B is allowed because this type of contention operation
can always be resolved.
Address Contention with Write Operation Followed by Read Operation
If an address contention occurs during a write to one port and a read from the other port, indeterminate results can
be written to and read from the array. The specification tcc (measured from both clocks rising) is the minimum
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separation time required for a write to one port to complete before a successful read from the same address (from
the other port) can occur. This guarantees that the data is written to the array before the data is accessed for a
read operation from the other port. If specification tcc is violated during a write followed by a read operation, then
the read output is indeterminate and the memory content at that address is invalid. The write output data remains
unchanged.
Address Contention with Read Operation Followed by Write Operation
If an address contention occurs during a read from one port followed by a write to the other port, indeterminate
results can be read from and written to the array. The specification tcc (measured from both clocks rising) is also the
minimum separation time required for a read from one port successfully complete before a write to the same address
(from the other port) can occur. This guarantees that the data read from the array before the data is accessed for
a write operation to the other port. If specification tcc is violated during a read followed by a write operation, then
the write output is indeterminate and the memory content at that address is invalid. The write output data remains
unchanged.
Address Contention with Write Operation Followed by Write Operation
If an address contention occurs during write operations on both ports, indeterminate results can be written to the
memory array. The output of both ports remain unchanged.
Write/Write where tcc is violated would invalidate the memory contents at that address.
Write/Read where tcc is violated would invalidated the read output.
Read/Write where tcc is violated would invalidate the read output.
Read/Read is always safe regardless of clock separation.
Sleep Mode
The chip-enable, CEBA/CEBB and sleep mode, SLP must be high to enter the mode. It reduces standby leakage
power by switching off part of the periphery circuitry. There is up to 30% current reduction depending on macro size.
The data in the memory is retained during this mode.
Shut Down Mode
The chip-enable, CEBA/CEBB and sleep mode, SD must be high to enter the mode. It reduces standby leakage power
by switching off most of the periphery circuitry and SRAM bitcells. There is up to 90% reduction depending on macro
size. The data is not retained in the memory during this mode.
AWT Function
Asynchronous Write Through (AWT) is enabled by AWT pin. In AWT mode, the data output pin gives out a
value according to result from combination logic of DA,DB/DMA,DMB and BWEBA,BWEBB/BWEBMA,BWEBMB
input.
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2.4.3
Compiler Range Information
Dual Port SRAM memory macro can be configured by column mux option (CM), number of words (W), and number
of bits per word (N). The valid range of these parameters is specified in the Table 2.2
SEG option
F
M
Mux
4
8
16
4
8
16
Word Depth
32,48...1024
64,96...2048
128,192...4096
32,48...2048
64,96...4096
128,192...8192
Word Width ( I/O )
4,5..72
4,5...36
4,5...18
4,5...72
4,5...36
4,5...18
Note1 : Instances with F SEG and WL (W/CM) number of 68,132,196 are not supported
Note2 : Instances with M SEG and WL (W/CM) number of 132,260,388 are not supported
Table 2.2: Configuration Range
16 of 45
2.4.4
Pin Description
Refer to Table 2.3 for detail pin description.
Pin
VDD
VSS
AA[M-1:0]
DA[N-1:0]
BWEBA[N-1:0]
WEBA
CEBA
CLKA
AB[M-1:0]
DB[N-1:0]
BWEBB[N-1:0]
WEBB
CEBB
CLKB
AMA[M-1:0]
DMA[N-1:0]
BWEBMA[N-1:0]
WEBMA
CEBMA
AMB[M-1:0]
DMB[N-1:0]
BWEBMB[N-1:0]
WEBMB
CEBMB
RTSEL[1:0]
WTSEL[1:0]
VS
VG
AWT
BIST
CLKM
SLP
SD
QA[N-1:0]
QB[N-1:0]
Type
Power Supply
Power Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Description
Power bus
Power bus
Address on Port A
Data In on Port A
Bit Write Enable Bar on Port A (Active-Low)
Write Enable Bar on Port A (Write=0/Read=1)
Chip Enable Bar on Port A (Active-Low)
Clock on Port A
Address on Port B
Data In on Port B
Bit Write Enable Bar on Port B (Active-Low)
Write Enable Bar on Port B (Write=0)
Chip Enable Bar on Port B (Active-Low)
Clock on Port B
BIST Address on Port A
BIST Data In on Port A
BIST Data Bit Write Enable Bar on Port A (Active-Low)
BIST Read/Write on Port A (Write=0/Read=1)
BIST Chip Select on Port A (Active-Low)
BIST Address on Port B
BIST Data In on Port B
BIST Data Bit Write Enable Bar on Port B (Active-Low)
BIST Read/Write on Port B (Write=0/Read=1)
BIST Chip Select on Port B (Active-Low)
Timing adjustment setting for debug purpose
Timing adjustment setting for debug purpose
Timing adjustment setting for debug purpose
Timing adjustment setting for debug purpose
Asynchronous Write Through
BIST Interface Enable
BIST CLOCK M
Sleep mode (in VDDM domain with dual rail option)
Shut down mode (in VDDM domain with dual rail option)
Data Out on Port A
Data Out on Port B
Table 2.3: Pin description
Refer to Table 2.4. RTSEL[1:0], WTSEL[1:0], VS and VGsetting might be subject to change in future revision release
after silicon validation. The timing data is characterized with the default setting. Other setting combinations of logic
state would only be used for silicon debugging purpose only.
Mux
Mux4
Mux8
Mux16
RTSEL[1:0]
01
01
01
WTSEL[1:0]
01
01
01
VS
1
1
1
VG
1
1
1
Table 2.4: Test Pin default settings
17 of 45
2.4.5
Logic Truth Table
Function
SD
SLP
CLKA/
CLKB/
CLKM
Standby
Deselect
Read
Write bit[i]
Write bit[i] mask
L
L
L
L
L
L
L
L
L
L
L/H
^
^
^
^
CEBA/ WEBA/
CEBMA/ WEBMA/
CEBB/ WEBB/
CEBMB WEBMB
H
H
L
H
L
L
L
L
BWEBA/ AWT
BWEBMA/
BWEBB/
BWEBMB
L
L
L
L
L
bweb[i]=H
L
DA/
DMA/
DB/
DMB
d[i]
-
AA/
AMA/
AB/
AMB
a
a
Q[i]
Memory
contents
Hold*
Hold*
mem[a][i]
No change
No change
No change
No change
No change
mem[a][i]=d[i]
No change in
mem[a][i]
Note1 : Hold*, Q is unknown if AWT is unknown and follow AWT truth table
Table 2.5: Active Pins in Normal Function Mode
Port A
Read
Write[i]
Read
Write[i]
Port B
Read
Read
Write[i]
Write[i]
DA[i]
da[i]
da[i]
DB[i]
db[i]
db[i]
QA[i]
mem[a]
No change
X
No change
QB[i]
mem[b]
X
No change
No change
Memory Contents
No change
mem[a][i] is da[i]
mem[b][i] is db[i]
mem[a][i] is X
Note1 : A port read & B port read with the same address is always safe regardless of clock separation(tcc).
Note2 : A port write & B port read with the same address where tcc is violated would still write into the memory at that address but
the read output is indeterminate. If bweba[i] is high for A port write & B port read, then mem[a][i] is unchanged.
Note3 : A port read & B port write with the same address where tcc is violated would still write into the memory at that address but
the read output is indeterminate. If bwebb[i] is high for A port read & B port write, then mem[b][i] is unchanged.
Note4 : A port write & B port write with the same address where tcc is violated would invalidate the memory contents at that address.
If bweba[i] and bwebb[i] are high for A port write & B port write, then mem[a][i](same location as mem[b][i]) is unchanged.
Table 2.6: Dual Port Contention Table
Function
SD
SLP
CLKA/
CLKB/
CLKM
CEBA/
WEBA/
CEBMA/ WEBMA/
CEBB/
WEBB/
CEBMB WEBMB
BWEBA/
AWT
BWEBMA/
BWEBB/
BWEBMB
DA/
DMA/
DB/
DMB
AA/
AMA/
AB/
AMB
Q
Memory contents
Sleep
Sleep (enter)
Sleep (wake-up)
Shut down
Shut down (enter)
Shut down (wake-up)
L
L*
L*
H
H
-/Z
-/Z
-
-/Z
H
H
-/Z
H
H
-/Z
-/Z
-
-/Z
-/Z
-
-/Z
-/Z
-
L
X
X
L
X
X
No change
No change
No change
All X
All X
All X
^
_
-/Z
-/Z
-/Z
-
-/Z
-/Z
-
^
_
Note1 : In Shut Down mode, except SD pin, all other inputs are allowed to be floating
Note2 : In SLP mode, except SLP and SD pin, all others inputs are allowed to be floating
Note3 : L*, must be low duting wake up or enter SLP or SD
Table 2.7: Active Pins in Sleep and Shut down Functional Modes
Function
SLP
SD
AWT
Clock
Chip
select
Read/
Write
Normal (BIST=L)
SD
SLP
AWT
BIST (BIST=H)
SD
SLP
AWT
BIST Simplified
(BIST=H)
SD
SLP
AWT
CLKA/ CEBA/
CLKB
CEBB
CLKM CEBMA/
CEBMB
CLKM CEBA/
CEBB
WEBA/
WEBB
WEBMA/
WEBMB
WEBA/
WEBB
Bit
Write
Enable
BWEBA/
BWEBB
BWEBMA/
BWEBMB
BWEBA/
BWEBB
Address
Data
in
Data
out
AA/
AB
AMA/
AMB
AA/
AB
DA/
DB
DMA/
DMB
DA/
DB
QA/
QB
QA/
QB
QA/
QB
BWEBA/
BWEBB
BWEBMA/ Q
BWEBMB
bweb[i]
-
bwebm[i]
-
Table 2.8: Active Pins in BIST mode
AWT BIST
SD
SLP
H
H
-
L
L
L
H
L
L
H
-
L
H
-
CLKA/ CEBA/
CLKB/ CEBMA/
CLKM CEBB/
CEBMB
-
WEBA/
WEBMA/
WEBB/
WEBMB
-
DA/
DB
d[i]
-
DMA/ AA/
DMB
AMA/
AB/
AMB
dm[i]
-
bweb[i](xor)d[i]
bwebm[i](xor)dm[i]
L
L
Table 2.9: Active Pin in Asynchronous Write Through mode (AWT)
18 of 45
2.4.6
Hazard Conditions
Below table lists the pin combinations that do not exist in normal/repair function truth table may cause unknown
memory content or data output. Users should be aware of or avoid these combinations.
SD
BIST
SLP
AWT
CLKM
CLKA
CEBA/
CEBMA
WEBA/
WEBNA
AA/
AMA
BWEBA/
DA/
BWEBMA DMA
mem
Output QA
Output QB
X/Z
L
L
L
L
L
L
L
L
L
L
L
L
L
X/Z
L/H
L/H
H
L
L/H
L/H
L/H
L/H
L/H
L/H
L/H
L/H
X/Z
L
L
L
L
L
L
L
L
L
L
L
X/Z
L
L
L
L
L
L
L
L
L
L
X/Z
-
X/Z
X/Z
L
L
L
L
L
L
L
X/Z
H
L
H
L
L
L
X/Z
X/Z
L/H
L/H
L/H
L/H
X/Z
H
L
all X
all X
all X
Hold*
all X
all X
all X
all X
all X
all X
Hold
mem[aa][i]=x
Hold
mem[aa][i]=x
X
X
X
X
X
X
X
X
X
Hold
data-out
Hold
Hold
Hold
X
X
X
X
X
Hold
Hold
X
Hold
Hold
Hold
Hold
Hold
Hold
X/Z
X/Z
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
^
Note1 : Hold*, Memory content will be changed when doing write operation.
Note2 : Above hazard condition is for functional definition. Input pin high impedance might cause leakage.
Table 2.10: SRAM hazard conditions
19 of 45
Terms used in the above truth or hazard tables
Condition:
ˆ L : logic low
ˆ H : logic high
ˆ x : unknown ( could be 0 or could be 1 )
ˆ z : high impedance
ˆ - : L, H, x, not include z
ˆ ^: signal rising edge
ˆ _: signal falling edge
Output Q:
ˆ hold : keep previous state
ˆ x : unknown ( could be 0 or could be 1 )
ˆ L : logic low
ˆ data-out : output of normal read function
Mem:
ˆ mem[a] = x : memory content is unknown at the specific memory address A
ˆ mem[a][i] = x : memory content is unknown at the specific memory address A and specific IO
ˆ hold : keep the previous state
ˆ all x : store unknown to all memory contents
20 of 45
2.4.7
Timing Parameter
ˆ The maximum slew for each input signal is 0.567ns
ˆ All timing is measured from a logic threshold at 50% of the power supply
ˆ Slew rates are measured from 10% to 90% of the power supply
Parameter
tas
tah
tds
tdh
tbws
tbwh
tws
twh
tcs
tch
tams
tamh
tdms
tdmh
tbwms
tbwmh
twms
twmh
tcms
tcmh
tbists
tbisth
tckh
tckl
tcc
tcd*
thold*
tawtq
tawtqh
tbwebq
tbwebqh
tdq
tdqh
Difinition
Address Setup Before CLK^
Address Hold After CLK^
Data Setup Before CLK^
Data Hold After CLK^
BWEB Setup Before CLK^
BWEB Hold After CLK^
WEB Setup Before CLK^
WEB Hold After CLK^
CEB Setup BeforeCLK^
CEB Hold After CLK^
Address M Setup Before CLK^
Address M Hold After CLK^
Data M Setup Before CLK^
Data M Hold After CLK^
BWEBM M Setup Before CLK^
BWEBM M Hold After CLK^
WEBM Setup Before CLK^
WEBM Hold After CLK^
CEBM Setup Before CLK^
CEBM Hold After CLK^
BIST Setup Before CLK^
BIST Hold After CLK^
Minimum CLK Pulse High
Minimum CLK Pulse Low
Minimum CLK Separation W-R/R-W
CLK to Valid Q (data output)
CLK to Invalid Q (data output)
AWT to Valid Q
AWT to Invalid Q
BWEB to Valid Q
BWEB to Invalid Q
D to Valid Q
D to Invalid Q
From
AA[M-a:0], AB[M-1:0]
AA[M-a:0], AB[M-1:0]
DA[N-a:0], Db[N-1:0]
DA[N-a:0], Db[N-1:0]
BWEBA[N-1:0], BWEBB[N-1:0]
BWEBA[N-1:0], BWEBB[N-1:0]
WEBA, WEBB
WEBA, WEBB
CEBA, CEBB
CEBA, CEBB
AMA[M-1:0], AMB[M-1:0]
AMA[M-1:0], AMB[M-1:0]
DMA[N-1:0], DMB[N-1:0]
DMA[N-1:0], DMB[N-1:0]
BWEBMA[N-1:0], BWEBMB[N-1:0]
BWEBMA[N-1:0], BWEBMB[N-1:0]
WEBMA, WEBMB
WEBMA, WEBMB
CEBMA, CEBMB
CEBMA, CEBMB
BIST
BIST
CLKA^CLKB^CLKM^
CLKA_CLKB_CLKM_
CLKA^/CLKB^
CLKA^CLKB^CLKM^
CLKA^CLKB^CLKM^
AWT
AWT
BWEBA,BWEBB, BWEBMA,BWEBMB
BWEBA,BWEBB, BWEBMA,BWEBMB
DA,DB, DMA,DMB
DA,DB, DMA,DMB
To
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKA/CLKB
CLKM
CLKM
CLKM
CLKM
CLKM
CLKM
CLKM
CLKM
CLKM
CLKM
CLKA/CLKB, CLKM
CLKA/CLKB, CLKM
CLKA_CLKB_CLKM_
CLKA^CLKB^CLKM^
CLKB^/CLKA^
QA[N-1:0], QB[N-1:0]
QA[N-1:0], QB[N-1:0]
QA[N-1:0], QB[N-1:0]
QA[N-1:0], QB[N-1:0]
QA[N-1:0], QB[N-1:0]
QA[N-1:0], QB[N-1:0]
QA[N-1:0], QB[N-1:0]
QA[N-1:0], QB[N-1:0]
Table 2.11: Timing Specification Symbols and Definitions
Parameter Definition
tslpwk
Wake up time for switching back to normal
mode from SLP mode
txslp
Wake up setup time for all input pins to SLP
disable
tslp
Waiting time for entering sleep mode
tslpx
SLP enable to input pin unknown or high
impedance
tslpqh
Output data valid time after SLP enable
tslpq
Output data (low) delay time after SLP enable
tqh
Output data (low) valid time after SLP disable
tslpwk2clk Wake up time for the first valid cycle from SLP
mode
From
SLP
To
CEBA/CEBB/AWT
All other input pins
(except SD)
CEBA/CEBB
SLP
SLP
SLP
SLP
SLP
SLP
SLP
All other input pins
(except SD)
QA/QB
QA/QB
QA/QB
CLK
Table 2.12: Timing Specification for Sleep Mode
21 of 45
Parameter Definition
tsdwk
Wake up time for switching back to normal mode from SD
mode
txsd
Wake up setup time for all the input pins to SD disable
tsd
tsdx
tsdqh
tsdq
tqh
Waiting time for entering SD mode
SD enable to input pin unknown or high impedance
Output data valid time after SD enable
Output data (low) delay time after SD enable
Output data (low) valid time after SD disable
From
SD
To
CEBA/CEBB/AWT
All other input
pins
CEBA/CEBB
SD
SD
SD
SD
SD
SD
All other input pins
QA/QB
QA/QB
QA/QB
Table 2.13: Timing Specification for Shut Down Mode
22 of 45
2.4.8
Timing Waveform
Figure 2.3: Timing protocol of SRAM Read-only operation
23 of 45
Figure 2.4: Timing protocol of SRAM Write-only operation
Figure 2.5: Timing protocol of BIST
24 of 45
Figure 2.6: Timing protocol of Asynchronous Write Through (AWT)
25 of 45
Figure 2.7: Timing protocol of the sleep mode
Sleep Mode behavior :
ˆ SLP pin is an asynchronous control input pin.
ˆ SLP pin must be active high for entering sleep mode (1’b1 = power saving).
ˆ The chip enable signal must be disabled with asserting high prior entering sleep mode.
ˆ SRAM wake up time from sleep mode to normal stand-by mode (tslpwk) is required and must be sufficiently
guaranteed for instance to have healthy power supply.
ˆ The SRAM data output (Q) is logic low after SLP is activated (SLP = 1’b1) with certain waiting time, tslpq.
While SLP is still activated, data output (Q) remains logic low.
26 of 45
Figure 2.8: Timing protocol of the shut down mode
Shut Down Mode behavior:
ˆ SD pin is an asynchronous control input pin.
ˆ SD pin must be active high (1’b1 = power saving).
ˆ All input pins can be floating or unknown (X) during shut down mode (SD=1’b1).
ˆ After SD goes high (1’b1) , tsdx timing shall be met before input pins become floating or unknown (x) states.
Similarly, txsd timing shall be met before SD goes low (1’b0) to ensure input pins are valid(0/1).
ˆ The chip enable signal must be disabled with asserting high prior entering shut down mode.
ˆ SRAM wake up time from shut down mode to normal stand-by mode (tsdwk) is required and must be sufficiently
guaranteed for instance to have healthy power supply.
ˆ The SRAM data output (Q) is logic low after SD is activated (SD = 1’b1) with certain waiting time, tsdq. While
SD is still activated, data output (Q) remains logic low.
ˆ When the values of data output (Q) changes from logic low (shut down mode) to unknown-X (normal stand-by
mode), there is no high-Z on output Q.
27 of 45
2.4.9
Characterization Corners & Slew Rate Definition
All timing is measured from a logic threshold at 50% of the power supply. Slew rates are measured from 10% to 90%
of the power supply.
The timing data is based on 5 output load 0.002/0.019/0.042/0.132/0.358 (pf) and 5 input slew rates of timing arc
for each process corner as shown in the Table 2.14
SR 0.9V +/- 10%
Corner
Process
tt0p9v25c
tt0p9v85c
ssg0p81vm40c
ssg0p81v0c
ssg0p81v125c
ffg0p99vm40c
ffg0p99v0c
ffg0p99v125c
tt
tt
ssg
ssg
ssg
ffg
ffg
ffg
Voltage
(V)
0.9
0.9
0.81
0.81
0.81
0.99
0.99
0.99
Temperature (C)
Input slew (ns)
25
85
-40
0
125
-40
0
125
0.005/0.021/0.042/0.085/0.255
0.005/0.021/0.042/0.085/0.255
0.008/0.045/0.092/0.188/0.567
0.008/0.045/0.092/0.188/0.567
0.008/0.045/0.092/0.188/0.567
0.005/0.021/0.042/0.085/0.255
0.005/0.021/0.042/0.085/0.255
0.005/0.021/0.042/0.085/0.255
Voltage
(V)
1
1
0.9
0.9
0.9
1.05
1.05
1.05
Temperature (C)
Input slew (ns)
25
85
-40
0
125
-40
0
125
0.005/0.021/0.042/0.085/0.255
0.005/0.021/0.042/0.085/0.255
0.008/0.045/0.092/0.188/0.567
0.008/0.045/0.092/0.188/0.567
0.008/0.045/0.092/0.188/0.567
0.005/0.021/0.042/0.085/0.255
0.005/0.021/0.042/0.085/0.255
0.005/0.021/0.042/0.085/0.255
SR 1.0V +5% /- 10%
Corner
Process
tt1v25c
tt1v85c
ssg0p9vm40c
ssg0p9v0c
ssg0p9v125c
ffg1p05vm40c
ffg1p05v0c
ffg1p05v125c
tt
tt
ssg
ssg
ssg
ffg
ffg
ffg
Table 2.14: PVT Corner and Input Slew of Single Rail
Note1 : Permanent damage could occur if the operation exceeds the table listing above
28 of 45
2.4.10
Power Definition
DC and AC power number can be found in macro datasheet after compiling, definitions as following:
ˆ Read current: Clock read current which excludes leakage and pin power
ˆ Write current: Clock write current which excludes leakage and pin power
ˆ Deselect current: memory is disabled by CEB pin, and clock is toggling; all signals are in steady state
ˆ Static standby (leakage) current: memory is disabled by CEB pin, and clock is not toggling; all signals are in
steady state
ˆ Dynamic standby current: memory is disabled by CEB pin, and clock is toggling; address, data and bit-write
pins maintain 50% activity
ˆ Pin power: specific power for pin/bus contribution information, please refer to ”Dynamic Power break down per
pin” table in datasheet of sram macros
29 of 45
2.4.11
Metal Layer Usage
ˆ Power pins are brought up to top level as M4 pins for easy access
ˆ Except M4 pins and blockage, certain routing space is available in M4 layer
ˆ M4 is mainly for power routing and can be used for signal routing as well
ˆ M1, M2, M3 layers are blocked completely
ˆ Memory M4 direction is orthogonal to M2 direction
30 of 45
2.4.12
Poly Direction
All device gate direction must be aligned across chip. Physical verification of DRC will flag this rule if gate directions
are not aligned. Refer to Figure 2.9
Figure 2.9: N28HPCP SRAM Orientation
31 of 45
2.4.13
Scramble Diagram and Mapping Example
A general scramble diagram is shows as below for word line and bit line physical order. BL[x] and BLB[x] are bit-line
and the complement of bit line. WL[x] is the word line. Refer to Figure 2.10
Figure 2.10: DPSRAM compiler scramble diagram
Note
cm : the number of column-mux
m : the number of row
n : the number of word width(bits)
seg: the max number of row in a segment (F:64, M=128)
If n is equal to even number, all IO(bits) will be allocated evenly into left and right bank, namely each bank has the
same number of IO(bits), whereas, if n is equal to odd number, left bank always has one more IO(bit) than right bank.
32 of 45
Figure 2.4.13 and Table 2.16 are two examples that show how address pins decoded for word line (WL) and Bit lines
(BL, BLB).
Column Mux Decode (BL & BLB)
0
1
2
3
4
5
6
7
A[2:0]
000
001
010
011
100
101
110
111
Row Decode (WL)
WL[1]
WL[5]
A[8:3]
000,001
000,101
Table 2.15: For word-depth=384, Mux = 8
Column Mux Decode (BL & BLB)
0
1
2
3
A[1:0]
00
01
10
11
Row Decode (WL)
WL[0]
WL[7]
A[6:2]
00,000
00,111
Table 2.16: For word-depth=128, Mux = 4
33 of 45
2.4.14
Power/Ground Connection Guideline
In the chip design level, the users should meet the Vccmin specification (>=Vdd-10%) at the SRAM IP boundary to
avoid performance degradation due to voltage drop from system power. The guidelines to have better IR drop result
and EM management:
ˆ Connect Mn VDD/VSS power lines through M(n+1) and vias as many as possible.
ˆ All power and ground pins MUST be connected to VDD and VSS (GND), respectively.
ˆ Metal hookup of power supply shall be taken more care around memory IO buffer area where data input and
output pins are located.
Note: Mn = Top metal
34 of 45
2.5
Reference Document
2.5.1
Release Note
The major contents include revision history, design documents/version (DRM/DRC, LVS, RC tech file, spice model,
etc.), PVT conditions, special note and tapeout layer information.
2.5.2
Quick Reference Table (QRT)
Provides PPA (Performance, Power and Area) data from most frequently used sram configurations with all PVT
conditions. The feature options in the QRT are based on default option. Users can refer to this table to have sram
PPA data instantly for estimation.
Please refer to tsn28hpcpdpsram 20120200 130a Quick Reference Table.pdf for SRAM performance data reference.
Terminology used in QRT is described in the Table 2.17
Terms
type
word
io
mux
seg
drawing dimension area (um2 )
access time (ns)
read cycle time (ns)
write cycle time (ns)
read adr setup (ns)
write adr setup (ns)
read adr hold (ns)
write adr hold (ns)
data setup (ns)
data hold (ns)
readc (uA/MHz)
writec (uA/MHz)
leakage (uA)
leakage slp (uA)
leakage sd (uA)
periphery Vt
total Kbits
Description
Compiler type
Word depth
Word width (Bit number)
Column mux
Segment type (bit-line partition)
Macro size in GDS layout
Access time (CLK to output Q)
Read cycle time
Write cycle time
Read address setup time
Write address setup time
Read address hold time
Write address hold time
Data setup time
Data hold time
Read current, excludes pin power
Write current, excludes pin power
Static power
Static power in sleep mode
Static power in shut down mode
SVT or LVT or HVT
(word * io) / 1024
Table 2.17: Terms and Description (used in QRT)
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Chapter 3
Compiler In-Output File Structure
3.1
Input file
The following files under two categories will be seen after decompressing the received package
(example package name: tsn28hpcpdpsram 20120200 130a.tar.gz):
1. Compiler execution code/database and batch mode script:
ˆ tsn28hpcpdpsram 20120200 130a.mco
– The SRAM compiler database which is utilized to generate the macro design kits with MC2 software
engine
ˆ tsn28hpcpdpsram 130a.pl
– The script file to generate SRAM instance in batch mode
ˆ config.txt
– The user-defined configuration file used for macro generation in batch mode. More than one macro
configurations can be listed in this file with the pre-defined format
2. Compiler MC2 software and installation script:
ˆ MC2 2012.02.00.d.tar.gz
– The compiler software engine that generates all the macro design kits by extracting the information
from the database *.mco file
ˆ install.sh
– Decompress MC2 2012.02.00.d.tar.gz for license installation
Note : Download the memory compiler object code ”tsmc n28hpcpmc 20120200” from tsmc on-line to install compiler
license. An installation guide ”AN N28HPCP CompilerInstallation UserGuide {ver}” can be found in the memory
compiler object code tool package.
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3.2
Output file
Below is the illustration of file directory structure of design kits for the SRAM macro generated from the compiler.
The LOG folder contains a log file from the macro compilation. The other folders contain the design kits that are
further described in next chapter.
Figure 3.1: Example file structure of generated kits
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Chapter 4
Views of Compiler Design Kits
4.1
Design kit and associated tools
The compiler generates the default design kits as shown in the Table 4.1
Kit Name
Datasheet
GDSII
SPICE
LEF
NLDM
VERILOG
DFT/ATPG
DFT/MBIST
DFT/MBIST
Kit Description
Macro datasheet
GDSII layout view
Spice net-list
SOC Encounter (phantom) view
Non-linear delay model
Verilog model (*.v & pwr.v)
ATPG model
Logicvision model
MASIS model
Associated Tool
NA
Calibre/ Hercules
Calibre/ Hercules
Soc Encounter/ ICC
Design Compiler
NC-Verilog/ VCS
TetraMax/ Fastscan
LogicVision
SMS
Tool vendor
NA
Mentor/ Synopsys
Mentor/ Synopsys
Cadence/ Synopsys
Synopsys
Cadence/ Synopsys
Synopsys/ Mentor
Mentor
Synopsys
Table 4.1: Compiler design kit deliverables
4.2
Verilog model usage note
User must pay attention to following instructions in order to have correct simulation result :
1. The Verilog behavior model doesn’t support the signals transition right at the positive clock edge of the control
enable, data, and address pins. Therefore sufficient setup time is required for these pins before clock rising to
ensure the correct behavior.
2. The Verilog behavior model provides UNIT DELAY mode for the fast functional simulation. UNIT DELAY
mode does not check timing values but only function. Its functional behavior still follows the truth table in
Chapter2
3. In a non-fully decoded array, a write operation to a non-existent address location does not change the memory
array contents whereas the output value remains the same as previous cycle.
4. In a non-fully decoded array, a read operation to a non-existent address location does not change the memory
array contents but the output of the current cycle becomes unknown.
5. In the Verilog model, the unknown clock will corrupt the memory data and make output unknown regardless of
CEB signal. But in real circuit behavior, when the unknown clock occurs with CEB at high, the memory and
output data will be held. The Verilog model behavior is more conservative in this condition.
6. Floating input signal to memory macro is not allowed for normal function mode. Isolation cells are required for
input signals fed into memory if the power domain of input signals are turned off.
7. User must refer to the important usage limitation in Verilog model header for correct functional simulation as
shown in Figure 4.1 as an example.
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Figure 4.1: Example Verilog model header
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Chapter 5
Compiler Installation and Execution
5.1
Memory Compiler Package
Compiler name : tsn28hpcpdpsram 20120200 <ver>
Example package name : ”tsn28hpcpdpsram 20120200 <ver>.tar.gz”
The naming convention is described in chapter 1.
The package name that user receives from TSMC for above compiler will be ”tsn28hpcpdpsram 20120200 <ver>.tar.gz”.
The ”ver” indicates the compiler version.
The available files after decompressing the above package are described in detail in Chapter 3.
5.2
Installation Environment
TSMC memory compiler supports the following Operating System
ˆ 32-bit Linux [Processor : Intel/AMD]
– Recommended RedHat Enterprise Linux 4/5
ˆ 64-bit Linux [Processor : Intel/AMD 64]
– Recommended RedHat Enterprise Linux 5
ˆ 64-bit SunOS 5.9 [Processor : SPARC64]
ˆ 64-bit SunOS 5.10 [Processor : SPARC64]
ˆ 64-bit SunOS 5.10 [Processor : Intel/AMD 64]
5.3
License Key
The license is required to activate the memory compiler. One license file is only valid for a certain period of time and
for the SRAM compilers designated in the file. There are also evaluation and formal licenses which is described in
later section. The license is also limited to start up on the designated host.
User should provide your host ID information to your TSMC regional technical contact window in order to receive
the required license file. The example host ID format is: 83cdac13 (SunOS) / 00E04DA61443 (Linux)
An example of a license key is shown below:
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5.3.1
Evaluation license (Front-End kit and LEF only)
ˆ The license feature includes MC2-CLV, MC2-Main and the corresponding memory library features.
ˆ Only front-end kits and LEF can be generated.
5.3.2
Formal license (include Front-End & Back-End kits)
ˆ The license feature includes MC2-CLV, MC2-CPV, MC2-Main and corresponding library features.
ˆ TSMC provides one year valid period. All design kits can be generated. MC2-CPV features the GDSII and
SPICE netlist generation.
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5.4
Memory Macro Generation
TSMC compilers support both Batch mode while generating macros. Users can generate more than one instance at a
time by running in Batch mode.
Before running the compilers, users must source MC2 license and set environment variable
$MC HOME to *.mco file (compiler execution code) by the command as below:
% setenv MC HOME $compiler path (path for tsn28hpcp{sram type}.mco)
GUI mode is not supported in compiler, users can generate sram macros by GUI mode from ”CLOUD” compiler
system on tsmc on-line.
5.4.1
Batch mode
In Batch mode, user can specify multiple instance sizes and options for compiling. An example config file(config.txt)
can be found in the received package where detail of parameters and variables are described below.
ˆ Source compiler license and set environment variable $MC HOME to *.mco file
% source cshrc.mc2
ˆ Execute the following command in any working directory to generate instances
% tsn28hpcpdpsram <ver>.pl
Example :
Prepare config.txt file with tsmc naming convention as default
ˆ config.txt
ˆ The above configuration is just an example. Please refer to Table 2.2 for correct configuration setting.
ˆ default input file is config.txt, users can input user-define naming (ex: config macro.txt) then execute the
following command.
% tsn28hpcpdpsram <ver>.pl -file config macro.txt
ˆ available options can be specified for perl script ”tsn28hpcpdpsram <ver>.pl”
-h : help
-NonTsmcName : Do not use TSMC naming convention
(default is use TSMC naming convention)
-file <configfile>: To use the input file from user as configuration file (default is config.txt)
-GND : To use GND as ground name (default is VSS)
-sd <unit delay>: To set SRAM DELAY value (default value is 0.01)
-NonBus : To set input and output pins as bit-blasted type
-NonBWEB : To disable BWEB option
-NonBIST : To disable BIST option
-NonAWT : To disable AWT option
-NonSLP : To disable SLP option
-NonSD : To disable SD option
-BistSimplified : To enable BIST Simplified function
-DATASHEET : To generate DATASHEET kit only
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-VERILOG : To generate VERILOG kit only
-NLDM : To generate NLDM kit only
-LEF : To generate LEF kit only
-SPICE : To generate SPICE kit only
-GDSII : To generate GDSkit only
-DFT : To generate DFT kit only
-LISTPVT : To list all pvt corners
-PVT : To generate specific pvt corners
ex : % tsn28hpcpdpsram <ver>.pl -GND -NonBWEB -NonBus
User defined configuration file example :
ˆ 1st character of library name cannot be numerical (eg. not ”1abc123”)
ˆ config macro.txt
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Chapter 6
References
6.1
Abbreviation
Abbreviation
BIST/MBIST
Cu ELK
DRM/DRC
EM
GUI
IO
IP
LVS
MC2
MUX
OS
PVT
RC
SRAM
ROM
SOC
Description
Build In Self Test/ Memory BIST
Copper Extreme Low-K (dielectric)
Design Rule Manual/Design Rule Check
Electron Migration
Graphic User Interface
Input Output
Intellectual Property
Layout Versus Schematic
Memory Compiler 2 (compiler tool vendor)
Multiplexor
Operating System
Process, Voltage, Temperature
Resistance and Capacitance
Static Random Access Memory
Read Only Memory
System On Chip
Table 6.1: Abbreviation
6.2
Quick Troubleshooting for MC2 License Issues
If the license fails to check out properly, please follow the troubleshooting procedure step by step:
1. csh>setenv FLEXLM DIAGNOSTICS 3
2. csh>cd $MC2 INSTALL DIR/aux/flexlm/<platform>
<platform>could be below:
i86 r6, i86 re3 : Linux 32 bit on AMD/Intel CPU
amd64 re3 : Linux 64 bit on AMD/Intel CPU
sun4 u5, sun4 u8 : SunOS 32 bit on SPARC CPU
sun64 u5, sun64 u8 : SunOS 64 bit on SPARC CPU
x64 sun10 : SunOS 64 bit on AMD CPU
3. csh>./lmgrd -c <LICENSE FILE PATH>/license.dat -l interrad.log
4. csh>cd <PATH WHERE COMPILER IS PRESENT>
5. csh>mc2-eu -c <CompilerName>.mco
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6. csh>$MC2 INSTALL DIR/aux/flexlm/<platform>/lmutil lmstat -a
7. csh>$MC2 INSTALL DIR/aux/flexlm/<platform>/lmutil lmhostid
8. csh>uname -a
9. How to get correct hostids,
In SunOS
csh>hostid
In Linux
csh>/sbin/ifconfig eth0
and remove colons from HWaddr 00:06:5B:1C:7B:B0 ->00065B1C7BB0
Commands 6 to 9 help you find the key information which needs to match the license file and installation environment.
If license still fails to check out after these trial, send us the output on the terminal for the above commands (1 to 9),
the file ”interrad.log” and the license file so that we can understand what the issue is and solve it in a timely manner.
6.3
Other Related Problems and Solutions
A user guide provided separately will also help the following problems:
ˆ Incorrect hostid and responding message from OS system
ˆ The license server fails to start the compiler due to multiple installation with different software
ˆ License feature unavailable or network connection problem
ˆ Incompatible OS platform issue
ˆ Corruption of execution code after file transfer
ˆ Environment parameter setting in OS shell
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