Uploaded by zhicheng zhang

Roadmap for SiC power devices

advertisement
Power Matters.TM
SiC MOSFET & Diode Roadmap
September
p
12,, 2016
DPG-PDM
© 2016 Microsemi Corporation. Company Proprietary
1
SiC Capabilities Vs. Silicon
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
2
SiC Epitaxial Wafer
Cross-Polarization History
2007
2008
2009
2010
2011
2012
2013
2014
doping stain
Birefringence induced by lattice strain
strain. A perfect crystal will produce a uniform appearance when viewed between crossed polarizers
polarizers,
as the polarized light rotation will be the same everywhere. Lattice strain induced by lattice defects, polytype inclusions, compositional
in-homogeneities, etc. can all result in regions that induce locally different rotations of the polarized light. The local variations in light
rotation are easily imaged with this technique, providing a picture of crystal quality.
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
3
18‐Sep‐09
9
29‐Jan‐10
0
22‐Feb‐10
0
12‐Mar‐10
0
1‐Apr‐10
0
16‐Apr‐10
0
16‐Jun‐10
0
5‐Aug‐10
0
3‐Feb‐11
29‐Apr‐11
1
26‐May‐11
1
1‐Aug‐11
1
2‐Nov‐11
1
19‐Dec‐11
5‐Jan‐12
2
22‐Feb‐12
2
9‐Apr‐12
2
26‐Jun‐12
2
5‐Nov‐12
2
20‐Feb‐13
3
26‐Feb‐13
3
13‐Mar‐13
3
15‐Mar‐13
3
20‐Mar‐13
3
1‐Apr‐13
3
19‐Apr‐13
3
23‐Apr‐13
3
10‐May‐13
3
30‐May‐13
3
28‐Jun‐13
3
19‐Jul‐13
3
2‐Aug‐13
3
30‐Aug‐13
3
3‐Sep‐13
3
13‐Sep‐13
3
27‐Sep‐13
3
17‐Oct‐13
3
29‐Oct‐13
3
22‐Nov‐13
3
3‐Jan‐14
4
24‐Jan‐14
4
25‐Jan‐14
4
7‐Feb‐14
4
31‐Mar‐14
4
17‐Apr‐14
4
9‐May‐14
4
22‐May‐14
4
30‐Jun‐14
4
1μm
Thicknes
ss [μm
m]
Epitaxial Layer Thickness
220-0402 Thickness Target = 12.5um
target
Dow
G 2
Gen
Gen2 Thickness Target = 10.5
Dow
Gen 2
© 2016 Microsemi Corporation. Company Proprietary
Denko
Gen 2
Power Matters.TM
4
18‐Sep‐09
29‐Jan‐10
22‐Feb‐10
12‐Mar‐10
1‐Apr‐‐10
16‐Apr‐10
16‐Jun‐10
5‐Aug‐10
3‐Feb‐11
29‐Apr‐11
26‐May‐11
1‐Aug‐11
2‐Nov‐11
19‐Dec‐‐11
5‐Jan‐12
22‐Feb‐12
9‐Apr‐‐12
26‐Jun‐12
5‐Nov‐12
20‐Feb‐13
26‐Feb‐13
13‐Mar‐13
15‐Mar‐13
20‐Mar‐13
1‐Apr‐‐13
19‐Apr‐13
23‐Apr‐13
10‐May‐13
30‐May‐13
28‐Jun‐13
19‐Jul‐13
2‐Aug‐13
30‐Aug‐13
3‐Sep‐13
13‐Sep‐13
27‐Sep‐13
17‐Oct‐13
29‐Oct‐13
22‐Nov‐13
3‐Jan‐14
24‐Jan‐14
25‐Jan‐14
7‐Feb‐14
31‐Mar‐14
17‐Apr‐14
9‐May‐14
22‐May‐14
30‐Jun‐14
1015
Dopin
ng concentra
ation
m-3]
[cm
Epitaxial Layer Doping
Dow
Early Gen 2
Dow
Gen 2
© 2016 Microsemi Corporation. Company Proprietary
Denko
Gen 2
Gen 2 Doping Target = 6E15
0402 Doping Target = 5.3E15
target
Dow
Gen 2
Power Matters.TM
5
© 2016 Microsemi Corporation. Company Proprietary
30‐Jun‐14
22‐May‐…
…
9‐May‐14
17‐Apr‐14
31‐Mar‐…
…
7‐Feb‐14
25‐Jan‐14
24‐Jan‐14
3‐Jan‐14
22‐Nov‐13
29‐Oct‐13
17‐Oct‐13
27‐Sep‐13
13‐Sep‐13
3‐Sep‐13
30‐Aug‐13
2‐Aug‐13
19‐Jul‐13
28‐Jun‐13
30‐May‐…
…
10‐May‐…
…
23‐Apr‐13
19‐Apr‐13
1‐Apr‐13
20‐Mar‐…
…
15‐Mar‐…
…
13‐Mar‐…
…
26‐Feb‐13
20‐Feb‐13
5‐Nov‐12
26‐Jun‐12
9‐Apr‐12
22‐Feb‐12
5‐Jan‐12
19‐Dec‐11
2‐Nov‐11
5Å
RM
MS Surrface R
Roughn
ness[Å
Å]
Epitaxial Layer Surface Roughness
Denko
D
k
Gen 2
Power Matters.TM
6
200
D
Defect
count
[per 100mm waffer]
Epitaxial Layer Defect Count
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
7
Special Processing
Contrast to Silicon Technology
• Dopant introduction by implant at elevated temperatures
• Dopant activation, implant damage anneal at high temperatures
• No diffusion
• High temperature gate oxidation
• Above translates into all layer removal post dopant introduction for
electrical activation
• Alignment is critical
E220
Production Implanter
CentroTherm CHV-100
P t Implant
Post
I l t Annealing
A
li tto 1700°C
© 2016 Microsemi Corporation. Company Proprietary
Hi Temp Oxidation
SiC MOSFET Gate Oxidation
Power Matters.TM
8
SiC MOSFET Transistor X-Section
poly gate
source
p-well
N- drain epitaxyt
Doping Concentra
ation [cm-3]
Source (N14)
# Athena simulation
Voltage blocking p-well (Al27)
Vth adjust p-well (Al27)
Depth [µm]
• Simulation-based technology development to cut cycles of learning
• Flexibility of design variations for special applications
• Thick
Thi k Al
Al-Cu
C metallization
t lli ti ffor iinterconnect
t
t and
db
bond
d pads
d
• Dual layer metal process integration for maximized packing density
• Thick final passivation for maximum reliability
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
9
Process Integration
• P-well implants for reduced RDS(ON) contribution from JFET region
o Vth adjustment implant
o Voltage blocking implant
• Balance between guard-ring, p-well voltage blocking enables UIS capability
• Topology conforming backend metallization for high yield
Mask 1
M1
M2
p-well1
p-well1
pw1
M2
pw1
p-well2
p-well2
n-epitaxy
n-epitaxy
n-substrate
n-substrate
(A)
(B)
M1
M2
n+ source pw
1
Mask 3
M2
+
pw n source
1
p-well2
p-well2
gate poly
n+ source
pw1
p+
n+ source
pw1
p+
pw1
p-well2
p+
p-well2
p-well2
n-epitaxy
n-epitaxy
n-substrate
n-substrate
(C)
n+ source
pw1
n+ source
p+
gr
p-well2
n-epitaxy
p
y
n-substrate
(D)
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
10
Microsemi SiC MOSFETs
Voltage
Current
RDS(ON)
Part Number
700V
35A
~100mΩ
APT35SM70B
APT35SM70S
TO-247
D3
Mid-August
TO-247
D3
SOT-227
Mid A
Mid-August
t
New
Package
Samples Availability
700V
70A
53 Ω
53mΩ
APT70SM70B
APT70SM70S
APT70SM70J
700V
130A
33mΩ
APT130SM70B
APT130SM70J
TO-247
SOT-227
End-July
1200V
25A
140mΩ
APT25SM120B
APT25SM120S
TO-247
D3
Early-August
APT40SM120B
APT40SM120S
APT40SM120J
APT80SM120B
APT80SM120S
APT80SM120J
TO‐247
D3
SOT‐227
TO-247
TO
247
D3
SOT-227
APT5SM170B
APT5SM170S
TO-247
D3
N
New
1200V
40A
80mΩ
1200V
80A
40mΩ
1700V
5A
800 Ω
800mΩ
© 2016 Microsemi Corporation
Mid-June
then
Early-July
Mid J ne
Mid-June
then
Mid-July
E l O t b
Early-October
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
12
What Makes A High Speed Switch
Typical Transistor Gain Characteristics
ft
fmax
Transistor switching speed
Transistor
i
power gain
i
gm
ft 
Cgs  Cgd
ft
f max 
rg  Cgd
ft
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
13
gm @ 10A, 1
10V
gm Optimization
gm
g m’
g m' 
gm
1  g m Rs
Rs
RDS(ON) @ 10A
10A, 20V
• Packing density (without increasing parasitic capacitance)
• Source resistance minimized (gm vs. RDS(ON) plot)
o Perfection of source contact formation
o Push the limit on gate/source overlap without trading manufacturability
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
14
DC Characteristics Key to
Switching Performance
N
Normalize
ed RDS(ON)
Best in Class RDS(ON) vs. Temperature
2.2
2.1
2
19
1.9
1.8
1.7
16
1.6
1.5
1.4
1.3
1.2
1.1
1
09
0.9
Competitor 2
1200V, 30A, 80mΩ
Competitor 1
1200V, 36A, 80mΩ
Microsemi
APT40SM120B
1200V, 40A, 80mΩ
25
50
75
100 125 150 175 200
Tj [°C]
• Lower RDS(ON) at temperature provides higher ceiling for continuous current rating
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
16
RG & Dynamic Performance
Turn-On
Turn-Off
+20V
+20V
Gate driver
ON
Gate driver
ig
OFF
RG(MOSFET)
RG(MOSFET)
OFF
ON
Ciss
20V
RG driver   RG  MOSFET 
Ciss
ig
MOSFET
ig t  0  
MOSFET
ig t  0  
20V
RG driver   RG  MOSFET 
• High gate resistance limits available charging current
current, consequently
consequently, retards
transistor switching performance
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
17
Ultra Low Gate Resistance
Minimized Switching
g Energy
gy Loss & Higher
g
Switching
g Frequency
q
y
10
9
8
RG (Ω)
7
6
Competition High RG
5
4
3
2
Microsemi Low RG
1
2
3
4
Compettitor 2
Compettitor 1
Oscillation-free with
minimal external RG
1
APT40SM
M120B
80m
mΩ
0
APT50SM
M120B
50mΩ
0
5
Microsemi
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
18
High Transconductance (gm) Cuts ton
Microsemi
ID [A]
gm [S]
competitor 1
† VD=0.1V
VG [V]
• 2× gm at the start of the turn-on
turn on process
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
19
High Transconductance (gm) Cuts ton
Microsemi (RG=7Ω) Intentionally added external
Rg to show case high gm
Competitor
p
1 ((RG=0Ω))
25
20
Microsemi 50mΩ (7Ω)
10
Microsemi 50mΩ (0)
5
0
70
60
D 50
40
30
20
10
0
12,000
Comp 1 (0)Microsemi
1.E+01
ID
solid=7Ω
dashed=0 Ω
Id [[A]
VG
1.E+02
15
V
1 E+00
1.E+00
competitor 1
1.E-01
Sub-threshold
S
b th h ld slope:
l
Shallow junction and
good interface quality
Pon
10,000
8,000
competitor 1
6,000
1.E-02
0
4 000
4,000
2,000
Microsemi
0
-20
-10
0
10
20
Time [ns]
30
40
50
5
10
15
20
Vg [V]
• Superior sub-1A gm jumps start the turn-on process
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
20
Maximum Switching Frequency, fmax
1.E+06
Total switching time ≤ 5% switching period
Microsemi
APT50SM120B
1200V, 50A, 50mΩ
fmax
fmax [Hz]
[Hz]
1.E+05
Limitation 1
Competitor 2
1200V, 30A, 80mΩ
Thermally limited switching frequency
1.E+04
Microsemi
APT40SM120B
1200V, 40A, 80mΩ
Limitation 2
† T =150°C; T =75°C
j
c
1.E+03
0
10
20
30
40
50
60
IDID [A]
[A]
Dynamic performance breakaway enablers:
•
Superior Eon (ton) due to high gm, ultra low RG
•
Superior Eoff due to extremely low RG (yet oscillation free with very low external RG)
•
Low RDS(ON) at high temperatures extends switching frequency and current capability
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
21
Superior Short Circuit Withstand
Microsemi
Competitor 1
8.5µs
• Microsemi
Microsemi’s
s 80mΩ SiC MOSFET demonstrates 25% longer
short circuit capability
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
22
Superb Avalanche Ruggedness
Unclamped inductive load
VDD
v  L
APT40SM120B
di
dt
Vg=20V
Id=20A
(1200V/80mΩ/40A)
Max Vd=2225V
DUT
gate poly
p+
n+ source
pw1
pw1
p-well2
n+ source
p+
gr
2 3J (20A)
2.3J
p-well2
n-epitaxy
n-substrate
• Competitor1 not UIS rated, competitor2 GEN2 1200V/80mΩ/36A Ea=1J
1J (20A)
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
23
SiC MOSFET Technology Reliability Assessment
Field-driven
intrinsic
weakness in
bulk SiC
materials
SiC gate
oxide,
interface
quality
Gate oxide
lifetime
High
temperature
reverse bias
(HTRB)
Positive bias
temperature
instability
(PBTI)
Negative bias
temperature
instability
(NBTI)
• 2000hrs VDD=960V
@ 175°C
• 2000 hrs VG=+20V
@ 175°C
• 2000 hrs VG=-20V
@ 175°C
Timedependent
dielectric
breakdown
(TDDB)
• Constant current stress
to breakdown
© 2016 Microsemi Corporation. Company Proprietary
Stacking
faults growth
in epitaxial
wafers
Body diode
forward bias
stress
• 100A/cm2 forward
current through body
diode
Power Matters.TM
24
Die Size Scaling
Larger=More capacitance=More Switching Loss?
Difference Between On/OFF
(not described by Qg characteristic)
20
† Inductive switching IV
18
turn-on
16
14
12
Id [A]
10
8
6
4
turn-off
2
0
0
100
200
300
400
500
600
700
Vd [V]
• Turn-on: An energizing process with transistor gm generator hard at work
p
• Turn-off: Capacitive
• Area under the dynamic load-line: Eon>Eoff
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
26
Gate Charge (Qg) Characteristic
linear saturation
sC
CA < CC  SA > Sc
ON
sA
450 OFF
700
• Plateau voltage:
g gm ((but note: Qg characteristic has no gm action,, i.e.,, high
g gm does not
speed things up due to the very choked gate current contrast to real switching. Further,
more gate charge does not mean higher switching loss necessarily)
• Slope of Vg in region A: Capacitance at weak turn-on (CA)
• Flatness of Vg in region B: Degree of saturation
• Slope of Vg in region C: Capacitance at strong turn-on (CC)  No contribution to
switching power loss (Vd=0)
Cgg
Cgd
CC
10V
CA
© 2016 Microsemi Corporation. Company Proprietary
Vth
Vgs=d
1kV
Vds=g27
Power Matters.TM
Low Current Qg @ 10A
Vd
25
40A (10A) VG
1E+03
80A (10A) VG
40A (10A) VD
80A (10A) VD
APT80
(solid)
APT40
(dashed)
20
1E+02
Vg [V]
1E 01
1E+01
VD [V]
† Transistor size
Vg [V
V]
15
Vd [V]
10
APT80=2× APT40
δ=3V
9V
1E+00
6V
5
-5
5.0E
0E-5
5
0
0 0E+0
0.0E+0
-5
1E-01
5 0E-5
5.0E
5
1 0E-4
1.0E
4
1 5E-4
1.5E
4
2 0E-4
2.0E
4
Time [s]
No Eoff APT80
2 5E-4
2.5E
4
1E-02
• Apparent: Bigger transistor=More capacitance (Vg slope,
slope duration)
• Not so obvious: Bigger transistor=Lower Vplateau=Higher gm
• Turn-on: gm-dictated process  bigger transistor wins
• Turn-off: Eoff worse for the bigger transistor (Eoff is purely capacitance)
• Etotal remains constant (current/capacitance scaling)  equal for big and small @
low/moderate currents
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
28
High Switching Current
180
APT80(1200V/80A) +20V
+18V
APT40(1200V/40A)
+16V
160
140
+14V
120
ID [A]
+20V
+18V
+16V
100
+14V
80
+12V
60
40
+8V
+8V
20
+6V
+6V
0
ON
0
5
10
15
VDS [V]
450 OFF
700
• VG required for a larger transistor to support a given current is lower
• @ a given high switching current, VG of a smaller transistor is required to climb to a
higher value to support ID in the turn-on process  Lag in VD fall
f time to complete turnon  Eon ↑
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
29
High vs. Low Switching Current Qg
(for APT40SM)
25
1E+03
APT40 (10A) VG
APT40 (60A) VG
APT40 (10A) VD
APT40 (60A) VD
Vd
20
1E+02
60A
15
Vg [V]
10
1E+01
VD [V]
Vg [V
V]
10A
Vd [V]
60A
5
10A
1E+00
5.0E
0E-5
5
-5
0
0.0E+0
0
0E+0
5 0E-5
5.0E
5
1 0E-4
1.0E
4
1 5E-4
1.5E
4
Time [s]
-5
1E-01
• In contrast to 10A
o 60A pushes the transistor to higher Vg (more saturated) to support current
o Transistor struggles to support the current
o Higher Vd is required
o Lag in Vd fall results
o Note the worse gate voltage slope indicative of higher gate capacitance at higher Vg
(no contriution to loss)
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
30
High Current Qg @ 60A
(APT40 vs.
vs APT80)
25
1E+03
Vd
APT40 (60A) VG
APT80 (60A) VG
APT40 ((60A)) VD
APT80 (60A) VD
APT40
(dashed)
20
1E+02
APT80
(solid)
Vg [V]
15
Vg [V] 12.4V
δ=4.25V 10
1E+01
Vd [V]
8.15V
1E+00
5
5 0E 5
-5.0E-5
0
0 0E+0
0.0E+0
-5
1E-01
5 0E 5
5.0E-5
1 0E 4
1.0E-4
1 5E 4
1.5E-4
2 0E 4
2.0E-4
2 5E 4
2.5E-4
Time [s]
1E-02
No Eoff APT80
• Smaller transistor screaming for gm (requires higher Vg to support high current)
• The falling of Vd slows toward the end of Miller plateau  onset of saturation for
smaller transistor to support current at a higher Vd
• Lag in Vd dissipates more power during turn-on
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
31
High Current Turn-On Lag
• @ a given
i
hi h switching
high
i hi currents
o Smaller transistor lags in gm  required to
sweep to a higher voltage (Vg, Vd)
o Smaller
S ll ttransistor
i t tturn-on lag
l lleads
d tto
higher turn-on switching loss
G, VD/10 [V]
VVG
g, Vd/10 [V]
50
1200V/40A (dashed)
1200V/80A (solid)
Vd/10
160
140
120
40
100
40A
80A
30
80
60
20
40
Vg
10
• A smaller transistor can only support a high
switching current at a higher Vds due to saturation,
i.e., drain voltage never falls sufficiently leading to
the increase of switching/conduction loss 
conduction loss  a bigger transistor is needed
Id
[A]
IID
d [A]
60
20
0
0
60000
50000
PPon
[V]
ON [W]
40000
40A
80A
30000
20000
conduction loss
due to
saturation
10000
0
1E‐8
1E‐7
1E‐6
Time [s]
Time
[s]
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
32
Transistor Size Scaling Summary
• Larger transistor  Lower conduction loss (RDS(ON))
• For a given voltage
• @ low/moderate switching current  Equal Etotal performance
• @ high switching current  Larger transistor has lower switching loss
• At a switching current where drain voltage fails to complete its fall 
Transistor size cannot support the current and a bigger transistor is required
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
33
Microsemi 700V SiC MOSFET Benchmarked
Against 700V Silicon Superjunction MOSFET
Microsemi SiC MOSFET APT70SM070B: 700V, 53mΩ
Silicon Superjunction MOSFET IPW65R045C7: 700V, 45mΩ
Norm
malized RDDS(ON)
(to 25°C)
Thermal Friendly SiC MOSFET
2.5
2.4
23
2.3
2.2
2.1
2
19
1.9
1.8
1.7
1.6
15
1.5
1.4
1.3
1.2
11
1.1
1
0.9
Silicon Superjunction
MOSFET
700V/45mΩ
SiC MOSFET
700V/53mΩ
25
50
75
100 125 150 175 200
Tj [°C]
• For silicon superjunction MOSFET, conduction loss deteriorates rapidly with
temperature while SiC MOSFET remains temperature insensitive
insensitive.
• Switching/conduction loss deteriorates at high current/temperature due to saturation
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
35
Norm
malized RDDS(ON)
(to 25°C)
Thermal Friendly SiC MOSFET
2.5
2.4
23
2.3
2.2
2.1
2
19
1.9
1.8
1.7
1.6
15
1.5
1.4
1.3
1.2
11
1.1
1
0.9
Silicon Superjunction
MOSFET
700V/45mΩ
SiC MOSFET
700V/53mΩ
25
50
75
100 125 150 175 200
Tj [°C]
• For silicon superjunction MOSFET, conduction loss deteriorates rapidly with
temperature while SiC MOSFET remains temperature insensitive
insensitive.
• Switching/conduction loss deteriorates at high current/temperature due to saturation
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
36
Silicon Superjunction MOSFET Qg ~
1.5×
700V/53mΩ SiC MOSFET (dotted)
50
1E+3
3E-9
700V/45mΩ superjunction MOSFET (solid)
Vd
45
1200V/40A
40
30
Vg [V]
25
1E+1 Vd [V]
20
Vg
15
Crss [F]
1E+2
35
2E-9
t
turn-on
1E-9
C
10
1E+0
5
0
0.0E+0
‐5
A
0E+0
1E-2
B
5.0E‐5
1.0E‐4
1.5E‐4
Time [s]
2.0E‐4
1E-1
2.5E‐4
1E‐1
1E+0
1E+1
1E+2
1E+3
Vds=g [V]
• Plateau Vg  silicon superjunction MOSFET lower  stronger gm (μn, die size)
• Slope of Vg in region A
o SiC MOSFET steeper  lower input capacitance Ciss in region A (Vth)
o SiC breakdown field 7.3×  Allows heavier doping for a given breakdown voltage
o For
F a given
i
breakdown
b kd
voltage
lt
and
d RDS(ON)  SiC MOSFET has
h a smaller
ll die
di size
i
o Silicon superjunction MOSFET die size 1.67×
• Flatness of Miller plateau (region B)
o Flat for silicon superjunction MOSFET  More saturation
o Never flat for SiC MOSFET  Much less saturation  More current capability
• Region C slope of Vg post Miller plateau (Cgg of Vg>Vth)  No contribution to loss
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
37
Qg Characteristic Summary
Features in gate
Switching performance
charge
implication
characteristic
gm
plateau voltage
SiC MOSFET
Silicon superjunction
MOSFET
turn-on loss
-
+
(die size, mobility)
-
Input
capacitance
slope(Vg)
switching loss
+
(die size, integration,
y )
layout)
Miller
capacitance
duration of Miller
plateau (till Vd
falls sufficiently)
switching loss
(+)
(die size, integration,
layout)
-
Saturation
flatness of
plateau
switching current,
temperature capability
+
-
linear saturation
sC
CA < CC  SA > Sc
ON
sA
450 OFF
© 2016 Microsemi Corporation. Company Proprietary
700
Power Matters.TM
38
SiC MOSFET Module Product Roadmap
 The SiC MOSFET Module product range is based upon:
• Two die sizes S5F04
and S5F05
• Two voltage ratings (700V and 1200V)
• APT70SM70D (700V /53 mOhms typ, 60 mOhms max)
• APT40SM120D (1200V/80 mOhms typ, 100 mOhms max)
• APT140SM70D (700V/30 mOhms typ, 35 mOhms max)
• APT80SM120D (1200V/40 mOhms typ, 55 mOhms max)
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
39
SiC MOSFET Module Product Roadmap
 Electrical configurations
• Boost Chopper
• Buck Chopper
• Single switch
• Phase leg
• Full bridge
• Triple phase leg
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
40
Packaging and power density
 To achieve the best switching performance and highest integration level
a custom approach totally dedicated to the application efficiency target
and mechanical constraints is the ultimate solution
Duplicated +DC terminals
Distributed +DC and –
DC terminals for
ceramic capacitors
decoupling
Thermal
sensor
G&S
OUT
Duplicated -DC terminals
Example of a high current, high frequency, high voltage SiC MOSFET
phase leg
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
41
Packaging and Power Density
Module performance and reliability depend on assembly material
choice
h i
Material
Base
Substrate
Die
CTE
(ppm/K))
(pp
Thermal
conductivity
(W/m.K)
Thermal
CTE
conductivity Rthjc (K/W)
(ppm/K)
(W/m K)
(W/m.K)
Density
(g/cc))
(g
CuW
6.5
190
17
Silicon Die (120 mm2) or
SiC Die (40mm2)
AlSiC
7
170
2.9
Cu/Al2O3
17/7
390/25
0.35
Cu
17
390
8.9
AlSiC/Al2O3
7/7
170/25
0.385
Cu/AlN
17/5
390/170
0.28
Al2O3
7
25
-
AlSiC/AlN
7/5
170/170
0.31
AlN
5
170
-
AlSiC/Si3N4
7/3
170/60
0.31
Si3N4
3
60
-
DBC s ub s t rat e So ld er J o int
Si
4
136
-
So ld er
SiC
2.6
370
-
4
136
Dice
Bas e
More closely matched TCEs of materials increases module lifetime.
Higher thermal conductivity maximizes thermal performance
Engineered materials such as AlSiC provide substantial weight
reductions (up to 50%) over traditional copper material.
© 2016 Microsemi Corporation. Company Proprietary
• AlSiC and Alumina offer best CTE
matching
• AlN and
d Si3N4 on AlSiC offer
ff
higher thermal performance with
good CTE matching
Power Matters.TM
42
Packaging and Power Density
 All full SiC Mosfet modules from Microsemi are built with
Aluminium Nitride (AlN) substrate for best thermal
p
performance
 Si3N4 substrates is offered as an option
 Any full SiC power module can be converted from a
standard
t d d copper b
base plate
l t tto an AlSiC b
base plate
l t ffor
extended operating temperature range and higher
p
cycling
y
g capability
p
y
temperature
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
43
Packaging and Power Density
 SiC technology is capable of high temperature operation
 All Microsemi SiC MOSFET modules use high temperature
solder alloy for die attach as a standard to allow maximum
junction temperature operation
 As SiC technology will improve, high temperature solder
alloy
ll will
ill b
become a lilimitation
it ti ffor extreme
t
jjunction
ti
temperatures operation
 Ag sintering technology is the future for SiC devices
assemblyy
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
44
Packaging and Power Density
Basic Ag sintering process
As printed
200-300ºC
3
After sintering
Organic cap
Ag Nano particle
 During Sintering process solvents and organic cap escape,
exposing pure silver core to allow particles to coalesce and
form solid conductive Ag structure
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
45
Packaging and Power Density
Ag is an ideal Die Attach Material
Melting
range
Density
CTE
Tensile
strength
Modulus
Thermal
conductivity
Electrical
resistivity
Material
°C
g/cm3
ppm/°C
MPa
GPa
W/m.K
µΩcm
Silver
962
10.5
20
140
76
419
1.6
287-296
11
29
29
-
27
8.5
80Au20Sn
280
14.5
16
276
59
57
16
96 5S 3 5A
96.5Sn3.5Ag
221
74
7.4
30
38
50
58
12 5
12.5
92.5Pb5Sn2.5Ag
 Ag paste is processed at 250°C – 300°C under pressure to form pure Ag
interface
 After processing , Ag paste acts as bulk Ag with a melting point of 962°C
 Density (85 to 90%)
• Thermal conductivity: 200 – 300 W/m.K
W/m K
• Electrical resistivity: 2 – 2.5 µΩcm
• No intermettallic phases formed
 Ag paste allows highest thermal performance and reliability
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.TM
46
Thank You
Microsemi Corporation (MSCC) offers a comprehensive portfolio of semiconductor and system solutions for
communications,, defense & security,
y, aerospace
p
and industrial markets. Products include high-performance
g p
and radiationhardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF
solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable antitamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and
services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally.
Learn more at www.microsemi.com
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo, CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1
1 (949) 380-6136
380 6136
Fax: +1 (949) 215-4996
email: sales.support@microsemi.com
www.microsemi.com
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any
particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical
equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance
specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and
provided by
y Microsemi hereunder is p
provided “as is,, where is” and with all faults,, and the entire risk associated with such
verifyy the same. The information p
information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights,
whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi,
and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.
©2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other
trademarks and service marks are the property of their respective owners.
TM
© 2016 Microsemi Corporation. Company Proprietary
Power Matters.
47
Download