Canvis a fitxers
LEF → smaller OBS
Perquè has ficat la mida (8.000000 8.000000 170.200000 160.000000) ?
La comanda write_lef_abstract té diverses opcions relacionades amb el OBS, a veure si trobo la
correcta per a no haver de tocar el .lef manualment.
LIB → change pin from internal to input
No veig cap comanda per a que ho escrigui bé automàticament, però és fàcil de canviar a mà
Warnings
**WARN: (IMPCTE-288): Could not locate the library tcbn28hpcplusbwp30p140tt0p9v25c
**WARN: (IMPCTE-290): Could not locate cell INVD0BWP30P140 in any library for view *
Aquests error venen del fitxer de constraints PE_row_netlist_sdc.sdc. Entenc que els 2 venen
d’aquí:
set_driving_cell -lib_cell INVD0BWP30P140 -library tcbn28hpcplusbwp30p140tt0p9v25c -pin
"ZN" [get_ports clk]
Tant la cel·la com la llibreria existeixen, i la cel·la està dins la llibreria, i a més la cel·la
INVD0BWP30P140 està dins del Cellviewer, llavors en algun moment la llegeix correctament. He
mirat que no hi hagi cap caràcters estrany amb el hexdump i tot està net.
El .view llegeix les tres llibreries (tt, ss, i ff) i llavors llegeix el .sdc per a mirar les constriants. Pels
warnings que surten, sembla que no troba la cel·la a la tt i llavors fa servir la ss, però com he
comentat abans, la cel·la i la llibreria (tt) existeixen...
Si li trec la comanda que especifica la llibreria (la comanda és opcional), no dona problema.
**WARN: (IMPLF-200): Pin * in macro 'PE' has no ANTENNAGATEAREA value defined. The
library data is incomplete and some process antenna rules will not be checked correctly.
Mirant les opcions per a fer el LEF, no veig alguna que sigui "include antenna" o similar.
Puc afegir el paràmetres manualment, però quin valor li fico?
**WARN: (TECHLIB-1329): The attribute 'related_power_pin' on the pin 'en_monit_tx' in cell
'PE' is missing, even though the cell has multiple supply voltages.
El pin 'en_monit_tx' no està connectat a res, al routing del PE. Mirant el vhdl, es fa servir a la
part de monitoreig, que està comentada. Ara per ara, aquest input no fa res.
Ho puc deixar així, i torno a fer el PE sense aquest input comentat?
**WARN: (TCLCMD-1461): Skipped unsupported command: set_units
El fitxer PE_row_netlist_sdc.sdc el genera automàticament el Genus, a partir de les constraints
i del script que li dono, no entenc perquè està ficant comandes que l'Innovus no entén, potser
és una cosa de versions...
Mirant per l'Innovus, la commanda correcta diria que és:
set_library_unit [-help] [-cap <string>] [-time <string>]
-help
-cap <string>
# Prints out the command usage
# capacitance unit for sdc data (string, optional)
-time <string> # time unit for sdc data (string, optional)
Commands
TO WRITE LEF
write_lef_abstract [-help] <out_file> [-add_obs_layers <layer_list>] [cut_obs_min_spacing] [-exclude_obs_layers <layer_list>] [-exclude_pin_layers
<layer_list>] [-extract_block_obs]
[-extract_block_pg_pin_layers <layer_list>] [ignore_bump_on_pin {all pg signal}] [-io_pad_pin] [-no_cut_obs] [-property] [stripe_pins [-selected ]] [-stripe_pins [-port_for_each_stripe_pin ]] [-stripe_pins [pg_pin_layers <layer_list>]] [-stripe_pins [-pg_nets <net>+]] [-top_layer <layer> [obs_above_top_layer <layer>+]] [-obs_above_top_layer <layer>+ ] [-extract_well_layer_obs
<well_layer_list> [-extract_well_obs_from_rows <margin>]] [-extract_well_layer_obs
<well_layer_list> [-merge_connected_well_only ]] [-obs_spacing <value_layer_pair_list>
[-obs_spacing_per_layer ]] [ -5.6 | -5.7 | -5.8 | -6.0 ] [-design_boundary
<point_list> ] [-cut_obs_to_expose_routing <microns> ]
-help
# Prints out the command usage
<out_file>
# LEF output file name (string, required)
-5.6
# write out LEF version 5.6 (bool, optional)
-5.7
# write out LEF version 5.7 (bool, optional)
-5.8
# write out LEF version 5.8 (bool, optional)
-6.0
# write out LEF version 6.0 (bool, optional)
-add_obs_layers <layer_list>
# Shapes on these layers will be written as
OBS shapes in the LEF. Cannot be routing or cut layers. (string, optional)
-cut_obs_min_spacing
(bool, optional)
# Cut OBS around pin shapes by min-spacing
-cut_obs_to_expose_routing <microns>
expose routing. (double, optional)
# Cut OBS from the boundary by <microns> to
-design_boundary <point_list>
boundary (string, optional)
# Write out SIZE and OBS based on the design
-exclude_obs_layers <layer_list>
((layer)+, optional)
# Do not create OBS shapes on these layers
-exclude_pin_layers <layer_list>
((layer)+, optional)
# Do not create PIN shapes on these layers
-extract_block_obs
# Extract OBS from BLOCK, RING, PAD macro
above top layer, and write to the LEF file (bool, optional)
-extract_block_pg_pin_layers <layer_list>
# Extract PG pins from BLOCK, RING, PAD, COVER
macros on these layers ((layer)+, optional)
-extract_well_layer_obs <well_layer_list>
# Extract OBS from instances on specified well
layers by merging all shapes into one bounding box ((layer)+, optional)
-extract_well_obs_from_rows <margin>
# Extract OBS from the bounding box of rows
plus the margin on specified well layers (double, optional)
-ignore_bump_on_pin {all pg signal}
optional)
# Do not dump bump shapes on pins (enum,
-io_pad_pin
# Write out IO pads that are connected to
design pins as LEF pin shapes (bool, optional)
-merge_connected_well_only
# Merge connected well shapes only, instead to
merge all shapes into one bounding box (bool, optional)
-no_cut_obs
optional)
# Do not cut OBS shapes around pins (bool,
-obs_above_top_layer <layer>+
# Write out OBS shapes rather than one large
abstract OBS shape for each wire and via on these layers that are not PIN shapes.
((layer)+, optional)
-obs_spacing <value_layer_pair_list>
section (string, optional)
# Write out LEF58_OBSSPACING property in OBS
-obs_spacing_per_layer
layer definition (bool, optional)
# Write out the spacing for each layer under
-pg_nets <net>+
((net)+, optional)
# Write out PG stripes only on these pg nets
-pg_pin_layers <layer_list>
((layer)+, optional)
# Write out PG stripes on these layers
-port_for_each_stripe_pin
# A separate LEF port will be created for each
pin shape created by -stripe_pins (bool, optional)
-property
(bool, optional)
# Write out all user defined design properties
-selected
pin shapes (bool, optional)
# Write out only selected PG stripes as LEF
-stripe_pins
LEF pin shapes (bool, optional)
# Write out PG stripes on top metal layer as
-top_layer <layer>
optional)
# Create OBS up to this layer ((layer),
TO WRITE LIB
write_timing_model [-help] <model_file> [-absolute_tolerance_optimistic_validation
<float>] [-absolute_tolerance_pessimistic_validation <float>] [absolute_tolerance_validation <float>]
[-assertions <constraint filename>] [-cell_name <cell_name>]
[-clock_transitions {<clk_slew1 clk_slew2>...}] [-gain <integer>] [include_aocv_weights] [-include_power]
[-include_power_ground] [-input_transitions {<input_slew1
input_slew2>...}] [-lib_name <lib_name>] [-max_num_loads <value>] [-max_num_transitions
<value>]
[-output_loads {<output_load1 output_load2>...}] [percent_tolerance_optimistic_validation <float>] [percent_tolerance_pessimistic_validation <float>]
[-percent_tolerance_validation <float>] [-precision <integer>]
[-resolution <float>] [-tolerance <float>] [-validation_dir <string>] [verilog_shell_file <filename>]
[-verilog_shell_module <top_module_name>] [-view <string>] []
[-post_check]
-help
# Prints out the command usage
<model_file>
(string, required)
# Specifies the name of the output file
-absolute_tolerance_optimistic_validation <float>
# This switch will specify the absolute
tolerance limit for flagging an optimistic failure. An optimistic path violating
absolute as well as percentage tolerance limit
# will be flagged as FAIL in
compare_model_timing output report. Default value of this switch is 15ps. This can be
used only when '-validate' is used with model
# extraction. (double, optional)
-absolute_tolerance_pessimistic_validation <float>
# This switch will specify the absolute
tolerance limit for flagging a pessimistic failure. A pessimistic path violating
absolute as well as percentage tolerance limit
# will be flagged as FAIL in
compare_model_timing output report. Default value of this switch is 15ps. This can be
used only when '-validate' is used with model
# extraction. (double, optional)
-absolute_tolerance_validation <float>
# Specifies the absolute tolerance value to
be used during the validation of extracted ETM. For more details refer
'compare_model_timing -absolute_tolerance'. This can
# be used only when '-validate' is used with
model extraction. The integer value specified with this switch is read as ns/ps
depending upon the time unit. Default 3ps
# (double, optional)
-assertions <constraint filename>
# Dumps the constraints for model, which is
used in validation flow (string, optional)
-cell_name <cell_name>
model (string, optional)
# Specifies the cell name used in the timing
-clock_transitions {<clk_slew1 clk_slew2>...}
# Specifies a range of slew values used at
all clock pins (string, optional)
-gain <integer>
# Represents an increase in the number of
delay arcs if a pin is removed (int, optional)
-include_aocv_weights
(bool, optional)
# writes stage weights on individual arcs
-include_power
block (bool, optional)
# Writes information of power consumed by the
-include_power_ground
pins (bool, optional)
# Writes the power ground information for
-input_transitions {<input_slew1 input_slew2>...}
# Specifies a range of slew values used at
all data input ports (string, optional)
-lib_name <lib_name>
timing model (string, optional)
# Specifies the library name used in the
-max_num_loads <value>
values (int, optional)
# Specifies the maximum number of output load
-max_num_transitions <value>
or clock slews (int, optional)
# Specifies the maximum number of input slews
-output_loads {<output_load1 output_load2>...}
# Specifies a range of load values used at
all output ports (string, optional)
-percent_tolerance_optimistic_validation <float>
# This switch will specify the percentage
tolerance limit for flagging an optimistic failure. An optimistic path violating
percentage as well as absolute tolerance
# limit will be flagged as FAIL in
compare_model_timing output report. Default value of this switch is 3%. This can be used
only when '-validate' is used with model
# extraction. (double, optional)
-percent_tolerance_pessimistic_validation <float>
# This switch will specify the percentage
tolerance limit for flagging a pessimistic failure. A pessimistic path violating
percentage as well as absolute tolerance
# limit will be flagged as FAIL in
compare_model_timing output report. Default value of this switch is 3%. This can be used
only when '-validate' is used with model
# extraction. (double, optional)
-percent_tolerance_validation <float>
# Specifies the percentage tolerance value to
be used during the validation of extracted ETM. For more details refer
'compare_model_timing -percent_tolerance'. This
# can be used only when '-validate' is used
with model extraction. Default 3% (double, optional)
-post_check
Valus. (bool, optional)
# Checks the generated ETM library using
-precision <integer>
for the timing model (int, optional)
# Specifies the floating point precision used
-resolution <float>
# Specifies the magnitude of delay difference
that can be ignored in extraction (double, optional)
-tolerance <float>
in percent (double, optional)
# Specifies the accuracy level of extractor
-validation_dir <string>
# This switch enables the validation of
generated ETM for corresponding view and displays number of failures at the end of
validation. It is mandatory to specify the
# name of validation directory with this
option (-validate valDir), this contains the write_model_timing, compare_model_timing
and summary reports. (string, optional)
-verilog_shell_file <filename>
# Generates a Verilog shell file that
instantiates the timing model (string, optional)
-verilog_shell_module <top_module_name>
Verilog shell file (string, optional)
# Specifies the top module name of the
-view <string>
extracted (string, optional)
# Specifies the view for which model needs to