Interfacing 8255 PPI with 8085 (Mode 1)
Theory:
Mode 1 (Handshake I/O)
In mode 1, handshake signals are exchanged between the MPU and peripherals before data transfer. Ports A and B act as
8-bit I/O ports, which can be set up as either input or output ports. Each port uses three lines from port C for handshake
signals, leaving the remaining two lines of port C for simple I/O functions.
When port A is configured as an input port, lines PC3, PC4, and PC5 handle control. Lines PC6 and PC7 can be set as
either input or output based on bit D3 (Cupper) of the control word. When port A is configured as an output port, lines
PC3, PC6, and PC7 manage control, while PC4 and PC5 can be programmed as either input or output depending on bit
D3 (Cupper) of the control word.
For port B, regardless of whether it is set as an input or output port, lines PC0, PC1, and PC2 are used for control.
Control word for input configuration:
D7
1
D6
0
D5
1
D4
1
D3
1/0
D2
1
D1
1
Control word for output configuration:
D0
X
D7
1
D6
0
D5
1
D4
0
D3
1/0
D2
1
D1
0
D0
X
Question:
1. Configure 8255A as:
- Port A: mode 1, input
- Port B: mode 0, output
Read port A and display the content in port B and datafile 1d of trainer kit (use maskable interrupt M6.5).
i) I/O Configure
D7
1
⇒ 80H
D6
0
D5
1
D4
1
D3
X
D2
0
D1
0
D0
X
D4
X
D3
1
D2
0
D1
0
D0
1
D4
X
D3
1
D2
1
D1
0
D0
1
ii) BSR Configure
Since, port A is at input mode, we will set PC4.
D7
0
⇒ 90H
D6
X
D5
X
iii) Generating SIM word
D7
X
D6
X
D5
X
We will reset D1 bit as it is for M6.5 and we must use maskable interrupt M6.5.
⇒ 0DH
Mnemonics Table
Mnemonics
MVI A,80H
OUT 83H
MVI A,0EH
OUT 83H
EI
MVI A,0DH
SIM
LAB: JNP lab
IN 80H
OUT 81 H
STA 8FF1
CALL 044CH
HLT
Address
8000 H
8001 H
8002 H
8003 H
8004 H
8005 H
8006 H
8007 H
8008 H
8009 H
800A H
800B H
800C H
800D H
800E H
8FBA H
8FBA H
8FBB H
8FBC H
8FBD H
8FBD H
8FBE H
8FBF H
8FC0 H
8FC1 H
8FC2 H
8FC3 H
Opcode
3E H
80 H
D3 H
83 H
3E H
0E H
D3 H
83 H
FB H
3E H
0D H
30 H
C3 H
00 H
80 H
DB H
DB H
80 H
D3 H
81 H
32 H
F1 H
8F H
CD H
4C H
04 H
76 H
Discussion
Initially, the I/O is configured. Then, based on the mode and switching of the port, the INTE signal is sent. The enable
interrupt instruction is then used. Similarly, to enable RST 6.5, a SIM word is created and sent to the accumulator. Finally,
we wait for the interrupt to occur and observe the output. As stated in the question, the content of input port A is displayed
at port B and on the data trainer kit.
2. Configure 8255A as:
- Port A: mode 0, output
- Port B: mode 1, input
Read the port B and display the content of datafile and port A. (Use RST 5.5)
i) I/O Configure
D7
1
D6
0
D5
0
D4
0
D3
0
D2
1
D1
1
D0
0
D5
X
D4
X
D3
0
D2
1
D1
0
D0
1
D3
1
D2
1
D1
1
D0
0
⇒ 86H
ii) BSR Configure
D7
0
D6
X
⇒ 05H is BSR configure as PC2 is set.
iii) Generating SIM word
D7
X
D6
X
⇒ 06H is SIM word
D5
X
D4
X
Mnemonics Table
Mnemonics
MVI A,86H
OUT 83H
MVI A,05H
OUT 83H
EI
MVI A,0EH
SIM
LAB: JNP LAB
IN 81H
OUT 80 H
STA 8FF1
CALL 044CH
HLT
Address
8000 H
8001 H
8002 H
8003 H
8004 H
8005 H
8006 H
8007 H
8008 H
8009 H
800A H
800B H
800C H
800D H
800E H
8FB3 H
8FB4 H
8FB5 H
8FB6 H
8FB7 H
8FB8 H
8FB9 H
8FBA H
8FB8 H
8FB9 H
8FBD H
Opcode
3E H
86 H
D3 H
83 H
3E H
05 H
D3 H
83 H
FB H
3E H
0E H
30 H
C3 H
00 H
80 H
DB H
81 H
D3 H
80 H
32 H
F1 H
8F H
CD H
4C H
04 H
76 H
Discussion
We first generated the I/O configure control word to set port B as input in mode 1 and port A as output in mode 0, and
then passed it to the control register. Next, we wrote the BSR control word to set PC2 and passed it to the control register.
After that, we wrote the EI (enable interrupt) instruction and similarly set RST 5.5 using SIM words. At the interrupt
vector table location, IN and OUT operations were performed. The subroutine was then called, and the program was
halted.
Conclusion:
In this lab, we interfaced the PPI 8255A with the 8085 in mode 1. The mechanism involved, along with the signals and
ports used, was thoroughly understood.