Edition 2020-21
Digital Electronics
& Microprocessor - 8085
PEN-Drive / G-Drive Course & LIVE Classroom Program
Workbook
Electronics & Telecommunication Engineering
Electrical Engineering
Electrical & Electronics Engineering
Instrumentation Engineering
GATE / ESE / PSUs
Digital Electronics & Microprocessor - 8085
PEN-Drive / G-Drive Course & LIVE Classroom Program
Workbook
ETC / EE / EEE / IN
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GATE ACADEMY ®
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Edition
:
2020-21
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GATE Syllabus
Electronics & Communication (EC) : Number systems; Combinatorial circuits: Boolean algebra,
minimization of functions using Boolean identities and Karnaugh map, logic gates and their static
CMOS implementations, arithmetic circuits, code converters, multiplexers, decoders and PLAs;
Sequential circuits: latches and flip‐flops, counters, shift‐registers and finite state machines; Data
converters: sample and hold circuits, ADCs and DACs; Semiconductor memories: ROM, SRAM,
DRAM; 8‐bit microprocessor (8085): architecture, programming, memory and I/O interfacing.
Electrical Engineering (EE) : Combinational and Sequential logic circuits, Multiplexer, De‐
multiplexer, Schmitt trigger, Sample and hold circuits, A/D and D/A converters, 8085
Microprocessor: Architecture, Programming and Interfacing.
Instrumentation Engineering (IN) : Combinational logic circuits, minimization of Boolean functions.
IC families: TTL and CMOS. Arithmetic circuits, comparators, Schmitt trigger, multi‐vibrators,
sequential circuits, flip‐flops, shift registers, timers and counters; sample‐and‐hold circuit,
multiplexer, analog‐to‐digital (successive approximation, integrating, flash and sigma‐delta) and
digital‐to‐analog converters (weighted R, R‐2R ladder and current steering logic). Characteristics of
ADC and DAC (resolution, quantization, significant bits, conversion/settling time); basics of number
systems, 8‐bit microprocessor and microcontroller: applications, memory and input‐output
interfacing; basics of data acquisition systems.
Table of Contents
Sr.
Chapter
Pages
1.
Logic Gates ……………………………………………………………………………..………….
1
2.
Boolean Algebra …………………………………………………..…………………………….
8
3.
K – Maps ……………………………………….…………………………………….…..….…….
17
4.
Number System, Binary Codes & Complement Form …………………...…….
26
5.
Combinational Circuits …………………………………………………………………..…..
32
6.
Sequential Circuits ………………………………………………………………....………….
46
7.
DAC & ADC ……………………………………………………………………….……………….
68
8.
Microprocessor 8085 ……………………………………………………..…….…………….
75
9.
Logic Family ……………………………………………………………………….……………….
89
10.
Semiconductor Memories ………………………………………………………………….
92
Video Lecture Information
Sr.
Lecture Name
0
How to Study Digital Electronics & Microprocessor 8085 ?
Logic Gates
1
Basic gates‐AND, OR & NOT
2
Universal gates‐NAND
3
Designing using Minimum number of NAND gates
4
Universal gates‐NOR
5
Designing using Minimum number of NOR gates
6
Workbook Questions 1‐5
7
Switching Circuit Representation‐basic & universal gates
8
Special Purpose Gates‐XOR
9
Special Purpose Gates‐XNOR
10
Workbook Questions 6‐12
11
Switching Circuit Representation‐Special Purpose Gates
12
Workbook Questions 13‐14
13
Special Case in minimum number of NAND & NOR gates
14
Workbook Questions 15‐16
15
Workbook Questions 17‐19 Based on Propagation Delay
16
Ring Oscillator & Workbook Questions 20‐21
Boolean Algebra
1
Laws of Boolean Algebra
2
Conensus Law
3
Associative Law, DeMorgan's Law & Duality
4
Maximum Number of Boolean Functions
5
Workbook Questions 1‐6
6
Workbook Questions 7‐12
7
Representation of Boolean Function‐SOP & POS
8
Standard/Canconical SOP & POS form (Part 1)
9
Standard/Canconical SOP & POS form (Part 2)
10
Standard/Canconical SOP & POS form (Part 3)
11
Workbook Questions 13‐23
12
Minterms through Logic gates & workbook questions 24‐26
K – Maps
1
Two variable K‐Maps
2
Three variable K‐Maps
3
Four variable K‐Maps
4
Workbook Questions 1‐6
5
Workbook Questions 7‐12
6
Concept of Don't Care
7
Workbook Questions 13‐17
8
Workbook Questions 18‐21
Duration
0:26:32
0:35:40
0:29:23
0:20:40
0:15:16
0:17:11
0:19:11
0:29:36
0:36:37
0:32:14
0:12:17
0:21:05
0:11:46
0:08:28
0:17:23
0:19:31
0:11:58
0:20:17
0:32:31
0:19:35
0:17:10
0:22:42
0:22:17
0:26:19
0:30:44
0:15:12
0:30:45
0:20:52
0:27:22
0:38:02
0:35:16
0:36:20
0:34:30
0:15:48
0:16:07
0:29:31
9
Workbook Questions 22‐25
10
Five variable K‐Maps & Workbook Question 26
11
Prime Implicants & Essential Prime Implicants
12
Workbook Questions 27‐33
Number System, Binary Codes & Complement Form
1
Number System & Conversion (Part 1)
2
Number System & Conversion (Part 2)
3
Workbook Questions 1‐11
4
BCD Codes
5
Workbook Questions 12‐14
6
Gray Code
7
Sign Magnitude & 2's complement representation (Part 1)
8
Sign Magnitude & 2's complement representation (Part 2)
9
Workbook Questions 1‐3
10
Workbook Questions 4‐8
11
Shortcut to find 2's
12
1's & 2's Complement's Arithmetic
13
Concept of Overflow
14
Workbook Questions 9‐11
Combinational Circuits
1
Introduction to Combinational Circuits & 2:1 Multiplexer
2
4:1 Multiplexer & 8:1 Multiplexer
3
Procedure to find output of Multiplexer
4
Workbook Questions 1‐6
5
Workbook Questions 7‐11
6
Workbook Questions 12‐15
7
MUX with enable input
8
Workbook Questions 16‐17
9
Designing of 2:1 Multiplexer
10
Designing of 4:1 Multiplexer
11
Designing of 8:1 Multiplexer
12
Designing any function using Minimum Number on MUX
13
Workbook Questions 18‐21
14
Workbook Questions 22‐25
15
Designing of Higher Order MUX using Lower Order MUX Part 1
16
Designing of Higher Order MUX using Lower Order MUX Part 2
17
Demultiplexer
18
Decoder Part 1
19
Decoder Part 2
20
Designing of Higher Order Decoder using Lower Order Decoder Part 1
21
Workbook Question 1‐4 (Decoder)
22
Encoder
23
Priority Encoder
24
Half Adder & Full Adder
0:27:32
0:12:20
0:38:18
0:34:34
0:27:22
0:29:29
0:39:22
0:25:21
0:05:17
0:17:28
0:21:20
0:22:09
0:31:22
0:22:52
0:11:51
0:30:05
0:28:21
0:09:07
0:17:34
0:24:59
0:14:21
0:27:49
0:21:17
0:18:00
0:21:45
0:12:11
0:20:45
0:29:40
0:20:16
0:22:43
0:26:08
0:16:31
0:24:43
0:22:27
0:26:23
0:39:00
0:35:24
0:32:24
0:34:25
0:30:15
0:25:42
0:34:33
25
Half Subtrator & Full Subtrator
26
Workbook Questions 1‐3 (Adder & Subtrator)
27
Binary Parallel Adder
28
Workbook Questions 4‐6 (Adder & Subtrator)
29
Workbook Question 7‐8 (Adder & Subtrator)
30
Comparator
31
Workbook Questions 1‐2 (Comparator)
32
4‐bit Comparator
33
Code Converter Part 1
34
Code Converter Part 2
35
Programmable Logic Devices
36
Workbook Question 1‐3 (PLDs)
37
Workbook Question 1‐4 (Code Converter)
Sequential Circuits
1
Sequential Circuits & Memory Element
2
SR Latch using NOR gate
3
SR Latch using NAND gate
4
Equivalence of SR Latch using NOR gate & SR Latch using NAND gate
5
Introduction to Flip‐Flop
6
SR Flip‐Flop using NOR Latch
7
Equivalence of SR Flip‐Flop using NOR Latch & SR Flip‐Flop using NAND Latch
8
SR Flip‐Flop using NAND Latch
9
Characteristics Table, Characteristics Equation and Excitation table of SR Flip‐Flop
10
D Flip‐Flop (NOR Latch & NAND Latch)
11
JK Flip‐Flop using NOR Latch
12
JK Flip‐Flop using NAND Latch
13
Characteristics Table, Characteristics Equation and Excitation table of JK Flip‐Flop
14
T Flip‐Flop (NOR Latch & NAND Latch)
15
Quick Revision of Latch & Flip‐Flop
16
Workbook Questions (1‐5)
17
Workbook Questions (6‐9)
18
Flip‐Flop Conversion
19
Workbook Questions (10‐14)
20
Designing of Synchronous Counter from Next State Equation
21
Designing of Synchronous Counter from State Table or State Diagram
22
Workbook Question 1‐3
Analysis of Synchronous Counter
23
(State Table or State Diagram or Sequence from Circuit)
24
Workbook Questions 4‐6
25
Workbook Questions 7‐10
26
Workbook Questions 11‐13
27
Workbook Questions 14‐17
28
External Input in Counter and UP/DOWN Counter
29
Alternative approach to Analyse Synchronous Counter
0:34:31
0:13:16
0:26:12
0:22:42
0:32:37
0:32:16
0:23:48
0:19:08
0:17:53
0:39:23
0:29:45
0:04:25
0:38:06
0:22:16
0:23:38
0:22:13
0:19:39
0:18:43
0:11:59
0:13:14
0:14:22
0:25:43
0:23:56
0:32:57
0:22:37
0:15:16
0:11:31
0:31:33
0:14:30
0:24:29
0:32:42
0:41:51
0:35:03
0:29:34
0:23:29
0:14:38
0:26:23
0:36:30
0:29:46
0:24:29
0:37:29
0:11:58
30
Alternative Solutions to Workbook Questions 4‐9
31
Alternative Solutions to Workbook Questions 10‐17
32
Workbook Question 18
33
Workbook Question 19‐20
34
Workbook Question 21
35
Workbook Question 22‐24
36
Edge Trigged and level trigged Flip‐Flops
37
Concept of Asynchronous Counter
38
MOD 8 or divide by 8 Asynchronous Counter
39
Designing of Down Asynchronous Counter
40
MOD‐N Asynchronous Counter
41
Asynchronous Clear and Preset Input
42
Analysis of MOD‐N Asynchronous Counter (Part 1)
43
Analysis of MOD‐N Asynchronous Counter (Part 2)
44
Designing of MOD‐N Asynchronous UP Counter
45
Designing of MOD‐N Asynchronous DOWN Counter
46
Shortcut for Designing & Analysis of MOD‐N Asynchronous Counter
47
Comparison on Asynchronous Counter & Synchronous Counter
48
Workbook Question 1‐6
49
Workbook Question 7‐10
50
Concept of Frequency Division in MOD‐N Asynchronous Counter
51
Workbook Question 10‐11
52
Synchronous Clear and Preset Input
53
Workbook Question 12‐13
54
Workbook Miscellaneous Questions (FF and Counters) 1‐3
55
Workbook Miscellaneous Questions (FF and Counters) 4‐6
56
Workbook Miscellaneous Questions (FF and Counters) 7‐9
57
Workbook Miscellaneous Questions (FF and Counters) 10‐12
58
Workbook Miscellaneous Questions (FF and Counters) 13
59
Delay Comparison in Asynchronous Counter & Synchronous Counter
60
Workbook Miscellaneous Questions (FF and Counters) 14‐16
61
Self Starting Counters & Workbook Miscellaneous Question 17
62
Cascading of Counters through Workbook Question 18
63
Cascading of Counters through Workbook Questions 19‐20
64
Workbook Miscellaneous Questions (FF and Counters) 21‐22
65
Race Around Condition
66
Master Slave Flip‐Flop & Workbook Miscellaneous Question (FF and Counters) 23
67
Shift Register
68
Application of Shift Register
69
Workbook Questions 1‐4
70
Workbook Questions 5‐6
71
Concept of Set‐up Time & hold time & Workbook Question 7
DAC & ADC
1
Weighted Resistor DAC & Workbook Questions 1‐5
2
Parallel Comparator ADC & Workbook Questions 6‐8
0:24:08
0:24:34
0:35:44
0:27:20
0:27:08
0:38:11
0:36:32
0:18:47
0:32:38
0:29:45
0:11:41
0:36:58
0:37:35
0:21:02
0:31:50
0:23:33
0:21:10
0:24:03
0:38:37
0:33:22
0:15:22
0:12:40
0:12:36
0:11:17
0:22:32
0:20:17
0:41:18
0:29:48
0:10:15
0:36:18
0:07:03
0:38:16
0:25:34
0:25:39
0:38:43
0:21:49
0:32:35
0:43:15
0:32:51
0:23:43
0:13:43
0:19:49
0:44:36
0:37:30
3
Successive Approximation ADC & Workbook Questions 9
4
Counter Type ADC & Workbook Questions 10
5
Full Scale Voltage, Resolution & Step Size through Workbook Questions 11‐13
6
Dual Slope ADC & Workbook Questions 14‐15
7
Workbook Questions 16‐19
8
Workbook Questions 20‐23
9
R‐2R Ladder Type DAC
10
Workbook Questions 24‐27
Microprocessor 8085
1
Introduction to Microprocessor 8085
2
Data Transfer Instruction Group (Part 1)
3
Data Transfer Instruction Group (Part 2)
4
Arithmetic Instruction Group (Part 1)
5
Arithmetic Instruction Group (Part 2)
6
Arithmetic Instruction Group (Part 3)
7
Logical Instruction Group
8
Workbook Questions 1‐11
9
Workbook Questions 12‐19
10
Branch Group Instructions (Part 1)
11
Branch Group Instructions (Part 2)
12
Stack Group Instructions
13
Workbook Questions 1‐6
14
Workbook Questions 7‐15
15
Workbook Questions 16‐18 based on IN & OUT Instruction
16
Workbook Questions 19‐21 based on DAA Instruction
17
T States, Machine Cycles & Instruction Cycle (Part 1)
18
T States, Machine Cycles & Instruction Cycle (Part 2)
19
Workbook Questions 1‐9
20
Workbook Questions 10‐12
21
Interrupts
22
Workbook Questions 1‐6
23
Memory
24
Workbook Questions 1‐15
25
Memory Interfacing
26
Workbook Questions 16‐22
27
Workbook Questions 23‐24
28
Workbook Questions 25‐29
Logic Family
1
Logic Family ‐ RTL & DTL with Workbook Questions 1‐3
2
CMOS Logic Family
3
Workbook Questions 4‐8
4
Workbook Question 9
Quick Revision of Digital Electronics (Part 1)
Quick Revision of Digital Electronics (Part 2)
0:32:35
0:17:20
0:29:06
0:47:29
0:36:11
0:23:37
0:28:48
0:17:06
0:44:33
0:39:54
0:39:19
0:34:35
0:37:25
0:15:55
0:29:07
0:33:28
0:32:42
0:37:34
0:52:11
0:21:26
0:37:28
0:37:06
0:13:14
0:37:02
0:18:04
0:37:37
0:25:29
0:27:42
0:22:42
0:06:46
0:17:32
0:38:41
0:52:12
0:30:33
0:35:38
0:17:22
0:40:20
0:30:35
0:20:51
0:12:49
1:12:37
1:20:32
1
Logic Gates
Objective & Numerical Ans Type Questions :
A
G1
Q.1
Q.2
B
The Boolean function Y = AB + CD is to be
realized using only 2-input NAND gates.
The minimum number of gates required is
_____________.
Which one of the following is the correct
output (f) of the below circuit ?
G2
Y
C
D
(A) NOR, OR
(C) NAND, OR
(B) OR, NAND
(D) AND, NAND
Q.6
A
B
EX-OR
AND
 
(C)  a + b  c + d 
(A)  a + b  c + d
Q.3
Q.4

 
(D)  a + b   a + d 
The Boolean expression Y(A, B, C) = A +
BC is to be realized using 2-input gates of
only one type. What is the minimum number
of gates required for the realization ?
___________.
The minimum number of 2-input NAND
gates required to implement the Boolean
function Z  AB C , assuming that A, B and
C are available is [GATE 1998, IIT Delhi]
Q.5
(A) two
(B) three
(C) five
(D) six
X
C
(B) a + b c + d
EX-NOR
Q.7
For the logic circuit shown in the above
figure, what is the required input condition
(A, B, C) to make output X = 1 ?
(A) 1, 0, 1
(B) 0, 0, 1
(C) 1, 1, 1
(D) 0, 1, 1
Match the logic gates in Column A with
their equivalents in Column B.
[GATE 2010, IIT Guwahati]
Column A
Column B
P.
1.
Q.
2.
R.
3.
S.
4.
In the figure shown, the output Y is required
to be Y  AB  C D . The gates G1 and G2
must be,
[GATE 2015, IIT Kanpur]
Codes : P
(A) 2
(B) 4
(C) 2
(D) 4
Q.8
Q
4
2
4
2
R
1
1
3
3
Q.9
Q.11 If the input to the digital circuit consisting of
a cascade of 20 X-OR gates is X, then the
output Y is equal to
[GATE 2002, IISc Bangalore]
S
3
3
1
1
1
Y
Which one of the following expressions
does NOT represent exclusive NOR of x and
y?
[GATE 2013, IIT Bombay]
(A) xy + x’y’
(B) x  y'
(C) x'  y
GATE ACADEMY®
2
Digital Electronics & Microprocessor 8085 [WB]
(D) x'  y'
For the output F to be 1 in the logic circuit
shown, the input combination should be
[GATE 2010, IIT Guwahati]
A
B
X
(A) 0
(B) 1
(C) X
(D) X
Q.12 Let x1  x2  x3  x4  0 where x1 , x2 , x3 ,
x4 are Boolean variables, and  is the XOR
operator.
Which one of the following must always be
TRUE?
[GATE 2016, IISc Bangalore]
(A) x1 x2 x3 x4  0
(B) x1 x3  x2  0
F
C
(A) A = 1, B = 1, C = 0
(B) A = 1, B = 0, C = 0
(C) A = 0, B = 1, C = 0
(D) A = 0, B = 0, C = 1
Q.10 A, B, C and D are input bits and Y is the
output bit in the XOR gate circuit of the
figure below. Which of the following
statements about the sum S of A, B, C, D and
Y is correct? [GATE 2007, IIT Kanpur]
A
B
XOR
XOR
Y
(C) x1  x3  x2  x4
(D) x1  x2  x3  x4  0
Q.13 A bulb in a staircase has two switches, one
switch being at the ground floor and the
other one at the first floor. The bulb can be
turned ON and also can be turned OFF by
any one of the switches irrespective of the
state of the other switch. The logic of
switching of the bulb resembles
[GATE 2013, IIT Bombay]
(A) an AND gate
(B) an OR gate
(C) an XOR gate
(D) a NAND gate
Q.14 Two square wave of equal period T , but
with a time delay  are applied to a digital
circuit whose truth table is shown in the
following figure.
X
1
C
D
XOR
(A) S is always either zero or odd.
(B) S is always either zero or even.
(C) S = 1 only if the sum of A, B, C and D is
even.
(D) S = 1 only if the sum of A, B, C and D is
odd.
T/2
T
t
Y
1
t
t+T/2
t
GATE ACADEMY®
3
Q.15 Assume that only x and y logic input are
available, and their complements x and y
Truth table shown below,
0
0
1
0
1
0
1
0
0
1
1
1
are not available. What is the minimum
number of 2-input NAND gates required to
implement x  y ? __________.
Q.16 In the given figure, the LED
[GATE 2001, IIT Kanpur]
The high and the low levels of the output of
the digital circuit are 5 V and 0 V,
respectively. Which one of the following
figures shows the correct variation of the
average value of the output voltage of  for
0  t  (T / 2)? [GATE 2007, IIT Kanpur]
VCC = 5 V
LED
1 kW
S1
(A)
1 kW
Output
1 kW
Y
1 kW
X
Logic Gates
S2
Vav
(A) Emits light when both S1 and S2 are
5V
closed.
(B) Emits light when both S1 and S2 are
t
T /2
opened.
(C) Emits light when S1 is opened and S2 is
(B)
closed.
Vav
(D) Doesn’t emit light, irrespective of the
switch positions.
5V
T/2
t
(C)
Vav
Q.17 All the logic gates shown in the figure have
a propagation delay of 20 ns. Let A  C  0
and B  1 unit time t  0 . At t  0 , all the
inputs flip (i.e. A  C  1 and B  0 ) and
remain in that state. For t  0 , output Z  1
for a duration (in ns) of ________.
5V
[GATE 2015, IIT Kanpur]
A
B
T/2
t
(D)
Z
C
Q.18 Consider the following circuit composed of
XOR gates as non – inverting buffers.
Vav
A
B
d1 = 2
2.5 V
T/2
t
d2 = 4
The non- inverting buffers have delays
1  2 ns and 2  4 ns as shown in the
figure. Both XOR gates and all wires have
GATE ACADEMY®
4
Digital Electronics & Microprocessor 8085 [WB]
zero delay. Assume that all gate inputs,
outputs and wires are stable at logic level 0
at time 0. If the following waveform is
applied at input A, how many transition(s)
(change of logic levels) occur(s) at B during
the interval from 0 to 10 ns?
pico-sec. What is the fundamental frequency
of the oscillator output?
[GATE 2001, IIT Kanpur]
V0
[GATE 2003, IIT Madras]
Logic 1
A
Logic 0
Time 0 1 2 3 4 5 6 7 8 9 10 ns 11 ns
(A) 1
(B) 2
(C) 3
(D) 4
(A) 10 MHz
(B) 100 MHz
(C) 1 GHz
(D) 2 GHz
Q.21 The inverters in the ring oscillator circuit
shown below are identical. If the output
waveform has a frequency of 10 MHz, the
propagation delay of each inverter is
[GATE 2002, IISc Bangalore]
Q.19 The gates G1 and G2 in figure have
output
propagation delays of 10 nsec and 20 nsec
respectively. If the input Vi makes an abrupt
change from logic 0 to 1 at time t  t0 , then
the output waveform V0 is
[GATE 2002, IISc Bangalore]
G1
V0
1
0
t0
Vi
Vi
Vi
(B) 10 ns
(C) 20 ns
(D) 50 ns
Practice (objective & Num Ans) Questions :
G2
0
(A) 5 ns
1
Q.1
z (t1  t0  10 nsec, t2  t0  20 nsec,
t3  t0  30 nsec)
Consider the logic circuit with input signal
TEST shown in the figure. All gates in the
figure shown have identical non-zero delay.
The signal TEST which was at logic LOW is
switched to logic HIGH. The output
TEST
(A) 1
0
t0
t1
t2
(A) Stays HIGH throughout
t3
(B) Stays LOW throughout
(B) 1
0
(C) Pulses from LOW to HIGH to LOW
t0
t1
t2
t3
(D) Pulses from HIGH to LOW to HIGH
Q.2
(C) 1
0
OUTPUT
t0
t1
t2
t3
For the circuit shown below the output F is
given by
X
F
(D) 1
0
t0
t1
t2
t3
Q.20 For the ring oscillator shown in the figure,
the propagation delay of each inverter is 100
(A) F = 1
(B) F = 0
(C) F = X
(D) F  X
GATE ACADEMY®
Q.3
Q.4
5
Minimum number of 2-input NAND gates
required to implement the function, F = ( X
+ Y ) (Z + W) is
(A) 3
(B) 4
(C) 5
(D) 6
Logic Gates
Q.7
x
A
y
Indicate which of the following logic gates
can be used to realize all possible
combinational Logic functions.
(A) Exclusive OR
(B) Exclusive NOR
(A) OR gates only
(C) NAND
(B) NAND gates only
(D) NOR
Q.8
(C) EX-OR gates only
(D) NOR gates only
Q.5
A
(C) an OR or an EX-NOR gate.
y1
XOR
y2
Which of the following truth table is
correct?
(C)
(D) an AND or an EX-OR gate.
Q.9
XNOR
(A)
(B) a NOR or an EX-NOR gate.
Z
B
The output of a logic gate is ‘1’ when all its
inputs are at logic ‘0’. The gate is either
(A) a NAND or an EX-OR gate.
For the combinational circuit shown in
figure,
NOT
Q.6
Identify the logic function performed by the
circuit shown in figure
A ring oscillator consisting of 5 inverters is
running at a frequency of 1.0 MHz. The
propagation delay per gate is _______ nsec.
Q.10 Any Boolean function can be realized using
only
A
B
Z
(A) NAND gate
(B) AND gate
0
0
0
1
(C) OR gate
(D) NOT gate
1
1
0
1
0
1
0
0
1
0
0
1
1
1
1
1
1
A
B
Z
A
B
Z
(A) Zero
(B) 1
0
0
0
0
0
1
(C) 4
(D) 7
0
1
1
0
1
0
1
0
1
1
0
1
1
1
0
1
1
0
A
B
Z
0
0
0
(B)
(D)
Q.11 The minimum number of NAND gates
required to implement the Boolean function
A  A B  A B C is equal to
Q.12 If A and B are the inputs to a logic gate, then
match the logic with its output
(a) NAND
(i) A  B
Boolean expression for the output of XNOR
(equivalence) logic gate with inputs A and B
is
(b) NOR
(ii) A  B
(c) XNOR
(iii) AB  AB
(A) A B  A B
(d) AND
(iv) A  B
(B) A B  A B
(C) ( A  B ) ( A  B )
(D) ( A  B ) ( A  B )
(A) a-ii, b-i, c-iii, d-iv
(B) a-ii, b-iv, c-iii, d-i
(C) a-i, b-iv, c-ii, d-iii
(D) a-iii, b-ii, c-iv, d-i
Q.13 The output of the logic gate in figure is
A
(A) 0
GATE ACADEMY®
6
Digital Electronics & Microprocessor 8085 [WB]
F
(B) 1
(D) A
(C) A
Q.14 What happens when a bit –string is XORed
with itself n – times as shown :
 B  ( B  ( B  ( B.....n times)
Q.20 The complete set of only those Logic Gates
designated as Universal Gates is
(A) NOT, OR and AND Gates.
(B) XNOR, NOR and NAND Gates.
(C) NOR and NAND Gates.
(D) XOR, NOR and NAND Gates.
Q.21 The output Y of the logic circuit given below
is
X
(A) Complements when n is even
(B) Complements when n is odd
(C) Divides by 2n always
(D) Remains unchanged when n is even
(A) 1
Q.15 Which of the following expression is not
equivalent to x ?
(A) x NAND x
(B) x NOR x
(C) x NAND 1
(D) x NOR 1
Q.16 The output of a logic gate is “1” when all its
inputs are at logic “0”. The gate is either
(A) A NAND or an EX-OR gate.
(B) A NOR or an EX-OR gate.
(C) An AND or an EX-NOR gate.
(D) A NOR or an EX-NOR gate.
Q.17 If the input to the digital circuit consisting of
a cascade of 20 X-OR gates is X, then the
output Y is equal to
1
Y
Y
(B) 0
(C) X
(D) X
Q.22 Which one of the following circuits is NOT
equivalent to a 2-input XNOR (exclusive
NOR) gate?
(A)
(B)
(C)
(D)
Q.23 The logic evaluated by the circuit at the
output is
X
Output
X
(A) 0
(B) 1
(C) X
(D) X
Q.18 The expression Y  AB is equivalent to
(A) A  B
(B) AB  A
(C) A  B
(D) AB
Q.19 The Boolean function Y = AB + CD is to be
realized using only 2-input NAND gates.
The minimum number of gates required is
(A) 2
(B) 3
(C) 4
(D) 5
Y
(A) XY  YX
(B) ( X  Y )XY
(C) ( XY )XY
(D) XY  XY  X  Y
Q.24 The minimum number of 2-input NAND
gates required to implement a 2-input XOR
gate is
GATE ACADEMY®
7
(A) 4
(B) 5
(C) 6
(D) 7
Q.25 In the logic circuit shown in the figure, Y is
given by
Logic Gates
Q.27 Find the fundamental frequency of the ring
oscillator given below. Propagation delay of
each inverter is 10ps.
V0
A
B
Y
C
(A) 8 GHz
(B) 16 GHz
(C) 8 MHz
(D) 16 MHz
D

(A) Y  ABCD
(B) Y  ( A  B )( C  D )
(C) Y  A  B  C  D
(D) Y  AB  CD
Q.26 The Boolean function F ( X , Y ) realized by
the given circuit is
X
F
Y
(A) XY  XY
(B) XY  XY
(C) X  Y
(D) X  Y
Answer Keys
Objective & Numerical Answer Type Questions
1.
3
2.
A
3.
3
4.
C
5.
A
6.
D
7.
D
8.
D
9.
D
10.
B
11.
B
12.
C
13.
C
14.
C
15.
4
16.
D
17.
40
18.
D
19.
B
20.
C
21.
B
Practice (Objective & Numerical Answer) Questions
1.
D
2.
B
3.
B
4.
B, D
5.
A
6.
B, C
7.
B
8.
B
9.
100
10.
A
11.
A
12.
B
13.
C
14.
D
15.
D
16.
D
17.
B
18.
A
19.
B
20.
C
21.
A
22.
D
23.
A
24.
A
25.
D
26.
A
27.
B
2
Boolean Algebra
(A) X Z  X Z  Y Z
Objective & Numerical Ans Type Questions :
Q.1
For the identity
(B) X Y  Y Z  Y Z
AB  AC  BC  AB 
(C) X Y  Y Z  X Z
AC , the dual form is
[GATE 1998, IIT Delhi]
(A) ( A  B) ( A  C) ( B  C )
(D) X Y  Y Z  X Z
Q.5
 ( A  B)( A  C)
(B) ( A  B ) ( A  C ) ( B  C )
For the circuit shown in figure the Boolean
expression for the output Y in terms of
inputs P, Q, R and S is
[GATE 2002, IISc Bangalore]
P
 ( A  B)( A  C )
(C) ( A  B) ( A  C) ( B  C)
Q
Y
 ( A  B)( A  C )
R
(D) A B  AC  B C  A B  AC
Q.2
The Boolean function x ' y ' xy  x ' y is
equivalent to
Q.3
Q.4
S
[GATE 2004, IIT Delhi]
(A) x ' y '
(B) x  y
(C) x  y '
(D) x ' y
If x and y are Boolean variables which one
of the following is the equivalent of
x  y  xy is
(A) x + y
(B) x + y
(C) 0
(D) 1
The Boolean expression
X Y Z  X Y Z + X Y Z  X Y Z  X Y Z can
be simplified to
[GATE 2003, IIT Madras]
(A) P  Q  R  S
(B) P  Q  R  S
(C) ( P  Q)  ( R  S )
(D) ( P  Q )  ( R  S )
Q.6
Let  denote the exclusive OR(XOR)
operation. Let ‘1’ and ‘0’ denote the binary
constants. Consider the following Boolean
expression for F over two variables P and Q
F ( P, Q)  1  P    P  Q    P  Q 
 Q  0
The equivalent expression for F is
[GATE 2014, IIT Kharagpur]
GATE ACADEMY®
Q.7
9
(A) P + Q
(B) P  Q
(C) P  Q
(D) P  Q
Boolean Algebra
P
Q
Q
R
For a three-input logic circuit shown below,
the output ‘Z ’ can be expressed as
[GATE 2017, IIT Roorkee]
f
P
R
P
Q
R
Z
Q
Q.8
(B) PQ  R
(C) Q  R
(D) P  Q  R
(D) P  Q  R
Q
Y
f
Y
R
Z
Which one of the following is TRUE?
[GATE 2005, IIT Bombay]
(A) F is independent of X
(B) F is independent of Y
(C) F is independent of Z
(D) None of X, Y, Z is redundant
For the logic circuit shown in figure write
the expression for Z.
[GATE 1998, IIT Delhi]
Q.9
(C) P  R
P
Consider the following circuit.
X
(B) P  Q
Q.11 The output Y in the circuit below is always
“1” when
[GATE 2011, IIT Madras]
R
(A) Q  R
(A) Q  R
A
X
C
Z
A
B
Y
(A) AC  AB  AB
(B) AC  AB
(C) AC  AB
(D) AC  BC  AB
Q.10 What is the Boolean expression for the
output f of the combinational logic circuit of
NOR gates given below ?
[GATE 2010, IIT Guwahati]
(A) two or more of the input P, Q, R are “0”.
(B) two or more of the inputs P, Q, R are
“1”.
(C) any odd number of the inputs P, Q, R is
“0”.
(D) any odd number of the inputs P, Q, R is
“1”.
Q.12 The logic gates shown in the digital circuit
below use strong pull-down nMOS
transistors for LOW logic level at the
outputs. When the pull-downs are off, highvalue resistors set the output logic levels to
HIGH (i.e. the pull-ups are weak). Note that
some nodes are intentionally shorted to
implement “wired logic”. Such shorted
nodes will be HIGH only if the outputs of all
the gates whose outputs are shorted are
HIGH.
X0
X1
X2
X3
Y
Digital Electronics & Microprocessor 8085 [WB]
The number of distinct values of X 3 X 2 X1 X 0
(out of the 16 possible values) that give
Y  1 is _______.
[GATE 2018, IIT Guwahti]
Q.13 The Boolean expression
F ( X ,Y , Z )  X Y Z  X Y Z
GATE ACADEMY®
10
(C) ( X  Y  Z ) ( X  Y  Z )
(X Y  Z) (X Y  Z)(X Y  Z)
(D) ( X  Y  Z ) ( X  Y  Z )
(X Y  Z) (X Y  Z)(X Y  Z)
Q.16 The minterm expansion of
X Y Z  X Y Z
converted into canonical product of sum
(POS) form is [GATE 2015, IIT Kanpur]
(A) ( X  Y  Z )( X  Y  Z )( X  Y  Z )
(X Y  Z)
(B) ( X  Y  Z )( X  Y  Z )( X  Y  Z )
(X Y  Z)
(C) ( X  Y  Z )( X  Y  Z )( X  Y  Z )
(X Y  Z)
(D) ( X  Y  Z )( X  Y  Z )( X  Y  Z )
(X Y  Z)
Q.14 The product of sum expression of a Boolean
function F ( A, B, C ) of three variables is
given by
F ( A, B, C )  ( A  B  C ).( A  B  C )
.( A  B  C ).( A  B  C )
The canonical sum of product expression of
F ( A, B, C ) is given by
f ( P, Q, R )  PQ  QR  PR is
[GATE 2010, IIT Guwahati]
(A) m2  m4  m6  m7
(B) m0  m1  m3  m5
(C) m0  m1  m6  m7
(D) m2  m3  m4  m5
Q.17 The simplified SOP (Sum of Product) form
of the Boolean expression
 P  Q  R  . P  Q  R  . P  Q  R 
is ___________.


(C)  P.Q  R 
[GATE 2011, IIT Madras]
(A) P.Q  R
(D)  P.Q  R 
0
0
0
0
[GATE 2000, IIT Kharagpur]
0
0 0 1 1 1 1
0
1 1 0 0 1 1
1
0 1 0 1 0 1
0
0 1 0 1 1 1
(B) ABC  ABC  ABC  ABC
(C) ABC  ABC  ABC  ABC
(A) AB  BC  CA
(A) ABC  ABC  ABC  ABC

Q.18 From the table, choose the correct logical
expression for Q.
A
B
C
Q
[GATE 2018, IIT Guwahati]

(B) P  Q.R
(B) A  B  C
(D) ABC  ABC  ABC  ABC
Q.15 A function of Boolean variables X, Y and Z
is expressed in terms of the minterms as
F ( X , Y , Z )   m(1, 2, 5, 6, 7)
(C) AB  BC  CA
(D) AB  BC  CA
Q.19 A Boolean function f of two variables x and
y is defined as follows
f (0, 0)  f (0, 1)  f (1, 1)  1; f (1, 0)  0
Which one of the product of sums given
below is equal to the function F ( X , Y , Z )?
Assuming complements of x and y are not
available, the minimum cost solution for
realizing f using only 2-input NOR gates and
2-input OR gates (each having unit cost)
would have a total cost of
[GATE 2004, IIT Delhi]
[GATE 2015, IIT Kanpur]
(A) ( X  Y  Z ) ( X  Y  Z ) ( X  Y  Z )
(B) ( X  Y  Z ) ( X  Y  Z ) ( X  Y  Z )
GATE ACADEMY®
11
(A) 1 unit
(B) 4 unit
(C) 3 unit
(D) 2 unit
Boolean Algebra
f1
f1 = ?
f2
Q.20 For the Boolean expression
f  a b c  abc +ab c  abc  abc
the minimized Product of sum (POS)
expression is [GATE 2011, IIT Madras]
(A) f  (b  c).(a  c )
f
(A)  m (4, 6)
(B)  m (4, 8)
(C)  m (6, 8)
(C)  m (4, 6, 8)
Q.25 Consider the logic circuit shown in the
below figure. The functions f1, f 2 and f (in
canonical sum of products form in decimal
notation) are [GATE 1997, IIT Madras]
(B) f  (b  c ).(a  c)
f1
f2
(C) f  (b  c ).(a  c)
f
f3 = ?
(D) f  c  abc
f1 ( w, x, y, z )   8,9,10
Q.21 The Boolean expression X(P, Q, R)  (0,5)
f 2 ( w, x, y, z )   7,8,12,13,14,15
is to be realized using only two 2-input
gates. Which are these gates?
f ( w, x, y, z )   8,9
(A) AND and OR
(B) NAND and OR
The function f 3 is
(C) AND and XOR
(D) OR and XOR
(A)  9,10
(B)  9
(C) 1,8,9
(D)  8,10,15
Q.22 Consider the following Boolean expression
for
F : (P, Q, R, S) = PQ + PQR+PQRS
The minimal sum-of-products form of F is
__________.
Q.26 Consider the following logic circuit whose
inputs are function f1 , f 2 , f 3 and output is f.
f1 ( x, y, z )
f 2 ( x, y , z )
[GATE 2014, IIT Kharagpur]
(A) PQ + QR + QS
(B) P + Q + R + S
f 3 ( x, y , z ) = ?
(C) P+Q+R+S
(D) P R + PRS  P
Given that
f ( x, y , z )
f1 ( x, y, z )  (0,1,3,5)
Q.23 If P, Q, R are Boolean variable, then
 P  Q  P.Q  P.R  P.R  Q  simplifies to
f 2 ( x, y, z )  (6,7) and
[GATE 2008, IISc Bangalore]
f ( x, y, z )  (1, 4,5),f3 is
(A) P.Q
(B) P.R
(C) P.Q  R
(D) P.R  Q
[GATE 2002, IISc Bangalore]
(A)  (1, 4, 5)
(B)  (6, 7)
(C)  (0, 1, 3, 5)
(D) None of the above
Q.24 Given f1 , f 3 and f in canonical sum of
products form (in decimal) for the circuit.
f1   m (4, 5, 6, 7, 8)
f3   m (1, 6, 15)
f   m (1, 6, 8, 15)
Then f 2 is
Practice (objective & Num Ans) Questions :
Q.1
The number of Boolean functions that can
be generated by n variables is equal to
n1
(B) 22
(C) 2 n1
(D) 2 n
(A) 2 2
[GATE 2008, IISc Bangalore]
n
Q.2
GATE ACADEMY®
12
Digital Electronics & Microprocessor 8085 [WB]
For the logic circuit shown in figure, the
output is equal to
(C) AB  ABC
(D) ( A  C )  B
Let * be defined as x * y  x  y,
Q.7
A
Let z = x*y.
Y
B
Value z * x is
C
Q.8
(A) A B C
Q.4
(C) 0
(D) 1
Which of the following operations is
commutative but not associative?
(A) AND
(B) OR
(C) A B  B C  A  C
(C) NAND
(D) EXOR
Q.9
The logical expression
y  A AB
The Boolean expression A  B  C is equal
to
equivalent to
(A) y  AB
(B) y  A B
(A) A  B  C
(B) A  B  C
(C) y  A  B
(D) y  A  B
(C) A  B  C
(D) A  ( B  C )
is
Q.10 The logic function f  ( x. y )  ( x . y ) is the
The logic expression for the output of the
circuit shown in figure 1 is
same as
(A) f  ( x  y )( x  y )
A
B
(B) f  ( x  y )( x  y )
C
(C) f  ( x. y )( x . y )
D
(A) AC  BC  CD
Q.5
(B) x
(B) A  B  C
(D) A B  B C
Q.3
(A) x  y
(B) AC  BC  CD
(C) ABC  C D
(D) AB  BC  C D
The Boolean expression of the output of the
logic circuit shown in figure is
A
(D) None of the above
Q.11 For the logic circuit shown in figure, the
simplified Boolean expression for the output
Y is
A
B
B
C
(A) Y  A B  A B  C
(B) Y  A B  A B  C
(C) Y  A B  A B  C
(D) Y  A B  A B  C
Q.6
Y
Y
The Boolean function A  BC is a reduced
form of
(A) AB  BC
(B) ( A  B )  ( A  C )
C
(A) A + B + C
(B) A
(C) B
(D) C
Q.12 The expression A  AB is equivalent to
(A) A  B
(B) AB  A
(C) A  B
(D) AB
Q.13 In the logic circuit shown in figure, the
output X is
GATE ACADEMY®
13
Boolean Algebra
(A) A D  B C D
B
C
A
(B) A D  B C D
X
(C) ( A  D) ( B C  D)
(D) A D  B C D
(A) AB  BC  CA
(B) A  B  C
(C) AB  BC  CA
Q.19 The simplest form of the Boolean expression
A B C D  A B C D  A B C D  ABCD
(D) AB  BC  CA
Q.14 Let f(A,B) = A’ + B Simplified expression
for function f (f (x + y, y), z) is
(A) (x’ + z)
(B) x y z
(C) xy’ + z
(D) None of the above
Q.15 The number of distinct Boolean expression of
4 variables is
(A) 16
(B) 256
(C) 1024
(D) 65536
Q.16 If the function W, X, Y and Z are as follows
W  R  PQ  R S
X  PQ R S  PQ R S  PQ R S
is
(A) AD
(B) BC
(C) AB
(D) AB
Q.20 Consider the following circuit.
X
Y
f
Z
Which on the following is TRUE ?
(A) f is independent of X
(B) f is independent of Y
(C) f is independent of Z
(D) None of X, Y, Z is redundant
Q.21 The point P in the following figure is stuck
at 1. The output f will be
f
A
B
Y  R S  P R  PQ  PQ
P
Z  R  S  PQ  PQ R  PQ S
C
Then
(A) W  Z , X  Z
(A) ABC
(B) A
(B) W  Z , X  Y
(C) A B C
(D) A
(C) W  Y
Q.22 If X = 1 in the logic equation

(D) W  Y  Z
Q.17 The
Boolean
expression
AC  B C
is
equivalent to
(A) A C  B C  AC
(B) B C  AC  B C  A C B
(C) AC  B C  B C  A B C
(D) A B C  A B C  A B C  A B C
Q.18 The simplified form of the Boolean
expression Y  ( A B C  D) ( A D  B C ) can
be written as
  X  Z ( X  Y )  1
 X  Z Y  (Z  X Y ) 


Then
(A) Y = Z
(B) Y  Z
(C) Z = 1
(D) Z = 0
Q.23 The logic gate circuit shown in the figure
realizes the function
X
Z
Y
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
14
(A) XOR
(B) XNOR
(C) Half adder
(D) Full adder
Q.24 The simplified SOP (Sum of product) form
of the Boolean expression
C
A
B
Y
(P + Q + R).(P + Q  R). (P + Q + R) is


(C)  P.Q + R 

(A) P.Q + R
(B) P + Q.R
A
B

(D)  P.Q + R 
(A) Y  A B  A B
(B) Y  A B  A B
(C) Y  A  B
(D) Y  A B
X
Y
f(X,Y)
0
0
0
0
1
0
Q.29 Let  denote the exclusive OR (XOR)
operation. Let ‘1’ and ‘0’ denote the binary
constants. Consider the following Boolean
expression for F over two variables P and Q
F ( P, Q)  ((1  P)  ( P  Q))  (( P  Q)
1
0
1
(Q  0))
1
1
1
Q.25 The truth table
The equivalent expression for F is
Represents the Boolean function
(A) X
(B) X + Y
(C) X  Y
(D) Y
(A) P  Q
(B) P  Q
(C) P  Q
(D) P  Q
Q.30 Consider the following Sum of Products
expression, F.
Q.26 The Boolean expression
(X  Y) (X Y )  (X Y )  X
F  ABC  ABC  ABC  ABC  ABC
simplifies to
(A) X
(B) Y
(C) XY
(D) X + Y
Q.27 The output F in the digital logic circuit
shown in the figure is
The equivalent Product of Sums expression
is
(A) F  ( A  B  C )( A  B  C )( A  B  C )
(B) F  ( A  B  C )( A  B  C )( A  B  C )
(C) F  ( A  B  C )( A  B  C )( A  B  C )
XOR
(D) F  ( A  B  C )( A  B  C )( A  B  C )
X
Y
Q.31 The output of the combinational circuit
given below is
AND
F
Z
XNOR
A
B
C
Y
(A) F  X Y Z  X Y Z
(B) F  X Y Z  X Y Z
(C) F  X Y Z  X Y Z
(D) F  X Y Z  X Y Z
Q.28 In the circuit shown in the figure, if C  0,
the expression for Y is
(A) A + B + C
(B) A (B + C)
(C) B (C + A)
(D) C (A + B)
Q.32 The Boolean expression
(a  b  c  d )  (b  c ) simplifies to
(A) 1
(C) a.b
(B) a.b
(D) 0
GATE ACADEMY®
15
Q.33 The Boolean expression
XY  ( X ' Y ')Z is equivalent to
Boolean Algebra
Q.38 A function F ( A, B , C ) defined by three
Boolean variables A, B and C when
expressed as sum of products is given by
(A) XYZ ' X ' Y ' Z
(B) X ' Y ' Z  XYZ
F  A  B C  A  B C  A B C
(C) ( X  Z )(Y  Z )
where, A, B and C are the complements of
(D) ( X ' Z )(Y ' Z )
the respective variables. The product of sum
(POS) form of the function F is
Q.34 In the digital circuit given below, F is
X
Y
(A) F  ( A  B  C )
( A  B  C )( A  B  C )
F
(B) F  ( A  B  C )
Z
(A) XY  YZ
(B) XY  YZ
(C) XY  YZ
(D) XY  Y
Q.35 The Boolean expression
simplifies to
(A) BC  AC
( A  B  C )( A  B  C )
(C) F  ( A  B  C )( A  B  C )
( A  B  C )( A  B  C )
AB  AC  BC
(A  B  C)
(D) F  ( A  B  C )( A  B  C )
(B) AB  AC  B
(D) AB  BC
Q.36 A and B are the logical inputs and X is the
logical output shown in the figure. The
output X is related to A and B by
( A  B  C )( A  B  C )
( A  B  C)
(C) AB  AC
A
X
Q.39 The equivalent Boolean expression of
(R  T) (R  T) (S  T)  F(R,S, T) is
(A) R T  R ST
(B) R T  R T  ST
(C) R T  R S T
(D) None of these
Q.40 The Boolean expression
equivalent to ________.
B
AB  AC
is
(A) ABC  ABC  ABC
(B) ABC  ABC  ABC  ABC
(A) X  AB  BA
(C) ABC  ABC  ABC
(B) X  AB  BA
(D) None of these
(C) X  AB  B A
Q.41 Minimize the logic expression
(D) X  A B  B A
C  D  AB  A BC  A BC
Q.37 If w, x, y, z, are Boolean variables, then
which
one
of the
following
is
INCORRECT?
(A) wx + w(x + y) + x(x + y) = x + wy
(B) wx  y+z +wx = w+x+yz


(C) wx  y+xz  +wx y = xy
(D) (w + y)(wxy + wyz) = wxy + wyz
(A) C  A B  C D
(B) A B  C D  C
(C) C  D  A B
(D) None of these
Q.42 If A and B are Boolean variables, which one
of the following is equivalent to
A  B  AB
(A) 0
(B) A  B
(C) AB
(D) A  B
GATE ACADEMY®
16
Digital Electronics & Microprocessor 8085 [WB]
Q.43 For the circuit given below, the output Y is
(A) Y0 is independent of ' B '
A
B
(B) Y0 is independent of A
(C) Y0 is dependent of A and B
C
(D) None of the A, B, C is dependent
Y
(A) A  B  C
(B) C
(C) B
(D) AB  BC

Q.44 Which of the following is correct?
A
Y0
B
C
Answer Keys
Objective & Numerical Answer Type Questions
1.
A
2.
D
3.
B
4.
B
5.
B
6.
D
7.
C
8.
A
9.
A
10.
A
11.
B
12.
8
13.
A
14.
B
15.
B
16.
A
17.
B
18.
A
19.
D
20.
A
21.
D
22.
A
23.
A
24.
C
25.
B
26.
A
Practice (Objective & Numerical Answer) Questions
1.
B
2.
B, C
3.
B
4.
A
5.
A
6.
B
7.
B
8.
C
9.
D
10.
B
11.
C
12.
A
13.
C
14.
C
15.
D
16.
A
17.
D
18.
A
19.
D
20.
D
21.
D
22.
D
23.
A
24.
B
25.
A
26.
A
27.
A
28.
A
29.
C
30.
A
31.
C
32.
D
33.
C
34.
B
35.
A
36.
C
37.
C
38.
C
39.
A
40.
B
41.
C
42.
C
43.
B
44.
B
3
K ‐ Maps
Objective & Numerical Ans Type Questions :
Q.1
Q.4
The output expression for the Karnaugh map
shown below is
[GATE 2016, IISc Bangalore]
BC
A
00 01 11 10
0 1 0 0 1
1 1
Q.2
1
1
1
A
B
C
f
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
(A) A  B
(B) A  C
1
0
0
0
(C) A  C
(D) A  C
1
0
1
0
1
1
0
1
1
1
1
0
The output expression for the Karnaugh map
shown below is
[GATE 2017, IIT Roorkee]
(A) B( A  C ) ( A  C )
CD
AB
Q.3
The Boolean expression for the truth table
shown below is
[GATE 2005, IIT Bombay]
00 01 11 10
00 0 0 0 0
01 1 0 0 1
11 1 0 1 1
10 0 0 0 0
(A) BD  BCD
(B) BD  AB
(C) BD  ABC
(D) BD  ABC
(B) B( A  C ) ( A  C )
(C) B ( A  C ) ( A  C )
(D) B ( A  C ) ( A  C )
Q.5
The SOP (sum of products) form of a
Boolean functions is  (0,1, 3, 7,11) , where
Consider the following Boolean function
with four variables
F(w, x, y, z) =  (1, 3, 4, 6, 9, 11, 12, 14).
inputs are A, B, C, D, (A is MSB, and D is
LSB). The equivalent minimized expression
of the function is
[GATE 2014, IIT Kharagpur]
The function is [GATE 2007, IIT Kanpur]
(A) ( B  C ) ( A  C ) ( A  B ) (C  D)
(A) Independent of one variables
(B) Independent of two variables
(B) ( B  C ) ( A  C ) ( A  C ) (C  D)
(C) Independent of three variables
(C) ( B  C ) ( A  C ) ( A  C ) (C  D)
(D) Dependent on all variables
(D) ( B  C ) ( A  B ) ( A  B ) (C  D)
Digital Electronics & Microprocessor 8085 [WB]
Q.6
The Boolean function x ' y ' xy  x ' y is
equivalent to
(A) x ' y '
[GATE 2004, IIT Delhi]
(B) x  y
(C) x  y '
Q.7
(D) x ' y
For the Boolean expression
f  a b c  abc +ab c  abc  abc
f ( A, B, C , D )   M (0, 1, 3, 4, 5, 7,9,11,
12,13,14,15) is a maxterm representation of
Boolean function f (A, B, C, D) where A is
the MSB and D is the LSB. The equivalent
minimized representation of this function is
[GATE 2015, IIT Kanpur]
(A) ( A  C  D)( A  B  D)
(B) ACD  ABD
(A) f  (b  c).(a  c)
(C) ACD  ABCD  ABCD
(D) ( B  C  D)( A  B  C  D)( A  B  C  D)
Q.12 The number of min-terms after minimizing
the following Boolean expression is
__________ .
(C) f  (b  c).(a  c)
(D) f  c  abc
From the table, choose the correct logical
expression for Q.
A
B
C
Q
Q.9
Q.11
the minimized Product of sum (POS)
expression is [GATE 2011, IIT Madras]
(B) f  (b  c).(a  c)
Q.8
GATE ACADEMY®
18
0
0
0
0
[GATE 2000, IIT Kharagpur]
0
0 0 1 1 1 1
0
1 1 0 0 1 1
1
0 1 0 1 0 1
0
0 1 0 1 1 1
(A) AB  BC  CA
(B) A  B  C
(C) AB  BC  CA
(D) AB  BC  CA
 D ' AB ' A ' C  AC ' D  A ' C ' D  '
[GATE 2015, IIT Kanpur]
Q.13 In the Karnaugh map shown below, X
denotes a don’t care term. What is the
minimal form of the function represented by
the Karnaugh map?
[GATE 2008, IISc Bangalore]
ab
cd
The simplified SOP (Sum of Product) form
of the Boolean expression
X
X
 P  Q  R  . P  Q  R  . P  Q  R 
is ___________.


(C)  P.Q  R 
(A) P.Q  R
[GATE 2011, IIT Madras]

(B) P  Q.R

(D)  P.Q  R 
Q.10 Consider the following Boolean expression
for
X
(A) b . d  a . d
(B) a . b  b . d  a . b . d
(C) b . d  a . b . d
(D) a . b  b . d  a . d
Q.14 Given the following Karnaugh map, which
one of the following represents the minimal
Sum - Of - Products of the map?
[GATE 2001, IIT Kanpur]
F : (P, Q, R, S) = PQ + PQR+PQRS
The minimal sum-of-products form of F is
__________.
[GATE 2014, IIT Kharagpur]
(A) PQ + QR + QS (B) P + Q + R + S
(C) P+Q+R+S
(D) P R + PRS  P
wx
00
01
11
10
00
0
x
0
x
01
x
1
x
1
11
0
x
1
0
10
0
1
x
0
yz
GATE ACADEMY®
19
(A) xy + y’z
(B) wx’y’ + xy + xz
(C) w’x + y’z + xy
(D) xz + y
Q.15 The minimal product-of-sums function
described by the K-map given in figure, is
[GATE 2000, IIT Kharagpur]
AB
K ‐ Maps
where d represents the don’t-care condition
in Karnaugh maps. Which of the following
is a minimum product – of – sums (POS)
form of f(w, x, y, z)?
[GATE 2017, IIT Roorkee]
(A) f =  w  z  x  z 
(B) f =  w  z   x  z 
00
01
11
10
(C) f =  w  z   x  z 
0
1
1
f
0
(D) f =  w  z  x  z 
1
0
0
f
0
(A) AC
(B)
AC
(C) A  C
(D)
AC
C
Q.16 Consider the following minterm expression
of
F (P,Q,R,S) =  m (0, 2, 5, 7, 8, 10, 13, 15)
The minterms 2, 7, 8 and 13 are ‘don’t care’
terms. The minimal sum-of-products form
for F is _______.
[GATE 2014, IIT Kharagpur]
(A) QS  QS
(B) QS  QS
f  w,x,y,z  =   0,4,5,7,8,9,13,15  .
Q.19 Let
Which of the following expressions NOT
equivalent to f ?
[GATE 2007, IIT Kanpur]
(A) x'y'z' + w'xy' + wy'z + xz
(B) w'y'z' + wx'y' + xz
(C) w'y'z' + wx'y' + xyz + xy'z
(D) x'y'z' + wx'y' + w'y
Q.20 The number of product terms in the
minimized
sum-of-product
expression
obtained through the following K-map
(where, ‘d’ denotes don’t care states)
[GATE 2005, IIT Bombay]
(C) QRS  QRS  QRS  QRS
(D) PQS  PQS  PQS  PQS
Q.17 Digital input signals A, B, C with A as the
MSB and C as the LSB are used to realize
the Boolean function F  m0  m2  m3
 m5  m7 , where
1
0
0
1
0
d
0
0
0
0
d
1
1
0
0
1
denotes the ith
(A) 2
(B) 3
minterm. In addition. F has a don't care for
m1 . The simplified expression for F is given
(C) 4
(D) 5
by
mi
[GATE 2018, IIT Guwahati]
Q.21 The function represented by the Karnaugh
map given below is
(A) AC  B C  AC
(B) A  C
(C) C  A
[GATE 1998, IIT Delhi]
BC
A
(D) AC  B C  AC
Q.18 Given, f (w, x, y, z) =  m (0, 1, 2, 3, 7, 8,
10) +  d (5, 6, 11, 15)
00
0 1
01
10
0
1
0
0
0
1
11
1
1
(A) A.B
(B) AB + BC + CA
(C) B  C
(D) A.BC
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
20
Q.22 Consider the following expressions :
1. Y  f ( A, B, C , D)  (1, 2, 4, 7,8,11,13,14)
Assume for all inputs (a, b, c, d), the
respective complements  a, b, c, d  are also
2. Y  f ( A, B, C , D)  (3,5, 7,10,11,12,13,14)
available. The above logic is implemented
using 2-input NOR gates only. The
minimum number of gates required is
______.
3. Y  f ( A, B, C , D)   (0,3,5, 6,9,10,12,15)
4. Y  f ( A, B, C , D)   (0,1, 2, 4, 6,8,9,15)
Which of these expressions are equivalents
of the expression Y  A  B  C  D ?
(A) 1 and 2
(B) 1 and 4
(C) 2 and 3
(D) 1 and 3
Q.23 A logic circuit implements the Boolean
function f  x . y  x. y .z . It is found that
the input combination x  y  1 can never
occur. Taking this into account, a simplified
expression for f is given by
[GATE 2007, IIT Kanpur]
(A) x  y .z
(B) x  z
(D) y  x.z
(C) x  y
Q.24 The minimal sum-of-products expression for
the logic function f represented by the
given Karnaugh map is
[GATE 2009, IIT Roorkee]
RS
PQ
00
01
11
10
00
0
1
0
0
01
0
1
1
1
11
1
1
1
0
10
0
0
1
0
Q.26 Following is the K-map of a Boolean
function of five variables P, Q, R, S and X.
The minimum sum-of-product (SOP)
expression for the function is
[GATE 2016, IISc Bangalore]
PQ
00 01 11 10
RS
00 0 0 0 0
PQ
00 01 11 10
RS
00 0 1 1 0
01
1
0
0
1
01
0
0
0
0
11
1
0
0
1
11
0
0
0
0
10
0
0
0
0
10
0
1
1
0
X=0
X=1
(A) P Q S X  P Q S X  Q R S X  Q R S X
(B) Q S X  Q S X
(C) Q S X  Q S X
(D) Q S  Q S
Q.27 The K-map for a Boolean function is shown
in figure below. The number of essential
prime implicants for this function is
_____________.
(A) QS  PRS  PQR  PRS  PQR
CD
00
AB
01
11
10
(B) QS  PRS  PQR  PRS  PQR
00
1
0
1
1
(C) PRS  PQR  PRS  PQR
01
0
1
0
0
(D) PRS  PQR  PRS  PQR
11
0
1
1
0
10
1
0
0
1
Q.25 Consider the Karnaugh map given below,
where X represents “don’t care” and blank
represents 0
[GATE 2017, IIT Roorkee]
ba
dc
Q.28 In the sum of products function
f ( X , Y , Z )  m(2, 3, 4, 5) , the prime
implicants are
[GATE 2012, IIT Delhi]
(A) X Y , X Y
(B) X Y , X Y Z , X Y Z
(C) X Y Z , X Y Z , X Y
(D) X Y Z , X Y Z , X Y Z , X Y Z
GATE ACADEMY®
21
Q.29 The total number of prime implicants of the
function
f (w, x, y, z )  (0, 2, 4, 5, 6, 10)
is______.
K ‐ Maps
Practice (objective & Num Ans) Questions :
Q.1
following expression f  ABC  A B C.
[GATE 2015, IIT Kanpur]
Q.30 Which are the essential prime implicants of
the following Boolean function?
Find the minimum product of sums of the
Q.2
f (a, b, c) = a’c + ac’ + b’c
A combination circuit has inputs A, B and C
and its Karnaugh map is given in figure. The
output of the circuit is
[GATE 2004, IIT elhi]
C
(A) a ' c and ac '
AB
00
0
(B) a ' c and b ' c
1
(C) a ' c only
(D) ac 'and bc '
Q.31 Consider the Boolean function,
F (w, x, y, z )  w y  x y  w x y z
Q.3
w x y  x z  x y z
01
11
1
1
10
1
1
(A) ( AB  AB ) C
(B) ( AB  AB ) C
(C) A  B  C
(D) ABC
What is the equivalent Boolean expression
in product-of-Sums form for the Karnasugh
map given in fig?
AB
Which one of the following is the complete
set of essential prime implicants?
CD
[GATE 2014, IIT Kharagpur]
(A) w, y, x z, x z
(B) w, y , x z
(C) y , x y z
(A) BD  BD
(D) y, x z , x z
(B)  B  C  D  B  C  D 
Q.33 For an n-variable Boolean function, the
maximum number of prime implicants is
(C)  B  D   B  D 
(D)  B  D  B  D 
[GATE 2014, IIT Kharagpur]
(A) 2(n 1)
(C) 2
n
(B) n / 2
(D) 2
Q.4
( n1)
Q.34 By inspecting the Karnaugh map plot of the
switching function
F (x1 , x2 , x3 ) = Σ (1,3, 6, 7)
one can say that the redundant prime
implicant is
Q.5
(B) x2 x3
(D) x3
(A) AC  BD
(B) AC  CD
(C) AC  BD
(D) AB  CD
The minimized form of the logical
expression ( A B C  A B C  A B C  A B C )
is
(A) x1 x3
(C) x1 x2
The minimal sum of products form of
f  ABCD  ABC  BCD  ABC is
Q.6
(A) A C  B C  A B
(B) AC  B C  A B
(C) A C  B C  A B
(D) AC  B C  A B
Which of the following functions
implements the Karnaugh map shown
below?
Digital Electronics & Microprocessor 8085 [WB]
00
01
11
10
(A) PQRS  QS
(B) PQRS  QS
0
0
1
0
(C) PQR  QS
(D) PQRS  Q
01
X
X
1
X
11
0
1
1
0
10
0
1
1
0
CD
AB
00
(B) D  C  A
(A) AB  CD
(C) AD  AB
(D) (C  D ) (C  D ) ( A  B )
Q.7
GATE ACADEMY®
22
Which function does NOT implement the
Karnaugh map given below?
wz
xy
0
x
0
x
0
0
Q.10 The switching expression corresponding to f
(A, B, C, D) =  (1, 4, 5, 9, 11, 12) is
(A) BC ' D ' A ' C ' D  AB ' D
(B) ABC ' ACD  B ' C ' D
(C) ACD ' A ' BC ' AC ' D '
(D) A ' BD  ACD ' BCD '
Q.11 Min-term (Sum of products) expression for a
Boolean function is given as follows.
f ( A, B, C )   m (0,1, 2,3,5, 6)
Where A is the MSB and C is the LSB. The
minimized expression for the function is
(A) A  ( B  C )
(B) ( A  B)  C
(C) A  ( B  C )
Q.12 The
expression
Y  ABC D
0
A BC D ABC D  ABC D
(B) x y + y w
(C)  w+x   w+y  x+y 
minimized to
(A) Y  A B C D  A B C  AC D
(D) None of the above
(B) Y  A B C D  B C D  A B C D
Minimum SOP for f(w, x, y, z) shown in
Karnaugh – map below is
(C) Y  A B C D  B C D  A B C D
x
0
(A) (w + x)y
Q.8
Boolean
(D) ABC
0
can
be
(D) Y  A B C D  B C D  A B C D
Q.13 The minimum sum of products form of the
Boolean expression
y  P Q R S  P Q R S  P Q R S P Q R S
 P Q R S  P Q R S is
Q.9
(A) x z + y’ z
(B) x z’ + z x’
(C) x’ y + z x’
(D) None
The Karnaugh map for a four variable
Boolean function is given below. The
correct Boolean sum of product is
RS
PQ
00
01
11
10
00
0
0
0
0
01
1
0
0
1
11
1
0
0
1
10
0
1
0
0
(A) y  PQ  QS
(B) y  PQ  QRS
(C) y  PQ  Q R S
(D) y  QS  PQR
Statement for Linked Answer
Questions 14 & 15
The following Karnaugh map represents a functions
F
F
X
YZ
00
01
11
10
0
1
1
1
0
1
0
0
1
0
GATE ACADEMY®
23
Q.14 A minimized form of the function F is
(A) F  X Y  Y Z
(B) F  X Y  Y Z
(C) F  X Y  Y Z
(D) F  X Y  Y Z
K ‐ Maps
C
AB
0
1
Q.15 Which of the following circuits is a
realization of the above functions F?
(A)
(A)
00
01
1
1
1
11
10
1
A
X
B
C
F
Y
(B)
Z
(B)
A
X
B
C
F
Y
Z
(C) A
(C)
X
F
Y
C
Z
B
(D)
(D) A
X
C
F
Y
Z
B
Q.16 What is the minimal form of the Karnaugh
map shown below? Assume that X denotes a
don’t care term.
ab
cd
X
X
X
X
(A) bd
(B) bd  bc
(C) bd  abcd
(D) bd  bc  cd
Q.17 Which of the following logic circuits is a
realization of the function F whose
Karnaugh map is shown in figure
Q.18 The total number of prime implicants of the
function f (w, x, y, z) =  (0, 2, 4, 5, 6, 10)
is _______.
Q.19 Which one of the following gives the
simplified sum of products expression for
the Boolean function
F  m0  m2  m3  m5
where, m0 , m2 , m3 and m5 are minterms
corresponding to the inputs A, B and C with
A as the MSB and C as the LSB?
(A) AB  ABC  ABC
(B) AC  AB  ABC
(C) AC  AB  ABC
(D) ABC  AC  ABC
Digital Electronics & Microprocessor 8085 [WB]
Q.20 Given
GATE ACADEMY®
24
Q.25 What is the minimized expression of given
f ( w, x, y, z)   m  0,1, 2,3, 7,8,10  
f ( A, B, C , D)   m(0,1, 2,3, 4,5)
 (5, 6,11,15)
  d (10,11,12,13,14,15)
d
where d represents the don’t-care condition
in Karnaugh maps. Which of the following
is a minimum product-of-sums (POS) form
of f ( w, x, y, z) ?
(A) f  ( w  z )( x  z )
(C) f  ( w  z )( x  z )
(D) f  ( w  z )( x  z )
Q.21 The Boolean expression equivalent to
ABC  ABC  ABC  ABC is
(A) AC  BC
(B) AB  AC
(C) AB  BC
(D) AC  BC
Q.22 A Boolean function is given by
m(0,1, 2, 4,5, 7) , the number essential
prime implicants is
(A) 2
(B) 3
(C) 4
(D) 5
Q.23 Find the number of Prime implicants and
Essential prime implicants in the given Kmap.
RS
PQ 00 01 11 10
00 1
1
1
1
1
11 1
10
(A) 4.5
(B) 0.6
(C) 6.0
(D) 6.6
Q.24 The simplified form of SOP form
f ( PQRS )   m(0,1, 2,3,5,8,10,11,13,15)
 d (4, 6, 7,12,14) is
(A) P  Q  R  S
(B) P  Q  R  S
(C) P  Q  R  S
(D) P  Q  R  S
(B) A  BC
(C) A( B  C )
(D) A( B  C )
Q.26 A function is represented by
f ( A, B, C , D)   m(0, 2, 4,5, 6, 7,8,10,13,15)
The number of prime implicant and essential
prime implicant are respectively
(B) f  ( w  z )( x  z )
01
(A) A  BC
(A) 4 and 3
(B) 4 and 4
(C) 4 and 2
(D) 2 and 2

GATE ACADEMY®
25
K ‐ Maps
Answer Keys
Objective & Numerical Answer Type Questions
1.
B
2.
D
3.
B
4.
A
5.
A
6.
D
7.
A
8.
A
9.
B
10.
A
11.
C
12.
1
13.
A
14.
A
15.
A
16.
B
17.
B
18.
A
19.
D
20.
A
21.
C
22.
D
23.
D
24.
D
25.
1
26.
B
27.
4
28.
A
29.
3
30.
A
31.
D
32.
D
33.
B
Practice (Objective & Numerical Answer) Questions
*1.
1.
*
2.
C
3.
C
4.
B
5.
A
6.
B
7.
D
8.
B
9.
B
10.
A
11.
C
12.
D
13.
A
14.
B
15.
D
16.
B
17.
C
18.
3
19.
B
20.
A
21.
D
22.
B
23.
D
24.
B
25.
C
26.
C
f  ( B  C ) ( A  B) ( A  C )
4
Number System, Binary
Codes & Complement Form
(224) r  (13) r , what is the value of
Objective & Numerical Ans Type Questions :
Q.9
Number System and Binary Codes
the radix r ? _____________.
Q.10 Consider the equation 1235   x8  y with
Q.1
Q.2
Q.3
Q.4
Q.5
The decimal equivalent of binary number
10110.11 is
(A) 16.75
(B) 20.75
(C) 16.50
(D) 22.75
Hexadecimal conversion of decimal number
227 will be
(A) A3
(B) E3
(C) CC
(D) C3
The octal equivalent of HEX number
AB  CD is
(A) 253.314
(B) 253.632
(C) 526.314
(D) 526.632
The number of digit 1 present in the binary
representation of 3  512  7  64  5  8  3 is
_____________.
How many 1's are present in the binary
Representation of
(4 1096)  (9  256)  (7 16)  5 ?
Q.6
___________.
If (2.3) base4 + (1.2) base4 = (y)base4 ; What is the
Q.7
value of y? ____________________.
Given (135)base x  (144)base x  (323)base x .
Q.8
What is the value of base x ? __________.
The base of the number system for the
addition operation 24  14  41 is_____.
[GATE 2011, IIT Madras]
When
x and y as unknown. The number of
possible solutions is _____________ .
[GATE 2011, IIT Madras]
Q.11 Consider the equation  43 x   y38 where x
and y are unknown. The number of possible
solutions is __________.
[GATE 2015, IIT Kanpur]
Q.12 Decimal 43 in Hexadecimal and BCD
number system is respectively
[GATE 2005, IIT Bombay]
(A) B2, 01000011
(B) 2B, 01000011
(C) 2B, 0011 0100
(D) B2, 01000100
Q.13 Which of the following is an invalid state in
8 4 2 1 Binary Coded Decimal counter
[GATE 2014, IIT Kharagpur]
(A) 1000
(B) 1001
(C) 0011
(D) 1100
Q.14 A new Binary Coded Pentary (BCP) number
system is proposed in which every digit of a
base-5 number is represented by its
corresponding 3-bit binary code. For
example, the base-5 number 24 will be
represented by its BCP code 010100. In this
numbering system, the BCP code
100010011001 corresponds to the following
number in base-5 system
[GATE 2006, IIT Kharagpur]
GATE ACADEMY®
27
(A) 423
(C) 2201
(B) 1324
(D) 4231
Number System, Binary Codes
Q.5
Complement Form
Q.1
Q.2
11001, 1001 and 111001 correspond to the
2's complement representation of which one
of the following sets of number?
[GATE 2004, IIT Madras]
(A) 25, 9 and 57 respectively.
(B) – 6, – 6 and – 6 respectively.
(C) – 7, – 7 and – 7 respectively.
(D) – 25, – 9 and – 57 respectively.
A number in 4-bit two’s complement
representation is X 3 X 2 X 1 X 0 . This number
when stored using 8 – bits will be
[GATE 1999, IIT Bombay]
(A) 0000X 3 X 2 X 1 X 0
Q.6
Q.7
a0
a3
a2
a1
a0
1
The value of the bit pattern in 2’s
complement representation is given terms of
the original number is N as
[GATE 2006, IIT Kharagpur]
Q.4
An 8085 microprocessor executes the
following instructions :
(A) 100000111
(B) 00000111
(C) 11111001
(D) 011111001
The 16-bit 2’s complement representation of
an integer is 1111 1111 1111 0101; its
decimal representation is
Let X be the number of distinct 16-bit
integers in 2’s complement representation.
Let Y be the number of distinct 16-bit
integers in sign magnitude representation.
Then X  Y is _____
[GATE 2016, IISc Bangalore]
It is copied into a 6-bit register and after a
few operations the final bit pattern is
a3
(D) 11011011
If Q is subtracted from P, the value obtained
in signed2’s complement form is
A number N is stored in a 4-bit 2’s
complement representation as
a1
(C) 11010111
P = 11101101 and Q = 11100110
Q.8
(D) X 3 X 3 X 3 X 3 X 3 X 2 X 1 X 0
a2
(B) 11100100
[GATE 2016, IISc Bangalore]
(C) X 3 X 3 X 3 X 3 X 3 X 2 X 1 X 0
a3
(A) 11100111
Two numbers are represented in signed 2’s
complement form as
(B) 1111X 3 X 2 X 1 X 0
Q.3
Assuming all numbers are in 2’s
complement representation, which of the
following numbers is divisible by
11111011?
[GATE 2003, IIT Madras]
(A) 32a3  2 N  1
(B) 32a3  2 N  1
(C) 2 N  1
(D) 2 N  1
Let A = 1111 1010 and B = 0000 1010 be
two 8 –bit 2’s complement numbers. Their
product in 2’s complement is
[GATE 2004, IIT Madras]
(A) 1100 0100
(B) 1001 1100
(C) 1010 0101
(D) 1101 0101
Q.9
Two 2's complement numbers having sign
bits ‘x’ and ‘y’ are added and the sign bit of
the result is ‘z’. Then, the occurrence of
overflow is indicated by the Boolean
function
[GATE 1998, IIT Delhi]
(A) x y z
(B) x y z
(C) x y z  x y z
(D) xy  yz  zx
Q.10 When two 8-bit numbers A7 ........... A0 and
B7 ...........B0
in
2’s
complement
representation (with A0 and B0 as the least
significant bits) are added using a ripplecarry adder, the sum bits obtained are
S7 ...........S0 and the carry bits are
C7 ...........C0 . An overflow is said to have
occurred if
[GATE 2017, IIT Roorkee]
Digital Electronics & Microprocessor 8085 [WB]
(A) The carry bit C7 is 1
GATE ACADEMY®
28
Q.4
(A) Sign magnitude
(B) All the carry bits ( C7 ...........C0 ) are 1
(C)  A7 . B7 . S 7  A7 . B 7 . S7  is 1
(B) 1’s complement
(D)  A0 .B0 .S 0  A0 .B 0 .S0  is 1
(D) None of the above
Q.11 Assuming all numbers in 2’s complement
form, which of the following additions will
result in overflow?
(A) 1100 + 1100
(B) 0011 + 0111
(C) 1111 + 0111
(D) All of the above
(C) 2’s complement
Q.5
Q.6
Practice (objective & Num Ans) Questions :
Q.1
Q.2
2's complement representation of a 16-bit
number (one sign bit and 15 magnitude bits)
is FFFF. Its magnitude in decimal
representation is
(A) 0
(B) 1
(C) 32,767
(D) 65,535
Q.7
Q.8
The result of (45)10  (45)16 expressed in 2’s
complement representation is
Q.3
Zero has two representations in :
(A) 011000
(B) 100111
(C) 101000
(D) 101001
A signed integer has been stored in a byte
using the 2's complement format. We wish
to store the same integer in a 16 bit word.
We should
(A) copy the original byte to the less
significant byte of the word and fill the
more significant byte with zeros.
(B) copy the original byte to the more
significant byte of the word and fill the
less significant byte with zeros.
(C) copy the original byte to the less
significant byte of the word and make
each bit of the more significant byte
equal to the most significant bit of the
original byte.
(D) copy the original byte to the less
significant bytes well as the more
significant byte of the word.
Q.9
The number 43
representation is
in
2’s
complement
(A) 01010101
(B) 11010101
(C) 00101011
(D) 10101011
The 2 's
–17 is
complement representation of
(A) 101110
(B) 101111
(C) 111110
(D) 110001
4-bit 2's complement representation of a
decimal number is 1000. The number is
(A) +8
(B) 0
(C) – 7
(D) – 8
The 2’s complement representation of the
decimal value – 15 is
(A) 1111
(B) 11111
(D) 111111
(C) 10001
The range of signed decimal numbers that
can be represented by 6-bit 1's complement
number is
(A) – 31 to + 31
(B) – 63 to + 63
(C) – 64 to + 63
(D) – 32 to + 31
Q.10 If 73x (in base - x number system) is equal
to 54 y (in base - y number system), the
possible values of x and y are
(A) 8, 16
(B) 10, 12
(C) 9, 13
(D) 8, 11
Q.11 An 8-bit 2’s complement representation of
an integer is FA (Hex). Its decimal
equivalent is
(A) 10
(B)  6
(C)  6
(D)  10
Q.12 The range of integers that can be represented
by an n bit 2’s complement number system
is
GATE ACADEMY®
29
(A) 2n 1 to   2n 1  1
Q.21 If (11X1Y)8  (12C9)16 then the values X
(B)   2n 1  1 to  2n 1  1
(C) 2n 1 to 2n 1
(D)   2n 1  1 to  2n 1  1
Q.13 The hexadecimal representation of 6578 is
(A) IAF
(B) D78
(C) D71
(D) 32F
Q.14 The binary representation of the decimal
number 1.375 is
(A) 1.111
(B) 1.010
(C) 1.011
(D) 1.001
Q.15
Number System, Binary Codes
(1217)8 is equivalent to
and Y are
(A) 5 and 1
(B) 5 and 7
(C) 7 and 5
(D) 1 and 5
Q.22 What are the values respectively of R1 and
R2
in the expression
 235R   56510
1
  865 R ?
2
(A) 8, 16
(B) 16, 8
(C) 6, 16
(D) 12, 8
Q.23 Consider the following multiplication :
(10w1z)2  (15)10  ( y 01011001) 2
(A) (1217)16
(B) (028 F )16
Which one of the following
appropriate values of w, y and z?
(C) (2297)10
(D) (0 B17)16
(A) w = 0, y = 0, z = 1
Q.16 The smallest integer that can be represented
by an 8 – bit number in 2’s complement
form is
(A) – 256
(B) – 128
(C) – 127
(D) 0
Q.17 The representation of the decimal number
(27.625)10 in base-2 number system is
(A) 11011.110
(B) 11101.101
(C) 11011.101
(D) 10111.110
Q.18 The number of 1 in 8-bits representation of
127 in 2’s complement form is m and that
in 1‘s complement form is n. What is the
value of m:n?
(A) 2 : 1
(B) 1 : 2
(C) 3 : 1
(D) 1 : 3
Q.19 A gray code is a/an :
(A) Binary weighted code
(B) Arithmetric code
(C) Code which exhibits a single bit change
between two successive codes
(D) Alphanumeric code
Q.20 Which of the following is a selfcomplementing code ?
(A) 8421 code
(B) Excess 3 code
(C) Pure binary code (D) Gray code
gives
(B) w = 0, y = 1, z = 1
(C) w = 1, y = 1, z = 1
(D) w = 1, y = 1, z = 0
Q.24 The maximum positive and negative
numbers that can be represented in 1’s
complement using n-bits are respectively
(A)  (2n 1  1) and  (2n 1  1)
(B)  (2n 1  1) and  (2n 1 )
(C)  (2n 1 ) and  (2n 1  1)
(D)  (2n 1  1) and  (2n 1 )
Q.25 The maximum positive and negative number
that can be represented in 2’s complement
using n-bits are respectively
(A)  (2n 1  1) and  (2n 1  1)
(B)  (2n 1  1) and  (2n 1 )
(C)  (2n 1 ) and  (2n 1  1)
(D)  (2n 1  1) and  (2n 1 )
Q.26 The range of numbers that can be
represented in 2’s complement mode with
four binary digits is
(A)  15 to + 15
(B)  8 to + 8
(C)  8 to + 7
(D)  7 to + 7
Digital Electronics & Microprocessor 8085 [WB]
Q.27 2’s complement number is 1001. Its
equivalent representation in 8 bit format is
______.
(A) 00001001
(B) 10011001
(C) 11111001
(D) None
Q.28 The range of signed decimal numbers that
can be represented by 8 bit 1’s complement
number is _______.
Q.29
(A) –127 to +127
(B) –128 to +128
(C) –256 to +256
(C) –256 to +127
(98)10  (1D)16  (72)8  (1011) 2 
(A) (314)8
(B) (B4)16
(C) (194)10
(D) None of these
Q.30 If (212) x  (153)8 then the base x is _____
Q.31 The minimum of bits required to represent 32 in 2’s complement representation is
_____.
Q.32 The 2’s complement representation of
(89)10 is
(A) 10100110
(B) 01011101
(C) 10100010
(D) 10100111
Q.33 The two numbers represented in signed 2’s
complement form are A  11101001 and
B  11100101 . If B is subtracted from A,
the value obtained in signed 2’s complement
form is
(A) 11111001
(B) 00000100
(C) 11000100
(D) 10000100
Q.34 A number system is represent by
(54)b  (13)b  (4)b the base of the number is
________?
Q.35 The addition of 4 bit two’s complement
binary number 1111 and 0010 results
(A) 0001 and an overflow
(B) 1001 and no overflow
(C) 0001 and no overflow
(D) 1001 and an overflow
30
GATE ACADEMY®
Q.36 The addition of two number 24 and 13, in
base 5 is _______.
Q.37 The base of the number system for the
addition 34  14  103 is _______.
Q.38 Convert given hexadecimal code into octal
code (CAFB )16 ?

GATE ACADEMY®
31
Number System, Binary Codes
Answer Keys
Objective & Numerical Answer Type Questions
Number System and Binary Codes
1.
D
2.
B
3.
*
4.
9
5.
8
6.
10.1
7.
6
8.
7
9.
5
10.
3
11.
5
12.
B
13.
D
14.
D
Complement Form
1.
C
2.
C
3.
D
4.
A
5.
A
6.
B
7.
–11
8.
1
9.
C
10.
C
11.
B
Practice (Objective & Numerical Answer) Questions
1.
B
2.
C
3.
C
4.
A, B
5.
C
6.
B
7.
D
8.
D
9.
A
10.
D
11.
B
12.
A
13.
A
14.
C
15.
B
16.
B
17.
C
18.
A
19.
C
20.
B
21.
*
22.
B
23.
C
24.
A
25.
B
26.
C
27.
C
28.
A
29.
D
30.
7
31.
6
32.
D
33.
B
34.
8
35.
C
36.
42
37.
5
38.
(145373)8
5
Combinational Circuits
Objective & Numerical Ans Type Questions :
Q.3
Multiplexer :
Q.1
The Boolean function realized by the logic
circuit shown is
[GATE 2010, IIT Guwahati]
C
I0
D
I1
4 ´1
The output F of the multiplexer circuit
shown below expressed in terms of the input
P, Q and R is
[GATE 2008, IISc Bangalore]
R
R
R
R
P
Q
S1
S0
(A) F  P  Q  R
A
B
(A) F  m (0,1,3,5,9,10,14)
(B) F = PQ + QR + RP
(C) F  ( P  Q) R
(B) F  m (2,3,5, 7,8,12,13)
(D) F  ( P  Q) R
I3
(C) F  m (1, 2, 4,5,11,14,15)
Q.4
(D) F  m (2,3,5, 7,8,9,12)
The logic function implemented by the
circuit below is (ground implies a logic “0”)
[GATE 2011, IIT Madras]
A 4  1 MUX is used to implement a 3-input
Boolean function as shown in figure. The
Boolean functions F ( A, B, C ) implemented
is
[GATE 2006, IIT Kharagpur]
A
I0
I0
I1
I1
(A) F = AND (P, Q)
(B) F = OR (P, Q)
(C) F = XNOR (P, Q)
(D) F = XOR(P, Q)
F
F ( A, B, C , D)
MUX
I2
Q.2
I0
I1
MUX Y
I2
I3 S
S0
1
4 ´1
F
I2
MUX
I3
S1
S0
P
Q
F (A, B, C)
'1'
I2
'0'
I3 S
1
S0
B
C
(A) F ( A, B, C )  (1, 2, 4, 6)
(B) F ( A, B, C )  (1, 2, 6)
(C) F ( A, B, C )  (2, 4,5, 6)
(D) F ( A, B, C )  (1,5, 6)
GATE ACADEMY®
Q.5
33
Combinational Circuits
Consider the following circuit which uses a
2-to-1 multiplexer as shown in the figure
below. The Boolean expression for output F
in terms of A and B is
[GATE 2016, IISc Bangalore]
X
I0
0
I1
X
I2
1
I3
4 to 1
MUX
F (X, Y, Z)
0
Y
F
Y
1S
A
Q.6
B
Q.8
(A) A  B
(B) A  B
(C) A  B
(D) A  B
Z
(A)  m (2,3, 4, 7)
(B)  m (1,3,5, 7)
(C)  m (0, 2, 4, 6)
(D)  m (2,3,5, 6)
The output F of the 4 to 1 MUX shown in
figure is
[GATE 2001, IIT Kanpur]
3
+ 5V
For the circuit shown in the following
figure, I 0 - I 3 are inputs to the 4 : 1
2
4:1
MUX
1
multiplexer. R (MSB) and S are control bits.
F
0 S1 S0
[GATE 2008, IISc Bangalore]
P
P
I2
Q
P
P
Q
4:1
MUX
I1
Z
I0
Q.9
(A) x y  x
(B) x  y
(C) x  y
(D) x y  x
Consider the circuit in figure shown. It
implements
[GATE 1996, IISc Bangalore]
C
0
The output Z can be represented by,
C
1
(A) P Q  P Q S  Q R S
C
2
C
3
R
S
(B) P Q  P Q R  P Q S
4 to 1
Multiplex
(C) P Q R  P Q R  P Q R S  Q R S
(D) P Q R  P Q R S  P Q R S  Q R S
Q.7
y
x
I3
A 4 to 1 multiplexer to realize a Boolean
function F ( X , Y , Z ) is shown in the figure
blow. The inputs Y and Z are connected to
the selectors of the MUX (Y is more
significant). The canonical sum-of-product
expression for F ( X , Y , Z ) is
[GATE 2016, IISc Bangalore]
S1
S0
A
R
B
f
(A) ABC  ABC  ABC
(B) A + B + C
(C) A  B  C
(C) AB + BC + CA
Q.10 An 8 to 1 multiplexer is used to implement a
logical function Y as shown in the figure.
The output Y is given by
[GATE 2014, IIT Kharagpur]
Digital Electronics & Microprocessor 8085 [WB]
0
D
0
D
0
0
1
0
I0
I1
I2
I3
I4
I5
I6
I7
GATE ACADEMY®
34
Z
8:1
MUX
Z
Y
S2
S1
S0
A
B
C
X
MUX
X
(D) Y  A B C  A B C
Q.11 Consider the 4-to-1 multiplexer with two
select lines S1 and S0 given below
1
1
4-to1
2 Multiplexer
R
3
S
0
F0
S
Y
(C) Y  A B C  A C D
R
0
1
(B) Y  A B C  A B D
0
F1
MUX
(A) Y  A B C  AC D
0
1
F
(A) ( X  Y )  Z
(B) ( X  Y )  Z
(C) ( X  Y )  Z
(D) ( X  Y )  Z
Q.13 In the following circuit, X is given by
[GATE 2007, IIT Kanpur]
I0
I1 4-to-1
I2 MUX
I3 S1 S0
0
1
1
0
A
SS1 SS 0
I0
I1 4-to-1
I2 MUX
I3 S1 S0
0
1
1
0
B
X
C
(A) X  A B C  A B C  A B C  A B C
(B) X  A B C  A B C  A B C  A B C
PP
OQ
The minimal sum-of-products form of the
Boolean expression for the output F of the
multiplexer is
[GATE 2014, IIT Kharagpur]
(A) PQ  QR  PQR
(B) PQ  PQR  PQR  PQR
(C) PQR  PQR  QR  PQR
(D) PQR
(C) X  A B  B C  AC
(D) X  A B  B C  A C
Q.14 Consider the circuit shown below. The
output of a 2: 1 Mux is given by the function
(ac’ + bc).
1
0
a
b
a
2:1
Mux
g
c
x1
Q.12 A MUX circuit shown in the figure below
implements a logic function. The correct
expression for F1 is
[GATE 2007, IIT Kanpur]
b
2:1
Mux
f
c
x2
Which of the following is true?
[GATE 2001, IIT Kanpur]
(A) f = x1’ + x2
(B) f = x1’ x2 + x1x2’
(C) f = x1 x2 + x1’x2’
(D) f = x1 + x2’
GATE ACADEMY®
35
Q.15 A combinational circuit using an 8 to 1
multiplexer is shown in the following figure.
The minimized expression for the output (Z)
is
[GATE 2006, IIT Kharagpur]
I0
I1
I2
1
1
1
0
0
0
1
0
Y
I3
I4
I5
I6
I7
Z
Combinational Circuits
x
I0
I1
y
I2
4 to 1
Multiplexer
I3
A1
z
OUTPUT
F ( x, y , z ) = ?
A0
EN
The function f (x,y,z) implemented by the
above circuit is
MUX
(MSB)
(LSB)
(B) C ( A  B)
(C) C  A B
(D) C  AB
(B) xy  z
(C) x  y
(D) None of the above
Q.18 A 2-to-1 digital multiplexer having a
switching delay of 1 s is connected as
shown in figure. The output of the
multiplexer is tied to its own select input S.
The inputs which gets selected when S  0
is tied to 1 and the input that goes selected
when S  1 is tied to 0. The output V0 will
A B C
Select Inputs
(A) C ( A  B )
(A) xy z
Q.16 In the TTL circuit shown, S2 to S0 are
1
and X 0 are LSBs. The output Y is
[GATE 2003, IIT Madras]
be
selection lines and X 7 to X 0 input lines. S0
S=0
V0
[GATE 2001, IIT Kanpur]
1
0
0
X 0 X1 X 2 X 3 X 4 X 5 X 6 X 7
E
C
B
A
S
8:1
MUX
S2
S1
S0
Y
(A) Indeterminate
(B) A  B
(C) A  B
(D) C ( A  B)  C ( A  B)
Q.17 Consider the following multiplexer where
I 0 , I1 , I 2 , I 3 , are four data input lines selected
by two address line combinations
S=1
(A) 0
(B) 1
(C) pulse train of frequency 0.5 MHz
(D) pulse train of frequency 1.0 MHz
Q.19 For the circuit shown in the figure, the
delays of NOR gates, multiplexers and
inverters are 2 ns, 1.5 ns and 1 ns,
respectively. If all the inputs P, Q, R, S and
T are applied at the same time instant, the
maximum propagation delay (in ns) of the
circuit is __________.
[GATE 2016, IISc Bangalore]
P
A1
Q
A0  00, 01,10,11 respectively and f is the
R
output of the multiplex (or). EN is the
Enable input.
[GATE 2002, IISc Bangalore]
S
T
0
0
MUX
1
S0
MUX
1
S0
Y
Digital Electronics & Microprocessor 8085 [WB]
Q.20 What are the minimum number of 2 to 1
multiplexers required to generate a 2-input
AND gate and a 2-input EX-OR gate?
[GATE 2009, IIT Kanpur]
(A) 1 and 2
(B) 1 and 3
(C) 1 and 1
(D) 2 and 2
Q.21 Without any additional circuitry, an 8:1
MUX can be used to obtain
[GATE 2009, IIT Kanpur]
(A) some but not all Boolean functions of 3
variables.
(B) all functions of 3 variables but none of 4
variables.
(C) all functions of 3 variables and some but
not all of 4 variables.
(D) all functions of 4 variables.
Q.22 A Boolean function f (A, B, C, D) =  M (1,
5, 12, 15) is to be implemented using an 8 ×
1 multiplexer (A is MSB). The inputs ABC
are connected to the select input S 2 S1 S0 of
the multiplexer respectively. Which one of
the following options gives the correct
inputs to pins 0, 1, 2, 3, 4, 5, 6, 7 in order?
[GATE 2015, IIT Kanpur]
0
1
2
3
4
5
6
7
f ( A, B, C , D)
S2
A
S1
B
GATE ACADEMY®
36
(A) 2n line to 1 line
(B) 2n1 line to 1 line
(C) 2n1 line to 1 line
(D) 2n 2 line to 1 line
Q.24 Consider a multiplexer with X and Y as data
inputs and Z as control input. If z = 0 selects
input x, and z = 1 selects input Y. What are
the connections required to realize the 2variable Boolean function f = T + R without
using any additional Hardware?
[GATE 2004, IIT Delhi]
(A) R to X, 1 to Y, T to Z
(B) T to X, R to Y, T to Z
(C) T to X, R to Y, O to Z
(D) R to X, O to Y, T to Z
Q.25 The minimum number of 2 to 1 multiplexers
required to realize a 4 to 1 multiplexer is
(A) 1
(C) 3
Decoder :
Q.1
A 3 line to 8 line decoder, with active low
outputs, is used to implement a 3 variable
Boolean functions as shown in the figure.
Z
A0
Y
A1
S0
C
(A) D, 0, D, 0, 0, 0, D, D
[GATE 2004, IIT Delhi]
(B) 2
(D) 4
3´ 8
Decoder
0
1
2
3
4
f
5
X
A2
6
7
(B) D, 1, D, 1, 1, 1, D, D
The simplified form of Boolean function
F ( X , Y , Z ) implemented in ‘Product of
(C) D, 1, D, 1, 1, 1, D, D
Sum’ form will be
(D) D, 0, D, 0, 0, 0, D, D
Q.23 Suppose only one multiplexer and one
inverter are allowed to be used to implement
any Boolean function of n variables. What is
the minimum size of the multiplexer
needed?
[GATE 2007, IIT Kanpur]
[GATE 2008, IISc Bangalore]
(A) ( X  Z ).( X  Y  Z ).(Y  Z )
(B) ( X  Z ).( X  Y  Z ).(Y  Z )
(C) ( X  Y  Z ).( X  Y  Z ).
( X  Y  Z ).( X  Y  Z )
GATE ACADEMY®
37
Combinational Circuits
P
Q
(D) ( X  Y  Z ).( X  Y  Z ).
( X  Y  Z ).( X  Y  Z )
Q.2
The functionality implemented by the circuit
below is
[GATE 2016, IISc Bangalore]
1E
2-to-4
Decoder
1Y0
Y0
1Y1
Y1
1Y2
Y2
R
1 A0
S
1 A1
1Y3
Y3
2E
2Y0
Y4
2Y1
Y5
2Y2
Y6
2Y3
Y7
P
Q
R
S
Y
2 A0
2 A1
O0
C1
C0
2:4
Decoder
O1
(A) S 2 , Din , S0 , S1
O2
(B) S1 , Din , S0 , S 2
O3
(C) Din , S0 , S1 , S 2
(D) Din , S 2 , S0 , S1
Enable = 1
Comparator :
is a tristate buffer
Q.1
(A) 2-to-1 multiplexer.
(C) 7-to-1 multiplexer.
(D) 6-to-1 multiplexer.
Q.4
Let X 1 X 0 and Y1Y0 unsigned 2-bit numbers.
The function F  1 if X  Y and F  0
otherwise. The minimized sum of products
expression for F is
[GATE 2007, IIT Kanpur]
(B) 4-to-1 multiplexer.
Q.3
2-to-4
Decoder
How many 3-to-8 line decoders with an
enable input are needed to construct a 6-to64 line decoder without using any other
logic gates? [GATE 2007, IIT Kanpur]
(C) Y1. X 1  Y0 . X 1. X 0  Y1.Y0 . X 0
(A) 7
(B) 8
(D) X 1.Y1  X 0 .Y0Y1  X 0 . X 1.Y0
(C) 9
(D) 10
(A) Y1.Y0  X 0 .Y0  X 1. X 0 .Y1
(B) X 0 .Y1  Y1.Y0  X 1. X 0
Q.2
A 1 to 8 demultiplexer with data input Din ,
address inputs S0 , S1 , S 2 (with S0 as the
LSB)
and
to
Y0
Y7
as
the
eight
demultiplexed outputs, is to be designed
using two 2 to 4 decoders (with enable E
and address inputs A0 and A1 ) as shown in
the figure Din , S0 , S1 and S 2 are to be
connected to P, Q, R
and S
but not
necessarily in this order. The respective
input connections to P, Q, R and S
terminals should be
[GATE 2015, IIT Kanpur]
The output Y of a 2-bit comparator is logic 1
whenever the 2-bit input A is greater than
the 2-bit input B. The number of
combinations for which the output is logic 1,
is
[GATE 2012, IIT Delhi]
(A) 4
(B) 6
(C) 8
(D) 10
Adder :
Q.1
In a half-subtractor circuit with X and Y as
inputs, the Borrow (M) and Difference
( N  X  Y ) are given by
[GATE 2014, IIT Kharagpur]
(A) M  X  Y , N  XY
(B) M  X Y , N  X  Y
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
38
Q.4
(C) M  X Y , N  X  Y
A 1 bit full adder takes 20 ns to generator
carry-out bit and 40 ns for the sum bit. What
is the maximum rate of addition per second
when four 1-bit full adders are cascaded ?
(D) M  X Y , N  X  Y
Q.2
In the given circuit of figure, A, B and C are
the inputs and P, Q are the two outputs. The
circuit is a
[GATE 2004, IIT Delhi]
A B C
Q.5
(A) 107
(B) 1.25 107
(C) 6.25 106
(D) 105
A 16 bit ripple carry adder is realized using
16 identical full adders (FA) as shown in the
figure. The carry-propagation delay of each
FA is 12 ns and the sum-propagation delay
of each FA is 15 ns. The worst case delay
(in ns) of this 16-bit adder will be_______.
Q
[GATE 2016, IISc Bangalore]
A0
P
(A) Half adder where P is the sum and Q is
the carry.
(B) Half adder where P is the carry and Q is
the sum.
(C) Full adder where P is the sum and Q is
the carry.
(D) Full adder where P is the carry and Q is
the sum.
The circuit shown in figure has 4 boxes each
described by inputs P, Q, R and output Y, Z
with
Y  PQ R
Q.3
B0
FA0
Q
P Q
Z
R
P Q
Z
R
P Q
Z
R
Y
Y
Y
Y
(A) 4 bit adder giving P + Q
(B) 4 bit subtractor giving P – Q
(C) 4 bit subtractor giving Q – P
(D) 4 bit adder giving P + Q + R
FA1
A14 B14
C1
FA14
S1
A15 B15
C14
S14
FA15
C15
S15
A half adder is implemented with XOR and
AND gates. A full adder is implemented
with two half adders and one OR gate. The
propagation delay of an XOR gate is twice
that of an AND/OR gate. The propagation
delay of an AND/OR gate is 1.2
microseconds. A 4-bit ripple- carry binary
adder is implemented by using four full
adders. The total propagation time of this 4bit binary adder in microseconds is
_______.
[GATE 2015, IIT Kanpur]
Q.7
Figure-I shows a 4-bit ripple carry adder
realized using full adders and figure-II
shows the circuit of a full adder (FA). The
propagation delay of the XOR, AND and
OR gates in figure II are 20 ns, 15 ns and 10
ns, respectively. Assume all the inputs to the
4-bit adder are initially reset to 0.
Y3
Output
B1
Q.6
P
P Q
Z
R
C0
S0
Z  RQ  R P Q P
The circuit acts as a
[GATE 2003, IIT Madras]
A1
Z4
FA
S3
X3
Y2
Z3
FA
X2
Y1
Z2
S2
X1
FA
S1
Fig. I
Y0
Z1
X0
FA
S0
Z0
GATE ACADEMY®
39
Combinational Circuits
Xn
P P
Q Q
R R
Sn
Yn
F
Z n+1
Zn
Fig. II
At t = 0, the input to the 4-bit adder are
changed to
X 3 X 2 X 1 X 0  1100, Y3Y2Y1Y0
 0100 and Z 0  1 . The output of the ripple
Q.8
carry adder will be stable at t
(in ns) = _______.
[GATE 2017, IIT Roorkee]
A 2-bit binary multiplier can be
implemented using
[GATE 1997, IIT Madras]
(A) 2 input AND gates only.
(B) Six 2-input AND gates and two XOR
gates.
(C) Two 2-input NORs and one XNOR gate.
(D) XOR gates and shift registers.
P
Q
R
The Boolean function F implemented is
(A) PQR  PQR  PQR
(B) ( P  Q  R )( P  Q  R)( P  Q  R )
(C) PQR  PQR  PQR
(D) ( P  Q  R )( P  Q  R )( P  Q  R )
Code Converter :
Q.1
The minimal function that can detect a
“divisible by 3” 8421 BCD code digit
(representation is D8 D4 D2 D1 ) is given by
PLA & PAL :
[GATE 1990, IISc Bangalore]
(A) D8 D1  D4 D2  D8 D2 D1
Q.1
(B) D8 D1  D4 D2 D1  D4 D2 D1  D8 D4 D2 D1
Q.2
Q.3
Choose the correct statements from the
following
[GATE 1992, IIT Delhi]
(A) PROM contains a programmable AND
array and a fixed OR array.
(B) PLA contains a fixed AND array and a
programmable OR array.
(C) PROM contains a fixed AND array and
a programmable OR array.
(D) PLA contains a programmable AND
array and a programmable OR array.
A PLA can be
[GATE 1994, IIT Kharagpur]
(A) as a microprocessor.
(B) as a dynamic memory.
(C) to realize a sequential logic.
(D) to realize a combinational logic.
A programmable logic array (PLA) is shown
in the figure.
[GATE 2017, IIT Roorkee]
(C) D8 D1  D4 D2  D8 D4 D2 D1
(D) D4 D2 D1  D4 D2 D1  D8 D4 D2 D1
Q.2
If the input X 3 , X 2 , X 1 , X 0 to the ROM in
figure are 8-4-2-1 BCD numbers, then the
outputs Y3 , Y2 , Y1 , Y0 are
[GATE 2002, IISc Bangalore]
X3 X2 X1 X0
ROM
BCD-to-Decimal DECODER
D 0 D1
D8 D9
0 1
Y3
Y2
Y1
Y0
Digital Electronics & Microprocessor 8085 [WB]
(A) Gray code numbers.
(B) 2-4-2-1 BCD numbers.
(C) Excess 3 code numbers.
(D) None of these.
The circuit shown in the figure converts
[GATE 2003, IIT Madras]
Q.3
GATE ACADEMY®
40
Q.2
Inputs
(A) P  Q  R
(B) P  Q  R
(C) P  Q  R
(D) P  Q  R
Which of the following sets of component
(s) is/are sufficient to implement any
arbitrary Boolean function?
(A) XOR gates, NOT gates
MSB
(B) 2 to 1 multiplexors
(C) AND gates, XOR gates
(D) Three – input gates that output (A.B) +
C for the inputs A, B and C
Q.3
MSB
Outputs
(A) BCD to Binary code.
(B) Binary to Excess -3 code.
(C) Excess -3 to Gray code.
(D) Gray to Binary code.
Identify the circuit below,
[GATE 2016, IISc Bangalore]
Q.4
X2
X1
X0
OP0
OP1
OP2
3 : 8 OP3
Decoder OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
8:3
IP4 Encoder
IP5
IP6
IP7
Q.4
The gray code equivalent of binary number
(1000001) 2 is
(A) 1100001
(B) 1100011
(C) 1000001
(D) 1111110
The logic realized by the circuit shown in
figure is
C
I2
I3
Y2
Y1
Y0
Q.5
S1
S0
A
B
(A) F  A  C
(B) F  A  C
(C) F  B  C
(D) F  B  C
The output of the circuit shown in figure is
equal to
A
B
Practice (objective & Num Ans) Questions :
Q.1
4 ´1
MUX F
I1
C
(A) Binary to Gray code converter
(B) Binary to XS3 converter
(C) Gray to Binary converter
(D) XS3 to Binary converter
I0
A
B
The Boolean expression for the output f of
the multiplexer shown below is
(A) 0
(B) 1
R
0
R
1
R
2
R
3 S1
4 ´1
S0
P Q
(C) A B  A B
f
(D) ( A  B)  ( A  B)
Q.6
The combinatorial circuit shown in figure
employs a 4 to 1 multiplexer. The output Q
of the circuit is
GATE ACADEMY®
Q.7
41
Q.11 The logic circuit given below is
1
D3
1
D2
1
D1
C
D0 S
1
S0
A
B
4 ´1
MUX
Q
(B) A  B  C
(C) A  B  C
(D) ABC
Match the following :
Logic
X Y
Function
inputs to I 0 , I1 , I 2 and I 3 of the MUX will
II. X Y
Q. NAND
realize the sum S?
III. X Y
R. Carry
4 to 1 MUX
I0
(A) I-Q, II-R, III-S (B) I-S, II-R, III-Q
I1
(C) I-Q, II-P, III-S (D) I-S, II-P, III-Q
I2
A multiplexer with a 4 bit data select input
is a
I3
(A) 4 : 1 Multiplexer
(B) 2 : 1 Multiplexer
Q.9
(A) Half adder
(B) XOR
(C) Equality detector (D) Full adder
Q.12 Figure shows a 4 to 1 MUX to be used to
implement the sum S of a 1 bit full adder
with input bits P and Q and the carry input
Cin . Which of the following combinations of
P. Sum
S. NOR
Q.8
A
B
Y
(A) ABC
I.
Combinational Circuits
F
S1
S0
P
Q
(C) 16 : 1 Multiplexer
(A) I 0  I1  Cin ; I 2  I 3  Cin
(D) 8 : 1 Multiplexer
(B) I 0  I1  Cin ; I 2  I 3  Cin
For a binary half-subtractor having two
inputs A and B, the correct set of logical
expressions for the outputs D ( = A minus B)
and X ( = borrow) are
(C) I 0  I 3  Cin ; I1  I 2  Cin
(A) D  A B  A B, X  A B
(B) D  AB  A B, X  A B
(C) D  A B  A B , X  A B
S
(D) I 0  I 3  Cin ; I1  I 2  Cin
Q.13 A digital circuit which compares two
numbers A3 A2 A1 A0 , B3 B2 B1 B0 is shown in
figure. To get output Y  0 , choose one pair
of correct input numbers.
B3 A3 B2 A2 B1 A1 B0 A0
(D) D  A B  A B , X  A B
Q.10 The number of full and half – adders
required to add 16 – bit numbers is
(A) 8 half – adders, 8 full – adders
(B) 1 half – adder, 15 full – adders
(C) 16 half – adders, 0 full – adders
(D) 4 half – adders, 12 full – adders
Y
(A) 1010, 1010
(C) 0010, 0010
(B) 0101, 0101
(D) 1010, 0101
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
42
x
Q.14 The Boolean function ‘f ’ implemented in
the figure using two input multiplexers is
C
0
0
C
1
f
1
B
1
y
0
A
0 MUX1
z
0
x
1
MUX2
f
y
E
(A) A B C  A B C
(B) A B C  A B C
(C) A B C  A B C
(D) A B C  A B C
Q.15 The cell of a field programmable Gate array
is shown in the figure. It has three 2-to-1multiplexers with their select lines
G0 , G1 , G2 and 4 digital signal input lines
(A) xz  xy  yz
(B) xz  xy  yz
(C) xz  xy  yz
(D) xz  x y  yz
Q.17 Consider the multiplexer based logic circuit
shown in the figure.
W
0
I 0 , I1 , I 2 and I 3 . The logical function that
MUX
0
1
MUX
F
1
relates the output O to the select and signal
input lines is
S1
S2
G0
Which one of the following Boolean
functions is realized by the circuit?
I0
0
I1
1
(A) F  W S1S 2
O1
(B) F  W S1  W S 2  S1S 2
0
(C) F  W  S1  S2
O
(D) F  W  S1  S 2
1
I2
0
I3
1
O2
Q.18 In the circuit shown, W and Y are MSBs of
the control inputs. The output F is given by
G1
G2
(A) G0 G1 I 2  G 0 G1 I 3  G 2 G1 I 0  G 2 G1 I1
(B) G 0 I 2  G 0G1  G 2 I 0  G 2G1 I1  G0
(C) G 0 G 2 I 0  G0 G 2 I1  G2 G1 I 2  G2G1 I 3
(D) G2G1 I 2  G 2 G1 I 3  G2 G 0 I 0  G0 G 2 I1
Q.16 Consider the circuit given. Which one of the
following options correctly represents f (x,
y, z)?
4 : 1 MUX
4 : 1 MUX
I0
I0
I1
I1
Q
VCC
Q
I2
I2
I3
I3
W
X
Y
(A) F  W X  W X  Y Z
(B) F  W X  W X  Y Z
(C) F  W X Y  W X Y
(D) F  (W  X )Y Z
Z
F
GATE ACADEMY®
43
Combinational Circuits
Q.19 If X and Y are inputs and the Difference (D
= X – Y) and the Borrow (B) are the outputs,
which one of the following diagrams
implements a half-subtractor?
(A) Y
I0
I1
I3
2:1
MUX
B
(B) 0110
(C) 1000
(D) 1110
2:1
MUX
0
R
B
2:1
MUX
B
2:1
MUX
2-to-1
R
0
1
2-to-1
MUX
s
0
2-to-1
MUX
s
1
P
X
Q
The minimal sum of products form of the
output X is
(A) PQ  PQR
(B) PQ  QR
(C) PQ  PQR
(D) QR  PQR
Q.22 Consider the circuit shown in the figure.
I0
I1
A
D
S
S
X
S0
Q.21 Consider the two cascaded
multiplexers as shown in the figure.
I0
I1
S1
(A) 1010
I0
I1
Y
B
S
S
Y
(C) Y
2:1
MUX
F
I2
D
I0
I1
X
MUX
I0
I1
(B) X
4 ´1
I1
S
S
X
Y
2:1
MUX
I0
D
Y
0
MUX
0
0
1
MUX
F
1
X
(D) X
I1
2:1
MUX
B
(B) X Y Z  X Z  Y Z
I0
I1
2:1
MUX
The Boolean expression F implemented by
the circuit is
(A) X Y Z  X Y  Y Z
S
S
Y
X
Z
I0
D
Q.20 In the 4×1 multiplexer, the output F is given
by F  A  B . Find the required input
I 3 I 2 I1 I 0 .
(C) X Y Z  X Y  Y Z
(D) X Y Z  X Z  Y Z
Q.23 A four-variable Boolean function is realized
using 4 1 multiplexers as shown in the
figure.
Digital Electronics & Microprocessor 8085 [WB]
I0
VCC
I0
I1
I1
4 ´1
MUX
I2
I3
Ground
4 ´1
MUX
F (U ,V , W , X )
I2
S1
S0
U
V
I3 S
1
S0
W
X
Ground
The minimized expression for
F (U ,V , W , X ) is
GATE ACADEMY®
44
(A) 111100
(B) 111011
(C) 1010111
(D) 111110
Q.27 What is the minimum number of 2 1
Multiplexer required to realize a 16  1
Multiplexer?
Q.28 Which of the following is the output
Boolean expression for ‘f’
(A) (UV  UV )W
(B) (UV  UV ) ( WX  WX )
(C) (UV  UV ) W
(D) (UV  UV ) (WX  WX )
B3
B2
B1
B0
1
0
1
I2
E
I3
Y0
A
4-bit
Comparator
A = B, Y1
B
D0
D1
A
B
 (0, 5, 6) is to be implemented using a
C
function
4 1 multiplexer shown in figure. Which
one of the following choice of inputs to semi
programmed multiplexer will realize the
Boolean function?
4 ´ 1 MUX
3´ 8
decoder
D2
D3
f
D4
D5
D6
D7
(A) f  m(0,3,5, 6) (B) f  m(0,5, 6)
(C) f  M(1, 2, 4, 7) (D) f  m(1, 2, 4, 7)
Q.30 The circuit shown can act as
1:4 DE-MUX
I0
I1
I0
I1
f
I2
I3
(B) C
(D) BC
(C) B
Q.29 The output expression of the digital circuit
shown in figure.
A < B, Y2
Boolean
C
(A) B  C
A > B, Y0
f
I4
I5
I6
I7
0
F ( A, B, C ) 
Q.25 The
I0
I1
0
1
Q.24 Consider the following circuit, the
maximum number of combinations of A, B
such that Y0  1 is ______.
A3
A2
A1
A0
1
0
'1'
S1
S0
B
C
(A) I 0  I1  1 , I 2  I 3  0
I2
I3
D
A
input
(C) I 0  I 3  A & I1  I 2  A
(A) Half Adder
(C) Half subtractor
Q.26 A number is represented in binary system
101011. It’s gray code equivalent is
output
y0
B
(B) I 0  I1  A & I 2  I 3  A
(D) I 0  I 3  A & I1  I 2  A
x0
(B) Comparator
(D) All of the above

GATE ACADEMY®
45
Combinational Circuits
Answer Keys
Objective & Numerical Answer Type Questions
Multiplexer
1.
D
2.
D
3.
A
4.
A
5.
D
6.
A
7.
A
8.
B
9.
D
10.
C
11.
A
12.
D
13.
A
14.
C
15.
C
16.
B
17.
A
18.
C
19.
6
20.
A
21.
C
22.
B
23.
C
24.
A
25.
C
C
4.
D
4.
A
5.
195
4.
A
Decoder
1.
A
2.
B
3.
Comparator
1.
D
2.
B
Adder
1.
C
2.
C
3.
B
6.
19.2
7.
50
8.
B
PLA & PAL
1.
C, D
2.
D
3.
C
Code Converter
1.
B
2.
B
3.
D
Practice (Objective & Numerical Answer) Questions
1.
B
2.
B
3.
A
4.
B
5.
B
6.
B
7.
A
8.
A
9.
C
10.
B
11.
C
12.
C
13.
D
14.
A
15.
C
16.
A
17.
D
18.
C
19.
A
20.
B
21.
D
22.
B
23.
C
24.
114 - 126
25.
C
26.
D
27.
15
28.
D
29.
D
30.
A
6
Sequential Circuits
Objective & Numerical Ans Type Questions :
Flip‐Flops :
Q.1
Refer to the NAND and NOR latches shown
in the figure. The input ( P1 , P2 ) for both the
latches are first made (0, 1) and then, after a
few seconds, made (1, 1). The
corresponding stable output (Q1 , Q2 ) are
Q.2
The following binary values were applied to
the X and Y inputs of the NAND latch
shown in the figure in the sequence
indicated below :
X  0, Y  1; X  0, Y  0; X  1, Y  1,
The corresponding stable P, Q outputs will
be
[GATE 2007, IIT Kanpur]
X
P
[GATE 2009, IIT Roorkee]
P1
Q1
Q
Y
(A) P  1, Q  0; P  1, Q  0; P  1,
Q  0 or P  0, Q  1
P2
P1
Q2
(B) P  1, Q  0; P  1, Q  0 or P  0,
Q  1; P  0, Q  1
Q1
(C) P  1, Q  0; P  1, Q  1; P  1,
Q  0 or P  0, Q  1
(D) P  1, Q  0; P  1, Q  1; P  1, Q  1
P2
Q2
(A) NAND: first (0, 1) then (0, 1) NOR :
first (1, 0) then (0, 0).
(B) NAND: first (1, 0) then (1, 0) NOR :
first (1, 0) then (1, 0).
(C) NAND: first (1, 0) then (1, 0) NOR :
first (1, 0) then (0, 0).
(D) NAND: first (1, 0) then (1, 1) NOR :
first (0, 1) then (0, 1).
Q.3 In the circuit shown in figure, when input
A  B  0, the possible logic states of C and D
are
[GATE 2001, IIT Kanpur]
A
C
D
B
(A) C  0, D  1 or C  1, D  0
(B) C  1, D  1 or C  0, D  0
GATE ACADEMY®
(C) C  1, D  0
Q.4
47
(D) C  0 , D  1
For a flip-flop formed using two NAND
gates as shown in figure. The unstable state
corresponds to [GATE 1999, IIT Bombay]
X
Sequential Circuits
Q.7
(D) Q goes to 0 at the CLK transition and
goes to 1 when D goes to 1.
Select the circuit which will produce the
given output Q for the input signals X 1 and
X 2 given in the figure
Q
[GATE 2005, IIT Bombay]
Y
Q.5
Q
X1
t
t
t
(A) X  0, Y  0
(B) X  0, Y  1
X2
(C) X  1, Y  0
(D) X  1, Y  1
Q
In figure A = 1 and B = 1, the input B is now
replaced by a sequence 101010 ……, the
output X and Y will be
[GATE 1998, IIT Delhi]
A
(A) X 1
X
X2
(B) X 1
B
Q.6
1
0
1
0
Q
Q
Y
(A) fixed at 0 and 1 respectively
(B) X = 1010 …. while Y = 0101 …
(C) X = 1010 …. while Y = 1010 …
(D) fixed at 1 and 0 respectively
For the circuit shown in the figure, D has a
transition from 0 to 1 after CLK changes
from 1 to 0. Assume gate delays to be
negligible.
X2
(C) X 1
Q
X2
(D) X 1
Q
CLK
D
Q
X2
Q.8
Q
Which of the following statement is true?
[GATE 2008, IISc Bangalore]
(A) Q goes to 1 at the CLK transition and
stays at 1.
(B) Q goes to 0 at the CLK transition and
stays at 0.
(C) Q goes to 1 at the CLK transition and
goes to 0 when D goes to 1.
The two inputs A and B are connected to an
R-S latch via two AND gates as shown in
the figure. If A  1 and B  0 , the output
[GATE 2017, IIT Roorkee]
QQ is
A
S
Q
R
Q
Q
Q
B
R-S Latch
Digital Electronics & Microprocessor 8085 [WB]
Q.9
GATE ACADEMY®
48
(A) 00
(B) 10
(C) 01
(D) 11
In the latch circuit shown, the NAND gates
have non-zero, but unequal propagation
delays. The present input condition is : P =
Q = ‘0’. If the input condition is changed
simultaneously to P = Q = ‘1’, the outputs
X and Y are
[GATE 2017, IIT Roorkee]
P
(B)
J
T
CLK
Qn
T flip-flop
K
Qn
(C)
J
X
T
CLK
Qn
T flip-flop
K
(D)
Y
Q
Qn
(A) X = ‘1’, Y = ‘1’
(B) Either X = ‘1’, Y = ‘0’ or X = ‘0’,
Y = ‘1’
(C) Either X = ‘1’, Y = ‘1’ or X = ‘0’,
Y = ‘0’
(D) X = ‘0’, Y = ‘0’
Q.10 An X-Y flip-flop, whose characteristic table
is given below is to be implemented using a
J-K flip-flop
[GATE 2003, IIT Madras]
J
T
CLK
Qn
Q.12 The digital circuit shown in the figure works
as
[GATE 2005, IIT Bombay]
Q
D
X
X
Y
0
0
1
0
1
Qn
1
0
Qn
(C) T flip-flop
1
1
0
(D) Ring counter
CLK
Q
(A) J-K flip-flop
(B) Clocked RS flip-flop
(A) J  X , K  Y
(B) J  X , K  Y
(C) J  Y , K  X
(D) J  Y , K  X
Q.11 A J-K flip-flop can be implemented by T
flip-flops.
Identify
the
correct
implementation.
[GATE 2014, IIT Kharagpur]
(A)
Q.13 A sequential circuit using D Flip-Flop and
logic gates is shown in figure, where X and
Y are the inputs and Z is the output. The
circuit is [GATE 2000, IIT Kharagpur]
X
CLK
Y
J
T
CLK
T flip-flop
K
Qn  1
This can be done by making
K
Qn
Qn
T flip-flop
Qn
D
Q
Z
R
Q
Z
GATE ACADEMY®
49
(A) S-R Flip-Flop with inputs X = R and Y =
S.
(B) S-R Flip-Flop with inputs X = S and Y =
R.
(C) J-K Flip-Flop with inputs X = J and Y =
K.
(D) J-K Flip-Flop with inputs X = K and Y =
J.
Q.14 An S-R latch is implemented using TTL
gates as shown in the figure. The set and
reset pulse inputs are provided using the
push-button switches. It is observed that the
circuit fails to work as desired. The S-R
latch can be made functional by changing
[GATE 2015, IIT Kanpur]
Set
Sequential Circuits
T2
clk
Q.3
The next state table of a 2-bit saturating upcounter is given below.
Q1
Q0
Q
Q
0
0
1
1
(A) NOR gates to NAND gates.
(B) Inverters to buffers.
(C) NOR gates to NAND gates and inverters
to buffers.
(D) 5 V to ground.
Q.2
Consider the partial implementation of a 2bit counter using T flip-flops following the
sequence 0-2-3-1-0, as shown below.
0
1
1
1
1
0
1
1
(A) T1  QQ
1 0 , T0  Q1Q0
(B) T1  Q1Q0 , T0  Q1  Q0
(C) T1  Q1  Q0 , T0  Q1  Q0
(D) T1  Q1Q0 ,T0  Q1  Q0
Q.4
Consider the following circuit.
D0 Q0
D1 Q1
’
00  11  01  10  00  ...
The connections to the inputs DA and DB
(D) DA  (QAQB  Q A Q B ), DB  Q B
0
[GATE 2017, IIT Roorkee]
Synchronous Counter :
(C) DA  (QA Q B  Q AQB ), DB  QA
0
1
0
1
1
The counter is built as a synchronous
sequential circuit using T flip-flops. The
expression for T1 and T0 are
Q
(B) DA  Q A , DB  Q B
(D)  Q1  Q2 
!
Reset
are
[GATE 2011, IIT Madras]
(A) DA  QB , DB  QA
Q1
LSB
MSB
(C)  Q1  Q2 
Q
Two D flip-flops are connected as a
synchronous counter that goes through the
following QB QA sequence
T1
To complete the circuit, the input X should
be
[GATE 2004, IIT Delhi]
'
(B) Q2  Q1
(A) Q2
5V
Q.1
x
Q2
Q’0
Q1
Clk
The flip-flops are positive edge triggered D
FFs. Each state is designated as a two bit
string Q0Q1. Let the initial state be 00. The
state transition sequence is
[GATE 2005, IIT Bombay]
(A) 00 ®11 ® 01
(B) 00 ®11
(C) 00 ®10 ® 01 ® 11 (D) 00 ®11 ® 01 ® 10
Digital Electronics & Microprocessor 8085 [WB]
Q.5
What are the counting state (Q1 , Q2 ) for the
GATE ACADEMY®
50
Q.7
If all the flip-flops were reset to 0 at power
on, what is the total number of distinct
outputs (states) represented by PQR
generated by the counter?
[GATE 2011, IIT Madras]
(A) 3
(B) 4
(C) 5
(D) 6
If at some instance prior to the occurrence of
the clock edge, P, Q and R have a value 0, 1
and 0 respectively, what shall be the value
of PQR after the clock edge?
[GATE 2011, IIT Madras]
(A) 000
(B) 001
(C) 010
(D) 011
In the following sequential circuit, the initial
state (before the first clock pulse) of the
circuit is Q1Q0  00. The state (Q1 Q0 ),
counter shown in the figure below?
[GATE 2009, IIT Roorkee]
Q1
J1
Clock
Q1
J2
J-K Flip-Flop
K1
Q.6
Q2
Q2
J-K Flip-Flop
Q1
K2
1
Q2
Q.8
(A) 11, 10, 00, 11, 10,….
(B) 01, 10, 11, 00, 01,….
(C) 00, 11, 01, 10, 00,….
(D) 01, 10, 00, 01, 10,….
A 2-bit counter circuit is shown below,
J
Q
K
Q
QA
J
Q
K
Q
QB
Q.9
immediately after the 333rd clock pulse is
[GATE 2015, IIT Kanpur]
CLK
Q0
If the state QA QB of the counter at the clock
time t n is “10” then the state QAQB of the
counter at tn  3 (after three cycles) will be
(A) 00
(C) 10
[GATE 2011, IIT Madras]
(B) 01
(D) 11
Common Data for
Questions 7 & 8
Consider the following circuit involving
three D-type flip-flops used in a certain type
of counter configuration.
Q1
J0
Q0
J1
Q1
K0
Q0
K1
Q1
CLK
(A) 00
(B) 01
(C) 10
(D) 11
Q.10 Consider a combination of T and D flipflops connected as shown below. The output
of the D flip- flop is connected to the input
of the T flip-flop and the output of the T
flip-flop is connected to the input of the D
flip-flop.
P
D
clock
Q
T
Flip Q1
Flop
Q
D
Q
Q
D
Flip Q0
Flop
Clock
Q
Q R
D
clock
Initially, both Q0 and Q1 are set to 1 (before
Q
the 1st clock cycle). The outputs
[GATE 2017, IIT Roorkee]
(A) Q1 Q0 after the 3rd cycle are 11 and after
the 4th cycle are 00 respectively
GATE ACADEMY®
51
Sequential Circuits
(B) Q1 Q0 after the 3rd cycle are 11 and after
Q1
the 4th cycle are 01 respectively
(C) Q1 Q0 after the 3rd cycle are 00 and after
Q2
the 4th cycle are 11 respectively
(D) Q1 Q0 after the 3rd cycle are 01 and after
0
the 4th cycle are 01 respectively
Q.11 A 2-bit synchronous counter using two J -K
flip flops is shown. The expressions for the
inputs to the J -K flip flops are also shown
in the figure. The output sequence of the
counter starting from Q1Q2  00 is
[GATE 2018, IIT Guwahati]
Q1 + Q2
J
Q1 + Q2
K CLR Q
SET Q
Q1
Q1 + Q2
Q1 + Q2
J
SET Q
0
J 0 Q0
K0
1
1
J1 Q1
J 2 Q2
J 3 Q3
K1
K2
K3
CLK
(A) 1111
(B) 1100
(C) 0001
(D) 0011
Q.14 Given below figure shows a MOD-k
counter, here k is equal to
Q2
[GATE 1998, IIT Delhi]
K CLR Q
J0
Q0
K0
Q0
J1
Q1
K1
Q1
Clock
(A) 00  11  10  01  00...
1
1
(B) 00  01  10  11  00...
(C) 00  01  11  10  00...
(D) 00  10  11  01  00...
Q.12 The outputs of the two flip-flops Q1 , Q2 in
(A) 1
(B) 2
(C) 3
(D) 4
the figure shown are initialized to 0, 0. The
sequence generated at Q1 upon application
Q.15 A sequential circuit is shown in the figure
below. Let the state of the circuit be encoded
as QA , QB . The notation X  Y implies that
of clock signal is
[GATE 2014, IIT Kharagpur]
state Y is reachable from state X in a finite
number of clock transitions.
Q1
J1
Q1
J2
Q2
K1
Q1
K2
Q2
CLK
(A) 01110….
(B) 01010….
(C) 00110…
(D) 01100…..
Q.13 Figure shows a sequential circuit with four
J-K flip-flops and generate a table of output
(Q3 Q2 Q1 Q0 ) changes with each clock
QA
QA
Q
Q
Q
Q
MUX
CLK
TA
CLK
TB
CLK
Identify the INCORRECT statement.
[GATE 2007, IIT Kanpur]
pulse. Start with Q3 Q2 Q1 Q0  0001 and the
next state after the first clock pulse
[GATE 1995, IIT Kanpur]
QB
(A) 01  00
(B) 11  01
(C) 01  11
(D) 01  10
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
52
(C) A = 0
Common Data for
Questions 16 & 17
A =1
A=0
Q=0
Consider the circuit shown in the following figure.
Q =1
A =1
(D) A = 1
X1
A =1
A=0
Y
X2
Q=0
Q =1
A=0
D1 Q1
D2 Q2
D3 Q3
CLK
Q.16 The correct input-output
between Y and (X1X 2 ) is
relationship
Q.19 A finite state machine (FSM) is
implemented using the D flip-flops A and B
and logic gates, as shown in the figure
below. The four possible states of the FSM
are QAQB = 00, 01, 10 and 11.
[GATE 2007, IIT Kanpur]
(A) Y  X1  X 2
(B) Y  X1X 2
(C) Y  X1  X 2
QA
(D) Y  X1  X2
CK
X1
(B) three of the four possible states if X IN  0.
(C) only two of the four possible states if
X IN  1 .
X 0 Select
A=0
(D) only two of the four possible states if
X IN  0.
Q =1
Q.20 The digital logic shown in the figure
satisfies the given state diagram when Q1 is
A =1
connected to input A of the XOR gate.
A=0
(B) A = 0
Q
CK
cycles, it starts cycling through
[GATE 2017, IIT Roorkee]
(A) all of the four possible states if X IN  1.
A
Q=0
Q
level throughout the operation of the FSM.
When the FSM is initialized to the state
QAQB = 00 and clocked, after a few clock
Y
(A) A = 1
B
X IN
Assume that X IN is held at a constant logic
2 : 1 MUX
CLK Q
A=0
D1
A =1
Q=0
Q =1
A =1
QB
CLK
is equal to
[GATE 2007, IIT Kanpur]
(A) 001
(B) 010
(C) 100
(D) 101
Q.18 The state transition diagram for the logic
circuit shown is [GATE 2012, IIT Delhi]
Q
Q
D
A
Q.17 The D flip-flop are initialized to
Q1Q 2 Q3  000 . After 1 clock cycle, Q1Q 2 Q 3
D
Q
D
CLK
Q1
Q1
A
D2
S
Q2
Q2
GATE ACADEMY®
53
S =0
S =1
00
S =1
01
S =0
S =0
10
S =1
11
S =1
S =0
Suppose the XOR gate is replaced by an
XNOR gate. Which one of the following
option preserves the state diagram?
[GATE 2014, IIT Kharagpur]
Sequential Circuits
(A) 1 – 1
(B) 1 – 0
(C) 0 – 0
(D) state 11 is unreachable
Q.23 The state diagram of a finite state machine
(FSM) designed to detect an overlapping
sequence of three bits is shown in the figure.
The FSM has an input ‘In’ and an output
‘Out’. The initial state of the FSM is S 0 .
S0
In = 1
Out = 0
In = 0
Out = 0
(A) Input A is connected to Q2
(B) Input A is connected to Q2
In = 1
Out = 0
01
S1
In = 0
Out = 0
(C) Input A is connected to Q1 and S is
10
complemented
In = 0
Out = 0
Q.21 When the output Y in the circuit below is
“1”, it implies that data has
[GATE 2011, IIT Madras]
Clock
D
Q
Q
D
Q
In = 1
Out = 0
S2
(D) Input A is connected to Q1
Data
In = 0
Out = 0
00
Q
Q.24
Q.22
S3
11
Y
(A) changed from “0”to “1”.
(B) changed from “1” to “0”.
(C) changed in either direction.
(D) not changed.
In = 1
Out = 1
If the input sequence is 10101101001101,
starting with the left-most bit, then the
number of times ‘Out’ will be 1 is _____.
[GATE 2017, IIT Roorkee]
The state transition diagram for a finite state
machine with states A, B and C, and binary
inputs X, Y and Z is shown in the figure.
[GATE 2016, IISc Bangalore]
Y=1
X = 0, Y = 0, Z = 0
A
X = 0, Z = 1
Y = 0, Z = 0
Y = 1,
X = 1,
Z=1 Z=1
X = 1, Y = 0
B
Y=1
Y = 0, Z = 1
C
Z=0
Analyze the sequential circuit shown above
in figure. Assuming that initial state is 00,
determine what input sequence would lead
to state 11 ?
Which one of the following statements is
correct?
(A) Transitions
from
State
A
are
ambiguously defined.
(B) Transitions
from
State
B
are
ambiguously defined.
Digital Electronics & Microprocessor 8085 [WB]
(C) Transitions
from
State
C
are
ambiguously defined.
(D) All of the state transitions are defined
unambiguously.
GATE ACADEMY®
54
Common Data for
Questions 4 & 5
Consider the counter circuit shown below.
Asynchronous Counters :
Q.1
The ripple counter shown in figure is made
up of negative edge triggered J-K flip-flops.
The signals levels at J and K inputs of all the
flip-flops are maintained at logic 1. Assume
all the outputs are cleared just prior to
applying the clock signal. Module number
of the counter is
[GATE 2002, IISc Bangalore]
Q0
J
Q1
J
CLK
CLK
K
K
CLK1
Q2
J
Q.4
CLK
K
CLR
CLR
CLR
(C) Q3 .(Q1  Q2 )
A
(A) 7
(B) 5
(C) 4
(D) 8
The circuit shown consists of J-K flip-flops,
each with an active low asynchronous reset
( Rd input). The counter corresponding to
Q.2
Q.5
Q.6
this circuit is [GATE 2015, IIT Kanpur]
1
Q
J
Q0
1
Q
J
Q1
1
In the above figure, Y can be expressed as
[GATE 2008, IISc Bangalore]
(A) Q3 .(Q1  Q2 )
(B) Q3  Q1.Q2
J
Q2
Q
(D) Q3  Q1.Q2
The above circuit is a
[GATE 2008, IISc Bangalore]
(A) Mod-8 Counter (B) Mod-9 Counter
(C) Mod-10 Counter (D) Mod-11 Counter
In the modulo-6 ripple counter shown in
below, figure the output of the 2-input gate
is used to clear the J-K flip-flops.
1
Clock
1
1
K Rd
1
K Rd
C
K Rd
J
B
C CLR K
(A) a modulo-5 binary up counter.
(B) a modulo-6 binary down counter.
(C) a modulo-5 binary down counter.
(D) a modulo-6 binary up counter.
The ripple counter shown in the given figure
is works as a [GATE 1999, IIT Bombay]
Q.3
Preset
J
Q
A
‘1’
K
Preset
J
Q
B
Q
‘1’
K
Preset
Q
C
Q
‘1’
Clock
(A) MOD-3 up counter.
(B) MOD-5 up counter.
(C) MOD-3 down counter.
(D) MOD-5 down counter.
K
Q
B CLR K
A
J
A CLR K
Clock
input
2-input
gate
Q.7
J
J
The 2-input gate is [GATE 2004, IIT Delhi]
(A) a NAND gate
(B) a NOR gate
(C) an OR gate
(D) an AND gate
A 0 to 6 counter consists of 3 flip-flops and
a combinational circuit of 2 input gate(s).
The combination circuit consists of
[GATE 2003, IIT Madras]
(A) one AND gate.
(B) one OR gate.
(C) one AND gate and OR gate.
(D) two AND gates.
GATE ACADEMY®
Q.8
55
A ripple counter using negative edgetriggered D-flip flops is shown in figure
below. The flip-flops are cleared to ‘0’ at the
R input. The feedback logic is to be
designed to obtain the count sequence
shown in the same figure.
D0
Clock
Q0
D1
C0
Q1
D2
C1
R
Q0
Sequential Circuits
Q.11 Five J-K flip-flops are cascaded to form the
circuit shown in Figure. Clock pulses at a
frequency of 1 MHz are applied as shown.
The frequency (in kHz) of the waveform at
Q3 is _______.
[GATE 2014, IIT Kharagpur]
Q2
1
C2
R
Q1
1
001
010
1
J3
K4
1
K3
011
100
101
(A) F  Q2Q1Q0
(B) F  Q2Q1Q0
(C) F  Q2Q1Q0
(D) F  Q2Q1Q0
CLOCK
are the next four values of Q1Q0 ?
[GATE 2010, IIT Guwahati]
Q
T
J1
1
K2
1
Q1
1
QA
QB
QB
QC
QC
QD
QD
Q3
Binary
Counter
Q2
(B) 10, 11, 01, 00
(C) 10, 00, 01, 11
(D) 11, 10, 00, 01
[GATE 2000, IIT Kharagpur]
J
Q2
J
Q3
CLK
CLK
CLK
CLK
K
K
K
K
CLR
CLR
CLR
Q0
CLR
Q.10 In the figure, the J and K inputs of all the
four flip-flops are made high. The frequency
of the signal at output Y is
f  10 kHz
Q1
Q1
(A) 11, 10, 01, 00
Q1
K0
Q.13 The figure shows a binary counter with
synchronous clear input. With the decoding
logic shown, the counter works as a
[GATE 2015, IIT Kanpur]
Q
Q0
J
Q0
QA
Clock
Q0
J0
CLK
K1
1
CLK
clock
J
1
CLK
CLEAR
In the sequential circuit shown below, if the
initial value of the output Q1Q0 is 00, what
T
Q2
CLK
4-Bit Binary
Counter
[GATE 1987, IIT Bombay]
1
J2
1
Q.12 A MOD-n counter using a synchronous
binary up-counter with synchronous clear
input is shown in the figure. The value of n
is _______.
[GATE 2015, IIT Kanpur]
The correct feedback logic is
Q.9
Q3
CLK
Clock
Feedback
Logic
Count sequence in the order of Q2Q1Q0
000
Q4
CLK
Q2
R
F
J4
(A) MOD-2 counter. (B) MOD-4 counter.
(C) MOD-5 counter. (D) MOD-6 counter.
Miscellaneous Questions (FF & Counters) :
Q.1
Y
Which one of the following statements is
true about the digital circuit shown in the
figure.
[GATE 2018, IIT Guwahati]
CLR
D
(A) 0.833 kHz
(B) 1.0 kHz
(C) 0.91 kHz
(D) 0.77 kHz
C
fin
Q
D
C
Q
D
C
Q
fout
Q.2
GATE ACADEMY®
56
Digital Electronics & Microprocessor 8085 [WB]
(A) It can be used for dividing the input
frequency by 3.
(B) It can be used for dividing the input
frequency by 5.
(C) It can be used for dividing the input
frequency by 7.
(D) It cannot be reliably used as a
frequency divider due to disjoint
internal cycles.
The clock frequency applied to the digital
circuit shown in figure below is 1 kHz. If the
initial state of the output Q of the flip-flop is
‘0’, then the frequency of the output
waveform Q in kHz is
[GATE 2013, IIT Bombay]
(A)
(B)
(C)
(D)
Q.5
In the circuit shown choose the correct
timing diagram of the output (y) from the
given waveforms W1 , W2 , W3 and W4 .
[GATE 2014, IIT Kharagpur]
X1
Q
D
CLK
FF1
Q
X
T
Q
Output (y)
Q
X2
CLK
Q
Q.3
Q.4
FF2
Q
(A) 0.25
(B) 0.5
(C) 1
(D) 2
For a J-K flip-flop, its J input is tied to its
own Q output and its K input is connected
Q
CIK
X1
to its own Q output. If the flip-flop is fed
with a clock of frequency 1 MHz. Its Q
output frequency will be in _______ MHz.
[GATE 1995, IIT Kanpur]
The digital circuit shown in figure generates
a modified clock pulse at the output. Choose
the correct output waveform from the
options given below.
[GATE 2004, IIT Delhi]
X2
W1
W2
W3
W4
PR = 1
1
J
CLK
1
K
Q
Q
CR = 1
Q.6
O/P
Q
D
(A) W1
(B) W2
(C) W3
(D) W4
The digital block in the figure is realized
using two positive edge triggered D-flipflops. Assume that for t  t0 , Q1  Q2  0. The
circuit in the digital block is given by
[GATE 2001, IIT Kanpur]
X
CLK
t0 t1 t2 t3
Digital
Block
Y
t0 t1 t2 t3 t4
GATE ACADEMY®
57
Sequential Circuits
(A)
D1
1
Q1
D2
1
Q2
counter whose UP/ DN input is fed with the
train pu . The counter is a negative edge
Y
triggered one. The counter starts with 0000
and will reach 0000 again at the
[GATE 2007, IIT Kanpur]
X
Q1
Q2
(B)
D1
1
Q1
D2
1
Q2
Y
C1
X
Q1
Q2
PU
(C)
D1
1
Q1
D2
Q2
Y
X
Q1
Q2
(D)
Q.9
(A) 15th clock pulse (B) 16th clock pulse
(C) 44th clock pulse (D) 48th clock pulse
The circuit below show an up/down counter
working with a decode and a flip-flop.
Preset and clear of the flip-flop are
asynchronous active-low inputs.
VCC
D1
1
Q1
D2
Q2
Y
X
Q1
Q.7
Q2
A 3-bit gray counter is used to control the
output of the multiplexer as shown in the
figure. The initial state of the counter is 000
The output is pulled high. The output of the
circuit follows the sequence.
[GATE 2014, IIT Kharagpur]
+ 5V
A2
3-bit gray
counter
CLK
A1
R
E
0
1
2
3
S0
S1
4 ´1
MUX
Output
(A) I 0 ,1,1, I1 , I 3 ,1,1, I 2
(B) I 0 ,1, I1 ,1, I 2 ,1, I 2 ,1
(C) 1, I 0 ,1, I1 ,1, I 2 ,1, I 3 ,1
(D) I 0 , I1 , I 2 , I 3 , I 0 , I1 , I 2 , I 3
Q.8
3 to 8 Decoder
C B A (LSB)
D Preset Q
Flip-Flop
Count
Down
Clock
Clear
Count
Up
Q
Q 2 Q1 Q0
Up/Down Counter
Clock
A0
I0
I1
I2
I3
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
The square wave C 1 shown in Fig is given
to the clock input of a 4-bit binary up/down
Assuming that the initial value of counter
output (Q 2 Q1Q 0 ) as zero, the counter
outputs in decimal for 12 clock cycles are
[GATE 2011, IIT Madras]
(A) 0, 1, 2, 3, 4, 4, 3, 2, 1, 1, 2, 3, 4
(B) 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0
(C) 0, 1, 2, 3, 4, 5, 5, 4, 3, 2, 1, 0, 1
(D) 0, 1, 2, 3, 4, 5, 4, 3, 2, 1, 0, 1, 2
Q.10 The minimum number of flip-flops needed
to make mod-2 counter is
[GATE 1998, IIT Delhi]
(A) 1
(B) 2
(C) 3
(D) 4
Digital Electronics & Microprocessor 8085 [WB]
Q.11 The minimum number of J-K flip-flops
required to construct a synchronous counter
with the count sequence (0, 0, 1, 1, 2, 2, 3, 3,
0, 0, …..) is ________.
[GATE 2015, IIT Kanpur]
Q.12 We want to design a synchronous counter
that counts the sequence 0-1-0-2-0-3 and
then repeats. The minimum number of J-K
flip-flops required to implement this counter
is _______. [GATE 2016, IISc Bangalore]
Q.13 A traffic signal cycles from Green to
Yellow, Yellow to Red and Red to Green. In
each cycle, Green is turned on for 70
seconds. Yellow is turned on for 5 seconds
and the Red is turned on for 75 seconds.
This traffic light has to be implemented
using a finite state machine (FSM). The only
input to this FSM is a clock of 5 seconds
period. The minimum number of flip-flops
required to implement this FSM is
________. [GATE 2018, IIT Guwahati]
Q.14 A 4-bit modulo-16 ripple counter uses J-K
flip-flops. If the propagation delay of each
FF is 50 ns, the maximum clock frequency
that can be used is equal to
[GATE 1990, IISc Bangalore]
(A) 20 MHz
(B) 10 MHz
(C) 5 MHz
(D) 4 MHz
Q.15 A pulse train with a frequency of 1 MHz is
counted using a modulo-1024 ripple-counter
built with J-K flip flops. For proper
operation of the counter, the maximum
permissible propagation delay per flip flop
stage is _________ nsec.
[GATE 1993, IIT Bombay]
Q.16 For each of the positive edge-triggered J-K
flip flop used in the following figure, the
propagation delay is  T .
GATE ACADEMY®
58
1
CLK
0
t1
J0
Q0
1
J1
CLK
1
K0
1
K1
Q1
t
Which of the following waveforms correctly
represents the output at Q1 ?
(A)
1
0
2T
t1 + DT
(B)
1
0
4T
t1 + 2DT
(C)
1
0
2T
t1 + 2DT
(D)
1
0
4T
t1 + DT
Q.17 Design a synchronous counter for the
sequence 0, 2, 4, 5, 7, 0…..
After designing, check if the designed
counter is self-starting or not?
Q.18 The figure shows a digital circuit
constructed using negative edge triggered JK flip flops. Assume a starting state of
Q2Q1Q0  000 will repeat after ______
number of cycles of the clock CLK.
[GATE 2015, IIT Kanpur]
[GATE 2008, IISc Bangalore]
1
T
1
J0
CLK
Clock
1
K0
Q0
J1
Q1
J2
Clock
Q0
1
K1
Q2
Clock
Q1
1
K2
Q2
GATE ACADEMY®
59
Sequential Circuits
Q.19 In Fig initially Q  A  B  0 After three
volts for logic LOW levels. The data bit and
clock periods are equal and the value of
T / TCK  0.15 , where the parameters T
clock triggers, the state of Q, A and B will
be respectively.
[GATE 2004, IIT Delhi]
1
and TCK are shown in the figure. Assume
that the flip-flop and the XOR gate are ideal.
Q
J
X
Clock
CK
Cl
K
Mod 3
Counter
Din
Q
D
D flip-flop
Q
CLK
Q
A
CK
B
(A) 110
(B) 011
(C) 001
(D) 101
Q.20 A cascade of three identical modulo-5
counters has an overall modulus of
[GATE 2014, IIT Kharagpur]
(A) 5
(B) 25
(C) 125
(D) 625
Q.21 Consider the D-Latch shown in the figure,
which is transparent when its clock input
CLK is high and has zero propagation delay.
In the figure, the clock signal CLK1 has a
50% duty cycle and CLK2 is a one-fifth
period delayed version of CLK1. The duty
cycle at the output of the latch in percentage
is______.
[GATE 2017, IIT Roorkee]
TCK
CK
Din
DT
DT
DT
If the probability of input data bit ( Din )
transition in each clock period is 0.3, the
average value (in volts, accurate to two
decimal places) of the voltage at node X, is
_________. [GATE 2018, IIT Guwahati]
Q.23 Consider the given circuit.
A
CLK
TCLK
B
CLK1
In this circuit, the race around
[GATE 2012, IIT Delhi]
(A) does not occur.
(B) occurs when CLK = 0.
(C) occurs when CLK = 1 and A = B = 1.
(D) occurs when CLK = 1 and A = B = 0.
CLK2
TCLK /5
CLK1
Q
D
Output
D-Latch
CK
CLK2
Q.22 In the circuit shown below, a positive edgetriggered D flip-flop is used for sampling
input data Din using clock CK. The XOR
gate outputs 3.3 volts for logic HIGH and 0
Shift Registers
Q.1
The initial contents of the 4-bit serial-inparallel-out, right-shift, Shift Register shown
in the figure is 0110. After three clock
pulses are applied, the contents of the Shift
Register will be [GATE 1992, IIT Delhi]
GATE ACADEMY®
60
Digital Electronics & Microprocessor 8085 [WB]
Clock
0
1
1
and 0 respectively. The clock has a 30%
duty cycle.
0
Serial in
D
Å
Q.2
Q
D1
(A) 0000
(B) 0101
(C) 1010
(D) 1111
D
Q
D2
D
Q
D3
D
Q
D
D4
R = 10 kW
Q
D5
Clock
A three bit pseudo random number generator
is shown. Initially the value of output
Y  Y2Y1Y0 is set to 111. The value of output
The average power dissipated (in mW) in
the resistor R is ________.
[GATE 2016, IISc Bangalore]
Q.5
Y after three clock cycles is
[GATE 2015, IIT Kanpur]
Y2
D2
Y1
Q2
D1
Q1
Y0
D0
Q0
For the circuit shown, the counter state ( Q1Q0
) follows the sequence :
CLK
Q.3
(A) 000
(B) 001
(A) 00, 01, 10, 11, 00 ….
(C) 010
(D) 100
(B) 00, 01, 10, 00, 01 ….
For the synchronous sequential circuit
shown below, the output Z is zero for the
initial conditions
QAQB QC  QA ' QB ' QC '  100
Clock
D SET Q
D SET Q
CLR Q
CLR Q
[MSB] QA
D SET Q
CLR Q
QB
QC
Z
[MSB] Q '
D SET Q
A
D SET Q
QB'
D SET Q
QC'
(C) 00, 01, 11, 00, 01 ….
(D) 00, 10, 11, 00, 01 ….
Q.6
For the circuit shown in figures below, two
4-bit parallel-in serial-out shift registers
loaded with the data shown are used to feed
the data to a full adder. Initially, all the flipflop are in clear state. After applying two
clock pulses, the outputs of the full-adder
should be [GATE 2006, IIT Kharagpur]
1 0 1 1
MSB
D
Q
LSB
CLK
CLR Q
CLR Q
CLR Q
Shift resisters
0 0 1 1
The minimum number of clock cycles after
which the output Z would again become
zero is _____. [GATE 2017, IIT Roorkee]
Q.4
Assume that all the digital gates in the
circuit shown in the figure are ideal, the
resistor R  10 k and the supply voltage is
5 V . The D flip-flops D1 , D2 , D3 , D4 and
D5 are initialized with logic values 0, 1, 0, 1
S
A
Full
Adder
Q
B
CLK
Ci
C0
Q
D
D
CLK
Clock
(A) S  0, C0  0
(B) S  0, C0  1
(C) S  1, C0  0
(D) S  1, C0  1
GATE ACADEMY®
Q.7
61
In the digital circuit shown in fig. the flip
flops have set time of 5 ns and a worst case
delay of 15 ns. The AND gate has a delay of
5 ns. Maximum possible clock rate for the
circuit to operate faithfully is
[GATE 2004, IIT Delhi]
Sequential Circuits
Q.3
0X /1,10 /1
Q=0
11/0
Clock
1
A state diagram of a logic which exhibits a
delay in the output is shown in the figure,
where X is the don’t care condition, and Q is
the output representing the state.
Q =1
0X /1,10 /1
11/0
Q
R
R
CI
Q
CI
CI
S
S
Q
Q
R
0
S
Q
Q
1
(A) 21 MHz
(C) 25 MHz
Q.4
(B) 22 MHz
(D) 30 MHz
Practice (objective & Num Ans) Questions :
Q.1
Q.5
For the digital counter shown in the figure
with outputs Q0,Q1,Q2 ,.... where Q0
The logic gate represented by the state
diagram is
(A) XOR
(B) OR
(C) AND
(D) NAND
An S-R FLIP-FLOP can be converted into a
T FLIP-FLOP by connecting ______ to Q
and _______ to Q .
For the initial state of 000, the function
performed by the arrangement of the J-K
flip-flops in figure is
indicates the LSB of the count value, the
correct statement when the switch Sw is
closed
A
PR
1
Q0
J
Q1
1
J
Q2
A
Clock
Q.2
Clk
Clk
1
K
J
Q
J
Q
K
Q
K
Q
K
Q
(A) Shift Register
(C) Mod-6 Counter
Sw
J
Q
CLOCK
VCC
1
J
A
1
K
1
Q.6
(B) Mod-3 Counter
(D) Mod-2 Counter
The output Qn 1 of a J-K flip-flop for the
Clk
input J  1, K  1 is
K
(A) 0
(B) 1
(C) Qn
(D) Qn
(A) Counter outputs are both even and odd
numbers.
(B) Counter outputs are only odd numbers.
(C) Counter outputs are only even numbers.
(D) Counter stops counting.
A 4-bit synchronous counter with a series
carry, uses flip-flop and AND gates, having
a propagation delay of 30 ns and 10 ns
respectively. The maximum time interval
required between two successive clock
pulses for reliable operation of the counter is
(A) 10 ns
(B) 30 ns
(C) 40 ns
(D) 50 ns
Q.7
The minimum number of flip-flop required
to design a MOD-10 counter is
(A) 3
(B) 10
(C) 4
(D) 5
Q.8
A
B
Q
Q
The circuit shown in figure is a
(A) R-s latch
(B) R-S flip-flop
(C) D latch
(D) D flip-flop
Q.9
GATE ACADEMY®
62
Digital Electronics & Microprocessor 8085 [WB]
A 4-bit shift register circuit configured for
right-shift operation, i.e. Din  A, A  B,
D0
B  C , C  D , is shown. If the present
state of the shift register is ABCD = 1101,
the number of clock cycles required to reach
the state ABCD = 1111 is _________.
B
C
D
Clock
Q.10 Consider the following J-K flip-flop
Q
J
Q
K CLK Q
1
D1
Q1
D2
LSB
MSB
Clock
Clock
0
1
Assume that the flip-flop was initially
cleared and then clocked for 6 pulses. What
is the sequence at the Q output?
(A) 010000
(B) 011001
(C) 010010
(D) 010101
Q.11 The circuit shown in the figure is a MOD-N
ring counter. Value of N is (assume initial
state of the counter is 1110 i.e.
Q3 Q2 Q1 Q0  1110 )
(A) 3
(B) 7
(C) 11
(D) 15
Q.14 The correct cyclic sequence of the outputs
(Q0Q1 ) for the master-slave JK flip-flop
circuit shown in below figure, when the
input clock pulse applied is
A
Q3
D2
Q2
D1
Q1
D0
Q0
1
(A) 4
(B) 5
(C) 7
(D) 6
Q.12 Consider the circuit given below with initial
state Q0  1, Q1  Q2  0 . The state of the
by
the
value
J0
Q0
K0
Q0
1
J1
Q1
K1
Q1
Y
Clk
CLK
circuit is given
4Q2  2Q1  Q0 .
0
1
Serial
input
In the above J-K flip-flop, J  Q and K  1
D3
Q2
Which one of the following is the correct
state sequence of the circuit?
(A) 1, 3, 4, 6, 7, 5, 2 (B) 1, 2, 5, 3, 7, 6, 4
(C) 1, 2, 7, 3, 5, 6, 4 (D) 1, 6, 5, 7, 2, 3, 4
Q.13 The shift register shown in figure is initially
loaded with the bit pattern 1010.
Subsequently the shift register is clocked
and with each clock pulse the pattern gets
shifted by one bit position to the right. With
each shift, the bit at the serial input is
pushed to the left most position (msb). After
how many clock pulses will the content of
the shift register becomes 1010 again?
Din
A
Q0
of
(A) 00, 01, 10, 11, 00, 01, …
(B) 00, 10, 01, 00, 10, 01, …
(C) 00, 01, 10, 00, 01, 10, …
(D) 00, 11, 00, 11, 00, 11, …
Q.15 Choose the correct one from among the
alternatives A, B, C, D after matching an
item from Group 1 with the most
appropriate item in Group 2.
GATE ACADEMY®
63
Group 1
P : Shift register
Q : Counter
R : Decoder
Group 2
1 : Frequency
Division
2 : Addressing in
memory chips
3 : Serial to
parallel data
conversion
Codes : P
Q R
(A) 3
2
1
(B) 3
1
2
(C) 2
1
3
(D) 1
3
2
Q.16 In an SR latch made by cross coupling two
NAND gates, if S = R = 0, then it will result
in
(A) Q  0, Q '  1
Sequential Circuits
D0
Q0
D1
Q1
LSB
MSB
CLK Q0
CLK Q1
Clock
The inputs D0 and D1 respectively should
be connected as
(A) Q1 and Q0
(B) Q0 and Q1
(C) Q1Q0 and Q1Q0
(D) Q1Q0 and Q1Q0
Q.20 Given that the initial state (Q1Q0 ) is 00, the
counting sequence of the counter shown in
the following figure for, Q1Q 0 is
'1'
J0
Q0
J1
Q1
K0
Q0
K1
Q1
Clock
(B) Q  1, Q '  0
(C) Q  1, Q '  1
(D) Indeterminate state
Q.17 The given figure shows a ripple counter
using positive edge triggered Flip-Flops. If
the present state of the counter is
Q2Q1Q0  011 then its next state Q2Q1Q0
will be
1
1
T0
Q0
1
T1
Q1
T2
(A) 00 – 11 – 01 – 10 – 00
(B) 00 – 01 – 11 – 10 – 00
(C) 00 – 11 – 10 – 01 – 00
(D) 00 – 10 – 01 – 11 – 00
Q.21 All the logic gates in the circuit shown
below have finite propagation delay. The
circuit can be used as a clock generator, if
Q2
Y
CLK
Q0
Q1
Q2
(A) 010
(B) 100
(C) 111
(D) 101
Q.18 In the figure, as long as X 1  1 and X 2  1 ,
the output Q remains
X1
1
Q
X
(A) X = 0
(B) X = 1
(C) X = 0 or 1
(D) X = Y
Q.22 Consider the circuit in the diagram. The 
operator represents Ex-OR. The D flip-flops
are initialized to zeroes (cleared).
X2
(A) at 1
(B) at 0
(C) at its initial value (D) unstable
Q.19 Two D flip-flops, as shown below, are to be
connected as a synchronous counter that
goes through the following Q1 Q0 sequence
00  01  11  10  00  …
Dq Q
q2 Q
D
1
clk
clk
+
D
q0 Q
data
clk
CLK
The following data: 100110000 is supplied
to the “data” terminal in nine clock cycles.
After that the values of q2 q1q0 are
(A) 000
(B) 001
(C)
(D) 101
010
GATE ACADEMY®
64
Digital Electronics & Microprocessor 8085 [WB]
Q.23 For the circuit shown, the counter state
(Q1Q0 ) follows the sequence
Q.26 Assuming that all flip-flops are in reset
condition initially, the count sequence
observed at QA in the circuit shown is
Output
DA
D0
Q0
D1
QA
DB
QB
DC
QC
Q1
QA
QB
QC
Clock
CLK
(A) 00, 01, 10, 11, 00 …
(B) 00, 01, 10, 00, 01 …
(C) 00, 01, 11, 00, 01 …
(D) 00, 10, 11, 00, 10 …
Q.24 The figure above shows a 3-bit ripple
counter, with Q2 as MSB. The flip-flop are
(A) 0010111…
(B) 0001011…
(C) 0101111…
(D) 0110100…
Q.27 The minimum number of D flip-flops
needed to design a mod-258 counter is
(A) 9
(B) 8
(C) 512
(D) 258
Q.28 Consider the given circuit.
A
rising-edge trigged. The counting direction
is
1
Clock
Q
J
Q0
J
1
CLK
1
K
Q
Q1
1
J
CLK
Q
K
1
Q
Q2
B
CLK
Q
1
K
Q
(A) always down
(B) always up
(C) up or down depending on the initial state
of Q0 only
(D) up or down depending on the initial
states of Q2 , Q1 and Q0
Q.25 In the figure shown, the initial state Q is 0.
The output is observed after the application
of each clock pulse. The output sequence at
Q is
1
Clock
J
Q
In this circuit, the race around
(A) does not occur.
(B) occurs when CLK = 0.
(C) occurs when CLK = 1 and A = B = 1.
(D) occurs when CLK = 1 and A = B = 0.
Q.29 The digital circuit shown below uses two
negative
edge-triggered
D-flip-flops.
Assuming initial condition of Q1 and Q0 as
zero, the output Q1Q0 of this circuit is
D1
Q1
D0
Q0
D-Flip-Flop
D-Flip-Flop
Q1
Q0
Y
CLK
K
CLK
Q
(A) 0000
(B) 1010
(C) 1111
(D) 1000
Clock
(A) 00, 01, 10, 11, 00 …
(B) 00, 01, 11, 10, 00 …
(C) 00, 11, 10, 01, 00…
(D) 00, 01, 11, 11, 00 …
GATE ACADEMY®
65
Q.30 Consider a 4-bit Johnson counter with an
initial value of 0000. The counting sequence
of this counter is
(A) 0, 1, 3, 7, 15, 14, 12, 8, 0
(B) 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
(C) 0, 2, 4, 6, 8, 10, 12, 14, 0
(C) 0, 8, 12, 14, 15, 7, 3, 1, 0
Q.31 A synchronous counter using two J  K flip
flops that goes through the sequence of
states
:
Q1 Q2  00  10  01  11
 00... is required. To achieve this, the
inputs to the flip flops are
J1
Q1
J2
Q2
K1
Q1'
K2
Q2 '
Sequential Circuits
(A) 010
(B) 101
(C) 011
(D) 110
Q.34 A ripple counter circuit shown in the
following figure uses JK flip flops with
propagation delay of 20 picoseconds each.
The clock signal of shortest pulse width that
can be used to driver the circuit is ps.
1
J0
Q0
J1
CP
K0
Q1
J2
CP
CP
K1
Q0'
Q2
K2
Q1'
Q2'
Q.35 A flip-flop has a delay of 10 n sec. The
clock edge applied to the time the output is
obtained. There is a mod-10 ripple counter
that uses this type of flip-flops. The
maximum delay in output is ______ n sec.
Q.36 Consider the below edge triggered JK flipflops, Present output at Q1Q0 is 00, The
output for next 3 clocks is
Clock
(A) J1  Q2 , K1  0 ; J 2  Q1 ', K 2  Q1
J1
(B) J1  1, K1  1; J 2  Q1 , K 2  Q1
(C) J1  Q2 , K1  Q2 '; J 2  Q2 , K 2  1
CLK
1
(D) J1  Q2 ', K1  Q2 ; J 2  Q21 ', K 2  Q1 '
1
0
J0
Q0
K0
Q0
Q1
(A) 11, 01, 01
(B) 11, 01, 10
(C) 11, 10, 01
(D) 11, 11, 11
Q.37 Consider the circuit shown below. If all the
flip-flops are initially cleared then the count
(Q1 Q2 Q3 ) after 114 clock pulses is?
0
1
K1
0
Q.32 The initial contents of the 4 bit serial-in
parallel out right shift register shown below,
is 1010. After 6 clock pulses are applied, the
content of the shift register will be______.
CLK
Q1
Q.33 Consider the circuit shown below. The
sequence of QA QB QC after 4th clock pulse
1
J1
Q1
K1
Q1
J2
Q2
K2
Q2
J3
Q3
K3
Q3
is [Initially QAQBQC  000 ]
JA
1
KA
QA
QA
1
JB
KB
QB
QB
JC
1
KC
QC
QC
1
1
CLK
(A) 000
(B) 110
(C) 101
(D) 001
Q.38 Determine the counting sequence AB of the
following counter
Digital Electronics & Microprocessor 8085 [WB]
TA
1
TB
2
A
B
GATE ACADEMY®
66
Q.42 On the third clock pulse a 4- bit johnson
sequence is 1110 at Q0 , Q1 , Q2,Q3 , what will
be the initial sequence of the register.
B
A
CLK
(A) 1000
(C) 1110
Q.43 Identify the characteristic equation of X-Y
flip flop whose truth table is given
(A) 00, 01, 10, 11, 00 ….
(B) 00, 01, 10, 00 ….
(C) 00, 10, 11, 00 ….
(D) 00, 10, 01, 11, 00 ….
Q.39 A mod K counter using Asynchronous
Binary up counter with synchronous clear
input is shown below.
LSB
Q0
Q1
6-bit Binary Q2
counter
Q
Clk
100 kHz
X
Y
Q ( n  1)
0
0
0
0
1
Q0
1
0
Qn
1
1
1
(A) XY Q
(B) XY  XQ
(C) XQ  YQ
(D) XY  XQ  YQ
Q.44 Consider the following circuit of a
synchronous counter,
3
Q4
Q5
Clk
(B) 0001
(D) 0011
MSB
D0
Q0
D1
Q0
Q1
D2
Q1
Q2
Q2
CLK
The output frequency in kHz is _______
Q.40 A 4 bit Ripple up counter consists of flipflops that each have a propagation delay of
12ns from clock to output. Amount of time
required for this counter to recycle from
1111 to ‘0000’ (in ns) is ______
Q.41 A 4- bit shift register circuit configured for
right shift operation is shown below. If the
present state of the shift register is ABCD =
1000, the number of pulses required to reach
the state ABCD = 1111 is
CLK
A
B
C
(A) 2
(B) 3
(C) 4
(D) 5
D
Q0
Q1
Q2
If the initial state of the counter is
(Q0Q1Q2 )  (010)
The clock period is 50 ns. The flip-flips are
ideal. Find the MOD number of the counter.

GATE ACADEMY®
67
Sequential Circuits
Answer Keys
Objective & Numerical Answer Type Questions
Flip-Flops
1.
C
2.
C
3.
A
4.
A
5.
A
6.
C
7.
A
8.
B
9.
B
10.
D
11.
B
12.
C
13.
D
14.
D
Synchronous Counter
1.
D
2.
D
3.
B
4.
B
5.
A
6.
C
7.
A
8.
A
9.
B
10.
B
11.
C
12.
D
13.
D
14.
C
15.
C
16.
D
17.
B
18.
D
19.
D
20.
D
21.
A
22.
C
23.
4
24.
C
Asynchronous Counters
1.
B
2.
A
3.
D
4.
A
5.
C
6.
C
7.
D
8.
A
9.
A
10.
B
11.
62.5
12.
7
13.
C
Miscellaneous Questions (FF & Counters)
1.
B
2.
B
3.
0.5
4.
B
5.
C
6.
C
7.
A
8.
C
9.
D
10.
A
11.
3
12.
4
13.
5
14.
C
15.
100
16.
B
17.
*
18.
6
19.
A
20.
C
21.
30
22.
0.8415
23.
A
4.
1.5
5.
B
Shift Registers
1.
C
2.
D
6.
D
7.
C
3.
6
Practice (Objective & Numerical Answer) Questions
1.
B
2.
C
3.
D
4.
R&S
5.
B
6.
D
7.
C
8.
A
9.
10
10.
D
11.
A
12.
B
13.
B
14.
B
15.
B
16.
D
17.
B
18.
D
19.
A
20.
A
21.
B
22.
C
23.
B
24.
A
25.
C
26.
D
27.
D
28.
A
29.
B
30.
C
31.
B
32.
1100
33.
B
34.
57 – 63
35.
38 – 42
36.
A
37.
4
38.
3
39.
5.5
40.
48
41.
3
42.
D
43.
C
44.
5
7
DAC & ADC
Objective & Numerical Ans Type Questions :
Q.1
A student has made a 3-bit binary down
counter and connected to the R-2R ladder
type DAC [Gain  (1k /2 R) ] as shown in
figure to generate a staircase waveform. The
output achieved is different as shown in
figure. What could be the possible cause of
this error? [GATE 2006, IIT Kharagpur]
2R
2R
R
R
2R
2R
R
Q.2
The output of a 3-stage Johnson (twisted
ring) counter is fed to a digital-to-analog
(D/A) converter as shown in the figure
below. Assume all states of the counter to be
unset initially. The waveform which
represents the D/A converter output V0 is
[GATE 2011, IIT Madras]
D/A
Converter
Vref
1 kW
V0
+
Counter
10 kW
(A) V
7
6
5
4
(B) V
0
3
2
1
0
3 4 5 6 7
D0
Q2
Q1
Q0
Johnson
Counter
Clock
– 12V
0
0 1 2
D1
+12V
_
1 kHz
clock
D2
t (ms)
(A) The resistance values are incorrect.
(B) The counter is not working properly.
(C) The connection from the counter to DAC
is not proper.
(D) The R and 2R resistance are interchanged.
(C) V0
V0
GATE ACADEMY®
69
DAC & ADC
(D) V0
Statement for Linked Answer
Questions 4 & 5
In the digital-to-analog converter circuit shown in
the figure below, VR  10 V and R  10 k .
Q.3
A 4-bit D-to-A converter is connected to a
free-running 3-bit UP counter, as shown in the
following figure. Which of the following
waveforms will be observed at V0 ?
VR
2R
R
R
R
2R
2R
2R
i
2R
R
1 kW
Q2
D3
D2
Clock
Q1
D1
Q0
D0
3-bit
Counter
V0
V0
Q.4
1 kW
(A) 31.25 A
4-bit
DAC
In the figure shown above, the ground has
been shown by the symbol
.
[GATE 2007, IIT Kanpur]
(B) 62.5 A
(C) 125 A
Q.5
[GATE 2006, IIT Kharagpur]
(A)
Q.6
(B)
The current i is
(D) 250 A
The voltage V0 is
[GATE 2007, IIT Kanpur]
(A) – 0.781 V
(B) – 1.562 V
(C) – 3.125 V
(D) – 6.250 V
A 2-bit flash Analog to Digital Converter
(ADC) is given below. The input is
0  VIN  3 Volts. The expression for the
LSB of the output B0 as a Boolean function
of X2, X1, and X0 is
[GATE 2016, IISc Bangalore]
3V
100 W
X2
200 W
(C)
X1
B1
Digital
Circuit
200 W
X0
(D)
100 W
VIN
(A) X 0 [ X 2  X 1 ]
(B) X 0 [ X 2  X 1 ]
(C) X 0 [ X 2  X 1 ]
(D) X 0 [ X 2  X 1 ]
B0
Digital Electronics & Microprocessor 8085 [WB]
Q.7
Q.8
Q.9
The number of comparisons carried out in a
4-bit flash type A/D converter is
[GATE 1994, IIT Kharagpur]
(A) 16
(B) 15
(C) 4
(D) 3
The minimum number of comparators
required to build an 8-bit flash ADC is
[GATE 2004, IIT Delhi]
(A) 8
(B) 64
(C) 255
(D) 256
An 8-bit successive approximation analog to
digital converter has full scale reading of
2.55 V and its conversion time for an analog
input of 1 V is 20 μs . The conversion time
for a 2 V input will be
[GATE 2000, IIT Kharagpur]
(A) 10 μs
(B) 20 μs
(C) 40 μs
GATE ACADEMY®
70
Q.11 The stable reading of the LED display is
[GATE 2008, IISc Bangalore]
(A) 06
(B) 07
(C) 12
(D) 13
Q.12 The magnitude of the error between VDAC
and Vin at steady state in volts is
Q.13
Q.14
(D) 50 μs
Q.10 The resolution of a 4-bit counting ADC is
0.5 Volts. For an analog input of 6.6 V, the
digital output of the ADC will be
[GATE 1999, IIT Bombay]
(A) 1011
(B) 1101
(C) 1100
(D) 1110
Q.15
Statement for Linked Answer
Questions 11 & 12
In the following circuit, the comparator output is
logic "1" if V1  V2 and is logic "0" otherwise. The
Q.16
D/A conversion is done as per the relation
3
VDAC   2n 1bn Volt, where b3 (MSB), b2 , b1 and
n0
b0 (LSB) are the counter outputs. The counter starts
Q.17
from the clear state.
VDAC
4 bit D/A
converter
Binary
to
BCD
+5 V
clk
4 bit up
counter
Vin = 6.2 V
Clock
2 Digit
LED
Display
Q.18
[GATE 2008, IISc Bangalore]
(A) 0.2
(B) 0.3
(C) 0.5
(D) 1.0
Consider a four bit D to A converter. The
analog value corresponding to a digital
signals of values 0000 and 0001 are 0 V and
0.0625 V respectively. The analog value (in
Volts) corresponding to the digital signal
1111 is _____. [GATE 2015, IIT Kanpur]
1
For a dual slope 3
digit DVM, the
2
reference voltage is 100 mV and the first
integration time is set to 300 ms. For same
input voltage the deintegration period is
370.2 ms. The DVM will indicate (in mV)
(A) 123.4
(B) 199.9
(C) 100.0
(D) 1.414
In a dual slope integrating time digital
voltmeter for integration is carried for 10
periods of the supply frequency 50 Hz. If the
reference voltage used is 2 V, the total
conversion time for an input 1 V is ______
sec.
A digital-to-analog converter with a fullscale output voltage of 3.5 V has a
resolution close to 14 mV. Its bit size is
[GATE 2005, IIT Bombay]
____.
The full scale input voltage to an ADC is 10
V. The resolution required is 5 mV. The
minimum number of bits required for ADC
is
[GATE 1998, IIT Delhi]
(A) 8
(B) 10
(C) 11
(D) 12
The circuit shown in the figure below works
as a 2-bit analog to digital converter for
0  Vin  3 V
GATE ACADEMY®
71
DAC & ADC
Start of conversion
(SOC)
3V
0.5 kW
–
Input Comparator
sample
X3
Control
logic
+
1.0 kW
–
X2
+
1.0 kW
–
Y1
Digital
Circuit
Reset
Clock
Y0
R-2R
Ladder
DAC
X1
Up
counter
+
0.5 kW
Vref
Vin
Output buffer
Enable
The MSB of the output Y1 expressed as a
Boolean function of the inputs X 1 , X 2 , X 3 is
[GATE 2007, IIT Kanpur]
given by
End of
conversion
(EOC)
(A) Directly proportional to Vref
(A) X 1
(B) X 2
(B) Inversely proportional to Vref
(C) X 3
(D) X 1  X 2
(C) Independent of Vref
Q.19 An 8-bit unipolar successive approximation
register type ADC is used to convert 3.5 V
to digital equivalent output. The reference
voltage is + 5 V. The output of ADC, at the
end of 3rd clock pulse after the start of
conversion is [GATE 2015, IIT Kanpur]
(A) 1010 0000
(B) 1000 0000
(C) 0000 0001
(D) 0000 0011
Q.20 The circuit in the figure represents a
counter-based unipolar ADC. When SOC is
asserted the counter is reset and clock is
enabled so that the counter counts up and the
DAC output grows. When the DAC output
exceeds the input sample value, the
comparator switches from logic 0 to logic 1,
disabling the clock and enabling the output
buffer by asserting EOC. Assuming all
components to be ideal, Vref , DAC output
and input to be positive, the maximum error
in conversion of the analog sample value is
[GATE 2014, IIT Kharagpur]
(D) Directly proportional to clock frequency
Q.21 Integrated output waveform for the dual
slope ADC is shown in the figure. The time
T for an 8 bit counter with 4 MHz clock will
be
[GATE 1998, IIT Delhi]
V
T
(A) 0.032 ms
(B) 0.064 ms
(C) 0.64 ms
(D) 0.024 ms
Q.22 In a dual slope ADC, the reference voltage
is 100 mV and the first integration period is
set as 50 ms. The input resister of the
integrator is 100 k  and the integrating
capacitor 0.04 F. For an input voltage of
120 mV, the second integration (deintegration) period will be
[GATE 2003, IIT Madras]
(A) 50 ms
(B) 60 ms
(C) 100 ms
(D) 120 ms
Q.23 A 4-bit successive approximation type ADC
has a full scale value of 15 V. The sequence
Digital Electronics & Microprocessor 8085 [WB]
of the states, the SAR will traverse, for the
conversion of an input of 8.15 V is
[GATE 2010, IIT Guwahati]
(A)
End
Conversion
(B)
GATE ACADEMY®
72
Q.24 For the 4-bit DAC shown in figure, the
output voltage V0 is
[GATE 2000, IIT Kharagpur]
7 kW
1 kW
End
Conversion
+15 V
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
Start
Conversion
Start
Conversion
1
0
0
End
Conversion
(D)
End
Conversion
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
Start
Conversion
Start
Conversion
R
R
2R
2R
2R
-15 V
2R
2R
1V
1V
(A) 10 V
(B) 5 V
(C) 4 V
(D) 8 V
Q.25 Consider
the
4-bit
digital-to-analog
converter shown in figure where the logic
levels 0 and 1 are 0.4 V and 2.4 V
respectively. The analog output (V0 ) for an
input of 1001 is _______.
[GATE 1995, IIT Kanpur]
2R
R
R
2R
R
–
+
2R
(C)
V0
R
2R
2R
2R
2R
B0
LSB
B1
B2
B3
MSB
V0
Common Data for
Questions 26 & 27
R
2R
2R
R
2R
S0
+
V
- 0
2R
S1
S2
+5V
-
An R-2R ladder type DAC is shown below. If a
switch status is ‘0’, 0 V is applied and if a switch
status is ‘1’, 5 V is applied to the corresponding
terminal of the DAC.
[GATE 2006, IIT Kharagpur]
Q.26 What is the output voltage (V0 ) for the
switch status S 0  0 , S1  1 , S2  1 ?
GATE ACADEMY®
5
15
(A) V
(B) V
4
4
17 .4
22.5
(C)
(D)
V
V
4
4
Q.27 What is the step size of the DAC?
(A) 0.125 V
(B) 0.525 V
(C) 0.625 V
(D) 0.75 V
Practice (objective & Num Ans) Questions :
Q.1
Q.2
Q.3
Q.4
Q.5
Q.6
Q.7
The resolution of an 8-bit A/D converter is
_______ %.
The number of comparators needed in a
parallel conversion type 8-bit A/D converter
is
(A) 8
(B) 16
(C) 255
(D) 256
The percent resolution of a 10 bit D/A
converter is ________
For an ADC, match the following :
List - I
(A) Flash converter
(B) Dual slope converter
(C) Successive approximation converter
List - II
(1) requires a conversion time of the order
of a few seconds.
(2) requires a digital to analog converter.
(3) minimizes the effect of power supply
interference.
(4) requires a very complex hardware.
(5) is a tracking A/D converter.
The advantage of using a dual slope ADC in
a digital voltmeter is that
(A) its conversion time is small.
(B) its accuracy is high.
(C) it gives output in BCD format.
(D) it does not require a comparator.
Percent resolution of an 8 bit D/A converter
is
(A) 0.39
(B) 0.78
(C) 2.56
(D) None of these
The number of comparators in a 4-bit flash
DC is
(A) 4
(B) 5
(C) 15
(D) 16
73
DAC & ADC
Q.8
Among the following four, the slowest ADC
(analog-to-digital converter) is
(A) Parallel-comparator (i.e. flash) type
(B) Successive approximation type
(C) Integrating type
(D) Counting type
Q.9 The number of comparators required in a 3bit comparator type ADC is
(A) 2
(B) 3
(C) 7
(D) 8
Q.10 The minimum number of comparators
required to build an 8-bit flash ADC is
(A) 8
(B) 63
(C) 255
(D) 256
Q.11 The number of comparators required for
implementing an 8-bit flash analog-to-digital
converter is
(A) 8
(B) 128
(C) 255
(D) 256
Q.12 A 6 bit successive approximation type A/D
converter has an input range of 0 to 63 volts.
The MSB output (b5 ) has a stuck at zero
fault. The pair of input voltages that
produces the same output code word is
(A) 16 V and 20 V
(B) 32 V and 2 V
(C) 40 V and 2 V
(D) 40 V and 8 V
Q.13 In a 3 bit counter type A/D converter,
resolution is 0.25 volt. The digital output for
1.13 volts analog input is
(A) 011
(B) 100
(C) 110
(D) 101
Q.14 A 12 bit digital to analog converter has a
step size of 10 mV. The full scale output
voltage and percentage of resolution are
respectively
(A) 40.95 V and 0.024%
(B) 40 V and 0.015%
(C) 41 V and 0.024%
(D) 50 V and 0.015%
Q.15 The percentage resolution 10 bit Analog to
Digital converter is _______.
(A) 1 volt
(B) 0.9 volt
(C) 0.098 volt
(D) 0.0098 volt
GATE ACADEMY®
74
Digital Electronics & Microprocessor 8085 [WB]
Q.16 A 4 bit successive Approximation ADC has
an input voltage range of 0 to 15 vols. The
sequence of states the successive
Approximation ADC will traverse for the
analog input of 13.26 volts is
(A) 1000  1100  1110  1111  1111
(B) 1000  1100  1110  1101  1101
Q.18 The Boolean function realized by the logic
circuit shown is
10V
5V
5V
4k
5 V
3k
I2
2k
1k
size of DAC is 1 volt. The output voltage for
next 6 clock pulses is
Rf
clk
MSB
QA
D3
QB
D2
QC
D1
D0
QD
4 bit
DAC
Vout
Y0
I1
(D) 1000  1100  1110  1101  1100
Q.17 In the diagram below, initial value of Ring
counter at QAQB QC QD  1000 and the step
x0
4:1
MUX
5 V
(C) 1000  1100  1110  1111  1111
4 bit
Ring
counter
I0
S1
S0
A
B
C
(A) AC
(B) AB
(C) A  B
(D) BC
Q.19 A 10-bit digital to analog converter has a
full scale output voltage of 20 V. What will
be the value of the output voltage (in volt) if
the input code is 0101101011?
(A) 8 V, 4 V, 2 V, 0 V, 8 V, 4 V

(B) 8 V, 4 V, 2 V, 1 V, 8 V, 4 V
(C) 1 V, 2 V, 4 V, 8 V, 1 V, 2 V
(D) 1 V, 2 V, 4 V, 8 V, 0 V, 2 V
Answer Keys
Objective & Numerical Answer Type Questions
1.
C
2.
A
3.
B
4.
B
5.
C
6.
A
7.
B
8.
C
9.
B
10.
D
11.
D
12.
B
13.
0.9375
14.
A
15.
0.3
16.
8
17.
C
18.
B
19.
A
20.
A
21.
B
22.
B
23.
A
24.
B
25.
–1
26.
B
27
C
Practice (Objective & Numerical Answer) Questions
1.
0.392
2.
C
3.
0.1
4.
A-4, B3, C-2
5.
B
6.
A
7.
C
8.
C
9.
C
10.
C
11.
C
12.
D
13.
D
14.
A
15.
C
16.
B
17.
A
18.
D
19.
7.1
8
Microprocessor 8085
Objective & Numerical Ans Type Questions :
Date Transfer, Arithmetic and logical
instruction set
Q.1
In 8085 A microprocessor, the operation
performed by the instruction LHLD 2100 H
is
Q.5
[GATE 2014, IIT Kharagpur]
(A) (H)  21 H, (L)  00 H
(B) (H)  M(2100 H), (L)  M(2101 H)
(C) (H)  M(2101 H), (L)  M(2100 H)
(D) (H)  00 H, (L)  21 H
Q.2
Q.3
The following instruction copies a byte of
data from the accumulator into the memory
address given in the instruction
(A) STA address
(B) LDAX B
(C) LHLD address
(D) LDA address
Q.6
If 8085 microprocessor adds 87 H and 79 H,
the flags will be :
(A) S = 1, Z = 0, AC = 0 and Cy = 1
(B) S = 0, Z = 0, AC = 1 and Cy = 0
(C) S = 1, Z = 1, AC = 1 and Cy = 1
(D) S = 0, Z = 1, AC = 1 and Cy = 1
Q4
In an 8085 A microprocessor based system,
it is desired to increment the contents of
memory location whose address is available
in (D, E) register pair and store the result in
same location. The sequence of instruction
is
[GATE 2006, IIT Kharagpur]
Q.7
(A) XCHG
(B) XCHG
INR M
INX H
(C) INX D
(D) INR M
XCHG
XCHG
The following FIVE instructions were
executed on an 8085 microprocessor.
MVI A, 33 H
MVI B, 78 H
ADD B
CMA
ANI 32 H
The Accumulator value immediately after
the execution of the fifth instruction is
[GATE 2017, IIT Roorkee]
(A) 00 H
(B) 10 H
(C) 11 H
(D) 32 H
In an 8085 microprocessor, the content of
the accumulator and the carry flag are A7 (in
hex) and 0, respectively. If the instruction
RLC is executed, then the content of the
accumulator (in hex) and the carry flag,
respectively, will be
[GATE 2016, IISc Bangalore]
(A) 4E and 0
(B) 4E and 1
(C) 4F and 0
(D) 4F and 1
The contents of Accumulator are 7 OH.
Initially all flags are zero. What will be
values of Cy and S after executing
instruction RLC?
(A) Cy = 0 and S = 0 (B) Cy = 1 and S = 1
(C) Cy = 1 and S = 0 (D) Cy = 0 and S = 1
Digital Electronics & Microprocessor 8085 [WB]
Q.8
What is the content of accumulator of 8085
 p after the execution of XRIFOH
instruction?
(A) Only the lower nibble of accumulator is
complemented
(B) Only the lower nibble is complemented
(C) Only the upper nibble is reset to zero
(D) Only the lower nibble is reset to zero
Q.9 Find the content of the accumulator after the
execution of the following program
MVI
A, FO H
ORI
FF H
XRI
FO H
(A) OOH
(B) FOH
(C) OFH
(D) FFH
Q.10 Assume that the Accumulator and the
register C of 8085 microprocessor contain
respectively FO H OF H initially. What will
be the content of Accumulator after
execution of instruction ADD C?
(A) OO H
(B) FF H
(C) EF H
(D) FE H
Q.11 An 8085 assembly language program is
given below. Assume that the carry flag is
initially unset. The content of the
accumulator after the execution of the
program is
[GATE 2011, IIT Madras]
MVI A, 07 H
RLC
MOV B, A
RLC
RLC
ADD B
RRC
(A) 8C H
(B) 64 H
(C) 23 H
(D) 15 H
Statement for Linked Answer
Questions 12 & 13
An 8085 assembly language program is given
below.
[GATE 2007, IIT Kanpur]
GATE ACADEMY®
76
Line
1 : MVI A, B5 H
2 : MVI B, 0E H
3 : XRI 69 H
4 : ADD B
5 : ANI 9B H
6 : CPI 9F H
7 : STA 3010 H
8 : HLT
Q.12 The contents of the accumulator just after
execution of the ADD instruction in line 4
will be
(A) C3 H
(B) EA H
(C) DC H
(D) 69 H
Q.13 After execution of line 7 of the program, the
status of the CY and Z flags will be
(A) CY = 0, Z = 0
(B) CY = 0, Z = 1
(C) CY = 1, Z = 0
(D) CY = 1, Z = 1
Q.14 Consider the sequence of 8085 instructions
given below,
LXI H, 9258 H
MOV A, M
CMA
MOV M, A
Which one of the following is performed by
this sequence?
[GATE 2004, IIT Delhi]
(A) Contents of location 9258H are moved
to the accumulator.
(B) Contents of location
9258H
are
compared with the contents of the
accumulator.
(C) Contents of location 9258H are
complemented and stored in location
9258H .
(D) Contents
of
location
5892H
are
complemented and stored in location
5892H .
Q.15 The following 8085 instructions
executed sequentially.
PROG XRA
A
MOV
L, A
MOV
H, L
INX
H
DAD
H
are
GATE ACADEMY®
After execution, the content of HL register
pair is
[GATE 2004, IIT Delhi]
(A) 0000 H
(B) 0101 H
(C) 0001 H
(D) 0002 H
Q.16 The following program is written for an
8085 microprocessor to add two bytes
located at memory addresses 1FFE H and
1FFF H
[GATE 2003, IIT Madras]
LXI
H, 1FFE H
MOV
B, M
INR
L
MOV
A, M
ADD
B
INR
L
MOV
M, A
XRA
A
On completion of the execution of the
program, the result of addition is found
(A) in the register A.
(B) at the memory address 1000 H.
(C) at the memory address 1F00 H.
(D) at the memory address 2000 H.
Q.17 In an 8085 microprocessor, the instruction
CMP B has been executed while the content
of the accumulator is less than that of
register B. As a result
[GATE 2003, IIT Bombay]
(A) carry flag will be set but Zero flag will
be reset.
(B) carry flag will be reset but Zero flag will
be set.
(C) both Carry flag and Zero flag will be
reset.
(D) both Carry flag and Zero flag will be set.
Q.18 The contents of register (B) and accumulator
(A) of 8085 microprocessor are 49 H and 3A
H respectively. The contents of A and the
status of carry flag (CY) and sign flag (S)
after executing SUB B instructions are
[GATE 2000, IIT Kharagpur]
(A) A = F1 H, CY = 1, S = 1
(B) A = 0F H, CY = 1, S = 1
77
Microprocessor 8085
(C) A = F0 H, CY = 0, S = 0
(D) A = 1F H, CY = 1, S = 1
Branch Group and Stack Group Instruction set
Q.1
Q.2
Q.3
In an 8085 microprocessor, the following
program is executed.
Address location – Instruction
2000 H
XRA A
2001 H
MVI B, 04 H
2003 H
MVI A, 03 H
2005 H
RAR
2006 H
DCR B
2007 H
JNZ 2005
200A H
HLT
At the end of program, register A contains
[GATE 2014, IIT Kharagpur]
(A) 60 H
(B) 30 H
(C) 06 H
(D) 03 H
For 8085 microprocessor, the following
program is executed.
MVI A, 05 H;
MVI B, 05 H;
PTR :
ADD B;
DCR B;
JNZ PTR;
ADI 03 H;
HLT;
At the end of program, accumulator contains
[GATE 2013, IIT Bombay]
(A) 17 H
(B) 20 H
(C) 23 H
(D) 05 H
In an 8085 microprocessor the value of stack
pointer (SP) is 2010 H and that of DE
register pair is 1234 H before the following
code is executed. The value of the DE
register pair after the following code is
executed
[GATE 2005, IIT Bombay]
LXI H, 0000 H
PUSH H
PUSH H
POP B
DAD SP
XCHG
Digital Electronics & Microprocessor 8085 [WB]
Q.4
Q.5
(A) 200E H
(B) 200C H
(C) 2010 H
(D) 1232 H
Following is the segment of a 8085
assembly language program :
LXI SP, EFFF H
CALL 3000 H
3000 H : LXI H, 3CF4 H
PUSH PSW
SPHL
POP PSW
RET
On completion of RET execution, the
contents of SP is
[GATE 2006, IIT Kharagpur]
(A) 3CF0 H
(B) 3CF8 H
(C) EFFD H
(D) EFFF H
The following sequence of instructions are
executed by an 8085 micro-processor:
Memory address
Instruction
in HEX
1000 H
LXI SP, 27FF H
1003 H
CALL 1006 H
1006 H
POP H
The contents of the stack pointer (SP) and
the HL register pair on completion of
execution of these instructions are,
Q.6
[GATE 1996, IISc Bangalore]
(A) SP = 27FF H, HL = 1003 H
(B) SP = 27FD H, HL = 1003 H
(C) SP = 27FF H, HL = 1006 H
(D) SP = 27FD H, HL = 1006 H
What will be the content of HL register pair
after execution of following instructions ?
______________ H.
Label :
Mnemonics
LXI H, 6876 H
SUB A
MVI D, 0F H
LOOP :
MOV M, A
INX H
DCR D
JNZ LOOP
HLT
78
GATE ACADEMY®
. Common Data Questions 7 to 100
An 8085 assembly language program is
given below :
Label :
Mnemonics
MVI C, 03 H
LXI H, 2000 H
MOV A, M
DCR C
LOOP1 :
INX H
MOV B, M
CMP B
JNC LOOP2
MOV A, B
LOOP2 :
DCR C
JNZ LOOP1
STA 2001 H
HLT
Contents of the memory location 2000 H to
2002 H are :
2000 H : 18 H
2001 H : 10 H
2002 H : 2B H
Q.7 The content of the register C is :
(A) 2B H
(B) 20 H
(C) 00 H
(D) 02 H
Q.8 The condition of the carry and zero flags are
(A) CY = Set, Z = Reset
(B) CY = Set, Z = Set
(C) CY = Reset, Z = Reset
(D) None of these
Q.9 The content of the memory location 2100 H
is
(A) 00 H
(B) 2B H
(C) 01 H
(D) None of these
Q.10 The content of the register A is
(A) 00 H
(B) 2B H
(C) 01 H
(D) None of these
Q.11 What is the result of the following 8085
code?
LDA 8C00 H
CMA
INR A
STA 8C01 H
HLT
GATE ACADEMY®
(A) 1's complement of the number stored in
8C01 H
(B) 2's complement of the number is stored
in 8C01 H
(C) Incremented number stored in 8C01 H
(D) None of these
Q.12 The following is an assembly language
program for 8085 microprocessors:
[GATE 2009, IIT Roorkee]
Address Instruction Mnemonic
1000H
3E 06
MVI A 06H
1002H
C6 70
ADI 70H
1004H
32 07 10
STA 1007H
1007H
AF
XRA
1008H
76
HLT
When this program halts, the accumulator
contains
(A) 00H
(B) 06H
(C) 70H
(D) 76H
Q.13 An 8085 executes the following instructions
2710 H
LXI H, 30A0 H
2713 H
DAD H
2714 H
PCHL
All addresses and constants are in Hex. Let
PC be the contents of the program counter
and HL be the contents of the HL register
pair just after executing PCHL.
Which of the following statements is
correct?
[GATE 2008, IISc Bangalore]
(A) PC = 2715 H
HL = 30A0 H
(B) PC = 30A0 H
HL = 2715 H
(C) PC = 6140 H
HL = 6140 H
(D) PC = 6140 H
HL = 2715 H
Q.14 A portion of the main program to call a
subroutine SUB in an 8085 environment is
given below as
:
LXI D, DISP
LP :
CALL SUB
:
:
79
Microprocessor 8085
It is desired that control be returned to LP +
DISP + 3 when the RET instruction is
executed in the subroutine. The set of
instructions that precede the RET
instructions in the subroutine are
[GATE 2011, IIT Madras]
(A) POP D
DAD H
PUSH D
(B) POP H
DAD D
INX H
INX H
INX H
PUSH H
(C) POP H
DAD D
PUSH H
(D) XTHL
INX D
INX D
INX D
XTHL
Q.15 In a 8085 processor, the main program calls
the subroutine SUB1 given below. When the
program returns to the main program after
executing SUB1, the value in the
accumulator is
Address Opcode Mnemonic
2000
3E00
SUB1 : MVI A, 00H
2002
CD 05 20 CALL SUB2
2005
3C
SUB2 : INR A
2006
C9
RET
Accumulator for A  00 increases and
finally
[GATE 2010, IIT Guwahati]
(A) 00
(B) 01
(C) 02
(D) 03
Q.16 Consider the following assembly language
program
[GATE 2002, IISc Bangalore]
MVI B, 87 H
MOV A, B
Digital Electronics & Microprocessor 8085 [WB]
START : JMP NEXT
MVI B, 00 H
XRA B
OUT PORT 1
HLT
NEXT : XRA B
JP
START
OUT PORT 2
HLT
The execution of the above program in an
8085 microprocessor will result in
(A) an output of 87 H at PORT 1.
(B) an output of 87 H at PORT 2.
(C) infinite looping of the program
execution with accumulator data
remaining at 00 H.
(D) infinite looping of the program
execution with accumulator data
alternating between 00 H and 87 H.
Q.17 8-bit signed integers in 2's complement form
are read into the accumulator of an 8085
microprocessor from an I/O port using the
following assembly language program
segment with symbolic addresses.
[GATE 2007, IIT Madras]
Label :
Mnemonics
BEGIN :
IN PORT
RAL
JNC BEGIN
RAR
END :
HLT
This program :
(A) Halts upon reading a negative number
(B) Halts upon reading a positive number
(C) Halts upon reading a zero
(D) Never halts
Q.18 Consider the following set of 8085
instruction
MVI A, 92 H
ORA A
JP DSPLY
XRA A
DSPLY :
OUT PORT 1
HLT
GATE ACADEMY®
80
The output at PORT 1 is
(A) 00 H
(B) FF H
(C) 92 H
(D) None of these
Q.19 Content of accumulator after the execution
of following instructions will be
MVI A, 55 H
MVI C, 25 H
ADD C
DAA
(A) 7A H
(B) 80 H
(C) 50 H
(D) 22 H
Q.20 The following instructions have
executed by an 8085 microprocessor.
Memory address
in HEX
Instruction
6010 H
LXI H, 8A79 H
6013 H
MOV A, L
6014 H
ADD H
6015 H
DAA
6016 H
MOV H, A
6017 H
PCHL
been
From which address will the next instruction
be fetched?
[GATE 1997, IIT Madras]
(A) 6019 H
(B) 0379 H
(C) 6979 H
(D) None of the above
Q.21 A part of a program written for an 8085
microprocessor is shown below. When the
program execution reaches LOOP2, the
value of register C will be ______________
H.
[GATE 2008, IISc-Bangalore]
SUB A
MOV C,A
LOOP 1 :
INR A
DAA
JC LOOP 2
INR C
JNC LOOP 1
LOOP 2 :
NOP
GATE ACADEMY®
81
Microprocessor 8085
Machine Cycle
Q.1
Q.2
Q.3
Q.4
Q.5
Q.6
Q.7
How many machine cycles are required by
STA instruction?
(A) 2
(B) 3
(C) 4
(D) 5
The number of memory cycles required to
execute the following 8085 instructions
(I) LDA, 3000 H
(II) LXI D, F0F1 H
would be
[GATE 2004, IIT Delhi]
(A) 2 for (I) and 2 for (II).
(B) 4 for (I) and 3 for (II).
(C) 3 for (I) and 3 for (II).
(D) 3 for (I) and 4 for (II).
The total number of memory accesses
involved (inclusive of the op-code fetch)
when an 8085 processor executes the
instruction LDA 2003 H is
[GATE 1996, IISc Bangalore]
(A) 1
(B) 2
(C) 3
(D) 4
Number of machine cycles required to
execute the following instructions in the
correct increasing order
1. NOP
2. ADI Data
3. STA Address
4. SHLD Address
(A) 1, 2, 3, 4
(B) 1, 3, 4, 2
(C) 4, 3, 2, 1
(D) 1, 3, 2, 4
Execution times of the instruction of 8085
shown below are in the order of ……
a) LDAX
b) ORA
c) XTHL
d) PUSH
(A) c > a > d > b
(B) a > d > b > c
(C) c > d > a > b
(D) b > a > d > c
Which of the following 8085 instruction will
require maximum T-states for execution?
(A) XRI byte
(B) STA address
(C) CALL address
(D) JMP address
In an 8085 microprocessor, which one of the
following is the correct sequence of the
machine cycles for the execution of the
DCR M instruction?
[GATE 2005, IIT Bombay]
Q.8
(A) op-code fetch
(B) op-code fetch, memory read, memory
write
(C) op-code fetch memory read
(D) op-code fetch, memory write, memory
write
The clock frequency of an 8085
microprocessor is 5 MHz. If the time
required to execute an instruction is
1.4 sec, then the number of T-states
needed for executing the instruction is
[GATE 2017, IIT Roorkee]
(A) 1
(B) 6
(C) 7
(D) 8
Q.9 An 8085 assembly language program is
given as follows. The execution time of each
instruction is given against the instruction in
terms of T-state.
Instruction
T-states
…………...
………..
MVI B, 0AH
7T
LOOP : MVI C, 05H
7T
DCR C
4T
DCR B
4T
JNZ LOOP
10T/7T
The execution time of the program in terms
of T-states is
(A) 247 T
(B) 250 T
(C) 254 T
(D) 257 T
Q.10 An Intel 8085 processor is executing the
program given below.
[GATE 2001, IIT Kanpur]
MVI A, 10 H
MVI B, 10 H
BACK :
NOP
ADD B
RLC
JNC BACK
HLT
The number of times that the operation NOP
will be executed is equal to
Digital Electronics & Microprocessor 8085 [WB]
(A) 1
(B) 2
(C) 3
(D) 4
Q.11 An 8085 microprocessor executes “STA
1234 H” with starting address location 1FFE
H (STA copies the contents of the
Accumulator to the 16-bit address location).
While the instruction is fetched and
executed, the sequence of values written at
the address pins A15 - A8 is
[GATE 2014, IIT Kharagpur]
(A) 1F H, 1F H, 20 H, 12 H
(B) 1F H, FE H, 1F H, FF H, 12 H
(C) 1F H, 1F H, 12 H, 12 H
(D) 1F H, 1F H, 12 H, 20 H, 12 H
Q.12 A software delay subroutine is written as
given below
[GATE 2006, IIT Kharagpur]
DELAY :
MVI H, 255 D
MVI L, 255 D
LOOP :
DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR L instruction will be
executed?
(A) 255
(B) 510
(C) 65025
(D) 65279
GATE ACADEMY®
82
Q.4
Q.5
Q.6
Interrupts
Q.1
Q.2
Q.3
The number of hardware interrupts (which
require an external signal to interrupt)
present in an 8085 micro-processor are
[GATE 2000, IIT Kharagpur]
(A) 1
(B) 4
(C) 5
(D) 13
The vectored address corresponding to the
software interrupt command RST 7 in 8085
microprocessor is [GATE 2004, IIT Delhi]
(A) 0017 H
(B) 0027 H
(C) 0038 H
(D) 0700 H
In the 8085 microprocessor, the RST 6
instruction transfers the program execution
to the following location :
[GATE 2000, IIT Kharagpur]
(A) 30 H
(B) 24 H
(C) 48 H
(D) 60 H
Which of the following is not a vectored
interrupt?
(A) TRAP
(B) INTR
(C) RST 7.5
(D) RST 3
In a microprocessor, the service routine for a
certain interrupt starts from a fixed location
of memory which can not be externally set,
but the interrupt can be delayed or rejected.
Such an interrupt is
[GATE 2009, IIT Roorkee]
(A) non-maskable and non-vectored.
(B) maskable and non-vectored.
(C) non-maskable and vectored.
(D) maskable and vectored.
Three devices A, B and C have to be
connected to a 8085 microprocessor. Device
A has highest priority and device C has the
lowest priority. In this context which of the
following is correct statement of interrupt
inputs?
[GATE 1993, IIT Bombay]
(A) A uses TRAP, B uses RST 5.5 and C
uses RST 6.5
(B) A uses RST 7.5, B uses RST 6.5 and C
uses RST 5.5
(C) A uses RST 5.5, B uses RST 6.5 and C
uses RST 7.5
(D) A uses RST 5.5, B uses RST 6.5 and C
uses TRAP.
Memory & Memory Interfacing
Q.1
Q.2
Q.3
Q.4
In 16 KB of RAM, the starting memory
location is ABCD H. find the last memory
location is
In 8 KB or RAM, the starting memory
location is A000 H find the last memory
location
In 2 KB of external RAM, last memory
location ABCD H. Find starting memory
location
In 32 KB of external RAM, last memory
location F000 H. Find starting memory
location
GATE ACADEMY®
Q.5
Q.6
Q.7
Q.8
Q.9
83
If starting and last location of external RAM
is 8000 H and 9FFF H, find
(i) Size of the RAM
(ii) Number of bytes in RAM
(iii)Number of bits in RAM
An 8085 microprocessor based system uses
a 4 K  8 bit RAM whose starting address is
AA00 H. The address of the last byte in this
RAM is
[GATE 2001, IIT Kanpur]
(A) 0FFF H
(B) 1000 H
(C) B9FF H
(D) BA00 H
An 8K  8 bit RAM is interfaced to an 8085
microprocessor. In a fully decoded scheme
if the address of the last memory location of
this RAM is 4FFFH, the address of the first
memory location of the RAM will be
[GATE 2011, IIT Madras]
(A) 1000H
(B) 2000H
(C) 3000H
(D) 4000H
A 2 K  8 bit is interfaced to an 8-bit
microprocessor. If the address of the first
memory location in the RAM is 0800H, the
address of the last memory location will be
[GATE 2008, IISc Bangalore]
(A) 1000 H
(B) 0FFF H
(C) 4800 H
(D) 47FF H
How many address and data lines are needed
for a memory of 4K 16 ?
(A) 10, 16
(B) 11, 8
(C) 12, 16
(D) 16, 12
Q.10 The number of bits needed to address 4 K
memory is ______________ .
(A) 6
(B) 8
(C) 12
(D) 16
Q.11 The address bus width of a memory of size
2048  8 bits is ______________ .
Q.12 In a microprocessor with 16 address and 12
data lines, the maximum number of opcodes
is
[GATE 2001, IIT Kanpur]
(A) 26
(B) 28
(C) 212
(D) 216
Microprocessor 8085
Q.13 A memory system of size 32 kbytes is
required to be designed using memory chips
which have 12 address lines and 4 data lines
each. What is the number of such chips
required to design the memory system ?
____________ H.
Q.14 How many 64 K x 4 RAM chips are needed
to form a 1 M x 4 memory module ?
(A) 4
(B) 5
(C) 8
(D) 16
Q.15 A memory system has a total of 8 memory
chips, each with 12 address lines and 4 data
lines. The total size of the memory system is
(A) 16 k bytes
(B) 32 k bytes
(C) 48 k bytes
(D) 64 k bytes
Q.16 An 8-bit microprocessor has 16-bit address
bus A0 - A15 . The processor has a 1 KB
memory chip as shown. The address range
for the chip is
[GATE 1988, IIT Kharagpur]
A15
A14
A13
A0 - A9
0
1
2
3
4
5
6
7
CS
A12
A11
A10
1 K ´8
RAM
CS
8
Data
lines
(A) F00F H to F40E H
(B) F100 H to F4FF H
(C) F000 H to F3FF H
(D) F700 H to FAFF H
Q.17 In the circuit shown, the device connected to
Y5 can have address in the range
[GATE 2010, IIT Guwahati]
A8
A9
A10
A
B
C
Y5
74LS138
3-to-8 decoder
A11
A12
A13
A14
A15
G2 B
IO/M
G1
G2 A
VCC
GND
To device
chip select
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
84
(A) 2000 H - 20FF H (B) 2D00 H - 2DFF H
(C) 2E00 H - 2EFF H (D) FD00 H - FDFF H
Q.18 The range of addresses for which the
memory chip shown in figure, will be
selected is _____ to _____.
[GATE 1997, IIT Madras]
A15
A14
A13
A12
A11
memory module is connected to the y5
output of a 3 to 8 decoder with active low
outputs. S0 , S1 , and S2 are the input lines to
the decoder, with S2 as the MSB. The
decoder has one active low EN1 and the
active high EN 2 enable lines as shown
below. The address range (s) that gets
mapped onto this memory module is/are
[GATE 2016, IISc Bangalore]
CS
Q.19 The logic circuit used to generate the active
low chip select (CS) by an 8085
microprocessor to address a peripheral is
shown in figure. The peripheral will respond
to addresses in the figure.
[GATE 2002, IIT Kharagpur]
A15
A14
A13
A12
A12 A13 A14
A11
EN 2
A10
EN1
y0
y1
S0
S1
S2
y2
y3
y4
y5
y6
CS
CS
(A) 3000 H to 33FF H and E000 H to
E3FF H
(A) E000-EFFF
(B) 000E-FFFE
(C) 1000-FFFF
(D) 0001-FFF1
Q.20 A ROM is interfaced to an 8085 CPU as
indicated in figure. The address range
occupied by the ROM is
[GATE 2003, IIT Madras]
(B) 1400 H to 17FF H
(C) 5300 H to 53FF H and A300 H to
A3FF H
(D) 5800 H to 5BFF H and D800 H to
DBFF H
Q.22 There are four chips each of 1024 byte
connected to a 16 bit address bus as shown
in the figure below. RAMs 1, 2, 3 and 4
respectively are mapped to addresses
[GATE 2013, IIT Bombay]
RAM#4
1024B
A9 of the processor are connected to the
corresponding address lines of the memory.
The active low chip select CS of the
RAM#3
1024B
E
A0 - A9
RAM#2
1024B
E
A10
A11
A12
A13
A14
A15
RAM#1
1024B
E
input
(A) 0000 H – 0FFF H
(B) 0000 H – 1FFF H
(C) 0000 H – 2FFF H
(D) 8000 H – 9FFF H
Q.21 A 1 Kbyte memory module has to be
interfaced with an 8-bit microprocessor that
has 16 address lines. The address lines A0 to
S1
S0
11
10
01
00
8 bit data bus
E
GATE ACADEMY®
85
(A) 0C00 H - 0FFF H, 1C00 H -1FFF H,
2C00 H - 2FFF H, 3C00 H - 3FFF H
(B) 1800 H - 1FFF H, 2800 H - 2FFF H,
3800 H - 3FFF H, 4800 H - 4FFF H
(C) 0500 H - 08FF H, 1500 H - 18FF H,
3500 H - 38FF H, 5500 H - 58FF H
(D) 0800 H - 0BFF H, 1800 H - 1BFF H,
2800 H - 2BFF H, 3800 H - 3BFF H
Q.23 An 8255 chip is interfaced to an 8085
microprocessor system as an I/O mapped I/O
as shown in the figure. The address lines A0
A1
A0
from an external device is shown in the
figure. The instruction for correct data
transfer
[GATE 2014, IIT Kharagpur]
3-to-8
Decoder
C
A1
B
A0
A
G2 A
G2 B
7
6
5
4
3
2
1
G1 0
I/O Device
Digital
inputs
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
Data Bus
(D0 - D7)
DI0 - DI7
DS1
IO/M
A3
A15
A13
A12
DS 2
WR
3L ´ 8 L Decoder
0
1
2
3
I2
I1
I0
E1
4
5
E2
6
7
E3
BDB
8
Output port
8
Output Device
BCB
The interfacing circuit makes use of 3 Line
to 8 Line decoder having 3 enable lines
E1 , E2 , E3 . The address of the device is
[GATE 2014, IIT Kharagpur]
(A) 50 H
(B) 5000 H
(C) A0 H
(D) A000 H
Q.26 A snapshot of the address, data and control
buses of an 8085 microprocessor executing a
program is given below :
(A) F8 H – FB H
(B) F8 H – FC H
(C) F8 H – FF H
(D) F0 H – F7 H
Q.24 For the 8085 microprocessor, the interfacing
circuit to input 8-bit digital data ( DI 0 - DI 7 )
A2
(D) LDA F8F8 H
A14
IO/M
CS
A1
A0
(C) OUT F8 H
AB
to decode internally its three ports and the
Control register. The address lines A3 to A7
8255
(B) IN F8 H
8
and A1 of the 8085 are used by the 8255 chip
A7
A6
A5
A4
A3
IO/M
(A) MVI A, F8 H
Q.25 An output device is interfaced with 8-bit
microprocessor 8085 A. The interfacing
circuit is shown in figure.
A11
as well as the IO/M signal are used for
address decoding. The range of addresses
for which the 8255 chip would get selected
is
[GATE 2007, IIT Madras]
RD
Microprocessor 8085
[GATE 2007, IIT Kanpur]
Address
2020 H
Data
24 H
IO/ M
Logic High
RD
Logic High
WR
Logic Low
The assembly language instruction being
executed is
(A) IN 24 H
(B) IN 20 H
(C) OUT 24 H
(D) OUT 20 H
Q.27 A 8-bit DAC is interfaced with a
microprocessor having 16 address lines
( A0 ... A15 ) as shown in the adjoining figure.
A possible valid address for this DAC is
[GATE 2010, IIT Guwahati]
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
86
d 0 ...d 7
A14
A13
A15
0
1
0
a0 2 LINE
to
a1
4 LINE
DECODER
CS
A2
b0
A3
DAC
b1
b2
CS
b3
(A) 3000H
(B) 4FFFH
(C) AFFFH
(D) C000H
Analog
output
A4
A7
A6
A5
Q.28 If CS  A15 A14 A13 is used as the chip select
logic of a 4K RAM in an 8085 system, then
its memory range will be
[GATE 1996, IISc Bangalore]
Q.1
(C) 5000 H - 5FFF H and 6000 H - 6FFF H
Q.2
(The address lines are designated as A0 to
A7 for I/O addresses)
The peripheral will correspond to I/O
addresses in the range
[GATE 1997, IIT Madras]
A2
A3
Chip Select
Q.3
A4
A5
A6
A7
(A) 60 H to 63 H
(B) A4 H to A7 H
(C) 50 H to AF H
(D) 70 H to 73 H
Q.30 An I/O peripheral device shown in the figure
below is to be interfaced to an 8085
microprocessor. To select the I/O device in
the I/O address range D4 H-D7 H, its chipselect (CS ) should be connected to the
output of the decoder shown in the figure
[GATE 2006, IIT Kharagpur]
IOWR
A1
A0
I/O
Peripheral
CS
(B) output 5
(D) output 0
Practice (objective & Num Ans) Questions :
(B) 7000 H - 7FFF H
Q.29 The decoding circuit shown in figure has
been used to generate the active low chip
select signal for a microprocessor peripheral.
Data
IORD
EN
(A) output 7
(C) output 2
(A) 3000 H - 3FFF H
(D) 6000 H - 6FFF H and 7000 H - 7FFF H
1
2
3
3-8
4
Decorder 5
6
MSB
7
LSB
Consider initial values (PC) = 1200H, (SP)
= 3000H. After execution of “RST7”
instruction, the contents of PC and SP
respectively ________.
(A) 1201H, 3000H
(B) 0038H, 2FFEH
(C) 0038H, 3002H
(D) 1201H, 2FFEH
For the 8085 assembly language program
given below the content of the accumulator
after the execution of the program is
______H.
3000
MVI A, 45H
3002
MOV B, A
3003
STC
3004
CMC
3005
RAR
3006
XRA B
3007
HLT
Consider the following program to be
executed in 8085 microprocessor
MVI
A 84 H
CPI
EA H
ACI
42 H
MOV
BA
MVI
A, A2 H
SUB
B
HLT
(B) (CB) H
(A) ( AB) H
(C) ( DB) H
Q.4
(D) ( BD) H
An 8085 microprocessor based system uses
RAM whose starting address is AA00 H. the
address of last byte in this RAM is B9FF H,
then the size of RAM is _____ KB.
GATE ACADEMY®
Q.5
Q.6
Initially program counter is loaded with
1000 H.
1000 :
LXI H, 1009
1003
MVI A, 40 H
1005
MVI B, 50 H
1007
PCHL
1008
ADD B
1009
ADI 42 H
100B
HLT
Content of accumulator after execution of
program will be ______H.
The following program is executed on the
8085 Microprocessor
MVI
A, F2H
MVI
B, 7AH
ADD
B
OUT
PORT 0
HLT
Initial flag and register content is specified :
A
B
S
Z
CY
00H FFH
Q.7
87
0
1
0
 Initial
conditions
The output at PORT 0 is
(A) 16 H
(B) 1C H
(C) 6C H
(D) FF H
Suppose memory chips of 256  4 size are
available in the market you need to make
memory block and interface it with a
microprocessor having 11 address lines and
8 data lines. The number of memory chips
you will need is________.
Microprocessor 8085
Q.8
The below given logic circuit shows the
active low chip select signal generation for a
RAM I.C. The valid address space of the
RAM I.C represented by the figure is
_________.
A11 A0
A13
I1
A12
I0
2´ 4
Line
decoder
D11 - D0
CS
RAM I.C
CS
A13
MWC
A14
Q.9
MRC
(A) 4000H-FFFFH
(B) 8000H-8FFFH
(C) F000H-FFFFH
(D) 4000H- 4FFH
An 8085 up executes “XTHL” instruction
which is available at ROM location of
address 1200H. Assume SP content is
3000H. While fetching and executing this
instruction , the sequence of values written
at the address pins A1  A0 are
(A) 12H, 30H, 01H, 00H, 30H, 12H
(B) 00H, 00H, 30H, 12H, 01H, 00H
(C) 12H, 00H, 30H, 12H, 00H, 30H
(D) 00H, 00H, 01H, 01H, 00H
Q.10 Consider the following assembly language
program
MVI A, AC H
MVI B, FF H
XRA B
ANI FF H
DAA
HLT
The program was executed in 8085, after
execution of HLT the decimal equivalent of
data present in accumulator is_________.

GATE ACADEMY®
88
Digital Electronics & Microprocessor 8085 [WB]
Answer Keys
Objective & Numerical Answer Type Questions
Date Transfer, Arithmetic and logical instruction set
1.
C
2.
A
3.
D
4.
A
5.
B
6.
D
7.
B
8.
A
9.
C
10.
B
11.
C
12.
B
13.
C
14.
D
15.
D
16.
C
17.
A
18.
A
Branch Group and Stack Group Instruction set
1.
A
2.
A
3.
A
4.
B
5.
C
6.
6885
7.
C
8.
B
9.
B
10.
B
11.
B
12.
D
13.
C
14.
C
15.
C
16.
B
17.
A
18.
A
19.
B
20.
C
21.
63
Machine Cycle
1.
C
2.
B
3.
D
4.
A
5.
C
6.
C
7.
B
8.
C
9.
C
10.
C
11.
A
12.
D
4.
B
5.
D
Interrupts
1.
C
6.
B
2.
C
3.
A
Memory & Memory Interfacing
1.
EBCC
2.
BFFF
3.
A3CE
4.
7001
5.
6.
C
7.
C
8.
B
9.
C
10.
(i)8 KB
(ii)8192
(iii)65536
C
11.
11
12.
C
13.
16
14.
D
15.
A
16.
C
17.
B
18.
C
19.
C
20.
B
21.
D
22.
D
23.
C
24.
D
25.
B
26.
D
27.
A
28.
D
29.
A
30.
B
Practice (Objective & Numerical Answer) Questions
1.
B
2.
67
3.
B
4.
3.8 - 4.2
5.
77.9 - 86.1
6.
C
7.
15.2 -16.8
8.
D
9.
D
10.
89
9
Logic Family
(A) 3-input OR gate
Objective & Numerical Ans Type Questions :
(B) 3-input NOR gate
Q.1
The figure shows the circuit of a gate in the
Resistor Transistor Logic (RTL) family. The
circuit represents a
[GATE 1991, IIT Madras]
(C) 3-input AND gate
(D) 3-input XOR gate
Q.3
In the circuit shown below,
has
negligible collector-to-emitter saturation
voltage and the diode drops negligible
voltage across it under forward bias. If VCC
VCC
V0
is +5 V, X and Y are digital signals with 0 V
as logic 0 and VCC as logic 1, then the
V1
Boolean expression for Z is
[GATE 2013, IIT Bombay]
V2
Q.2
Q1
(A) NAND
(B) AND
(C) NOR
(D) OR
+ VCC
R1
In the circuit shown, diodes D1 , D2 , and D3
are ideal, and the inputs E1 , E2 and E3 are ‘0
Z
V’ for logic ‘0’ and ‘10 V’ for logic ‘1’.
What logic gate does the circuit represent?
R2
X
Q1
Diode
[GATE 2015, IIT Kanpur]
E1
E2
E3
D1
Y
D2
D3
V0
1kW
10 V
Q.4
(A) XY
(B) XY
(C) XY
(D) XY
If X1 and X 2 are the inputs to the circuit
shown in the figure, the output Q is
[GATE 2005, IIT Bombay]
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
90
Q.7
VDD
In the circuit shown
[GATE 2012, IIT delhi]
5 Volts
A
Y1
Q
X1
C
B
X2
Y
C
Q.5
(A) X 1  X 2
(B) X 1  X 2
(C) X 1. X 2
(D) X 1. X 2
A
B
The logic functionality realized by the
circuit shown below is
[GATE 2016, IISc Bangalore]
B
(A) Y  A B  C
B
Q.8
A
Y
(B) Y  ( A  B)C
(C) Y  ( A  B )C
(D) Y  A B  C
The logic function implemented by the
following circuit at the terminal OUT is
[GATE 2008, IISc Bangalore]
Vdd
Q.6
(A) OR
(B) XOR
(C) NAND
(D) AND
OUT
P
The output (Y) of the circuit shown in the
figure is [GATE 2014, IIT Kharagpur]
Q
VDD
A
B
Q.9
C
Output (Y)
(A) P NOR Q
(B) P NAND Q
(C) P OR Q
(D) P AND Q
The logic function f ( X , Y ) realized by the
given circuit is
[GATE 2018, IIT Guwahati]
A
B
f ( X ,Y )
C
(A) A  B  C
(B) A  B C  A C
(C) A  B  C
(D) A B C
GATE ACADEMY®
91
(A) NOR
(B) AND
(C) NAND
(D) XOR
Logic Family

Answer Keys
Objective & Numerical Answer Type Questions
1.
C
2.
C
3.
B
4.
D
6.
A
7.
A
8.
D
9.
D
5.
D
10
1
Semiconductor
Memories
Introduction :
A major advantage of digital systems over analog systems is the ability to easily store large quantities of
digital information or data for short or long periods. This memory capability is what makes digital
systems so versatile and adaptable to many situations.
The information usually consists of instructions (processing steps) coded in binary form, data to be
processed, intermediate and final results, etc. The sub – system of a digital processing system, which
provides the storage facility, is referred to as the memory. Till recently, the memories used were mostly
of magnetic type. With unprecedented developments in semiconductor technology, it has become
possible to make semiconductor memories of various types and size. These memories have become very
popular due to their small size, low cost, high speed, high reliability, and ease of expansion of the
memory size. Therefore, it is necessary for a designer of digital processors to know thoroughly the
principles of operation and limitations of various semiconductor memory devices.
2
Memory Organization and Operation :
The basic element of a semiconductor memory is a FLIP –FLOP. The information is stored in binary
form. There are a number of locations in a memory chip, each location being meant for one word of
digital information. The number of locations and the number of bits comprising the word vary from
memory to memory. The size of a memory chip is specified by two numbers M and N as M  N bits.
The number M specifies the number of locations available in the memory and N is the number of bits at
each location. In other words, this means that M words of N bits each can be stored in the memory. The
commonly used values of the number of words per chip are 64, 256, 512, 1024, 2048, 4096 etc. whereas
the common values for the word size are 1, 4 and 8 etc. Memories requiring higher number of words and
/ or larger word sizes can be formed by using these chips.
The block diagram of a memory device is shown in Fig. below. Each of the M locations of the memory
is defined by a unique address and therefore for accessing any one of the M locations, P inputs are
required, where 2 P  M . This set of lines is referred to as address inputs or address bus. The address is
specified in the binary form. For convenience, octal and hexadecimal representations are commonly
employed.
GATE ACADEMY®
93
Address P - lines
inputs
N - lines
MXN Bits
Of
Memory
Data
inputs
Semiconductor Memories
Data
outputs
N - lines
Control inputs
3
Memory Device, Parameters and Specifications :
(1) Memory cell : A device or electrical circuit used to store a single bit (0 or 1) is called a memory
cell. Eg. A flip flop, a charged capacitor.
(2) Memory word : A group of bits (cells) in a memory that represents instructions or data of some type
is called a memory word.
(3) Byte : A byte is a special term used for a group of 8 bits. Word sizes can be expressed in bits as
well as in bytes. For example, a word size of 8 bits is also a word size of one byte; a word size of 16
bits is two bytes, and so on.
(4) Capacity : Capacity is a way of specifying how many bits can be stored in a particular memory
device or complete memory system. For example, suppose that we have a memory which can store
4096 twenty-bit words. This represents a total capacity of 81,920 bits.
(5) Density : Yet another term for capacity is density. When we say that one memory device has a
greater density than another, we mean that it can store more bits in the same amount of space. It is
more dense.
(6) Address : Address is a number that identifies the location of a word in the memory. Each word
stored in a memory device or system has a unique address. Addresses are always expressed as a
binary number, although octal, hexadecimal and decimal numbers are also used for convenience.
(7) Read Operation : The operation whereby the binary word stored in a specific memory location
(address) is sensed and then transferred to another device is called read operation.
(8) Write Operation : The operation where by a new word is placed into a particular memory location is
called write operation. It is also referred to as store operation. Whenever a new word is written into
a memory location, it replaces the word that was previously stored there.
(9) Access Time : Access time is a measure of a memory devices operating speed. It is the amount of
time required to perform a read operation. More specifically, it is the time between the memory
receiving a new address input, and the data becoming available at the memory output. The symbol
t ACC is used for access time.
(10) Volatile Memory : Any type of memory that requires the application of electrical power in order to
store information is called volatile memory. If the electrical power is removed, all information
stored in the memory will be lost. Many semiconductor memories are volatile, while all magnetic
memories are non-volatile, which means they can store information without electrical power.
(11) Random Access Memory (RAM): Memory in which the actual physical location of a memory word
has no effect on how long it takes to read from or write into that location is called ‘random access
memory’ (RAM). In other words, the access time is the same for any address in memory. Most
semiconductor memories are RAMs.
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
94
(12) Sequential Access Memory (SAM) : A type of memory in which the access time is not constant, but
varies depending on the address location is called sequential-access memory. A particular stored
word is found by sequencing through all address locations until the desired address is reached. This
produces access times which are much longer than those for random access memories. Examples of
SAM devices include magnetic tape, disk and magnetic bubble memory.
(13) Read / Write Memory (RWM) : Any memory that can be read from or written into with equal ease
is called read / write memory (RWM).
(14) Read-Only Memory (ROM) : A broad class of semiconductor memories designed for applications
where the ratio of read operations to write operations is very high is called read-only memory
(ROM). Technically a ROM can be written into (programmed) only once, and this operation is
normally performed at the factory. Thereafter, information can only be read from the memory.
Other types of ROM are actually read – Mostly memories (RMM) which can be written into more
complicated than the read operation and it is not performed very often. All ROM is nonvolatile and
will store data when electrical power is removed.
Solved Example 1
Sol.
What memory stores more bits: a 5M  8 memory, or a memory that stores 1 M words at a word size of
16 bits?
5M  8  5 1, 048,576  8  4,19, 43, 040 bits
1M 16  10, 48,576  16  1, 67, 77, 216 bits
Hence, the 5M  8 memory stores more bits.
Solved Example 2
Sol.
4
How many address input, data input line has and data output lines are required for a 16 K  8 memory?
We have,
2p  M
Where, P = Address input; M=Number of location
2 p  16 K or 24  210
P  14
And size of memory M  N  16 K  8
Data input (N) = 8
Memory Classifications :
Memory
Primary
or
Semiconductor
Read only
memory
(ROM)
Read/write
memory
(RAM)
Static
RAM
Secondary
or
Auxiliary
Dynamic
RAM
Erasable
Permanent
EPROM EEPROM Flash PROM
Backup
storage
Secondary
storage
Masked
Semirandom
access
Serial
access
CD-ROM
Magnetic tape
Hard disk
Magnetic bubble
Floppy disk
CCD
GATE ACADEMY®
95
Semiconductor Memories
4.1 Read/Write Memory (RAM) :
(i) Random-access memory is a form of computer data storage that stores data and machine code
currently being used. A random-access memory device allows data items to be read or written in
almost the same amount of time irrespective of the physical location of data inside the memory.
(ii) It is the hardware in a computing device where the operating system (OS), application programs and
data in current use are kept so that they can be quickly reached by the device's processor. RAM is
the main memory in a computer, and it is much faster to read from and write to than other kinds of
storage, such as a hard disk drive (HDD), solid-state drive (SSD) or optical drive.
(iii) Random Access Memory is volatile. That means data is retained in RAM as long as the computer is
on, but it is lost when the computer is turned off.
(iv) Figure below shows how RAMs are categorized. RAMs are also manufactured with either bipolar
or MOS technologies. Bipolar RAMs are all static RAM; that is the storage elements used in
memory are latches, so data can be stored for an indefinite period of time as long as the power is on.
Some MOS RAMs are of the static type and some are dynamic RAMs. A dynamic memory is one
in which data are stored on capacitors which require periodic recharging (refreshing) to retain the
data.
RAMs
Bipolar
Static
RAMs
MOS
Static
RAMs
Dynamic
RAMs
(v) Difference between SRAM and DRAM
(i) SRAM : Static Random Access Memory also needs constant power to hold on to data, but it
doesn't need to be continually refreshed the way DRAM does.
In SRAM, instead of a capacitor holding the charge, the transistor acts as a switch, with one
position serving as 1 and the other position as 0. Static RAM requires several transistors to
retain one bit of data compared to dynamic RAM which needs only one transistor per bit. As a
result, SRAM chips are much larger and more expensive than an equivalent amount of DRAM.
However, SRAM is significantly faster and uses less power than DRAM. The price and speed
differences mean static RAM is mainly used in small amounts as cache memory inside a
computer's processor.
(ii) DRAM : Dynamic Random Access Memory – The term dynamic indicates that the memory
must be constantly refreshed or it will lose its contents. DRAM is typically used for the main
memory in computing devices. If a PC or smartphone is advertised as having 4-GB RAM or
16-GB RAM, those numbers refer to the DRAM, or main memory, in the device.
More specifically, most of the DRAM used in modern systems is synchronous DRAM, or
SDRAM. Manufacturers also sometimes use the acronym DDR (or DDR2, DDR3, DDR4, etc.)
to describe the type of SDRAM used by a PC or server. DDR stands for double data rate, and it
refers to how much data the memory can transfer in one clock cycle.
GATE ACADEMY®
96
Digital Electronics & Microprocessor 8085 [WB]
In general, the more RAM a device has, the faster it will perform.
BASIS FOR
COMPARISON
SRAM
DRAM
Speed
Faster
Slower
Size
Large
Small
Cost
Expensive
Cheap
Used in
Cache memory
Main memory
Density
Less dense
Highly dense
Construction
Complex and uses
transistors and latches
Simple and uses capacitors
and very few transistors.
Single block of memory
6 transistors
Only one transistor
Charge leakage property
Not present
Present hence require power
refresh circuitry
Power consumption
Low
High
4.2 Read Only Memory (ROM) :
(i) Read-only memory (ROM) is a type of non-volatile memory used in computers and other
electronic devices. Data stored in ROM can only be modified slowly, with difficulty, or not at all,
so it is mainly used to store firmware (software that is closely tied to specific hardware, and
unlikely to need frequent updates) or application software in plug-in cartridges.
(ii) Strictly, read-only memory refers to memory that is hard-wired, such as diode matrix and the later
mask ROM (MROM), which cannot be changed after manufacture. Although discrete circuits can
be altered in principle, integrated circuits (ICs) cannot, and are useless if the data is bad or requires
an update. Such memory can never be changed is a disadvantage in many applications, as bugs and
security issues cannot be fixed, and new features cannot be added.
(iii) More recently, ROM has come to include memory that is read-only in normal operation, but can
still be reprogrammed in some way. Erasable programmable read-only memory (EPROM) and
electrically erasable programmable read-only memory (EEPROM) can be erased and reprogrammed, but usually this can only be done at relatively slow speeds, may require special
equipment to achieve, and is typically only possible a certain number of times.
(iv) Types of ROMS :
Read only
memory
(ROM)
Erasable
Permanent
EPROM EEPROM Flash PROM
Masked
MROM (Masked ROM)
The very first ROMs were hard-wired devices that contained a pre-programmed set of data or
instructions. These kind of ROMs are known as masked ROMs, which are inexpensive.
GATE ACADEMY®
97
Semiconductor Memories
PROM (Programmable Read Only Memory)
PROM is read-only memory that can be modified only once by a user. The user buys a blank
PROM and enters the desired contents using a PROM program. Inside the PROM chip, there are
small fuses which are burnt open during programming. It can be programmed only once and is not
erasable.
EPROM (Erasable and Programmable Read Only Memory)
EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes.
Usually, an EPROM eraser achieves this function. During programming, an electrical charge is
trapped in an insulated gate region. The charge is retained for more than 10 years because the
charge has no leakage path. For erasing this charge, ultra-violet light is passed through a quartz
crystal window (lid). This exposure to ultra-violet light dissipates the charge. During normal use,
the quartz lid is sealed with a sticker.
EEPROM (Electrically Erasable and Programmable Read Only Memory)
EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten
thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM,
any location can be selectively erased and programmed. EEPROMs can be erased one byte at a
time, rather than erasing the entire chip. Hence, the process of reprogramming is flexible but slow.
(vi) Advantages of ROM
The advantages of ROM are as follows •
Non-volatile in nature
•
Cannot be accidentally changed
•
Cheaper than RAMs
•
Easy to test
•
More reliable than RAMs
•
Static and do not require refreshing
•
Contents are always known and can be verified
4.3 Difference between RAM and ROM :
A ROM chip is used primarily in the start up process of a computer, whereas a RAM
chip is used in the normal operations of a computer once the operating system has been loaded.
A RAM chip can store multiple GB (gigabytes) of data, ranging from 1 GB to 256 GB per chip. A ROM
chip stores several MB (megabytes) of data, typically 4 MB or 8 MB per chip.
BASIS FOR
COMPARISON
RAM
ROM
Basic
It is a read write memory.
It is read only memory
Use
Used to store the data that has to
be currently processed by CPU
temporarily
It stores the instructions
required during bootstrap of the
computer.
Volatility
It is a volatile memory.
It is a nonvolatile memory
Stands for
Random access memory
Read Only Memory
Modification
Data in RAM can be modified
Data in ROM can not be
modified.
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
98
Capacity
RAM sizes from 64 MB to 4GB
ROM is comparatively smaller
than RAM.
Cost
RAM is a costlier
Memory.
ROM is comparatively cheaper
than RAM
Type
Types of RAM are static RAM
and dynamic RAM.
Types of ROM are PROM,
EPROM, EEPROM.
Solved Example 3
Sol.
A certain semiconductor memory chip is specified as 4 K  8. How many words can be stored on this
chip? What is the word size? How many bits can be stored in this chip?
4 K  4  1024  4096
Each word is having 8-bits (1byte)
The total number of bits, that can be stored is 4 1024  8  32768 bits
Solved Example 4
The data bus width of a memory of size 2048  8 is
Sol.
(A) 8
(B) 10
The given memory is of size 2048  8
(C) 12
(D) 16
Since we know that, the size or the capacity of each memory chip is specified by ( M  N ), where M
specifies the number of locations available in the memory and N is the number of bits that can be stored
in each memory location.
Address P - lines
inputs
N - lines
MXN Bits
Of
Memory
Data
inputs
Data
outputs
N - lines
Control inputs
Where M  2 p
P is the number of address input and N is the number of data inputs.
Thus, data bus width of a memory of size 2048  8 is 8
Here the correct option is ‘A’
Solved Example 5
A memory has 16 bit address bus. The number of locations in the memory are
(A) 16
(B) 32
(C) 1024
(D) 65536
Ans.
(D)
Sol.
The given memory has 16 bit address bus. Thus, the number of locations in the memory are
2 p  216  65536
Hence, the correct option is (D).
GATE ACADEMY®
99
Semiconductor Memories
GATE Questions :
Q.1
A dynamic RAM consists of
[GATE 1994, IIT Kharagpur]
Sol.
(A) 6 transistors.
(B) 2 transistors and 2 capacitors.
(C) 1 transistor and 1 capacitor.
(D) 2 capacitors only.
Sol.
(C)
A typical dynamic RAM cell consists of a
MOSFET and one capacitor.
The circuit of DRAM cell is shown below,
(A) 6 MOS transistors.
(B) 4 MOS transistors and 2 capacitors.
(C) 2 MOS transistors and 4 capacitors.
(D) 1 MOS transistor and 1 capacitors.
(A)
Each cell of a static Random Access
Memory contains six MOS transistors. Each
bit on static RAM is stored on four
transistors out of which two are PMOS and
two are NMOS that form cross-coupled
inverters. Remaining two transistors are used
to control reading from or writing into cell.
Circuit of static RAM :
WL
Column (Sense line)
VDD
ROW
(Control line)
BL
BL
The dynamic RAM consists of 1 transistor
and 1 capacitor.
Hence, the correct option is (C).
Q.2
The minimum number of MOS transistors
required to make a dynamic RAM cell is
Q.4
NMOSFET is 1 V. What could be WL, C
and BL voltages when read operation take
place.
[GATE 2001, IIT Kanpur]
[GATE 1995, IIT kanpur]
Sol.
(A) 1
(B) 2
(C) 3
(D) 4
Word line (WL)
(A)
The minimum number of MOS transistors
required to make a dynamic RAM cell is 1.
Bit line
(BL)
The circuit of DRAM cell is shown below,
Column (Sense line)
ROW
(Control line)
Sol.
Hence, the correct option is (A).
Q.3
Hence, the correct option is (A).
In the DRAM cell in the figure, the Vt of the
Each cell of a static Random Access
Memory contains
[GATE 1996, IISc Bangalore]
C
(A) 5 V; 3 V; 7 V
(B) 4 V; 3 V; 4 V
(C) 5 V; 5 V; 5 V
(D) 4 V; 4 V; 4 V
(B)
Given DRAM cell is shown below,
Word line (WL)
VG
Bit line
(BL) VD
VS
C
Digital Electronics & Microprocessor 8085 [WB]
GATE ACADEMY®
100
output acts as the input to a 16  4 ROM
whose output is floating when the enable
input E is 0. A partial table of the contents
of the ROM is a follows
[GATE 2003, IIT Madras]
Given : Vt  1 V
(i) The source capacitor is connected to
drain voltage VD , it will charge to drain
voltage VD only when MOSFET is ON.
(ii) MOSFET will be ON when,
VGS  Vt
Address
0
Data
0011
2
1111
4
0100
6
1010
8
1011
10
1000
12
0010
14
1000
VG  VS  Vt
VG  Vt  VS that means source voltage is
less than or equal to VG  Vt .
(iii)Maximum voltage that source can attain
is,
VS  VG  Vt
From option (A) :
VG  5 V, VS  3 V, VD  7 V
MSB
W
Here, VD  VG  Vt and VS  VG  Vt
From option (B) :
VG  4 V, VS  3 V, VD  4 V
C
Here, VD  VG  Vt and VS  VG  Vt
1
From option (C) :
VG  5 V, VS  5 V, VD  5 V
A
E
ROM
Here, VD  VG  Vt and VS  VG  Vt
From option (D) :
VG  4 V, VS  4 V, VD  4 V
C:
Here, VD  VG  Vt and VS  VG  Vt
Only option (B) satisfies these conditions.
There are two condition for charging the
capacitor “C”.
(i) If VD  VG  Vt (saturation) then
t1
data on the bus at time t2 is
(ii) If VD  VG  Vt (ohmic) then VS  VD .
Q.5
Time
The clock to the register is shown, and the
data on the W bus at time t1 is 0110. The
VS  VG  Vt .
All the options comes under (i) condition
but only option (B) satisfy condition (ii).
Hence, the correct option is (B).
In the circuit shown in the figure, A is a
parallel-in, parallel-out 4 bit register, which
loads at the rising edge of the clock C. The
input lines are connected to a 4 bit bus W. Its
t2
Sol.
(A) 1111
(B) 1011
(C) 1000
(D) 0010
(C)
At first clock pulse,
Input to ROM = 0110 (= 6)
Output of ROM = contents at location 6 =
1010.
At second clock pulse, this 1010 will act as
input to the ROM.
GATE ACADEMY®
Q.6
101
Input to ROM = 1010 (= 10)
Hence, output of ROM
= Contents at location 10
= 1000
Hence, the correct option is (C).
If WL is the Word Line and BL the Bit Line,
an SRAM cell is shown in
[GATE 2014, IIT Kharagpur]
(A) WL
Semiconductor Memories
Sol.
(B)
select (WL)
CMOS Inverters
CMOS Inverters
M1
M3
M5
Complementary
access transistor
M6
M2
M4
Complementary
access transistor
VDD
bit’ (BL)
BL
BL
(B) WL
VDD
BL
BL
Q.7
(C) WL
VDD
BL
BL
Sol.
(D) WL
VDD
BL
BL
bit’ (BL)
Fig. Design of an SRAM core cell
The SRAM core circuit is shown in figure.
The value is stored in the middle of four
transistors, which form a pair of inverters
connected in a loop (try drawing a gate-level
version of this schematic). The other two
transistors control access to the memory cell
by the bit lines. When select line (word line)
= 0, the inverters reinforce each other to
store the value. A read or write is performed,
when the cell is selected.
Hence, the correct option is (B).
In a DRAM
[GATE 2017, IIT Roorkee]
(A) periodic refreshing is not required.
(B) information is stored in a capacitor.
(C) information is stored in a latch.
(D) both read and write operations can be
performed simultaneously.
(B)
Inside a dynamic RAM chip, each memory
cell holds one bit of information and is made
up of two parts: a transistor and a capacitor.
These are extremely small transistors and
capacitors, so that millions of them can fit
on a single memory chip. The capacitor
holds the bit of information 0 or 1. The
transistor acts as a switch that lets the
control circuitry on the memory chip read
the capacitor or change its state.
A capacitor is like a small bucket that is able
to store electrons. To store a 1 in the
memory cell, the bucket is filled with
Digital Electronics & Microprocessor 8085 [WB]
Q.8
electrons. To store a 0, it is emptied.
Therefore, for dynamic memory to work,
either the CPU or the memory controller has
to come along and recharge all of the
capacitors holding a 1 before they discharge.
To do this, the memory controller reads the
memory and then writes it right back. This
refresh operation happens automatically
thousands of times per second.
This refresh operation is the reason why
dynamic RAM gets its name. Dynamic
RAM has to be dynamically refreshed all of
the time or it forgets what it is holding. The
downside of all of this refreshing is that it
takes time and slows down the memory.
Hence, the correct option is (B).
A 2  2 ROM array is built with the help of
diodes as shown in the circuit below. Here
W0 and W1 are signals that select the word
lines and B0 and B1 are signals that are
output of the sense amps based on the stored
data corresponding to the bit lines during the
read operation.
B0
GATE ACADEMY®
102
1 0
(C) 

1 0
(A)
Sol.
1 1 
(D) 

 0 0
Given :
B0
B1
Sense amps
W0
B0
W0 é D00
W1 êë D10
W1
VDD
Bits stored in the ROM Array
Fig. (a)
Different arrangement of ROM cell for logic
0 and logic 1 is shown below,
Read-Only Memory Cells
BL
1
WL
VDD
BL
BL
WL
WL
BL
BL
BL
B1
0
Sense amps
WL
WL
WL
W0
GND
B0
W1
VDD
B1
D01 ù
D11 úû
W0 é D00
W1 êë D10
B1
D01 ù
D11 úû
Bits stored in the ROM Array
Diode ROM
MOS ROM 1
MOS ROM 2
Fig. (b)
From figure (a),
When, W0  VDD , B0  VDD ; else B0  0
During the read operation, the selected word
line goes high and the other word line is in a
high impedance state. As per the
implementation shown in the circuit diagram
above, what are the bits corresponding to
Dij (where i  0 or 1 and j  0 or 1) stored
in the ROM? [GATE 2018, IIT Guwahati]
1 0
0 1
(A) 
(B) 


0 1
1 0
When, W1  VDD , B1  VDD ; else B1  0
So, B0  W0 and B1  W1
Therefore,
B0
W0  D00
W1  D10
B1
B0 B1
D01  W0 1 0

D11  W1  0 1 
Hence, the correct option is (A).
