Synopsys EDA Tool Flow for Back-End Digital
IC Design
Sci.D., Professor Vazgen Melikyan
Synopsys Armenia Educational Department
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CONFIDENTIAL INFORMATION
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prior written authorization.
IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys’ future plans, such
plans are as of the date of this presentation and are subject to change. Synopsys is
not obligated to update this presentation or develop the products with the features
and functionality discussed in this presentation. Additionally, Synopsys’ services and
products may only be offered and purchased pursuant to an authorized quote and
purchase order or a mutually agreed upon written contract with Synopsys.
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© 2023 All rights reserved..
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Course Overview

Back End EDA Tools


Floorplanning and Partitioning


2 lectures
Physical Verification


3 lectures
Routing


4 lectures
Clock-tree Synthesis (CTS)


4 lectures
Placement


2 lectures
4 lectures
Static timing analysis (STA)

4 lectures
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Back End EDA Tools
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Digital Design Flow
Back End
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Back End Design Flow
Physical Design
Constraints
Gate level
design
Timing
constraints
Logical and
physical libraries
Floorplanning
Placement
Clock tree synthesis
Routing
Physical Verification
Signoff
Static Timing Analysis
Completed
design
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Floorplanning

During the floorplanning step the overall cell is defined, including: cell size,
supply network, etc.
Floorplan
Power Planning
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Placement
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Clock Tree Synthesis (CTS)
Clock
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Clock Tree Synthesis (CTS) (2)
Clock

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A buffer tree is built to balance the loads and minimize the skew
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Routing

Routing creates physical connections to all clock and signal pins through
metal interconnects
•
•
Routed paths must meet setup and hold
timing, max cap/trans, power and clock
skew requirements
Metal traces must meet physical DRC
requirements
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Physical Verification: Design Rule Check
Layout
DRC
(IC Validator)
Output Summary files
(Error database)
DRC Rules
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Physical Verification: Layout Versus Schematic
Layout
LVS
(IC Validator)
Output Summary files
(Error database)
LVS Rules
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Static Timing Analysis (STA)
Net Parasitics (.spef, .sdf)
Layout
Parasitic Extraction
Netlist (.v)
module CONTROL ….
AIR_GAP_SMAX=2.0 }
DIELECTRIC d1 { THICKNESS=0.725
ER=3.9 }
CONDUCTOR poly { THICKNESS=0.125
WMIN=0.3 SMIN=0.3 RPSQ=10.0 }
DIELECTRIC d0 { THICKNESS=0.375
ER=3.9 }
VIA sub_tie { FROM=SUBSTRATE TO=m1
AREA=0.25 RPV=5 }
VIA poly_cont { FROM=poly TO=m1
AREA=0.25 RPV=4 }
VIA via { FROM=m1 TO=m2 AREA=0.36
RPV=4 }
input A, B, C;
output reg X;
…..
and2 U1 (.I0(B), .I1(C), .Z(T1);
or2
Static Timing Analysis
(PrimeTime)
U2 (.I0(B), .I1(C), .Z(T2);
mux2 U3 (.S(A),.I1(T1),.I2(T2), .Z(X);
Design Library
.db
Timing Report
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Parasitic Extraction
Layout
Extraction
deck
Parasitic Extraction
(StarRC)
Parasitics
(.spef, .sdf)
AIR_GAP_SMAX=2.0 }
DIELECTRIC d1 { THICKNESS=0.725 ER=3.9 }
CONDUCTOR poly { THICKNESS=0.125 WMIN=0.3
SMIN=0.3 RPSQ=10.0 }
DIELECTRIC d0 { THICKNESS=0.375 ER=3.9 }
VIA sub_tie { FROM=SUBSTRATE TO=m1 AREA=0.25
RPV=5 }
VIA poly_cont { FROM=poly TO=m1 AREA=0.25
RPV=4 }
VIA via { FROM=m1 TO=m2 AREA=0.36 RPV=4 }
Parasitics
(.spef, .sdf)
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Back End EDA Tools

Physical Design (Synthesis)


IC Compiler II
Signoff
IC Validator – Physical Verification
 StarRC- Parasitics extraction
 Prime Time – STA

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Thank You
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