ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ
Evaluation Board User Guide
UG-1759
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADMV4530 Dual-Mode, Ka Band Upconverter With Integrated
Fractional-N PLL and VCO
FEATURES
EVALUATION BOARD PHOTOGRAPHS
Fully featured evaluation board for the ADMV4530
On-board system demonstration platform (SDP-S) connector
for SPI
5 V operation through LDO
ACE software interface for SPI control
EQUIPMENT NEEDED
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5 V dc power supply
Baseband signal generator(s)
Spectrum analyzer
USB cable
SDP-S controller board
Figure 1. ADMV4530IQ-EVALZ
DOCUMENTS NEEDED
ADMV4530 data sheet
SOFTWARE NEEDED
ACE software
GENERAL DESCRIPTION
The ADMV4530 is a highly integrated upconverter with an
I/Q mixer that is ideally suited for next generation Ka band
satellite communications. The chip can be programmed using a
4-wire serial port interface (SPI). The SDP-S controller allows the
user to interface with the ADMV4530 SPI through the Analog
Devices, Inc., Analysis, Control Evaluation (ACE) software.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Downloaded from Arrow.com.
23154-002
The ADMV4530IQ-EVALZ and the ADMV4530IF-EVALZ are
the two evaluation boards available for the ADMV4530 that
work in inphase/quadrature (I/Q) mode and intermediate
frequency (IF) mode, respectively. Both boards incorporate the
ADMV4530 Ka band upconverter with low dropout (LDO)
regulators and an interface to the EVAL-SDP-CS1Z (SDP-S)
controller board to allow the simple and efficient evaluation of
the ADMV4530. The on-board LDO regulators allow the
ADMV4530 to be powered on by a single supply.
Figure 2. ADMV4530IF-EVALZ
For full details on the ADMV4530, see the ADMV4530 data
sheet, which must be consulted in conjunction with this user
guide when using the ADMV4530IQ-EVALZ and the
ADMV4530IF-EVALZ.
Rev. A | Page 1 of 21
UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Equipment Needed........................................................................... 1
ADMV4530IQ-EVALZ OR ADMV4530IF-EVALZ Quick
Start .............................................................................................. 10
Documents Needed .......................................................................... 1
Signal Generator Settings .......................................................... 10
Software Needed ............................................................................... 1
RF Gain Control ......................................................................... 11
General Description ......................................................................... 1
IF Gain Control .......................................................................... 11
Evaluation Board Photographs....................................................... 1
Automated Chip Reset .............................................................. 11
Revision History ............................................................................... 2
Manual Chip Reset ..................................................................... 11
Evaluation Board Hardware ........................................................... 3
Loss of Board Communication ................................................ 11
Evaluation Board Software .............................................................. 5
Regulator Bypass ........................................................................ 11
Installing the ACE Software, ADMV4530 Plug-Ins, and
Drivers ........................................................................................... 5
Evaluation Board Schematics and Artwork................................ 12
Plug-In Overview ......................................................................... 6
ADMV4530IF-EVALZ .............................................................. 16
Plug-In Details .............................................................................. 7
Ordering Information.................................................................... 20
Performing Evaluation .................................................................. 10
Bill of Materials .......................................................................... 20
ADMV4530IQ-EVALZ ............................................................. 12
REVISION HISTORY
3/2020—Rev. 0 to Rev. A
Change to User Guide Title ............................................................ 1
3/2020—Revision 0: Initial Version
Rev. A | Page 2 of 21
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ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
UG-1759
EVALUATION BOARD HARDWARE
Both the ADMV4530IQ-EVALZ and the ADMV4530IF-EVALZ
evaluation boards have on-board ADMV4530 chips. Figure 3
and Figure 4 show lab bench setups for both boards.
For each setup, connect the SDP-S board to the on-board, 120-pin
connector and then to the PC through the mini USB connector.
A 5 V dc power supply must be connected to the 5V and GND1
test points. Alternatively, the power supply can be connected to
the VSUPPLY Subminiature Version A (SMA) port.
Two signal generators must be connected to the
ADMV4530IQ-EVALZ or the ADMV4530IF-EVALZ
evaluation board. One signal generator provides the reference
input signal, and the other signal generator provides either the
IF input or the I/Q inputs. The IF input is a single-ended
configuration, whereas the I/Q inputs are a differential
configuration.
To observe the output signal from the ADMV4530IQ-EVALZ
or the ADMV4530IF-EVALZ board, connect a spectrum analyzer
(or similar instrument) to the RF output (RFOUT) port.
SPECTRUM ANALYZER
SIGNAL GENERATOR
RF OUTPUT
REFERENCE INPUT
BASEBAND
SIGNAL GENERATOR
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IQ INPUTS
Figure 3. ADMV4530IQ-EVALZ Lab Bench Setup for I/Q Mode
Rev. A | Page 3 of 21
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ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
SPECTRUM ANALYZER
SIGNAL GENERATOR
RF OUTPUT
REFERENCE INPUT
IF INPUT
Figure 4. ADMV4530IF-EVALZ Lab Bench Setup for IF Mode
Rev. A | Page 4 of 21
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IF SIGNAL GENERATOR
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
UG-1759
EVALUATION BOARD SOFTWARE
INSTALLING THE ACE SOFTWARE, ADMV4530
PLUG-INS, AND DRIVERS
Once the installation finishes, the ADMV4530 evaluation board
plug-in appears when the ACE software is open (see Figure 6).
The ADMV4530IQ-EVALZ and the ADMV4530IF-EVALZ use
the Analog Devices Analysis|Control|Evaluation (ACE)
software. For instructions on how to install and use the ACE
software, go to www.analog.com/ACE.
Note that both the ADMV4530IQ-EVALZ and the ADMV4530IFEVALZ evaluation boards use the same ACE plug-in, which
displays on the main ACE screen as the ADMV4530 Board.
If the ACE software is already installed on the PC, ensure that
the installed software is the latest version, as shown on the
www.analog.com/ACE page. If the previously installed software
is not the latest version, take the following steps to install the
updated ACE software:
1.
2.
23154-006
3.
Uninstall the current version of the ACE software on the PC.
Delete the ACE folder found in C:\ProgramData\Analog
Devices.
Install the latest version of the ACE software. During
installation, ensure that the .Net 40 Client, SDP Drivers,
the LRF Drivers installations are checked off as well (see
Figure 5).
23154-005
Figure 6. ADMV4530 Board Plug-In Window after Opening the
ACE Software
Figure 5. Required Driver Installations with the ACE Software
Rev. A | Page 5 of 21
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UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
PLUG-IN OVERVIEW
When either the ADMV4530IQ-EVALZ or the ADMV4530IQEVALZ is connected to the PC, the ADMV4530 Board appears
in the Attached Hardware section. Double-clicking on the
plug-in opens two tabs, the board level plug-in and the chip level
plug-in, which are the ADMV4530 Board (see Figure 7) and the
ADMV4530 (see Figure 8), respectively.
The ADMV4530 plug-in has the following functions and
features:
Device initialization
Mode selection
Block power downs
Phase-locked loop (PLL) synthesizer settings
Mixer settings
Temperature sensor readback
VCO core and band readback
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






Figure 7. ADMV4530 Board Plug-In View
23154-008
Note that the ACE software provides a simple tutorial for
testing the ADMV4530. For a more customized and detailed
implementation, refer to ADMV4530 data sheet for a full
description of each block, register, and the corresponding
settings.
Figure 8. ADMV4530 Chip Block Diagram
Rev. A | Page 6 of 21
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ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
UG-1759
PLUG-IN DETAILS
23154-009
The full screen ADMV4530 user interface with labels is shown
in Figure 9. The labels correspond to items listed in Table 1,
which describes the functionality of each block. For additional
detailed programming, refer to the ADMV4530 data sheet.
Figure 9. ADMV4530 Block Diagram with Labels
Table 1. ADMV4530 Block Diagram Label Functions (See Figure 9)
Label
A
Function
Use the Initial Configuration to initialize the ADMV4530IQ-EVALZ or the ADMV4530IQ-EVALZ evaluation board. Set the
following under the Initial Settings section:
Mixer Mode Selection: select IF, I/Q, or user defined mode.
Requested LO Frequency: enter the requested local oscillator (LO) frequency.
Reference Frequency Input: enter the reference input frequency.
Reference Doubler: use the dropdown menu to disable or enable the reference doubler.
R Word: enter the R word value.
Reference Divide-by-2: use the dropdown menu to disable or enable the reference divide by 2.
CP Current: use the dropdown menu to select the charge pump (CP) current.
Summary: click this button to review the settings for the initial setup.
Apply: click this button to apply the initial settings. The settings are reflected in the right sections. Note that clicking Apply
Changes (Label K1) does not update the changes in this section.
Rev. A | Page 7 of 21
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UG-1759
Label
B
C
D
E
F
G
H
I
J
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Function
Use the Frequency & N Parameters section to change settings for the LO frequency after applying the initial settings in the
Initial Configuration (Label A) section. This section includes the following:
Requested LO Frequency and VCO Frequency: enter values in these two text boxes to trigger the INT, FRAC1, FRAC2, and
MOD2 calculations.
INT, FRAC1, FRAC2, and MOD2: calculations based on the requested LO or VCO frequency. Changing these values directly
changes the actual LO and VCO frequency accordingly but does not change the requested LO and VCO frequency text boxes.
PFD Frequency: calculation based on the Reference Path (Label C) section.
Actual LO Frequency and VCO Frequency: the actual LO frequency and the actual VCO frequency are calculated from the PFD
frequency, INT, FRAC1, FRAC2, MOD1, and MOD2 parameters shown on the right side of the equation (see Figure 9).
Delta LO Frequency and VCO Frequency: the delta is computed from the difference between the requested and actual
frequencies, which is useful for detecting if there is any residual frequency error due to limitations caused by synthesizer resolution.
Lock Detect Readback: click the check button next to this option to check whether the PLL is locked.
Integer and Fractional indication light: indicates if the chip is in integer or fractional mode.
Use the Reference Path section to change the reference parameters and PFD frequency after applying the initial settings in the
Initial Configuration (Label A) section. This section includes the following:
PFD Frequency: the calculated PFD frequency based on the equation on right (see Figure 9).
REF Frequency: enter the reference input frequency.
Doubler: click this button to enable or disable the doubler.
R Word: scroll up and down to change the R word values, ranging from 1 to 32.
Div-by-2: click this button to enable or disable the reference divide by 2 function.
Click the Read button in the Core & Band section to read back the chip core and band values.
Click the Read button in the Temp ADC section to read back the chip temperature sensor values.
I and Q: scroll up and down to adjust the I and Q phase value in the LO Phase section.
Use the Power Downs section to configure the different blocks power conditions in the chip. This section includes the following:
RF BIAS PD, PLL PD, and VCO PD: scroll up and down to power up or power down these blocks in the chip.
PD pin: scroll up and down to select normal operation or to power down the chip.
RESET_N Pin: scroll up and down to select normal operation or to reset the power-on state.
Use the Mode Selection section to select the mixer mode and configure the automatic gain control (AGC).
Use the Baseband Settings section to configure the dc settings for both IF and I/Q mode and the mixer common-mode
settings. This section includes the following:
DC Offset Target: scroll up and down to set the target dc offset. Changing the values result in changes in DC Offset I and DC
Offset Q values accordingly.
DC Offset I, DC Offset Q: bidirectional calculation associated with DC Offset Target. Scroll up and down to change these
values. The DC Offset Target changes accordingly.
MIXER_VCM: scroll up and down to change the mixer common-mode voltage. The hexadecimal value is shown to the right.
IQ Mode: scroll up and down to change the I/Q mode common-mode voltage (VCM).
Calc Error light: this light illuminates if there is a calculation error when MIXER_VCM is changed to a value outside of the
nominal equations. Refer to the ADMV4530 data sheet and Register 0x103 for more details.
The Other PLL Settings section consists of the following:
ΣΔ PD: click the dropdown menu to power down or power up the Σ-Δ function. For integer mode, power ΣΔ PD down. For
fractional mode, power ΣΔ PD up.
Aux ΣΔ: click the dropdown menu to enable or disable this function.
AUTOCAL: click the dropdown menu to enable or disable the auto calibration function.
Prescaler: click the dropdown menu to select the prescaler.
PD Polarity: click the dropdown menu to select the PD polarity.
CP Current: click the dropdown menu to select the charge pump current.
CP Bleed: click the dropdown menu to enable or disable the charge pump bleed.
MUXOUT: click the dropdown menu to configure the MUXOUT signal, which can output to the SDO pin.
Rev. A | Page 8 of 21
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ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
Label
K1
Function
Lock Detect: click the dropdown menu to change the counting cycles for lock detect.
Loss of Lock: click the dropdown menu to enable or disable the loss of lock function.
VCO_BAND_DIV, SYTNTH_LOCK_TIMEOUT, TIMEOUT, and VCO_ALC_TIMEOUT: use these text boxes to configure the
parameters.
All changes, except within the Initial Configuration section, do not take effect until the Apply Changes button is clicked. If Auto
Apply is highlighted in the ADMV4530 Board tab, the Apply Changes feature continuously runs every few seconds, and the
Apply Changes button does not need to be clicked to apply or read back the block diagram settings.
To read back all of the SPI registers of the device, click Read All.
Click Reset Chip to reset the device.
Click Diff to show registers that are different on the device.
Click Software Defaults to restore the software defaults to the device, and then click Apply Changes.
Click Memory Map Side-By-Side to enable the side by side memory map view.
Click Proceed to Memory Map to open the ADMV4530 memory map (see Figure 10)
23154-010
K2
K3
K4
K5
K6
L
UG-1759
Figure 10. ADMV4530 Memory Map in the ACE Software
Rev. A | Page 9 of 21
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UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
PERFORMING EVALUATION
ADMV4530IQ-EVALZ OR ADMV4530IF-EVALZ
QUICK START
1.
2.
3.
4.
5.
6.
7.
8.
Connect the SDP-S to the 120-pin connector on the
ADMV4530IQ-EVALZ or the ADMV4530IF-EVALZ
evaluation board.
Connect a USB cable to the PC and then to the SDP-S.
Connect a 5 V dc power supply to the 5V and GND1 test
points. Alternatively, the power supply can be connected
to the VSUPPLY SMA port. The power supply current
limit must be set to 800 mA.
Connect the reference input signal generator to the
REF_IN port on the ADMV4530IQ-EVALZ or the
ADMV4530IF-EVALZ evaluation board. Ensure that the
board is set to the desired reference input frequency and
power level.
Depending on which board is being evaluated, connect the
signal generator for either IF input or I/Q inputs.
Connect a spectrum analyzer (or similar instrument) to
the RFOUT port.
Open the ACE software. The ADMV4530 Board appears
in the Attached Hardware section. Double-click on the
plug-in to see the chip plug-in ADMV4530 on screen.
Use the Initial Configuration in the ACE software to
initialize the chip. Be sure to select the correct mixer mode
of operation, either IF or I/Q mode. Additionally, set the
desired PLL configuration settings, and then click Apply in
the Initial Configuration section (see Figure 11).
SIGNAL GENERATOR SETTINGS
When evaluating the ADMV4530IQ-EVALZ, a good starting
point for configuring the signal generator inputs is as follows:








Reference input frequency = 200 MHz
Reference input power = 8 dBm
I/Q input frequency = 25 MHz
I/Q common mode voltage = 0.5 V
In-phase (negative) IN input power = −16 dBm
In-phase (positive) IP input power = −16 dBm
Quadrature (positive) QP input power = −16 dBm
Quadrature (negative) QP input power = −16 dBm
When evaluating the ADMV4530IF-EVALZ, a good starting
point for configuring the signal generator inputs is as follows:




Reference input frequency = 200 MHz
Reference input power = 8 dBm
IF input frequency = 2.5 GHz
IF input power = −40 dBm
Rev. A | Page 10 of 21
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23154-011
To set up the ADMV4530IQ-EVALZ or the ADMV4530IFEVALZ evaluation board, take the following steps:
Figure 11. ADMV4530 Initial Configuration Section
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
RF GAIN CONTROL

To adjust the RF gain control on either the ADMV4530IQEVALZ or the ADMV4530IF-EVALZ evaluation board, take
the following steps:

1.
2.
Connect a power supply to the RF_GAIN_TP test point
and one ground test point on the ADMV4530IQ-EVALZ
or ADMV4530IF-EVALZ evaluation board. Alternatively,
the power supply can be connected to the RF_GAIN SMA
port. The power supply current limit must be set to 1 mA.
Adjust the power supply voltage as desired from 0 V to
1.8 V. The maximum gain corresponds to 1.8 V, and the
minimum gain corresponds to 0 V. Refer to the
ADMV4530 data sheet for more information regarding
gain performance.
UG-1759
Programs the PLL for a 28 GHz LO frequency anticipating
a 200 MHz reference input frequency.
Reads back the register settings of the ADMV4530.
MANUAL CHIP RESET
For manual reset operations, the following outlines various
ways to perform a reset.


IF GAIN CONTROL
There is a reset button (S1) on the ADMV4530IQ-EVALZ
or the ADMV4530IF-EVALZ evaluation board. Pressing
this button pulls the RST pin low to initiate a reset to the
factory power-up state.
The RST pin can also be pulled low from within the ACE
software by using the dropdown menu in the lower left
corner of Figure 9 (see Label G). When using this option,
be sure to return the dropdown menu back to Normal
Operation after resetting the device.
Register 0x00 can be programmed to 0x81 to initiate a
reset of the ADMV4530.
To adjust the IF gain control on ADMV4530IF-EVALZ
evaluation board, take the following steps:

1.
Regardless of the manual reset option used, it is recommended
to perform the following after the device resets:
2.
Connect a power supply to the IF_GAIN_TP test point
and one ground test point on the ADMV4530IF-EVALZ
evaluation board. Alternatively, the power supply can be
connected to the IF_GAIN SMA port. The power supply
current limit must be set to 1 mA.
Adjust the power supply voltage as desired from 0 V to
3.3 V. The maximum gain corresponds to 0 V, and the
minimum gain corresponds to 3.3 V. Refer to the
ADMV4530 data sheet for more information regarding
gain performance.
AUTOMATED CHIP RESET
If a reset of the ADMV4530 chip is required on the
ADMV4530IQ-EVALZ or ADMV4530IF-EVALZ evaluation
board, it is recommended to use the automated reset sequence.
Click Reset Chip (see Figure 9, Label K3 and Table 1 for
additional information). This automated sequence performs
the following actions:





Toggles all SDP-S general-purpose input/outputs (GPIOs)
to a low state, which sets both the RST and PD pins of the
ADMV4530 low.
Toggles the RST pin high to bring the ADMV4530 chip
back to the normal operating state.
Programs Register 0x00 to 0x81, which also resets the
ADMV4530. This step covers legacy boards that did not
have the RST pin connected.
Programs Register 0x00 to 0x18 to enable the SDO pin on
the ADMV4530.
Programs the recommended mixer settings for IF mode.


LOSS OF BOARD COMMUNICATION
When the ADMV4530 is turned off and then on, or if the USB
cable is unplugged and plugged back in while the ACE software
is open, communication with the ADMV4530 may be lost. To
regain communication, click the System tab, click the USB
symbol in the SDP-S Controller subsystem, and then click
Acquire. If this step does not work, restart the ACE software to
reinitiate communication with the ADMV4530IQ-EVALZ or the
ADMV4530IF-EVALZ evaluation board.
REGULATOR BYPASS
Both the ADMV4530IQ-EVALZ and the ADMV4530IFEVALZ evaluation boards have voltage regulators that allow
the user to operate these evaluation boards from a single 5 V dc
power supply. The on-board voltage regulators supply several
bias voltages to the various supply pins on the chip. If desired,
these voltage regulators can be bypassed by removing the 0 Ω
registers (R25 to R28) from the ADMV4530IQ-EVALZ or the
ADMV4530IF-EVALZ evaluation board and then by injecting
each voltage independently by using the corresponding test points.
See the schematics for details (see Figure 13 and Figure 19).
Rev. A | Page 11 of 21
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Program Register 0x00 to 0x18 to enable the SDO pin on
the ADMV4530.
Read back all registers on the ADMV4530.
Rev. A | Page 12 of 21
2 3
Figure 12. ADMV4530IQ-EVALZ Evaluation Board Schematic, Page 1
AGND
2 3 4
IN
IP
QP
QN
EXT_VT
IFIN
IF_GAIN
VCC_3.3V
0
R11
VCC_3.3V
VCC_1.8V
PAD
PAD
VCC_DRV_4V
NC
NC
VCTR_RF
QN
QP
VCC_IF_3P3V
IP
IN
EXT_CAP_N
PAD
PAD
C17
1UF
AGND
AGND
AGND
AGND
C36
TBD0402
0
AGND
R16
C16
1UF
AGND
0
C15
1UF
AGND
R15
C35
TBD0402
AGND
C37
TBD0402
0
AGND
680
R44
AGND
PAD12
PAD
PAD11
PAD
30
SDO
29
SCLK
28
SDI
27
SEN
26
CP_OUT
ADMV4530ACCZ
25
PD
24
VCC_DIV_3P3V
23
VCC_VCO_3P3V
22
VG_VCO
21
VCC_BG_3P3V
PAD9
PAD
PAD10
PAD
U1
R17
C14
1UF
AGND
C13
1UF
AGND
PAD1
PAD2
1
2
3
4
5
6
7
8
9
10
PAD3
PAD4
RFOUT
0.01UF
C60
0
C34
TBD0402
AGND
C33
TBD0402
C51
0.1UF
IP
IN
QN
QP
AGND
C23
1UF
REF_IN
R14
0
R13
1.1K
R42
1.1K
R41
AGND
C11
1UF
AGND
C24
1UF
AGND
RESET_N
VCC_4.0V
IF_GAIN
AGND
C12
1UF
RF_GAIN
AGND
C31
TBD0402
AGND
C44
TBD0402
0
R24
0
C43
TBD0402
R23
AGND
10K
DNIC80
TBD0402
R45
AGND
S1
B3S-1000
3
1
4
2
AGND
C32
TBD0402
0
R12
VCC_4.0V
VCC_4.0V
VCC_1.8V
VCC_3.3V
RF_GAIN
ORG
IF_GAIN_TP
ORG
1
1
RF_GAIN_TP
HK-LR-SR2(12)
1
EXT_VT
142-0701-851
1
DNI
AGND
2 3
IFIN
AGND
2 3 4
IF_GAIN
142-0701-851
1
DNI
AGND
2 3 4
IN
142-0701-851
1
AGND
2 3 4
IP
142-0701-851
1
AGND
2 3 4
QP
142-0701-851
1
AGND
2 3 4
QN
142-0701-851
1
AGND
2 3 4
RFOUT
REF_IN
HK-LR-SR2(12)
RF_GAIN
142-0701-851
1
DNI
AGND
1
RFOUT
AGND
2 3 4
REF_IN
142-0701-851
1
PAD16
PAD
PAD15
PAD
40
VCC2_DRV_4V
39
AGND
38
RFOUT
37
AGND
36
VCC_REF_1P8V
35
REF_IN
34
RST
33
VCC_CP_PFD_3P3V
32
VCC_LDO_3P3V
31
CREG
PAD14
PAD
PAD13
PAD
PAD
PAD
EXT_CAP_P
VCC_RFAMP_4V
VCC_VVA_1P8V
NC
VCC_MIXER_3P3V
VCC2_IF_3P3V
VCC_DOUBLER_3P3V
IFIN
BG_RBIAS_1P1K
VTUNE
PAD
PAD
PAD5
PAD6
11
12
13
14
15
16
17
18
19
20
PAD7
PAD8
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R22
CPOUT
AGND
C55
10UF
R52
33
R54
33
R43
1.1K
VCC_3.3V
VCC_3.3V
IFIN
VTUNE
R51
33
R53
33
C53
1000PF
DNI
C52
0.1UF
AGND
AGND
AGND
VCC_3.3V
VCC_3.3V
DNI
PD
AGND
C18
1UF
AGND
AGND
C38
TBD0402
AGND
C39
TBD0402
AGND
AGND
C19
1UF
C40
TBD0402
0
R18
0
R19
0
R20
VTUNE
CPOUT
C20
1UF
C54
4.7UF
SDO
SCLK
SDI
CSB
R21
0
C41
TBD0402
AGND
0
C42
TBD0402
C21
1UF
AGND
C22
1UF
AGND
R1
910
C2
15NF
VCC_3.3V
VCC_3.3V_VCO
VCC_3.3V
AGND
C1
150PF
R2
AGND
C5
TBD0402
DNI
910
AGND
C3
20PF
0
R3
R5
100K
DNI
EXT_VT
0
R4
C4
20PF
DNI
AGND
23154-018
UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
EVALUATION BOARD SCHEMATICS AND ARTWORK
ADMV4530IQ-EVALZ
Rev. A | Page 13 of 21
Downloaded from Arrow.com.
Figure 13. ADMV4530IQ-EVALZ Evaluation Board Schematic, Page 2
AGND
PAD
1
R25
C63
10UF
AGND
AGND
BLK 1
GND4
RED 1
0
R27
0
R26
0
C61 R0402
10UF
VCC_4.0V
AGND
03-053057
M1
1
C65
10UF
AGND
BLK
GND3
RED 1
VCC_3.3V
AGND
BLK
GND2
RED 1
AGND
VCC_4.0V
4.0V,240MA
VCC_3.3V
3.3V,440MA
VCC_1.8V
1.8V, 3MA
VCC_1.8V
AGND
AGND
R50
10K
R49
2.1K
AGND
8
VIN
7
VIN
5
EN
4
SS
3
SENSE
EP GND
PAD 6
1
VOUT
2
VOUT
U4
ADM7170ACPZ-3.3
AGND
8
VIN
7
VIN
5
EN
4
SS
3
SENSE
EP GND
PAD 6
1
VOUT
2
VOUT
U3
ADM7171ACPZ-3.3
AGND
1
8
VOUT
VIN
2
7
VOUT
VIN
3
6
SENSE
GND
4
5
SS
EN
EP
PAD
C69
0.001UF
U2
ADM7170ACPZ-1.8
1000PF
AGND
C71
C66
10UF
1000PF
AGND
C70
C64
10UF
R30
0
0
DNI
R31
5V
AGND
AGND
5V
RED 1
AGND
C62
10UF
AGND
1
GND1
AGND
C67
10UF
R47
100K
R48
TBD0402
DNI
AGND
R46
100K
TWI_A0
AGND
8
1
VIN
VREG
7
2
EN
VOUT
3
6
REF
BYP
5
4
REF_SENSE GND
EP
PAD
C72
1UF
AGND
ADM7154ARDZ-3.3
U5
AGND
4 3 2
VSUPPLY
142-0701-851
1
AGND
8
1
2
3
4
5
6
7
8
9
10
AGND
24LC32A-I/MS
E014160
JEDEC_TYPE=MSOP8
TWI_A0
PD
SPARE
330
330
R63
330
R62
RESET_N R61
SDA_SDP
AGND
C50
0.1UF
3P3VUSB
M20-9980546
P2
U6
AGND
AGND
1
VCC_3.3V_VCO
GND5 3.3V,45MA
BLK
1 A0 VCC
2
A1
3
5
SDA
A2
SCL_SDP 6 SCL
7
WP
VSS
4
SCLK
PD
SDI
SPARE
CSB
RESET_N
3V3USB
SDO
AGND
0
RED 1
VCC_3.3V_VCO
R28
C73
1UF
AGND
C68
10UF
P1
FX8-120S-SV(21)
AGND
61
RESET_IN_N
BMODE1
62
UART_RX
UART_TX
63
GND
GND
64
RESET_OUT_N
SLEEP_N
65
EEPROM_A0
WAKE_N
66
NC
NC
67
NC
NC
68
NC
NC
69
GND
GND
70
NC
NC
71
NC
CLKOUT
72
TMR_C
TMR_D
73
TMR_A
TMR_B
74
GPIO6
GPIO7
75
GND
GND
76
GPIO4
GPIO5
77
GPIO2
GPIO3
78
GPIO0
GPIO1
79
SCL_1
SCL_0
80
SDA_1
SDA_0
81
GND
GND
82
SPI_SEL1/SPI_SS_N
SPI_CLK
83
SPI_SEL_C_N
SPI_MISO
84
SPI_SEL_B_N
SPI_MOSI
85
GND
SPI_SEL_A_N
86
SERIAL_INT
GND
87
SPI_D3
SPORT_TSCLK
88
SPI_D2
SPORT_DT0
89
SPORT_DT1
SPORT_TFS
90
SPORT_DR1
SPORT_RFS
91
SPORT_TDV1
SPORT_DR0
92
SPORT_TDV0
SPORT_RSCLK
93
GND
GND
94
PAR_FS1
PAR_CLK
95
PAR_FS3
PAR_FS2
96
PAR_A1
PAR_A0
97
PAR_A3
PAR_A2
98
GND
GND
99
PAR_CS_N
PAR_INT
100
PAR_RD_N
PAR_WR_N
101
PAR_D1
PAR_D0
102
PAR_D3
PAR_D2
103
PAR_D5
PAR_D4
104
GND
GND
105
PAR_D7
PAR_D6
106
PAR_D9
PAR_D8
107
PAR_D11
PAR_D10
108
PAR_D13
PAR_D12
109
PAR_D14
GND
110
GND
PAR_D15
111
PAR_D17
PAR_D16
112
PAR_D19
PAR_D18
113
PAR_D21
PAR_D20
114
PAR_D23
PAR_D22
115
GND
GND
116
USB_VBUS
VIO
117
GND
GND
118
GND
GND
119
NC
NC
120
VIN
NC
AGND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R29
SCL_SDP
SDA_SDP
3P3VUSB
AGND
AGND
AGND
AGND
SCLK
C84
TBD0402
DNI
CSB
C83
TBD0402
DNI
SDI
C82
TBD0402
DNI
SDO
C81
TBD0402
DNI
23154-019
BLK
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
23154-020
UG-1759
23154-021
Figure 14. ADMV4530IQ-EVALZ Evaluation Board Layer 1
Figure 15. ADMV4530IQ-EVALZ Evaluation Board Layer 2
Rev. A | Page 14 of 21
Downloaded from Arrow.com.
UG-1759
23154-022
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
23154-023
Figure 16. ADMV4530IQ-EVALZ Evaluation Board Layer 3
Figure 17. ADMV4530IQ-EVALZ Evaluation Board Layer 4
Rev. A | Page 15 of 21
Downloaded from Arrow.com.
Rev. A | Page 16 of 21
Figure 18. ADMV4530IF-EVALZ Evaluation Board Schematic, Page 1
VCC_3.3V
AGND
2 3 4
RF_GAIN
ORG
IFIN
EXT_VT
VCC_3.3V
VCC_1.8V
VCC_4.0V
AGND
R42
VCTR_RF
QN
QP
VCC_IF_3P3V
IP
IN
EXT_CAP_N
PAD
PAD
PAD
PAD
VCC_DRV_4V
NC
NC
C17
1UF
AGND
AGND
AGND
AGND
AGND
C36
TBD0402
0
AGND
R16
C16
1UF
AGND
0
C15
1UF
AGND
R15
C35
TBD0402
AGND
C37
TBD0402
0
AGND
R44
680
VTUNE
AGND
C55
10UF
R52
33
R54
33
R43
1.1K
AGND
C53
1000PF
DNI
C52
0.1UF
VCC_3.3V
VCC_3.3V
IFIN
R21
0
C41
TBD0402
AGND
AGND
R51
33
R53
33
R22
0
C42
TBD0402
AGND
C21
1UF
AGND
C22
1UF
PAD12
PAD
PAD11
PAD
30
SDO
29
SCLK
28
SDI
27
SEN
26
CPOUT
CP_OUT
ADMV4530ACCZ
25
PD
24
VCC_DIV_3P3V
23
VCC_VCO_3P3V
22
VG_VCO
21
VCC_BG_3P3V
PAD9
PAD
PAD10
PAD
U1
R17
C14
1UF
AGND
C13
1UF
AGND
PAD1
PAD2
1
2
3
4
5
6
7
8
9
10
PAD3
PAD4
RFOUT
0.01UF
C60
0
C34
TBD0402
AGND
C33
TBD0402
C51
0.1UF
AGND
C23
1UF
REF_IN
R14
0
R13
1.1K
RF_GAIN
C12
1UF
R41
1.1K
AGND
C11
1UF
AGND
C24
1UF
AGND
RESET_N
AGND
C31
TBD0402
AGND
C44
TBD0402
IF_GAIN
0
0
R24
C43
TBD0402
0
R23
AGND
10K
DNIC80
TBD0402
R45
AGND
S1
B3S-1000
3
1
4
2
R11
AGND
C32
TBD0402
0
R12
VCC_4.0V
VCC_4.0V
VCC_1.8V
VCC_3.3V
IF_GAIN
IF_GAIN_TP
ORG
1
1
RF_GAIN_TP
HK-LR-SR2(12)
1
EXT_VT
142-0701-851
1
DNI
AGND
2 3
IFIN
AGND
IF_GAIN
142-0701-851
1
DNI
2 3 4
AGND
2 3 4
RFOUT
REF_IN
HK-LR-SR2(12)
RF_GAIN
142-0701-851
1
DNI
AGND
2 3
1
RFOUT
AGND
2 3 4
REF_IN
142-0701-851
1
PAD16
PAD
PAD15
PAD
40
VCC2_DRV_4V
39
AGND
38
RFOUT
37
AGND
36
VCC_REF_1P8V
35
REF_IN
34
RST
33
VCC_CP_PFD_3P3V
32
VCC_LDO_3P3V
31
CREG
PAD14
PAD
PAD13
PAD
PAD
PAD
EXT_CAP_P
VCC_RFAMP_4V
VCC_VVA_1P8V
NC
VCC_MIXER_3P3V
VCC2_IF_3P3V
VCC_DOUBLER_3P3V
IFIN
BG_RBIAS_1P1K
VTUNE
PAD
PAD
PAD5
PAD6
11
12
13
14
15
16
17
18
19
20
PAD7
PAD8
Downloaded from Arrow.com.
PD
SDO
SCLK
SDI
CSB
DNI
C54
4.7UF
C38
TBD0402
C18
1UF
AGND
AGND
AGND
AGND
C39
TBD0402
AGND
C40
TBD0402
VTUNE
CPOUT
C19
1UF
AGND
C20
1UF
VCC_3.3V
VCC_3.3V
0
R18
0
R19
0
R20
AGND
C1
150PF
R2
AGND
C5
TBD0402
DNI
910
VCC_3.3V
VCC_3.3V_VCO
VCC_3.3V
AGND
R1
910
C2
15NF
AGND
C3
20PF
0
R3
R5
100K
DNI
EXT_VT
0
R4
AGND
C4
20PF
DNI
23154-012
UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
ADMV4530IF-EVALZ
Rev. A | Page 17 of 21
Downloaded from Arrow.com.
Figure 19. ADMV4530IF-EVALZ Evaluation Board Schematic, Page 2
AGND
PAD
1
AGND
BLK
1
GND4
RED 1
R25
0
R27
0
R26
0
R0402
C63
10UF
03-053057
M1
C61
10UF
AGND
VCC_4.0V
AGND
C65
10UF
AGND
BLK
GND3
RED 1
VCC_3.3V
1
GND2
BLK
AGND
AGND
VCC_4.0V
4.0V,240MA
VCC_3.3V
3.3V,440MA
VCC_1.8V
1.8V, 3MA
VCC_1.8V
RED 1
AGND
AGND
R50
10K
R49
2.1K
AGND
8
VIN
7
VIN
5
EN
4
SS
3
SENSE
EP GND
PAD 6
1
VOUT
2
VOUT
U4
ADM7170ACPZ-3.3
AGND
8
VIN
7
VIN
5
EN
4
SS
3
SENSE
EP GND
PAD 6
1
VOUT
2
VOUT
U3
ADM7171ACPZ-3.3
AGND
1
8
VOUT
VIN
2
7
VOUT
VIN
3
6
SENSE
GND
4
5
SS
EN
EP
PAD
C69
0.001UF
U2
ADM7170ACPZ-1.8
1000PF
AGND
C71
C66
10UF
1000PF
AGND
C70
C64
10UF
R30
0
0
DNI
R31
5V
AGND
5V
RED 1
AGND
AGND
C62
10UF
AGND
1
GND1
AGND
C67
10UF
C68
10UF
RED 1
R47
100K
R48
TBD0402
DNI
AGND
R46
100K
TWI_A0
8
AGND
24LC32A-I/MS
E014160
JEDEC_TYPE=MSOP8
SDA_SDP
AGND
C50
0.1UF
3P3VUSB
M20-9980546
P2
U6
AGND
1
2
3
4
5
6
7
8
9
10
VCC
1
A0
2
A1
3
5
A2
SDA
SCL_SDP 6 SCL
7
WP
VSS
4
SCLK
PD
SDI
SPARE
CSB
RESET_N
3V3USB
SDO
330
R63
PD
330
330
R62
R61
TWI_A0
SPARE
RESET_N
VCC_3.3V_VCO
3.3V,45MA
VCC_3.3V_VCO
8
1
AGND
VIN
VREG
R28
7
2
EN
VOUT
6
3
0
GND5
REF
BYP
5
4
REF_SENSE GND
C73
EP
BLK 1
1UF
PAD
AGND
C72
1UF
AGND
AGND
AGND
AGND
ADM7154ARDZ-3.3
U5
AGND
4 3 2
VSUPPLY
142-0701-851
1
P1
FX8-120S-SV(21)
AGND
61
RESET_IN_N
BMODE1
62
UART_RX
UART_TX
63
GND
GND
64
RESET_OUT_N
SLEEP_N
65
EEPROM_A0
WAKE_N
66
NC
NC
67
NC
NC
68
NC
NC
69
GND
GND
70
NC
NC
71
CLKOUT
NC
72
TMR_C
TMR_D
73
TMR_A
TMR_B
74
GPIO6
GPIO7
75
GND
GND
76
GPIO4
GPIO5
77
GPIO2
GPIO3
78
GPIO0
GPIO1
79
SCL_1
SCL_0
80
SDA_1
SDA_0
81
GND
GND
82
SPI_SEL1/SPI_SS_N
SPI_CLK
83
SPI_MISO
SPI_SEL_C_N
84
SPI_MOSI
SPI_SEL_B_N
85
SPI_SEL_A_N
GND
86
SERIAL_INT
GND
87
SPI_D3
SPORT_TSCLK
88
SPI_D2
SPORT_DT0
89
SPORT_DT1
SPORT_TFS
90
SPORT_DR1
SPORT_RFS
91
SPORT_DR0
SPORT_TDV1
92
SPORT_RSCLK
SPORT_TDV0
93
GND
GND
94
PAR_FS1
PAR_CLK
95
PAR_FS3
PAR_FS2
96
PAR_A1
PAR_A0
97
PAR_A3
PAR_A2
98
GND
GND
99
PAR_INT
PAR_CS_N
100
PAR_RD_N
PAR_WR_N
101
PAR_D1
PAR_D0
102
PAR_D3
PAR_D2
103
PAR_D5
PAR_D4
104
GND
GND
105
PAR_D7
PAR_D6
106
PAR_D9
PAR_D8
107
PAR_D11
PAR_D10
108
PAR_D13
PAR_D12
109
PAR_D14
GND
110
GND
PAR_D15
111
PAR_D17
PAR_D16
112
PAR_D19
PAR_D18
113
PAR_D21
PAR_D20
114
PAR_D23
PAR_D22
115
GND
GND
116
USB_VBUS
VIO
117
GND
GND
118
GND
GND
119
NC
NC
120
VIN
NC
AGND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R29
SCL_SDP
SDA_SDP
SDO
C84
TBD0402
DNI
CSB
C83
TBD0402
DNI
SDI
C82
TBD0402
DNI
3P3VUSB
AGND
AGND
AGND
AGND
SCLK
C81
TBD0402
DNI
23154-013
BLK
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
23154-014
UG-1759
23154-015
Figure 20. ADMV4530IF-EVALZ Evaluation Board Layer 1
Figure 21. ADMV4530IF-EVALZ Evaluation Board Layer 2
Rev. A | Page 18 of 21
Downloaded from Arrow.com.
UG-1759
23154-016
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
23154-017
Figure 22. ADMV4530IF-EVALZ Evaluation Board Layer 3
Figure 23. ADMV4530IF-EVALZ Evaluation Board Layer 4
Rev. A | Page 19 of 21
Downloaded from Arrow.com.
UG-1759
ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
ORDERING INFORMATION
BILL OF MATERIALS
The ADMV4530IQ-EVALZ bill of materials is identical to the ADMV4530IF-EVALZ except for one row (see Note 1 of Table 2).
Table 2. ADMV4530IQ-EVALZ
Quantity
5
1
14
1
1
3
1
1
8
1
2
2
5
1
2
6
1
Reference Designator
5V, VCC_1.8V, VCC_3.3V,
VCC_3.3V_VCO, VCC_4.0V
C1
C11 to C24
C2
C3
C50 to C52
C55
C60
C61 to C68
C69
C70, C71
C72, C73
GND1 to GND5
RFOUT
IF_GAIN_TP, RF_GAIN_TP
IN, IP, QN, QP, REF_IN, VSUPPLY1
P1
1
2
20
2
3
1
2
2
1
4
3
1
1
1
1
1
1
1
20
1
1
1
3
1
1
1
P2
R1, R2
R3, R4, R11 to R25, R28 to R30
R26, R27
R41 to R43
R44
R45, R50
R46, R47
R49
R51 to R54
R61 to R63
S1
U1
U2
U3
U4
U5
U6
C5, C31 to C44, C80 to C84
C4
C53
C54
EXT_VT, IF_GAIN, RF_GAIN
R31
R48
R5
1
Description
Test points, red
Manufacturer
Components Corporation
Part Number
TP-104-01-02
Capacitor, 150 pF, 50 V, 5%, 0402
Capacitors, 1 μF, 16 V, 10%, 0402
Capacitor, 15 nF, 35 V, 10%, 0402
Capacitor, 20 pF, 16 V, 5%, 0402
Capacitors, 0.1 μF, 16 V, 10%, 0402
Capacitor, 10 μF, 6.3 V, 20%, 0402
Capacitor, 0.01 μF, 50 V, 10%, 0402
Capacitors, 10 μF, 16 V, 10%, 0603
Capacitor, 1 nF, 50 V, 5%, 0603
Capacitors, 1 nF, 50 V, 5%, 0402
Capacitors, 1 μF, 16 V, 10%, 0603
Test points, black
Connector, 2.92 mm, 40 GHz
Test points, orange
Connectors, edge launch, SMA
Connector, vertical, surface-mount
technology (SMT), 120-pin
Connector, vertical, header, 10-pin
Resistors, 910 Ω, 1/16 W, 0.1%, 0402
Resistors, 0 Ω, 1/10 W, 0402
Resistors, 0 Ω, 1/10 W, 0603
Resistors, 1.1 kΩ, 1/16 W, 1%, 0402
Resistor, 680 Ω, 1/16 W, 0.1%, 0402
Resistors, 10 kΩ, 1/10 W, 1%, 0402
Resistors, 100 kΩ, 1/16 W, 1%, 0402
Resistor, 2.1 kΩ, 1/16 W, 1%, 0402
Resistors, 33 Ω, 1/10 W, 5%, 0402
Resistors, 330 Ω, 1/16 W, 5%, 0402
Switch, mechanical, push button
IC, Ka band upconverter
IC, LDO regulator, 1.8 V
IC, LDO regulator, 3.3 V
IC, LDO regulator, 3.3 V
IC, LDO regulator, 3.3 V
IC, 24LC32A, EEPROM, I2C
Capacitors, 0402, do not install (DNI)
Capacitor, 20 pF, 16 V, 5%, 0402, DNI
Capacitor, 1 nF, 50 V, 5%, 0402, DNI
Capacitor, 4.7 μF, 16 V, 10%, 0603, DNI
Connectors, edge launch, SMA, DNI
Resistor, 0 Ω, 1/10 W, 0402, DNI
Resistor, 0402, DNI
Resistor, 100 kΩ, 1/16 W, 0402, DNI
Murata
Yageo
TDK
AVX Corporation
Kemet
Samsung
Murata
Murata
Murata
Murata
TDK
Components Corporation
Hirose Electric Co.
Components Corporation
Cinch Connectivity
Hirose Electric Co.
GRM1555C1H151JA01D
CC0402KRX5R7BB105
CGA2B3X7R1V153K050BB
0402YA200JAT2A
C0402C104K4RACTU
CL05A106MQ5NUNC
GCM155R71H103KA55D
GRM188R61C106KAALD
GRM1885C1H102JA01D
GRM1555C1H102JA01
CGA3E1X7R1C105K080AC
TP-104-01-00
HK-LR-SR2(12)
TP-104-01-03
142-0701-851
FX8-120S-SV(21)
Harwin Inc.
Panasonic
Panasonic
Panasonic
Yageo
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Omron Electronics Inc.
Analog Devices
Analog Devices
Analog Devices
Analog Devices
Analog Devices
Microchip Technology
Not applicable
AVX Corporation
Murata
TDK
Cinch Connectivity
Panasonic
Not applicable
Panasonic
M20-9980546
ERA-2AEB911X
ERJ-2GE0R00X
ERJ-3GEY0R00V
RC0402FR-071K1L
ERA-2ARB681X
ERJ-2RKF1002X
ERJ-2RKF1003X
ERJ-2RKF2101X
ERJ-2GEJ330X
ERJ-2GEJ331X
B3S1000
ADMV4530ACCZ
ADM7170ACPZ-1.8-R7
ADM7171ACPZ-3.3-R7
ADM7170ACPZ-3.3-R7
ADM7154ARDZ-3.3-R7
24LC32A-I/MS
Not applicable
0402YA200JAT2A
GRM1555C1H102JA01
C1608X5R1C475K080AC
142-0701-851
ERJ-2GE0R00X
Not applicable
ERJ-2RKF1003X
For the ADMV4530IF-EVALZ, only REF_IN and VSUPPLY are applicable for this row.
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ADMV4530IQ-EVALZ/ADMV4530IF-EVALZ Evaluation Board User Guide
UG-1759
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written
notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED,
RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF
INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S
POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES
SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will
comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the
Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and
Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is
expressly disclaimed.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG23154-3/20(A)
Rev. A | Page 21 of 21
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