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ISSCC 2009 / SESSION 19 / ANALOG TECHNIQUES / 19.5
19.5
A 25mA 0.13µm CMOS LDO Regulator with PowerSupply Rejection Better Than −56dB up to 10MHz
Using a Feedforward Ripple-Cancellation Technique
Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari,
Edgar Sánchez-Sinencio
Texas A&M University, College Station, TX
Low drop-out (LDO) linear regulators have become a key building block in
portable communication systems for power management ICs. The LDO usually comes after a switching DC-DC converter to reduce the output ripples and
provide a regulated voltage source for noise-sensitive blocks. For a higher
level of integration, there is a need to increase the operating frequency of the
switching converters [1]. This necessitates a subsequent LDO regulator with
high ripple rejection at frequencies up to several MHz. These LDO regulators
should also provide a low drop-out voltage to cope with the low supply voltage of the state-of-the-art CMOS technologies. In addition, due to the feedback nature of the system, the LDO should be stable for a wide range of supply currents while consuming a very low quiescent current.
Power-supply rejection (PSR) techniques have been reported by means of
simple RC filtering at the input of the LDO [2], cascading two regulators [2],
or cascoding an NMOS device with the PMOS pass transistor along with either
RC filtering [3] or charge-pump technique to bias the gate of the NMOS transistor [4]. Simple RC filtering increases the drop-out voltage in LDO regulators that supply high current due to the high voltage drop across the resistance. Cascading regulators also suffer from high drop-out voltage, in addition
to their large area and high quiescent current. Similarly, using an NMOS cascode transistor leads to a high drop-out voltage. In the case of the chargepump technique, a clock is necessary along with RC filtering to remove the
clock ripples, which leads to a higher complexity of the system. The main idea
behind all the previously proposed techniques is that they focus on providing
more isolation between the input and output along the high-current signal
path. As a result, the drop-out voltage is higher than 0.6V, which is not suitable for low-voltage state-of-the-art technologies. In addition, these techniques are unable to provide sufficient PSR (better than −50dB) at frequencies
up to several MHz, even though they achieve a high PSR at low frequencies.
This paper presents a high PSR low-voltage LDO regulator using a feedforward ripple cancellation (FFRC) technique. The LDO maintains conventional
loop dynamics, supplies high current, has a low quiescent current, and provides a PSR better than −56dB over a wide frequency range. Figure 19.5.1
presents a simplified block-level description of the LDO with feedforward cancellation technique. The supply ripples, appearing at the source of pass transistor Mp, are reproduced on the gate of Mp using the feedforward path. Thus,
the gate-source voltage of Mp is free of ripples. Ideally, a feedforward path with
unity gain should achieve complete ripple cancellation. However, due to the
finite output conductance of Mp, the feedforward gain should be larger than
unity. The capacitor CF1 is added to provide a zero that cancels the pole existing at the gate of the pass transistor to extend the frequency range. Hence,
the limit of this cancellation technique is set by the internal poles of the summing and feedforward amplifiers. The feedforward gain is based on the ratio
of resistors to reduce its dependency on process, voltage and temperature
variations. As high PSR is only required when the output is stabilized, this system biases the positive terminal of the feedforward amplifier directly from the
output. This approach requires no additional voltage reference circuit. Similar
to conventional LDOs, the ripples that leak through the error amplifier and the
bandgap voltage reference circuit determine the PSR of the LDO at low frequencies. Therefore, an error amplifier and a voltage reference circuit with
high power-supply rejection ratio (PSRR) are designed. The main advantage
of this FFRC approach is achieving a high PSR for a wide frequency range,
without the need to increase the loop bandwidth and hence the quiescent
power consumption. Also, this approach preserves the same low drop-out
voltage of a conventional regulator, since supply rejection does not occur on
the high-current signal path.
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• 2009 IEEE International Solid-State Circuits Conference
Figure 19.5.2 shows the transistor-level implementation of the LDO. The error
amplifier utilizes current sources with improved output impedance as active
loads [5]. This configuration achieves a boosted gain of 55dB and a PSRR
exceeding 90dB at DC with a limited output swing. This limited swing could
be problematic for conventional LDOs when the error amplifier drives the pass
transistor to accommodate a wide range of load currents. However, in the presented LDO, the summing amplifier is the one responsible for driving the gate
of the pass transistor. This amplifier is implemented using a two stage amplifier configuration with wide output swing. The same amplifier core is used for
the feedforward amplifier. The total on-chip compensation capacitance for the
amplifiers is 5pF. The three amplifiers draw a total current of 40µA, equally
distributed among them. The bandgap voltage reference circuit with a PSRR
of 90dB at DC consumes a current of 8µA, and establishes a supply independent bias of 0.5V. An off-chip low-cost low-ESR ceramic capacitor of 4µF is
used to stabilize the system. The LDO is capable of sourcing an output current
up to 25mA.
The LDO with FFRC technique is implemented in a 0.13µm CMOS process.
The minimum input of the LDO is 1.15V and the output is 1V, which shows a
drop-out voltage of 0.15V. The measured PSR for different load currents is
shown in Fig. 19.5.3. As depicted, the LDO achieves a worst-case PSR at
10MHz of −56dB for a load current of 25mA. For frequencies above 4MHz, the
PSR starts to increase due to the internal poles of the feedforward and summing amplifiers. For a conventional LDO with comparable performance at MHz
frequencies, the open-loop gain and bandwidth should be increased, simultaneously. This increase comes at the cost of higher quiescent current as in [6],
which is not the case using the FFRC technique. In Fig. 19.5.4, the load transient measurement of the load regulation shows a maximum overshoot of
15mV for a 25mA load step with rise and fall times of 10ns. Compared to [4],
this FFRC technique does not degrade the load transient response because the
high-current path does not include any additional device for isolation other
than the main pass transistor. Simulations over process, voltage, and temperature variations indicate that the LDO achieves comparable performance to
that measured in the lab, making the LDO robust for high-performance powermanagement ICs.
The measurements confirm a PSR of better than −56dB up to a frequency of
10MHz, a minimum drop-out voltage of 0.15V, and a quiescent current of
50µA. Figure 19.5.5 compares key LDO performance parameters to those of
[4] and [6]. Finally, Fig. 19.5.6 shows a chip micrograph.
Acknowledgements:
The authors would like to thank Texas Instruments for funding support and United
Microelectronics Corporation for chip fabrication.
References:
[1] M.D. Mulligan, B. Broach, T.H. Lee, “A 3MHz Low-Voltage Buck Converter with
Improved Light Load Efficiency,” ISSCC Dig. Tech. Papers, pp. 528-529, Feb., 2007.
[2] Maxim, “Application Note 883: Improved Power Supply Rejection for IC Linear
Regulators,” Oct., 2002, Accessed on Dec. 4, 2008, ‘http://www.maximic.com/appnotes.cfm/appnote_number/883”.
[3] J.M. Ingino and V.R. von Kaenel, “A 4-GHz Clock System for a High-Performance
System-on-a-Chip Design,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp.1693-1698,
Nov., 2001.
[4] V. Gupta and G. A. Rincón-Mora, “A 5mA 0.6µm CMOS Miller-Compensated LDO
Regulator with −27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip
Capacitance,” ISSCC Dig. Tech. Papers, pp. 520-521, Feb., 2007.
[5] V. Ivanov and I.M. Filanovsky, Operational Amplifier Speed and Accuracy
Improvement, Kluwer, 2004.
[6] Y. Lam and W. Ki, “A 0.9V 0.35µm Adaptively Biased CMOS LDO Regulator with Fast
Transient Response,” ISSCC Dig. Tech. Papers, pp. 442-443, Feb., 2008.
978-1-4244-3457-2/09/$25.00 ©2009 IEEE
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Figure 19.5.1: Block-level representation of the feedforward cancellation technique.
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Figure 19.5.2: Schematic of the LDO with feedforward ripple cancellation technique.
Figure 19.5.3: Measured PSR for different load currents.
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Figure 19.5.5: Performance summary and comparison with recently published LDO
regulators.
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Figure 19.5.6: Chip micrograph.
• 2009 IEEE International Solid-State Circuits Conference
978-1-4244-3457-2/09/$25.00 ©2009 IEEE
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