N c-3
POWER MOSFET FAILURE REVISITED*
David L. Blackburn
Semiconductor Electronics Division
National Bureau of Standards
Gaithersburg, MD 20899
exceeded some critical value, called the critical current.
The failure signature (a rapid collapse of the blocking
voltage capability) is identical to that for second breakdown in bipolar transistors, and therefore this failure
mode is also called second breakdown in power MOSFETs. It was shown at that time that the failure of the
‘pre-1985’ devices was not related to the energy dissipated by the device during turn-off. In fact, the ‘pre1985’ devices would either fail immediately upon beginning to avalanche (and thus dissipate no energy during avalanche) or would safely turn off without failure
through the entire time of avalanche breakdown.
ABSTRACT
The failure of power MOSFETs during avalanche
breakdown is discussed. A theory is presented that relates the failure to the temperature rise of the chip during
the avalanche breakdown and to a critical current for failure. It is shown that the energy that can be safely dissipated during avalanche breakdown decreases as the starting current increases or as the case temperature increases.
Thus, if power MOSFETs are to be rated for their energy
dissipation capability during avalanche breakdown, both
the starting current and temperature must be specified
as it is these two parameters that determine the failure
limits and not the energy.
The purpose of this paper is to discuss the applicability of the previously reported results to present-day
power MOSFETs and to discuss how the failure of these
devices is related to the current and energy dissipated
during avalanche breakdown. A simplified theory for the
thermal and electrical behavior of power MOSFETs during avalanche breakdown is presented. Experimental results of the failure of power MOSFETs as a function of
energy dissipated during avalanche breakdown, current,
and temperature are given. Also, some manufacturers
data appearing on data sheets are used to help substantiate the results.
INTRODUCTION
Over the past several years, the capability of power
MOSFETs to dissipate energy safely during avalanche
breakdown has increased tremendously [l-31. Prior to
about 1985, power MOSFETs essentially had no capability to dissipate energy during avalanche breakdown.
Today, there are power MOSFETs which have ratings
for single event energy dissipation during avalanche of
from a few millijoules to nearly 1000 mJ, and of course,
the actual capabilities exceed that. The reason for the
expanded capability of power MOSFETs is primarily related to improved design of the power MOSFET cell
structure. Processing and design innovations have permitted a reduction of the intrinsic resistance of the pbody (for an n-channel device) below the n-type source
and have made the resistance more uniform from cell to
cell. This permits an increase in the current which can
flow in the p-body without activating the intrinsic bipolar
transistor.
BACKGROUND
The rating of power transistors on the basis of their
capability to dissipate energy during avalanche breakdown is not new. Bipolar power transistors have had
an avalanche energy rating for many years [5]. The energy dissipation capability during avalanche breakdown
for bipolar transistors has been given the symbol E , / * ,
to denote a ‘second breakdown energy’. A difficulty with
this concept is that the relationship between the capability of most modern bipolar transistors to dissipate energy
during avalanche breakdown and their failure due to second breakdown is very weak. It is accepted that the majority of bipolar transistor failures during turn-off result
from second breakdown initiated by avalanche injection
[6-91. The phenomenon of avalanche injection depends
strongly upon current density and voltage (electric field)
Research reported in 1985 [4] attributed the failure
of power MOSFETs during turn-off to activation of the
intrinsic bipolar transistor when the avalanche current
* Contribution of the National Bureau of Standards; not subject to copyright.
PESC ’88 RECORD (APRIL 1988)
68 1
CH 2523-9/88/0000-0681 $1.00 0 1988 IEEE
but only weakly upon device temperature (and therefore
energy dissipation). It has been demonstrated that the
energy dissipated by a bipolar transistor during turn-off
has very little or no effect upon its second breakdown
capability [9].
As already mentioned, early research on the failure
of power MOSFETs also showed their failure during turnoff to be independent of the energy dissipated during
avalanche breakdown [4]. It was shown that the failure
occurred at a critical value of avalanche current, that the
critical current decreased with increasing temperature,
and that if a device began to avalanche, it would either
fail immediately or safely turn-off i.e., it would not fail
during avalanche breakdown.
800
Approximate
-
Chip
1
7
E
8
6oo
500
>
400
z
300
Y
2 200
I
\
\
.
100
0
_L
I
20
40
STEADY STATE CURRENT RATING (AI
Figure 1. Manufacturers’ rated avalanche breakdown energy capability versus rated current for five different chip
sizes.
It is important to note that most ‘pre-1985’ devices
could not safely avalanche at any significant current level.
Few if any devices of that time could safely avalanche at
room temperature at a current as large as the the maximum steady-state, rated current level, 10. The critical
avalanche current for failure of these early devices was
very low so the capability of the devices to dissipate energy during avalanche (E = + L I Z )was essentially nonexistent. If the drain voltage were clamped at or below the
rated drain voltage (which is always below the avalanche
breakdown voltage), the device would typically turn off
safely for all rated currents.
failure occurred at a given temperature. The maximum
power dissipatedin avalanchebreakdown ( I D XVBR,where
ID is the maximum drain current and VBRis the avalanche
breakdown voltage) is nearly constant for a given chip
area. This is because the rated avalanche breakdown
voltage, v B R ) D S , is nearly proportional to the reciprocal of the rated current, which occurs because the onstate power dissipation rating is kept constant (I‘dc =
I& x RDS(OTZ)
where R ~ s ( ma) V;42 [lo]) for a given
chip area.
Whereas the early power MOSFETs were observed
never to fail during avalanche breakdown, many present
day devices can fail after beginning to avalanche safely.
Also, many present day devices can safely avalanche at
currents considerably larger than I D . Because these devices can dissipate considerable energy during avalanche
and thus may become quite hot, the question arises as
to whether present day power MOSFETs fail by some
mechanism that differs from that of the earlier devices.
Figure 1 shows the energy rating (at I D )versus current rating for a number of devices from one manufacturer. Five different chip sizes are included. As can be
seen, for a given chip size, as the rated current increases,
the rated energy capability during avalanche breakdown
decreases. This strongly suggests that the devices do
not fail at a constant temperature, but that as the current increases, the temperature at which failure occurs
decreases (as suggested by the decreasing energy rating
with increasing current rating for each chip size). It is
emphasized that the data in Figure 1 are derived from
manufacturers’ ratings and are not the actual failure limits of the devices. It is assumed that the trends shown
by the rating data agree with those shown by the actual
failure data.
Because energy dissipation is associated with temperature rise it is possible that devices fail during avalanche
because they reach some critical failure temperature. A
possible mechanism may be that some portion of the device reaches a high enough temperature for the silicon to
become intrinsic or to cause some irreversible damage to
the silicon or silicon-metal system. If this were the case,
the temperature at which the devices fail should be independent of current or other device parameters. It will be
shown later that if the chip area and maximum power are
kept constant, the peak temperature rise, ATM,during
avalanche breakdown can be related to the total energy
dissipated, E , by:
AT,
No. Area lmm21
--
700
THEORY
A schematic of an n-channel power MOSFET is shown
in figure 2a. The gate voltage and drain current and voltage waveforms for switching the device with an inductive
load at the drain are shown in figure 2b. The portions
of the waveforms of interest here are those during turnoff, after the gate voltage has gone below the threshold
voltage and the drain current begins to decrease and the
drain voltage to increase. Before the gate voltage falls below the threshold voltage, the drain current is conducted
through the MOSFET channel. As the gate voltage is decreased, the channel is removed and the current is trans-
oc @.
In other words, if the chip size were kept constant (thus
also keeping the maximum power nearly constant), one
would expect the avalanche energy capability or rating
to be independent of current capability or rating if the
682
Source metal
-,
roXid>Silicon
gate
ody
the drain. Providing that the power MOSFET does not
fail during the avalanche breakdown time, the total energy stored in the inductor before turn-off was initiated
is dissipated in the MOSFET. This energy is given by:
1
E = - x L x It
2
HIGH RESISTIVITY DRAIN REGION n-
DRAIN CONTACT REGION (n + )
a
1
I
where E is the energy and 10 is the current immediately
prior to the beginning of turn-off (the on-state or starting
current). During the time that the current is linearly decreasing with time, the temperature of the power MOSFET chip will change. This is due to the energy that
is being dissipated within the chip. The instantaneous
power being dissipated, P ( t ) ,is given by:
P ( t ) = i ( t ) X U' = i ( t )x VBR
where i(t), the current, is decreasing linearly with time
as :
VBR
qt) = io - x t.
L
VBR-
VdS 0
-
The total energy dissipated from the beginning of to any
time t during avalanche breakdown is given by:
n
I
l+&--- -
'
I
1
1
I
I
Avalanche breakdown d
e
rt
E=
b
Figure 2. a) Schematic of an n-channel power MOSFET.
b) Gate voltage, V,, drain current, I d , and drain voltage,
V,., waveformsfor switching an inductive load at the drain
of the MOSFET.
ferred from the channel to the drain-source diode. During
the time that the drain-source voltage is rising, the drainsource diode current is composed of displacement current
from the formation of a depletion region at the junction
required to support the rising voltage. As the depletion
region expands, the magnitude of the electric field in the
depletion region increases. Eventually, the field becomes
large enough to cause significant avalanche generation of
carriers to occur, at which time the voltage ceases to rise
and becomes constant. This is the beginning of sustaining
and the drain-source diode current (and consequently all
of the MOSFET current) is avalanche current sustained
by the carriers generated within the depletion region.
Pdt = IL(1; - i2).
2
To calculate the rise in temperature, it will be assumed that the heat flow can be described in one dimension. This is equivalent to assuming that the power is
dissipated uniformly over the entire top surface and that
the chip is infinitely thick (or is thick enough so that the
thermal energy does not reach the bottom of the chip
during the time of interest). It has been demonstrated
that for the first 2 0 0 p or so of heating or cooling, onedimensional theory is valid [ll]. For the one-dimensional
system, the temperature rise after some time t for a eonstant power PO is given by:
In the following development of the temperature rise
of the chip during avalanche breakdown, it is assumed for
simplicity that both the drain supply voltage, V o o , and
the energy supplied by the drain voltage supply during
avalanche are small enough to be ignored. Also, the resistance of the inductor at the drain terminal is assumed
to be negligible. Once avalanche has begun, the current,
i, begins to decrease linearly with a time rate of decrease
given by:
-d i= - VBR
TIME, t
where VBRis the avalanche breakdown voltage (assumed
to be constant here) and L is the circuit inductance at
Figure 3. Approximation of power versus time during
avalanche breakdown using a staircase function.
dt
L
683
where:
2
K = A@
3)
where A(cmZ)is the area of power generation, and p (
is the density, k( *)
is the thermal conductivity, and
is the thermal capacity of silicon. As described
c( *)
9 deg c
previously, the power, P , is not constant but is decreasing
linearly with time as the current is decreasing. Because
of the linearity of the thermal equations, the nonconstant
power can be accounted for by using the principle of superposition [12]. Doing this, the power versus time relation is
approximated by a staircase function as demonstrated in
figure 3. The temperature rise can then be approximated
as :
m
AT(t) A P o K h -
6 P n K a
\
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.7 0.8
0.6
0.9 1.0
tlt,
Figure 4. Theoretical temperature rise (normalized to the
maximum temperature rise) versus time in avalanche breaJcdown (normalized to total avalanche time).
(2)
n=l
where:
AT,
= -P
Po = Io x VBR
3
o K f i .
(7)
A plot of the normalized temperature rise versus the normalized time is shown in figure 4.
It was previously shown experimentally that the critical avalanche current at which failure occurs for power
MOSFETs is temperature dependent [4]. Failure is thought
to occur when the lateral current in the base of the intrinsic bipolar transistor becomes great enough to activate the
bipolar transistor. An expression for the critical current as
a function of the voltage ‘required to turn on the emitterbase diode’ and of the ‘intrinsic base resistance’ is:
and,
Equation 2 can be written:
m
(3)
n=l
If the limit as m approaches infinity of the summation
in equation 3 is taken, the equation may be written:
The intrinsic base resistance increases with temperature
and one would expect that the voltage required to activate
the emitter-base diode to decrease with temperature. Thus
the critical current decreases with increasing temperature.
The temperature rise after a time t is then:
Because VBE is not well defined and Ri is not a lumped
resistance but is distributed in some manner, it is difficult
to write an analytic, temperature-dependent expression for
Icr,t in terms of known quantities. For illustration, though,
if one assumes:
(5)
This last expression for the temperature rise can be normalized and written as:
[g]
2.5
R = R(To)
and
where:
LIO
and thus:
tf = VBR
VBE(T) = E,
is the time at which i = 0 and ATM is the maximum
temperature rise, which always occurs at t =
and is
given by:
2,
and finally that:
684
+ [VBE(TO)- E g ] T-To
25
50
I
I
I
75
100
125
4
150
175
200
TEMPERATURE 1°C)
Figure 5. Theoretical variation of critical current for fdlure
with temperature.
then the variation of Icer;twith T would be as shown in
figure 5 . The experimental data previously reported (figure
11 of reference 4) show Icr;tversus T for several devices.
with T as large
Some of the devices have a variation of
as shown in figure 5 here, and others have a considerably
smaller decrease with temperature. The plot in figure 5
might be considered to be an upper limit of the magnitude
of the decrease in Icr;twith temperature.
EXPERIMENTAL RESULTS
A variety of power MOSFETs from several manufacturers were measured. Some of the devices were rated by
the manufacturer for avalanche energy capability and others were not. All of the devices though demonstrated the
capability to dissipate significant energy during avalanche
breakdown for currents greater than their rated 10. A
test system that has been described previously was used
for the measurements [13]. The devices were switched on
and off with an inductive load at the drain with the drain
voltage unclamped; that is, the devices were allowed to
avalanche freely and all of the energy stored in the inductor was dissipated in the MOSFET during avalanche.
Typically, measurements were initiated by setting the inductance and case temperature to fixed values and applying a small, single pulse of drain current to the device.
The initial current was kept small enough such that the
device would safely avalanche. The current was then increased by a small amount and another single pulse was
applied to the device. This procedure was continued until the device experienced second breakdown during the
avalanche breakdown. An oscillogram of the drain current
and voltage waveforms for a safe turn-off is shown in figure
6a and the waveforms at failure for the same device (for a
slightly larger value of current) are shown in figure 6b. In
the following, the energy discussed is the energy dissipated
during avalanche for the safe turn-off at a starting current
(IO)slightly less than the starting current for which the
device experienced second breakdown. That is, the energy
is the maximum energy the device can safely dissipate during avalanche breakdown with the given inductor and case
Figure 6. a) Drain voltage and drain current waveforms
for a device during "sde" avalanche breakdown. b) Waveforms for the same device but for a slightlylarger current.
Second breakdown has occurred at the point the waveforms
seem to disappear.
temperature. Two currents can be distinguished in the
breakdown event, one being the current at which the device begins to avalanche (lo)and that at which the device
fails ( i ~ ) . As will be discussed later, because the current
is increased only a small amount each time, when failure
occurs, it is almost always true that iF x ; l o .
A schematic of the circuit used to test the devices is
shown in figure 7. This circuit has been discussed in detail previously [13]. It had been found previously that
the circuit can nondestructively test bipolar transistors
under nearly all realistic operating conditions [9,13] and
MOSFETs under conditions for which the devices do not
avalanche [4]. Nondestructive is defined to mean that
no observable changes in the drain-source leakage current
(measured at approximately 95% of VBR)occur after the
device experiences second breakdown. The circuit was not
successful in nondestructively testing all of the devices
studied in this work. Approximately 50% of the devices
tested experienced no degradation after second breakdown
and the other 50% were either degraded or failed totally after one second breakdown event. The reason for the higher
failure/degradation rate is probably that the devices undergo a significant rise in temperature during avalanche
685
Io.lpoo"~ I
CLAMP SUPPLY
(,,, I I
p" ,
- 7.5
- 7.0
SHUNT
PROTECTION
0.1 0.2
GATEDRIVE
0.3
0.4
-
0.5
0.6 0.7 0.8 0.9
INDVCTANCE (mHl
1.0
1.1
1.2
I
I
30 -
Figure 7. Schematic of circuit used to test devices.
breakdown, and although they are not degraded prior to
second breakdown (see next paragraph), the localized temperature, at a small area of the device, rises much higher
after the occurrence of second breakdown. The devices are
apparently degraded at the higher temperature. Perhaps
the devices could be tested without degradationif all of the
current could be removed from the device more rapidly after the onset of second breakdown. The circuit used here
removes the current in less than 30m. If avalanche does
not occur, the starting temperature at the onset of second
breakdown is lower, and the current can be removed from
the device before its temperature becomes high enough to
degrade the device.
Because devices were often degraded after experiencing second breakdown, measurements were made to determine if degradation to the device might have occurred prior
to second breakdown; that is, to see if the temperature rise
during the 'safe' turn-off shown in figure 6a degraded the
device. Degradation was defined as above. It was found
that no degradation occurred (that is, the drain-source
leakage current did not change) unless second breakdown
actually occurred. The devices were found not to degrade
during safe avalanche.
28 -
- 26 --2> 2242 g 20 Y 18 16
:
5
14
-
5 12-
7.0
6.0
8.0
9.0
10.0
AVALANCHE CURRENT ( A )
Figure 8. a) Maximum energy that can be safely dissipated during avalanche breakdown and the maximum current that is being turned off, Io, versus inductance for two
devices. b) A re-plot of the data as energy versus maximum current.
-
1
70
60 -
-I 12
7
E 50 -
&
40 -
w
30 -
The measured energy dissipated during turn-off immediately prior to failure versus the magnitude of the inductance at the drain is plotted in figure 8 for two generic
IRF 510 devices. These are typical results for the devices
measured in that, as the magnitude of the inductance is
decreased, the energy that can be safely dissipated prior
to failure is also decreased. Also plotted in figure 8 is the
maximum current (IO)versus inductor size for the same
devices (the energy dissipated is f L I i ) . Again these are
typical results in that the maximum current increases as
the inductor size decreases. The data from figure 8a are
replotted in figure 8b as maximum current, IO,versus energy. From figure 8b, it can be seen that as Io is increased,
the energy that can be safely dissipated during avalanche
is decreased.
A plot of the energy dissipated immediately prior to
8
5 20 -
2
10 -
20
30
40
50
60
70
80 90
TEMPERATURE ('Cl
100
110
120 130
Figure 9. Maximum energy that can be safely dissipated
during avalanche breakdown and the maximum current
that is being turned off versus case temperature.
failure versus case temperature for a given inductor size is
shown in figure 9 for two other generic IRF 510 devices.
As above, the results are typical in that the energy is observed to decrease as the case temperature increases. The
maximum current versus case temperature for the devices
is also shown. Again, these are typical data.
‘
1
DISCUSSION
Safe turn-off
Failure
The approach of the power MOSFET to failure as
proposed here can be explained with the aid of figure 10
which is a composite of plots similar to those in figures 4
and 5 . In figure 10 are plotted the actual device current,
the temperature, and the critical current for failure versus
time during avalanche breakdown. The curves are plotted
for two slightly different values of starting current, IO.The
value of the critical current decreases as the temperature
increases and then increases as the temperature begins to
decrease during the avalanche breakdown. For the lower
value of Io, the critical current is always greater than the
actual device current and the device will turn off safely.
For the slightlylarger value of starting current, the critical
current equals the actual current near to the time that
i = ;lo. The device will fail at this point. This also
demonstrates why it is usually found that devices fail when
i x fro. It is at this point that the temperature is the
highest and the critical current therefore the smallest. Of
course, if 10 is increased even more, failure would occur for
i > :Io and i approaches lo as lo is increased even further.
-\
TIME
Figure 10. Theoretical plot of the actual current, critical
current for failure, and temperature rise during avalanche
breakdown for two slightly different starting currents, lo.
For the solid line case, the device turns off sdely. For the
dashed line, the device will fail when the critical current
equals the actual device current.
Manufacturers typically rate the avalanche energy capability of their devices for a current equal to the steadystate maximum allowed current, ID. To vary the energy
dissipation during avalanche at a given current, the magnitude of the inductance must be varied. In this work,
though, for a given test, the magnitude of the inductance
was kept constant and the current slowly increased. It has
been found that devices that are rated for avalanche energy capability will usually avalanche safely at currents in
excess of the rated steady-state current. The results shown
in figure 8 indicate that if the current being turned off (IO)
is in excess of the rated steady-state current, the avalanche
energy capability must be de-rated below that allowed at
ID. If the current is less than ID, more energy can be
dissipated.
The above can be explained from the analysis of the
temperature rise during avalanche breakdown and figure
11. Figure 11 shows the current and temperature rise for
two different inductance values, L and fL.It is assumed
that the device fails for inductance L at a starting current
Io(L) (and therefore fails at i
fIo(L)). If the inductance is decreased to ;L, then the device will not fail for
starting current & ( L )because the temperature will always
be less at each current than for inductance L. Thus, the
device will not fail until the starting current is increased
to a current greater than Io(L).In figure 11, the starting
current is increased to IO(f L). The energy dissipated for
the smaller inductance and higher current though is less
than for inductance L. From equation 7, it can easily be
shown that:
ATM a
(8)
TIME
Figure 11. Theoretical plot of current and temperature
for two different inductances. For inductance L and starting current Io(L), (solid lines) the device fails at current
fIo(L). For inductance equal to $, the device does not
fail for starting current equal to IO (dashed lines). The
starting current must be increased to Io( $) (dotted lines)
for failure to occur for inductance
t.
creased, PO is larger for the smaller inductance. Thus from
equation 8, the energy dissipated safely during avalanche
breakdown must be less for the smaller inductance compared to that for the larger inductance. The avalanche
breakdown energy dissipation capability of a device is not
a constant but depends upon the magnitude of the current
that is being turned off.
Both the critical current and the energy that can be
dissipated safely during avalanche decrease as the case temperature increases, as shown in figure 9. Some manufacturers’ data sheets have curves of the avalanche energy rating
versus case temperature. An example of such a curve is
versus T. The linear
shown in figure 12 plotted as
relationship between
and T suggests that the curves
Because the device fails at a higher current for the smaller
inductance, the temperature rise at failure(ATM) must be
less for the smaller inductance (critical current decreases
with temperature). Because the maximum current is in-
a
687
REFERENCES
1. M. Glogolja, “Ruggedness Test Claims Demand Another Careful Look,” Powertechnics Magazine, pp 2328, July 1986.
2. P. J . Carlson, “The Unclamped Inductive Switching
Test - A Closer Look at Power MOSFET Ruggedness,” PowertechnicsMagazine, pp 32-33, August 1986.
3. K. Gauen, “Specifying Power MOSFET Avalanche
Stress Capability,’’ Powertechnics Magazine, pp 3438, January, 1987.
CASE TEMPERATURE P C )
Figure 12. Plot of square root of manufacturers’ rated
avalanche breakdown energy dissipation capability versus
case temperature. The linear relationship suggests that
the device is rated to fail or to be limited by a constant
chip temperature - 150 deg C in this case.
4. D. L. Blackburn, “Turn-off Failure of Power MOSFETs”, PESC ’85 Record, Proc. 1985 IEEE Power
Electronics Specialists Conference, pp 429-435, June
1985. (Also reprinted in IEEE Trans. Power Electronics, vol. PE-2, No. 2, pp 136-142, April, 1987.)
for the data sheet are drawn for conditions where the chip
reaches a constant temperature independent of the case
temperature. This can be seen by applying equation (8)
where Po is constant (because the manufacturers’ ratings
are for the constant steady-state current rating). Similar
results would be obtained for the device failing at either
a constant temperature or at a critical current which depends upon temperature. This is because the manufacturers’ curves are generated for a constant starting current,
(Ib= Io),and thus failure would also occur at a constant
current ( i N~310)and a constant temperature (TM),
independent of case temperature.
5. JEDEC Suggested Standard No. 10, Low Frequency
Power Transistors, January 1976. (Available from the
Electronic Industries Association, 2001 Eye Street,
N.W., Washington, DC 20006.)
6. P. L. Hower and V. G. K. Reddi, “Avalanche Injection
and Second Breakdown in Transistors,” IEEE Trans.
Electron Devices, ED-17,pp 320-335, April 1970.
7. S. Krishna and P. L. Hower, “Second Breakdown of
Transistors During Inductive Turn-off,” Proc. IEEE
61, pp 393-394, March 1973.
CONCLUSIONS
Many state-of-the-art power MOSFETs can have substantial capability to dissipate energy during avalanche
breakdown. Although ratings are presently based only
upon avalanche at the steady-state current rating, 10,the
energy that power MOSFETs can dissipate during avalanche
breakdown depends upon the starting current. The energy
dissipation capability decreases as the current increases.
The energy that can be safely dissipated during avalanche
also decreases with increasing case temperature. According to the theory presented, power MOSFETs fail at a
critical current that decreases as the chip temperature increases. If power MOSFETs are to be rated for their
avalanche breakdown energy capability, the rating must
include the starting current and the case temperature conditions, as it is these two parameters that actually determine the failure limits and not the energy. A more realistic
avalanche rating approach would be to eliminate energy as
a variable and replace it with limits on the starting current, case temperature, and drain inductance, all variables
over which the circuit designer has some control.
ACKNOWLEDGMENTS
The author thanks Dr. A. R. Hefner, Jr., for his contributions to this manuscript and Ms. J. Walters for her
assistance in preparing the manuscript for publication.
688
8. B. A. Beatty, S. Krishna, and M. A. Adler, “Second
Breakdown in Power Transistors Due to Avalanche
Injection,” IEEE Trans. Electron Devices ED-23, pp
851-857, August 1976.
9. D. L. Blackburn and D. W. Berning, “An Experimental Study of Reverse-Bias Second Breakdown,” 1980
IEDM Tech. Digest, 1980 IEEE Int. Electron Devices
Meeting, pp 297-301, December 1980.
10. B. J. Baliga, Modern Power Devices, John Wiley and
Sons, New York, 1987, p 295.
11. D. L. Blackburn and F. F. Oettinger, “Transient Thermal Response Measurements of Power Transistors,”
IEEE Trans. Ind. Electron. Contr. Instrum., IECI22, pp 134-141, May 1975.
12. F. W. Gutzwiller and T. P. Sylvan, “Power Semiconductor Ratings Under Transient and Intermittent
Loads,” AIEE Transactions, Part I, Communications
and Electronics, pp 699-706, January 1961.
13. D. W. Berning, “Semiconductor Measurement Technology: A Reverse-Bias Transistor Safe Operating Area
Tester,’’ NBS Special Publication 400-54, April 1979.