ARM Instructions
logic
access
ing
arison
Memory
Branch-
Comp-
Bitwise
Arithmetic
ADDcd S† reg , reg , arg
SUBcd S
reg , reg , arg
RSBcd S
reg , reg , arg
ADCcd S
reg , reg , arg
SBCcd S
reg , reg , arg
RSCcd S
reg , reg , arg
MULcd S
reg d , reg m , regs
MLAcd S
regd , regm , regs , regn
UMULLcd S reglo , reghi , regm , regs
UMLALcd S reglo , reghi , regm , regs
SMULLcd S reglo , reghi , regm , regs
SMLALcd S reglo , reghi , regm , regs
ANDcd S
reg , reg , arg
ORRcd S
reg , reg , arg
EORcd S
reg , reg , arg
BICcd S
reg , rega , arg b
CMPcd
reg , arg
CMNcd
reg , arg
TSTcd
reg , arg
TEQcd
reg , arg
MOVcd S
reg , arg
Data movement
MVNcd S
reg , arg
LDRcd B‡ reg , mem
STRcd B
reg , mem
LDMcdum reg !, mreg
STMcdum reg !, mreg
SWPcd B
regd , regm , [regn ]
Bcd
imm 24
BLcd
imm 24
BXcd
reg
SWIcd
imm 24
add
subtract
subtract reversed operands
add both operands and carry ag
subtract both operands and adds carry ag − 1
reverse subtract both operands and adds carry ag − 1
multiply regm and regs , places lower 32 bits into regd
places lower 32 bits of regm · regs + regn into regd
multiply regm and regs place 64-bit unsigned result into {reghi , reglo }
place unsigned regm · regs + {reghi , reglo } into {reghi , reglo }
multiply regm and regs , place 64-bit signed result into {reghi , reglo }
place signed regm · regs + {reghi , reglo } into {reghi , reglo }
bitwise AND
bitwise OR
bitwise exclusive-OR
bitwise rega AND (NOT arg b )
update ags based on subtraction
update ags based on addition
update ags based on bitwise AND
update ags based on bitwise exclusive-OR
copy argument
copy bitwise NOT of argument
loads word/ byte/ half from memory into a register
stores word/ byte/ half to memory from a register
loads into multiple registers
stores multiple registers
copies regm to memory at regn , old value at address regn to regd
branch to imm 24 words away
copy PC to LR, then branch
copy reg to PC, and exchange instruction sets (T ag := reg [0])
software interrupt
† S = set condition ags
‡ B = byte, can be replaced by H for half word(2 bytes)
um: update mode
cd: condition code
AL or omitted
EQ
NE
CS
CC
MI
PL
VS
VC
HS
LO
HI
LS
GE
LT
GT
LE
always
equal
not equal
carry set (same as HS)
carry clear (same as LO)
minus
positive or zero
overow
no overow
unsigned higher or same
unsigned lower
unsigned higher
unsigned lower or same
signed greater than or equal
signed less than
signed greater than
signed less than or equal
(ignored)
Z = 1
Z = 0
C = 1
FA / IA
EA / IB
FD / DB
ED / DA
ascending, starting from reg
ascending, starting from reg + 4
descending, starting from reg
descending, starting from reg − 4
R0 to R15
SP
LR
PC
register according to number
register 13
register 14
register 15
C = 0
N = 1
reg: register
N = 0
V = 1
V = 0
C = 1
C = 0
C = 1
C = 0
∧Z=0
∨Z=1
arg: right-hand argument
N = V
6= V
Z = 0 ∧ N = V
Z = 1 ∨ N 6= V
N
#imm 8
reg
reg , shift
shift: shift register value
LSL #imm 5
LSR #imm 5
ASR #imm 5
ROR #imm 5
RRX
LSL reg
LSR reg
ASR reg
ROR reg
shift left 0 to 31
logical shift right 1 to 32
arithmetic shift right 1 to 32
rotate right 1 to 31
rotate carry bit into top bit
shift left by register
logical shift right by register
arithmetic shift right by register
rotate right by register
immediate on 8 bits, possibly rotated right
register
register shifted by distance
mem: memory address
[reg ,#±imm 12 ]
[reg ,±reg ]
[rega ,±regb ,shift ]
[reg ,#±imm 12 ]!
[reg ,±reg ]!
[reg ,±reg ,shift ]!
[reg ],#±imm 12
[reg ],±reg
[reg ],±reg ,shift
reg oset by constant
reg oset by variable bytes
rega oset by shifted variable regb †
update reg by constant, then access memory
update reg by variable bytes, then access memory
update reg by shifted variable, then access memory †
access address reg , then update reg by oset
access address reg , then update reg by variable
access address reg , then update reg by shifted variable †
† shift distance must be by constant
