UNIVERSITY OF KWAZULU-NATAL
School of Engineering: Electrical, Electronic & Computer Engineering
MAIN EXAMINATIONS: June 2013
Course and Code:
Analogue Electronics 1: ENEL3TA H1
Duration: TWO hours
Paper 1 of 1
Maximum marks: 100
Examiner:
Mr H Jay
Independent Moderator: Prof TJO Afullo
Instructions:
Answer ALL questions.
NO NOTES of any form are allowed into the examination.
Any calculator may be used, provided that no text or formulae are present in memory
during the examination.
Show all working in calculations and derivations.
Fully label all diagrams and graphs.
Supplied information is given on page 5.
UNIVERSITY OF KWAZULU-NATAL
Course and Code:
MAIN EXAMINATIONS: June 2013
Analogue Electronics 1: ENEL3TA H1
Page 2 of 5
Question 1 [25 marks]
1.1
The differential amplifier circuit shown in Figure 1 uses matched BJTs with VBE = 0,7 V (except Q3)
and VT = 25 mV.
+5 V
RE
Q3
Q4
Ro
(Q3)
IT
IE1
IE2
IREF
Q2
Q1
vS1
vS2
vO
RC1
22 kΩ
RREF
9,3 kΩ
RC2
22 kΩ
-5 V
Figure 1
1.1.1 Identify the current mirror circuit used to bias this amplifier and state two advantageous features
it has. With v S1 = v S2 = 0 V the measured dc output voltage v o = −2,8 V . Determine the
resistance RE required to achieve this neglecting base currents and the Early voltage effect. (5)
1.1.2 Sketch the small-signal equivalent half-circuit for differential signals. Determine the differential
input resistance (Rid) as seen between the bases of Q1 and Q2 and the overall differential voltage
gain A vd ≡ v o ( v S1 − v S2 ) assuming β = 100 and neglecting the Early voltage effect.
(4)
1.1.3 Sketch the small-signal equivalent half-circuit for common-mode signals. Determine the output
resistance Ro of the current mirror and hence calculate the common-mode voltage gain and
hence the common-mode rejection ratio (CMRR) in dB assuming VA = 100 V for Q3. Neglect
the Early voltage effect for the other transistors.
(8)
1.2
A CMOS logic inverter is fabricated with the following parameters:
W
Supply voltage VDD = +3 V
Vtn = 0,7 V   = 1,5 k ′n = 120 µA / V 2 k ′p = 60 µA / V 2 .
 L n
1.2.1 Determine the suitable values for Vtp and  W  to give a symmetrical switching point
 L p
1.2.2 Calculate the noise margins.
1.2.3 Determine the maximum current that the inverter can sink while VO = 0,1 V.
1.2.4 Determine the output resistance of the inverter when VO ≈ 0 V.
(8)
Question 2 [25 marks]
The circuit diagram of a simple operational amplifier using current repeater dc biasing is shown in Figure 2
below. The transistors are all matched except transistors Q10 and Q14 where Q10 has twice the area and Q14
has five times the area of the other transistors. Assume VBE = 0,7 V and VT = 25 mV.
UNIVERSITY OF KWAZULU-NATAL
Course and Code:
MAIN EXAMINATIONS: June 2013
Analogue Electronics 1: ENEL3TA H1
+9 V
Q14
Q10
Q9
R1
12 kΩ
Page 3 of 5
2X
IC10
R2
12k Ω
IE3
5X
IC14
IE4
Q4
Q3
VO
IE5
V1
Q1
Q2
IE1
IE2
V2
IREF
RL
1 kΩ
Q5
RREF
+9 V
IC6
Q6
Q7
Q12
Q8
Q11
Q13
-9 V
Figure 2
2.1
Identify the sub-circuit comprising Q6, Q7, Q8, and identify and correct the error in this sub-circuit.
Briefly explain how this sub-circuit improves the performance of the first amplifier stage.
(3)
2.2
Identify the configuration of the second amplifier stage and briefly explain the main purpose of that
stage and the reason that particular configuration is used.
(3)
2.3
Determine RREF so that IREF = 1 mA, determine collector currents IC6, IC10 and IC14 and emitter currents
IE1, IE2, IE3, IE4 and IE5. Assume that external negative feedback keeps VO = 0 V when the inputs are
grounded. Assume that base currents and the Early voltage effect can be neglected for all BJTs.
(6)
2.4
A differential input signal is applied to this amplifier. Determine the differential input resistance Rid
and the small-signal differential voltage gain A Vd = Vo (VS1 − VS2 ) in dB assuming a load resistance
RL = 1 kΩ is connected to the output. Draw a small-signal equivalent circuit for each stage, use the dc
bias conditions calculated in 2.3, assume β = 100 for all transistors and neglect the Early voltage
effect.
(13)
Question 3 [25 marks]
3.1
An n-channel enhancement MOSFET with k ′n W L = 1mA / V 2 ; Vt = 1 V; and λ = 0 is used in the
RC-coupled amplifier circuit in Figure 3 below. Analyse the dc bias circuit to determine ID, VG, VGS,
VD & VDS.
(7)
3.2
Identify this amplifier configuration, draw the relevant small-signal equivalent circuit diagram at
“mid-band” frequencies, derive an expression for the signal voltage gain A v ≡ v o v in and hence
(7)
calculate the overall signal voltage gain A vs ≡ v o v sig assuming R sig = R L = 10 kΩ
UNIVERSITY OF KWAZULU-NATAL
Course and Code:
MAIN EXAMINATIONS: June 2013
Analogue Electronics 1: ENEL3TA H1
Page 4 of 5
+ 10V
RD
2,2 kΩ
RG1
1 MΩ
Rsig
vsig
vin C1
C2
Q1
RG2
1 MΩ
vo
RL
C3
RS
1 kΩ
0V
Figure 3
3.3
One stage of a CMOS multistage amplifier circuit is shown in Figure 4. Ignoring the Early voltage
effect, determine RREF required to give the design value of I REF = 100 µA with VDD = + 3 V assuming
Vo is such that Q1 and Q2 operate in saturation. The MOSFET data is as follows:
For Q2 & Q3 (matched): k ′p W / L = 650 µA / V 2 ; Vt = −0,6 V ;
k ′n W / L = 2 mA / V ;
2
For Q1:
Vt = 0,6 V ;
VA = 10 V
VA = 20 V
(6)
+VDD
Q2
Q3
vo
IREF
vin
Q1
RREF
0V
Figure 4
3.4
Identify the amplifier configuration, draw the small-signal equivalent circuit, and determine the
small-signal voltage gain A v = v o / v in assuming any external load resistance is very large.
(5)
Question 4 [25 marks]
4.1
A unity gain Butterworth high-pass filter to be designed. The specification of the equivalent low-pass
filter requires a maximum attenuation of 1 dB at 1 kHz and a minimum attenuation of 45 dB at 5 kHz.
Determine the order of the filter required, draw the pole-zero diagram and hence determine the transfer
function of the low-pass filter expressed as a combination of 2nd and/or 1st order terms.
(13)
4.2
Using suitable transformations, convert this low-pass transfer function to that of the equivalent
high-pass filter. This filter is to be realized with an appropriate combination of 2nd order Sallen Key
and/or 1st order high-pass sections. Draw a block diagram showing the relevant filter blocks required
and their cut-off frequencies and Q values.
(5)
4.3
Calculate all the component values for the 2nd order high-pass filter section with the highest Q value.(7)
UNIVERSITY OF KWAZULU-NATAL
Course and Code:
MAIN EXAMINATIONS: June 2013
Analogue Electronics 1: ENEL3TA H1
Page 5 of 5
Supplied Information:
Mirror equations:
Widlar Current Mirror :
I
I o R E = VT ln ref
Io
Wilson Current Mirror :
Ro ≈
R o = (1 + g m R ′E ) ⋅ ro
R ′E = R E // rπ
β
⋅ ro
2
CMOS inverter equations:
1
(5VDD − 2Vt ) VIL = 1 (3VDD + 2Vt )
8
8
V
1
rDS = DS =
W
ID
 
k ′ ⋅   ⋅ (VDD − Vt )
L
VIH =
NM L = NM H =
1
(3VDD + 2Vt )
8
MOSFET equations:
k ′ = k ′n = µ n C ox or k ′p = µ p C ox
MOSFETS
λ=
g m = 2k ′ ( W / L)I D = k ′ ( W / L)(VGS − Vt ) =
Triode region
NMOS : VDS < VGS − Vt
1
VA
ro =
VA
ID
2I D
VGS − Vt
1
 W 

i D = k ′   (VGS − Vt )VDS − VDS 2 
2
 L 

PMOS : VDS > VGS − Vt
Sat. region
NMOS : VDS > VGS − Vt
iD =
1 W
k ′  (VGS − Vt ) 2 (1 + λVDS )
2 L
PMOS : VDS < VGS − Vt
Butterworth low-pass equations:
A max
ε = 10 10 − 1
1
1 N
ωo = ω P  
ε
2N 

2  ω 


A(ω) = 10 ⋅ log 1 + ε 
ω P  




Transformations : LPF(ωA ) ⇒ LPF(ωB ) : s ⇒
ωA ⋅ s
ωB
T (s ) =
K ⋅ ωo N
(s − p1 )(s − p 2 ) ⋅ ⋅ ⋅ (s − p N )
LPF(ωA ) ⇒ HPF(ωA ) : s ⇒
Sallen Key high-pass 2nd order circuit and equations.
T(s) =
ωo =
1
=
Q
K s2
ω
s 2 + s o + ωo 2
Q
1
ωA 2
s
R1
C1
C2
+
R2
-
R 1R 2 C1C 2
R 1C1
R 1C 2
R 2C2
+
+ (1 − K )
R 2C2
R 2 C1
R 1C1
RB
RA