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Phase-Locked Loops
IEEE Press Editorial Board
Sarah Spurgeon, Editor in Chief
Jón Atli Benediktsson
Anjan Bose
James Duncan
Amin Moeness
Desineni Subbaram Naidu
Behzad Razavi
Jim Lyke
Hai Li
Brian Johnson
Jeffrey Reed
Diomidis Spinellis
Adam Drobot
Tom Robertazzi
Ahmet Murat Tekalp
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IEEE Press
445 Hoes Lane
Piscataway, NJ 08854
System Perspectives and Circuit Design Aspects
Woogeun Rhee and Zhiping Yu
Tsinghua University
Beijing, China
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Phase-Locked Loops
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Library of Congress Cataloging-in-Publication Data Applied for:
Hardback: 9781119909040
Cover Design: Wiley
Cover Image: © Tuomas A. Lehtinen/Getty Images
Set in 9.5/12.5pt STIXTwoText by Straive, Chennai, India
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Copyright © 2024 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved.
To my academic advisers Prof. Zhijian Li of Tsinghua University, and
Prof. Robert W. Dutton of Stanford University
Zhiping Yu
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To my parents and my wife, Soojung, and
To my acacemic adviser Prof. Bang-Sup Song
Woogeun Rhee
Contents
Preface xiii
About Authors
1
1.1
1.2
1.3
Introduction 1
Phase-Lock Technique 1
Key Properties and Applications 2
1.2.1 Frequency Synthesis 3
1.2.2 Clock-and-Data Recovery 3
1.2.3 Synchronization 4
1.2.4 Modulation and Demodulation 5
1.2.5 Carrier Recovery 6
1.2.6 Frequency Translation 6
Organization and Scope of the Book 6
Bibliography 7
Part I
2
2.1
2.2
2.3
xv
Phase-Lock Basics 9
Linear Model and Loop Dynamics 11
Linear Model of the PLL 11
Feedback System 13
2.2.1 Basics of Feedback Loop 13
2.2.2 Stability 15
Loop Dynamics of the PLL 16
2.3.1 First-Order Type 1 PLL 16
2.3.2 Second-Order Type 1 PLL 17
2.3.3 Second-Order Type 2 PLL 19
2.3.4 Natural Frequency and Damping Ratio
21
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vii
Contents
2.4
2.5
2.6
3
3.1
3.2
3.3
2.3.5 High-Order PLLs 23
2.3.6 Bandwidth of PLL 23
2.3.7 Loop Gain and Natural Frequency 24
2.3.8 3-dB Bandwidth 25
2.3.9 Noise Bandwidth 25
Noise Transfer Function 26
Charge-Pump PLL 29
2.5.1 High-Order CP-PLL 32
2.5.2 Control of Loop Parameters 34
2.5.3 Another Role of Shunt Capacitor 34
Other Design Considerations 39
2.6.1 Time-Continuous Approximation 39
2.6.2 Practical Design Aspects 39
References 41
Transient Response 43
Linear Transient Performance 44
3.1.1 Steady-State Phase Response 44
3.1.2 Transient Phase Response 46
3.1.3 Settling Time 48
Nonlinear Transient Performance 52
3.2.1 Hold-In Range 53
3.2.2 Pull-In Range 53
3.2.3 Lock-In Range 55
3.2.4 Nonlinear Phase Acquisition 55
Practical Design Aspects 56
3.3.1 Type 1 and Type 2 PLLs with Frequency-Step Input 57
3.3.2 State-Variable Model 58
3.3.3 Two-Path Control in the CP-PLL 59
3.3.4 Two-Path Control in DPLL 61
3.3.5 Slew Rate of CP-PLL 62
3.3.6 Effect of the PFD Turn-On Time 64
References 65
Part II
4
4.1
System Perspectives 67
Frequency and Spectral Purity 69
Spur Generation and Modulation 69
4.1.1 Spurious Signal (Spur) 69
4.1.2 Reference Spur 77
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viii
4.2
Phase Noise and Random Jitter 87
4.2.1 Phase Noise Generation and Measurement 87
4.2.2 Integrated Phase Noise 93
4.2.3 Optimum Loop Bandwidth for Phase Noise 96
References 100
5
5.1
Application Aspects 101
Frequency Synthesis 102
5.1.1 Direct Frequency Synthesis 102
5.1.2 Indirect Frequency Synthesis by Phase Lock 103
5.1.3 Frequency Synthesizer Architectures for Fine Resolution 106
5.1.4 System Design Aspects for Frequency Synthesis 108
Clock-and-Data Recovery 112
5.2.1 Wireline Transceiver with Serial Link 112
5.2.2 Clock Recovery and Data Retiming by PLL 114
Clock Generation 120
5.3.1 System Design Aspects 120
5.3.2 Clock Jitter for Wireline Systems 123
Synchronization 127
5.4.1 PLL for Clock De-skewing 127
5.4.2 Delay-Locked Loop 128
References 132
5.2
5.3
5.4
Part III Building Circuits 135
6
6.1
6.2
6.3
Phase Detector 137
Non-Memory Phase Detectors 137
6.1.1 Multiplier PD 137
6.1.2 Exclusive-OR PD 139
6.1.3 Flip-Flop PD 139
6.1.4 Sample-and-Hold PD 140
6.1.5 Sub-Sampling PD 141
Phase-Frequency Detector 142
6.2.1 Operation Principle 143
6.2.2 Dead-Zone Problem 145
6.2.3 Effect of the PFD Turn-On Time on PLL Settling 147
6.2.4 Noise Performance of PFD 147
Charge Pump 149
6.3.1 Circuit Design Considerations 149
6.3.2 Single-Ended Charge Pump Circuits 154
ix
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Contents
Contents
6.3.3 Semi- and Fully Differential Charge Pump Circuits 157
6.3.4 Design of Differential Loop Filter 160
References 164
7
7.1
7.2
7.3
7.4
8
8.1
8.2
8.3
Voltage-Controlled Oscillator 165
Oscillator Basics 166
7.1.1 Oscillation Condition 166
7.1.2 Quality Factor 167
7.1.3 Frequency Stability 170
7.1.4 Effect of Circuit Noise 171
7.1.5 Leeson’s Model and Figure-of-Merit 173
7.1.6 Effect of Noise Coupling 174
LC VCO 175
7.2.1 Design Considerations 175
7.2.2 LC VCO Circuit Topologies 184
RING VCO 190
7.3.1 Design Aspects 191
7.3.2 Phase Noise 192
7.3.3 Circuit Implementation 196
Relaxation VCO 201
7.4.1 Relaxation Oscillator with Ground Capacitor 201
7.4.2 Relaxation Oscillator with Floating Capacitor 202
References 205
Frequency Divider 209
Basic Operation 209
8.1.1 Frequency Division with Prescaler 209
8.1.2 Standard Configuration of Prescaler-based Frequency
Divider 212
8.1.3 Operation Principle of Dual-Modulus Divider 215
Circuit Design Considerations 219
8.2.1 Frequency Divider with Standard Logic Circuits 219
8.2.2 Frequency Divider with Current-Mode Logic
Circuits 220
8.2.3 Critical Path of Modulus Control 226
Other Topologies 229
8.3.1 Phase-Selection Divider 229
8.3.2 Phase-Interpolated Fractional-N Divider 230
8.3.3 (2k + M) Multi-Modulus Divider 231
8.3.4 Regenerative Divider 232
References 234
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x
Part IV PLL Architectures
9
9.1
9.2
9.3
9.4
237
Fractional-N PLL 239
Fractional-N Frequency Synthesis 239
9.1.1 Basic Operation 239
9.1.2 Spur Reduction Methods 243
9.1.3 Multi-Loop Hybrid Frequency Synthesis 248
Frequency Synthesis with Delta-Sigma Modulation 249
9.2.1 ΔΣ Modulation 250
9.2.2 All-Digital ΔΣ Modulators for Fractional-N Frequency
Synthesis 255
9.2.3 Phase Noise by Quantization Error 261
9.2.4 Dynamic Range and Bandwidth 265
9.2.5 Nonideal Effects 267
9.2.6 Practical Design Aspects for the ΔΣ Fractional-N PLL 270
Quantization Noise Reduction Methods 271
9.3.1 Phase Compensation 272
9.3.2 Noise Filtering 273
Frequency Modulation by Fractional-N PLL 278
9.4.1 One-Point Modulation 278
9.4.2 Two-Point Modulation 279
References 281
10 Digital-Intensive PLL 287
10.1 DPLL with Linear TDC 288
10.1.1 Loop Dynamics 289
10.1.2 TDC 295
10.1.3 DCO 299
10.2 DPLL with 1-Bit TDC 304
10.2.1 Loop Behavior of BB-DPLL 304
10.2.2 Fractional-N BB-DPLL 308
10.2.3 Different Design Aspects of BB-DPLL
10.3 Hybrid PLL 315
10.3.1 Hybrid Loop Control 316
10.3.2 Design Aspects of the HPLL 318
References 320
11 Clock-and-Data Recovery PLL 325
11.1 Loop Dynamics Considerations for CDR 325
11.1.1 JGEN and Noise Sources 325
11.1.2 JTRAN and Jitter Peaking 326
11.1.3 JTOR and Jitter Tracking 327
310
xi
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Contents
Contents
11.2 CDR PLL Architectures Based on Phase Detection 329
11.2.1 CDR with Linear Phase Detection 329
11.2.2 CDR with Binary Phase Detection 333
11.2.3 CDR with Baud-Rate Phase Detection 338
11.3 Frequency Acquisition 340
11.3.1 Frequency Detector 341
11.3.2 CDR PLL with Frequency Acquisition Aid Circuits 343
11.4 DLL-assisted CDR Architectures 344
11.4.1 Delay- and Phase-Locked Loop (D/PLL) 345
11.4.2 Phase- and Delay-Locked Loop (P/DLL) 348
11.4.3 Digital DLL with Phase Rotation 349
11.5 Open-Loop CDR Architectures 351
11.5.1 Blind Oversampling CDR 352
11.5.2 Burst-Mode CDR 353
References 355
Index 359
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xii
Preface
Over 15 years of giving a phase-locked loop (PLL) course to graduate students,
the authors felt a strong need for one textbook that covers PLL basics, system perspectives, practical design aspects for integrated circuits, and PLL architecture for
both wireless and wireline communication systems. Without such a book, the PLL
lecture had to be given based on several textbooks. Even though there are many
PLL books available for circuit designers, most of them can be classified into three
types. The first one is a theory-oriented book that describes the PLL based on control and communication theories but lacks circuit details. The second type of book
deals with more circuits but is mostly based on discrete circuits, not covering practical design issues over on-chip variability or modern PLL architectures such as
fractional-N PLLs. The last one is a circuit-oriented book but does not describe a
PLL from system basics to circuit design aspects for diverse applications with an
integrated step-by-step format.
This book combines bottom-to-top and top-to-bottom approaches to address
the system and circuit design aspects of the PLL, covering essential materials for
circuit designers, from fundamentals to practical design aspects. Compared with
circuit-oriented PLL books, this book has substantial material on system design
considerations in addition to circuit design aspects for wireless and wireline
applications. Unlike other PLL books from the area of communication systems,
this book mainly focuses on the linear behaviors of the PLL and describes them in
an intuitive way without deriving mathematical analyses and equations in detail,
while touching system analyses tailored for circuit designers. Below are some
examples.
● Is the critical damping ratio of loop dynamics ever used for on-chip PLL design?
● Is the natural frequency 𝜔 from control theory as meaningful as the loop gain
n
to circuit designers?
● Is the type 2 PLL with other phase detectors as well as the phase-frequency detector (PFD) able to provide the infinite range of frequency acquisition if not limited
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xiii
Preface
by circuits? Does the PFD behave like other phase detectors after frequency
acquisition?
● Do we implement the second-order type 2 charge-pump PLL in practice? Why
should we consider third-order or fourth-order type 2 charge-pump PLLs in
most cases?
● How to consider a peak-to-peak jitter budget from random jitter if the random
jitter is unbounded in theory?
● How to analyze clock jitter in the frequency domain? How to relate phase noise
and sidebands to the time-domain jitter?
● Do we care about frequency-domain sidebands for clock generation if their level
is lower than the carrier power by 40 dB?
● Is the digital-intensive phase-locked loop (DPLL) totally a new PLL architecture
that requires z-domain analysis?
The first half of the book covers system basics, while the second half deals with
hardware implementation. In the first half, PLL basics and system design considerations are discussed. In addition to the linear and transient behaviors of the PLL,
analyzing clock jitter in the frequency domain is deeply explained. In addition,
the book addresses system design trade-offs for three key applications: frequency
synthesis, clock-and-data recovery, and clock generation/synchronization. In the
second half, building circuits and PLL architectures for the three applications
are discussed by considering system and circuit design aspects. Also, frequency
generation and modulation circuits based on analog, digital-intensive, and hybrid
PLL architectures are described. Learning system architectures and circuit design
trade-offs in wireless and wireline systems, readers will gain the knowledge of
where and how to design the PLL for a broad range of applications.
The authors would like to thank Su Han, Xuansheng Ji, Luhua Lin, Longhao
Kuang, Qianxian Liao, and Liqun Feng in the School of Integrated Circuits at
Tsinghua University for a lot of help drawing figures. Special thanks to Liqun Feng
who not only reviewed technical details with valuable comments but also provided
many simulation plots.
Beijing, China
Woogeun Rhee
Zhiping Yu
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xiv
About Authors
Woogeun Rhee, Ph.D., is a Professor at the School of Integrated Circuits,
Tsinghua University, Beijing. He has over 25 years of professional career in integrated circuit design with nearly 10 years in industry and 17 years in academia.
Dr. Rhee has worked on PLL architectures and circuits not only with different
careers (academia and industry) but also over different fields (wireless and
wireline systems). He is an IEEE Fellow.
Zhiping Yu, Ph.D., is a Professor at the School of Integrated Circuits, Tsinghua
University, Beijing. He is an IEEE Life Fellow with over 400 published papers on
subjects related to ICCAD, nanoelectronics, and RF circuit design.
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xv