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Catalog
~3R-: ~ic.*~~±t&~~~
I
Chapter 3 the architecture of the laptop motherboard
3.1 Intel xxttf (GMlPM45,& ~ ~) B~~ftj
3.1
3.2
3.2
3.3
·
·
·
·
·
·.. · 1
The architecture ofIntel double bridges(GM/PM45 and below)
Intel.l1f (HM55 ~...t) 8~ ~ftj
1
The architecture oflntel single bridge(above HM55)
AMD xxl1f (RS780) ~~ftj
· ·
5
3.3 The architecture ofAMD double bridges(RS780)
·· .. ·· .. ·.. ·
3.4 AMD.ttf (A70) ~~ftj .. ·· .. ·
3.4
3.5
··
·
··
·.. ·5
··
The architecture ofAMD single bridge(A70)
nVIDIA XX;j;jj: (C51M) ~~ftj
5
3.5 The architecture ofnVIDIA double bridges (C51M)
3.6 nVIOlA.;j;jj: (MCP67) ~~ftj
5
3.6
~4~
The architecture ofnVIOlA single bridge (MCP67)
·.. 10
~ic.*~Mit.*F'HIl~&~~1I¥~"·
Chapter 4 The explanation ofnouns and common concepts of laptop maintenance
4.1 ~Jt!.~ffi%
4.1
4.2
·
10
Power supply and signal
.
iWiJt!..if~1~Jt!.,.if
4.2 High level and low level
4.3
~5f~)JI{~..
.
4.3
4.4
4.4
4:5
~
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4.b
4.7
Power good si!-!,nal
'}'tl'
ll
J! . II lit '';
4.7
4.8
J\".i2\;(.·j\@
4.8
4•9
4.9
•· ..
.
·15
pen ignul
··
Chip selection signal
_~J7 L\.}- ,.". In J ~ J':I h T.hl~71;fS/..
tW T.J
'3l. t'l~ JW l,::j '5' -(..J l1J'III'ld n
.
16
, •.••••• , •• ,
17
The explanation of the signal name for some manufacturers
4.9.1
rtQ~
······ .. 17
4.9.1 Wistron
4.9.2
ii1s:
4.9.2
4.9.3
Quanta
·.. ··
···· .. ·.. ··· .. ·· .. ···· .. ·.. ········· .. ···· 18
f~®!
20
4.9.3 Asus
23
4.9.4f=:li
4.9.4
Compal
4.9.5
DELL
4.9.5
DELL
4.9.6
'f.:!iIl:
4.9.6
4.9.7
···· .. ······ .. ···24
27
Apple
9:f~i1s:
4.9.7
Inventec
4.9.8
ThinkPad (ffiM)
4.9.8
ThinkPad (IBM)
·.. ·.. ····· .. ···28
· .. 29
.
~T~fHt-J~illlJ§lm~
.
5.1
rg~l'lg~iifljmffl ~~
5.1
5.2
The basic application circuit of capacitance
5.2
5.3
The basic application circuit ofthe resistance
5.3
5.4
The basic application circuit ofthe diode
5.4
5.5
The basic application circuit ofthe audio
.
~~.Ilsg~ilflmffl ~~
.
=~&~sg~iIflJ§lffl ~~
.
-=J1Hfsg~iIflJ§lffl~S&
%J~mifsg~iIflJ§lffllti&
.
5.5
5.6
5.6
5.7
5.7
.' ~
,
-~~~
. ~ "t:'1:' '.
y.<. •
.- .. - ~
\
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m
It!.~
.. ,
·48
ffl Jt!itl-
···49
tion circuit of the voltage regulator
······················51
~i!m
circuit diagram and the point bitmap
.................................................................................... ·51
• uit diagram
...................................................... ··························56
mon point bitmap
...................................................... ······························66
ODofEC and BIOS
68
J,;/J~
and functions of EC
fl:itilj:
72
conditions of BIOS
• ·· .. ·.. ····· .. ··
···
·.. · .. ··
ess of notebook computer
·• .. ·
·
·· .. ······
kcomputer
,,··
·
·
·
······
··
·
·· .. ··80
······
·····80
··
·
··8\
standard timing
•
·
·
·.. ·
· .. ·.. ·.. ····· .. ···· .. ·86
................ ··· .. ·· ........ ·· .... ·· .... ···· .. ····90
················································90
........... ·· .... ········ .. ······· .. ··· .. 91
....... ·· .. ··· .. ·· .......... ········92
... ·· .. ·93
................
94
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8.2.6 the power and the control signal of ACPI
....... ,.... · .. ·9
1l1'f!~, PWRGD fill,£{. Il!.~;}"
8.3
8.3
..
Clock.PWRGD and tht: res t circuit
8.3.1
IIft'l' 1l!.~O
,
..................... ·.. <)8
,
,
, .,
8.3.1 The clock circuit
8.3.2
PWRGD
f11\£b'.l:Il!.~~
8.3.2 PWRGD and the re t circuit
PWM ft!Jt§-*J!JfIJ¥
m9Iil
104
,.,
,
108
Chapter 9 The explanation ofPWM circuit
9.1 PWM rgli'-aft~H
9.1
108
The introduction ofPWM circuit
PWM O~T f1=Jm:llliM fr
108
9.1.1
9.1.1 The brief introduction of the working principle of PWM
9.1.2
9.1.2
9.1.3
PWM rt!.~~r11'~·~~)(rii1·"J'fr)(
112
TI,e meaning of common English abbreviation in PWM circuit
EI ¥7H.frt!.~
·
·.. ·
113
9.1.3 The boot-strap circuit
9.1.4 ~JlUIl\rt!).fij~Tirt!ili
.• ..
9.1.4 Output voltage regulation circuit
9.1.5 rt!.Lld'&i~IJrt!:f#· .. ··· .. ·· .. ···· .. ·.. ·
·
115
•
9.1.5
The voltage detection circuit
9.1.6 rt!.1ftIt;ti~IJrt!:m····
·· .. ·· .. ··
The current detection circuit
9.1.7 T.{f-t~:tt··············
····
.
9.1.6
9.1.7
9.2
9.2
··
··
·
The working mode
l~.fJLf4:!.VJ}.·~Jt7Hrr
.
Analysis of the standby power chip
MAX8734A fHfi
.
9.2.1
9.3
9.3
9.2.1
Analysis ofMAX8734A
9.2.2
TPS51125 71'tfi
9.2.2
Analysis ofTPS51125
9.2.3
RT8206AIRT8206B 71'*
9.2.3
Analysis ofRT8206A1RT8206B
.
,.":~
P3 {ffP;Et!Z Jt*~
••:.,.
,P...!t:
Analysis of the memory po er suppLy chip
9.3.1
1 L88550A 71'*'"
,.•'"•.,'!,~
9.3.1 Analysis oflSL88550A
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RT8207 :.rHfr············································
9.2
.4
.mI.
147
nalysis of RT8207
~-mF.l!;t
h 7HJr
152
L
.4 Analysi of the bridge/bus power supply chip
9.4.1
I)i PWM ~llifJ~~ RT8209
,.HJr
J 52
9.4.1
Analysis of the single PWM controller RT8209
9.4.2 )!)l PWM ~ilJtJ~~ TPS51124 7HJT
154
9.4.2 Analysis of the dual PWM controller TPS51124
9.5 CPU ~11)~F.l!'HJT·············································································157
9.5 Analysis of CPU core power supply
157
9.S.! CPU VCORE ~rBDgW.~
9.5.1
The features of CPU VCORE power supply
9.S.2 MAX8770 7Hfi ....... .............................................. ......................... I 60
9.5~
Analysis ofMAX8770
9;-$:3 ISL6260 ~
............................................................. .... I 73
9.5.3 Au8lysis ofISL6260
9.~
.5
9
65'~$J.I~JtISL95831 ~~
180
omy used chip ISL95831 by HM65 motherboard
It626S :StfT
..................... I92
:L6265 by AMD platfonn
.. ···
·
············
·· .. ·202
·· .. · .. ·· .......... ··· .. · .. ·· .. ·.... · .. ··········202
··· .. ·
· .. ·
·.. ····· .. ···204
............. ·.. ·.. ·...... ·.... ·.... ·210
..· .. ·· .. ·.. · .. ·· ........ ···227
• !:Ureuit
......... 232
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Chapter 12 Analysis of Com pal OEM laptop circuit
12.1 f=~ LA-5891P HfH?I%~fU~fJL~~~'Hrr
-
····················"········ .. ···· .. ·2:·,)
12.1
12.2
Anal sis of Compal LA_5891 P protecti e isolation and the standb) circuit
1=~ LA-6631P HiHP~~Eg~1'Hrr
"'··········"······"······"··""··
12.2
12.3
Analysis of Compal LA-6631 P protective isolation circuit
1=~ LA-6751P HiH?I%{i!;I'£lJ~?Hrr
"""·"""""""""""·"·"""·"""· 2 2
12.3
Analysis of Compal LA-675I P protective isolation circuit
~13:f ~~~i-\:I~ic.*Et!.~Et!.j§.~~
·· .. ····
····
·· .. ····"
26
·· .. ··277
Chapter 13
Analysis oflnvenyec OEM laptop circuit
13.1 ~~LbZ5: DosXX Dunkel 1.0 f~iHplWi7i!;Eg~ii7H.rr· .......... ·"""""·"·"""""""··· 277
13.1
Analysis oflnventec DosXX Dunkel 1.0 protective isolation circuit
~~1J6t DosXX Dunkel 1.0 ffl:mIt~&?Hfi"'"''''''''''''''''''''''''''''''''''''''''''''
13.2
Analysis of Inventec DosXX Dunkel 1.0 standby circuit
13.2
13.3
13.3
~~1J6t*f'@.It:m7Hfi""""""'·······"··················"··"
·.. ········287
Analysis of Inventec feature circuit
ocp rQJ!~7tt1T
········· .. ···················· .. ·· .. ·· .. ··
·············288
13.3.1
m14~
13.3.1
Analysis ofOCP circuit
13.3.2
7\:l§Ilrt!.f'it7tfJT .. ···· .. ·· .. ········ .. ·...... ·.... ······ .. ········· .... ········ .. ···· .. ·.. ··295
13.3.2 Analysis of Big OR GATE circuit
[ntel PC" 1t-tJ¥ (13115/[7) ~~
298
Chapter 14 Analysis of Intel PCH sequence(I3/I5/I7)
14. I ~T Intel ME
Intel AMT
····
··· .. ·.. · .. ···
*"
•
..
14.1
14.2
About Intel ME and Intel AMT
Intel HM55 ~J~;t:;JttEl.It1"~7HJi·.. ·....·....··..···· ..···· .~.~1Io!l~:'·.:."....,,-l~""..:.. ..~} .•l! ... ~
14.2
Analysis of Intel HM55 series chipset timing sequence
14.3
Intel HM65 *J~1?lJ:.;t:;Jtmlt1"~7HJi ....·..········· ...
14.3
Analysis of the chipset timing sequence above Intel HM65
$~ K42JR (HM5x) P1J¥~*"
.
~15~
283
298
Chapter 15 Analysis of ASUS K42JR(HM5x) timing sequence
15.1 1~fJL;jft~············ .. ·.. ·
·
·
··..····
15.1
15.2
The standby state
15.2
15.3
Trigger
15.3
15.4
The boot state
15.4
~ 16!P-
M:tJt···········
7ffJL;jft~···
··
.
.. ······ .... ·· ........·........··· ..··
rrt~, PG~~tL· .. ···
.
Clock,PG and reset
1ii* A1286 (HM5x) P1,,~~....~.~~~
Chapter 16
Analysis of AppleA128~
XIV
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. . 343
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.
3~2
····
·· .. ····359
... ,
394
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.................................... -l13
·· .. ····.. ··· .. ····· .. ·414
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............ 467
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.... .. ·· .. ·· .. ·· .. ·467
. .. ···· .... ·470
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J
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............... 494
I
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.. ·.. · ...... ·497
I
.............. 498
·499
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··············545
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m:1I~·I\ ..·.·,.··""",,,,,,,,,,,,,,,,,,,,,,
............. ·· .. ················ .. ········· .. · .. ···550
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=====tl
~1.9 ~-I-~pr;r""""""""""""""""""""""'"
11.9
The network card fault
~1.10
.!..
SAT'Af"\ "J-S<
-Hz:lJ 11)(.
hI,!'.11i-<r.t .....•..........••.•............•..
21.10
21.11
SATA interface fault
)X1.ffljj11:: lJ t&1lf.t
21.11
The fan interface fault
21.12
~tJ1ittll~"""""""""""""
21.12
Crash fault
~221iI
····· .. ··581
···
,
586
,
)88
$1~~1§~······
Chapter 22
···584
590
Example of maintenance
22.1 /f7ftJ1ittll~B<:JtfUi~19~'"''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
22. I The example pf maintenance about don't boot fault
~Wtll
IBM T61 1'3HJ1.
Example I
IBM T61
590
not boot
~f1iJ 211M!! G480 j£*~ilt1'1fm··············································
Example 2
~WIJ 3
Example 3
~f1iJ 4
Lenovo G480
m-m~iIt~~ Z360
592
inflow water,which cause not boot
'f'1fm
595
lightning stroke cause that Lenovo Z360 does not boot
IBM R60 x:ffl'm·····························
············· ..·· ..····
no standby
Example 4 IBM R60
::tWtl 5 fj;.l!iii A42J $ 1I!i'OC!*
Example 5
590
ASUS A42J
601
606
multiple fauh
jf-ilJi 3tJ1~$iiJi K42JR xr.Jm···················
Example 6
ASUS K42JR no standby
~19tl 6
.
'f':bnrt! ............•..•
Example 7
Acer Aspire 47380 poWi
~f1iJ 8 it<@i K42JR 1':bnrt!
.
~f1iJ 7
*~ Aspire 4738G
Example 8
ASUS K42JR powered 0
:tf1iJ 9 SONY NS90HS Sil1I1'1fm ......
Example 9
SONY NS90HS
:t:f1iJ 10 h!!B 410M ~J:.EI!
Example 10
..
Xuri 410M
:tWtlll .~ N4030 I3~
Example II
DELl:, N40
:tf1iJ 12 *~ LSOO ~ftl!r:r:
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22;2
Bxample 12 Toshiba L500
,. 13 .=.li!. R23 ::ffHfL
not boot
Example 13
not boot
Samsung R23
63 I
~~~'ij:.!tfl.~~f9~··························
······633
............. 661
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......
22.4
Jtft!!.ittpl;1~€fl$~Wtl
···
,
674
The maintenance examples of other faults
'tif1J 30 Ir-r..w A8E "t'trl!~I!J.J-m~il"""'''''''''''·''''''''''''''''·''''·''''·''''''''''''·''''''·
Example 30
ASUS A8E large short circuit when install battery
'tif1J 31 IlMl! s10-2 B§11f
Example 31
Lenovo s10.2
674
677
dark screen
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Chapter Three
3 The architecture of laptop motherboard
o
the chipset used by the mainstream laptop on the market is onl} two manufacturer.the
Intel and AMD Intel is the absolute dominance.Once the most popular nVlDlA has quit the
chipset industry in 2010,on the markeuhe notebook computer products ""ith nVIOlA chipset
are few.
3 1 The architecture of Intel double bridge(GMlPM45 and below)
lirtel double bridge architecture.including the 855-GM PM45 chipset.
~~~;J',ddOU~ble bridge architecture.CPU and the
orth Bridge are connected through the
Orth Bridge also control memory, PCI-E 16X discrete graphics card and
card. mini PCI-E slot.etc.
8Ji~ is LPC(Low Pin Count.means one of
by EC are keyboard, touch pad
LPC bus.or connected the South
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PCB control USB, PCI-E IX, SATA, audio card and other peripheral device.
The connection of PCH and EC is still using LPC bus,devices under EC remain unchanged.
It was nothing that in the architecture of Intel single bridge,although CPU integrated the
graphics card,but the display signal output is not usually output by itself.and after transmitted to
PCH through FDI bus.then completed output by PCH.It's different from the next AMD single
architecture.
The architecture of Intel HM75 chipset as shown in figure 3-2.
-2-
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Intel Cantiga
Memory BUS(DDRlll)
Dual C1JlJnne1
'11
__
rl3iiI DDiillos00DIMMbll
2.J
.... 14,11
IIFCBGA-IJ29
. - '7,',.,10,11,12,13
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DMl
USB conn xl
USBl"'nO
_II
PCI-Express
UTA
LAN Bromlcom
InteIICH9-M
_17
Card Reader
Rea/lek RTS5137
CMOS
Camera
_u
:uv_
:uv_ _
BGA·676
. . . . 20.21.22.23
BCM57780
,.",0
HDA Codec
ALC272X
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SATA HDD
Conn.
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3.3 The architecture of AMD double bridge(RS7~()
Because the AMD chipset uses AMD 638-pin PU,so PU can manage IIICInO' y dirculy.
The North Bridge manage all PCI-E dcvice,it's difference froln Intcl doublc hridge,pl·i!'.'
remember.The North Bridge also integrated the graphics card,and is rcspollsible to output di'lplfly
signal.
The South Bridge manage audio card, USB, S/\T/\, I~ "etc,and devices ullder I~ , rClnaili
\JnChanged.
Here to mention,the BIOS has a variety of work bus,solllc work through X-BUS Iindel
Be some work through LPC bus connected in parallel with E ,und some work through Sf'1 bus
ected South Bridge independently,this is not Illuch associated with the architecture actually.
The architecture ofAMD RS780 as shown in figure 3-3.
e architecture of AMD single bridge(A70)
AMD chipset A4S(mobile version is ASO) development,it changed to the sin~lc
caned FCB.There are a lot of similarities with Intel single bridge,the bridge and devices
Care almost the same,so no longer elaborated.The CPU of /\MD also integrated thc
~ca11ed APU,but it can output the display signal directly,and it's difference with the
flntel single bridge.
·teefure ofAMD A70 chipset as shown in figure 3-4.
C 67)
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In the architecture of nVlOlA single bridge.the memo!) managed by CPU.and the other i
managed b. the Bridge.the large heat release of the bridge.ifs easy to \\eld.
The architecture ofnVlOlA MCP67 chipset as shown in figure 3-6.
II
•
• •
I
I
I
I
fi-
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'eIIfOry BUS(DDRIH)
AMDBtazos APU
S""k C1ItIItMI
_Dom-802oMb
.....,. ~ I
3
FTI
BGA -413-BaIl
19rrtm % 19mm
.- .,.,,,
xA UMlGen. 2
._----.....;)MI2Channel S=l:J?
Hudson M3L
I
BGA 656-&11
23_x23_
_I.
WLAN oIWiMax I
pap 27
1D.1l.12.13.U
12
0 SArll.
••rial
" I Audio Jacks
I=j BlueTooth CONN ...... 1
21
I
:»c:
G1GAL4N
I
St.reo
-4. xI PCI·E 1.0
_
)I!nlemal MlC_ 2 7
H••dPhon. Output
CMOS Camera ...... 2211 Microphone Input
10 0 0SB2.0
I
I
ADLU
LPCBUS
USB PORT 2.0 x2(Left)
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Chapter Four
The common concepts of laptop and noun explanation
About laptop motherboard maintenance,often involving some professional tenninologies of the
circuit and signal.To understand the schematic circuit diagram and learn to repair well,we must
understand these concepts first.
4.1
Power supply and signal
1£±1N.L. 1f@it!rn1f 5V 1:\!1li. ~ifJ~73 5V ~I:\!. jf1fi¥J±tI!1:f\SJ;fl~ 5V I:\!lli. ~m
~73m~. ~~~mi¥J~~i£ • • ~?
On the motherboard,some places have 5V voltage,we called 5V power supply,and some places
also have 5V voltage,we called signal,then what's the difference between them?
1. ~Et!
l.Power supply
~1:\!~~~m~~llil:\!~i¥JI:\!1li, 1:\!~~~*oi£I~~~~,~~I:\!1li~m~~~
EJt~:fiI1f£ "((0 *~ I:\!llt:fiI1f£ 7. ~:J!~2&o 1£~ft1t?.5rf, IjffjtB~~ft~i¥J.
0
Power supply is an output current of the voluage and current is~During working,the
voltage can not be set higher or 10wer.Ifthe power sURPlyis 10
. SH
~el'I1 set high
is not allowed.
*1:\!~~~~m~~ni¥J. ~~~*~ft~
YBAT, 5VALW, +3VO~o
The power supply is providing the power to the dcrdl
VDDQ, VTT, VBAT, 5VALW, +3VOetc.
1~I:\!B~~~~~:(m!l4-1 ffi~o
The circuit symbol of power supply is
+1.5V
?
.)
-10-
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"
jD=.i~E@.&&IIIJ:j:1. ~lt IJXI;), pp Jr~, 1)(11~~IJA(Jl~ftBilf-'%, ~ul~ 4-2 pfriF.
hi the circuit diagram of Apple products.the power supply is generally beginning with PP and
en t other special symbols as shown in 4-2.
PPQV75 53 MEM
00 4-2
Figure 4-2
~:W:f=JMJ~f~tJ:\:!.iff-'%
The power supply symbol of Apple products
.iiI!.:Jl~~ E@.fqnltlID&&. ¥i1f~±t!1..
ilJi)F ~ ~ It t.iiUflEi::!: -j,j: -it B B~ 3ti
0
"*- RXJj vss,
$lie circuit symbol of grounding is shown in figure 4-3 .
.....L.
(8)
(b)
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4.2
4.2
High level and low level
.~~~~~~~.*~.~n~~*~,~~~mo*~, .~~ml*~o ~.~
•• ~.*~~, ~~~~~~~ilio@~D~m&~Wm~~~~,
~.~~~~~
3.3V m~j@j~~o
In the digital logic circuitthe low level is represented by O.and the high level is represented by
I.The high and low level in the circuit needs to be decided by the circuit,not to be limited to a certain
value.But in general.OV is low level and 3.3 is high level.
4.3
Jump and pulse
E131'flJ~~m~73ffk~.if-, t!?1l4~~7G, 1nJOO 4-5 ffi~.
From high level to jump to a low level,also called the falling edge,as shown in figure 4-5.
Figure 4-5 The falling edge wavefonn
EI3 j@j~~~73ffk.fl}m;lgiifj,
t!?114~-iff-~JIt~
From high jump to low then jump to bigh;a1so
7.
-12-
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4.4
The clock signal
~ CLK (CLOCK a~ffii~)
, tl!t;ijU~~'tt~:~WjfI1f-tlr:{jt-1-~(j£, 1t~1-~:§ii8~
iJ;iIiIIi'F. It-H+IW.*~1ft;l! Hz <Mftt) 1:E±flXJ:1lfiff-1-±B~-~F~F@.~,
.~f'Fmlt:Jlt€t~~J::(J(Jm1fii-ttrtRd;ltWH·l', ~~JR~i)i~, rJ1"!r!' F[=1.~~*tI:J~Rl8~B'.t
0
jn)!t& CPU IW~.~ 100MHz 1lAJ:. *~ PCI i)i~8~®1I!rI~ 33MHz, *~f; PCI-E
..
lOOMHz i!ta' USB ~IIiIJi* <;tRJJX;r£i¥H1i=!*J$) (1~!J;j)j*~ 48MHzo {g~t§~
~~~*tI1ifJ 1W~f+ !Jim**ll 1t!.1li7tfmjJ1H §
_
m-
1Ytl'tiD. 1*.1 :ff- il'0:1 ~lfr: ff,} ~ I~ ~ 8~ D~- ~~l *[1 It!.
~.ift1}. ~f+ffl.!% ~1:E±flXiE1ji;illl 1t!.J§ J3.1I~·t4';t:.:Jt I 1f-iE1t J§7t~g~~:;:
Jim _ B;j"t+fa"'%
0
0
l(X:k signal CLK{CLOCK) is to provide a benclmmk for the digital circuit work.so that
d vice unified work pace.The basic unit of the clock is Hz(hertz).There is a main
~atiDg:circuit on the main board,the function of this circuit is to provide the clock for all
~i1t:lemain board,for different device,the clock circuit will send different frequency.such as
~~ICY of CPU is more than IOOMHz,to PCI device is 33MHz,to PCI-E device is
B controller(integrated in the South Bridge intemal)is 48MHz.But the two connected
lit'bilvei:th same clock frequency and voltage to communicate.For example.memory and
same clock and voltage to transmit signal nonnally.After main board
on nonnally and the clock chip working nonnally,then the clock signal can be
can use the oscilloscope or multimeter to measure the clock signal.
rR ~-14MHz 1W~*ffl~:(zom 4-8 m~o
ighBl ofcloc chip benchmark-14MHz is shown in figure 4-8.
~j.;~\clhmarK-14MHz
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4.5
4.5
Reset signal
~f\Lf~-'% RST (RESET O~~~~) n~*1ID:@:}iE.:J;ikill;frr7H€iA1fg,%. ~IJ7ftJtA1, *13z;1]1[
h. i~JAi~t:l!4!.lt4t~7:JMill!.>f; IEn'I WM. ;Jt(""f~ ifLW!, ~JAi%tt!. .>f!oJi~~ .>f~6~¥J @]¥U
lUll\! f. WH,ZlJ, ~1T PCI, JA 3.3V !oJ OV lt46~N@]¥U 3.3V ffJt~--i'-IE1tB1}[f.l1.~t~. 1[ffL
i:i.q.-.hVcbF~***RST#, ~lJ PCIRST#, CPURST#, IDERST#~.
The literal meaning of reset signal RST is the new signal.Just starting.it will reset
automatically,and jump from low level to high level:dllring normal operation,press the reset
buttonJrom the high level to jump to the low level then to the high level.For example,for PCI.from
3.3V to jump to OV,then to 3V,which is a normal reset jump.Reset signal is generally expressed as
**"'RST#.such as PCIRST#, CPURST#, IDERST# and so on.
~Z. ~&RR.~~~~4!., ~.1E3IW".& • • • tt!.~.~"m*~~1[m,
jUl"'I~ J.M1119Jiiii t:l!J.I.
IIP!li$Lffi -'%~~:I:..a tt!.1li19 OV.
In short,the reset can only be momentary low level,but when the main board works
normally.the reset is high level.We said not reset usually,refers to no reset voltage,that is the
measurement point voltage ofthe reset signal is OV.
ryHJfbtl±lA~ 3.3V ~€i~&, *~j:HTffi1iX; 1.1 V J6f'Fjg CPU 1{i$L, :ta:J1il4-9 fiJT"ffi.
3.3 V platform reset from the South Bridge after dividing into 1.1 vas the CPU reset shown in
fi gllre 4-9.
2llOII2I~
1414044 00
~Rev1.11
4.6
1 1-
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po er good Signal PG(POWERGOOO) is used to describe the normal power supply. is
UlV"'lIC(lVe higb. or example after sending the CPU voltage normally.then the CPU power supply
send PO signal.The common abbreviations of PG signal are PO, PWRGD, POK,
VTTP
GD CPUPWRGO,etc.
205 J:f1::iE'WiJEi. 2tw SPOK, :tm~ 4-10 PJT7f-.
:r8205 working nonnatly,then send SPOK,is shown in figure 4- J O.
VOl f-o'"-------'
POK
VFB-2.0v
1114-)0 PO -m-li}1II Figure 4-10 PO signal diagram.
4.7
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But orne ignal with "W·.the main board working nonnally must be high. For example, 1999SHDN# shO\\11 in figure 4-12 is the low level control signal for closing MAX 1999.
111ff ffifi!:jf!i::!: EN, PG ~1j§ Ji% ~JJiil.t£ljj~.
Timing is through EN, PG and other signals to achieve control.
Figure 4-11
the screenshot of VR-PWRGD-CK41 0# signal
Figure 4-12 the screenshot of I999-SHDN# signal
4.8
Jt ~ 11i %
================:I
4.8
Chip select signal
ftm cs ~fi!:;c;ft~1f (Chip Select) • m$~ftitf:EIiiJ-.\3.~J:~Bti~, fffl~ff­
~ffiJi%*~*~~J:~~m~~~ffi~~;C;ft~~,~Bt~~~-~ft~ffi%.ftmffi
Ji%~mT BIOS ~ft, ~)(-Rim CS#, "#" ~jFi~Jt~ff~o Bfi!:El3 CPU 1i:l±I, ~~t
milJ1¥H~'F, liE!IJ:!! BIOS 1¥Jo B~flX, IiJI;H}]Z17~Jl9Tm~tf1f& CPU ~N7f~I{'F,
~N BIOS ~~-J.ft~tr-o SPI BIOS JJt4ItiLlnlOO 4-13 WijF, ~tP 1 JJt4I cs#RP BIOS B~ft~
{~-5o
1114-13 SPI BIOS JIlIiftlll
-16-
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tP anation of common signal name about
some manufacturers.
TiIii;tl~-~1t.9i!.r*(jJ,J~.9i!.fJL~f§~ ~l1J;. jffl~i5tllJ]A~
--_."- 4!I~raJ,
~ffJoit~ ~tIU1H~, i! -.~tE~ ~~~ 00 I1t- JE~fHlIllR7t.
fP.ffi.'is different in the name of signal,some common types and signal name in
((jIioUJd be noted that not all signal names are the same for each manufacturer.it
~~~.when we read the circuit diagram.
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LID-CLOSE!;
CLK-E #
close cover switch
after CPU power supply being normal.sent the 10\\ level that can be used to op n the
clock.
G792-RST#
the high level sent by the temperature control chip when the temperature is normal
CK-PWRGD
after the South Bridge receiving VRMPWRGD.5ent the high level for opening the
clock.
fR .y. ~ f:l; S'Im.1! \ilnw
AD...
i1
jlil£ll3~~I1J*IrJ:n-1 EE./f
DCBATOUT
0P<.r!1.
-3VL
3 3V tlGtU/t!t!..
DCIN
rc;1!!.'I:.'!; trJlItt1!~A
ACIN
1fLt!.ZI\trJ~I£~f,t~~A
ff: Explanation
i1t EC fI~Fl!.
ACAV IN
!t)I!..c; HlY1.i.?il£25 r.ll.4~ I1J
PWR 55 EN
IJI J 7ffrimt(rf;'tj/lLt!n;:trJt2~IJki.y.
·5VALW. t3VALW
r.llm~If1.{It!\!.
AD INa. AC INa
~~ EC O!Jili~~ilf1iJ-l}. fltLt! 'f-«~;iliI£3~ttfj J\.
KHC rWR BTN#
I1rF Jf*f"!tlYiilHi't EC (JlJti~{il1i}
LID CL05E11
~ll*~
CLK ENu
CPU fltEtliE'Ml'lS.
G79:!. RST/I
.~~~~~iE~~~I1JO!J.!\!."I'
CK_PWRGD
ltJ~ftJVRMPWRGDJ6. ~lI:IOIJ.EI!."I'. 1lJ-F*JfIJ1ott+
~
I/V1../
4.9.2
J":},
..-.
rjEffil*~'li'
£lI:IO!JfltEtl"l'. iifIlJHf"Jt.tt'!'
Quanta
w. fa ~ .gft.m~ 4-2.
Some of common signal names about Quanta shown in tab)
Table 4-2 the list of orne common ..2"';~·::!.!.I~
VIN
the common point voltage
ACIN \ ACOK
adapter detection
3V-AL, 5V-AL, VL
3VPCU,
5VPCU
3V- 5
trigger
witch.
3V U ,
IR
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;power on the trigger signal,press the power key to produce high-low-high signal to
Be sent high-low-high effective trigger signal to the South Bridge PWRBTN#
ACPI controller signal sent by the South Bridge is used to opening voltage
receiving SLP-S5# from the South Bridge,then producing S3 voltage opening
receiving SLP-S3# from the South Bridge,then producing SO voltage opening
'c Bild all power supply except the CPU core power supply.
ived'1iigh level HWPG signal,delay producing PWROK-EC signal.
core voltage power managed the clock open signal from chip,low
CK-PWRGD open clock chip after receiving VRMPWRG D.
Slm~ CPUPWRGD signal delay buffer
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=
BLlC#
represent high level,low battery (only for battery model)
D/C#
inverse relationship with ACIN(for only D/C#.main board without BLlC#)
IJ ~ It Stgn31 Name
ii'l
f1~
ACIN. ACOK
o J~.¢.i~l!Jf
ilina* 1&i'i!I)
3V AL. 5V AL. VL
3V. 5V f.J(!'llJ~F\!
+ 3VPCU. •5VPCU
EC nWf./JUM!.
VIN
til ~ -g It
If- Explanation
iii'
ff
3V S5
~~~T~~ffi.
~ffi~m~~. ~R*~~, ~~rrg
... 3VSUS. +5VSUS
S3 :tX~nYrt!H,. Jl;J1f.fI~F\l, III EC ZtW SUSON JFFw
NBSWON#
~i'Jt*.jU!l1..i3f:l-Y-, j1iT~i'J;DfY.:ml""l-:i;'f,-il~-I:;,rJ%:i-Y-'f, EC
DNBSWON#
EC 1;tWA~JiI'Jj-fl5;-il'Jjff~fI!h~irl \}!£,+Jt1fAY PWRBTN#
SLPS4#. SLP.S3#
55 ON
i¥lt/fUtHOY ACPI12fM:I»fil-Y-, mILn·l J.Il-j-~Ili7fJA, ;)HILII·l mT-tI!.Ili~I'?l
EC 1,tW(Mjll'fj~tJLF\!J~:lrFwfR 1;. JtftJll.J1:t.'l PCU ~iJ~ S5 rl!1f.:
SUSON
EC ll~l£~JlWll'f:tl:*A~ SLP S5#Jrii"'':En~ S3 rt!!:liJrFwi;'j I;
MAINON
EC tl~Utlj$jfli:R*rt:l SLP S3# ~j""1:C(.j SO ~ffiJf 1.:1 ifl-lJ'
VR ON
EC 1;tWA':I CPU ~·C.·rt!It.:JFFwfR~
IIWPO
~'* CPU ~·C.·fJttl!.~).~~rt:lm1-H't~n~ PO j~UUl1E1ilii*
PWROK.EC
EC I/l{JIjitlirt!lf'- HWPG fA ~'Fn, j,[Rti"'':E PWROK EC fa~'
DELA Y VR.PWG
CPU ~·ul\!.llitl!iU!l!fra-l}
VR.PWRGD.CK410#
CPU ~oUtl!litl!ill'l!JI~Wl>ttliC(.jp.jt'l'7flfHa-lt,
CK PWRGO
Mfmi&jj VRMPWRGO Ttl, 1,tUJ CK]WROO JfIi1lIl1\'1'.t:::J.1'
il~tt!.lf'-
CPUPWRGO
tEMftlf~8Il PWROK
PLTRSTh
If'-&.~. MftlftE1,tUJ CPUPWRGO ffl i}zTtl. ~M:iill1t1l'!'1,tUJ PLTRST#
_fl'L& VRMPWRGO IlllHtLjlljfll'3'~i:l ~i!mr"1: CPUPWRGD
ft!li~JAWJtfI~~7f!lliIf1'
I'CIRST#
PCIj[fl'L. /fiT.l:.tt!.JIlt1J[fl'L PCI.l!lil!.J:l'JI.JlU"
CPURST#
CPU ll«LftJi}. ~tM~ PLTRSTIIJB1,tW CPURSTII~ CPU
BUC#
itlirt!~. ~~~t&(&mT~~)
O'C#
.!J; ACIN /i.tftLifllJ~. (iiJDffitf DIC#. 'illf BlJCtIfIlJ~-l!t)
[)(){> 4.9.3 $fi9i ASUS
ip,@j1f1.11t~ ~ra-Ji}~$m~ 4-3.
Figure 4-3
AC-BAT-SYS
ACIN
adapter detection
20-
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SV linear voltage
3V linear voltage
+SVAO renamed +5VA after jumper
+3VAO renamed +3VA after jumper JP81 0 I
+3VA renamed +3VA-EC after through the inductance as the power supply of EC
sv standby voltage in S5 donnant state
3¥ standby voltage in S5 donnant state
+'SVO renamed +5VSUS after jumper
+3VO renamed +3VSUS after jumper
SUS voltage power-good signal,to EC
the reset signal of the South Bridge ACPI controller,can be understood that the
~~~iYing PWRSW-EC,EC sent PM-PWRBTN# effective trigger to the
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=
I·e deln. l'd ')l)I1\S 10 semi VI{-ON aner sending SlJSI1-0NJor opening
It -\ I )
l'
core
\( 1t.1 l
E - LK-E
EC -cnl VRMPWR
to the outh Bridge pin.infonn the South Bridge that CPU
core voltage i nom1al
the
CLK-PWRGD
outh Bridge generated CLK-PWRGD to IC clock after receiving
\ RMPWRGD.for opening the clock signal
PM-PWROK
after receiving ALL-SYSTEM-PWRGD.EC delayed sending PW-PWROK
H-CPlJRST#
the North Bridge sent H-CPURST# to CPU after receiving PLTRST# signal
GATE-PWR-SW#
the boot trigger signal
L1D-SW#
close-lid sleep switch signal,when the machine is closed.the signal is low level
L1D-KBC#
the close-lid sleep switch detection signal for EC
KBCRSM
the keyboard wake-up signal
FORCE-OFF#
HW-PROTECT#
OTP-RESET#
the forced shutdown signal,generated by the undervoltage protection circuit
CPU overtemperature protection signal
CPU overtemeprature indication signal
..
"Explanation
ACIN
·5VAO
~3VAO
~3VA
"5VO
43VO
+5VSUS
+3VSUS
VSUS ON
SUS PWRGD
-22-
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EC lt~!{i'IJ I'WRSW ECf/lfi'l,(.II\ I'M I'WRBTNII (TXdl!lI'l,;."'.lm(rn~ I'WRI3TNIIIJ.!WI.
so 11!.IL:;n: lri In I}
l~lffl~1I:fIJ VRMI'WRGD Jiii"'1: CLK]WRGD gll·Ii'l' IC.
Jlrf JFIJIIott<i'lh \';
EC ~\(flj ALL_SYSTEM]WRGD Jf;. JiIl·t&IIII'M I'WROK fa'}
Jtffl~\(flj I'LTRSTf/lo'I r; lii'l.Zlll H CI'URSTII g
CPU
the list of some common signal names about Compal
sigD8.1 is inserted to the adapter and the high level represents that the
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PBTNOUT#
the boot trigger signal sent by EC to the South Bridge
SYSON
S3 voltage open signal
SUSP#
SO voltage open signal
+VCCP
the working voltage of CPU front side bus,this voltage distributes in CPU, the North
Bridge, the South Bridge
+CPU-CORE
VGATE
CPU core voltage power-good signal
ICH-POK
BCLK
CPU core voltage
PWROS for the South Bridge,inform the South Bridge system voltage power good
the front side bus clock signal
SUS-STAT#
sent by the Soth Bridge,the low level indicates that the system will be power-down
mode
ra -l} ~ It Signal Name
Wi
~
Explanation
B+
PACIN
VL
+3VALW, +5VALW
ON/OFFBTN#
ON/OFF#
PBTNOUT#
SYSON
SUSP#
+VCCP
VGATE
BCLK
[){)C> 4.9.5
DEIL
-24-
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Figure
the list of some common signal names about DELL
the motehrboard button battery voltage
power adapter voltage input
the common point voltage
Ee sent a ALWON signal to the system power supply chip,to open the system p wcr
overheat protection signal active-low level
a low voltage signal generated by the power switch or keyboard,and Ee chip
receiv~ the trigger signal,EC sent SUS-ON to used to open the South Bridge
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PGD-IN
one of the conditions of that CPU power supply chip sent CLK-EN#, PGOOD and
others.
CLK-ENABLE#
the open signal of clock chip,active-Iow level
H-PWRGOOD
PGD reset signal sent by the South Bridge to CPU
H-RESET#
the North Bridge sent CPU reset signal
+VCHGR
charging output voltage
+SBATT
Auxiliary battery power supply terminal
+PBATT
main batter power supply terminal
SBAT-PRES#
insert the auxiliary battery to detection
PBAT-PRES#
insert the main battery to detection
IMVP-VR-ON
open CPU power supply
IMVP-PWRGD
power supply good signal sent by CPU power supply chip
IF! .q. .g ~ Signal Name
...
~ Explanation
ALWON
RUNPWROK
SUSPWROK
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CHGR
S!MlT
If.1'BAlT
JHl CPU fJ~rt!
t:::Dt> 4.9.6 • • APPLE
• •ifI#,* ~m%~~~~4-6.
Some ofcornmon signal names about APPLE shown in figure 4-6
Figure 4-6 the list of some signal names about APPLE
V42-G3H-REG 3.42V power supply in the condition of G3 equivalent to the linear power
Iy of other machines.
3.3V power supply in the condition of S5 provided the standby voltage to the
3.3V power supply ofthe South Bridge RTC circuit
common point voltage
the indicator signal oflow battery voltage,active-low level
S3 state voltage(memory supply) of L8V open signal
from all power supply good signal except CPU power supply converge
,.....,...,...c"'l"oc~sent by CPU power supply chip after
-27
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MC-ADAPTER-EN
the high level signal,olltpllt by SMC after receiving the adapter detection
signal
SMC-BATT-CHG-EN
the charging enable signal,sent by SMC active-high level
SMC-BATT-TRICKLE-EN-L
ACPRN
the trickle charging signal,sent by SMC.active-low level
low level ACPRN sent by charging chip after the adapter is detected
ONEWIRE-EN
ONEWIRE enable signal,for the adapter to identi1)t circuit(the head of power is
green)
fn .y. 'Z It Signal Name
ff Explanation
"
-PP3V42 G3H REG
G3 :tIC~rR!j 3.42V fJ!!\! • .mllT:Jtitl!milSR!jt~t.H:J~f\!
PP3V3 S5 REG
S5 :tR~rlY:J 3.3V mil!.. !*WHJj:~!lHJWjmLt!.lli
PP3V3 G3 SB RTC
mt#fB'1 RTC !\!2II((oJ 3.3V mf\!
-PPBUSA G311
~:Jl< l,( 4!..ffi
PM BATLOW L
Il!.tmll!.lIiflH~~m-l}. fLt;Lt!.'JllHt:
IV8S3_RUNSS
VR]WRGOOD_DELA Y
I.8V ((oj S3 :tIC$fI!ffi (~ffmfl!) *.€HB~
Il! CPU fJtfl!~;.l*lY:Jl1TliffM!tfm~'".!;jiJiBI~
CPU mfl!~Jt:iE,*1"~ CPU 1l!.8£.I6. IiIl't~tI.IB'1!f!.tf
VR PWRGD_O:.505_L
CPU fJ!1l!.;c::Jt :iE,*"1"~ CPU fl!IDii • .ttI:lHfJaIt.j't-I'CJlJfl1;rt!'Jlra~
ALL. SYS PWRGD
fii .y. 'Z ~
ilil:.ltl!lfilf~. ..Et!.1f'1lf~
SMC_BC ACOK
*'
.
SMC_ADAPTER_EN
SMC a&jfJiil:hlJ!U*~JS • •wfICJliEt!~-IJ
SMC BATT CUG EN
SMC .ttll:l flCJ1t;Et!flt!1!-IJ. ..Et!.lf• •
SMC_BATT TRICKLE EN_L
SMC.ttWfICJ~.1t;Et!1!~ • •~."...
ACPRN
1t;rt!~Jtltl!lft.~JS~~~~A~
ONEWfRE EN
ONEWIRE flfl1fl-lt. lOTiiEII:ISUJIJU (Et!.~M'm
[)(){> 4.9.7 ~.ill!~ INVENTEC
~~iE$7t1it mf§-%}i?if;m~4-7.
Some of common signal names about INVENTEC Sbo
.4-7
+VADP
~28
adapter interface voltag
.
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~1.~·:E1N:#
adapter enable active-low
adapter detection output,it can be used to open the system power suppl) directly
common point voltage
linear power supply
the signal sent by trigger switch to EC
the power signal,is sent by EC after EC receiving trigger switch,is used to open the
.~~n·:standby power supply under the battery mode
the initial reset signal ofEC
standby power supply system
the adapter intermediate pin,power identification signal
M-
ff Explanation
~~IBM) shown in figure 4-8
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In \, t; Fl' SIIlIl.ll N;l11w
noc K I'W lun I·
it~ I\(~ :!~ Il!. /Ii
t \'_0
jiS~~~ 1)0J" f.f... LIIIJn~J
VIN r:!o
DISCIIARGE
~}J".o:'!'.
~~'ln,IJ XI iJUl tl~ m; , ll!.il!!!Jl(Il!.f,·1 \1
-I'WRSIIUTDOWN
Ji/I.!. ~lrf~~~f;.Ij, J[J·:r-~';lmU!I'iC~fr
'IV
H Explimullun
i 1l!.1I
VCCJSW
TB ,i:::H4JIlWfl:)3.3V fl!./I;. J.:H.-PWRSIIUTDOWN, ~1f)tlli,1::·H fJlFl!
-EXTPWR
1Ct1:!.;;:';H-~~ 1±I0~i5:n~:t~If:l:it!IHrt"1. fl~t1:!.'fH~
-EXTPWR ASIC
JOClli·i:::J4 A%1J:l\C$r.;i¥'~4u~Af;:' ~
-EXTPWR 118
118S O:Ji5:tf~~~f"&mtl~'J;JAlaJ,}
VL5
flJ!11.,i:::Hr:1:.fl~ 5V tJH'lF\!lli
DCIN DRV
rnTtl!:hIMlli!~CAI1\Ii"''l!f • ,;'jt1:!. 'l'U·J 7C3t.\T-il.!iifi~~I:M"'fr
I;. ~ ~ f~:
BAT_DR V
MI_ON
VCC5M
VCC3M
TII_DET
ACDET
SWPWRG
VREGIN20
BAT_VOLT
MPWRG
-H8_RESET
VDDI5
VCPIN28
TB <'>Jt-ttIlJJ M EMUE'M"Jii. 1!I~.Ii8lJ 28V _Ji2SV). Ji"f_iU'JI.tiI
CA N #ililUilUI'
BPWRG
AMTPWRG
-PWRSWITCH.
-PWRSW
M_BATVOLT
MJRCI.
_TRCI.
30-
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the adapter voltage
the voltage between adapter and common point
forced to close adapter,battery discharge signal
over-temperature and under-voltage protection signal,used to isolate the
3.3V voltage,output by TB chip,pull-up -PWRSHUTDOWN,to supply power to the
the adapter detection signal,output by the charging chip,active-Iow level
the adapter detection input signal ofthe Lenovo chip
the adapter detection input signal ofH8S
efSXTlinearvoltage,generated by the standby chip
the spacer tube,used to control adapter,turned-on the adapter spacer tube fully at high
tube used to control the battery,isolated the battery in a high level
is
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WPWRG
the standby voltage good rthe Lcnovo chip
VREGI 20
the voltage with a small current generated after the adapter or battery accessing
to.for the power upply orTB chip.
BAT-VOLT
VREGrN20 voltage detection pin,the threshold is 2.9V
MPWRG
TB chip detects VCC3M, VCCSM are nonnal,sent PClRSMRST# to the South Bridge
-H8-RESET
VDDIS
the reset sent by Lenovo chip to H8S
TB chip detects M voltage is nonnal,bootstrap boost 15V.To provide power to xx-DRY
orTB chip output
TB chip detects M voltage is nonnal,bootstrap boost 28V(is 25V in fact),N channel
VCPIN28
field-effect tube for driving and protecting the isolating circuit
A-ON
A voltage is turned on(S3 voltage,such as memory power supply)
B-ON
B voltage is turned on(SO voltage,such as the bus PQwer syPPly)
B-DRV
B voltage drive signal,sent by TB chip
BPWRG
power-good,sent by TB chip after detecting
AMT-ON
ME module voltage is turned on
SLP-M#
sent by the South Bridge,used to contto~
AMTPWRG
AMT power-good
-PWRSWITCH, -PWRSW
BATMON-EN
M-BATVOLT
M I-DRV, M2-DRV
-32-
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12.6V charging voltage,control output by charging chip
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=
~ic.*egn~9=Jujeg-=f5Gft:±~1f~~, It! [ill. ,
fJkff , =,fJ.HE, ~~,-,v.t!f, r J ~l:!.m, It
~ • • •ff ••• ~ID~~.9=J~~ffl, ~~~_.~~~*M~~*~U*~~AM*
i~. ~~·tI-1'~*ujeg-=fegn;J~H1335C1HI1.jgilif~~~et!.:mi!IHiili~/'g~IH~AU<:Jt~~iHk.4>: ,;'i:
:±!Hr~E.e- eg-=f:7tftJ:-tE eg~~~ u<:J~uiliJ§lm, JP\"E1*:7tftJ:u<:J iA iRfj]~W:!i1. ~j] *it~t'll(j5Gfll'l(J
~m~.~~~.~. ~~.oom*~~~., ~®~1f*~jg~~ ••
Chapter Five
The basic application circuit of electronic element
Electronic components of laptop are capacitors. resistors, diodes, transistors, field effect
transistor, gate circuit, comparator, voltage regulator and so on.They are the most changeful
when used in the circuit.For the people who have just touched with laptop repair.it's quite difficult to
understand a basic electronic circuit.It makes the circuit-based become a stumbling block for
maintenance people.This chapter mainly introduces the basic application of the electronic
components in the circuit,and dose not include the understanding and measurement of components. If
the reader is not familiar with the understanding and measurement of components can refer to the
relevant basic book,there are a lot of such books on the market.
l.Filter capacitor
~~~~ffl-tEeg~~~eg~*,ffl*d
~, ~*eg?ff-m$X/J"l¥J*ffl~Jt~~~o II 5--
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PC90
Figure 5-1
PC89
PC93
PC161
Filter capacitor
.Coupllng capacitor
it~J3:m,*"*,ED~J:f~~, J§Z,EDtE PCI-E fO SATA B1f§-'%~.l., ~IA~tjb~$~!HE1"§-'%
fF,ED;1!,ED*IlI.:m:~, *f*i.iEi\lJ!m~B11t~o :!mOO 5-2 JJJT7f-, 4 1-#~~8~Eg~JJYt
1#, W3U~~til.
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PCH RTCXl
PCH RTCX2
YI
i-----'--lD
J2.768KHZ_12.5PF_CM3'5327680ZFT
1'81'
, C181
_0402_5OV8J
Figure 5-2
Coupling capacitor
Figure 5-3
Resonant capacitor
Basic application circuit of resistance
rg~JltE~-F~~9Jt¥J~ffl±~ff...tr1[~~.I3., {~HF~~.I3., ~fj~~!l.JLfr/!.
The application of resistance in the board circuit are mainly pull-up resistance. pull-down
resistance, protective resistance, thermal resistance.
I.the pull-down resistance
iill1f;:Jt~llit¥J~m1g...t1[~m (JA!.m 5-4), ~:J:l!1.t¥JI@.Im.;Jgr1[1@.1m. (£00 5-5) • ...ttli
~~~~~~t¥Jffi%~~-~l@.lm.m~~.I@.~,
1@.1m.~~~~~~ffl.rtt~~.
In general,the resistance connected the voltage is the P.W:I-:YJrres'
resistance connected the grounding is the pull-down rest
uncertain signal at a high level through a resistance the
in figure 5-4),and the
I-up is to clamp
' 'ted effect at the
same time.And pull-down is in the same way,
+1.05V
~
00 5-4
J::.~rtm
Figure 5-4
pull-up resistance
Figure 5-5
pull-down resistance
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::f:"Fftrt!lm.tmE!lffl:tullE 5-6 JiJTiF: ~ R206 %Lt.. R205 /I'~ot, lNTVRMEN /3~Eg
VOCRTC
-'jZ, ffJ§ ICH7 i*J$B~EgfflJWTJ~ (l!.\i~iAm); ~ R205
~L, R206 /1'#&01, INTVRMEN /31lt ttf,
INTVRMEN
--'
£i\a1:S1e
(default'
1
Disable
0
R2lII
332K
,.,.
R2lII
*
If]
ICH7 i*JWB~Egff~lJ.7,~o
The application of pull-up and pull-down resistance
shown in figure 5-6:when R206 is installed and R205 is
not installed,the INTVRMEN is high level,open the
~.
internal voltage regulator of lCH7(the default value);when
R205 is installed,R206 is not installed,INTVRMEN is low
1115-6
J:."fttltmeffl
level,close the .mternal voltage regulator oflCH7.
;t~Et!J&: ~ff1£..ttt, Xf¥fFftt, I1Pfij..5.X;*ffEg~4l, :!zoOO 5-7 JJ)TiFo *If';J(:5tffi~~/'g
VA=V .~(RI+R2)'" R2
The voltage division circuit:both the existence of the pull-up,and the existence of the pulldo~tbat constitutes a voltage division circuit,as shown in figure 5-7.The fonnula of series partial
pressure is VA=V ~(RI+R2)*R2
iRe ~lt-tl:@.i& (Jh!.OO 5-8): +VCC_RTC t£M R1701 1t~ Cl704 Jt;Eg, RTCRST#FE!.ff~
ft, i!1'..tftIUl§j+VCC_RTC I:@.ffi~~JiJT~:fHt-Jll1rEi]m~MB'j"B~A..I"I'8]o MO~'B~'rEi]B~fB'j
~P.TW.ffl R*C, jm 20~ *1 ~F=2Oms.
IRe delay circuit(shown in figure 5-8):+VCC-RTC charge C1704 first through R170 l,the
ffi# voltage will slowly rise,the time required that it rises to equal with +VCC-RTC voltage is
lay.eel time.A simple calculation of the delayed time can be used R*C,such as
~~Oms.
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ft, M. ffijits:iIH~HJ~ 5C1*B~ § B~
I:t!.mL
0
f~Hp f[IJ1I.llJlffi -f.J9::m1:E 10~~) ~ 00 5-9 t:j:J R243 ffJt~f!fj?
0
The protective resistance plays the role in protective effect.When the circuit load becomes
large,beyond the range of resistance can afford,resistance will be open circuit,make the
corresponding circuit to stop working,so as to achieve the purpose of protecting the components.The
resistance of protective resistor is generally blow 10
.In the figure 5-9,R243 is the protective
resistor.
Figure 5-9
the physical map of protection resistance
3.Thermal resistance
;Jt.1: 1f1 ft!Jl3. 7.)- "~& ~ ~ ft!Jl3. ~ f~" (NTC, ffJ. ~ Ijt~H&) ~IJ "~Jjt ~ ~ ft!Jl3. ~ ~ "
(PTC, .iE~J3i~~O jIij;fij1o ;Jt.1:~ft!Jl3.~DOO 5-10 FJT~, ::ftlM.~~l:;R:::f~~7.)-t\j NTC ~~
PTCo
The thermal resistance is divided into two,"the higher the temperature,the lower the
resistance"(NTC,the negative temperature coefficient) and "the higher the temperature,the higher the
resistance"(PTC,the positive temperature coefficient).The thermal resistance shown in figure 5I O,but we can not distinguish NTC or PTC from the physical.
PH4
~
(b)
(a)
III 5-10
Figure 5-10
~.Et!1l.1l
the thermal resistance
-38-
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=
.Or gate application of diode(shown in figure 5-12)
if~~m
3V BAT ~~, :fi1tJ.J§m 5VALW {'±l;~,
l2Ut~~'1tJ.7tE.EI§.jL
PJ1V,f~hiE
€CRTC ~~1f~o J1t~=~'lf-JN:~!'l..g.=;t}klf, ~¥J.]~[] 00 5- J 3 p!TiF
Power failure with 3V BAT power supplY,after plugging with 5VALW power supplY,in order to
save battery power,can ensure that VCCRTC always have electricity.Such diodes are generally
0
composite diodes,the material object shown in figure 5-13.
TI ~~
+---Z-1
1115-12
=ti~B"J!OCn@ffl
Or gate application of diode
Composite diode physical map
2.:A:ND gate application of diode(sbown in figure 5-14)
~~.=••ti::iiiH(.J-ff-ul'%lf{l(;ItJ..>ftl:lJJY., =f&'lf:m-~Jm,
mil(; HWPG
0
Ns long as any signal at the left end of the diode have low level,diode will conduct,pull HWPG
+"SoI
HWPG
HWPO
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m 5 ~ EIFJ-J[f~~09lnlllfiYmEt!rm
==:====================~~~=~==========t
VlN
3VPCU
00 5-15
PD9
A
=tbt'm'(j~ttHftSffl
CJ) VIN El!lli Cffiii9:jg 18.5V) ~i1~JllPR29, PR28 $~7tlli, 7tlliJ§EI!llijg7.6Vo
(I )VIN voltage(assumed to be 18.5V) after resistance PR29,PR28 series partial pressure,the
voltage after partial pressure is 7.6V.
(2) Jlta-t PD9 iH&EI!lli;Jg 7.6V, pH&EI!lli;Jg 3.3V, ~Jlt.iEf&*+pH&, llM1i1Jt~)ffi
lli~~ 0.7V
0
(2)Now the positive electrode voltage of PD9 is 7.6V,the negative electrode voltage is 3.3V,so
the positive electrode is greater than the negative electrode,and over the conduction voltage drop
0.7V.
(3) PD9 ~jfji, ~jfjiJ§=f&1flE~.R~th:ffJ.lfiffjtl:l
0.7V, ~J1t A R,:Jt!J.Hl/(Wfftjg 4V tr.ti
Wfft=f&1f-~tE USB ~J:l:at VGA ~O~lil, fflTIUi~EI!1zIl00 5-16 PJT7Fo
0
JVGA VB
(3)PD9 conduction,the diOde
conducting,so the A point voltage is 01
Clamping diodes are geneiall}:
static electricity shown in figure Si- •
Figure 5-16 Anti-static clamp'
-..JO-
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+5VO
1l'C28T
TOOOO
o
R9000
1KOhm
TPC28T
~
+2.5VREF
C9000
,UFI1011
MlCCl+J.10%
'Wheri the diode reverse voltage to a certain
~1be reverse current will suddenly increase,which is
ea the breakdown phenomenon.In the state of
wn,the current through the tube changes a lot and the voltage of both ends of the tube is
Constant,by using this feature,it can achieve voltage regulation,which is called the voltage
diode.In the figure 5-17,U9000 is 2.5V voltage stabilizing diode,when the negative
applied is more than the regulated value,then the reverse breakdown current will appear,so
dl~e of both ends can be fixed.R9000 is the limit current resistance,and the reverse
ao
current ofthe voltage stabilizing diode is between 5-40mA.
- 8 'i:P. PD12:Jg 5.1V affi=fitf, ~ VS :Jg 19V 1l1, 1Jr@J:1t:f;1;j;]R, lJIl2J,ili5f, ¥U
1t!1UfF 13.9V. Nt£J:J: PR87 ~ PR90 ~ffi.J!~~)=f 6 }J!lJ SHDN#it7~7f Ja, § 81
.1f£ El!.ffi .R1f VS j{iJ:J:-}:Emp;J-. &jRJtli~z.J5 fijJj- ffi7tf'i~TJiijfE SHDN#B1 ~
0
~ 5-18'pD12 is 5.1 V voltage stabilizing diode,when VS is
19V,applied to the
bi:o en down,the voltage reaching the positive is remaining 13.9V,and after the
ore 0
S!'[ and PR90 to send chip 6 pin SHDN# as open,the purpose is to limit VS
y V;oS exceeds a certain value,the partial pressure after the reverse breakdown
hold value: of SHDN#.
N:C.
... i
IIHDNf
OHII
OMS
DH3
IlU
UC3
0U13
RI3
PQOOl)
REF
i
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M 5 ~ 1t!-¥-n:,q:09Jilil@JDIt!Il3
~======================~~=~==::::~==========i
Basic application circuit of transistor
t:E~ic.*El!IDMEl!:m9=J, - ~&~B~@fflljt±~~7f~fFffl: NPN =::m~ E ~&*±t!!: B f&
.A.El!~",C:m~~~~; B:m.A~~~",C:m~a~~.A.~~:
In the laptop circuit,the main application of the transistor is switching action:E pole of NPN
transistor connects ground:when B pole input high level,C pole is low level;when B pole input low
level,C pole is high level.Specific content as follows:
~Jm NPN~: VB>VE 0.7V ", B-E ~jffl, C-E t!?~im.
Common NPN type:when VB>VE 0.7V,B-E is conducted,and C-E is also conducted.
~ii PNP~: VB<VE 0.7V ", E-B ~im, E-C t!?~Jm.
Common PNP type:when VB<VE 0.7V,E-B is conducted,and E-C is also conducted.
00 5-19 rep, A F.:\~~El!.iJZ 0.7V I~LI::", t.£i1El!~il1Joj~=:~&1f B ~&,
Jill , Y ~ii'tr :±l fe; El! .IjZ- •
-~,&~ C-E mt~~
In the figure 5-19,when A point is high level 0.7V or more,applied to B pole of transistor via
resistance,then the transistor C-E will be conducted,and Y output low level.
00 5-20 9=J, PQ41 :JgP3*El!~il(fll!!:~ NPN =:f&lf, jiij~AffiYfJm=t&~~~.iJZ~im,
fe;El!~~~~*tt.~i1, Bf&El!~~~*i1Ef&~ffi-~~,~~~~~m*~~~~~
-¥Jl!t. DTCI44EUA, t.£~¥M, Jt.ijt)l~.m Pi(...)=1.9V, :mill 5-21 JiJT7J'.
In the figure 5-20'pQ41 is the digital NPN transistor with inner zone resistance,it's same as
the common transistor,also has the feature of ihigh level conduction and low level cutoff.However,the voltage of B pole must be ~
value,about this value,You need to check the reI
conduction voltage is Vi(OII)=] .9V,as shown in fi~ ..,
the vol1&ge of E voltage for a certain
n CCording to the manual,the
VCC3
y
A
00 5-19
-·12-
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the application of common transistor
the application of the digital transistor
-20
S-22 ,,=It'lf7f*fFJfHt-JJ§Zffl: 9fJ3+VLDT r~ffitifi1 O.7V JE, 1JuiU PQ26 B~ B
~~~iI; tlLi~ PQ25 a<J B t&. PQ25 ~Jt: +3VRUN H~J:.tL VLDT_PG, ;O:~~~
U.5•.
Figure 5-22 is the application of transistor switching action:only when +VLDT voltage is
greater than 0.7V:added to the B pole of PQ26,making it to be conduction.;pull the B pole of PQ25
1 tPQ25 is cut-off;+3VRUN pull VLDT-PG up directly,generating high level to send to rear pole.
..
0 . _....
InpuIVOIIgo
8ynIboI
IIln
Typ
II•• Un"
V_
0.5
1.1
-
-
...
V....
3
T••I Condition
Vcc_SV, 10. 100tJA,
V
Vo- O.3V, 100:: 2OmA. ODTC123EUA
vo.a.aV.lo= 2OmA, DOTC143EUA
Vo. a,3V. 10. lOrnA. OOTC1,4EUA
Vo. a.3V, 10- SmA. OOTC124EUA
VO"" a.3V, 10 = 2mA. OOTCl44EUA
VO. a.3V.lo. lmA. OOTC11SEUA
III 5-21 DTC144EUA fdf,T;'f-llJ]-mt~
+-=~---_-:»VlDU'G
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m 5 w 1t!~J[f'togllfJ9lfiYmlt!;m
:::::=============~~=========i
SVPCU
y
Figure 5-23
the switching action of the field-effect tube
00 5-24 9=J. ~ SUSON /3i'iliIt-'fnt. PQ70 ~ifii, tL1~ PQ73 (j~ G ~&. PQ73 ~.J1:;
+15V Ltl SUSD /3 ISV, ~tft PQS6 ~ PQ76 a~ G f&: PQS6 fO PQ76 tI~PJt;).iti:~jffi, J
1: 3VSUS, SVSUS (N~:ii MOS iGi:~iIDa~~11j:: VC;>Vs 4.5V l?J-.t)
0
In the figure S-24,when SUSON is high level,PQ70 is conducted,pull down the G pole of
PQ73.PQ73 is cut-off;+ISV pull SUSD up on ISY.to send to the G pole of PQ56and PQ76:PQ56
and PQ76 can be conducted completely generating 3VSUS, SVSUS(the condition of
channel
MOS full conduction:VC;>Vs 4.SV or more).
8USONC=>--~"'HI'.1
-14-
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Figure 5-24
examples of application of field-effect tube
Basic application circuit of gate circuit
74NtC1G14GIIIIUI0T3535
Figure 5-25
the application ofthe NOT gate
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IMVP]WRGD
EC PWRDK
00 5-26
Figure 5-26
~fl~ffl
the application of the AND gate
-~'l
3 • '=',.:.-1
3.Three-state gate
00 5-27 m7F~.=:~nmm: 9-1f~ OE ~11£~.3f1t-j, ~l±li¥JEE!.3jZ-;;t~~4iJ"IJ}dl~
~~-~(~Tm~B); ~OE~~EE!..3fIt-j,~~.A~*~~~,~~~~~
~.m~omOO5~7~,~B~~~~~.,m~~EE!..~~~mM~~EE!.~~
~11: ..t & lK ~U
0
The application of the three-state gate shown in figure S-27:only when OE is low leveI.the
output level is consistent with the input level(equal to the follower);when OE is high level,no matter
what state the input is,the output is always keep high impedance state.But in the figure 5-27,OE has
been forced to ground,so it s no difference between this circUitimd follower in the level logic.
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Basic application circuit of comparator
fJ.6VIHII:IIE 5-28 ffilf-, 3Y E£!.7tB:tJ03iO~tt.X~&;f§~iU,Ajiffi. £3 YIN 5}ffJ§B~E£!.ff
jeT 15.67V~, 5}ffia~E£!.ffi~1rJlJT3Y. ~UX~7fi\lHiJ"'I)tJ:\ (7 )j!;p£3 PU48 ~t$.l(
) EB RSMVCC3 J:.:tfL ACIN 1iXi'CfjE£!.3f:i!~;c:;Jt: 3 YIN /J\T 15,67Y Ai. tt$.l(
f&oIfl (7 • .!:i 4.~JlU~ti).
ACIN :fBltL3iIJitB.
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M 5 ~ tl!-J-nf~09}lfilllfiYmtl!m
===o:=:=================~=~~==========1
amc timc.because the comparator output low level.leading to PR 167, PR 163 series.and fonn
cries with PR 161.50 that the 2 pin voltage of PilI is pulled down again.
Figure 5-29
the comparator in a temperature control circuit
~PHl.~*•• m.~~~.~2~L~. ~~.5~~~~~ffi~~~6~~
2.5V. ~~!tX~~'lJ:±l 5V ~~.iF. -~(t PQ39 ~)!. 1iL1i.t; MAINPWON. *ffEEE!.~:Y.t~~I~;
[i'iJnH~~*~~'lJ:±l(8~~lf-, ~{f PRI67, PRI63 ~ PHI *JVZ:JfJf*. JAffiHE PHI S<J 2 Jj!p~ffi
.pJ{j':tftI~-R:. ~1- PRI67 tt~iB$~~lL {1=lf1-Al$~E:T:1 "±&Ek1jt~~Ji" 11=J:lL~1.t
CPU ili!}}t (~Hp 1R ~ ~ ~ l' :(£ -1- R.i:..t. , ~:flIl 90'C Mtgd~H? 5O'C :t R~ ·t~O[ iE 'Ij;
0
m
0
When the temperature of PHI increases,the resistance is reduced to less than 2.55L!the
voltage of the comparator 5pin achieved will be hiaherthan 2.5V of6 pin,the comparator outputs 5V
high level,make PQ39 conduct,pull down MAlNPWON,the system power supply is shut down;at
the same time.the high level comparator output;making P-RI67, PRI63 and PHI be series,thus pull
up the 2 pin voltage of PHI again.This PR167 is
is resistance,the author called it as
"fence resistance",The role is to make the CPU tern
'on value not stay at a point,such
as 90 degrees over temperature protection,50 d
al.
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Figure 5-30
the definition of converter pin
Basic application of tne voltage regulator
[115-31 J1f7J'. U8100 it~1~.ffi~~M:~.ffi~ (LDO), 13M I J]!p~fitrAi#r-g,
• ~ 4 .8#4J~j!(f<JWiJJiltlllH~lIitl~:±Ilt.ffii\!61~, ~~IM!lliR:: 1.24V
0
M 5 JJt4J~6Uili
3 J)kjJ7~;G~Jtn~Jf
rd fg
~~~*~.:±I.~lt~~m~:±Io~:±Iltlli~.~~:
VOUT= VFBx(1 +RS11.vRSI04)
~ shown in figure 5-31,U8100 is low dropout regulator(LDO),which input power supply from
PlD?0mP-ut voltage from 5 pin,two resistances connected by 4 pin control high-low of the output
the reference voltage is 1.24V.3 pin is the open signal of chip,high level opens output and
o
level Stops output.The calculation fonnula of output voltage is: VOUT = VFB x ( 1+RSI14/Rs IO~)
+l2VSUS
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_================================9
the control voltage of chip.YIN is the input voltage.REFEN is partial pressure of + 1.5Y to O.75Y,the
conditions are sati fied.the chip output +O,75YSP from 4 pin.This chip is mainly used for the current
amplification.can provide I.5A current.
+1.5V
----lL/PU~2~1----;~0_Ei..-.......,.--r--{)+3VAL
W
VlN
VCNll.
+-I
,....-----"-1 GND
NC 1-"---+
NC
Figure 5-32
f-L---+
common voltage regulator in memory YTI power supply
:i£1i-*!I'ffi"ffltiffiB 431L, :tmm 5-33 PJT7J', :I: 1.24Y ~\f~ffiB: +3YPCU i!:ct Rl39
IIRifiU§, ~.£rl43IL itl.E~ti:l1.24V l'ro~j1M!ffi (C ~ R it-~, ~!::H1=~ffi=;j:&~ffl).
There is also a commonly used voltage regulator 431 L,as shown in figure 5-33,is the 1.24Y
precision voltage regulator:+3VPCU current limiting through R139,and stable output reference
voltage of 1.24Y through 431 L(C and R connected'together,as a voltage regulator diode).
Figure 5-33
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ABJ/F Yonah/Calistoga BLOCK l
~
c:---J
1= 8881
GEIlK
1CSII54310
Yonah
7
I
I
1ft
1ft
1ft
1ft
478
....1:
L WI.
~ ~
'.- .... I~ .1
L....-_.......-_.......
I
I
_~
BOS
AGTL
l'CI-1I:
~
VGA ..16
: 1.-
~r;J
1_-
1.468V.133H8Z
Calistoga
1466 FCBGA
J7
Figure 6-1
I 'mii.llllllLawWllIIIf ...
DDR2
~
~
'.J.lo,u,n,J
architecture diagram
00~~ttl.~~~m~m~~mOO,M~~U~~1.4m~.5~.~*m~.
CPU JiJT~l¥JmIfii, iiJ\;.J,M. "FiIiil¥J~iIiHfHtAm~, ~OO 6-2 m~.
The figure marked the page where each function module,for example,CPU occupies page 4 and
page 5.Ifyou want to view the page with CPU,you can input the page number in the following page
frame.as shown in figure 6-2.
Figme 6-2
page.input bo
00 6-3 ~ ~ CLK_CPU ~ CLK_cPQ)3CIi.K.• _.. _.7=im~fmf'Fpij~m~.
In the figure 6-3 CLK_CPU and CLK_ Pas the same signal,but to be regarded as two si
Fi~
7tBf!j:((.ji3I.IJI4I~*~r
Jik C26 JlilI((.j i31.IJI4I~f*. ifii P. m
1~ PLT_RST#.
The pin name of COM
same concept,as shown in
signal named by manu
-52-
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Ir
m
6-5 ~ \it .. T83,
~u
Figure 6-5 i the test point T83.for fact r: te ting.
Figure 6-4
PLT_RST# signal diagram
Figure 6-5
circuit symbol diagram of the test point
Mt!.QlJI.s. -ml:ffl.H~ii~. jJf9!j:jpllJiP¥. jtEf!.Jj!jH~%~DOO 6-6 PlT7Fo
Jumper pointlisolation
pointusually
connected
with
tin
directly.con enient
to
the
troubleshooting the circuit symbol shown in figure 6-6.
PJPlI01
~
(8)
Figure 6-6
bl
~004i
: [ili----
POWERPAD 2 0810
cl
PJPGlO
7?-'-
--1....
....UI'
(d)
circuit symbol diagram afthe i alation point
53-
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~Hf l:H7*§J(:if@. ;tbF~$1tj:B:~iWYiIX*R~1&Tlll1.£ff3i~cL NO STUFF l1!.~T~5t
"#:tc~. :f~, 7&~p;r;jftffil~l1;fiJFn~,
*m;t{ 6-1.
* or @ is printed on the device.indicating that the device is not installed in the board of the
current version.NO STUFF also indicates that there is no installation.Not installed,it represents that
both ends are disconnected,as shown in table 6- I
*
r
Table 6-1
Manufacturer
the list of some parts of the motherboard not installed
?rt
~
.q. Symbol
*
R231
@
R3055 1
17tJ Example
'VV'*1KIF 4
i=::li Compal
.!f.1iJi ASUS
2 10KOhm
@
~
IX
OOhm
IX
DY 2 0R2J-2-GP
R2008
tf,QIJ Wistron
1
--....L.-,VV'v-:h.~--1
R194 2
~~ib: Inventec
OPEN
~
.=:R Sumsung
nostuff
~
1JZW; Apple
NOS TUFF
OPEN
nostuff
R1888
NOSlJUFF
2J\1V'l
, . '"9
201
IBM
~Il;~~ftt:f~,
mX/fft~Ifi7f.
01Jn
If the parts are not installed,but can not
connected with a straight line,as show in figt1l!' ~
Figure 6-8
f* -9 j§ lfjj1W "#", "-L" Wt:#
im jffl ~ mJmJ mi.. 11tt!ii!i -a- u #" 101
*11 2231_SHDN#ffi~f£7fm~~
'.Th<*r
1T~.
The signal back with "#"., if -hI'
level.The word of "efficient" needS
front of "#" to understand.As :slid
-54-
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igh level in the boot state,but did not conflict with the expression of "active-low level".
Figure 6-9
active-low level signal circuit diagram
-.lIIt1£lfl-rnJ%}jfitimMI¥J~::j::, *5F~f§-%j2tj~iIjB~m:-li!?J, 1fl.1:E IBM *D Apple r~
IIIt1£lfl, :fzIl1II 6-10 ftTlJ', 7503 ~Jj!Ij*5F~1§-%~t~iU75 m:~tffi1ftii D-3 B~±fu7J, JE1ft:§l!
1mMft, 1JiJ!1l~1f1%o
In the common drawings,the digital followed by signal,indicates the page the signal connected
to,but in the product drawing of IBM and Apple,as shown in figure 6-10, 75D3 and others indicate
lite place that the signal connected to page 75 coordinate position D-3,positioning is more
accurate,it's convenient to find signal.
75D3 21C4 Ie?
em>
CKS05 CPUO P
00 6-10 Apple f"~rt!~~OO
Figure 6-10
screenshot ofApple product circuit
~~, fi~l¥J1JrRJ, Jli*J!~~11lJ%I¥J~rRJ,
:!mOO 6-11 J5!f5F, 1fl.E13TlIDJ~A9:!B~m~~
, ~!t~PJ~1f1o
In addition,the direction of the arrow,represents the trend of the signal,as shown in figure 6bilt due to the randomness of drawing staff,leading to not believe all.
=::8--
-cu<REQJ
-"=m;;;:r;:5M~CH:.:-----ClllID 18.1 N<
--,,-M::.::CH<':":-:S~~:":'= _ _---{]lLWD!lIJ 36.28<
(b)
(a)
Figure 6-11
screenshot of the signal
~)tIf1, .Rfl'ftfJ~HI(;]~lJ'tiliMfI~-~,
:!mill 6-12 Pff/Fo
line is crossed,only the point indicates that the line is connected together.as shown in
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M6 ~ 1t!fl8l!JffiD::~H!!m09f~m
============~~=====4
BlUE I
GREEN I
REO I
'5(11
..
GND
""I
..
R111
:"
'T'
v 1005
R118
:" A tl2tIN
V V 1005
REQ(O)II
REQ(1)1I
RE0/2]11
l ~~:s;-~ REQ(3JII
~~~>q REQ(4)11
"'0\ ~'. v~...
R341 V 1005
~
Figure 6-12
the circuit diagram of cross connected and disconnected
Figure 6-13
the similar signal circuit diagram
The use of common point position figure
1. CASTW--*.Ist
CASTW H:
IBM ~,EfH(.J.~ 1ft III, ~# .~ firIIIl1A tt-J~.~~H: PI I;t ~ ¥Ufi§ -5 B~ 3k ~ffi;Q:: [i3]
IT~~~m-5a~ftm,.~.~a~~mo~."~~m"~m~Btt-J~-OO,
0
&m
PCB B"~rprii]mo 'M'JfH~1'F~tR~~1j!:tm1ll6-14 JiJT~o
I.CASTW-*.Ist
CASTW is the point position figure used by mM,the most outstanding characteristics of this
point position figure is that we can see the actual direction of signal.The red indicates that the signal
is in the current layer,and the yellow indicates that the signal is in the other layer.Here "the other
layer" refers to the other side of PCB,also refers to the middle layer ofBCB.Common operations and
shortcut menu shown in figure 6-14.
-!'i6-
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Figure 6-14
the screenshot of IBM point position figure
2. Test Link--*.brd
IlJl~i!~iii:«rIlX1mzI¥JJtitj::mJ:t~BRO. ~ffl1li'F:tzrrF: ,8 c m~1~5IA~Ht ([EJA;J
~="t:7t1tf.); iii: N .:fU~ffi%; 5(Jl.ttrm.~1r:m:&t*; $*~rlttjf-:t5lt~/J\: ,8 R t~JjJE$!?
'ifiij !i!:m• • ~o Af*.i'FPJ!?J.ilit "Help" ~$:i~. a:~1Il6-15~1Il6-21 B~~;l{d'F
f1JJ:j:l, i!!I!f..1: N .1!f~l¥Jffi%:l: "+1.5V" ~1-Jtlli. Jtlli-ill.-lJtfm~-1'-f§-'% (~~
PH&)o
2. TestLink-*.brd
!he point postion figure ofLandrex corresponds to the file fonnat of BRO.Common operations
below:click C key to find components(a1so supports three components);click N key to find
.aouble-click the left mouse button to enlarge;click the right mouse button to shrink;cl ick R
tale the screen;click the space key to page.The specific operation can be viewed through
It ofe!the operation example of figure 6-15-figure 6-21,the signal found by clicking N
ol~eNoltage is also regard as a signal(or network).
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Figure 6-15
the operation drawing I of Landrex point position figure
Figure 6-16
the operation drawing 2 of Landrex point position figure
58-
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Figure 6-17
the operation drawing 3 of Landrex point position figure
Figure 6-18
the operation drawing 4 of Landrex point position figure
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Figure 6-19
the operation drawing 5 of Landrex point position figure
00 6-20
Figure 6-20
~JlfilgUlII1l1!k1'F1Il6
the operation drawing 6 of Landrex point position figure
hO
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Figure 6-21
the operation drawing 7 of Landrex point position figure
00 6-22
~Jjf.p~:tOO 8
1-1itml¥J~!!id1=;ij!:: ~W~tl:lJJA\1¥ PrN JJA\~, PJ~X1mtBfftOO, lt~IW~JJ:!;. PIN fffi~tl' PIN, 19J~
@/F~JHI'o
When we click to select the pin of components,the name of signal will be shown in the below
status bar,as shown in figure 6-22.A common operation is:when the welding plate appear the
phenomenon of PIN dropping,we can refer to the point position figure,to check which PIN need to
fill PIN and which don't need to fill.
Figure 6-22 the schematic diagram 8 of empty pin
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3. Bmlrdvic,,- *.hl'd \ whdv, *bv
l30ardview .','.d 1/ 1"1 !t}'f'1 )IJ J II I ilJ (.f'l' I j~ BoardVic\ R4,
Y... 1'1 ~?r J ~ *.brd )
¥)( (f'i 1J'
HoardView, ~ i'l ~i'lJ\.i .\)(Iv), ?1i1~ (WI j'. BoareiViewl.3. xi'I ~:f'l.r~*.bv) '~~ Ii] (I(J ltf'l
/J(J
'( he software or 13 ardview point po ilion ligun: is used in the file or 1110 "lI(program
BoardViewR4,the file r, nnat is *.brel)
Iiong Ilan(program BoardVicw.the file fonnat is *.bel\).
Wei Yang(pro 'ram BoardVicw 1.3,lhe file formal is *.bv) and othcr company.
~1111J BoardvicwR4 11~1'.<.111111~16 23 J91/J '
m "N"o
fuLl'I ){Hd)~~kHt "D
The 'crcen hot ofTuo Fu BiardviewR4 shown in figure 6-23,pre
u
,
fHI',"J){Hd)dl~
the shol1cut kcy "D" to find
the camp nents,pre s the shortcut key "N" to find thc signal.
Figure 6-23
the interface map ofTuo Fu point position figure
jJijy,X 130ardView 1t.lU¥l~nl¥l 6-24 rfr~,
tit "'-:."
The scrcenshot of Hong Han shown in figure 6-24 press the shortcut key "0" to finel the
component .press the shortcut key "E" to find the signal.
>2
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Figure 6-24
the interface map of Hong Han point position figure
The screenshot of Wei Yang BView).3 shown in figure 6-25,press the shortcut key "C" to find
the components,press the shortcut key "E" to find the signal.
--------------_
~=_~_
Figure 6-25
TDP
. , . :..~-:
the interface map of Wei Yang point position figure
4. TSICT--* .asc
TSICT ~flf:-~~$ijif£~ffl. ttJHg~ff] ~ffl~ft:~Il"F
TSICT software is generally used by ASUS,Gigabyte also uses it.The common operations are
0
0
as below.
lIt* "m~" ~.;hll~)(flf:. BaM ff!9='flr-J~~~9='. N-1JiTt OK ti<ffi. ~DI*I 6-26
ffi7J\
D
Click the "models" menu to load the file,if there are contents in the BaM box,selected it,then
-63
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~ 6 ~ EI!:mmIllD::.=tfUm09~m
_~~=======================~~~~=;;'~~=======1
==_.-"'"
click the OK button.as shown in figure 6-26.
eo"
~
~e·.8OM
~"'_.'
Figure 6-26
~
iii I
CANQ:Lj
the schematic map ofTSICT point position figure opening files
N J2 rifJ((.J~UtrA*tg~A~1tj:fi-%, ~tUHj:: !f!m "TOP" fO "Bottom" :i2i;~.:l:JJiB<:JiE
&. Inl . ~III!fl 6-27 fff7f-;
0
Input the device label in the input box on the left bottom,to find the device;c1ick "TOP" and
"Bottom" to select the positive and negative side of the motherboard,as show in figure 6-27.
Figure 6-27
the interface ofTSICT point position figure finding the device
~t-m.t/j;Wragf~:J:, JA1:lut~.~~ "~*Uitft;& PAD" iiJ~UU§)!F.L tlllOO 6-28
rrr;j<
0
The mouse will be stopped on the device select "~Ia~
connected point from the context menu as shown in ~
8
-().\-
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Figure 6-28
the operation example of ASUS point position figure
Click the right key in the blank position,and click Net query,you can find the signal,as shown in
figure 6-29.
_ _. i a : ~ _. . . . .a
"I
Figure 6-29
ASUS point position figure finding the signal
If you move the bitmap,and can not find,You can click AUTO to automatically retUnl to the
initial state as shown in figure 6-30.
.
.-'~I'"
.
: '-" '-c=
•
I
"
~, ,
1 ;~
-.
Top r IoU.
Figure 6-30
oJ.
.
~
,""
LI.l
_
,
~
I
•
__
'
,
,
-
911 aJI Auto I
the position map ofAUTO key
-65-
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m7 ~ EE JIlD BIOS nm
Chapter seven
The introduction ofEC and BIOS
EC (Embedded Controller it A A-h: iii') ~) Jt -1' 16 {.i if. ~ *Jt... it Jt;S ;e..$- ~ nit
I
~8A#~~.~, £~~~EC~~m. ~~~l~~.$-~~~.~~A~.~-~
I~I!~j1Jo
EC(Embedded Controller) is a 16 bits single chip microcomputer. which is featured in laptop.it is becau e of the
use of EC.reflecting an important difference bet\yeen laptop and desktop.
a ~ A. ttJlii ~, iltJt*" A\.#Jt8..:i. -t ffd~l-~~. --Ati]iii PS/2 A USB -* 0 ~ l-*Jt.. ~
~~-*o ~4~~$ttJlii~. ~l~~t.~m~. ~~~~m~I.Jt(~~~~~·
it) *0 ~ .i..6\# ("*" ~;Ji~4., 4rs .p..#~~ -t ~ .i. A\.~;j;iiA}) ~ ttk. ;e.$ ~J1it '.t ~{- n 99 i'l!
JttHHi. ~;e.$ttJlii€f.J~mECJ1.~A4:tli!~.lJJ~L
0
In desktop.the keyboard and the mouse are independent of the system hostis generally connected with the host
system by PS/2 or USB interface.But in the laptop,in order to achieve the purpose of portability.it's necessary to use
the built-in keyboard(matrix decoding keyboard) and the built-in mouse(such as the touehpad, traekpoint are built-in
mouse deviee).So the laptop needs a special keyboard controller,the special EC of the laptop is equipped with this
feature.
~A, ~~.$-tt~t#€f.J-+.t~"~~a~~«.~L.*tt, ~.tt~€f.J~~~
h, a~.~*€f.J.A~~, ~~~.C~.~".~, ~~~
~4~~~UR.~
~#ok.~$tt~€f.J-~tt~~~,.~~~~.~A*~~*~~A., *.tt~~~~tt
h~4,.Rtt~€f.Jtth.~,£~~~., ~~-4~m"*.8., i!~t~€f.J~R.
••
ltliJ EC
*'
~A"
0
In faclEC of the laptop is an
function of KBC and embedded control,
EC m;iff t-i!& m~Jl."
.i.iJiJt, til.ti~ (TOUCHPAD
.tf.k.;e.$ ttJlii"{:t.~ ""t'.~
-66-
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m7 ~ EC IIID BI05 fl!3
built-in keyboard. touchpad. laptop battery intelligent charging and discharging management and tcmpcrature
monitoring and others.EC plays an important role in design of portable. intelligent. personalizcd of the laptop.
Be fI;J-4tt.$.:t~~-~~~lr.JFlash *-ft-1it EC 6~1V~o EC {t;f.rA.tf'6~.tl!!.1.ir~/G;.t-TJtJ
:f~~. ,(f. ~ ~ ~ ~ ii« tf, EC 4£'iM:tr reo *- ~ ~t ~ ~1t -;- 6~ at,lf. 1.f. ~ iL.$. rtJJit tf', EC:>t
*'
0
-i.*.~, ~~~,(f.*,~i£Jl~.AJt.~J;.~,
f.i~f~e.rtitl!.;foi!?JC.g 1L~,irf~
0
EC interior has a certain capacity of Flash to store the EC code.The position of EC in the system is not next to
the North and South Bridge,in the process of open system.EC control the timing sequence of most of important
signal.In laptop,no matter in the boot or shutdown state.EC is always open,unless the battery and adapter completely
removed.
4*~a~T.
E -• • #~~, *~.#mi~ff~n~o ~{tff~g, EC
~.~~_*~~~. ~rta*~~aA • • ~., ~£~~.;f.~~#~.~~
...atr.
In the shutdown state,EC has kept running,and waiting for the user's boot information.And after the boot.EC
continue to control the keyboard controller. charging indicator light and fan and other device.and even control the
system standby. sleep and other state.
BIOS ,{.~~ "Basic Input Output System" lr.Jtlll~, 1i:itjj:*"J§ tf' ~.t>ft:Y.t:>t "£.$.~;fit
Nfilit ~ tot". Jt.~, 't ~ -mIil1tJ'Jit .n.;JJt.J*.J .i.;M...!:.-.Ij'- ROM ~ J4 J:. 69 >f1.,If. , {*-ft-::t it
~~.~~lr.J.l..$.*A/* tl: ~~Jt.. ~Htit.l.1t ,to ff~Jt.J§ ~ #t>f1.,If.;fo,~ ~jdJ ra #J>f1.,If.,
.*~~~*
•••••tf
B 0S 1!i .$.,t.;fBIiI1t4 ROM
0S.
AA~ . • A.~~*~I~4£~.«~~.~:>t,~~
~~Jf., 1£tft-ftttf -.~PJ ·tM·ti>ft'9'- I!Ht 1 >f1.Jf.~ ROM ~ J:\
BIOS is the abbreviation of "Basic Input Output System" in English,and the Chinese name is "basic input/output
" after literal translation.In fact,it is a group of program curing to a ROM chip on the computer
holds the most important basic input/output program. the system settings information. self-check
after booting and the system self-triggered program of the computer,it's main function is to provide the
cl and the most direct hardware setup and control for the computer.
d ~no1Cd tlJat,a1though the BIOS is referred to the program curing in the ROM,but in maintenance.we
the ROM c~ curing the program as BIOS.
EC~BIOS ~4hIll.
:k~L~*J~~ ~ EC, IJ,{f.J*~;fJ~~ f.J BIOS.
hysical map of Be and BIOS a large square chip is EC,a small rectangle chip is BIOS.
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00 7-)
Figure 7-1
EC ~ BIOS ~!lm00
the physical map ofEC and BIOS
The working conditions and functions of Ee
l.The basic working condition ofEC
(I)
ffl.tJl:fJteg: EC tr-J#J~l:~J:I!, ~*iI#;I! VCCO, AVCC, VCCA~, &fx: EC B~*f
*Jl:fj~eg~ VBAT.
(1 )Standby power supply:the name of E
VCCA,etc,a small number ofEC standby PQw
(2) fflmnt~: !?Amril~~~~.3!1.7.
(2)Standby lock:it's usually an exterli81
(3)
fflfJUHft: EC .*f!fia<J~
\
~, SMSC H8S tr-J~ {ft;l! RES·.
(3)Standby reset:the most beginm
WRST#, VCC_POR# etc.the rese 0
(4) N~: EC
lIJ!.tltlflttn
I*J $, tE.iJJ~~f*1ff£EC rWti9
(4)Program:EC need to g
work.The program may be sto
2. EC ~~mil.MJ~
-68-
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tx
.~~;-fQ3:e ~iIl.r*ffl·I~ P
a.
(Low Pin ount, (L(;)J14J Fr i I
~HQli J
'.'~~connects lwj'th
outh Bridg by LPC(Low Pin ounl) bus.
'~V~GC3: LPC .~t:lta~'fitf\!, 3.3V"
po rsupply ofLPC bu .3.3Y.
CL : LPCCLOCK~LPCJ.)JfmW(J~ Mllz)t]j!,~~, 1.6V Jdiu
LPGCLK:LPC CLOCK provides 33MHz frequency (or LP ,about I. V.
LRBSET#: LPC ~
I
{ftffi~, 3.3V"
E1W:LPC reset signal3.3V.
UPC_AD[O:3]: !'lh!ll:ft~J:~tIG, i!lru I {§S-JI1~E('HIN LP 1'i~~.{t'JIl!.J'Ii:;rIl'i&·JJ,li"
-.-tT·.Pt' _AD[O:3]:address data complex line,these four signal are used to tran mit the addrcs and data
.i;'l~·bus.
LPC_FRAME#: LPC I¥.J)i!jJMm~, ~i!l'{§·liHoJ~n'J, jl1~Jl~flJ1.'.Wj),j~- I LP N~JUJ.
LPC_FRAME#:the cycle frame ofLPC,when this signal is active.indicates the tal1 or end of a y Ie
.EC controls LCD backlight
ID_SW#: ~i6t7f~. LID_SW#ffiW1-f1=ffl: ~f}VIJC~rl1tf~"'%m r EC Jljltrr~:r1IIJl2J.
. 7fmJS~1~JIt1B~iiJ~~rij1rJlG. J.W.tE)!1it~ffl ~7Cftj: (l!!t!.~1l'Z ~fljIJJ1t1i'1 \}.
**)
_SW#:1id-close s1witch.There are two functions of LlD_SW#:in shutdown stote.this signal
forEC to determine whether it can tum on'pull down this signal after starting up,which can
off-the backlighlNow commonly using the Hall element(magnetic sensor) to control this signal.
Jl)jBACKOFF:
lfJlG¥-t$tJ.
_BACKOFF:backlight control
Li_PWM: Mi.'1"W.
_ _PWM:brightness control
il?t1f~tlCJH
lrM:me battery charging
,~~~~~~B~~$
~~~~f\!~~tr~f\!,
~~~B
:t:1\iJII jql.~~D.
O.
:i is determihed that the battery has been damaged,will
battery lDay cause safety problems,such as
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hen the battery voltage is I wer than the di charge end voltage(3V) and greater than
0.9 .with I 10 urrent of the constant current charging current to charge with small current.and the
horLgenerally for a few minutes.If you use a large current to charge the battery with full
time i
di charge.it will damage the battery.
(_) ti!~m."fE ~
(2) Constant current charging
~it!!.~ffi.*T-;E~1iJ§, :j$j.U1Al§:1iit1trl!, iJ:}~Ufdf!¥m:o E\!¥l!!.(I~:kgMHj~:u.1: (80%) 1£
~-~ IRf~ff, IJ1f8]~*o 1t~~iiit-hl(:fd~i~'JtEiff~(J~ffiL i:.t*~mlll~1tFI:I.~$, 1tifiiJ)§rl~
~
~~.
When the battery voltage is greater than a certain threshold.it will be the constant current
charging.and the feature is constant current.Most of the energy of the battery(80%) is stored at this stage
for a long time.The charge current is generally controlled at an appropriate value,if the value is too
large.which will affect the charging efficiency.and the capacity will be reduced after full.
(3)mlli1t~
Constant voltage charging
~7t!!. Jt!.ffi.~iU1t ~(fl~ 7 E@.ffiJJ;j"jitA mlli1E ~, !M' I.U~. ~¥l!!. ~ffi f~H~t[[~
When the battery voltage reaches the end voltage of the charging.the battery is charged with
(3)
0
constant voltage,and the feature is that the battery voltage is kept constant.
1E~Jt!.mt~i$T$.~l-'J • E@.iitt/J'T 1110 m:mt1t~~mtll;j", IlTI»- iA~1E~~*o It¥m?§:I:~$j.
ft~m-iU~~ ft..
The charging current is gradually smaller.When the current is less than 1/10 of constant current
charging currenlcharging end.The battery c:apagi~will be fully replenished.
(4) ~mt1E~
Trickle charge
:!t:Ft!Ft!mE'J'T 1/10 m:mL1trt-flJIID
(4)
~~mL1tE@., ~.ra~~rm~lI
t!!;Eo
When the charging current is less
charging current is close to 0 which
con tant.
The purpose is to supplemen
lithium battery is usually 50/0-
How to judge whether E
EC ~jG.6l-g~-&
ROM. 1lT~fi-fif£~ti
*~*N~
1iJ!?J-ttJijJ
EC needs the pro
-70-
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tG 7!T!
EC IftU BIOS 11ill
d in its internal ROM,also may be stored in the motherboard BIOS.lfthc EC comes with the
program h n doing maintenance,you must find the same motherboard to disassemble.lf EC not
t
com s
com
ith the program,you can find the same type of chip to replace. How to judge whether EC
ith the program?
1t;t~~~~, ~iIii~~~, 1Jic.-50~ EC -f~m EI ?tH~ffo I!I 7-1 J:1:1j'I~ EC /F;IIH1ff:,
III 7-21fl~ EC 13*~~o
First,observe the appearance,EC with stickers, marked on the sUiface is usually bring their
own procedures.EC in the figure 7-1 not comes with the program,and EC in the figure 7-2 comes
with the program.
Figure 7-2
;)t~~~f4,
fffjj\
EC comes with the program
~numiIiiJ:.fl~1~Jtl~m~J:j:l,
EC ~ll BIOS fflrn;rllj1ft~7J~, YOOO 7-3
0
Second,observe the architecture,in machines can be repaired on the current market,there are
four kinds ofconnection ways for EC and BIOS,as shown in figure 7-3.
I~~~
~
~
(b) SPI
(d) SPI
(c) SPI
117-3 EC ~ BIOS 1't-J~~1Il
FjgJ,Ue 7-3
the relational graph ofEC and BIOS
-~1J ~ SPI Ji~~~ Be,
f'!fr5 EC ilM LPC ~jtl~m, -Ai3!
~, -tEit;l!~ BIOS ~m-1'~ Jt 0
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M7 ~
E[ IIlD BIOS
nm
s .~ SCSI -F~-@~~JJJ~el¥JJr-iID-Filif-I§ c.o~ B]OS. 19~PD, ~-F Loti 8]OS
~SB-F~±:*z.fBJ(J{Jim1§.@!~BtlJ8Z9J~f~FlllEflij~HOD 8IOS *~PX:. {£3Hn:ctHI
~, $Jt BIOS ~~m*fA.ff~@5"~j]OB~BlOS EJ~l~~, ~,*M~®~1!:j::B0~)]~€i1tIfFo IEl
rii.~.:h*iJt:, q~1~m"iJJI»-f-IEI c.B~ BlOSo fEb~ B]OS :i\g;Q{Jt65IL /G1£!~Jfr1]DJJX:
l!~U*~M:(J{JfOJJm, ~l1t, -J.RJ~:1EB1;Fi1£1tEJ~~_iIJ~-fr:(£±t.& BIOS pg, MTJJ~
~:r8?ff(J{J1&., ::t1»-5"~1Jo BIOS I¥J~At:I:ll.mo ~®~~Wi&1:~L(j~ BlOS ili~lJ:t:flXl¥J BIOS
~lHD Flash ROM 11: BIOS ROM ~J:t, lEJ~ili"iJJI~A7J1fB~3l~, l2J,fl~~Jtff}R~f.3.&~5.ffi
*
-n,
~*~fto
In addition to the motherboard,on the other device,such as network card, graphics card,
M9E>EM.. digital camera, hard disk and so on,are also have the so-called BIOS,some SCSI cards
iiiid some interface cards with special function also have its own BIOS.For example,BlOS on the
:graphics card is used to complete the communication between the graphics card and the
otlietbOard.The start and using of the hard disk also needs HOD 8]OS to complete.ln the process
2ni:1ie bOOt,the motherboard BIOS will call and execute these additional 8IOS program to complete
initialization ofthese hardware.So theoretically speaking,each kind of hardware can have its own
B 0S ut too many BIOS,it will not only increase the cost,and will lead to compatibility
oD ems,therefore,in general,integrated the standardized device in the motherboard for those unique
ifieation of manufacturers,appears with the form of additional BlOS.These BlOS on the external
motherboard BIOS using Flash ROM as BIOS ROM chip,also easy to upgrade.to modify its
erectS: and enhance its compatibility.
CST J:tt~t&: .m~i!It~J§, ~tJftt$tE13 POST (Power On Self Test, LJ:E!.E1
~p.g.~1-li4:i1HTt&:ft.
i!1it5G~(J{J POST E1~-E!1J5M CPU, 640KB ~*pg
..
~L~~M~~ ROM . . CMOS~~$ . .
a~~~~~~~.,
$*Q . . H-F,~@!~T*m.&m~ill
~tJf~~ilim~ffi~~~m.~.
wet on selftest:afl:er the computer power-on,POST(power On Self Test) program
.ee- ~ the system.Usually complete POST includes to test CPU, 640KB basic
~~l~ of extended memory...
ROM... CMOS memory, serial and parallel,
am dis and keyboard,once found the problem during self test,the system
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operating system boot record,then give the system control power to the boot record,and completed
the sequence boot of the system by the boot record.
(3)
'lllifrJJ[i %-t~Jj~: fJl fi:$Hlc3::t&@!1*4J 11YT-50~7H'co
(3)lnterrupt service routine:responsible for the allocation of the motherboard hardware interrupt
number assigned.
(4) l~J¥i5[J1: m7ftJLJ§illA CMOS i&B.
(4)Program settings:refers to enter the CMOS settings after booting.
2. BIOS ~:l:iR~IJ
2.BIOS capacity identification
19t1~o, ~-'%T:J SST 39VF040, ffrlillJt:lW~J§-=-fft~*/f'IPJ, 1~*~:!i/f'1PJ·
For
example.the
model
of SST 39VF040,
three
digits
with
underlined
are
di ffcrent,representing different capacity.
001/010/100: IM=12SKB
001/010/100: IM=12SKB
002/020/200: 2Mb=256KB
002/020/200: 2Mb=256KB
004/040/400: 4Mb=512KB
004/040/400: 4Mb=512KB
OOS/OSO/SOO: SM=lMB
008/080/800: SM=lMB
160: 16Mb=2MB
160: 16Mb=2MB
320: 32Mb=4MB
320: 32Mb=4MB
640: 64Mb=SMB
640: 64Mb=8MB
11: Sb (1ft) = 1B (*li)
Note:8b(bit)= 1B(byte)
3. BIOS ~~3"=1f~Jt
3.The package type ofBI05
BIOS IY-JM!lt~;ct~fli~fIJ, A1*1lft
There are many kinds of BIOS ~
(I) TSOP48
TSOP48 M~~ BIOS ~
(I)TSOP48
BIOS with TSOP48 pao
7-4.
-74-
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M7 ~
00 7-4
Figure 7-4
E[ ffiD BIOS flffi
TSOP481i1ti(19 BIOS
BIOS with TSOP48 package
slJ4J~)(mIll7-5 1WlFo
The definition of pin shown in figure 7-5.
8M TSOP
30
FAI
30 FA2i IIADDAO
FOO
FD1
FD2
FD3
FD4
30 FMlPPEN
30 FA5IIMlM
30
FAll
30
FA7
30
FAa
30
FIl.I
30
FAIO
30
FAll
30
FA12
30
FAl3
30
FAU
30
FAl5
30
FAll
30
FAl7
30
FAI.
30
FAIt
F05
FOG
FD7
AO-AI8. Utli DO-DIS, Uill CEIl,
30
30
:lO
30
:lO
3D
30
30
Jtilt vcc, fM!.3.3V
OEII• • UH!fm WEll. !ifCilF RESET#. Jlfit VSS, f t
00 7-5
:A18:the address line
TSOP48 M~I'JIJ BIOS ~llJ/.lIlEx
DO-DI5:the data line
WE#:write enable
CE#:Chip select VCC:power supply
RESET#:reset
VSS:ground connection
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I' 7 6 T. 01'40 JHH(.J 1310S ·-:t~~l¥l
L.::..:.....:.:.::~~f.i. ~~2~. eE'
[ \\U,
11:"
r
Vwl •
9 Of'
_ _- - - W.
~----~
1117 7 T
'STMICIO
TSOP40
O·
P40 :J,';t~(t1 X-BUS .({J.t!G BIOS i;IJI/~ig X.
(2)'1 sor40
BIOS with T OP40 packa ear g n rally X-BU bus the material object shown in figure 76.i1lld the dcfiniti n of pin hown in figure 7-7.
Fi 'life 7-6
th materialobj ct f 1 with 0 40 pac e
(. i 'ure 7-7
the definiti n ofX- U
in with OP40
(3) '( SOP32
TSOP 2 lH1t~ BI
alii I 7 8
mIJ •
0 40 *!iW-. JJl4Jift~.x.
7ti
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1117-8 T 01'32 J'J;~~ x-nus .'~fJG 1310S 'JllJJ.ll'ilX
ofp
o with TSOP32 are generally X-BUS bus,pin runction is similar to TSOP40.the definition
wn in figure 7-8.
Figure 7-8
the definition of X-BUS BIOS pin with TSOP32 package
(4) PLCC32
eC32 ti~(f(J BIOS f£~ic.*rt!.n®epillil~··l!!.M X-BUS .~,~JL 'JI})l.il/E)(.!mI¥l7-9 rfr/J;,
~:tmm 7-10 iff'J'.
•••
•••
•••
-
.
'.~
.(
SIll
39VF040
70-4C-NHE
060710B-L
•
•
••
••
•
I
-.-,..,..,.,..~
8#: Jt~ OE#: i!l±lft-vt: (i!~)' WE#: ~ftitF
vcc: {jtEl!JJ!lJ
GND: :I:l!! AO-AI7: :I:l!!!.JI:m%~ DO-D7: ~i1M~-%~
1l,..:{J
PLCC32 ti~(f(J X-BUS .~~ BIOS i3IJJ14I~5(
00 7-10
PLCC32 t-t~ BIOS ~
power supply pin
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+3VAlW
I
U20
Ee sPies" F5Elil
SPI WP#
SPI HOLDp
vee
es#
5ClK
WP#
51
HOlD#
50
GND
MX25L512AMC-12G_508
~
EC SPIClK
EC so SPI 51
I::l 51 SPI SC
CS&: J.i~
so: tjJtd;:;l}~:±l WP#: :Lj!~tf' GND: J:t!l
51: I.\Jrr!i'i ~~ijA
ClK: I.\JtfRt# HOLD: fil' vcc: f:ttEl:t.
~ 7-11
~ 7-12
SPI .~,~ BIOS 5IntlJ):£)(
SPI .~,tlG BIOS ~!/PJ~
(S)SOP8
BIOS with 8 pin are SPI bus.the definition of pin shown in figure 7-] ],the material object
shown in figure 7- I 2.
CS#:chip select SO:serial signal output
signal input
SCLK:serial clock
Figure 7-1 I
Figure 7-12
(6)
HOLD:pause
WP#:write protection
GND:ground
SI:seriai
VCC: power supply
the definition ofSPI bus BIOS pin
the material object ofSPI bus BIOS
SOPI6
IBM X200 mm BIOS $7HJl.~!B1E:ma<J~ 16 JJW SPI .~~, i31ij!pJE;X.~f]OO 7-13 Jiffffi. ~
~mW1r~ 7-14 JifTlFo
00 7-13
i3111#415E;x'!§i 811#41 SPI ~i!;J.. NC ;Jg~lI#4Io
SPr.~~ 16 JJIIJ BIOS ij
(6)SOPI6
BIOS used by IBM X200 ~
figure 7-13 the material object sIlO
is Not Connected.
Figure 7-13
the definition Of
Figure 7-14
the material oljj
-78-
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m7 ~ EC WiD 810S flffi
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~~+~~~~~~$#A~, ~1~.-~~£~~~*, ~~~~~~~~~~~
~~U.~~$~~#*~~~$#~~~~~£~~lM. ~~~~*~~~~~~~~
#J ~;fl;fo Intel ~;f.;ii ot Jt.
Chapter 8
The basic working process of notebook computer
As a professional notebook computer maintenance personnel,in addition to have a certain basic
knowledge,also need to understand the working process and Intel chipset standard timing of the
laptop and other maintenance theories knowledge.This chapter focuses on the boot process and Intel
standard timing.
8.1
The general boot process of notebook computer
~-iG* rt!/mi1¥J I i'F~~ilM-~I¥Jp;j Ji! (Sequence). :{£~-iG*rt!/mia~$f~ ~ rp, Rt q
$iJ&·tff{5rFI¥JJfZJ:IHi:::{£~~7fmJ:.ft!1l\{;t, m~-mp4i'F Power Sequence, :±~mt~ffi-tk:~
-iG*rt!/mi:±tN..JA~mtt~JIJ CPU ~~ RESET -m~z.ra]~~:±tN.JiJifitl¥J.:rfHff. n~i,..JA*oo I:
*:W, ll1~mt~p;jra]~III9i~o ~~J>\fto~jlJJ:.ft!, NJIJ CPU Ii'F, )!z.fa]:{£~1fJI¥J~~L
R ~ 1~~ I¥J at fa] , JL .If~;l!-f!PoJIIl1i:~tm :If, i§;l!:(£~tli I¥JI i'F1:, )!- f!P~ I¥J at fa] I*J ~
:&~1~$I¥J$'tff, .JAffl:mft!ffi;tz:~, jiJ
~~ffi.®~:±tN.~lli*fl<J~~~~~,
@tJ7m{Utttfl¥JJ1~9J, ~-1'-~.:fIl:i~
®~~1'-tJ7~z.~W~~.F~~p;j
~.; JJ~~~I&7f~fl<J-m~, NJIj:&lli~~I
~~~~~~~~fl<J -m~;l!~,:{£~
-1'-~.R;If'~7fMi~.
~ PWRGD-m~I¥J;tz:
~, Jl:Jt~*.e-JE&rt!ffi~~ Sms ~~2fflj
The working process of the l~
cases,timing applied on the power-on
refers to a laptop motherboard
literally,timing is time and ~
work,we feel just a short time is
lot of things in a seco~frii
motherboard received the swi
made so much action,it will
steps,if the first step isn t
requirements between eac
-80-
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generation requires that each voltage stabilize about 5ms will be sent.
JA:J:ifiil¥J1l"iB, 1iJl;A~:±I, n~'ffx1T-~3::ffB~lE1tI 11=f=j ~~ i.:t:~(J~~)(, ~1t]A!,
~.J:. Et! ~*m~i!iX~" mfO lit ff: fi ~Mn'l~B~~
IJJ ~ iJ'L ~~Ji 7 at ff: , x1~ i(l.*= EE!.JJili
~&~~
~~7-~~*~m~~~o
*
0
••
From the above introduction,we can see that the timing has vel}' important significance for the
notrtiaIJ working of a motherboard,the most common fault.such as no electricitY,no boot and
~1here have an important relationship with the timing.!t can be said that if you master the
~1hen you have a basic idea of maintenance for all kinds offaults of the laptop.
Hard starting process and Intel chipset standard timing
U~i~UI hard starting process
B-ut, Intel~Jtt.ll (4~9tl~~) (f.]~i(l.*=egOOi7fmi1f¥~Dr:
lh pneral,the boot process ofthe laptop with Intel chipset(below series 4) is as follows:
(D ~ ti ~ {f fRJ ft:J It!;h 1i ~ ~ It!l!'J 02: It! rtk fO eg ¥1ljD, Jill i1 3V B~ ~1l.10 eg ¥tB
*f= ~
ff'€ ~ta'MfJj:ft:J RTC It!i!, l;Af~H~~$lI1f8](f.]ili{ff01*ffCMOS {§,~'O
ttbOut any electrical equipment supply power (no battery and no power),through 3V button
produce VCCRTC to supply RTC circuit of the South bridge.to keep the operation of the
time and save the CMOS information.
~Llt!~~~~E~~,~~0~~o
pI~ng in the battery or adapter,produce the common point.
_f'=~ EC ft:J~m~1t!. (-~R!~tElt!.ffiJ, t£%'.fJi..fiteglE1t)§, EC ~g-lfErl1~fjl:eg
mlt-t"', ftm~lt!.glJi.tr=~ EC ~fft, EC ~~~ffl§Cti'.E15J'IJ!IJ{iL (BIOS J:tm~
- .,m"J ).
uce the EC standby power supply(usually linear voltage),after the standby power
!tEe supply power to crystal oscillator to produce the Be standby c1ock.the standby
delay produce EC reset,EC reads the program configuration own pin(BIOS chip select
mvn in figure 8-1).
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~
1':" ,
t
t
~
CHTIOOV
Figure 8- I
BIOS chip select wavefonn
® iJo* EC ~~~¥tllt!.~~re;g, ~EIi;IJ1it1±l{"§.!%1fjgWifftB"J~:fJl{~1t!. (VCCSUS3_3.
V5REF_SUS), ~15~ RSMRST#{"§-'%1it~Wi:fjfJm~Wi:fjf~m~ffiiE~;:t/O* EC :f~j~~:f¥tl~
wc.;g (It!.i'I!!m~ ), EC $~1&¥tl1f~fA!I!1it {"§.!% 15, ;t ~~ 1f jg Wi:fjf~m1ft It!., !J. T.i ~ Ft! j]
0
If EC detected the power adapter,it will automatically send a signal to open the standby power
supply of the South bridge(VCCSUS3_3,V5REF_SUS),and send RSMRST# signal to the South
bridge to notice the South bridge that the standby voltage is nonnal;if EC is not detected the
adapter(battety mode),EC need to receive the switch trigger signal,then will open the South bridge
standby power supply,to save power.
@ ~ ~ 1f ~, EC 1&JtJ3f~ffl~ 15,
~It-.t 1it~ -1' j@j -{~- j@j B~ 3fm f"§ -'%~ Wi ffi
PWRBTN#j]l:Jlo
Press the switch,after EC receiving the switch signal,delayed send a high-low-high boot signal
to the South bridge PWRBTN# pin.
® Wi:fjf B~ ffl: tTL ~{lj: iE 'ilt J3.1lkJlJ
SLP_S3#{"§.!%
After the standby condition of
0
receiving PWRBTN#
signal,raising SLP_S5#,8LP_84# 8r:,P,,-
CD SLP_S5#Wt SLP_S4#~$tJr;
(VCCP). ~!llft~-F~I:\!~ (1f~S
m~Et!, ,~~~Et!
Be ~¥.l*tl)o
SLP_S5# or SLP_84# control
SLP S3#
control the production of the brid~
hies
power supply etc(some is controll
sending to EC).
@ EC ~lt-.tttl:I:H~%
mB"J I:\!ffi e.~~$3f ~
0
EC delay send signal
voltage of the machine has
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® CPU f:Jt1t!.:iE'i'itJ5, CPU Eg¥J,jj!~lj1:.~JtJj:I±\ PG mc~J!;tF(HfI: VRMPWRGD )jl;JJo
Ret CPU power supply being normal,CPU power management chip send PG to the South
.~ :v:RMPWRGD pin at last.
@) CPU f:Jt1t!.:iE1it J5, imii tt~~~~7f JEl f1~'~rp;C'.~Jt,
tz:~.e-~ilnt~111
0
After CPU power supply being nonnal,open the clock chip through the conversion circuit,then
produce :various clock.
@ l~UJfi&!JJ 7 f:Jt It!. ,
B1~, VRMPWRGD, #4~iU EC Ql(;{jt ItJ. ~~il}if Dt~~* 01
PWROK, jiijM~1±I CPUPWRGD *iffi;;u CPU t:;81~'C.\ltJ.ffiB;2JJX:r}J7fJEl, #fi'DatLitlli
P-.LTRST#~ PCIRST#ffi~.
$he South bridge received the power supply.clock,VRMPWRGD and received EC or power
ply circuit delay conversion PWROK,the South bridge will send CPUPWRGD to infonn CPU
lbit om core voltage has been successfully opened and send PLTRST# and PCIRST# signal at the
emme.
@ ::f~~i&¥tlPLTRST#J5, 1tCPURST#{§-5~E'CPU, CPU iE:r.t7fPi=lIfFo
~ the North bridge receiving PLTRST#,send CPURST# signal to CPU,then CPU officially
work.
!UUJ!W!J6 z;fjMN, ?£@J6 z;fjii~ 9=J, ft{fJilJ ~1E~ i2* ItJ.JMi 8%)± 1tJ.0-:tJ 4 1- miJ\
0
e above is the hard start process,in the process of hard start,we can divide the power supply
laptop into 4 levels.
1~ 63 It!.: Ii§d• ..tIt!.~B1;a:~l¥.Jttffi, -~~~tt~7f~~ EC, M11it~~jH11J:r.ttz:~
wer:vol1age generated just plug the power,generally supply to power switch and EC,is usually
linear way.
S5 It!.: iiml¥.J*mIt!ffi, ~~mml¥.J VCCSUS3_3, ~·fJ1.:1*~r01E€., iffi1t~
~~l¥J.
wer:the standby voltage of the South bridge,supply to VCCSUS3 _3 of the South
in the state ofpower offis usually produced by PWM way.
@: P36l¥J~Jt!, S311i~~~"fI¥.JIt!.
epower supply of the memory,the power in the state ofS3 sleeping.
°
M:iE1itjiffll~I¥.J±~Jt!,
1Bn4 RUN It!. , 'E!.1\MJj:±~It!, .~~~11!,
....cr."'we.'~. I: swply to the normal operation of the machine,also called RUN
er sQPPly,the bus power supply,CPU power supply and others.
~~i~OO PWM 1iitl:lH~tJ(J 3V, 5V ~~~tJf~lt!. ~J
63 l{jC~""F.1irroo X1m, ~iJt A8E
*m*
are also called the
Jy, hut it exits
[@.l$',PjO«(Qjucedby
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PWM way.it is the system power supply.
2.Intel itJ:t~M;r-;la1J¥
Intel chipset standard timing
Figure 8-2 is Intel chipset standard sequence diagram.
PLTRsn
CPUI'WRGO
PWROK
CLKGEN
VRMPWRGD
VCORE
Vee
VDIMM
PWRBT...
Running <&011l
VSREF_SUS
32761l<Hz
SRTCRSTI
RTCRSTI
VCCRTC
Figure 8-2
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rding to the sequence diagram shown in figure 8-2 is explained as follows.
1Jf:tR System State)
03:
JU1U1J ~Jlj~~ l';fj •
•the po er of the whole system are closed.
.1-
5: ~tJl.:tR~.
:po r offstate.
4: i*~:tR~.
:donnant state.
3: DiQ~.
:sleeping state.
0: *m:tR~.
SO:power on state.
~n the interpretation of the signal
CCRTC: MmRTCEt!i~HfJ-mEt. 3V. ~i¥i.jfrl*JtfllUjCMOS~~J:t CRAM) ffJ:Et!..
CCRTC:the power supply of the South bridge RTC circuit,3Y.supply power to CMOS chip
..~.••~ insid the South bridge.
RTC Et!i~HfJJ:fft.m~. 3V. ICH9 l,;},J§itl1Jn7.§5-/j' RTC R1ft1§
RTCRST#:
~, ~*~ SRTCRST#.
RST#:the reset signal of the South bridge RTC circuiUY.ICH9 added another RTC reset
the name is SRTCRST#.
2.768kHz :
m m- jU 7 VCCRTC ~ RTCRST# J§. ~ rlTJ fJ& {,~ Et!.. n'T, ~m ~ 1m
unning). dMijJijJJilJIt!..l3itE O.I-O.5V.
768kHz: after the South bridge receiving VCCRTC and RTCRST#,supply power to the
oscillator:the crystal oscillator running.The voltage of two pins of the crystal oscillator is
"*m
"*
:sRBF_SUS: 5V ~mlt!..ffi.
~~_ U :5V standby voltage.
N&<~SUS3_3: 3.3V ~m$..l3i.
~Tj.S3._3: 3.3V standby voltage.
leSl:1SI_OS: Mt1fpg~IHb:~13 afJtEt!1Y-J I.OSV. 7HJTJt-t~Jt-t:fffl~~~1'Et!ffi..
OS: the South bridge internally produced the power supply 1.05V for itself,not to
When we analyze the timing.
_*If
B.3V ft'mlt!..l3ilE'J', Et!.l3i 3.3V. ~T;~$IIt!.i&.
the SQUth bridge that 3.3V standby voltage is nonnal voltage 3.3V is
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PWRBTN#: POWER BUTTON.3.3V-O-3.3Y pulse signal.
• SLP_S5#: 3.3Y, F-iHJi:ill.[L\~~1Lt'C~O~4~*U1§~o
SLP_S5#: 3.3Y.the control signal when the South bridge exit the power off state.
• SLP_S4#: 3.3Y,
i¥i#fill:±lf*lJ~:\7C~O~~*U1§~o (-fJ~ S5#%n s4#9:W-ffl--"j , )=1=1:*
~*IJjft~l*J1'¥f~rg, !f!J--t£~o)
SLP_S4#: 3.3V,the control signal when the South bridge exit the donnant state.(usually just use
S5# or S4#,used to control the production ofthe memory power supply,and another is idle.)
• SLP_S3#: 3.3Y,
i¥Jm=i1HI:\lJjlJ~t'C~B~~*IH§~ (-!RJ=iHt~~*'Jm=1fr-~, }~.~ W
0
It, ~!ll~~It, CPU fAlt~.)
SLP_S3#: 3.3V,the control signal when the South bridge exit the sleeping state.(usually used to
control the bridge power supply,the bus power supply,the independent graphics power supply.CPU
power supply etc.)
• VDlMM: l*J1'¥fAlt.
VDlMM: the memory power supply.
• YCORENCC: mm=f~lt, .~~~El!, ~!ll~~It, CPU {,:ltlt~o
VCORENCC: refers to the bridge power supply,the bus power supply,the independent power
supply.CPU power supply etc.
• YRMPWRGD: ji~mm.Jlt1l1 CPU ~ltiE'M', 3.3Y.
VRMPWRGD:infonn the South bridge that CPU power supply is nonnal,3.3V.
• CLK GEN.: II1tajJ~J:t1fMiIf'F, ~l±I~Jmll1tajJ.
CLK GEN: the clock chip starts to work,send various clock.
• PWROK: ii~lrmm.JltIl1~ItWiE11ty (SLP_S3#tE*5C~)' 3.3Y.
PWROK: infonn the South bridge that power supply is normal (SLP_S3# complete task),3.3V.
• CPUPWRGD: mmttl±l~ CPU a<J PO, l.OSV.
CPUPWROD:the South bridge send PO to CPU,l.OSV.
• PLTRST#: ~i1'~{:!z:, Wim~l±\a<J.--tJ[fm, 39V
PLTRST#: the platfonn reset the South bridge
North bridge.EC,MINI slot etc.
• PCIRST#: PCI jt{ft, mm~l±Ia<J.=
PCIRST#: PCI reset,the South bridge send
used.
• CPURST#: ~~mt&~1j PLTRST#fii,
CPURST#:after the North bridge recei; •
[)(){> 8.1.2
~@~itf1 the soft
~r*1;.L Intel ~m (1lJJ GM4 )
-lli1m.~o
Next to the Intel bridge (sue
-86-
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In the process of the computer hard start,CPURST reset signal is sent and keep a low level of a
ceJ'tiilii ~e,when the power supply circuit has been stable,then removed the RESRT low level and
k~:a high level,CPU start to work,the hard start finished,and start to the soft start.
~j) CPU ~i&it~[:lEl!j!a<J DBSY#f§%~~~ FSB Fltrftjlij.~,~~~1.i~,tto 3 DBSY#./':1
:fW&~p;j~7J' FSB .~~.tt, ~1ffHtfW~, CPU :t~~-WIf'F; 3 DBSY#./':1it1EE!.~Bt
~$SB .(i~;r:.i't, CPU ~;mu ADS#±I!l.±.Il:i&Jmf§%~Ei)f~tt1Hft~:hti!~Wio
ADS ~10~:mm 8-3 fJT7J'.
CPU will check FSB front bus line is busy or not through the DBSY# signal of the interface
ciiWitWhen DBSY# is low level,it means that FSB bus is busY,only released it,CPU will be the
~~ep worlc;when DBSY# is high level,it means that FSB is not busy.CPU will through ADS#
strobe signal line to tell the North bridge ready to send the data.
S waveform as shown in figure 8-3.
(2) ~~tm=~~J~1-ffi%m, ~lll:* 13 ~5MHf Bi1£46-~f.
~tm4l':& tJj -1'-ff£ EE!.f D~
;y#~ CPU, i9-W CPU B?l46-jf, iiJ~*l&~~o ~Bt CPU :t4l'iffirl A3l ~AO :&i!
OHU1i§%, ~~BIOS 1*Ja<J-~M~m~. AO~A31 flJ~tml¥J FSB jj1JftjIij.~.~~t~D,
SB (fCJ1Jji~~, El!.sp:~~*,~:l:.JI:~~mfUtl~tm=. ~tmq~ftl CPU B~~±.Il:m~J§Jmrl
~~~~mm=.
fter the North bridge receiving this signal,if its in good condition and has been ready,the
'8ge-will send a low level ofH_TRDY# to CPU,told the CPU is ready,and can receive the
CPU will through A31-AO send FFFFOH address signal,which is ajump instruction in the
rAo-;...A31 to FSB front bus interface of the North bridge,through FSB frequency
~level conversion and address decoding send to the North bridge.After the North bridge
, g eRU addressing instruction,through DMI bus send to the South bridge.
~.Mf DMI .~~E8 16 ~~m1iX,
..aM..a~tifg,
m%~1:i!.m DMI_RXP(O:3),
0:3), DMI_TXP(O:3), DMI_TXN(O:3), 1101118-4 fJTiF.
bridge and the South bridge DMI bus consists of 16 Iines,point to point
gNlllines including
is lMCRXN(O:3) DMIjUCN(O:3),DMI_TXN(O:3),as shown in figure 8-4.
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00 8-3 ADS#a!i7f3
Figure 8-3
Figure 8-4
AOS# wavefonn
OMI bus signal diagram
iWffi:q~~IJ~~ffi:\¥J~:W::lll~~JfMi~·jtBIOS, tBtJ!!l~ PCI .~~J:£~~ BIOS
(moo 8-5). ~ PCI .~~J:~fl BIOS, *Ii PCI .~.~1"§-%11m.**~~ BIOS fr1ti.±iH1J. :!In
(3)
W<: BIOS tttE EC
r, iWffi:iI):1: PCI m~w~~~.7f~~~ LPC .~.~J:\¥J EC 3m1"§, 3 EC q5l~IJ
B.:l:Il:m~~.fJ}~£ X-BUS .~~!iJt1!t SPI .~!U~ BIOS. BIOS .fJ}mtJmiS.@]fll:1m~~ CPU, CPU i.E
1T BIOS t:j:J\¥J POST ~~m~, Jff!€i~~~1'J;.
After the South bridge receiving the addressing instruction of the North bridge,then start to
search BIOS,first search whether there is BIOS on the PCI bus(see figure 8-5).When there is no
BIOS on PCI bus,according to the PCI bus signal set to determine where BIOS is.IfBIOS is under
EC,after the South bridge through PCI decoding module,then to communicate with EC on the LPC
bus,when EC receiving the addressing instruction,then through X-BUS or SPI bus to BIOS.BIOS
returns the data to the CPU,CPU running POST seIf-check program in the BIOS,and start self-check
action.
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.. BIO J!:ai;bi~BCJ~ffi~:
C :: Uki$ f§-,%).
key signal to detennine whether 810
19~~~,1S not selected
Ill( Et! Sfi$9:J. ~Et! Sf&:ffm9:J
action:C =(chip
elect).
c
lected \,hen low
hen high Ie el.
CPU iEMiitiJ BIOS i3 ~~n:.Fo. lfilfJ ff PO T fg48~j1J~L
~- CPU reading BIOS self-test correctly. then tart to e:-.e ute the pro ess of POST
<D.~ CPU ~JtiE'i"JiiWJ BIOS ~@]8~ POST El . ~Jf:.Fo~1ftl1<1]~1-t;t;Jt~1l (lli~~m
:i£htftit PCI-E ~il (!!It1L~ -t ) c
-~I"'I.CPU addressing is normal, received POST self-test program returned by BIOS. then start
iitiJ!U#!d 1be chipset(the South bridge and the
1
orth bridge).and also initialized PCI-E
~Meodc!lDt graphics).
@ *~tftitJii, ;!i:t 5MBUS .~~:I1IiJttP3f¥. *trYJ~1-t. ~*WlOO 8-6 fiJfij,;c
~.&~'tbe South bridge initializing grab the memory through S 1BUS bus to be initialized. the
~~~'isshown in figure 8-6.
"-~J'~ ffEl~Jii, BIOS :f3.i3*Mf¥AP3f¥o
the memory self-test finishing BIOS stores the self-test program into the memo!).
)A~ffJ:i,IIIm BIOS M~-.l1l:~l'-i.9:~. Wlm~~~tl~. ~-t. jE-t~o
Called the BIOS program from the memory to test each device one by one. such as the
'COntroller. network cards, souild cards etc.
~_.a~
.~ll-FBCJ BIOS, *i.llm't{fJ~I£~-tl¥rfJJ{zijf.to
1be graphics cards, find BIOS of the graphics cards.. and call them to complete the
ofthe graphics cards.
~~ EDID ~!litJIUHg.@.
(};\!.m 8-7). ~¥iJM.Fo, 1t It rn -'%If fcl M~ Et!
cs cards starts to read the screen information through EDID bus(shO\\n in figure 8-7).
•
~ then sends a signal to open the screen power supply and backlight.
111-7 BOmO
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It
ri'lir 8-7
FDID wavcl'Orlll
() !II"/J,JrHL I O(i() 11 1111(11,
)1 Jl'1~(d,;'ti~IIJJ( 1/'IIJ{f )HIII~ r'411J''LJlI~JII
Di.'pla, tht: hoot piclllr', ami slllrt to I 'sl til' cxtclldl:d III 'Illnry ami give Ihe l;oITl:spondin '
addr s .
t~i~!IJ .JIl:t'J\(fLi~;;).. HMM!/,''\' )VJI~, /1\11, )1·11. (1)i'JI~~1 .
Te. t some standard 'quipmcllt, including hard disk, CD drives, serial ports, parallel pOl1S,
(H
floppy drive etc.
® ~/J;~h i~ ~t~-l.i~!~ '/l!,J, i, ;f. Nt I),j ,~lll'l~ Xn 1!IJ M[IIJ) IJ f~(il~;I~) r~(it;(J.~)!IJ.flil'll~ \"1# ric 'II (I~) ['PM
UIJ Jl]l~ ~. ~l: 1:J~ I/"~ i~ 1h-5}J"lG '11J'l;Ji jIll JII:, DMA )ll1m.f11 I/O !liM I I ~: IJitl);(
0
After te ting the standard equipment, the plug and play code supported by the system will start
to te t and configure the plug and play equipment in the system, und distributes the interrupt address,
DMA channel and I/O port and other resources 1'01' these equipment.
r!JTrifl\!!1'H'.@:w!fl~Jii. ~1;i'l1l'lHill·/'IIJ~iJW.J11:. l!!.liVtJ1:!9r{j (I0fJ!l! f'HIl \'f.IW [ "I {1!l!1'1;f
tic. lS:IIJ:!t·'I=JJl(. 1- ESCD X1!I: (~tJt BIOS m~~lj~~~11:~tJt?(W~fJll!f'l:fflGf·i_1I'j.I.;!,(I() -.fIll r
r~. ~il~lJ&W:fftE CMOS ~I~), CPU 01el.l:IJ~(I~ ESCD fllJ:(j(((~) ESCD illrrbt~. 1x:fYlXJ}IJ
111, i';1J.!.fffr ESCD 4'A~!I&~.
10
Afier all hardware testing and being assigned the interrupts address,that is.all the hardware set
up a hardware system then it will generate a ESCD file (it is the method that the system BIO
exchange hardware configuration information for the operation system.the data is in CMOS),CPU
will compare the generated ESCD with the last ESCD,if finds the difference.it will update the data
in ESCD.
@ ESCD J!flTJ5, CPU i:B$Ue POST "~4'ItJT)JIUHi~:J:MTjGl:r-. f1Fr.f~illrrj},tJt(I~I'1
7~*'EJ}. j},#t BIOS t'fJJ6f4Jft{il9;"UlmF~1i:iEtJ<J~f4JJIIDl~*J6f4J~ff-*tJt, 7tf:[Ja i'iIJi&*" I
~~~tlKJqJ)tf!f, ~J5~A~ff, BIOS ~E!.~$tl:+X~~J6f4J)(1!f, r:lJJ6iJr>cfit-iJl W':!'JRWffi
rfc. ~Il Windows XP, Windows 7 ••
After updating ESCD CPU will complete
out the bootstrap program of the system
system according to the boot sequence ~i
first.then write in the memory BIOS give
operation system guided by the bootfiles,suc
the interrupt service routine,and then carry
ystem BIOS start the operating
hoot files in the starting device
uter to the boot files.the
on.
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!'trR!Ul1!l (Advan
d
onfi uration & Power Inlcrt1H:e) '(; I :;:-~ j'lfG 'n. I. IQ;'~1 II t'f. nF.
aizto' ft ilm~El!.$i Jlli~!\!ti~)(;IIJi~k!lj''l~I&(I~ . I BID ,'tlij \P I t \d\anc d
M1!'~'IQm'lent)
(
ACPlit
!UfI(Xf~l:J.Il~nj P 1
dvaneed Conti uration & Power Interface) i. til
f th
-tandard
ad\:lI1 d
on and the pow r interfac .Before A PI pr p sed.lhc univ rsal p \\ r managem '01
iib4iriliS PM with a BIO I v I developed by Micr n. PI i to repla th pr \ i u P \ .
Eb lnt 1 Microsoft, To hiba rrrJUliJi~IJii:t'10. J1:.J:J J (£n~f'f:*tJifD1i2!f'fZ.I8]A­
lI~O. J;At!Xi!J;A JiU t£ 1t!?!J;[1TlJU L:.11J r~ IliJ (I~ Il'ii Jirrl~tl i.E ary:ftJi -1~ Do
r
..~~"I isjointly developed by Intel.Micro ofi.~ shiba.is to have a comm n pow r managem nt
een the operating system and the hardware,and t
impro e the di unit) interfa'
!¥Q»Red by th different manufacturers on the power management before.
"'OLI,-...tndo s 98/8E, Windows ME & Windows :WOO, Windows rp 7f~3tr.-J CPI
M. ~
m Wtndows 98/SE,Windows ME and Window 2000.Windows XP taning to
uppon
.~.Lm~.*.~§*~~~~~o
rom the laptops to the desktops and servers are included in thi
p citi arion.
I iiJJ;A iJ:~tJfi!A1~El!.~m'M~ , 1Ii~~ ..,.. ", tm~mfl1i*IIa:~.
tfi.
I can make the system to enter a 10
§ B~fJt~~ ,1 E@.
power consumption of "sic p state".su h as tandb:
the purpose is to control the power consumption of the computer.
IRi~tJ(J~~iiJ~'.JG (GlohaJ), D (Device), S tSleeping), C (CP
) .
ofACPI can be divided into G(Global).D(Device).S(Sleeping).C(CP ).
8.2.2
ACPII¥J G ( Global) ~~
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this time.As long as any wake-up activation events message into the system.it will soon be restored
to a working state.Under this state.the machine can not be disassembled and assembled.
@G2/S5: Soft Off (!i9\:!JHJ1) :l7Ci$. llt:I7Ci$r ~tfLR 1~c\If:i'~~'~YB~ ~tJffi. 1i*T 1f1iiJ1tJfJ
~~.~.m~fi~~~ff.~~~~r~~~*~~~*~.~I~~~.~~~r.
~
(j~tfl;~m.
G2/S5:Soft Off state.System only keeps very little power under this state,no users and the
operating system programs are executed.The state takes a long time to return to a working
state.Under this state.the machine can not be disassembled and assembled.
@G3: Mechanical Off :I7C~. llt:I7C~r~~*mB~ EE!.tJffit>.J;tcI~. 11:~ 1fiiiJ EE!.¥mJIDli*
m.• m9H.~n*EE!..~@ft~*;tc*.~.llt:I7C~rEE!..~mft~
••
G3 :Mechanical Off state. Under this state.the power of the whole system is closed,there is no
current through the system,the system can only reopen the power supply switch to active. Under this
state,the power consumption is zero.
~»
8.2.3
ACPI (l(J D (Device) :tR~
1»)
D(Device) state
Device ~m-@ii1i-. i9JHmiP!l*tlfiWJ~, li}!ff!, :7't~I8:~, x.PJ*~~Dr 4 #.
Device refers to some devices,such as modems,hard drives,CD-ROM,etc,also can be divided
into the following 4 kinds.
(DDO: FuIly-On. iE1ItIf'I:::m~.
DO:FuIly-On.The normal working state.
®DI: PJ~~~Y~m~. ~~~~m~~ii1i-m~~D2~~r~$~$.~~~rn
~~*~m*~. ~@ii1i-~~~ADl~~.
DI:1t can save less power consumption,the device function with keeping activities is much
more than which in D2 state.This sate is determined by the device itself,and some devices cannot
enter into the 0 I state.
is determined by the
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.2 ..
C
(J(J
(lcCllillg ) ~J(.a·
."~;""'" means Sleeping and refers the system enter inlo the . . I<.;eping siale ill (i I,alsu (;(111 he
~_q~~1{l' to 0 SI S2,S3,S4,S5.
1
0:
~~ it. ~ifJJF'lIlj((~ U12:j)'i:, mil i}tf,V,-Jr. J)JnflJ.~~,1iiH HOW"
Q~ faet,this is our normal working state,all devices arc ('lilly open,the power con. lInlpticJII is
"I more than SOW.
lr r£JIt:jjti5r B~:I4J CPU r)H~II'HJI'.x: I~J, {1I;HJc ( PI), 'Hche ,I~,l'i?ll) (I(J I),)
~, itk~S1Htj:iJ3t),t.iE1lf; 11'0 ~II,J'(I~J)J~~ ·mUF 30W ~~, I:" Jty:. 1) JII~ 'pu
~Jff.I it:f+ if. JjJ{ JJIlff ~ ((1
, U internal clock has been shut down under this state,bUI the contents 0(' the system
ibe chipset) are not lost,the other parts arc still working normally.At lhis time,lhe power
'on is generally below 30W.ln fact,some of CPU cooling sofiware is developed in II is
rinciple.
2: ~i!j.{T SI. iAp;j CPU ~r-f .l1:iE1f.*~. CPU III Cache (JWn;~ IjJllV··, ";~,?.!G
~m, fEl.~~atJli4iJ3tI.Ui~0
'l8r to SI at this time,CPU is in the state of stop,the content of CPU and uche has been
bus clock is also shut down,but the rest of the device is still running.
: itilt ~ifJ"~atJ STR (Suspend to RAM), [l#i 7 r)~ :(:J.(I(J ~i ~\l~I' JU 'P
•
0
mtro ~~J$Jit~, ~ ~atJ ~ ~ E8iil1!ittr.f~~1Jt~~Q.~Hp f!iH1'J {E. j.6:IH (J~ J)J~G
's ~ TR(Suspend to RAM) we familiar with,in addition to the information of the
content of CPU,Cache,chipset is lost,the content of the memory is provided by the
er. service data is exist.The power consumption is less than lOW at this time.
D (Suspend to Disk), lUJt~Et!.Il~~, fEI. ~tJt1 .rn,~{l-AfiJIWL
it.f1:~tJt Jji!., ~1¥~J.m~i1I**i~H¥!UiV!m:1¥.I hiberfil.sys X{!f:rll, ii!1!JM:
::ro<Suspend to Disk) the system main power supply is shut down but the
red in the hard disk.By the operating system implementation after
:6fitllie~J1~&rnorysaved to hiberfil.sys file in the hard disk the hard disk is
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V;r,Ml't~Jg~ff-'1;jibt:'~Ii~i5t1&(~~II1,
~:J.f1ffJ(~~'J&:IJ.'i'fT;j~.
I(ijJUl!!.i)!'1ilJ~'Hd: J XriJ:l) .~ ..•
I
-13 ft1fH1i:T-"r-gilm11(m, -*rfti;(}tf&:I~~II~. til 1·.M.IJ~{f 'I Jj.I'lI\( 'kV,'; Jill}. J.I)
STR z.tru((.]I1"F~~0 JJ-jfffl~i~1gj£tJrf&·~Jl. 1~l!t}lJ! !u,'?j;ljillAtll~~ JF S" R ~} LJ~i n. 'I}((I')
lI;j'riij::fii~JLfyffij Go ffij S4 ~;:t. E!P STD (.j:b~i'ljfJ!I!~U. 1&JJ~:){ (~"{{(1: M! I,',{ 'I I (I() III J /1 /)1
1M:1¥J~/~it&bt.~f¥!&t3H~$, lEJl1tffl~*iliifJttL*i STR )JIS i',·tk /0
tJtI't1f€rt!
t&1~0
I
The most commonly used is the S3 state.that is Su pend to RAM state.referred to S'I R.J\. thl:
name impfies,STR is that to save the data of the working state before the system entering S" R into
the memory.Under the state of STR.the power still continues to supply the power for the most
necessary devices,such as memory.to ensure that the data is not lost,while other devices arc in "
closed state,the power consumption of the system is very 10w.Once we press the power hutton.the
system will be awakened.immediately read the data from the memory and return to before workin I
state of STR.The read-write speed of the memory is very fast.so users feel that it takes just a few
seconds to enter and leave STR state.And S4 state,that is,STD,the data is stored in the hard
disk.Because the read/write speed of the hard disk is much slower than the memory,so it dose not so
fast like STR in using.
[)(){> 8.2.5
ACPI t¥J C ( CPU) ~~
C state of ACPI
ACPI I'fJ C ~~~m CPU ta~~, XiJJ7t~~r 5 #0
The C state ofACPI refers to the state ofCPU and can be divided into the following 5 kinds.
CD CO: CPU j£'/ltIfF:tR~o
CO:the normal working state of CPU.
c!oi£:ii'~~~, 'ff
f~a<J~MlJ1fil]o {£~:U'
13i;1}lfWIfF
~
;5 r B~{iJ!!1tf~gl!'tfBJ!.IZ'~Ji!.."J
~*'
~~~~m~~4I!'tiJJ~~~~~~~
C 1:CPU suspends worle automati
unaffected under this
.s state must be small
@ CI: CPU
:1ft ~ r 1'fJ~1tf~1W1!'t fBJ
0
state,and there is a minimum time to iVU
enough.so the operating software caDI
time in this state
when determine whether use this
® C2: ~fl;,{ C I. J1tfl\.t*~~
~f'l.~~~jf:j)l~ffa<J-!l:11ho
C2:Similar to CI the So
CPU continues to monitortbe
in figure 8-8.
-94-
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CPU IIF I' '-'...L.L-...o
(':==..-)
fi~
II Unlatched I
Latched (l'J,Wf)
I
! (~~~ml+)
I
J1
I
14--r----j+:=='-J.,.....-.J
=
~F'J/llr
SlPO.J(#
\
I250
__
-<~>--t2-73--!_127_4_
1
__
I
(Q*ftI:)
00 8-8
Figure 8-8
CO-C2-CO 01" J.J.
the sequence of CO-C2-CO
@ C3: C3 1*D~~~, Ilp~~5'Hmll1~, i¥JtftRtI:J STP cpu#~ll1t.sp;t;JtIj,~HfJ CPU
mJ~"', 18J1t-j**:&ili DPSLP#~ CPU, Jm~ CPU JitA C3 ~J!f1;*D~~;:tQ CO-C3-CO B1Ff
8-9 ffi7J'o
G3:C3 sleeping state,that iS,close the external c1ock,the South bridge send STP_CPU# to clock
close CPU clock,the South bridge send DPSLP# to CPU at the same time,to infonn CPU into C3
sl~ing state.The sequence ofCa-C3-CO is shown in figure 8-9.
CPUUF I UnlJllchec!:
Signals
(~IiIl1f )
STPCLK'
Latched (t111f: )
Unlatched
~
~
I
( II,WI1f:)
[;1
Bu. Muter I
(~)
DPSLN
cPUIJottII I
I
ActIve( ffiidJ);I<
Idl.(~f.*I)
I
I 1211
1270
\
Runnlng( ""~)
J
c;;:
~
t+ 1.7
-='
""'"
(lfl!:)
r=;~
Running ( ,Il,l1l<Aill1l< )
I
III 8-9 Co-C3-e0 II'tJ1:
Figure 8-9
the sequence ofCO-C3-CO
ftkf C3 f*~~if;, 1£~m:&lli STP_CPU#~~ CPU 1l1~J5, i¥J#fRtH
)FRSTP#ffI~~ CPU ~1t1t~'lf3;!!~Jt, m !;A~~ CPU m,t.\ltffi. CO-C4-
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(JIIJ IIF
I.Sd1ed ( I~Hi )
I~
~ IIIMI
"II " ( IIIVHf 1+_
'J
I
\
I
I
kIo (.,;~ r~·1
AdlYo ( i!,4J )':t'
l
)
I~
I21ll
r;:
~
fr;s:j
(JIIJ IHi'I'
t
IbwircI ( ,\I,l.\(.I!lltil )
';I(
"I
~
lZ!Il
..
...
00 8-10
I
-- ~r.a:
\
(JIIJYa:
Ira.
(f';!l) ....
SIllA>Bd ~ 1UrW1l( ,\I.lAi@<) I
J
CO-C4-CO I!'t Ff
Figure 8-10 the sequence ofCO-C4-CO
[){)I> 8.2.6
ACPI iJCJ II!. II ,"~'J
moft the power and the control signal of
ACPI
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S,E,P_83#. 8LP_S4#. SLP_S5#:the signal of the low level control enter S3,S4,S5 state.For
I~Riill'tlple the system is in the state of SO when running normally.three signals should be invalid.is
d .SlJSB# SUSC# and others are similar to SLP_S"'# signal.The state of the sleep signal in each
$Ieepmg state is shown in figure 8-11.
1111}
~
so
Sl
S3
S4
S5
SIoP_S3'
1
1
0
0
0
SLP_S4.
1
1
1
0
0
SLP_S5.
1
1
1
1
0
Figure 8-11
the state of the sleep signal in each sleeping state.
:a:
@ PWRBTN#: Power Button, fl!~~m. 1<: fJL lit , 1ft1~ PWRBTN#1]§-'%, ACPl ~~1~
8LP_SS#. SLP_84#, SLP_S3#¥tJ 3.3V. ~ll:~ PWRBTN#~~ 4s 1~Et.'Sf, ~~1!£*~jf.S.¥.
S5~~.
TN#:Power Button.At shutdown,pull low PWRBTN# signal,ACPI will set high
~~S!'im.
SLP_84#, SLP_S3# to 3.3V in turn.lf PWRBTN# continues being the low level for
will be forced into the 85 state.
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The clock circuit
The working condition of the clock chip.
~[l 00 8-12 fiff7F, Et1~~Jt 8~I f1=9.k{tj:~[lr
0
As shown in figure 8-l2,the working condition of the clock chip is following:
CD fjiJt!.:
*0 L32 f=:±.+CLK_VDD, +CLK_VDDI t~fft 3.3V, d3
83+3VS ~ LI6
+ 1.0SVS ~ LIS f=1:.+CLK_VDDSRC m:1;J:l: 1.0SV
0
The power supply:+3VS produces +CLK_VDD, +CLK_VDDI through LI6 and L32 and
provides 3.3V.+ 1.0SV produces +CLK_VDDSRC through LIS and provides J.OSY.
® 7fJf-l{i§.!% CK]WRGD/PD#: ~F4!:if 3.3V 7f~ a
The open signal CK]WRGD/PD#:the high level 3.3V opened.
® 14.3 18MHz t!i1Ur:.:J1& Y2
a
14.318MHz benchmark crystal Y2.
@) CPU_STOP#, PCI_STOP#: CPU ~ PCI B1~1~Jtllit<~·, iElitIf1=B1~nit"r:g:ifa
CPU_STOP#, PCI_STOP#:CPU and PCI clock stop instructions,it needs to be the high level
when working nonnally.
@ 5MBCLK, 5MBDATA ~~1fJ!(.~~: fflffHu'U BIOS m~
5MBCLK, 5MBDATA system management bus:used to transfer BIOS instructions.
® FSLA, FSLB, FSLC !Wi.~~: IHi/f'1iiJ1¥J CPU f=:±'/F[iiJB''11iUftffij.~~B1tTo
FSLA, FSLB, FSLC frequency selection:according to the different CPU to produce the
different front bus clock.
0
The clock signal distribution ofGM45 chi
-98-
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s t display clock thutlhc clock chip send 10 the North bridgc,96Mllz and
It-tfl1·~,Jt1it~I*HJi:lkJ(l~ ATA tJ~mlj~II'H)I't IOOMHz.
ATA controller clock that the clock chip end to the outh bridge, 100M Hz.
It-tfl1~Ft1it~m#j:(I~ PCI-E ~~~cn~'~llt IOOMHz.
6 pin is the PCI-E module clock that the clock chip send to the South bridge, IOOMHz.
56. 1t-t~;cjFt1it~~tm(j{JIOOMHzf~/c..'Ii'H~l.
pm is lOOMHz core clock that the clock chip send to the North bridge.
I~~ 45 .~It-t~;e;Jt1it~ MfNI PCI-E flJt(j~ I OOMHz 1l1ll~ ffl T7C~~-F~.
;45 pin is lOOMHz clock that the clock chip send to MIMI PCI-E slot,used for wireless
t
~etc.
ir§j" 47 JJp~It-t~~Jt1it~tlH~~-F(jj 100MHz IW~ll0
~ .l47 pin is lOOMHz clock that the clock chip send to the onboard card.
~ 15 .:Jllt-tflll;e;Jt1ittft EC ~Jta~ 33MHz 11'J·~ll.
mis 33MHz clock that the clock chip send to the EC chip.
7 .:1!It-t~~Jt1it~WJml'¥J 33MHz lI1iT ffl T mffi: rJ;j f.fIHY0 ~ 1iL Et!.~
hi is 33MHz clock that the clock chip send to the South bridge, used in the reset circuit in
t
0
bridge.
o• •It-t~;e;Jt:tt~SD ~-FB;e;JtllJWJml*J USB ~*IJ-1*B~ 48MHz Mtrt'.
is 48MHz clock that the clock chip send to the SO card reader chip and USB controller
bridge.
~lt-tflll~ Jt:tttftAim I'¥J 14.318MHz ~t1E1!'J~
. 14.328MHz reference clock that the clock chip send to the South bridge.
8 43, 46 21 JJpJ!~S&lt-titl'it*ffi%, f~rt.!JZfl~o
;46~1 pin is the request signal of each clock,the low level is effective.
0
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Clock Genera/or
.,........_ ...........=-__-<:>
D_ot.~l...
, ...."
D_Ol..~ ",'.
SQI(
"""-""" 1-"-_-""'-""'U!!4'-_-<:::JQJ\.CP\I~KIJI4
0'UCU1'fV"
c:ut.CPU_1lCl.J\I •
".",.'JJ"LF ....--""'.....""'''---<:::Ja.-...aDL8CI.Jt r
0'\lC1.J."!'V
•
8flClD_U"MXJ'fT__J,rR
&ACCll.lIMJOT'C__....,...
~~-=~_7
_
aJt.DMY__ I
fA-,......""'!.!!!"---<:::JCUL...".- •
nutt...~.J,J"RIE,I---~""""'''-'''L.:.YGk=·'''''C''51~~~~.1IIOS
ZMtr,.1MRlC1J.I'MID
a.x..DfII(F_1KI •
~lATJI"'I---""';:J:&ll"",,"",,:a.~..:.Y.::llk":'·"'·Ot'~"J~
~TA(;J.I"fl
~~SA'Ut1
""'"_
....-
cm
loL..--<:::Jcu....lIIDLaot'U. •
--<:::JClJl...IOL........
I-'--r------..........a....---"i ..
. ,.....- ~;~~~~~~~~~~:~~~
CU-.Drl . .
IJClJI...OL1"
.....-
....-
""''-'''L---<:::JaJlLPCE...._ 11
""'U!!l....--<:::JCUL~_ D
D
1...--'
....._
~I....'---.:=Jcuc..~LMI
•
""'UoIllL---<:::Ja.Jl."ClI:,.......
......_ .........,_.....-<:::J_ _ •
~
Figure 8-12 the clock sign!ij,..d,il""·.......,..."
The clock signal distribution ofHMSS clii~
HM55 ;C;iH.lift-jttl'1~%I'(.J?t;(p:tm1l 8f!} El3 PCH ~ :It te ~i&ft-jttl'i'f3Jt{1Bli~ ..
-ItO. ffr7ffl1f 25MHz ~~.
The clock signal distribution of
clock chip is just sent to PCH cloc~then
the display set,and the display set suppg
crystal.
-100-
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The clock signal distribution of above HM65 chipset
65 ~J:.~Jtmllt~{~~(j{]7.t;(Ptmoo
.... ~.":"lr-
8-14 JiJT7F:. %'=.8~m~px:n~·t.rp~Jt,
1Z'~~
Afi.
The clock signal distribution of above HM65 chipset is shown in figure 8-14,the characteristic
• must be 25MHz crystal when the bridge integrates the clock chip.
PCIE GraphICS-'-
-101-
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The clock signal dislribution of AMD double chipset
AMD ~ffi:;e::J-t~RD1~..pf§-I%B10"1fj ~f100 8-15 f'fTjF,
f1~/flP;0)ibttIJ ~Jmn'HJII, illllllAw 1 iii
1i:&tI:l33MHz D1Mt, 33MHz A~·trI1El311Hj'f:&tI:lo
The clock signal distribution of AMD double chipset is shown in figure 8-15,the clock chip
sends each clock,but is just not responsible for sending 33MHz clock.33MHz clock is sent by the
South bridge.
-.
-
.
aa-.
.......
........
--
8'1' fOlE
-
mul118
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..
-"'"
--
_
--...
Figure 8-16
........
AMDFCH
Hudlan D2/0l
.,...
"""""
--""
,-
--""
_CAlI>
"T_GFX..CUC
_PCIE
GPP_CLK1
,
'-
(TU
'"
..""
roil•
.... ROM
.....
-
the clock signal distribution ofnVIDIA chipset
signal distribution ofnVIDIA chipset
vtlJilM'fIl?};{fi:(m m8-17 JiJfiF, ~ R.:~:m.J£lt-.tfll.
SIgnal distribution of nVIOlA chipset is shown in figure 8-17,the characteristic is that
the clock.
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--"' ......
."',..,...
"""
"'.......
"'_.
_ _ wo
-
...-
"'",...,
""-U:LIlI
~......;
r--;~
..
",,~~f'
MJ_tlGJU
'''-''''''''
N''''''''
PO.
::t=-
PO'
"'lIII!"'(:U("
-=- ........
--
nVIDIA
I
,
, • •HI;I!:)4M1U
......
-.>'
I
I
~
00"""
.~
0
_....
-=--
PO'
'«.J<='"
-~
O
IlIMM1
..",.,..,.
..........'
..--_........
"""'.
.
--=-......
a._ ..
tJ'U_Q.lf..tr
n-
L:J
<,
~I
_J>"
O'V
OltAtO
(
...-""
--""
~-g:-:
..-
-
(
,
........ a.<
_a.<
AMD638
Kt~I'
..
~
[C
(
~
IPeO . .
l:j ... 1I
[£] 1b~ .. 1
PO ....
..........
.......
......... ==--._~a.t
~
....... -
Lr.nnJ
-
PO
[
"t-
..--.
-.-
"
.....
I
~
Figure 8-17 the clock signal distribution ofnVIDlA chipset
[)t){> 8.3.2
PWRGD '"tlf;ltl!.
PWRGD and the reset circuit
Intel i¥im:l*Jfflla~ VRMPWRGD
M:fJ~DTo
The explanation of VRMPWRGD
in the South bridge is following:
VRMPWRGD: J1tffi%@~~11
tf< 'G' EI!lli B f!)E JIt ffi -i} :tE T~UJf ~
"!zn~ 8-18 JiJTlFo
0
VRMPWRGD:this signal
supply chip,used to indicate
PWROK signal in the South b
8-18.
VRMPWRGD
-104-
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Figure 8-18
the screenshot of the text about VRMPWRGD pin definition
OK: 1Ei~lf~lI1, PWROK Jm9;O ICH Jifr~ttWi!B~~t"~Jl~JE 99ms, PC1CLK
-~ Ims. PWROK ~;I:]f~~4'-II1, ICH f"~il\;tt4'-B~ PLTRST#. 8:: PWROK 1Z,~.m7G
y 31"RTCCLK lI1~fflIM. PWROK ijl}J!fJfE5Zrntt~~~D~ 8-19 Jifr~.
DOK:when the signal is effective,PWROK infonn that all power oflCH has been generated
Ie for 99ms,PCICLK has been stable for Ims.When PWROK becomes lower level.lCH
PLTRST# with low level.Note:PWROK must be inactive for three RTCCLK clock cycles
screenshot ofthe text about PWROK pin definition is shown in figure 8-19.
CNlPWRGD: CPU E@.~~f, ~l'f§-%@ii~iO~~~B~PWRGOOD)]!P, ~~ CPU O~
~3:fttJ<J. i!:J!-l'Wu:±l{§~, ~ PWROK *0 VRMPWRGD if§l=j*JJX. CPUPWRGD
lljC:flIJ m8-20 WT7J'.
UPWRGD:CPU power good,this signal should be connected to PWRGOOD pin of the
~dicates that CPU power supply is effective.This is an output signal.fonned by the phase
IDK and VRMPWRGD.The text ofCPUPWRGD pin definition is shown in figure 8-20.
",ROK
I
Power OK: When asserted, PWROK Is an indication to the ICH9 that all
power ralls have been stable for 99 ms and that PCICLK has been
stable for 1 ms. PWROK can be driven asynchronously. When PWROK
Is negated, the ICH9 asserts PLTRSTlf.
NOT!!.
PWROK must deassert for a minimum of three RTC clock
1.
periOds In order for the ICH9 to fully reset the power and
properiy generate the PLTRST# output.
PWROK must not glitch, even If RSMRSTf Is low.
2.
Figure 8-19
CPUP.WRGD
the screenshot ofthe text about PWROK pin definition
0
CPU Po_r Good: This signal should be connected to the
processor's PWRGOOD Input to Indicate when the processor power Is
valid. This Is an output signal that represents a logical AND of the
ICH9's PWROK and VRMPWRGD signals.
m8-20 CPUPWRGD i3IMJ~.:x.Jl)C.OO
as
-10]-
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PLTRST#
0
Platform Reset: The Intel' ICH9 asserts PLTRST# to reset deVICes
on the platform (e.g., 510. FWH, LAN. (G)MCH. TPM, etc.). The ICH9
asserts PLTRSTII during power-up and when SIW 'nltlates a hard reset
sequence through the Reset Control register (110 Register CF9h). The
ICH9 dnves PLTRSTII Inactive a minimum of I ms after both PWROK
and VRMPWRGD are dnven high. The ICH9 dnves PLTRSTI: active a
minimum of 1 ms when Initiated through the Reset Control register
(lID Register CF9h).
NOTE: PLTRST# Is in the VccSus3_3 well.
Figure 8-21
PCIRST#:
the screenshot of the text about PLTRST# pin definition
i!~~=-t~flLffi%, 't~d3 PLTRST#~Il1~fPmH1to PCIRST#91JJti1~)(
mt)(~OO 8-22 PJT7Fo
PCIRST#:this is the second reset signal,which is produced by the PLTRST# delayed buffer.TI1c
text of PCIRST# pin definition is show in figure 8-22.
PCI R...t: Th'. IS the Secondery PCI Bus reset signal. It I. a Io9lcal OR of tile
primary Interface PLTRST# signal and tile stale of the Secondary Bus Reset M of
Ihe Bridge Control register (030.FO:3Eh. bit 6).
Figure 8-22
the screenshot of the text about PCIRST# pin definition
i«JI5, ~t#j:1¥J RSTIN#JJp (i31 JJp~5(W.OO 8-23) ~~~$IJrw#f1JtIH I¥J PLTRST# J§ No'j
1 ms ~IH CPURST#~ CPU, ~ffltil!JSi;lJo HCPURST#i]I)J!IJ}E5(~OO 8-24 JYT7J"o
0
At lastafter the RSTIN# pin (the pin definition is shown in figure 8-23) of the North bridge
receiving PLTRST# sent by the South bridge.Delayed Ims send CPURST# to CPU.to complete the
hard start.HCPURST# pin definitionJs shown in figure 8-24.
RSTIN#
I
HVIN
When asserted, this signal asynchronously resets
k:. this IIgnal Is connected to the PCIR5Tjp
ICH7. All PC! Express Graphics Attach
1M complIant to PO Express"
1.
Figure 8-23
HCPURST'
-106-
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!!1t!..H1~:(m1ll8-25 JiJT~o
e sequence ofthe reset circuit is shown in figure 8-25.
Figure 8-25
the sequence ofthe reset circuit
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--::::::=:::=::==
PWM (Pulse Width Modulation) t1p!l>t-i'!' :9tJ.ti'!l-$'], j;ij ,ft-!l>t-:9ti2J-$rJ. ,'t.::fIJ m.fkBtJ£~€r.;4t
;f4tnl:: ~nll41J. t!.S3-il-1t4t-$IJ lr.}-fl';ff ~ ~ ~{€r.;.tt~, J if-B. m .(£.M.~JIJ-:i, i! 1t j.J Jj] if-ti:-$IJ
~f.lr.}*f.~t.~~~t!..tkfft*t!.t!.S3-.*m~#~A.~~.~.4~a,
PWMt!.S3-• • • ~,.~~.k.~~, ~~~t!.S3-.1~€r.;~~·
Chapter 9
The explanation ofPWM circuit
PWM is that pulse width modulation,it is a very effective technique of using the digital output
of the microprocessor to to control the artificial circuit,is widely used in many fields from
measurement,communication to power control and transformation.This way is used in most of the
power supply circuit in the laptop.Compared with the linear regulated power supply,the PWM
circuit has the advantages of high efficiency,high output power,but also has the disadvantages of
complex circuit.
9.1
~~*~~±~~~PWM~.-.
The PWM circuit in the laptop mo
the coil and the capacitance.
[)(){> 9.1.1
:..r.MOS+~II+Et!.~~px;.
~ ofPWM chip and MOS and
PWM t'JCJIft:IlU,..:1t
PW M jffiMirnj iJff ~McX'M1JUJ !l'l
00 9-) 73f~J, ff~fflIM~Jt!.Ii.
5V X50%=2.5V •
PWM regulates the output 0
for the proportion of the entire
period ofthe highest voltageam
is 5V·50010=2.5V.
-108-
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18k
J'L
II Trlg'd
MPOI: 0.000,
+
'r
Uu
AUTOSET
I
I
I I I
"-"Ii
'an
Ji!ilM
;p.~1! 2.S0V
~$ 1.000kHl
S.08V
'.OOOm,
cHii.oov
""'JW?~~
iJJt~;
MSOO)!1
CHl / 2.60V
9-Nov-1312:S6
l.0000Ol:Hl
PWM 1B<*
00 9-1
Figure 9-1
PWM waveform
~1' mJ M
the entire cycle
ff~mJM
the valid cycle
*l-diffl
peak-peak value
mJM
.ijZ:ltgfl
!J;iii$
lflm i3i;IJ-tiI
cycle
the average value
frequency
cancel the automatic set-up
ttU~.JI
• principle ofPWM power supply
IJJI.:W:i1l 9-2 fffffi, PWM ~Jt~*,L.t~'1flY-JiWiil7f::}t*ir.JTiEgff, 3
d::1ft€i LC iiUM!~1tIt!.#~m~~It!.: ~Jtil~ FB %i:~iUJt:Egm7
""f1f, ft;jfflt LC 1f~It!.i&IY-J:6XIt!.@)~, ti~~m~tftlt!.. \Il1:j:l TI1-.J7f
~ R~~*,J TIIY-J 6~~~iiJl».~*,J.1±l UIY-Jitlifl£.
PQwer supply circuit is shown in figure 9-2 PWM chip controls the high
r, anCilower tube to adjust the voltage,when the upper tube is opened,the
be to charge LC energy storage circuit and supply power to the rear;
c~eifull then closes the top tube,and opens the down tube,forms
c're '~aild continues to supply power to the rear.TI in the figure is
oog as control the duty cycle of TJ then it can control the
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PWM
Zit
FB
LORV
LGATE
Figure 9-2
the principle figure ofPWM power supply circuit
The working process ofPWM power supply
m:
PWM t~ l{i.Af*I i'Fi1~X JJJ~*lI!I1'WJThe specific working process ofPWM power supply can be subdivided into four stages:
CD Tl z-ffiJ, ~IKBtrBJ, J:.~r~:l$Jti, lltBt J:.r'lf!}gzlJJ1~-'%i5J/'gil£~4'-, jlij~i5Jf&.LL
Before hthe dead time the top tube and down tube are cut off,at this time,the top and down tube
drive signals are low level,and two tubes are cut off.
®nBt~~,J:.~~~~%~~~~,r~~~m%/'g~~~,lltBtJ:.~~~,
r~
~lL YIN ~ffi~£J:. ~ D-S fi, i1 L1 Ji§itJILMffJ.t1, .~tJlLjRJi1!!, ~ ~mtmt~ ~~Bt, 1£ ~
f i.IC;J:.f= ~1i: iE:1:i ffJ.1¥J ~ mz ~ffi.
The period oftimen ,the top tube drive sigtial is high
level.the down tube drive signal is low leve~atthiS:time the
top tube is conducted,and the down tube, s
voltage through the D-S pole of the top t1:l1:Je
flows through the load,and flows to the
inductance,produces the positive on the lett
om
UGATE
L
inductance.
Figure 9-3
the waveform of the top and
@ Tt-T2 BtrBJ~, lltl!'t:¥c~U:
~ffi.IC;jlijftilij~f=~-1'&jRJtf.J~Bi,
9-3 JiJTli;, UGATE 1t/'g{l£Ji§i, }ip;Ji
BtrBJ •
The period of time Tt"""'T2
inductance disappeared suddenly;
inductance will produce a reve
-110-
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·ve on the left.The enlarged drawing of the top and down tube signal waveform is shown in
9-3 after UGATE becoming to be 10w,LGATE will be driven to be high after delaying
ftiis period of time is also the dead time.
* nH~., ~"~.~~~U~~. ~W~~~~~~.~~~W.~, T~~
i&.J:..mzffHJ~;fi.iEti:~B<J~J§Z~ff!2ii LI 8j;fift;m~tl:DH.t ~1f.ii~~ S-D f&. 1J}i',m1oJ
(J(JJAtIi, llP LI B<J li:~ •
~ period of time T2,at this time,the top tube drive is low level and the down tube drive is high
I.~ the top tube is cut off,the down tube is conducted,the induced voltage with the positive on
right and the negative on the left inducted on the inductance through the right end of LIto the
flp.ws through the S-D pole of the down tube,then flows to the negative tenninal of the
that is the left end of LI.
*S PWM f@.~~¥J.J:tmOO 9-4 PJT~, -f.Rffl~I*J11'{~~, m{f!;~, ,(;H~{f!;~, ~-F
e real object of the single phase PWM circuit is shown in figure 9-4,is usually used for
m ory power supply,the bridge power supply,the bus power supply, the graphics card
e supply and others.
Figure 9-4
the real object of the single phase PWM circuit
f@.~~~:tmIil9-S JilflJ', -~ffl~ CPU ~IC.'~~.
o ~ect of the multiphase PWM circuit is shown in figure 9-S,is usually used for the
supply.
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,
\
Figure 9-5
the real object ofthe multi phase PWM circuit
The meaning of common English abbreviation in PWM circuit
SKIP, SKIPSEL: If'F.J:tiiJEo
SKIP, SKIPSEL:the work mode setting.
TON, RT, FS: 1J;jji~iiJE (IDt-1-Jt!.~.I3.~:li!!eJt~~~JtEi&JE~*)o
TON, RT, FS:the frequency setting(set the frequency by the resistance connecting the ground
or the power supply).
BOOT, BST, BOOST:
13*:ftliJJI4I, ...t1fG.~f;JJ.t.J*~o
BOOT, BST, BooST:boot-strap pin,the wJlt source of the G pole ofthe top tube.
UGATE, DH, HDRV, DRVH: ...t1f!Jl~
UGATE, DH, HDRV, DRVH:the tOlrtil
LGATE, DL, LDRV, DRVL: ~1f~LGATE, DL, LDRV, DRVL:the down
FB: &.ijt ir.Jli" JJt4J
0
FB:the feedback adjusting pin.
CaMP: &.1l1H~, fJjlE&~Et!..1W
COMP:feedback compensation,correct
OUT, VOUT, VO: ttl:HEt!.Bi~
OUT, VOUT, VO:output vol
PHASE, SW, LX: ~iftJJI4I,
~~ liJf~ Et!.mt~~~
0
PHASE, SW, LX:the phase •
tube/the inductance,forms the IOQP
CSP/CSN: rt!.~~IU' ..
CSP/CSN:the currentd
-1l2-
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lfRIP, CS: i1mt~1F~mi5bE. fJklll~I1!.¥jfEiiJEo
~
CS:the over current protection threshold value setting.the limited current setting.
-strap circuit
1IiJ:l, -ftJ:.Q~ N 14JiH. ;l't~Attffi~~§Ti;*teo E13TttWi!~Jt*~X1...t~
Ill, JL~mfl(t-J~Jt$*ffl7 E1l:l5*ffittR!*m~IJIR~~5.1Jo §~*J±JJtII36*-f:&:
ST, BOOST. U E1**ffi1J~1¥J PWM E{i.R!t!DOO 9-6 PJT7Fo
power,the top tube is usually N channel,the output voltage is from the common
:1he power chip is limited to the driving ability ofthe top tube.and almost all of the chips are
~ circuit to improve the driving ability.The name of boot-strap pin are usually
T.PWM circuit using the method ofboot-strap is shown in figure 9-6.
~-M, )I-mi1kiJI:*¥ § ** ffiJ~J~.:
gwe 9-6 an example,explains the principle of boot-strap:
+!*iii_1'f PQS ~E{i., Jltlt-t G ~~¥9:flE{i.. J5JT12A S fJk!fu"trtl:\ avo li5Jot. 19V B~
03, ~HllIr.:~ SV (t-J~ttJtlli VL, ~~J:t~$=fJkrg~~ BOOT1 ~E{i., ~,maffiJ~
y, 1JlljJ PC33 (t-J I JJ!p, ~JtJtJt. Jt~~fififl5V l¥JE!!ffio
supplies power to the high-end tube PQ5,at this time,the G pole is no power,so the S
OVAt the same time,B+ of 19V is input to PU3,the internal produces the linear voltage
ugh the internal diode supplies power to BOOTl,if skips the pressure drop,its still
m ofPC33,to charge it,the capacitor stored SV voltage.
00l'1 !* UGATEI t>!HJ:~Z9JjJ. £I±l~ili 5V (t-J~Jt:SP:, J!iU PQ5 B~ G fJk,
6 11~ SV,
!!tat
s t&~ OV, PQS (t-J14JilrpJl2Ajc~~Jm, 19V ¥m.i1 PQ5, PL4 ~
s II' I±l (t-J JtJ.3iii~ .L1T•
SV supplies the power to UGATEI,sends the high level about SV,is sent to the G
time,the G pole of the moment PQS is SV,the S pole is OV,the channel of PQ5
completelY,19V flows through PQS and PU to charge PC35,the voltage output by
. creased.
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B.
Pl._
".7UH PCWcoe::rr-tR1MN 5.5"
......-~VL
Typ: 175mA
Figure 9-6
PWM circuit using the boot-strap method
3 PQ5 ~tI:Il¥JJt!lli~~7t~Il1, flii;Jg 2V, l!1- 2V IfiJIl1;bQ¥UJt!$ PC33 I¥J 2 Jli\l, E13-r~
?&:AtliftE, 'BI1IJ;tfffit7 5V tJ(JJt!, JltfJ1-iJb-1- 2V, JiJTv)', Jt!$ft~tE.Wi:~ BOOn ~~
7g 7V, 7V m~~ UGATEI ~Jt!, PQ5 rro '5j m~;Jg 7V, ~ PQ5 -f*r.f Vo>Vs, *'§J~i:t
4.5V, PQ5 1*M:~~7t~~m, s ltatBi
!ftit, :pJ~~QJU PC33. ~QlIt~1f, :{£ PIA
(J'~ftftiMPJv)'~~¥U.iI!li 19V, 1I1~ OV tJ(J~.
33 tJ(JJt!.:M:i~¥i1f:'&:~j!j!, Boon Btl
~lli t!?8Jt4?7j(ili;~t PIA ftjfiiij 5V, liP 19i: UGATE1 1¥J~%t!?JM';~:lif~ OV, A:ifIi 24Y..
When the voltage output by PQS .is
increased,if this voltage is 2V,and 2V is ad
VIIIl_
of the capacitance PC33 at the same time
feature of the capacitance,it just stOreS
5V.at this time,adds 2V,so,the left 0
(that is BOOTl)will become to be
to supply power to UGATEl,the (jJ
also become to be 7Y.keeps PQ
than 4.5V,PQ5 keeps conducted
of the S pole will also follow to
highest 19V and the lowest 0'1.
not be discharged the vol~ Q
-114-
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~onn ofUGATEl is also that the lowest is OY,and the highest is 24Y.
e regulation circuit
-, iI~ FB .&tJtlJ!lJiinHf.JjJ}31-!fR~~~£I.:5HL -'=i~$i¥J¥ifE~ffbt$x, N
iI.. tU~*:tt~
in figure 9-7,through two sampling resistance connected by FB feedback pin
o
,compared with the internal reference voltage,so as to realize the output voltage
putational formula is
Vour=FB X (I+RtlR2)
, Rl f1l R2ff1~, D!~ Vour=1.6Y.
lis equal to R2,then Vour= 1.6Y •
.5V
.......~r-+-...---t:---- ALWAYSON
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protection).3.3V of standby voltage over-voltage protection waveform is shown in figure 9-9.
JL
'Ii
• At eoo.,lele MPos: 0.000,
M£ASUlE
--nil
fi5J1S
1~
~~
1
...
.:
:
.
.......... ;
~
. ..
CH1'
Figure 9-9
[)(){> 9.1.6
v
:
:
•
'l.?6V
~
;
:: :
:: ;
:
:
... ;
--nil
'~-"IS
:
JalM
_1-
:
:
:
.: .. :.
CH1
M
JJS
1
22-001-1210:18
<llJ1Z
. . : : :
7C
~
.3.3V of standby voltage over-voltage protection waveform
ttlii-ttillttlJ&
the current detection circuit
PWM E@.iJjiVS~MIl't*Id.I:I1~¥ilto ~i1mtll't, ~Jtpg$mffl OCP (i1¥m.{~Hf') ;t!tllJlJ.
ttld ~¥iIt((']1JJ:t~j1ijf'P:
RTI201A1B1C
BOOT I-----.J\A--.
UGATE 1----."""~~__1 ...
PHASE I-_-!-_L--+-:'':':'''....rrn.
LGATE 1---.!!:~~~i4.
PGNDII-----~
FBI-------=:.....--=--~ 9-10
-116-
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urrent,its not very precise.During calculating,we should use the maximum value of the
'n the data manual of the field effect transistor,and considers that the resistance value
d effect transistor conducting will be increased with the rising of the temperature,so its
certain allowance.The benefit of this way is reliable,and its the nondestructive over-
·on.
1±I1@,EHtffi, ~m l:ti 1tV1ti1V1tat, ~ Jt ~ Jr.5 ffl i*J WB~~'tr tI:J llX ItmJt !ltmA r ,
.iibffl~ft~lfi~ OV f~lt3f, r~ G f}HgZ9Jf§%iUgZ9J~ 5Y i'8'i1t-'f, !ltB1J:~~
0
~ ~iI, "1±I~~It~LfiM¥1¥-JIt1niimi1r~illi!X1!f!!}j)(It,
!fu-'tr:±lltffi:k~
0
output voltage is over or the output current flows through,the chip will use the internal
~rgit1. Ii mode.In this mode,the top tube G pole driver signal is turned off to be OY low
Ie driver signal of the down tube is driven to 5Y high level,at this time,the top tube is cut
tube continues to be conducted,the charge stored on the output filter capacitance is quickly
the ground through the down tube,the output voltage is closed.
: PWM 1t1&1fi, p:~t1F*~Jt m:IJlllto ..t "if G m~~~-@f~ YIN lIit1JIl3Wm
~"
, ~nder:in the PWM circuit,is strictly prohibited to remove the chip then power
e ot: the top tube is suspended,which will cause that YIN is added to the rear stage
the components.
• 1fi~*$1lr PWM It~ IC ~~If1=:A::f/6J1¥-JW3flPmJtr,
~~~.~),
PWM t~Al*.
~§~.~7.m:f/6J~~~~~r,.tI:J:f/6J~It~(.tI:J
~~Ifi~S~mT~~.Jtm~,
~S~~~~at,~JtI~T~~~~m
), JltIl'1'u.l±I E@.V1t./J', :m 3V #ftltE@.ffi, :A:#ftltB1 ~ mfIf1=:A: SKIP f~Aen
R
3V ft:tJt E@.ffi1¥-Jm tI1 E@.V1t~\ ~!l1JJl , j;§ ~JltB1-@ ~!Jf 1tJ.I:l$J El3 3V fJim Itffi
~.tI:IE@.:i)ft~\@i!l*,
~Jt~ SKI~ <1itfflICH ~tI1~ SLP_S3#~f1i~) jj
WM.~,.tI:IE@.ffi:f~,@.tI1E@.~*~o
051 ofPWM power IC can work in the different two modes,PWM mode and
.on mode) the purpose is to adapt to different sleep state and outputs the different
~ cqnStartt).There is SKIP# in the chip,is used to realize the mode switch,when
c' works in the pulse separation mode(SKlP mode),at this time,the output
as 3V standby voltage,it just needs to work in the SKIP mode when in the
P9wering on,the output current of 3V standby voltage must be
system voltage at this time is from the 3V standby voltage
Ui'J'etlt\IDust be increased,SKIP#(usually controlled by SLP_S3# sent
works in PWM mode the output voltage is constant,but the
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I. PWM.~ PWM mode
PWM m~rlt!ffi*:D1~fj~j]53L
~utl:llt!mt::k. PWM m~rl¥J~m:tmoo 9-11 PffiF. ~
$~ 299.4kHz.
In PWM mode,the voltage load capacity is strong.the output current is large.The waveform in
PWM mode is shown in figure 9-ll,the frequency is 299.4kHz.
2.
sKIPi#l;t (McitPfBJllMmit)
SKIP# mode (pulse separation mode)
J¥!.{ftlJ1fiijpg. PWM ~m~y, V!lJ4iI"IjtJj It!mt~/J'. SKIP#m~rl¥J~m:tmoo 9-12 ffiiF.
~$-rx. 34.63kHzo
Within the unit time,the less the PWM waveform,the smaller the output current.The waveform
in SKIP# mode is shown in figure 9-12,the frequency is just 34.63kHz.
"lIllWiEI
f4Jii.
5h1~";"""'''''''''''''''''.-...:f~~'''''~iftot1,a.v2ISIQHz
Figure 9-11
the waveform in PWM mode
Figure 9-12
the waveform in SKIP mode
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. A~M~~mit~ PWM fjtit~~: ~*Jrlffi'lZffif~iH?J1J~~o
(is in common use with MAX 1999) is the standby power chip with high efficiency
o\¢put produced by MAXIM company to use for the laptop.The main features:not
detection resistance; 1.5% output voltage accuracy;supplies the linear output with
maximum current with IOOmA;can output two path of PWM power supply:3.3V
~......''l!i voltage range of 4.5-24V;the choice of the pulse mode and PWM mode;over-voltage protection.
the pin name ofMAX8734A(the top view)
'on of the pin definition and common used pin
~ 51J1J!6~:lm1ll9-13 ffTlJ'o
e ofMAX8734A is shown in figure 9-13.
slB_lJjJtiJE)(~~ 9-].
'tion oftbe pin function ofMAX8734A is shown in table 9-1 .
• 9-1
MAX8734A SI.IjJ~;E)(
the definition ofthe pin function ofMAX8734A
iiible inputON3 connects to REF,3.3VSMPS will start after 5V SMPS being
le'inpuhONS connects to REF,5V SMPS will start after 3.3V SMPS being stable.
The main switch ofthe chip,the opening ofthe linear voltage.
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12
low noise mode controI.When SKIP# connects the ground,works in the idle mode,when
SKIP# connects VCC,works in the PWM mode,when SKIP# connects REF or is vacant,works in the
ultrasonic mode.
13
frequency selective input.When TON connects VCC,chooses 200/300kHz worlcing
mode,when it connects the ground,chooses 400/500kHz working mode(respectively corresponding
the switching frequency of5V,3.3V SMPS)
14
the bootstrap capacitor connection terminal of 5V SMPS
15
the inductance connected 5V SMPS.lts the internal low-end power supply rail ofDH5.LX5 is
the current detection input of 5V SMPS
16
the high-end G pole driver of 5V SMPS
17
the analog supply voltage input of PWM core.It needs a I capacitor bypass
18
SV linear regulation output.It can provide 100 current.If the voltage of OUT5 end is higher
than the LD05 switch threshold,then LD05 regulator is turned-off,and LD05 connects to OUTS
through a small resistance.
19
the low-end tube G pole driver of 5V SMPS
20
the main power input
21
5V SMPS output voltage detection input.When the voltage of this pin is higher than 4.56V.it
will replace the internal LDOS output.
3.3V SMPS output voltage detection input.When the voltage of this pin is higher than 2.91 V.it
22
will replace the internal LD03 outpul
23
ground connection
24
the low-end G pole driver of3.3V SMPS
25
3.3V linear regulator outpuUt can prov.'(ie
higher than the LD03 switch threshold,then IOOJ3
OUTJ through a small resistance,
the high-end G pole driver of3.3V S·ME~"
26
27
the bootstrap capacitor connecti
28
~
fft
~
~
N,C.
2
PGOOD
-120-
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ON3
3.3V SMPS f~tJMiJ1jA. ~~ ON3 ~ REF il'Oi1, 3.3V SMPS ~f-E 5V
SMPS ~~J§ Ja ZJJ
SV SMPS f~BMlltlA. ~~ ON5 ~ REF il'Oitf, 5V SMPS ~1£ 3.3V
SMPS a~J§ Ja ZJJ
3.3V SMPS ~~¥!rUp.j:P
3.3V SMPS &tjftWiA. ~ FB3 lim GND ~j~IJj])E~tll±J 3.3V, ~
FB3 ~~~ OUT3 *tJ GND z.rEi]I¥Jr:g~.§.7tlli~, Fi~~~~fJil2~5.5V B~
iiIiJIIWHti
SV SMPS &tJHlitiA. ~~ FB5lij~ GND ~;j$~JE:'futll±J 5V, ~~ FB5
~~~ OUT5 ~ GND z.rEi]B~r:g~.§.7tlli~, fj~1yp~fJil2~5.5V (j<JPJifril
_ttl
j1ffi~Xffif~H?f~"~JJ!P. PRO#m vee 1Jt, ~.L!:f;\jHF. PRO#m:l:iP.
IM", 1fJ6 f~UFJ1J"~
f~~fI5.;i:\~$JJ. SKIP#~±t!!.at, If1=1£~I*Jf~A, SKIP#m vee
IM"If1=t£ PWM m;i:\, SKIP#~ REF §x~£Bt, If1=?±~Ff~A
~.~~.A. TON ~ vee at, ~;j$ 200/300kHz IfF*~A, j~
i&1l'j~1f 400/S00kHz If"Fm~ (7t~IJ)(1Jiil 5V, 3.3V SMPS B~7f*
~.)
~~ SV SMPS 1¥J1t~. ~ DH5 I¥JI~rmH~~It~!fJL. LX5 t! 5V
SMPS 1¥J ltVft:ttld4tA
w ilM:a5• • ttl. 1iJ~~ lOOmA It¥t. :tm~ OUT5 ~Et!lli,~
005 **J1Illl, JJI1.. LOOS tiffia~litfi,
.-JJOUTS
*
1l LD05 JiIi)i-l'
fJf~.1' G .~f;IJ
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24
OL3
25
LOO3
3.3V SMPS O~f~~'Ir G m~i;I]
3.3V ~J},t.H~lli~~H:I:I. jjJtlHJ~ IOOmA r4!mt.
OUD ~Et!lli~
f L003 7f~f1llfL JJI) Z L003 frJ.ffi$~WT, jt- J3. LD03 illi1 "1
WJ*
'J' rgliIl.i!t~ftl OUT3
26
OH3
27
LX3
28
BST3
3.3V SMPS ((.]j@j~1f G ~&~i;lJ
i!t~ 3.3V SMPS a!Jr4!~. ~ 3.3V SMPS ((']r4!mt~~U~A
3.3V SMPS a!J 13 ~r4!~i!~g;jij
The electrical features of SHDN# threshold value in the MAX8734A data manual are described as
shown in figure 9-14.
Rising edge
mmR Inpul Trip Level
Failing edqe
1.2
096
1.6
1.00
The screenshot of the description of the electrical features of SHDN# threshold value of
MAX8734A
[~]
explanation
SHDN#tuJV,,~{ir4!.;y;: l:7Hft:ll:f~{i 1.2V, -1li73 1.6V, ~i'1i73 2.0V.
HDN# input threshold value level:the lowest value of the rising edge is 1.2V,usually is 1.6V.the
maximum is 2.0V.
SHD #~A~{ilt!.;y;: "fJf¥mllfQ;{i O.96V, -~73 I.OOV, .~73 I.04V.
SHON# input threshold value le\lel:the lowest value of the falling edge is O.96V.usually is
I.OOV.the maximum is I.04V.
MAX8734A 1'flti:tt&-¥JJtep~ @
In the MAX8734A data manuil
described as shown in figure 9-1
0.8
2.3
01'3. ONS Inpul Voltage
Figure 9-15
v
the screenshot 0
[1m]
Explanation
ON3. ONS .AE!
•
ON3 and ONS inp
ON3, ONs.A
-122-
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mput oltage:when it i 1.7 - 2.3 V,delays start.
4* It:
T 2AV 111, I'UtJFJtlo
input voltag :when its higher than 2.4 V,opens directly.
~lcli tllfl:f:l~fflJWi1ffif*:tPI~{r:IrtJiTI~W't1j1:1i~!lDI~ 9-16 J5fr7.f;o Witl:Jrt!.
'llI:I'I:[;-~-flitJfli";IJi:J:llif~H?: ~/Hll 8%, -mHil 11%, l7?l::k1t 14%0 {VtlYD, i&
JJ 3.3+3.3*1 I %=3.663 V ifJtf~iH?o
8734A data manual,the electrical features of over-voltage protection threshold
shown in figure 9-16.When the output voltage is higher than the set voltage to a
it will start the over-voltage protection:the minimum value is 8%,usually is
• urn value is 14%.For example.sets to be 3.3V,achieves 3.3+3.3* II %=3.663V,then to
FB3 or FB5 with respect to nominal regulation point
+8
+11
+14
the screenshot of the description of the electrical features of the over-voltage
protection in the MAX8734A data manual
A (j(jU~M9='~~I±iXffi~1?~flltr-JEt!/=t*fttrai~~DOO 9-17 fifr7.f;o ~D;~Hiltr
li~lt!ffil¥J 7()O/O (-ftfll), utJSz;lJxllif*1?o
8734A data manual the electrical features of the output under-voltage protection
described as shown in figure 9-17.1f the output voltage can only reach 70%(the
f:the set voltage then it will start the under-voltage protection.
FB3 or FB5 w11h respect to nominal output voltage
65
70
75
screenshot ofthe description of the electrical features of the under-voltage
~:ecti'on threshold value in the MAX8734A data manual
PJ.:& oun ~ LOO3 tr-JtJJ~It!i&:tmm 9-18 ffi7fi: OUTS/3 Mi:ct
~i$lt!ffitifl ilia
of OUT,LOOS and OUTI,LOO3 is shown in figure 9-18:when OUTS/3
ill r;place the internal linear voltage output
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FB3/FB5 connects to the ground,You can choose a fixed output 3.3V and 5V.If FB3/FB5
connects to the resistance divider between OUT3/0UT5 and the ground,then it can adjust the output
in the range of 2-5.5Y.The specific calculation formula is VoLJFVFB o CRl+R2)IR2. is shown in figure
9-19.
MAXIM
M~8732A
MAX8733A
DL
MAX8734A
GND
00 9-18
MAX8734A I'f.J OUTx!3 LDOx t.m~oo
00 9-19
MAX8734A 1'f.J!iu~l:!:lffi.iJlfiJOO
Figure 9-18
the switching graph of OUTx and LDOx of MAX8734A
Figure 9-19
the output voltage regulation diagram of MAX8734A
~~~moo:tmoo 9-20 JiJT7J'o
The typical application diagram is shown in figure 9-20.
3.
-f6:If'Fat~
1r $'G~ V+!iu"U A, V+t£JJJ::J:I!m.7}ffi.A.~~;'HmJli*
~ J:I!.If~ SHDN#fF ~7f JI5 •
MAX8734A J14~;a:~ L005, PiJ'IlIS!6t1Jtmlll9-21 JiJT7J'o
First,V+ inputs,V+ through the: resistance divider input or the high level sent by the external
acts the open for SHDN#,MAX873~A will produce LOO5,the internal structure is shown in figure
9-21.
-124-
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.... lUllV
11LI1-----=i
OllTll----=--==-----...J
'\r-..;;,."...j
'IaI---I
tal
'1c
I~I----+--
.'---l
'""
III 9-20
MAX8734A A~}§Zm 1*1
the typical application diagram ofMAX8734A
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r---------1!:.v.--------, PGOOO
~AXI~
MAX8l32A
MAX8133A
MAX8l34A
TOIl
4):----It-;:=~==;-n
(UlIAXII·.:.:T.I4
5V
SMPSPWM
j(!"lB
Vee
009-21
MAX8734A P3$~OO
00 9-22
Figure 9-22
Figure 9-23
-126-
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REF being stable,outputs the linear voltage LD03 of 3.3Y.The timing sequence
ofV+,LOOS LOO3 is shown in figure 9-24.
r'T~-_-r-_~'~W<:!!!!9rJ2~Al3AJ~'~">:22~
..
v+
lOV
..
"
10V/div
O ~. ,f".-:.-
-t;-...-!""-;......-4 LVD/05
:: :' :I" :,. :_.'-'--1 :D:~v
o r""'-¥-t"l-+i4-i-m..,.f1,....i,.'+.. . . . ..;...~~ 2V/div
~I....J
o..._:
......
: J7~"":":' ~~:~...-.-.
--I
o t'·: _..
I
.
, :
I
:
:
.
~~jdiV
•
.
400llS!div
[II 9-24
MAX8734A ~tt il!llillt
rr
the timing sequence of the linear voltage ofMAX8734A
DDects Vee,ON3 connects REF,is shown in figure 9-25,so,the chip produces PWM
o SV first,after being stable,then produces PWM power supply of 3.3 Y.
5 .~, :tzolll 9-26 ffii.f;, i!~~7E~tl:l 3.3V ~ 5V. 3JiJf1:f4TItrl:l:\m~JE
• •Iti PGOOD,
vee t£j:j: IOOkn
5 are connected the ground,is shown in figure 9-26,chooses the fIXed output 3.3V
uts being stable,the chip open drain outputs PGOOD finally, is pulled up by the
m
x.fJL.
~:
FB3
--
100kQ
PGOOD
1119-26 FBD
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Control timing relationship
MAX8734A ~*IJlltff*~~}(m!;&.9i!.;&9-2.
The original of MAX8734A control timing relationship in English is shown in table 9-2.
Table 9-2
MAX8734A control timing relationship(the original in English)
SHDN
(V)
VON3
(V)
VaNS
(V)
LD05
LD03
5VSMPS
3V SMPS
Low
X
X
Off
Off
Off
Off
"> 2.4" => High
Low
Low
On
On (after REF powers up)
Off
Off
On
"> 2.4" => High
High
High
On
On (after REF powers up)
On
"> 2.4" => High
High
Low
On
On (after REF powers up)
Off
On
On (after REF powers up)
On
Off
"> 2.4" => High
Low
"> 2.4" => High
"> 2.4" => High
High
On
High
REF
On
On (after REF powers up)
On (after 3V SMPS is up)
On
REF
High
On
On (after REF powers up)
On
On (after 5V SMPS is up)
[111m]
Explanation
'!lOW: SHDN#t:11~1t:sy.,
JjJ3~, 1'~ ON3 ~ ON5 ItBi~1~, i:!G'tj: 5V, i:!G,tj: 3V, 5V 7f
;kFQ.1L5'!, 3V 7f*It~~~*~, &~!ifilili.
If SHDN# is low level,then,no matter what ON3 and ON5 iS,the linear 5V,linear 3V,5V
switching power supply and 3V switching power ~ply will be closed,there is no output.
'!ln~ SHDN#::kr 2.4V, W ON3 ON5 .~~a;It!.~, ~115V, ~tt 3V ~:fJjz7f~ (~
tl: 3V ~tt REF ~J;EJ§~l;JJ), 5V, 3V 7f
If SHDN# is higher than 2.4V,and ON3 an 0
el,the linear 5V and linear 3V will
be opened(the linear 3V will start after REF be"
switching power supply are
closed.
'!lO* SHDN#::kr 2.4V, ON3 ON5 fi]
;k E\:!.iliflflI~1T7f, ~ Itffiffi ili •
If SHDN# is higher than 2.4V:ON3 arid B
supply and 3V switching power supply will
"!LO* SHDN#::kr 2.4V, ON3 ~
rt!.¥Jh!~ff~, 5V 7f*It.i£~mo
If SHDN# is higher than 2.4~
and 3V switching power supply are;
"!LO* SHDN#::k-F 2.4V, m
rt!~mtflt7f~, 3V **ItKU
-128-
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#I• is hi her than 2.4V' ON3'IS Iow level.ON)~.I high
. level,thc linear SV.the linear
.
3V
ng
. I')Illg power supply i closed.
N#pow r supply are opened '3V SWltC
*7- 2.4V, ON3 ~~Et!.!jL, ONS l!H~ REF m~t 0JH1sv, t:JH13V, 3V 7f
~, SV 7f~rt!.It~tE 3V ~~J§Wm~J.
1#• is higher
than 2.4VON3'IS h'Igh level.ON)- connects REF pin.the linear SY.the linear
.
tchlDg power supply are opene,)
d ~V sWltC
. I'1ll1g power supply will start after 3V bell1g
.
SBDN#:kf"- 2.4V, ON3 i!1l REF J]t;p, oNs1~jl6!jEg~t ~JH1sv
~JH13V, sv 7f
~, 3V 7f~rt!.ft~tE SV ~~J§fI}JSi0.
# is higher then 2.4VON3 connects REF pin.ONS is high level,the linear SV,the linear
'tching power supply are opened.3V switching power supply will tart after SV being
TPS51125~;tfi
analysis ofTPSS112S
5~~~.ffl&~~~~~~-~ffl~~~*~.~m~IT~~m~~~~n
allo ~If1:JtBs:~ 5.S-28V, ml±llt!ff~ 2-S.5V Q)'ijlJJ, 1J<ff 5V fa 3.3V rm
~~5~ili, ~~~~~I%~2v~~lt!ff~I±l,~~urr,~IT,u~~
JjJMo 'Emilt 270kHz (fl VCLK ml±lQ)'ffl~~Z;tJ~r1:tfl§~fj-ITI:I3lij, 1:£/1'
!Ef.1:3lt* tro tf~ r ~ffltffl ~ J§ 1.1 1t!?Jj~~ 7f1c ~~IJH& ~~ 19J It! IT. TPS5 I125 5f.
~1fi~:JHi1~Ha~~1tfmffi%. Out-of-AudioTMmAtH~t*fF/1'{g~:E.w. 7 111
M.T~~~$tl PWM •
economical and efficiency dual channel synchronous buck controller produced
use for the standby voltage of the laptop.The voltage is 5.5-28V.the output
adjustable with SV and 3.3V two path of IOOmA linear voltage output and 2V
o ilt with internal error I%,integrates the over-voltage,under-voltage and overthe function of over-heat protection.It provides VCLK output of 270kHz to
boOtstrap circuit,in the case ofno reduction in the working efficiency ofthe
the gate drive voltage for the rear power conversion switch.TPS51125
ien response and provides a combination of enable signaI.Out-ofoperation realizes low noise and its efficiency is higher than the traditional
• (8Jl
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Figure 9-27
the name ofthe pin ofTPS51125(the top view)
TPS51125 i]IJl!IJJE5C~!.~ 9-3.
The pin definition ofTPS51125 is shown in table 9-3.
• 9-3
Table 9-3
TPS51125 sIJl$~)(
the pin definition ofTPS51125
Channel I open and current limit set pin.The direct grounding closes the output,sets the
threshold value of the over-current through the resistance grounding
2
the feedback of channel 1
3
2V reference voltage output
4
the frequency setting
5
the feedback of channel 2
6
channel 2 open and current limi
•
ding closed the output,sets the threshold
value of the over-current through the
7
8
9
10
II
12
13
the main starting sl
-130-
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open the linear when through the resistance grounding,c1ose VCLK and ready to open
grounding,close the whole chip.
Ode and pulse mode select pin
power supply input,is the origin of the linear voltage power supply
voltage output of 5V
ency output of 270kHz,is used for the boot-strap circuit of 15V
tube drive of channel 1
pin of channel 1.Function:<Dthe top tube conducts the 100p;(2)the current detection
. g pin of channell,the boot-strap terminal
ojtage detection of channel 1.Function:<Dvoltage detection;(2)is used to replace the
e~
......~....,..
#
----,
~_~
)E )l..
iii! 1 7ffi3~IIIHAt1i)E~ • .m~~±I!!.*I~HiJ"Ul±I, illi:ctEE!.~.EI.*±l!!.
\ijEitmtfIJil
ilil27ffi3~~~1ijE~ • .m~~~~~~I±I,~uEE!.~~±I!!.
ii~u.JJil
;1m2 tIfIl±lft!.llittl~. i'Fffl: <Dft!.llitt$J!~; ®FllT~~~ttEE!.
Ii.
·~2~~~.~ffl:<DL~~iI~~;®~mt:~ft
llacJ::J)""~f;b
,ft. fFJ:lJ:
®.~I!'t1T7f~1t, m-l-1T7f VCLK ~
~~~~) Rn7f~~,~~V~K~m~1T7f
1. ~mtil;1f
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l'~ H,:rlJll'l'.
~ ENO l'I~I;'9Jfat~'i.i£~nl~ 9-28 pJT}i;: ~ ENO n~L{Uld\T­
fJl: I·NO lUll k r O.8V II·JJH·lrJG'~E. ~I;n VCLK; ENO 1t!1li:kr 2AV
I K.
hI \11 rr 11_: d It \ Illanual.the threshold value of ENO described as shown in figure 9.' "h II \h ,)lta' l rENO is Ics' thun OAY,th chip will be closed;when the voltage of END is
III, h'l \han 0. \, p n th Iinc'lr und do 'cs VCLK:when the voltage of ENO is higher than
l ,'I 'II, til lin ar and
l
~;.=. ~ ;. . :~:
Ibng
1'tI
li'II\'-_
LK.
til
JI-"=;.;.;;U;:.;;1dOWll;.;..:
TP
Il-_~_: l;d :: [J
11
fth d
ription of electrical features of ENO threshold value in the
TP 51125 data manual
NTRIP#tt<JlJJmtli~oo 9-29 PJT7F: ENTRlPl {O ENTRlP2
l'i~un:
-_
til
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II Inlh' L'hip is ~11lI\' 11 ill Ii 'lire 9- O.
I FU"'. IJIII'III 11 iV, 'J, (J { EN iJ~, VIN )t;~~¥,r~
II,; n~JII·.'t' :l:·I'I(J)X.~'I1'III~Au;i,j, ·lvml]/Clt. VREG5-t1l
t.th n produ' . VI ELi''',L shown in Ii 'urc 9-31 ,aftcr EN being
n 1.lh II
IUlIIII.JBH~ ~
I EF Is inpllt I th' invcrtctl input terminal of the
• ntrol. Ih· pI' ltillction ol'VREG5 lind VREG3.
n~ll!. !1~·t/I·JUd£UIII·1 () 2 mIJ··: V 'LK 1':1 270kHz ~jz
[ I ~I~ O.06V (~Q 'II! !I'I) "
nu Ith I 'Iri 01 l'clItllrCS or V LK de. cribed as shown in figure 97 kH I 4.9. V in Ih • high Icvcl.i. O.06V in the low levcl(the typical
. - ' - - - - - - - l - { " J VRCG3
h m tic diagram ofthe production ofVREF and VREG* in the
TP 51125 data manual
4.84
4.92
175
0.08
0.12
270
325
v
kHz
ription ofthe lectrical features ofVCLK in the TPS51125
d
manual
2
~.
&a. VCLK ~i~E!.Jf, VOl t&i:2:
:b~
(~.-.
~~ IOV. IOV
sv
2 !t
.m.>
)'fifl!.. ~hhS
sv ~i:2: 04.
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33.Firsl,VCLK is low level,VOI charges CI through DO.5V.When VCLK comes,4.92V add
5V(ignore the diode voltage drop) is IOV.The voltage of IOV flows through Dl and C3 voltage
rectifier filter,then charges C2 through D2.Add again is 15V,outputs 15V(the measured voltage is
between 12....... 14 V) through D4 and C3 rectifier fi Iter.
VCLK'
V01 (SV)
r r
<J--...-.£*----+~~__._____E'*_ ........._e~~__t.
C3
m
1000F
1000F
PGND
PGND
Figure 9-33
2. *'@iil~~$tJ*~
C3
T
15V/10mA
luF
.&
PGND
the boot-strap circuit of 15V
the open signal control relationship
TPS51125 ((.J7f Ja f~ -'%~*,J;k~~)cJj~m~ 9-4.
The original table in English of the open signal control relationship of TPS51125 is shown in
figure 9-4.
Table 9-4 the signal control relations •
ENO
ENTRIP1
ENTRIP2
VREf
GND
Don't Care
Don't Care
0If
RtoGND
orr
Rto GND
On
orr
orr
R to GND
orr
On
On
On
On
On
On
RIo GND
On
Open
orr
Open
On
Open
orr
Open
On
On
On
orr
orr
On
On
On
On
(fi~l
Explanation
~ ENO J9*!1!!I11, :f'lf
ii}iifi 1, imil2, VCLK ~;klil.
When ENO is ground
is.VREF,VREGS,VREG3 c
~ ENO imj1Et!.~.lill:tm,
-134-
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1~ ilil2 VCLKit~I~.
ois ground connection through the resistance.and ENTRIPI and ENTRIPI are low
•• 05 VRE03 are opened,channel l,channeI2,VCLK are closed.
~m~:i1k, ENTRIPI :Ri@i, ENTRIP2 791~1J-.t, jj]:i!r 2 jfO VCLK :WZ;;Clfl, jf;
o is ground connection through the resistance,ENTRIP I is high,ENTRIP2 is
ana VCLK are closed,others are opened.
~1Sil~:i1k, ENTRIPI :R1~, ENTRIP2 7:Ji@iot, Jmm 1 jfO VCLK fIJi:!JClfI, jf;
o is ground connection through the resistance,ENTRJPI is low.ENTRIP2 is
and VCLK are closed,others are opened.
• ~JtISJl~:i1k. ENTRIPI jfll ENTRIP2 ~~79i'liJM, VCLK ~lfI, jf;1lt!.:i:$1J7f.
o is ground connection through the resistance,ENTRIP I and ENTRlP2 are
• closed,others are opened.
~, EN1RIPI ~ ENTRIP2 ~:>':J1ltflt, W3-t-immlO VCLK Wi:;;Clfl, ft:1ffi1J7f.
ois vacant,ENTRIPI and ENTRlP2 are low,two channels and VCLK are closed others
~, ENTRIPI ~tli. ENTRlP2:>':J1ltflt, .R1fimm2~~lfI,
ft:1t!!.~~1J7f.
(;) is 'Vacant,ENTRIP1 is high,ENTRIP2 is low,only channel 2 is c1osed,others are
, EN1RIPI ~flt. ENTRIP2 :>':Jiiiflt, iQiil I jfll VCLK ~:!JCltI, jf;1ffi~1J3f.
~C8n1:,ENTR.IPl is low,ENTRIP2 is high,channel I and VCLK are c1osed,others are
~m'RIPl .. ENTRIP2 ~:hJ~fIt,
:i:HlI1T7f•
• wcant,ENTRIPl and ENTRIP2 are high,all ofthem are opened.
A1.RT8206B
~W~T~(~.#~~~flm0~)~~~~m~~~~, ~~~
,~ SV 70mA ~tltJ:±l. iiJti~I§I~t*f:I:j 3.3V 13 5V !!,IG 2V iU
A,fLlI: 6-25V.
Stanaby power supply chip produced by RichTek,the internal of the
ator module,which provides the output of 5V 70mA.It can
olmge of 3.3V and 5V or 2V to 5.5V.The range of the main
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RT8206A1RT8206B i31JJt4J~f$J9itmOO:tllJoo 9-34 JiJTlJ'o
The top view of the pin name ofRT8206A/RT8206B is shown in figure 9-34.
!!~I~ffi~~
REF
TON
VCC
ENLDO
NC
VlN
LDO
NC
c:J
N
N
Q
~
N
W
~3§1~~ffi~i
,
BOOT2
LOATE2
POND
OND
SECFB
PVCC
LGATE1
BOOTl
REF
TON
VCC
ENLOO •
NC
VIN
LDO
NC
c:J
,
BOOT2
LOATE2
POND
OND
NC
PVCC
LOATE1
BOOTl
a..- ........ - - - >§m::EQzj!!w
m>L1.;;l§w
~-------
m~f!lffi~~
ll.
gi
WQAII-32L 5x5
WQAII·32L 5x5
(a) RT8206A
(b) RT8206B
1119-34 RT8206AIB i31 JJt4J ~ f$ (J9i fm I~D
Figure 9-34
the pin name ofRT8206A1B(the top view)
RT8206A1RT8206B i31 Jjip:tJJff~~)(£~ 9-50
The definition of the pin function ofRT8206A1RT8206B is shown in table 9-5.
• 9-5 RT8106A1RT8206B 5IJJP~)(
Table 9-5
the pin definition ofRT8206A1RT8206B
2.0V reference voltage output tenninal
the
2
switching
frequency
setting
connects
VCC(200kHzJ250kHz),connects
REF(300kHzJ375kHz),connects GND(400
3
the switching power supply input,conn
LOO module open
4
low
level.LOOIREF is closed
5
the vacant pin
6
7
SV 70mA LDO voltage output,
is c1osed,and through internal switch 0
SMPS
8
the vacant pin
9
10
-136-
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eedback inputWhen FBI connects to vee or the ground wire,SMPSI is the fixed
Ode'when FBI connects to the resistance partial pressure between VOUTI and
the output voltage to be 2"'S.SV
ell good signal output,when SMPS I output voltage is
less than the standard
es to be the low level
signal input.If ENI is high level,SMPS I is opened,if its low level,SMPS I is
REF,8MP8l is opened after SMPS2 working
driver signal output tenninal
is vacant pin
of low-end M08FET driver signal
82 power good signal
• g end.connect the ground:custom mode.Connect REF:ultrasonic
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2.0V ~f1t El!ffi~1trlli~
I
REF
2
TON
3
VCC
4
ENLD
0
S
NC
~Jlt4J
6
VIN
~ Jt ±:{jt EI! A~!fn'tA
7
LOO
Jlt4J
1ft
~
~
8
NC
9
BYP
VOUT
I
10
II
FBI
12
[LIM I
13
PGOO
01
14
ENI
IS
16
17
18
19
20
21
22
23
24
UGAT
EI
PHAS
EI
BOOT
1
LGAT
EI
PVCC
SECF
B
GNO
7f~~~i9:.'ii~, ~ VCC ( 200kHz/2S0kHz ) •
(J00kHzJ37SkHz), ~ GND (400kHz/SOOkHz)
~
REF
*~~~~EI!~A. ~~H~~~-~I~~EI!~
LOO f~:lR7f Ja {§ %~ A, ~ EI! f, LOOIREF 7f Ja , flt ~:if.
LOO/REF ~ If!
SV 70mA LOO El!lli!fn'tlli, ~~U1t~Et!. SV r=~J§, LOO m~1(If!,
:J:f:if1li1I*JW I.S~B~7f;jCtJ]WdUEi35'~W SMPS rz:~B~ sv {;!tEt!.
SMPSI &1#!.Ao lt~ FBI ~U VCC ~!i!!~B1, SMPSI :7:11I!1J;E~'trl±l
sv Et!.ffim~; lt~ FB I ~U VOUTl ~!i!!Z.rEi)~ Et!.~1l7tffi, iJJ I;:J. i~m.~-:
lli Et!.ffi~ 2--S.SV
SMPS I tiD tJj Et!.~ ISlliI
SMPSI Et!.~1LTm~.tfj, ~ SMPSI .tJjEt!.ffi1~T~;r-l1E7.S%II1. Jltf§
-'% ~~:7:11~ Et!.-'F
n
SMPSI 'fj!~-m.li}.x.o
SMPSI ~mo 1m.~
SMPSI 7f~, {~ft!.f.
SMPS2 IfFJS7fJE SMPSI
,l :J9i\!fji:@.-'F
~Yitij MOSFET !jg~
(RT8206A)
PGNO
LGAT
E2
BOOT
-138-
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.SMPS2 UHI.1I,.t:.J .,u... .uJ
thre hold vailic of ENx and ENLI () dl:scrihcd us shown in
0.6
1.8
2.6
1.2
0.94
2.3
1.6
2.0
1
100
V
V
~~tIJIJ1j£11~ I I
o th d scription ofth
lectrical featurcs of ENx and I~NLD
shold valu ofRT8206
2.3V MIiJ
If;j'
~lb~em 18 2.3
idJ 2.SV !;AJ.:II-j, JF J(: SM PS"
lay starts'when its higher than
1.6V. :kii 2,OV •
1) j 1.2Y. the typical
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2, ~*,JII1J* control timing sequence
RT8206A1RT8206B B~t£*IJIltFf~:tmU&.9t!.* 9-60
The original in English of control timing sequence of RT8206A1RT8206B is shown in table 9-6.
~ 9-6
RT8206A1RT8206B 1'rn~*IJII1J¥: (~)cJJ~)
Table 9-6
the control timing sequence ofRT8206A1RT8206B(the original in English)
$V SMPS1
I 3V SIIPS2
LDO
ENLOO M ' VON< M I V.w,lV)
x
X
Low
Low
'>';N' High
Low
REF
'>';N' High
Low
High
">';N' High
REF
'>';N' High
REF
I Low
I REF
Low
'>';N' High
">';N' High
I
I
REF
High
I
High
Low
I
High
REF
I
HIgh
High
,
,
'>';N' High
-">';N' High
'>';N' High
Olf
On
(aft9r REF DOwers up)
On
(aft9r REF DOwers up)
On
(aft9r REF powers up)
Olf
Olf
Olf
Olf
Olf
Off
Olf
On
On
Olf
I
On
Olf
(lIIlIlr REF DOwers up) I
I
On
IIlllBr REF powers up) I lalter ~~S2 on) I
(aft9r REF powers up)
On
(alter REF powers up)
On
(eller REF powers up)
On
feller REF powers up)
Olf
Olf
On
~O<
On
(alter SMPS1 on)
On
On
i
On
[Mml
Explanation
3 ENLDO 791IUt, ~p, EN) ~ EN2 tro~~, LDO~ 3V, 5V 7f:JC~~~$:JC1~0
When ENLDO is low,no matter what the state of EN) and EN2 is,LDO and 3V,5V switching
power supply are closed.
3 ENLDO 79*r 2V (I{J~lt-SJZ, EN1
iOOm~llt, LDO 1£ REF ~J:E:)§~tf:l.
5V, 3V 7f:JC~~ff:JCl~o
When ENLOO is high lever more than 2l
being stable,5V,3V switching power supply
3 ENLDO 79*r 2V tro~lt-SJZ, E
tf:l, 5V, 3V 7f*~~ff:JCf:flo
When ENLOO is higher level more
after REF being stable,5V,3V switching
3 ENLDO 79*r 2V a9~lt~,
5V 7f:JC~~~f:fl, 3V 7f~lt.tF
When ENLDO is high level m
being stable,5V switching power
~ ENLOO 79*r 2V lWiffi
i±J. 5V, 3V 7f~lt~ik~fflo
When ENLDO is high le.v.el
-140-
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REF being stable SV,3V sWitching power supply are closed.
~ ENLDO ;J~J*T 2V ~iWilt-'¥, ENI ~ REF}JiijJ, EN2 ·tM~ REF Jjj;p, LDO 1£ REF ~5E
1£ SV 3V 1f~It$t~~tf.I.
en ENLDO is high level more than 2V,EN I connects REF pin,EN2 also connects REF
00 is output after REF being stable,SV,3V switching power supply are closed.
§ ENLDO ~*T 2V a<J;iiIt-'¥, EN] mREF n!IJ, EN2 ~iWiB~', LOO 1:£ REF f.~JEJ5~
3V :m:tl7fJS, 5V:(£ 3V ~JEJ5{I}~"iJ I±i
When ENLDO is high level more than 2V,EN] connects REF pin,EN2 is high,LDO is output
REF being stable,3V is opened directlY,5V is output after 3V being stable.
~ ENLDO ~*T 2V a<J~It-'¥, ENI 73i<lJ, EN2 73f~8t, LOO 1£ REF ~JEJ5!ffltrI±i,
0
~Ja, 3V f£~tf.I.
When ENLDO is high level more than 2V,EN I is high,EN2 is low,LOO is output after REF
stable,5V is opened,3V is closed.
§ ENLDO ~*T 2V a<Jiiilt-'¥, EN] ~?iJj, EN2 ~ REF JJ!lJBt, LOO 1£ REF ~JEJ5~"tr
sv :fttl7fJS, 3V:(£ 5V ~JEJ5~~ I±i
0
~ ENLDO is high level more than 2V,ENI is high,EN2 cormects REF pin,LOO is output
being stable,5V is opened directly,3V is output after 5V being stable.
~ ENLDO ~*T 2V a<Jif6It"F, ENI 73rf!lJ, EN2 i1?73i<lJBt, LOO 1£ REF ~.JEJ541Jtr
fiV." 3:V ~~:m:tl7fJS.
"Wlil~ ENLDO is high level more than 2V,EN I is high,EN2 is also high LOO is output after
jog stable,5V,3V are opened directly.
Analysis of the memory power supply chip
* introduction ofthe pin definition and common pin
-14:1-
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ISL88550A
(28 LDTQFN)
TOP VIEW
~
~
OVP/UVP
REF
:l
Z
Q
!E~ g~
~~
-,
~~
-,
ILIM
~~
POK1
5 •
.,
-,
.,
!~
Figure 9-36
•a.
i2
0
c
Z
~
1i
z
t'
a.
0
0
>
~2=D~ BOOT
~1-9"
...
PHASE
[~:
UGATE
.... --
~1-7· YIN
.16
OUT
the name of the pin ofISL88550A(the top view)
ISL88550A ;;;1 JJt;pJ1Jfj~}:EJO\!.~ 9-70
The definition of the pin function ofISL88550A is shown in table 9-7.
• 9-7 ISL88550A S1IIilJ:.lE)t~
Table 9-7
I
frequency
the table ofthe pin definition ofISL88550A
selection:TON
connects
AVDD(200kHz),when
its
in
vacant,connects
REF(4S0kHz),connects the ground(600kHz)
3
2V reference voltage output
4
the limiting current setting
5
PWM power good
6
LDO power good
7
8
soft start
9
-142-
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~~ voltage output,connects to VTTS to keep it to be half of VREFIN
mvoltage ofVlT voltage regulator,in the application ofthe memory power supply.will
ect it to PWM output tenninal
back of PWM.When it connects AVDD,fix output J.8V,when it connects the
i.lt 2.5V.If its adjusted by the resistance partial pressure,it can output the voltage
3.5V
• ,power supply input,the range of 2"""'25V
pin ofPWM.the function of the top tube drive loop and the current detection
~ply ofthe chip,the origin ofthe driving force ofthe down tube
it connects AVDD,low noise forced PWM mode,when
n
I :input A the rising edge clear fault latch,connects the high level open chip
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-
--
R F
2V Jt~~ 1l!,lf~JiJ III
4
IUM
fJk ~~ Il!, ~!JE & ,~
5
POKI
PWM ll:!.ilJ;fH
JlW
~
if!.
¥1f-
6
POK2
LOO t1!.i}gH
7
STBY#
!!
8
SS
9
VTTS
VTT rt!.ffif&~~4B~.A
10
VTTR
f;t. ~ iliHtt 'tffi , {fi.!¥i VTT - ff
11
PGN02
~:il!!
12
VTT
~~ E@.ffi4B~ I±l, i!~~u VTTS f~z. {~M'73 VREFIN Et-J-*
13
VTTI
14
REFIN
15
FB
16
17
OUT
VIN
18
UGATE
PHASE
19
20
~
STBY#~f~lI1, VTT ~lltrc~,
REFIN I¥J-~
PWM I¥J&~. 1t AVOO Bt~);E4B~1±l I.8V, ~±t!!.Bt~);E4B~tl:l
2.5V. iI~ItISlHtff~iJtI~i!, PTIV-~~:±l 0.7-3.5V z.rEi]Et-J~lli
PWM B<J.l±Iltffi*~!dtt AIt''A, 2--25V m:~
PWM B<JJ:'lf~i;fJ
:±-m
PWM B<J*DO. J:'f~i;lJIEl~IV-&ltmt~~H'Fffl
PWM B<Jr"l:.i!
22
23
LGATE
VOO
PGNDI
24
GND
filtlk
fil*&
25
SKlP#
26
AVDO
SHONA
#
28
¥. ;I§ii ~ll~
VTT.ffi~Et-J • .AE@.lli, a~~~~~ffl~, .3~re~i!~~
PWM _I±l jjjij
~~!II~i1t ~ffi4UlJ.A, ffl Tir.J~ VTT f-O VTTR, B ffJ 4B~ ttl a~ ~ffi~
~.3Tffi_
27
51-.
~.Fci\lJ
BOOT
21
-
;e;J:t B<J~,g,
I~D
JJt~.st
LOO
TPO
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.9-8 ISL88550 r..J7f~1~.!i5-~iliIJ*~
(~3tJjj[*)
the open signal control relationship of ISL88550(the original in English)
IttDNAI
GNO
AVOO
STBy,
BUCK
OUTPUT
vn
X
OFF
OFF
OFF
(Discharge 10
OV)
(Tracking Y.
OFF
ON
GNO
ON
VTTR
REFIN)
(High
Impedance)
AVOO
AVOO
ON
ON
~._-
ON
~
-
iNA# COnnects the ground,no matter what the state of STBY# is,PWM,VTTR are
also closed(discharge to OV).
NA#~ AVDD, STBTY#~fl!!Il1, PWM til VTTR t1~1Jff, VTT ~*I~ (j;,J
SBDNA# connects AVDD,STBY# connects the ground,PWM and VTTR are
Will be closed(the high resistance state).
#~ STBY#fII~ AVDD 111, PWM, VIT, VTTR :i:$1Jff
0
iNA# and STBY connectsAVDD,PWM,VTT,VTTR are opened.
troA~mzffl:tulI!l9-37 ffilfi.
51
lication ofISL88550A is shown in figure 9-37.
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ISL88550A
OYPIUYP
-U---IAVOD
5Y BIAS SUPPLY
CI: OPEN
YDD
S5
TON
YIN
C8: bl0~F
~
SKIP'
BOOT
Ql
GND
Ll:
FALCO ER13l19
1~~H.3~ ~
UGATE
VODQ
1.8V/12A
STBY'
PHASE
C11
Q2
LGATE
12mO
"'='
R2
1_
R3
1_
cn
C12
IZZO~F IzzoP' I
SHDNAI
_1~
_
-
-
l~F
PONDl
POK2
Ql: IRF782113OVl9mO
OUT
Rl: 182k
POKl
02: IRF7832J3OV/5mO
IUM
vrn
R4
200k
REF
YTT: a.loni.IA
FB
YTT
~
RUIN
VTTS
bl0pl'
-
O.tvMDmA
YTTR
Cl
~ OPEN
C.
llP'
00 9-37
Figure 9-37
......_-==""--0 AVOD
ISL88SS0A A~~Jfl 00
the typical application ofISL88SS0A
Jl: 1*I f"Flm.~:
The specific working process:
CD SV ¥r?i 22 W4J-mIt, 4.S--2SY tit 17 JJ1J~
5V supplies power to 22V,4.S--2SV' s~
® 3 Jl!IJf=j: 2V ~$ltffo
3 pin produces 2V reference voltage.
® j¥jfjj::&:±l ~ It 3f1W SLP_S5#1
The South bridge sends the higH ~
@ PWM 7fJi3, _1:1:1 VD~
PWM is opened,outputs VD~
@ VOOQ ~§I~ OUT
VOOQ is returned to 0
power to REFIN.
® ~4I:±l VlTR, Jt~
It fa, r~i:J:j1ij 1- 10kO
-146-
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1
is the half of REFIN h
.
lJ!.\~bij)~tbro
.t at IS 0.9V(as shown in figure 9-39.after
• ugh two of IOkQ resistance serie divides into the voltage to b
th O.9V through voltage follower).At the same time.lhe chip output
REFIN/2
REFIN
IOkO
1Oko
VITI
VIT
1-----1--0
PGND2
tofthe internal relationship ofREFIN and VTI,VTIR ofTSL88--0
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3
the ground connection
4
output discharging mode setting pin.Connect to VOOOQ trace discharge:connect to the
ground,the non trace discharge;connect to VOO,not discharge
5
VTIREF voltage output pin.is sent to the memory reference voltage
6
the diode emulation mode open pin.Connect to VOO to open the diode emulation
mode;connect to the ground,is always working in the forced CCM mode
7
the vacant pin
8
the reference input pin of VTI and VTIREF.The output voltage of VTT and VTTREF is the
half of VOOQ.If FB connects VDO or GND,VDDQ can be acted as the output voltage feedback
input pin
9
VDDQ(PWM) output voltage setting pin.Connects to GND,outputs I.5V;connects to
VOO,outputs 1.8V;it can set the adjustable output voltage between 0.75 ~3.3V through the
resistance partial pressure
)0
SLP_S3# sent by the South bridge,is used to control the output ofVTI
11
SLP_S5# sent by the South bridge,is used to control the output ofPWM and VTIREF
)2
connects to VIN through a resistance,sets the frequency
13
the open drain output pin ofthe power good,it means that PWM control output VDOQ voltage
has normal
14
the power supply
15
the power supply
16
17
the vacant pin
18
the ground connection(the ground co
19
the down tube drive
20
21
the top tube drive
22
the boot-strap pin
23
24
the output ofVTI
-]·18-
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=:ti.-f1i• •~7f.€l./l!ll. hitl VDD 7fJa=~hZ:g1jjJffjt:rt Jt~itl
:l1!!., tt&~ I f'Ff£~!ii*,J CCM ~A
VIT ~ VITREF rt:J~;1UifUA./l!II. VTT .fO VTTREF sf](fu"Ut!:J 1t!.J.I~
1m* FB 1i VDD EX GND, VDDQ iiJ!?J1'Fjg(fu"Ut!:JIt!.J.I
VDOO
tA-*".
.&tlIlABIlJ
VDOO (PWM) ~tl:lEt!.ffitt)i;./l!II. J!1iitl GND, (fu"Ut!:J 1.5V; 3i1i
!tJ VDD, .tl:l I.8V; ili1Jt1J.Il?tffiiJ!?Ji,iJE:~t!:JEgJ.I O.75-3.3V Z.
raj iiIiJf!l
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The typical application ofRT8207 is shown in figure 9-39.
V,N
2.5V II> 26V
R4
Il2Ot<
RT8207
12 TON
BOOT ~--./'./V--,
1
C8
'O~Fx2
VODPo--t_---..---..,p-----!.2l15 VDOP
5V
Rl
5.1
4
~---<.-.!:!.j' VDD
C2
:J;l~F
R2
lOOk
Vvooo
'.8V/l.5V
C6
1220~F
R3
5.6k
PGOODo---......- - - - . ! > ! . j
VTT Conlnll o-------Wl 53
1
'
55
VDDQNTTREF ConInlI
DIKh8Ige Mode
MODE
CCMlDEM
3
OEM
FB 9
VDOP fa< CORII
I!--------OGND fa< DDRIII
=
m9-39 RT8207 A~gffl 00
Figure 9-39 the typical application ofRT8207
RT8207 tr-J S3 1O S5 ~flitJ;r.~~~)t.J.l.J\!.~ 9-90
The original in English of the control logical relationship between S3 and S5 of RT8207 is
shown in table 9-9.
Table 9-9
the control logical Ie
53
as
SO
HI
HI
S3
Lo
HI
S41S5
Lo
Lo
STATE
•
(Ql
-150-
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'ng process ofRT8207 is shown in figure 9-40.
v..,
2.5V 10 26V
R4
620k
FB 1"-9
-oVOOP fo< OORU
GNO for DORIII
~~ I\!.lI'tPWM~l±l1.8V
~:Il!!il'tPWM~tfjl.5V
1119-40 RT8207 BgI11=mE~~
the working process of RT8207
Figure 9-40
~ It!.
-1
7f."ttl
the power supply
-1 open drain outputs PO
PO
Mm~* SLP_S3#
the South bridge sends SLP_S3#
Mm~* SLP_S5#
the South bridge sends SLP_S5#
_ttl
:ti~d
VOOQ
~Et!Bi~Rlt VTT
_ttl
detection
output VODQ
(VODQ ~-*") convert the voltage input by
VLOOIN to VTT output( half ofVODQ)
output VTTREF
halfofVODQ
PWM outputs 1.8V when it connects the
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Analysis of the bridge/bus power supply chip
m~~~A~~~Z~~~~., -.*ffl.PWM~#~PWM~~••
The bridge power supply and the bus power supply chip is relatively simple,is usually used a
single PWM or dual PWM controller.
I){)I> 9.4.1
Jtl PWM ~"JH RT82091Hfi
Analysis of the single PWM controller RT8209
'~ffl(f.J. PWM ~*Ijft RT8209 iJTfflTm~~,
,~,~~~, i*Jf¥.:t1;!t~~1&~~~~. IT
l~:: RT ~'UZJt*1*-.f6:~:::f~ff.~~%, .Rfff=£.f-t%· 19Hz!], RT8209BGQW, ~Jt
*1*P1f "AO=" ::j::~, 1m1ll 9-41 m~. J1t~ZJt(f.J~lltj~%iR§}'J~JfF~ RT ~Jt(f.J!-g-9&Jt
11f. g iiUlitJTmt{~I:tl(f.J.tfiAli*~ 09 1¥(f.J, Jt1tf~73 Richtek_Marking_Code_090424.PDF, I'iJ
~{fmmlAAJ (www.chinafix.com) '""F~¥U.
The common single PWM controller RT8209 can be used for the bridge power supply,bus power
supply,the memory main power supply and other circuits.Note:RT series chip body usually do not have
a real model only the product code.For example,RT8209BGQW,the chip body is only the word
"AO=",is shown in figure 9-4l.About the actual ~ recognition of this series chip,you need to
download the packaging file ofRT chip,at
version ofthe new efferent is 2009,the name
of
this
field
is
Richtek_MarkinLCode_
,PJl>F,you
can
download
in
the
website:www.chinafix.com.
-152-
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.h===::::;:;:{\--'BOOT
~
'--lC==~
RT8209B (WQFN-14L 3.5x3.5)
Figure 9-42
UGATE
PHASE
CS
VDDP
LGATE
PGND
RT8209C (TSSOP-14)
the pin definition of RT8209 series chip (the top view)
.~IJIJ: ~7 PWM :m~5IlJ14J7'~, ~EBJl!lJ VDD, VDDP -!J9:J1fHglj 5V, CS ~t)H~
~
TON :JgMJi*1i~, 7fJalJl4J EN/OEM B~JE:x.~;arn/=~1H211JAr~:rt~1IjIJ$r1trA
Q=t-mJlfl ENIDEM B"J~fliJNiit~OO 9-43). ~~flj VDD 7g-,I'lJZ~11JAf~:rt, jrf
-mg~.~~~OCM(•• EBfi)m:rt.-.I~~, .~~~~~, *ffi~
~.
;important pin:in addition to the PWM related pin,the power supply pin VDD. VDDP are
connected to SV,CS is the current limit set,TON is the frequency setting,the definition of the
ENlE>EM is the start using/the diode emulation mode control input(the threshold value or
RT8209 data manual described as shown in figure 9-43).Connected to VDD,is the
"on mode,connected to the GND tum off chip,is CMM(the continuous current) mode
~~:antGenerally,its the vacant state during working,and is the ground state when its turned
ENlDEM Low
IENlDEM High
ENlDEM ftoat
0.8
Z9
V
2
the screenshot ofthe description of the electrical features of EN/OEM pin threshold
value in RT8209 data manual
7,~rKJ.mzffl:tznIll9-44 ffi7J', If"Ffi~fijit:tzn"f.
of RT8209A1B/C is shown in figure 9-44,the description of the working
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Starts PWM outputs VOUT.
@ ]A VOUT )J!p~WlU r:fiffio
Detect the voltage from VOUT pin.
@ 7f~~1:tl PGOOD, IE VDDP LtL79~Jtl.fo
Open drain output PGOOD,is pulled up to be the high level by VDDP.
RTON
250k
R4
0
RT820BAIBIC
BOOT
TON
VOOP
VOOP
Rl
10
R2
1001<
C2
=
VOUT = 1.05V
': OpllonaJ
PHASE
VOO
R7'
LGATE
I1~F
PGOOD
RS
0
UGATE
PGNO
PGOOO
cs
GS' Gll"'
R8
12k
G1
1220~F
FB
R9
30k
ENIDEM
GGMIDEM
VOUTI-----------===----...J
GNO
":"
00 9-44
Figure 9-44
RT8209A/B/C B~mffl 00
the application ofRT8209A/B/C
:« PWM ~.1jJ1 TPS51124 ~trr
[)(){> 9.4,2
Analysis of the dual PWM controller TPS51124
m
1t ffl T tit JtI. ~ I~ ~ ~ It! l¥J)OC EWM ~Jt! ~ J:r
TPSS1124 1f 3-28V l¥J~Alt!ffi~lJJ, •
Jg O.76-S.5V
0
The input voltage range of th~ ffi:iil
supply chip TPS51124 which is c~
bridge power supply and the bus power
to 28V,and the output voltage range is fro
TPSSI124l¥JijIJJtll~f$:tmm 9-45
The pin name ofTPS51124 is sh
:m~ijIJJtllm~: 15, 16'-;>'g
$~, ~ 1, 2, 17-24 )Jip~~=
~LHi,
EN1/EN27tj}lJ7fJaPJlU
The explanation of the lID
frequency selection,from 5 pin
pin and from 17 pin to 24 pj
respectively the over-c
-154-
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• •.=f.MJ:j:IX'j VSIN, VSFILT (jry1~1:rE!.~U:I:liI:Ii~~~rJ[~1 9-46 fn7J\: V5JN,
WiIl4.s-s.SV.
51124 data manual,the power supply range ofV51N and V5FILT described as shown
:tile power supply range ofVSIN and VSFILT is from 4.5V to S.SY.
VSIN, VSFILT
MIN
MAX
4.5
5.5
the screenshot ofthe description of the power supply range ofV51N and V5FILT in
the TPSSl124 data manual
4fdl.=f.MJ:j:IX'j EN ~l!IJil#fl~~[)OO 9-47 JJJT7ft:, EN Enl*JiliUdl£:tJ IV, -119:7:1
1.5V.
51124 data manual,the threshold value of EN described as shown in figure 9-47,the
Id value ofEN is 1V,is usually I.3V,the maximum is 1.5V.
the screenshot ofthe description of the electrical feature of EN pin threshold value in
ClND
FLOAT (Open)
V5F1LT
IWlTCHING FREQUENCY
CH1
CH2
240 kHz
300 kHz
300 kHz
3110 kHz
3110 kHz
420 kHz
the screenshot ofthe description ofthe frequency setting ofTPS51124
.-JI
PWM I11=1£ 240kHz, ~=J& PWM I11=1£ 3OOkl-iz.
the ground connection the first path of PWM works in 240kHz,the second
kHz.
.=J&
PWM I11=1£ 300kHz,
PWM IfF1£ 360kHz.
die first path of PWM works in 300kHz,the second path of PWM
PWM I f1=.tE 360kHz ~~. PWM If'F1£ 420kHz.
e rSt ~th of PWM. works in 36O~the -second paUl of
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TPS51124 !I'df,t}-,¥-Jut1l1x-J FB IJillrfJr~/=VI~H1rroj£~IJOO 9-49 PJT7Fo FB ItlliifW!fJ"i!lEmHtl
SKIP f!;b:t~ 764mV, PWM ftht1'9 758mVQ 25°CA1, i~~*ffJJ[ +0.9%, 0~85°CII1i~&*I'iJ!J:
+ 1.3%. -40-85°ClI1wt~;fflJ3t± 1.6%.
In the TPS51124 data manual,the electrical features of FB pin described as shown in figure 9.
49.1n the SKIP mode,the reference value of FB voltage regulation is 764mV,in the PWM mode,the
reference value is 758mV.the error precision is about 0.9% in 25 °C ,the error precision is about 1.3%
in 0~85°C,and the error precision is about 1.6% in -40-85°C.
VF8 VOLTAGE and DISCHARGE RESISTANCE
FB voltage, skip mode (fPWMI10)
VFB regulation voltage
VVFB
TA ~ 2Soe. bandgap lnillal accuracy
VFB regulation voltage
TA = ooe to 8Soel')
VVFB
tolerance
TA • """coe to 8Soe ll )
0.75S-V target for resistor divider. see PWM Oparatlon of
VFB regulation Shill In
VVfOBSKIP
Detailed Descripllon (1 )
conlmuous conduction
Figure 9-49
mV
764
0.9%
-0.9%
-1.3%
1.3%
-1.6%
1.6%
758
mV
the screenshot of the description of the electrical features ofFB pin reference value
in the TPS51124 data manual
TPS51124 A~@FIUIJ 00 9-S0 Jijf7f.; a
The typical application ofTPSSl124 is shown in figure 9-50.
InlWl VoIlIIge
3VIo2SV
R4
C9
22uF
R5
73.2kO 75kQ
R1
28.7kO
SOND POND
10 uF
V02
V01
'.5 V/10A
1.05V110A
C4
2x330uF
V51N
4.5Vlo5.5V
Fi~9~S
fsj ~I f'FiALfj!~"F
0
The description of the wor •
CD ~E\:!~A 4.S--S.SV
-156-
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er supply outputs 4.5 --5.5V to 15'
.
pm an d 16 pill.
EN2 tlfrIA.
2 input
r--.,ij,\G~~=~ PWM.
path ofPWM or the second path of PWM.
@1 ~~ V02 tijl8!'f!lli.
voltage from VOl or V02.
lim PGOODI ~* PGOOD2.
output PGOODI or PGOOD2.
Analysis of CPU core power supply
.Jt:~~!'f!1f$1", :ro:J 478 at CPU li~ 3 #1~~, -1"\ 13/[5/17 ~~ 5 1'-1~~
CC ..::t~~'c.,~!'f!. *li':±~ijj:fA¥JL#'M'
CPU ~JL.'tit~~c;JtI 11=J~J~o
y requires a nwnber of power supply,for example,CPU of 478 needs three kinds of
first generation 13115117 needs five kinds of power supply,but only VCC pin is the core
this section,we mainly explains the working principle of several common CPU core
msj
of CPU VCORE power supply
~1"1t¥!jj~4iI±lii~tE-~,
~1!'J:J3 CPU ~~, ~.WijJE CPU A~¥j[1ffl
m~~:tm !I 9-51 JiJT7J'.
output is that the output of multiple current sources are connected
er to €PU,whieh meets the demands of CPU large current.The real object of
ypply is shown in figure 9-51.
~~J.~ts.I{,FIt.ffi~/f'jRJ(J(j, m~ilJt:-#~*IJ1fA*§Z9J~g~
IlP.I±lIt.ffi~ VID rl*~.
w.ol~ required by CPU at the different times is different,so it needs the
tieatly, tbe requirements of the different CPU on the voltage that is,the
G
~~m~)~-~~s~~tt*, ~k~jRJ~~U, ~~
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VlD
nr 7t7~ PVlD (JHf VID) ;fn SVID ($ ff VlD)
0
VlD can be divided into PVID(parallel VlD) and SVID(serial VID).
Figure 9-5]
the real object of two phase CPU power supply
AMD .!liM*" Intel 5 -*~tl~Jt~!l (HM55 ~) ziW,
m~~T PVIDo Jt~*JJjU~8Jt~tE
CPU J: i5Hi7 4-8 l' VlD i~UIIJJJI4J, *ii!lJiffiii:(£~®iJUIUJj!pJ:B~?iflj1~1:1~!;~fl, ~p)t-m VID
in}}U1§-5, ~ VlD iJU}tlJJtpJ:13~It!.-'FIJ't, 9!tl13=:itt$IJ8"J I *~, ~ VID iJUltlJj!pJ:~1~~~D'J,
JjltlJ~~*ltiIJ8"J 0 *~o Ui!® I ~ 0 8"J~.Il~, Wt~p)t7 -~!l:li~*B~m~rrf§1§-5' *83 CPU
fl;4JlIJf-U CPU f;tt:lt!.~rm9J8"JIt!.~'fJl~Jt, 1t!.~'fJl~JtfLHf.5JiJf~JIJB~ VID 1§%, iPiJ~!fu'tt±JJljjcf1=P
f§%AtJ d.:i£l:t. i§.~ CPU ~1t!.$J&.:±IIW.m:mtttBi~ffi1i8"J VID JiJf1-\:~8"Jfl-3&o
AMD early and before Intel 5 series chipset(HM55,etc),are all belong to PVID.The basic principle is
thatsets 4-8 VIO recognition pin on the CPU,and through the high and low level values preset in these
recognition pin.to fonn a group ofVID recognition signal,when its high level on V1D recognition pin,then
is the I state of the binary,and when its the low level on the V1D recognition pin,is the 0 state of the
binary.According to the combination of these 1 and O,forms the group ofthe most basic machine language
signaI.and is transmitted to the power
CPU,according to the VID signal,the power
signal,which forces the DC voltage output by CR
Chip in the CPU power supply circuit by
. adjusts the duty cycle of the output pulse
circuit to be consistent with the value
represented by pre-set VID.
Intel 0jjj~jt~liiJlJ'tfB]~;a:IW~. CPl!1
• ~.~ (Voltage Regulation
Model, VRM) iiit~!U[, JA Prescott ~I
~t&m VRD (Voltage
Regulation Down) *1ftr:t, :(£~ia*f,@;
(Intel Mobile
Voltage Positioning), ~~*~EI!lilt"
BiiJlill!mmliI
~ :iF ffIliiJ
0
Intel company developed the ~
each CPU produced at different
regulation specification used
Mobile Positioning,the VlD digits
the various version ofthe pow
i!#mJ:tIW VID,
IiIBt
-158-
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tp~-1-~~t- VID f~ :tl±b
.
~ rtj! IC~:fi! .:~ l!!, JJtotEfJ.1m. IC 8~ VIDO~VID7 i]IJJi;lJJ:8)t~!J~U
0
~!2J.~:J@:.CPU ~~~ I /F1aJ8j~.El.~, t£*~~tIHB~OjEgEL m8Jt~i£, it
'this mode can ' cheat' the CPU
Old,
to come out by loading the dummy 10ad.After loading
co~ects one or more VlD signal of VIDO ~ VlD7 to the ground,at this
7 pm of the power IC g 15 th
e
e new voltage combination according to this different
d h
.'
power IC will control to
" "
sen t e correspondmg voltage.That is to say let CPU
6hip IDlstakenly assume that the true CPU is loading.
AM2+ CPU 7f1lfj, CPU 1~;fg-~W3$7tEfJ.LI (AMD %":z.tJ Dual-Plane), -1'-~
lit -1-~ CPU P3~1iX:((.]~tm:8j EfJ.LIo -~J3.j-HT VID ~*IH~:ljc7C~1:EfiJ-a;j
lX1\§"l+rtBt, IS!~FNm~-m:JHT VID ~*IJ CPU ep8'~~tm:~LI, 19j!~~~
• rJ! AMD *$I6ml±lffi-f-tltlliifiiJT.it~:ljc~.mm,
fT VID (SVID) tffi;~*
*ffl *
• $tr YID ~-~·~~~m!((']#J·-j,)(o JAli9!ftj: J:*~, JiJTi¥r~Et-J)1H11mHJ El3 (;l.
5 jt 6 -t~Pl SVC (*qTa;J~), SVD (*qT~1J.O fm1-, r.iJ(;l.i.£~rn.!ftJ
H1r$tr VID :J!-~.~~Iffm~, JiJTlV-tffi~tj~1tj:8jwc.1r, 19fiJH;jm~U*~
f1:tt~J!5;o iWM*iW1t AMD '±:lJX:T:JJ*t~ AM2/AM2+/AM3, *ffl J
PWM~fMBo
m AM2+ CPU,CPU contains two parts of the voltage(AMD calls it to be Dualcore voltage of CPU,one is the voltage of the North bridge integrated in CPU.A
el VID control modules can not asynchronous control these two voltages at the same
"des a group of parallel VID again to control the voltage of the North bridge in
• be more complex.So AMD launched a new generation of voltage regulation
"on,using serial VID(SVID) mode to solve this problem.Serial VID is a type of bus
hardware point of view,the required external interface is from the previous
a total of 6 becoming into SVC(serial c1ock),SVD(serial data),it's very
use the serial VID is the bus working mode,so it needs the cooperation of the
means that the operability adjusted latter wi1l be stronger.Most of the previous
USed PVIlSVI compatible of PWM controller in order to to compatible with
ft.Ja(l(J Core i31iS/i7 CPU .fflt7 ~~~Ic.\, 197£M±l!!~*Uj!W3~J3.1t
WD _l::::J W.?HJIJ~$tJ CPU tr.J~lc.\~ffi*,~~~lc.\~ffi,
j!p:ij~J3.ItLI
N.. ita~J!~H.~7-@.
. lay core in Core i3/iS/i7 matched with 5 series platform in order to
er supply better,so provides two groups ofPVID interface to control
a cree and the display core voltage,these two groups of voltages are
tel Y.RDI J.t which is more complex.
2 ~~
-mitJ!l$qf VID .~. ~ AMD SVI.:tt
: SYD (lilHr V1D ~.)"\ (SV:C $iT VJD lI[~)
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Starting from 6 series platform,lntel imports VRD 12 specification.that is the serial VID
mode.its exactly the same with AMD SVI mode.There are three line
of SVID of Intel
platform:SYD(serial YID data).(SVC serial VID clock),ALERT#(waming signal).
[)(){> 9.5.2
MAX87701,Hfi
Analysis of MAX8770
MAX8770 ~ MAXfM 0'§]j::f"(j~RlT CPU ~lc,\1j±~~~*tl;L:;Jt,
rq:g- IMVP-6 ;ij!,m:,
.± ~~ };~t~ll"F •
MAX8770 is the control chip produced by MAXIM company,which is used for the CPU COre
power supply,in accordance with the IMVP-6 specification,the main features are as follow.
• xt.fjlij.ffi CPU ~~.
Support two phase CPU power supply.
• xt.¥ 7 UL VIO, ~~tl1~lli O-t.5000V iJJ~.
Support 7 bit VID,the output voltage is adjusted from OV to 1.5000Y.
• x t.fiifJ~.ffi ULW!.Mll1*D~.
Support for dynamic phase adjustment and sleep.
• ~Jj.l(;!3giifJ;L:; J:f •
Integrated driver IC.
• Jl,-i-~~mt~ (PWRGD) .tl1f=nIt-J"~~fl~ (CLKEN#) ~"i]tl1.
With power ready (PWRGD) output and clock enable(CLKEN#) output.
• *J ~~%i:~~i:1~00?
With the power monitoring and over-heat protection.
• xt.f 4-26V ffllA~.lli1l1I1o
Support 4-26V input voltage range.
• ~~ tl1 i:1Ek f*:tF •
Output over-voltage protection.
MAX8770 iJlJl!p!6~:tm1m 9-52 ffim,
The pin name of MAX8770 is shown •
3 JJTlJ'o
:of MAX8770 is shown in
figure 9-53.
-160-
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00 9-53 MAX8770 ~!/o/}OO
the pin name ofMAX8770(the top view)
the real object ofMAX8770
70 ~iJlJ)ip}E50~!.~ 9-11
0
m definition ofMAX8770 is shown in table 9-11 .
• 9-11
Table 9-11
MAX8770 iJIJP;E)(
the pin definition ofMAX8770
o the clock enable logic signaJ.When the output voltage detected from FB pin reaches
ue this pin outputs the effective logic low level.
00d signal of the open drain output.When the output voltage detected from FB pin
ified value,this pin open drain outputs the high level.
logic signal and DPRSLPVR commonly set the power mode.lf PSI# is low,then
Me ofN-l phase.When PSI# is high,then recovery the PWM mode ofN phase.
lUt pin of the internal comparator.When the voltage ofTHRM terminal is less
'WUiOT# is pulled low.Its the high resistance at shutdown
internal comparator.Connects one end of the thermistor(usually is NTC)
end to THRM,and through a resistance to vce at the same time.By
lhe required temperature,the voltage of THRM end is reduced to less
oltage swing)control pin.TIME connects a resistance to the
':Ihe application of the voltage slew rate contains:the chip
chip enter VID MODE from BOOTMODB.For toe soft start
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and shutdown process the chip reduced automatically the slew rate to 1/8.
8.the switching frequency setting pin.The switching frequency is set by a resistance connecting to
the power supply end and the TON end.
9.the capacitor connection of the voltage integrator.
1O.the current balance compensation
11.2.0V reference voltage output,through a maximum of 1 11 F capacitor bypass to the ground.REF
can provide SOO"A current to the external loads.
12.the feedback input.The external resistance capacitance element is used for detecting the output
voltage.
13.the negative of the inductance input end of the feedback bypass.Connects to GND of the load end
in general.
14.the positive input end of the second phase output current detection.This pin must be connected to
the positive end of the output current sense resistor.Connects the PIN pin to VCC.the second phase
is closed.
IS.the negative input end of the second phase output current detection.This pin must be connected to
the negative end of the output current sense resistor.Under the case of the DC inductance of the
output inductance being used as the output current detection resistance,this pin is connected to the
output filter capacitor
16.the negative input end of the first phase otitp
c
:t detection.This pin must be connected to
the negative end of the output current sense .resi
e case of the DC inductance of the
output inductance being used as the output cumm
,this pin is connected to the
output filter capacitor
must be connected to the
CC,the first phase is
18.simulated ground
19.the controller power supply pin.Co
11 F bypass capacitor to connect to the 8r.9
21.the output end of the top
between LX2 and BST2.ltS
-]62-
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• ill end ofthe output inductance of the second phase.It sets up the opening voltage on
top tube acts as the input end of the zero crossing comparator of the second phase at
hase power ground.Its the ground end of DL2.1t acts as the input end of the zero
or ofthe second phase at the same time.
end of the down tube drive signal of the second phase.The voltage values is changed
aDd GND.DL2 is high in the shutdown.When the output voltage is abnormal,it has
tie high.!t also is low in the small load mode,until detecting the inductance current
IZero crossing
ply pin of the down tube drive of each phase.!t acts as the charging source of the
ofeach phase at the same time.This pin connects to the voltage source of 4.5~5.5V
of the down tube drive signal of the first phase.The voltage values is changed
ifid GND.DLl is high in the shutdown. When the output voltage is abnormaI.it has
high.!t also is low in the small load mode,until detecting the inductance current
crossing
und of the first phase.Its the ground end ofDLI.It acts as the input end of the zero
[ ofthe first phase at the same time.
end of the output inductance of the first phase.It sets up the opening voltage on
,acts as the input end of the zero crossing comparator of the first phase at the
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39.the input end of the depth sleep control.This signal and PSl# signal set commonly the pOWer
mode
40.the deep sleep awaken signal When this signal is low it means that CPU is in a deep sleep state
JW
~
fir.
f*
1
Ci:KEN
2
PWRGD
3
PSI
4
POUT
5
VRHOT
6
THRM THRM, ~~iiit-1-Ef!Jm.~Jtl VCCo ~R§8g~1tf:. 1~.mtEfffl~B~
¥M!;AJ:, THRM _t¥JEf!EIi~~ 1.5V !;AT
Ef!ffiJI* (Ef!ffitl*~R: Ef!ffitlz;/J rJgj£$) ~li;;1 JW TIME M±{!!A~REf!Jm., fflT~.~~.$oEf!ff~*rJgEffl~: ~~~A~~tB~~
TIME
fBJ/fiI.A, ~JtJABOOTMODEi£A VIDMODE. X1T~jgz;b~:¥-:IjjTi1
X.
5:E
~~~R~.m~~.ilio§MffiJWM.~~.ili~ffi~~~~m
~, ~JJI4J4iJlI tlF(if ~iZ .1l;t Jt .>f
8tJHfi!4irllilil¥J~~~H§%o §JA FB JjI;fJ~~tl¥tl8g.ili ~ffi~¥tl~~;Em
~, ~JJlJ7fim.ili~~3f
~1l;t~ff~.m~.!§ DPRSLPVR ~~i9:ff~im!~Ao ;ff PSI#~1K.
9!~i£A N-I ~'fHir.EJ<J PWM mAo § PSI#~~~t~![ N .ffi1ft PWM t~A
Ef!~~P-t~tB
a
~ 1flI It ~
EJ<J iI ~ 7f lffl. $)11 tB Jj!p § THRM jffij ~ ffi 1a T 1.5V
(JO%VCC) ~, VRHOT#1fL1ao *m~79~~£I.
P31flIIt~_NW. ~-11Mi&Ef!~£I. (iM-m-~ NTC) ._jffij~:tt!!., ¥J-Jilrati
0
0
7
N, ~~E1z;/J~~$"M1/8
8
TON
7f~~$~I~om-~~m~.~.~~roN~*~.7f~~$
~~
JW
~
1ft
ffF
9
10
CCV
CCI
II
REF
12
13
FB
GNDS
14
CSP2
15
CSN2
16
CSNI
17
CSPI
-164-
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m•I .:. IIWM 1t!fl8:t1.iWl
hown
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QfBSLELB
~
MlIl1ll
l a V e r y low currenl (I-phase skip)
1
1
Low currenl (approximately 3A)(I-phase skJp)
a
a
Inlermed'a'e power polenlie' (1-phase PWM)
a
1
Max power palenlia' (2- or l-pha.e PWM as canligured al CSP2)
Figure 9-54
the screenshot of the original of the combination of DPRSLRVR and RSI# setting in
the information of MAX8770 chip
~ DPRSLPVR :J3liii, pSI#:J3f~B1, ;r;JtI ff~:rt:J3 ~¥!rE~P1t IJ', I ~B~~J]ik{rf
0
When DPRSLPVR is high.PSI# is low.the chip working mode is that the current is very
small,the 1 phase jump pulse.
~ DPRSLPVR :J37lIi, pSI#:J3liiiB1, ;r;Jt I ff1£ 3A IJ' ~¥!rEf~:rt, 1 ;f1]~~Jlik{rf
0
When DPRSLPVR is high,PSI# is high,the chip works in the 3A small current mode,the I
phase jump pulse.
~DPRSLPVR:J3f~, pSI#:J3f~B1, ;r;JtI1f1£ I ;f1]PWMm:rt. ~im:~,*o
When DPRSLPVR is low,PSI# is low,the chip works in the PWM mode of I phase,the current
is moderate.
~ DPRSLPVR :J31lk, PSI#13~II1, ;c';JtI1f1£r~UB PWM m:rt, ~:kEl!¥!rE~~tI:I
When DPRSLPVR is low,PSJ# is high,the chip works in the PWM mode of the full phase,the
0
maximum current output.
ctllif*3P: IC ~~lI1ti • • tI:i~Bi:1!:a12iJlJOVP fff,i1Eo ~~~tI:I~lli~T~Jru VID xtJ.iiZ
!fritrtl:l£t!.lli-aI 300mV 111 (~m, .%111 9-55), ~1£Jlijci1PriiJl!lm:rtr (DPRSLPVR :J3~) ~
T J.8V 81. IC J€3z;JJ OVP 1*!Po ~:tE~;f1]tbtr (DPRSLPVR :J31lk PSI#:J3~) f.&m~~U OVP
111. IC :fl:l'!p:m- DLl .. DL21iLjij", DBl .. DB2~fI£. ~~1!~r'lf~z;JJfi1i-'% r!i~bt:J3 100%,
r~ili~m~~tI:I~~,1!m.tI:i~m
The over-voltage protection:IC will
in real.When the output voltage is hi
ut voltage meets the OVP standard or not
of the output voltage current VID
corresponding 300mV(the typical vaJue;'
or is higher than 1.8V in the pulse
interval mode,IC starts OVP proteclion.
Ultiphase mode(DPRSLPVR is
low and PSI# is high) IC pulls DLl
uDs DH I and DH2 low.lt
makes the down tube driving sigijlil
's emptying the output
capacitor rapidly,the using output vol
Figure 9-55
-166-
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threshold value in MAX8770 data manual
. ~.I±lJt~f~T VID M@~~:±lEt:!.J.Im 400mV n1 C:9tr-lli!ffi, ~OO 9-56), IC
I\t.N 1J't~#-li"'Mc~'t1li~, lL~~~:±l Et:!.J.Ifl1~ OV IC lItD14H~HllutL~ DLI ,
1 DH2o:l4f SHDN#Jtffit1:ttLE,lt~~ VCC Et:!.&tLfl1~ O.5V ~ r ~1f=j~it~J~~.!Ji
0
Co
er- oltage protection:when the output voltage is less than the output voltage value
Cal value,is shown in figure 9-56) that VlD corresponding to,IC starts SHUTDOWN
and sets the fault latch until the output voltage as low as OV.At this time,IC will be
. mDLI and DL2,and pull DHI and DH2 low.Pull the SHDN# voltage clamp or
down to less than 0.5V to clear the fault latch,and re-activate Ie.
Vwp
Measured at FB with respect to unloaded
output voltage
tuvP
-450
FB farcad 25mV balow trip threshold
·400
-350
mV
10
the screenshot ofthe description ofthe electrical features of the over-voltage
MIN
CONDlTION8
TYP
4.5
MAX
UNITS
5.5
V
nshot ofthe description ofthe electrical features of vee pin and VOD pin
threshold value in the MAX8770 data manual
'" ffiJ MAX8770 1¥J ~. ffi % IiJJ {l1¥J El! '=i: ~ tt 11 ~ .l~J, SOON,
~itiJt.lf <JI:*m:), VIDO~VID6, PSI, DPRSTP i1iii O.67V 75JiWi
0;) V ;1gfl£~SP: <lI*m:).
-'58 is the screenshot ofthe description ofthe electrical features ofthe key
8770,SOON and DPRSLPVR are the high level(the maximum
2.3V:VIDO'-'- VID6, PSI and DPRSTP are the high level(the
~er ~ 0.67Y.are the low level (the maximum value) when its less
1.2
17
2.3
V
13
V
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Figure 9-58
the screenshot of the description of the electrical features of the key signal threshold
value in the MAX8770 data manual
IMVP-6 ~W:I¥J VID ~ffiM~~~ 9-120
VID voltage corresponding of IMVP-6 specification is shown in table 9-12.
~f1lJ: ~ D6-DO m19f~~-;:P:Dt, ~te~ffi19 I.5000V; ~ D619f~~-;:P:, D5-DO ~~
~-;:P:Il-L ~"tr:±llt!ffi19 0.7125V; ~ D6-DO ~19~~-;:P:Dt, ~"trte ~ffi~ OVo
For example:when D6-DO are the low level,the output voltage is 1.5000V;when D6 is the low
level,D5-DO are the high level,the output voltage is 0.7125V;when D6-DO are the high level.the
output voltage is OV.
Table 9-12
06
D5
D4
D3
02
the table 1 ofVID corresponding of IMVP-6
Dl
DO
~te
It!ffi
D6
D5
D4
03
D2
DI
DO
o
o
o
o
o
o
(V)
o
0
0
0
0
0
0
1.500
o
o
0
0
0
0
0
1
1.~87
1
0
0
0
0
o
0
0
0
0
1
0
1.~75
1
0
0
0
0
0
1
o
0.700
o
0.687
5
0.675
o
0.662
5
0.650
o
0
0
0
0
1
1
1.46
o
0
0
0
1
0
0
1.450
1
o
o
0
0
0
1
0
1
1.43~
1
o
o
0
001
1
0
o
0
0
1
1
1
o
0
0
o
C1
0.600
o
0
0
o
0
0.587
0
00010
5
o
o
o
o
1
o
o
0.637
5
o
0.625
o
0.612
5
o
5
75
00010
o
o
0
0
1
0
0
1
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M9!."1
1
1
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
1
0
1
1
0
PWM Ef!fmll'lifiW
5
1.325
0
1.312
5
1.300
0
1.287
5
1.275
0
1.262
5
1.250
0
1.237
5
1.225
0
1.212
5
1.200
0
1.187
5
1.175
0
1.162
5
1.150
0
1.137
5
1.125
0
1.112
5
1.100
0
1.087
5
1.075
0
.062
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
5
0.525
0
0.512
5
0.500
0
0.487
5
0.475
0
0.462
5
0.450
0
0.437
5
0.425
0
0.412
5
0.400
0
0.387
5
0.375
0
0.362
5
0.350
0
0.337
5
0.325
0
0.312
5
0.300
0
0.287
5
0.275
0
0.262
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~ ~iCjM!Ifj!l.'1\l'i!$Jl
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1.025
0
1.012
5
1.000
0
0.987
5
0.975
0
0.962
5
0.950
0
0.937
5
0.925
0
0.912
5
0.900
0
0.887
S
O.8i1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
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1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0.225
0
0.212
5
0.200
0
0.187
5
0.175
0
0.162
5
0.150
0
0.137
5
0.125
0
0.112
5
0.100
0
0.087
5
0.075
0
0.062
5
0.050
0
0.037
5
~~
~tI:l
06
05
04
03
02
01
DO
et!JI
( V)
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0.025
0
0.012
5
:0
1
1
1
-170-
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Mg~
1
0
1
0
1
1
1
1
0.750
0
0.737
5
0.725
0
0.712
5
0
0
1
1
pWMll!fmMM
0
0
0
0
0
0
1
0
0
sm Et!M&:fm1ll9-59 m~, lIlJ:j:Jtff-:±lJ JL1-~~I 1"F~1tj::
on circuit of MAX8770 is shown in figure 9-59,several key working conditions
figure:
5V~) fAL/!.ffiA ]
. . . . . . - - - - - - - . -.........- - _ _ o l SUPPlY
~~
II
1GIl
112
lJIQ
C2
Vee
VII)
I'IWIISO
RION
22jIF~
AlB
2IIIIln
m
--{
(!VI.-:)
INPUT V,.
BV 10 2'"
Ill2
III
8ST1
III
IJII1
D1
RCS1
lm1l
U
112
lIS
04
IX1
11.1
IIli
III
Al2
1Il1O
PlIIII1
e11
lIID
2.2Jf
II!lI
CSP1
'C&II1
iiii!ft;
IJI'IISIJ'\IR
iii
II
~.p
r:tN
a:~
WJIIlTI
IIf IlAll8m CCI
AUXlAII
1lAll87lD
_C7
III
All
lIl3
III
1IIIE
1512
..-_.~GIIl
IJll2
u
Ill2
...
112
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Figure 9-59
the typical application figure of MAX8770
CLKEN#~ PWRGD ~)~I±l
CLKEN# and PWRGD output
VID ~A
VID input
7f fa (§" -% the opening signal
{,It Eg~A
the power supply input
CPU 1~ Eg~"tr I±l
CPU power supply output
MAX8770 fa Z;I] ~O ~ l:fl llt ff ~O 00 9-60 JiJf7j: •
The timing sequence of MAX8770 starting and closing is shown in figure 9-60.
Vcc~
VIO (OD
06)
.
'--=~.=
1/8lliS~~~t~ ~;-i-~<,:-i~------;'----i-j~ :
Vco~
PlVM ~~R~~
J.&-f,PWIlI1lM>
~~ i
:'-./~: :
'FORCED PWM:!:: (§ltPli.o:!:: tXX><XixxXXxj FORCED PWM (j;!1b1l~ j
• • • •
(r
PHASEGO
j
1
------;----:--...:....:.~:f---__!.
•
CLKcN
ii::1El'1l$1Y-J1/8)
.- - - - - : - - + - - - + - - -
•
. '
PWRGO _ _---:.._ _
118111 SLEW RATE SET )l]T IIEI!IJtl!.ffilll:
BYRn!"E
0
o
~
SOFT-SHUTDOWN = (fl:1<fiJ, '1<fiJiU:
~--i-i__..:..o
__
:"'---
~i----;L-.----~....:....-~-­
'&.- :...I--..;...:--:-_~~..,:,.
t...
OOpsTYP: .. :- : :
: 5nTYP
::
: tlllNl(
: ~ 2lJpsTYP
Ia.wc
2lJps1YP~
Figure 9-60
CD 1tf:Jt;C;Jt~¥U~It!.,
pg$~J:tJt OL
Firstthe chip gets the power supply,the •
® ~J§5'r$~*~It!..sy:~7fJilm~
Then.the external sends the high level 0
® VCORE :Jt~i1i9J~-~EI!.BiJlrl
- ), ~!iHM PWM m~.
VCORE soft starts to a certain v.o
resistance setting the slew rate),forcecl
@ ;C;Jt7f~M~ CPU i!*tB
The chip starts to decode VID $i
@ VCORE i1i9J¥tl VID li
-172-
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corresponding voltage set by VlD.
~.s, ~1l1601JS .l.f~ CLKEN#o
being nonnal,delays 60lls to set CLKEN# low.
~ VID \i~ft-.JE@.lliJB, ~R1 5ms B~ PWRGD (MAX8770 &~
~ply achieving the voltage set by VlD,delays 5ms to set PWRGD
PHASEGD signal).
~~.
be low level.
#, PWRGD i:$~737C~:I7C~, PWM t!l(j:s!iHM PWM ~~~, VID
aIid PWRGD are turned into the invalid state,PWM restores the forced
aecoding.
CLKEN#-&~:l9f~ 1t.>jZ 7, ;tJt ItFf It 7
CLKEN# also changes to be low level,the chip is outage.
0
IMVP-6 ;l;im;1¥J CPU -mJt;tJtt ;It.±:~% R~O-"f
'Vier supply chip confonned the IMVP-6 specification.its main features
0
, ~~=~-mJtt liJtIU~;
.
el voltage regulator,supports for three-phase power supplY,ls
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o 140113111)1113711311135.
_ _ _ ,,_ ':WI
_.. "1)3_ ".32. '31'. .
~~ VIDZ
PGD_IN
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~~ \#lin
R8tAS
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[€. VIDO
VR...nl
~]
NTC
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SOFT
[~ PWM1
r~ PWMZ
GNDPAD
€:
[~ PWM3
(BOTTOM)
ocsn €]
VW
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COMP
!;
FB
[2! FCCM
[~ tsEN1
'!:
-- - - _...
_"
I
r~ lIEH2
.. _
~~
I8£N3
.. _ .... _, .. _ .... _ .... _ .... - .. rOo'" .. _ .......... r ....
'111112' '13- ".1 1151 '11' '17' '1111'" 120 1
ISL6260 51}J1;JJ~~ (]9Hml~j)
009-61
Figure 9-61
the pin name ofISL6260(the top view)
ISL6260 51}J1;JJJ:E50\!.~ 9-13.
The pin definition ofISL6260 is shown in table 9-13 .
• 9-13
Table 9-13
ISL6260 ~IJP;E:)(
the pin definition of ISL6260
] .low load current input indication,is effective in the low leveI.ISL6260 can be used to close the
PWM2
2.the high level input means that VCCP ana vce,precondition ofCLK_EN# and PGOOD sent by IS
3.through 147k....
!
bias resistance connect the grQ
4.over-heat indication output,is effective in the 10
I o. the feedback pin,which is
-174-
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differential amplifier
iitQliIR~aid 0 the internal attenuation ampIifier
~y~qmput end of the internal attenuation amplifier
li'.iJliP\lUJ:1CI ofthe output voltage detection
Dooduction mode enable pin(forced PWM mode) of the driver chip
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..,
ISL6260 tstili CLK EN#.fQ PGOOD (fliWfJHjH~
..>
RalAS
imii 147k•..{;11 E\! ~lHt±l!!. . ii:Q:: ~ $~ i1t E\! mt
4
VR IT#
ii1t.':m 7J'~~ ill, 1~ E\! 3fff %c
5
NTC
~~:6U1ftUt~~~~ffAE\!~.I3.,
1"1"79 VR IT#E\!w.!-tW:$t
)lii-*9!E\!~ii:Q::.*B~ E\!lli~:f*i!$ (lli~$, 1~s B1fB]lI!
6
SOFT
E\!lli*.(fl~&, • • ~.E\!lli~.~*~• • m.B1~, .~
im7ltff VIs. V/ms.fQ V/~ =#)
7
OCSET
8
VW
9
COMP
~~*H~, j!~I*J$~~$:*~B~tu~illjlfij
10
FB
.l~:i1tJJt4J, j!~I*J$~~$:*~B~&ffitu"trAylfij
11
VDIFF
~:$t$:*~~!ilitrillYlfij
12
VSEN
E\!lli~j!d,
jEjifij
13
RTN
E\!lli~~d,
~9jtij
14
DROOP
~$.~jj$(*."tI:l~
15
16
17
DFB
VO
VSUM
~
IJ!Il
1ft
~
18
19
20
21
22
23
24
25
26
27
VIN
VSS
VDD
(SEN3
ISEN2
(SEN(
FCCM
PWM3
PWM2
PWMI
28~
VlDO~
34
35
37
VID6
VR ON
DPRSLPV
R
DPRSTP#
38
CLK_EN#
39
40
3V3
PGOOD
36
ii¥RE1i~~AJjt;p
iiiiE\!~.l3.j!~COMP ~:Q::7f~~$
••~jj$(*• .&ffi~A~
• ili E\!lli~JU*A~
.~E\!.~.
~
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frr
I L6260 (J(J Jl.1' til ffi ;7 IlIJ 11:1 (I~ Il!/ {~,'f't1JNi i£: 1;;1 )( OX I~I ~III~I 9-62
7ft VR_ON,
epRSLPVR, PGDJN J:3HIH:iJilili~uJ\J~ 2.3V, n~7:i1!'~lflM)'J~ IV; VfDO-VJD6,
psJ#, DPRSTP#-.C3HfHiJ-{ti IJ t-J 0.7V, F~~~1AI~liJlfUIl[j-J~ O.JV
I
0
'The original screenshot of the description of the electrical features of several key signals
threShold value ofISL6260 is shown in figure 9-62.the minimum of the rising edge threshold value
ofVR_ON DPRSLPVR and PGD_lN is 2.3V,the maximum of the falling edge threshold value is
lv·the minimum of the rising edge threshold value of VIDO-VJD6,PSJ# and DPRSTP# is O.7V,the
maximum ofthe falling edge threshold value is O.3V.
UIIIIC_
_La
\/R.CH _ _ "'PGO ..
=-.. .
!
Yll,.ON .............. PGO ..
-....
Vl.U3Vl
v~SVI
10
>,
V
v
I
I YlU1
=-.. . --1
IlI'RITPI_
0\I1
V.... I 1M
0]
v
V
0'
the original screenshot ofthe description of the electrical features of VR_ON and
other key signals threshold value of ISL6260
III~3 }1f7J', ISL6260 ~ VID i:~ 0 JJ;f, VCC_CORE ~*%ljtJjEE!.).I 1.5V; VlD 7'.1
"'Eli
~(iLC0RE.-f:I:l
O.3V, ~ VID i:~ 1 l!'t, VCC_CORE 1ij1j tJj OV
~Mb'tiJ·p·:figure 9-63,when all VID of ISL6260 are OV,the maximum of the output voltage
is l.SB;Wb.en MD is llOOOOO,the output voltage of VCC_CORE is 0.3 V,when all
£0
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0
O~
1.soo
v
0.300
v
0.0
v
SCreenshot ofthe decoding range of ISL6260VID
II 9-064 I$L6260 ~ PGOOD ~
_
*~.blll
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power supply of 3V3,then it will send CLK_EN#.So,no PGD_IN will not cause no CPU POWer
supply it will only cause no output ofPGOOD,no 3V3 will not cause PGOOD does not output,it will
only cause CLK_EN# does not output low level.
The simplified application diagram and the key pin of ISL6260 are shown in figure 9-65.
Figure 9-64
the intemallogic figure ofPGOOD and CLK_EN# ofISL6260
m
VDO
YIN
3V3
RBIAS
m-~ll1:fi~
~:±l
VIN
Lo
ISL6208
PHASE
[
VIDs J>VIO<O:6>
R
C
fi\ 1111: 1"11 'Ii"
fJH\J;~~
(
?J
lli4i1lJ:f1
OPRSTP#
OPRSLPVR
MCHOK
C:LK_ _
CLK_ENABLE#
-
0
Lo
ISEN2
ON
JfJr~ J==:VR
'MVP~PWRGO
VR..OH
-
PGOOO
Remote
Sense .J
alCPU
CORE
ISL6208
PHASE
TCo
=
RlN
VDIFF
Fa
C,
COIIP
C,
YW
GHD
Figure 9-65
DFB _
-
Clc:I!T
\10
the simplified 8I?pli
11frUt ~W!tl ~i1t1ilm~
-178-
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Egff f'J:W!IJ
the voltage detection
.~ Jt:± fJt rl!.
the chip main power supply
eLK EN#.~fJtEg
CLK_EN# module power supply
.-*tI1i~mtl:l
the first phase of square wave output
OO:i;b~JtfJt~
driver chip power supply
Egim¥,q:~~tl
PGOOD (J{J~f!f
the current detection
the condition of PGOOD
the second phase of square wave output
the current detection
the third phase of square wave output
the current detection
the total current detection
soft start
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The chip decodes VID,drives VCORE to the voltage set by VID according to 1MVP-6
standard,the starting speed is lOmV/I!S.
® 7ms J§, ~Jt~tI:l PGOOD.
7ms later,the chip outputs PGOOD.
Figure 9-66 the starting timing sequence figure ofISL6260
The set voltage
Analysis of commonly used chip ISL9583I by HM65 motherboard
ISL95831 ~-1'x~ 3;ffi CPU ~,c.,.gtlt~ I ;ffi.JiX;~-F.gtItB9rt*tlB, :±~mT
Intel 8~ HM6x LHLt-f-Ei, ~.g. IMVP-7/VRI2 ~m:, TQFN ~~, 48 JJ!IJ. 1t:±J!%'
}~ ~D
-r- •
ISL95831 is the controller supported three phase CPU core power supply and 1 phase
integrated graphics power supply,is mainly used for HM6x and above platform of Intel,in
compliance with the IMVP-7/VRI2 specification,is TQFN packaged,48 pin.The main
features are as follow.
• x~~~ill: ~-~ltlli~~~~reI~3;ffi,2ffi,.;ffi;~=~~lli~~Bx~
~;ffi!ill" ill •
Support dual outputthe first path of the voltage regulator can be configured as 3 phase,2 phase
and single phase;the second path of the voltage regulator supports a single phase output.
• W3l~MtIliill;Jt$ SVID ~*tl.
Two path of output shared SVID control.
• ~~'=:1'~Z;JJ~Jt (~-~W31', ~=~-1').
Integrated three driver chips(the first path has two,the second path has one).
• x~ ~1'P~~:I: 1t7jfUI~1i7*.
Support a kinds of methods of current measurement.
• xM'i:1:~, Mmtf*1r'.
-180-
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1119-67 ISL95831 iJl )J!lJ~f* (JYlt~l¥J)
tgure 9'-67 the pin name of ISL95831 (the top vie\\)
9-14.
~~tC!lh9.S831 is shown in table 9-14.
~!SbiIDCeto set the switching frequenc) of thl: \ ollage
!J!cC~ent of the voltage regulator::! form· a certain
that the oltag regulator 2 has nomlal.The
~Ansgetnont cbjp
.aI VlD bu
has nonnal. The
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temperature of the voltage regulator I
12.connects this pin to COMP through a resistance to set the switching frequency of the voltage
regulator I(8k 0 resistance is about 300kHz)
13.the output end of the error amplifier of the first path of the voltage regulation
14.the inverting input end of the error amplifier ofthe voltage regulator 1
IS.when the voltage regulator 1 is configured as a 3 phase,is used to detect the current of the third
phase. When its configured as 2 phase,the internal connects the switch of FB2 and FB,is used to
adjust the precision of the compensation voltage regulator I.When its configured as 1 phase.the
switch is invalid
16.the second phase current detection of the voltage regulator 1
17.the first phase current detection of the voltage regulator 1
18.the input end of the voltage detection of the voltage regulator 1
19.the loop end of the voltage detection of the voltage regulator 1
20.21.the input pin of the droop current detection of the first path of regulator
22.SV power supply
23.the power supply
2S.the first phase boot-strap pin of the voltage regqt
pin oftbe first phase
26.the first phase of the top tube drive signal ofth
27.the first phase of the top tube driver loop oftb
tube,the D pole of the down tube and the outputind
28.the first phase of the down tube driver loop 0
the down tube
29.the first phase of the down tube drive signal
30.the third phase of the square wave 0
5V,disable the third phase
31.the power supply of the
capacitors
32.the second phase of the down tube
•
-182-
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11hi~ond phase of the down tube driver loop of the voltage regulator I,connects to the
tube
pole of
Bttlie second phase of the top tube driver loop of the voltage regulator J.connects the S pole of the
toP 1Ube,the D pole ofthe down tube and the output inductance
35.tlte second phase of the top tube drive signal of the voltage regulator 1
36.tbe second phase of the boot-strap pin of the voltage regulator 1.Connects the PAHSE pin of the
Second phase through a capacitor
31:tbe down tube drive signal of the voltage regulator 2
~ tube driver loop of the voltage regulator 2,connects the S pole of the top tube.the D pole
~and the output inductance
. e signal ofthe voltage regulator 2
pin of the voltage regulator 2.Connects the PHASEG pin through a capacitor
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~~J
_ _ _D
!l~
9
10
11
12
IMON
VR HO
T#
NTC
vw
iIlu-_t_E~J.ll1E~_t_/]t4Iii~f~COMP fflT~~~lli~T.i~ 1 8~Jf~
~$ (8k.Q ~~.ll:k~ 300kHz)
13
14
lSEN3/F
15
B2
16
ISEN2
17
18
19
ISENI
VSEN
20
ISUMN
lSUMP
21
22
3 ~lliifnjT.i~ 1 nGW.19 3 ;f§BtfflT~m~jfE::;f§~~mt. 3l!Cw..19 2 tI
D1, pgfff\ii~ FB2 ~ FB JJt4J8~Jf:*fflTifnjT.i~H~~ffi~1J~I ~:MJ.l.
3nGJ!..19 1 t~Bt, *:*x3'&
RTN
VDD
5V~~
VIN
24
PROG I
25
BOOTI
iIl)i-_t_~~.lliif.lJlJ:I:&I3I~EEil15:.
OOT ~Bi
ifnjT.i~~
~lliirnJT.i~ 1 I¥Jjg-*o §~
PHASE /]t4I
26
27
28
29
6!J
LGATEI
Fl!J.liiPnJT.i~ 1 1¥J~-*O~1i
31
PWM3
VCCP
Fl!J.li ~1J ~ 1 I¥J~=~
pg fff\Jmz;/J~ Jt 1¥J-mJt!, i!H
32
LGATE2
~J.li~"iJ~ 1 I¥Jjg=*OJE
30
33
34
35
36
BOOT2
37
LGATE
Et! J.li iIlI"iJ B 1 I¥J_PHASE IJ!1J
G
Et!ffi~lHt 21¥J""F
-]8'1-
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PHASE
38
G
UGATE
G
BOOTG
39
40
41
3~ ISUMNG ~~IJ 5V, ~$j-~ffl
9583J U-¥JJltIf!~ VR_ON ~AJtf~ffiJHji£;jlil~~DOO 9-68 p}TiF, VR_ON ;01~E/3
;JC-o O.3V, ISL95831HRTZ If! VR_ON ;0~Jtffl~j~(lJ {ijg O.7V, ISL958311RTZ
-o
~~Jt~I'fCJ./NI~ 0.75V.
~sa1 data manual the screenshot of the description of the input level threshold value
~~~in fi~!h-68tbe maximum value of VR_ON in the low level is O.3V.in the
minimum aloe of VR_ON in the high level is O.7V,in the ISL95831IRTZ.the
inrtbe liigh.level is O.7SV.
D.3
•• _ ~
...
~o.7;-
G.7.
~ Vv
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>-----1 RTN
Figure 9-69
Three power supplies
SVID wavefonn
starting
-186-
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11¥J PROGl "ftG.l.m~ 9-15.
·,{,:;'::Io.!~.~'figurationofPROG] pin of ISL9583I is shown in table 9-15.
the configuration of PROG 1 in the ISL95831 data manual(the original in English)
..
(a)
VR11CCMAX (A)
With POWER·UP
CONFIGURATION
RPROG1
(IIIIun)
Typ.
Max.
t+3%)
VsoOT
IV)
3-PH
2-PH
1-PH
0
99
66
33
0.61
0
93
62
31
1.13
0
87
58
29
1.74
0
81
54
0
75
50
25
0
69
46
23
0
63
42
21
0
67
38
19
111
67
38
19
63
42
21
I
27
46
23
50
25
54
27
III
29
82
31
88
33
are
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lSL9S831 B~ PROG2 ~f£.mm~ 9-16.
The configuration of PROG2 of ISL9S83I is shown in table 9-16.
¥191JM~:
Give some examples to explain:
~~ PROG2 ~imii O~~Jil.tl±t!!Jlt, ~J:f~ii7mr.f~H?f1i751120·C, .m=~E@.BiWll.ftffg
tJ:l Eg~m.Ntk 33A.
When PROG2 connects the ground through O~ resistance,the value of the over-temperature
protection of the chip is 120·C,the maximum of the output current of the second path of the voltage
regulator is 33A.
~~ PROG2 ~imi1 24.15~-X75*~et!~il.~tI!!.Bt, ~J:f~ii1liif*1?f1i:751 9S·C, ~
=~Ff!.lliWJlJ~~i)'trt\:j E@.1m.m:* 33A.
When PROG2 pin connects the ground through 24.15k.... or infinitely-great resistance,the
value of the over-temperature protection of the chip is 9S·C,the maximum value of the output
current of the second path of the voltage regulator is 33A.
SVID ~%~QOO 9-70 JiJT7J', j!)ll 751 SCK, j8i)l2 751 SVD.
The waveform of SVID is shown in figure 9-70,the channell is SCK,the channel 2 is SVD.
~ 9-16
ISL9S831 • •-¥fl&~ PROG2 JJlPIC.
Table 9-16
M1n.(4'6)
0.57
1.07
:2.19
3.07
5.33
6M
7.63
9.03
13.29
16.71
ISL95831 16 i;tJBt r=ftm 1119-71
The starting timing sequence o~
-188-
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VDD--.J
VR_ON - - . J r - - - S - l E - W - R A - T E - - - 2.SmV/~s
~V;;;;:ID-COMMAND
VOLTAGE
800~1
DAC _ ____'"
PGOOD
m9-70 SVID ~*
ALERTo
I
========~Lf . ·.. lJr--
00 9-71
ISL95831 JS~01J¥
the waveform of SVlD
...P;N', ~JItjpJtBim~¥U O.7V (ISL95831 HRTZ B~~+
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When the chip again received the corresponding SVID signal of control second of power supply
outputthe chip outputs a integrated graphics power supply.
Table 9-17
~ 9-17 ISL958311¥iJ$~TVID .~*i-/l~ (~)c~~)
the standard table of serial VIN decoding of ISL95831 (the original in English)
-190-
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~g~
....
Yin
"'o('f'J
....
hu
··00000
.~
0..255OU
0 .....
0~6000
0.58500
,
Oj65OO
.......
0.60500
o.GJ.OOO
o~ll5Oo
0.61500
0.....,.
0
• • .""!OO
.62000
•.6Z500
0.>0000
•.GJOOO
ll..JOSOO
•
0
0
•
• •
0
• •
• •
• •
• •
•
• •
•
•
I
I
0
:I.
:I.
:I.
:I.
:I.
:I.
:I.
:I.
:I.
0
• •
• •
•
=...
--,
0
0.>1000
:I.
.......
.......
.......
•
•
:I.
•
:I.
:I.
0
•
•
:I.
:I.
0
0
:I.
0.64500
0
•
1
r--.0
5
1
•
:I.
•
•
:I.
:I.
:I.
:I.
:I.
:I.
A
•
-.......
D.J'IODO
....,• . C
0
I
:I.
---
•
5
0.65500
1
0.66000
.67000
0
0.87500
0
0."000
0
•
•
•
•
I·
066500
A
069500
0
0.10000
0
o 70~OO
0
0
O.1J.OOO
0
0.71500
0
0
0,72000
:I.
0.12500
0
..-
I
:I.
0
:I.
.-
•
0.69000
"-
..-
0.65000
~
1
0.66500
• .......
"'..-
:I.
:I.
r
D.3JSDo
:I.
I
0.64000
•
'-JUDO
:I.
:I.
0.63500
•.UO.O
0.>2000
......
......
O.S9000
•
O.21SOO
0
YoM
""'000
0.27000
•
PWM EI!:Jga~M~
0
:I.
0
0
:I.
0
•
•
0
:I.
0
0
:I.
:I.
I
:I.
:I.
I
:I.
I
:I.
•
•
•
:I.
:I.
0
0
0
:I.
•
•
•
•
•
I
:I.
0
~
:I.
:I.
:I.
:I.
:I.
•
•
0
:I.
0
:I.
:I.
:I.
0
I
:I.
.73000
0
0.74000
0.14500
••
••
• •
••
• •
:I.
:I.
0
:I.
A
:I.
:I.
:I.
:I.
:I.
:I.
:I.
:I.
:I.
:I.
•
•
1:I.
:I.
I
:I.
• • • •
• • •
• • :I. •
:I.
I
C
:I.
E
-'-
•.78000
0.10000
0.10000
0.70500
0.7TODO
---
..77...
• ..
• • • ..
•
• ..
• ..
• , .-
:I.
•
O.13!iOO
1
0
:I.
a
----
...-
I-
.-
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JtR
6mmX6mm, QFN48 Ji~o
626S is commonly used in the motherboard of AMD CPU.as the output control of the CP
",1JQ'WQ supply and VDONB power supply.The ize of chip is 6mm*6mm.QF 48 packaged.
6265 ~IJJjfJ:tf*:(m1ll9-72 JiJTjf0
in Dame ofISL6265 is shown in figure 9-72.
--':
.... 1:
.....
:
----.'.'.:
•
•
--.... "·
-.'
"•
f'IU ~~
r-
,
I
I
:31 BOOT_NIl
I
I
I
I
I
I
I
:35 SOCJT_O
:34 UGA~'
:33 PKA5E_O
•
GOlD
:3:2 PGND_O
: J1
:»
:2] PHASE_'
I
:_ UGATE-1
MX:
:3 1..GATl:_,
:21 POtCU
--",--:": ._-------------- :a
•
LGo\TE_0
I
I
I
I
I
I
BOOT_'
1IIIIIi~ili.,i
119-72 ISL6265 i3IJjip~~ <JY!f!tOO)
the pin name ofISL6265 (the top view)
~in,~m·tion ofISL6265
tbe~~u,'then it
ill be
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5.serial VIO identification pin clock pin,connects with AMO processor
6.the enable signal input,when its high level,ISL6265 is opened
7.connects the 117k Q resistance to the ground,sets the internal reference current
8.the over-current ofCORE_O and CORE_l setting signal input
9.CORE_O differential amplification output
1O.CORE_O feedback input,to the input end of the internal CORE_O error amplifier
°
II.CORE_ controller error amplifier output
12.from this pin connecting the resistance to COMPO to set the switch frequency,for
example.6.81 ~ is 300kHz
B.the positive input ofCORE_O current detection
14.the negative input ofCORE_O current detection
15.CORE_O voltage detection input
16.the input loop ofCORE_O voltage detection
17.the input loop of CORE_l voltage detection
18.ClRE_l voltage detection input
19.CORE_I differential amplification output
20.CORE 1 feedback input,to the input end 0
21.CORE_l controller error amplifier outp
22.from this pin connecting the resistance
of the chip for
example,6.81 K.. is 300kHz
23.the positive input of CORE_l current
24.the negative input of CORE_l currentd
25.CORE_l boot-strap end
26.CORE_I high-end MOSFET driver si
27.CORE_I phase pin,connects the 0
signal
28.the ground terminal
29.CORE_I low-end MOSFET drN
30.the internal MOSFET driver
-194-
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coRE. 0 low-end MOSFET driver signal output
•
grolDld temrlnal
<;Xt>RE_Pl>hase pin,connects the output inductance.This pin is the loop of the high-end tube drive
~~~i~~~'~ MOSFET driver signal output ofNB power supply
fNB power supplY,connects the output inductance.This pin is the loop of the highdriver signal output ofNB power supply
is set to be 260kHz
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JL
7
8
9
10
11
RBJAS
OCSET
VDIFF 0
FB 0
CaMP 0
12
VWO
13
14
15
16
17
ISPO
JSNO
VSENO
RTNO
RTN1
'51
}]ifJ
)!~ 117kn ~J.fi~~±&, iilE~$~ilEft!mt
CORE 0 ~ CORE I i1¥m:f~H?iiji1~~tt.JA
CORE 0 ~7t1iX:*:~ I±l
CORE 0 &/~tNtrA, ~IJ~aII CORE 0 ~~1iX:*:ft((.Jt'UtrA~
CORE 0 ~*IJ~~~~:*:~1j1±l
MJ! -1' it }J!p i1 ~ EE!J.fi ilJ COMPO jfj 1i If 1f ~ ~ ~ , tl
6.81 k-..~ 300kHz
CORE 0 ft!¥ffL~~~iHII~A
CORE 0 Jtmt~~~ffJ.~i)'1A
CORE 0 Jtffi~~~!iu~A
CORE 0 Jtffi~wW!iu~A@]:m
CORE I Jtffi~~~~A@]:m
-
=*
~
18
19
20
2]
l$
VSEN1
VDIFF I
FB 1
CaMP 1
22
VWl
23
24
25
26
ISP I
ISN 1
BOOT 1
UGATE_l
27
PHASE I
28
29
30
31
32
PGND 1
LGATE_I
PVCC
LGATE_O
PGND_O
33
PHASE_O
34
35
36
37
UGATE_O
BOOT_O
BOOT_NB
UGATE_NB
38
PHASE_NB
39
40
LGATE_NB
PGND_NB
lE
!J..
CORE_l Jtffi~~~~A
CORE_I ~7tfD(:*:!ffij I±l
CORE_I &tJt~A, iU~tffI CORE_l ~~1iX*ft((.JUUAjfIij
CORE_I ~$tJft.~~fD(*!iu~I±l
JJd!1-ttlJl4Ja~ft!~.fi~U CaMPI jfj*iijf~Jt1f~~$., ~
6.81k...Jg 300kHz
CORE_l 1t~_lE.A
CORE_l lt~ajJ.
A
CORE_l EJ~
CORE_l ifti
~iii_1f~1;bffi%a<J
CORE_I," '
@lS&
~:Ii!!_
CORE 11
~~MOS
CORE oi
~:Ii!!.
CORE_O
@Ii!
CORE 0
CORE 0
NB~
NBM
NB
IIDf!:
NB
-196-
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vee
YIN
-
4.35
3.9
4.1
4.5
V
V
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Figure 9-75
the screenshot of the description of the electrical features ofPWROK threshold value
in lSL6265 data manual
ISL6265 ~Jt:(£ PWROK 79f~eg-'fM, ;f1:/FtJ.tAt SVlD m4t-, ffij~fRtm VFIXEN i~JE(8
~~, =/}~~T;ffi@egffi: VF1XEN j!*~U 1.2V ~ rWt~ 5V li:;(:j"Mj;J;tAt PRE-PWROK METAL
vro t~~, VlD ~IlB~egffim~ 9-19, iK#If1=~~r, SVC *1] SVD W79f~eg.sp:D;j, !iu~tI.1
ItI.fflg 1.1 V: SVC *1] SVD ~79~eg-'f81, ~tI:l egffilg 0.8V.
When PWROK is low level,ISL6265 chip does not implement SVID instruction,but implement
the corresponding voltage according to the state set by VFTXEN:when VF1XEN connects to 1.2V
below or about 5V,implements PRE-PWROK METAL VID mode,the voltage configured by VIn is
shown in table 9-19,in this working mode,when SVC and SVD are low level,the output voltage is
1.1 V;when SVC and SVD are high level,the output is 0.8V.
ISL6265 A~ VFlXEN ii~~U 3.3V lI1fftAt VFIX fl~, VlD DC"B9egffim~ 9-20, tE~
;rHbta:r, SVC ~ SVD m79f~eg.ifD;j, fflltl:legffi lAY; SVC ~ SVD W79~eg.if1l1, ~tI.1
r:gfflg a.8V.
ISL6265 trtJ PRE-PWROK
METAL VlD ~;:t.iij
~ 9-19
svc
SVD
.illll!Bi
0
0
1.1
.9-20 VFIX .~.
0
I
1.0
SVC
I
0
0.9
1
I
0.8
SVD
•
ill is Bi
When VFlXEN of ISL6265 connects tb
by VlD is shown in table 9-20 in this mode,Wli
I AV;when SVC and SVD are high level,the 0
Table 9-19
PRE-PWROK METAL VID
Table 9-20
VFIX mode decoding
Figure 9-76 is the typical applicati
ISL6265 B9Iffmtfi:mM 9-77 ~
The working process of ISL626S •
~ rPJ 1¥J~~~7J'll'trB], !i:rRJ§{1
-198-
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p;traJ 1-2: vee ~A, *~li POR (4.3V) , 7t1lX;;t-j:f i:J U IfL.
Time 1-2:Vee input and crossed POR(4.3 y),l0 complete the chip self reset.
p;j'1iiJ 2-3: sve ~ SVD imlijH~jU:tL§.jrHfL,~9:JE pre_Metal VID f-U~.
lime 2-3:SVe and SVD are pulled up or pulled low by the external.sets pre_Metal VlD code
p;j'1iiJ 3-4: EN ~;Jgi\ijI:\!~,Fo, VDD;fo VDDNB TfJi5Ji5i;7], J::JlilJ pre_Metal VID f~:rt
li1ltJCJit
0
Time 3-4:after EN changing to be the high level, VDD and VDDNB starts up.rises to the value
set by pre_Metal VID mode.
JlitIiiJ 4-5: VDOPWRGD ~73ii1iJEg3f, j'~1F CPU f:j:l~EgBiEm-.
Tune 4-5:VDDPWRGF changes to be the high level,indicates that CPU power supply has been
normal.
II'traJ 5-6: PWROK tt.JAiWi 1t->jZ, j~IF;t-j:f{fMb·~t15( SVI 1~~.
TlDle 5-6:PWROK inputs the high level,indicates that the chip ready to receive SVI code.
~1: CPU ~i;b SVD, SVC 7f~1~~ SVI m~
.
'J,
Udrives 8VD and sve to start to transmit SVI instructions.
-8: 181:;6265 ~~ SVI ~~m~
:18E6265 responds to SVI code instructions.
~: If PWROK ~;Jg1~, ;5Jt!?JL~.Il: SVI ffJ~1iI), Jj:~gi;b CPU Eglli¥1J
0
eta! VID li~l'Rmo
0K changes to be lowthe chip stops SVI decoding immediately,and drives
~Tn'!TI""~
_by RreyWROK Metal VID.
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* *
veCPYCC
1Vl00TA
YIN
GND
8VD
_La
-
IVlCU>C1C
IVC
-em
...
UQATEDI---J"'1
PWROK
BDDTI
POCO.
"=?{
"={
VlIEND
L.....TEDI-_ _.J>:-+
IlTNO
PGHDO1------1
VlIEN.
RTN'
-1------''------'
_'I-
---J
VDO_PL.NE_STRAP
>----_~0PINF1XEN
.---O/w,-_--i
_D
+-------i-
.......1-"""'--........"..-...,
DCSETI-_---J
.VIM
UGATI.I---~
t-'w..--u-_--1 COIR
-
.---""'IY-"""'T-;-'
+ - - - - - - - i ...
LGATI.I----'9
-1------1
1IP11-_ _--=:..----J
_I---J
..,..
t-'w..--II-.......,--i - .
.--.,......_N--"""'T-;......
.----il--.....,--1~..
-1 ....
L
00 9-76
Figure 9-76
z
vec
~ooooV'"t-t--r1i~
&Yc ---I'-'ooCl---+---+"""E
.YO
---I'-'ooCl---+---+.-;
ENABLE
---1--+--1
PWROK
---I--+-+--.....,-+.:=
+_+_+---
YDD IIIVODHB _ _
VO:=OGf ---1---+---+-""":"""'"
111 fa] 9- 10:
-200-
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1ime 9·10:PWROK changes to be high,indicates that the chip readies to receive SVI
~diri1CU· ODS again.
Jtt-rRJ 10-11: SVC, SVD f~~&lTO~ VID 1-~~o
'lime tQ-l1:SVC and SVD transmits new VID code.
~OO 11-12: ISL6265 ~z;/J CPU {,~rgrg&~1j SVI i&JER~wfrffio
Tune 11-12:ISL6265 drives CPU power supply voltage to the new value set by SVl.
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r it.6~*~n$] ~ tt3~~ !iL~;ff.=..#. t1i1 RTC tt3&-, #:.VL tt3~;fQJ6 ~~ ~J:. tt~at Jt£
,$.-ft. ,$.~.i.~l-Arit. CT6 7-J1ftli#-M RTC tt3&-, *~n5J~tt3&-~~Atlf.JJ:.ttatJt.
n
jr, i#-fflii-ZQ5 6~*~i'frfJ~tt3&-vAJLAXl ~*~nrfJ.%ttS!.
Chapter 10
Analysis of Quanta computer circuit
There have three kinds of the protective isolation circuit of Quanta,the RTC circuit,standby
circuit and the sequence of subsequent trigger power-on are basically no difference.This chapter
mainly takes CT6 as an example to explain RTC circuit,protective isolation circuit and complete
power-on sequence.In addition to explain the protective isolation circuit ofZQS and AXI.
Analysis of Quanta CT6 RiC circuit
}~Jt CT6 B~ RTC rt!.Jm±~~,*1m""fJL~-M
32.768kHz, INTVRMEN.
The RTC circuit of Quanta CT6 mainly includes
RTCRST#, 32.768kHz, INTVRMEN.
1. VCCRTC
~mA"J VCCRTC *~~~1«la~ VCCRT:G,
The name ofVCCRTC ofthe South bridge •
ICH
Vc:I:RTC . . . . - . - - - - - - : : : : :
III11H
Figure to-t
VCCRTC )g1'rt!.ffiB"J*~, 1m1li
~i:t R196, D5 F~: ~ 3VPCU 1'=
:JJoiU VCCRTC. l29=fiH11. OS
PJJf.rt!.rt!.rlP.: 5VPCU r£3:J: R201 ~
202-
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U~J1l1 JJI4J_tI:l, E@.ffi~ 3.1 V jL;(j, Jlt 3.1 V ilt~~ BTl ftrb..
gm ofVCCRTC voltage is shown in figure IO-2,when there is no extel11a1 power supply.is
CMOS battery BTl with 3V through R196.D5;after 3VCPU producing (the principle of
~ is shown in 10.3 section),3VCPU with 3.3V is added to VCCRTC through D4,due to the
A;li_mstiC' of the diode,DS will be cut-of'f,CMOS battery can save electricity.ln addition.the CMOS
~ in this clrcutt is a rechargeable battery:5VCPU produces 3.8V voltage through the partial pressure
bf:BlO l and R203 to the B pole of Ql8,the triode Q18 will convert the voltage of 3 pin input to 1 pin
~thevOftiige is about 3.lV.this 3.1 V is directly charged to BTl.
J111<r21:f ttHl7J'7 RTCRST#rfl*1mi, ep VCCRTC jf'ffi'J§, ~~u R198, C220 ~ot
at ~.4tF.!f 1iJ~J.W. CMOS tD!:rt.
~ 10-2 also shows the origin of the RTCRST#.thal is,after VCCRTC being
through R198,C220.G 1 is the short contact,CMOS discharged can be
CKL:Cl/C2: 18pF -> CL:12.
Cl/C: lOpF -> CL Value
8.5pr.
=
~ ~
tpdnt for SMT
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Figure 10-2 the screenshot ofRTC circuit
4. INTVRMEN
i¥jmO~jH'l--l'itB(j{JR1'C f*~-IN1'VRMEN,
?tt&HJH~~A$lBa, Jltf*-'%?'£ ICH7
r*J-B-IXB~}:E)(Jg;
Internal Voltage Regulator Enable:
This signal enables the internal 1.05 V Suspend
regulator when connected to VccR1'C. When
connected to Vss, the internal regulator is disabled.
( r*J 1m It lli ir.J li ft fj~: ili J3: l' f§ -'% i! ~ ¥~
VCCRTC, PJfflT7f~ r*.I{flI(j{J 1.05V q~H)1.ltllio
3J3:l'f*-'%itf~¥~±t!!.,
r*J1m~lli~~lBZ~ffl 0)
VCCRTC
ICB7 internal VR
enable sttap
R2D6
INTVRMEN
332K
ICH IIffiIRMEN
Enable
(default)
1
Disable
0
R2ll5
'O/F
~*i¥jm.~J3:l'ffl-'%, .~~.~M~~.o
lltf*-'%tE C1'6 4J(j{J*~, :IlnOO 10-3 JiJT7f-:, 004J
00 10-] INTVRMEN ~ilHI&OO
R205 1~ ff ~ ~, IN1'VRMEN Jm M R206 ft
VCCR1'C J:ti/SJ~, i5tJ:EJg7f~i¥imr*J{flIa<J~lliBo
Another key R1'C signal of the South bridge is INTVRMEN,is easily overlooked by many
people,the definition of this signal in ICH7 is:lntemal Voltage Regulator Enable: This signal enables
the internal 1.05 V Suspend regulator when connected to VccRTC. When connected to Vss, the
internal regulator is disabled.Ifthe South bridge hasn't this signal,it will lead to not trigger fault.The
origin of this signal is shown in figure 1O-3,in this fi
OS is not installed,INTVRMEN is pulled
up to be high by VCCR1'C through R206,and is set
9 ~ regulator to open the internal of
the South bridge.
Figure 10-3 the screenshot ofINTVRMEN eire •
Analysis of Quanta @
:Jt;*~~ j
it C1'6 (j{Jf~HFIWi ,nlJJt; t:!
Let's look at the full figure about the
C1'6,is shown in figure 10-4.
00 10-4 4J, 0~Bt:I!Ek (1£: ~
-204-
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.
.i
~
~
Lil
~q~
..."•
~0
S~
,!,
'"
.:¢:
"""
.=fI
.:nJ
~
~
j!:1T
IcE
=-
~
OlE
..,...
"='
t-
U
"7
-0
~
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-'f8~ ACOK, ~I]OO 10-5 JiJT7.J'o
In the figure 10-4,the production of the common point(the battery and the adapter pass through
this point together to supply the power to the system,then this point is cal1ed the common
point)voltage VIN,need to go through PQI5,this P channel tube need to be conducted,and controlled
by PQ4,and PQ4 is control1ed by ACOK with high level,is shown in figure 10-5.
Figure 10-4
the figure ofCT6 protective isolation and the charging circuit
VA
BATTERY CHARGER
ADAPTER 18.5V 6SW 3.S1A
VIj
5ecoDd:BlM66790014
V","
POlS
VA3
_
-
UII
PR3D
~r*-~*~ ACOK B'-Jf=~: 1LOIII
~lI VA2 -~{fr-~ MAXI772 B'-J~Jt!..8iP
5f1J 4.096V B'-J~ftE~J.li <.~OO 10-7);
MAX 1772 I¥J ACIN JJ!II
Let's look at the production of ACOK:
0
and the adapter interface voltage VA2 suppl
MAX 1772 produces LOO voltage 5.4V
other path through PR40 and PR49 divided •
-206-
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....
-
At<><
PRI~l
0
....
~
'
''I''''
""
11110-6
~
•
~
t
MAXI772 B~ DCIN jf[) ACIN f.\!JEi'\-~
Figure 10-6 the circuit diagram of DCIN and ACIN of MAX 1772
r - - - - - - - - _ + _ DCIIJ
r - - - - - t - LOO
REF
the internal block diagram of the LOO production of MAX 1772
eIN and ACOK in the MAX 1772 data manual is in the
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grounded,YA3 through PQ5 internal resistance and PR46 divide into the voltage,after dividing into
the voltage,the conducted condition of PQ 15
is satisfied,and produces the common voltage YIN.
ADAPTER 18.5V 65W 3.51A \'II
~:BIM&679001.
VKJ.
PO,S
Pl.,
FlII&J321Ii1lll41l111T\&
I
11o.....'!'~ "':EMI:=-ofI
~SI-2 "modified
"
PR30
PIMI
4.711
PR3lI
4.7.
1l1(li
PC17
+'~+i
::1
I~~
REV.B
Figure 10-8
the production circuit ofVIN
m7f-: it.2.;tr +ttSi~i.i t:, -.*om 10-9 ~;f.', ~
~~~~ttSi.
~*+~~~~~~~:
Note:there is a circuit to be payed attention;as
the battery mode,is the battery low-voltage prote:cti
J!1-~~~9=t1¥J SL/C#~ D/C#~~~i:!m.
SL/C# and D/C# in this circuit are used in
~~-Hm~~, SL/C#~ EC ~~~iiJ,
fj!p, 4 }j!p7fim!fDtr:±l IE 3VPCU ..tt'L~iiif@.lf,
~ij, PQ36 W/f'~~jM.
Under the adapter mode,SUC is driven as •
comparator PU lOis greater than 3 pin,4 pin
3YPCU,and added to S pole ofPQ36.AttlliS
not be conducted.
~ltt!mJ:tr, SL/C#/Fill EC JE)(;,
PRI46 *19C7.tlli~ PD19 (J(JttHILki,
Sf, JltIl1 D/C#~1Jt EC !JgZ;b}!giffi~
~$~I¥J~~~~. ~~EC~J~
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er the battery mode,BLlC# is not defined by EC,the initial is low level. When VIN voila '(;
ftJllPlUttbrough the series partial pressure of PR 14J and PR 146 and the clamping or PD 19,it \ also
.P~ than the voltage of the comparator I pin. the comparator 4 pin output the low Icvcl.at this
~ C will be driven as high level by EC,make PD7 to be conducted, pull lo\v the I pole 01
pQ4~ut-offPQ4 close the isolation circuit of the adapter.At the same time.EC receive BL/ # with
loW I vel;ii1dicating that the battery voltage is enough.
fI~.!it"F~ VlN r4!J.liftkfl¥O 7.5Y ~rnt, bt~x~:t- 1 )J!4J )-.::.J:' J )J!4J. 4 1]1.II~iJ~IIII"JIl!,
~PRl44 JSF1=..Jt~1¥-J BLlC# (~El=J.fnt Batiery Low 7fHf). Mr-II EC ~Jl1J'ltJrll!,o
OC ~~tJ<J BUC#4t>~fIltJ PQ34 ~jffi, ~t:£tL1IHt~-X*rr J IJLIJ. i~HT-bt~ ~~+!J;IJ)': r -y;I,;(j(J'h'j
.witiJt~tr<J BUC#, i!1- § lJJl r.[:J.~PJ ~~lJl. EP.itJ!.:r ).1 (~tlJ"r)JfjE:. n 'W'l:ldl'fa:~ 1lJ.
....
mOde,when YIN voltage falls below 7.5V,the comparator I pin will be
bUtputthe high level,produces the high level of BLlC#(Batlcry Low i valid
~.~'F~I44infonn EC to execute outage.And the high level of BL/ II will
&nci~:edtlcoDtinues to pull low the comparator 3 pin.and keeps the comparator
Pl~~WIJys output the high level of BLlC#,the lock-in circuit can real ize the
~5liQ~.f8nctjon. When the adapter is inserted again,it can be unlocked.
PR3I
100K11l
P04
2N7002K L.F
PQ38
2N7IllI2EL-F
21
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JL
Analysis of Quanta CT6 power-on sequence circuit
0:Jtr2: VIN 1J~~~ MAX1999, f2ii PR79, PR80 7tff~ SHDN#, ~lDOO 10-10 ffT-jj;.
m
41iS MAXI999 n~I11=J*lID, MAX1999]A L003 Jjl;p~ LD05 Jjl;p7t§Willtrtf:l3V_AL SV_AL. jt
r:p, 5V_AL Xi!ftl;t;:ftl'r..J VCC)]!P, 12J.,& ON3, ONS. vcc iEJitJ§, rz:~ 2V ~IiItlI,
ON3, ONS iE'r~J§, MAXI 999 tyftjIJW3~~ PWM IfF, 7t~IJrz:~ 3VPCU, SVPCU. ;t;:ftI1"F
if 'ffi §, 1f~41)'tl tf:l PGOOD, itti¥tl HWPG.
The common point VIN supplies to MAX I999,through PR79 and PR80 divide into the voltage
to SHDN#.is shown in figure 10-10.According to the working principle of MAX1999,MAX1999
outputs 3V_AL,SV_AL respectively from L003 pin and LOOS pin.And SV_AL is sent to VCC pin
of the chip.as well as ON3,ONS.When VCC is nonnal,it produces 2V reference voltage,and when
ON3 and ON5 are nonnal,MAX1999 controls two paths of PWM work,produces 3VPCU,5VPCU
respectively.After working of the chip being nonnal,open leak outputs PGOOD,and connects to
HWPG.
5VPCU f2ii POlL PC63 !:3 1999_0L3 .1m, ~M: POll, PCS9 §~~~I±I+Iov.
+10V fI}~rlPOIO, PC62, PC611t~rz:~+lSVo
5VPCU through PDl1,PC63 and 1999_D
POll PC59rectifying.+10Vproduces+lSVtbroug)} ~ e
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I
~II
.
0
0
0
..:::
..~g
:
~
~
I I~'
H
<
• ~ ~
~
0
g
::
~
<
;
~
.~
~
8
•
~
~
Hit. ~
~
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f=~(j15VPCU j!~ l~fJf(j1 V5REF_sus, ~IJOO 10-11 JiJTJJ'o
Produced 5VPCU to send to V5REF_SUS of the South bridge,is shown in figure 10-11.
3VPCU It!ffi f;tt~ EC,
fi;g EC (U23) fflm It!ffi, :~1IJ 00 10-12 JiJTJJ'
0
3VPCU voltage is supplied to EC,to be EC(U23) standby voltage,is shown in figure 10-12.
5VPCU
R218
'0
C250
+'u
Figure) 0-11
V5REF_SUS power supply of the South bridge
Figure 10-12
EC standby power supply
EC jH~ 32.768kHz ~~jf9~, Jg EC mf;ftffl~l.Ij;tB<Jp;j"~, :tm1ll10-13 .PJfJJ'o
EC external 32.768kHz crystal oscillator,supplies the clock in the state of standby for EC,is
shown in figure 10-13.
•
_-..J&l-
....
+-
..J!&..,..,....II...--~-
..::JT_
_
we
- ...
~
11110-13
3VPCU ~J1It!~.EI., It!~~p;j", Jg Ee P.€8~
3VPCU delayed through the resistance,ca~
EC PC87541,is shown in figure 10-14.
EC jiR;i1 X-BUS .~~iillJ( BIOS ~
00 10-16 JiffJJ'o BIOS B<Jf;ft1t!-&:J!3
EC reads the EC code stored in
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M.lIllIllgw~ 1()'1 Jigure lO-16.Thc pOwer slJppl) ofBlO
~,[~~~~~
..,
11110-15
Figure 1001S
EC (('1 X·BUS ,',Jr.!::
X-BU' bus of I:C
8 bit (1M Byte), TSSOP40
--C:::>!lI' 7]
DO
D1
lIZ
DO
DO
1M
DO
DO
Dr
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Figure 10-17
EC receives the switch signal
EC tstl±l 55_ON )!JiOO 10-]8 jiJTffiJt!.N~F~3V_55, m~i!~T~*1¥JVCC5U53_3.
EC sends S5_ON to produce 3V_S5 through the circuit as shown in figure ]O-18,and finally
sends to VCC5US3_3 of the South bridge.
""_SS
YIN
.oo
-..
86_ON
..,.,
PR171
PQ!l1
tlr*, EC ~B1tst:±l RSMRST#£i
Next,EC delays send RSMRST# to ffie
RSMRST#~~7i¥.i~,
•
5l:dLtR1, LID_EC#E8 3VF
DNBSWON#591,
)!Ji D20
jlfr7f' •
RSMRST# is sent to
AClN,LID_EC# are high(as s
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1 by 3VPCU).sends the pulse DNB WON#59I with "high-low-high"
~di'~;lQb:lI.erlS to DNBSWON# through D20 to send to PWRBTN# of the South bridge,is
~~Iute 10·21.
lvPCU
1\R420D
PV-l modified
R417
33KIB
015
Close to EC
-""'----"--t!--'-----t---{=:>L1D_ECIl
LID
00 10-20 SW I rt!:m
Figure 10-20 SW I circuit
--""-
""""
OHRS~,
ioPw.o;i
......,,,
"""""'''
""""",.
1OPII1.o1S
nn",
CSI
<:so
TO>
om
'EU
EC
QJ(
RSMRST. 28
~sus
..
SUSOl!
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Jl
upply i normal.open leak outputs POK.and connects to HWPG,is shown in figure 10.
210-
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-
.....
•
+--
~MI
"
c:::>- ,.
.........
/;;m--JII'
ab
MV-l modified
r=
_
~:rR~ l1-
__nus for
;I
--_QIII
171KIF
rr
rc:o
lU/'OVmoo3IX5R
~LJ\4
:::::::=I:::::
I
mSJ
PR16'
"..
I'iz 1.8V Output
'10M:<:
...
Cl
~~
"1YI'
all
'7V('1:.Ba/IU»
..
5
-_
"""""
'"1
-
I>i=
l"'f.
II~
~::J
.7llrJ.OV/040'lX1l1
H
r=
Vcs=I_L(A)+L_DCR(rnOHH)=V_ILl
SI-2 modifi.ed
dlt~
ru
(/'J
~
§
rEB-
o
a
(D
p..
~
n
S
o
§
(/'J
~
f¥I 10-23
I)~ {f.:t f1t rl! ~I(J f" ~ rlH'~
rEB-
5)g
tl)
~
Figure 10-23 the producing circuit of the memory main power supply
SUSON :?J-~~* PQ41 ~Ji!i. PQ39 :jjGlt. ;n:~~Ft!.-'f 15V B~ SUSD.
tznOO 10-24 PJT7F:o
The other path of SUSON conducts the PQ4I,PQ39 is cut off,produces SUSD with the high level
15V.is shown in figure 10-24.
.....
""'56
1M
22A
G
-
II
"""
OTC1oUEUA
I¥J 10-24
SUSON t!11itlf'1:. SUSD
Figure 10-24
SUSON control produced SUSD
SUSD FIBlH~iI1IJ PQ37 fIl PQIO ~iiB,
tz:1=. 5VSUS ~ 3VSUS, :mllllD-25 ffi7J'o
SUSD is used to control PQ37 and PQlO conducted,produces 5VSUS and 3VSUS,is shown in
figure 10-25.
PCII
L,ul•••
M
'F
00 10-25
Figure 10-25
MAINON J=IBIUf ~ tUfF l@.ffi:
MAINON is used to open the follo~
CD MAINON ~11iIJtz:1::P3fj~.iJt«
M~o~~-~~~~~iJtl@.~~~
~w~1±l VlTREF: ~fU VLooIN, S315
MAINON controls to produce the
SMDDR_VTERM),is shown in figure to,;
•
and the reference voltage after getting
-218-
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3 it will output VTItests the voltage of VTr by VITSNS.
the production of the memory load power supply
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.
~ ~G ~ ~
~
,
i
.....
s,
ii
I
~
Ii!
~
s,
i
~
~'~
II.
~
•
~ ~
0
t='
~
.......UIWI
. (-r1~.
J
I
• "H'CIX7R
~
~
~
'II
•
~ <If----!
B
I
...I
..
N
i0
II'
0.t!H'"
I"
II'
~
..Il: I3 ~ h~
~I ~
D
f~
R
I
I
I
• ••
-220-
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the production circuit or + 1.5V and = 1.05V
00 10-28 MAIND D~f"~
iFlgure 10-28 the production of MAIND
irSV ~+3V, :(WOO 10-29 FJT~o
iDd +3V with the state of SO,is shown in figure 10-29.
3VPCU
POlO
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signal.it will lead to the common fault of power down for Quanta motherboard.
18~
lIP
MY16
IOPJ2.eSTO
I ~
~
VOLME lJPjJ
--.... VOLME DNf.
~
~ 10-30
Figure 10-30
~~EC
IOPJ5IPfS
IOPJ8IPU
_
IOPJ7IBR1<L_RSTC
EC ~~iU HWPG
EC received HWPG
EC 45c¥V HWPG J§, ~Bt£tl1 VR_ON ~ CPU t:tt~~):f 35 )Jtp,
m**Ji5 CPU ~Eg
VeC_CORE, CPU ~~iE~J§, £tl11~Itfl¥J VR]WRGD_CK410#fIl~~fl¥J DELAY_VR_
PWRGOOD,
:tmOO 10-31 JifTii-.
After EC receiving HWPG,delays send VR_ON to 35 pin of the CPU power supply chip,is used to
open CPU power supply vce_CORE,when the CPU power supply is normal,then sends
VR_PWRGD_CK41O# with low level and DELAY_VR_PWRGDOOD with high level,is shown in
figure 10-31.
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~
~
.:iJ
='
....
,
. .
J
l
:::l
0-
U
M
I
:=
:;r.l
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Figure 10-31
CPU power supply circuit
VR_PWRGD_CK410#~ffJElIJ1~~)=-t, 1J1~~Jt:&ili~~IJ1~, :(mOO 10-32 Jifl7Fo
VR_PWRGD_CK410# opens the clock chip,and the clock chip sends each clock,is shown in
figure 10-32.
:S=513=31
~:~ =~= 8_01::::::;-,
,.
.,....._.4e<::::J-IlIIl.,.,..".....a..,
VR_PWRGD_CK410#liiJlJ'.tlmrJ:
m
CPU 1~Et!. E.~~iE'M", :(mOO 10-33 fi.
VR- PWRGD- CK410# is sent
inverted,infonns the South bridge
."..,
figure 10-33.
CPU #t It!. ~ Jt tit I±lI¥.J DEfu
'&ilil¥J PWROK .tD1:§, .I±l J
CPU power supply chip
sent by EC after receiving
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......a ••. ,..
3VSUS
51-2 modified
CIwlate La '.11
=
wWi'l(j(jIJ PWROK
the South bridge received PWROK
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ADn
AD,.
AD1I
AD20
AD21
ADZl
AD23
AD24
NJ25
AD2ll
AD71
AD2ll
AD29
AD30
IRDYI
Ii!I
,e,.'
PAR
18.41
I'l:IIISn
'''9,.'
lJE\'IEU. 1.,4'
PERRI
SEAM
STl:lN
1',41
19,41
, ...'
TRO....
19,41
FRAMEI
1.,41
ADJ,
+3V
t~~~1N19
INTF.
::PAD
111
11
O.1UI
C187
1115 PAD
Tl81 PAD
T112 PAD
~
T RST
J-f--C:> PI.lRST. 32.33
R'87
',KIF
00 10-36
Figure 10-36
~ffi::&:±l PLTRST#.f[l PCIRST#
the South bridge sent PLTRST# and PCIRST#
PLTRST#~9Jff-i&i!~7~tffi:1¥J RSTIN#JJtII, DELAY_VR]WRGOOD tBi!~7~t
ffi: , ~IJ 00 I0-37 JiJTlJ'.
One of the path
of
PLTRST#
is
sent
to
RSTIN#
pin
of
the
North
bridge.DELAY_VR_PWRGOOD is also scotto the North bridge,is shown in figure 10-37.
16
ism
n
itifr5, ~tffi:Q::±l H_CPURST#!t OP
:±l H_ADS#JIJ~tffi:B~ E8 JJI4J. ~ifJtfliJ~
fiX, , CPU B7H&~:I1I:.
At last.the North bridge sendS H:....
receiving the reset,sends H_ADS# from
signal from T4 test point,then indi
started addressing.
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H ADS# 3
H ADSlBIIO 3
H ADSTB#1 3
H BNRtI
H_IIPRJ#
o
11110-38
3
3
H BREOIlO 3
H_CPURST# 3
H_DBSY# 3
H DEFERtI 3
H DPWR# 3
H_DRDY# 3
~t~~l±l CPURST#
the North bridge sent CPURST#
Acer as4733z) protective isolation circuit
;fltI1i 10-39 ffi7J'
0
PL12 is shown in figure 10-39.
!JI.""'''5U..
VA1
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Figure 10-39 insert adapter to produce VAI
VAl jiJi PDIO ~ PQ56 /tFi~¥U:it:0~,B VIN,
:(Lolli 10-40 JiJi7i;. PQ561¥J~jBlf-·f!j:~,
G fJ1~ffi~;f1IMfl£~5JZ, iliff)t~i.sl PQ5 I¥J I JJtIJ*O 6 JJtIJ~ • .l1:, VAl iiJi PRl9 ~ PRI7 'tBi
t-J 9.5V tiki •
VAl reaches the common point VIN through PDlO and PQ56,is shown in figure I0-40.The
conducted conduction of PQ56 is that the voltage of G pole should be low level relatively,that iS,1
pin and 6 pin of PQ5 should be cut off,VA2 partial pressure to be about 9.5V through PRI9 and
PRI7.
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>
~
~
HII'~i'
~~
HI'
~p
~
",
HII'~I
~
~,s
~
gi
•
II
Ii
- >
&
3 ~
~!
-",
E?
~
~
~
,,1
~
ON
~!
fl
=
~~
;Z;
,...
:>
ON
0
'<:t
6
~
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Figure 10-40 the producing circuit diagram of VIN
PQ5 ~1 I Jl!lI~ 6 JJtlJ~J1:~{tf~ 2 JJtlJ~7'.1~etJ.1f (PNP -=:m~), 2 Jl!lIEmitfm 3 JJ!IJ, tE.
lj1JtfiJ~UgHu~~ 31l!111O 4 JJtlJ-JE~~J.I: (NPN -=:f&~), JiJTl;/- 5 Jl!lI D/C#~7:J{I£etJ.1f· D/C#*
EI r EC, lj!ffH~~BIJt, E13T*~fXJIJ~J:etJ.ilffi, J§mfjl:etJ.~*f=1:, EC xlitetJ.. D/C#~1ll;
I:@. 'fL. JlJT l;/- VIN PI l;/-lt
*I±l*.
The condition of I pin and 6 pin of PQ5 been cut off is that 2 pin should be high level(PNP
triode),it also can be understood us 3 pin and 4 pin must be cut off{NPN triode),so 5 pin D/C should
be low level.D/C# comes from EC,when used the adapter singly,due to the system just connected to
the power,the subsequent stage power supply is not produced,EC has not power supply.D/C# is low
level.So VIN can come out directly.
D/C#B1~,ffi.: ~etJ..if1Jt DISCHARGE,
{1£etJ.5jZ1Jt CHARGE. J1t~.Rff D/C#, Wi
BL/C#, ftHm ~ ~ffi~ll: , ~ Ie -B~ mUIJ J§ D/C#:t:J {I£ , etJ. ¥tl!. m Jt r 7:J iWi. m r
~ tfT EC
81 ~ iNC ~ ;jft iYm etJ. ~ •
*
The means of D/C#:DISCHARGE in the high level,CHARGE in the low level.This
board just have D/C#,not BLlC#,according to the actual measurement,the adapter is low
after detecting D/C#,and is high in the battery mode.Let's us analysis the adapter detection
circuit of EC.
VAl ~uPD1 ~PR78~ISL8873lI¥JDCIN~Et!, :tmOO 10-41 JiJT7.J'.
VA I supplies the power to DCIN ofISL88731 through PDl and PR78,is shown in figure 10-41.
VAl
PRl81
I ......
AClH<::J----+----4-----'
;flHJ.!i ISL8873I I¥JI*J~~I!I C.roJ
~lJ VREF fflj I±l Et! lli I¥J IW -m: f£'dl~
A1 E~/4:.*f·t1ti'ii~:tmOO 10-43 Hf/$,
~ I±l Et! lli:f'ff- (i {! 73 5.1 V, VDI}
tflE/j\T 30mA nt, ttylfJ f@.li~:Ii:
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v (fi- (1H~i.)
0
mal block diagram(shown in figure 10-42) of ISL88731,ISL88731 will
the description of the electrical characteristics about the the threshold
F output voltage in the data manual is shown in the figure 10-43,the
Output voltage is 5.1 V,when VDDP load current is less than 30mA,the
F output voltage is 3.2V(the standard value).
K ~i3I)J!p~5Z
pin definition of ACIN and ACOK.
Detection Input. Connect to a resistor divider from the AC adapter
ut This open drain output is high impedance when ACIN is greater
remains low when the ISL88731 is powered down. Connect a 10k
5.0
3.168
5.1
5.23
v
35
100
mV
3.2
v
cation description about the threshold value or VDDP and
voltage
i!JEft~~JWiu"tr 1±\)Jt;p
0
~ ACIN
e£!.& 1'<0 T
IS.Ilre ACOK ii~~tl VDDSMB )).~o
• ;ACOK is the adapter detection output
o 1J!ge 3.2V,ACOK open drain output,it
49 and PRl50,then is sent to
VAl through the diode
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II
I I/) I I
I. un: 10..
11I1X J,t r II
.11 1,;,11 ul,IlI(l11 (If III
eric partIal pre ure
fltfl:NJd'.
CK ·n;"JfM"uHII, rl13VPCU rn:t PRJ31 L1-JFix
J1ltf J,J III. IIf \)),1 n n D' # J:J1l It! V-· PO IS iJ,t!l:. PQ39 (Ij G tl%11J
fix ,'t! PO 9 'II. 1t!'l!!.fI!i . tzlll¥! 10-45 ffr/r-. rg7l!!.~J:t
J 'I IJ tl!.thZ. VI . I HiirJ:J 'I: EC fr.Ji}t.. rt!, EC f,'oL&IJfIJ:ffH~
I.
I {-/,ji PR40,fU PR39 -rrlli, 1'039 7i:!F.:-~j!!L
PQI5 Id:J.
II th
olt 'c f A I i not lo\\cr than the limit valuc.ACOK will open drain output3VPCU
Ihr 1I·1t PR I I and i pulled up 10 be 3.3 V.then end to EC.A fter EC receiving this signal.can keep
I)
It he Ihe 10\\ I vel.PO 15 i cut off.G pole of P039 i pulled up to be the high level by V£N
Ihr II 'h I'R40 dire tl .1'039 i cut otr.thc batte!) is isolatcd,is hown in figure 10-45.ln the battery
m J Hr I pt lUll
mall current VI through P039 diode.then produces the power supply of
I dCI' I Ih hi h Ie el of D # nt by the adapter.and makes POlS conducted.VI paniaI
pr 1II tltr III ·It I'R40 and PR39.P039 i conducted completely.
-
- -'
[
- -'
•
.....•
IAT
1111
,
II 'un: IO-4S
JJ 'J'.r .Jlo 11l~
"
.
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ItmC~.~ to through PD20,PQ52 from the adapter CN 17 to the common point VIN;and it
ugh PQ55 from the battery CN 16 to the common point.is shown in figure 10nneeted together to the G pole of PQ55.are BATDIS_G.lf BATDlS_G is high
11 be conducted,PQ55 will be cut off;on the contrarY,PQ52 will be cut off.PQ55
cted.lfit needs the adapter supply the power to the system,then BATDIS_G must
and the voltage should be high enough(more than 23.5V).
-
VIN production circuit
in partial
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0010-48
m10-47 PQ52 1tJ&
Figure 10-47
PQ52 circuit
Figure 10-48
partial pressure calculation
:It lliit~
~ r *j1zp7tfJT~=:1-~1tj::
Then,let's US analysis these three conditions:
+VH28 *§-f" PU2 (P2805MF),
~{tj:CD:
~IJOO 10-49 JiJT7F' ~~-1-P3mImpX;771-1I
i¥.~I¥J7Tffi.~Jt. 19V I'f.J VA ~j:J: PDO JU+VAD 1, ~~ PU2, PU2 I*JmJ7Tllif=~+VH28.
37tffp,X:J}])§, ~Jt7ni~tI:l6251ACIN.
Condition CD:+VH28 comes from PU2(p2805MF),is shown in figure 10-29,this is the boost
chip with internal integrated the boost circuit.VA of 19V through PDO to +VAD_l,supplies to
PU2,PU2 internal boost produces +VH28.When the boost is successful,the chip open drain output
6251ACIN.
1
-
..,IQ 1
~{tj:®: ACOK#E8 ISL6251l'ro A
Conduction ®:ACOK# comes frO
.VA
.......
.YAO'
.....
-.'
-
- .4
-234-
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Figure 10-50
the origin of ACOKH
tro.llc.¥JlIfiiJ~[l ACPRN A~5IJ]EjJ1.E)(; Open-drain output signals AC adapter is
pUlls low when ACSET is higher than 1.26V; and pulled high when ACSET is
the data manual of ISL625I ,the pin definition of ACPRN:Open-drain output
ris present. ACPRN pulls low when ACSET is higher than 1.26V; and pulled high
1 lower than 1.26V.
*7-
~CSET
1.26V, ACPRN fJ.ttiL1r£; 3 ACSET 1r£r 1.26V. ACPRN *ltJiiGJo
O*:ar~fl:I:l, +VA ~2ii poo f=~+YAO_l. -a~~rl PDI ~f?i lSL625I OJ OCJN
~P1U35, PR236 *lli~f?i ACSET. ISL625I r~~IJ OCIN j5}A YDO fJl:Wfritrtl:l
~,at~ S.07V (A~ffi), ~D 00 10-51 Mij;
0
o-50+VA produces +YAO_I through PO-,and supplies the power to OCIN of
otberpath is to through PR235,PR236 partial pressure to ACSET.ISL625I
VDD after receiving OClN,the voltage is 5.07V(the typical value).is
4.925
5.075
5.225
_
VI
electrical characteristic about VDD output threshold value in
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00 10-49, 00 10-59 9='~~.
CSET JJ!4Ju~ 6251A IN {;; ~}lfiJlI1ii~fIJftlli~Jt PU2 O~
PG. tm~ PU2 Jffj~fi.tI:hfl-ffi, 6251ACIN f5J~~WU.!L{~o )
(According to the figure J0-49.figure J0-59.6251 ACIN ignal of ACSET pin connected to the
PG of the boost chip PU2 ifPU2 does not succeed in boosting.6251 ACIN will also be pulled low.)
~f!j:@: ACOK_IN it~f1J PQ9 • .(mOO 10-54 JiJT~o ~{Bf!·iHg: ACOKJN /f~j~J:t!!.. PQ9
~,@f~Jt. W~!.1Z·@f~f~1f!3f1¥.J O/C#o
Condition ®:ACOK_IN connects to PQ9,is shown in figure 10-54.To keep ACOK_IN not
grOlmded.PQ9 must be cut ofIthen there must have the low level ofO/C#.
Figure 10-54 ACOK_IN connection circuit
D/C#*§r EC. ~lloo 10--55 J:i)j/J • 1£~~,Sjfwn=~z.iW. M=m;c::JttIJ/f'I{'F, EC ~lf
~1I, ill/f~I{'F, .Ptr~ DIC#/f'~;Ig~Et!.3f; 1£ EC ~JU~If!)§. EC !.1Z\~~~~¥U~nGMtE
(ACIN~~). /f~{mDIC#73f~o ~.Ec~J~E., O/C#~~EC.~o
D/C# comes from ECJs shown in figure lo-S5 beforeitbe common point produced,the standby chip is
not working,EC has not voltage,and is also not
will not be high Jevel;after EC getting the
power supply,EC must detect that the adapter .
will keep O/C to be 10w.lfEC is
not detected the adapter,D/C# wiJI be set high by
U'/O
MY1
MY2
IIY3
MY4
IoIY5
MYlI
MY7
MYlI
MYlI
MY10
MY11
MY12
MY1
MY14
ii5: !!C ~
::7
AON
-236-
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gtIl't 10-55
the srcen-hOI of D/C# and ACI
*- ~IJ 00
of EC
1l\; ,,:!;~p: nj ACOK# N ilJu PQ10 -B: ir1l , re
~ PR84, PR85 )t)£ fr.1: ACIN ~g- EC 11=Jg~~;m~f~-5.
_1*ii1estsignaI ofEC is shovm in figure IO-56,ACOK# with low level controls PQIO
10-56 r1T 5F,
~~~l"':VDD to ACOK,then through PR84,PR85 partial pressure,produces ACIN to
AC
'ISLG251 VDD
POlO
OOTA124EU....1-F
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!ti ilJ a~ t£.33-;fo at It ~t ~ :k.. 3Ht e.-, -I!!. ar l-;J. -it$.- ft e.-;f..t Jt tf j t tf f.e. -+t RTC t£. 33-lj t it
~~~, t£.~-.Jt~ar£t£.~, ~t£.atlt~~£~~~I~~#*atlt. ~.~J~~
RTC t£.33-;fo~ t£. at Jf, .i-~1*11!lf.-r1,fdn~ r% ;fo#*1l. t£.33-. {.l r;ljt: l-;J.tfj €'l HBU16-1.2 ~ i~1
~ ~Jf*-tt f~ r% ;fo#~ t£. ~.
Chapter 11
Analysis ofWistron OEM laptop circuit
The circuit and sequence of Wistron are not too many features,it can also be said that its feature
is quite satisfactory.The RTC circuit is similar to those of the Quanta,the battery is usually not
chargeable,the power-on sequence is the Intel standard sequence.This chapter is not much
introduced the RTC circuit and the power-on sequence,mainly to explain the protective isolation and
the standby circuit.Then,as Wistron HBUl6-1.2 an example to analyze the protective isolation and
the standby circuit.
11.1
Analysis ofWistron HBU16-l\.2
mA~1!C~, j"L1:: AD_JK, 1JoJd Ul £j(J S at
.If, ~*IJ UI ~ialj"L1:: AD+ (1:ElXJdMA~IG.
1L*~ftf~ff~*'JX1Eg¥tB~j*tl$: Eglt-t, EC ;t~~m
Insert the adapter,producing AD_JK added to
and R 1 produced the low level of 6.3V,controll:J
adapter,because EC is no power,AD_OFF is low 1
to discharged the battery,then EC will send the hi
Adaptor In to generate DCBATOUT
DC'"
l05.106
>12.106
-2:38-
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Figure 11-1
the screenshot or AD+ production circuit
~U2 tro1*-t&'lrrz:~/J\E@.¥m:U~0;tt8 DCBATOUT, 18.3V, t!OI!fl11-2 Fif/Fe
'A1l~~)(IUced
the small current common point DCBATOUT through U2 body diode, 18.3 V,is
In figure 11-2.
~"ID~'
D15
h.J1I'Y'~-t-_>>> t
I
1~14P1I
-
A1R1JE_VOll
NEAR
I
2SI
llDool"tV. e1i.ohlo
cbarg.r rutlction
Adaptor In Soft-Start Circuit
-_1O_1lVS
Layout T<:1C8 250mil
llCIlATOUT
2
R3
DD1R251:lF-4-GP
the production ofthe small current common point
Jt~IMltll'"
1m1lJ 11-3 JiJT7Fo
es' Cut off,the battery is isolated,is shown in figure 11-3.
BT+
AD+
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RI94
I
ORlM02·PAD
R217
3lI3ICR3F-GP
C346
SCIU26V
-IGP
l-_......!!!!MAX8~73!..!..I
-",OC"",'N,---""""""'-l DCIN
+---_t------,~---~'Ir_--~MAX873~.:!.!I..!lA~CIN~__...L..j
AC-.
3VIC>---k=-~~l---<~_.!!!!MAX8~73!..!..1~VD!!!.D_....ll....l VDD
R216
o&llKlIR2f.l-GP
-::r
C351
5CD1U25V3KX
-GP
'7
--"'ACIi"""V....I N"'--_---'''-! ACOK
CHG_AGND
:>ll.:W KAC llC'J n
00 11-4
Figure 11-4
(( ' ) ' ) - - - - - - l 1 L . l ..,.,
DClN ~ AClN rJ!~~OO
the screenshot ofDClN and ACIN circuit
3 OCIN ff rgj§, U44 M. LOO .lJiilJ4tu I±l 5.4V a9 MAX8731_LOO, :tzll!l 11-5 fJT7J'
0
When OCTN is power on,U44 outputs 5.4V MAX873l_LOO from LOO pin,is shown in figure
11-5.
!I 11-6 Jg MAX8731 a9 DeIN ~ LDO a9:ft~P3W:f:l!!Io
About the figure ll-6,is the relationship between DeIN and LOO of MAX8731 internal block
diagram.
. - - _......-=lDO
01.0
cssp 1--2II----l
0011-5
Figure J 1-5
LDO output
Figure 11-6
the internal principle diagram ofLOO
MAX8731 8<]~Ii¥M9='m DCIN a<J
f'Jtj(1itE 8~26V, ?zffi~}E-m: 7.4V
<*
In the data manual ofMAX8731,the
DCJN effective value,is shown in fi~
lockout value is 7.4V(typical value).
SUPPLY AND LINEAR REGULATOR
DCIN, Input Voltage Range
DCIN Undervollage-Lockout
Tllp POint
Figure 11-7
-240-
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manualofMI\X8731
8731 LDO t£i1 R204 -1:1 vee JJ!;IJ fJ.t rh, ~n Ifl 11-8 rfT:iF.
M~J\.O
7 I LOO supplies the power to vee ptn
. t I1rough R204,ls. shown .111 figure 11-8.
RlO<l
33R2J·2-GP
r
C358
SC1Ul0V3KX·3GP
IG_AGND
U4
SI4llUOBDY·T1
SC1Ul0V3KX·3GP
l
-===-
Figure 11-8 the circuit screenshot of LOO supply power to vee
, MAX8731 P3tl1Ijb=~ 4.096V ~~f1EItJ.I REF, ~DOO J ]-9 ffl5F •
• ])0 er on,4.096V reference voltage REF produced by the MAX873I intel11al,is
1- .
~1.1J!J.(1l.x:
AC Detect Output This open-drain output is high impedance when
~RiEF,I2. The ACOK output remains low when the MAX8731 is powered down.
istorii'om VCC to ACOK.
-pin defitfition:: AC Detect Output. This open-drain output is high
's
REF/2. The ACOK output remains low when the MAX873]
a 9
up resistor from VCC to ACOK.
~tt, ~ ACIN
*=f
REF/2 (2.048V) 111, ACOK 7fZ\TI~ru
Jialf of REF in the internal,when ACIN is greater than
is shown in figure 11-10.
ACII~
---,
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12.
1114
0R0402
I
C346
setU
-IGP
L-_....!!MAXlI~73:!l1 ~DC~IN!-.....zLj DC...
~_ _~ ~_ _~ ~_ _~MAXlI~731WAClN!!<!!!.._-'1N;Ill
3VlO--lr.~~--\--t-_....!!MAXlI~73ll1..l!!VDO~~1..j
VDO
C351
-;rSCOl
lJ25V3KX.GP
~
~:w
Figure I I-I I
_~=V~IN _ _...Jo>..-tACOK
CHG~ND
or. 1=;("'JO ( ( "'>"'>
-=-1..,.,
the screenshot of ACOK output ACAV_IN
ACAV_TN E8 MAX8731_LDO 7tEfiJg 3.3V ~~4Z, -~~ Q3 1'=:±'11£~~1¥J AD_IN#~
EC (1i=Jg EC B~~nc.B~:@jf!dffi%), 1mOO 11-13 JiJT5F.
ACAV_IN is divided into the voltage by MAX873I_LDO to be 3.3V high level by
MAX8731_LDO,through Q3 to produce the low level of AD_IN# to EC(as the adapter test signal of
EC),is shown in figure 11-13.
J1-JE1H~$IJ U3 B~ 3-4 JJp~iOi, 1E RI83 1t:tt!!.. 1}~mtl¥JiHt'i?:~ii RI82 ~ RI83 mJ£
7t)J~,
1'=::1:. 6V 1L;t]((']~ffi*~ U2 ~ 4 Jjip (0 ~), U2 ~ S ~Jg 18.3V, 0 ~Jg 6.IV, U2
~ii~J~:i:n7f, AD+ 1I1tmt~0~t.i:, ~:±.*Jt!rm:~0~t.i:, 1mOO 11-14 JiJilJ'.
The other path controls 3-4 pin conducted of U3.makes RI83 grounded.The small current
common point through Rl82 and RI83 to fo
~ure,and produces about 6V voltage to
send to 4 pin (0 pole) of U2,the S pole 0
6: JX)le is 6.lV,U2 channel is fully
opened,AD+ directly flows to the commo
e erge curteot common point,is
shown in figure 11-14.
Figure 11-12
Figure 11-13
-242-
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layoutTrae:e 250mll u,
,
R3
OOt1Q512f'.4.GP
RIM
-...0>
C1AlE.
'the screenshot of the large current common point production circuit
QlJ HBU16-1.2 ~~fJl~R%7tt-JT
YIJ~ 11-15
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VI-Ill
VI-Ill
R483
END
ENTRlP2
ENTRIPI
51125 ENTRIPI
VREF
575
51125 TONSEL
51125 SKIPSEL
TONSEL
SKIPSEL
on
~
CI
~
~
W
W
TPS51125RGER·GP
VI.
GAP-ClOSE-PWR
R
~
-------~C5T7
-------
(, ~~~I~:v~I--: :- +
:r_~~s:x~ ~ )
.,
C578
.....
0630 -1
00 11-16
TPS51125 l1!i&8111
Figure 11-16 the screenshot ofTPS 51125 circuit
+3VL KBC
Q
' -; - - - -,-,
R56S
O~PAO -
LIMIT SiGNAl n
+3VL
9
/
0701.1
1 .... A.~t....-------.....-~~
-244-
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power supply.to supply Ihl: voila 'c to X2.Cf) sIal 0 cillator slan.and send to
2.7 8kHz.i. shown in figurc 11-19.
32.768Khz 12.5pf 10ppm
1a~: 82.30001.691 (KeS)
2D4: 82.30001.861 (EPSON)
1-19
Ee standby clock
Be ttCJ~.fft, ~OO 11-20 rfr/ft.
standby reset of EC.is shown in figure 11-20.
Scanned by CamS canner
Jl
~ I : 8PI:--;sac
_"- ~B~::::::mjU§~ii3iIE~~i:~::;"SCl('
~gl::G iii i~. iii ~[-
FI:tJ
WPCE773l.AllDCJ.
EC n~ SPI.~,~xi3l)Jtp
III 11-21
Figure 11-21
SPI bus pin of EC
.:JIIl KDC
.M_ICBC
0120
~
.
1~
....
.... COl
COl
I
>
.
DO
~
~N
....
8PlWPl2C
...
\ICC
.2
:..-
"""
I•
HOUlI
~= ~
":;:"
~
"'r.?'"'
... WPG
R>I>
a .....soo
21 II'l.IlQ(
<0
«»
t1Ot2J.1"
W:z5X18YI8Q.GP
......",
r
2M Flash ROIl
l.t: 72 .25Xl6.AOl
2nd: 72 . 25165.AOl
",,1lQ(
~~
00 11-22 U25 rt!i'6~OO
Figure 11-22 the screenshot ofU25 circuit
EC .iE1t*]lH~Ff)§, fta.wEi ~.8I~HJLo ~r* EC iJUjlj~1j 93 ~B"JmI!iCB:talA.f&mH~.f}
AD_TN#, ~DOO 11-23 Jiff/Fo
After EC reading the program normally,contigured their own pin.Then,EC identifies the
adapter insert test signal AD_IN# of 93 pin,is
gure 11-23.
EC f&~m~f~~-'fZB"J~ljmnGHA.m7J'-m
JiJT/F
1:l1~~3JZB"J PWR_85_EN, ~[JOO II-24
0
EC detects that the low level of the
automatically the high level ofPWR_S5_EN;
Figure 11-23
the adapter test signal ofEe
Figure 11-24
E sends PWR_S5_EN
an indication signal,then sends
PWR 85 EN ~$Ij Q42 ~1I,
~D 51 I 25_ENTRlP2 ¥i1flIH:t&,
PWR 85 EN controls Q42 co
25.51 I25_ENTRIPI and 51125_
R498 and RS08.
-246-
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.3VL
RSU
100KR3J·L·GP
51125 ENTRIP
51125 ENTRIP1
CG08
Cl>
Y
R508
..,£
1GOKR2F-GP
'"~
~
z
.:.
..,
Q
'1
51125 ENTRIP
041
51125 ENTRIP2
ClIIII
CD
I,
Y
R498
160KR2F·GP
-
PWR_SS_EN ~$lJflCJEl!.iU\H~
t oCtile circuit controlled by PWR_55_EN
figure 11,+SVALW.
Scanned by CamScanner
~
U30
z
:>
51125 VBST2
ORII603-PAD
51125DRVH2
Q
'1
1n
51125 u.2
H
., 51125 DRV1.2
ORII603-PAD
I?
V8ST1
DRVH2
DRVHl
Ul
u.2
DRVll
DRIIl2
., V02
51125 V02
51125 VF82
VOl
" VFB2
3
51125 ENO
2IlKR2F-GP
51125 ENTRIP2
VllST2
1~
R
~
51125 TONSEL
..
51125 SKlPSEL
1..
VFBl
ENO
PGOOD
ENlRP2
ENlRPl
GND
VREF
lONSEL
GND
SKPSEL
VCU<
.,.,
51125 VBST1
,
R471
."
51125 DRVI·t1
?n
51125 LLI
1Q
51125 DRVLl
,
R4n
.,.
51125 VOl
'1
51125 VFBI
.,..
,
51125 ENTRIPI
1"
?J;
~
l!J
TPS51125RGER-GP
00 11-26
i ~
..l
.J
TPS51125 (fj 1 Jj!plO 6 JJt4J-I\! III
Figure 11-26 the screenshot of 1 pin and 6 pin ofTPS51125
Design Current-6A
OCP design>8A
G46
GAP-Cl
_R
G50
GAP-Cl
_R
G49
SV_PWR
GAP-Cl
_R
G51
GAP-Cl
_R
0fN1UI
G46
QAP.Q.~R
GAP-ClOSE_R
G113
QAP.Q.
R
00 11-27
Figure 11-27
+3VALW fn+5VALW ?t§jlJiJt~j1jmtf(J
ffi, ~IJ ~ 11-28, ~ 11-29 PJT7.l'.
+3VALW and +5VALW supply resPecl
bridge.as the South bridge standby vol~e is
-248-
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+3VALW
-Clsa - --I
SCD1U10V21O\-4GP
Figure 11-28
3.3V standby voltage of the South bridge
lmA
OJO
CH751H~PT
I
R427
10R2J-2-GP
VSREF S5
I
I
C551
~SCD1U1OV2KX"GP
U60F
4".,
1~29
VCCRTC
VllREF so
All
VllREF 86
41'1
VSREF
5B
VSREF_SUS
SV standby voltage of the South bridge
, iIllllu-30]Jfff;;.
,is shown in figure 11-30.
==~---~ GPI044ITDI
~'------::-1 GPlO45/E PWM
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RSMRSTII 0 ' - " " ' - - - - - - < < <RSMRSTILSB 32
>>>CK_PWRGD 16
CK_PNRGD
58
M PNR
/ / / M PNROK 7 12
Figure 11-32 RSMRST#_SB is sent to the South bridge
-250-
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, ~'UdIHt e,:r,t.>Z 1~~n,1i ~ ;fo~HJLtt3~. J:. ttutJf.;fo RTC tt3&-~£.$­
~~fi~~~.~~~tt~.~k~._~~~~#~tt~.
EM laptop circuit
ofthe motherboard designed by Compal is the protective isolation and the
wer-on sequence and the RTC circuit is almost the standard sequence.This
kinds of Compal protective isolation circuiLThen explain one of the
P protective isolation and the standby circuit
1fI• .f;I1*m Et!~.
as an example to analyze the protective isolation and
PL24 mtz:1:. VIN. 19V,
!ZIJOO 12-1 Jifr5f-.
il and produces VIN, 19V through PL24.is
er interface is shown in 12-2.
VIN
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Figure 12-2
~ PD2
Com pal motherboard po\\er interface
PR304 fll PR305 afJ*lf*$t"~ VS, ~~ PQ42f*=f&1ft'::l::
1, ~ PRJ06
TCP. pj.~j1 PR309 tz:~ N2 ~~1li:im PUI4 ~Et!., PUI4 $J4J:±l 3.3V f8
1112-3 fiffiF.
VS through the parallel connection of PD2.PR304 and PR305.and produces j Ij
diode changes to be CHGRTCP through PR306.then through PR309 to produce
to the pressure regulator.PUl4 outputs 3.3V RTCVREF,is shown in figure
VIN
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f'1 VIN It!JU ]-17.24V (~IU~ilir;~
IN/(I'R l)7IPR,OI)· PR1(J1 I'I:J~i,~"J,V- f 3.3V). It~{,H;JfiW
PI I till)" II 1" :1 It! '1'1'1:) PI\ IN .flll\ IN. ~lIr~112-4 f1j/J
(II
h 1
IIJi 111
I 1·:1·
1
)
I'I(VRU, L~h.
,n 'I' thl' ugh PI 297 and PIUO I diving into the voltage,if the
r th \l\ 17._,IV(llluk' n rough calculation after ignoring the hysteresis
IN/ (PI - q7 I PI 0 I) '" PRJO I i higher than 3.3 V),lhe comparator will
into th ' vnlt" 'e by VIN and through PD I steady pressure to produce the
IN.is shown in Ii ure 12-4.
VIN
vs
L.--L.A./V'-"------O
RTCVREF
17.525V, L7Ha~ 17.90IV. t!nl~ 12-5 ffriji: •
. g edge of the VrN voltage threshold value is
-5.
• Bt~l:I!~ B+. ~IJ 00 12-6 Jfriji: (PO 14
0
_it.:
-f*iiTif I~
...----vi-n-o.-",,-.o-to-.----,
1CiD.
8-->L 16."6V
L->B 1'7.430V
Typ
.......
11.52SV
11.728V
1"7.901V
18.3B4V
+)X
00 12-5
YIN ~1!El!lli~~
fI conduction,power supply in
f lmA the voltage is about
t the data manual of
l'Mlllan calculation:if
1357.).... !the
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8+
power supply in advancc B+ production circuit
1! PQ69 ~jjft, 1N~ PR395 fO PR394 ft-II*. ~H~
~*Ir*Et!J.Ii?tffi, ~O~ 12-7 J5JT7F. ~ B+J:l:!.ll~-f
~*T 3.3V, ~t$X~Hfim~tfJ, El3 VL U1LT:J~E\!
J:I!~,
~ ~tEM=mEt!.~9J?ttJT).
evel,rnakes PQ69 conducted,and makes PR395 and
istance is 138k..., after parallel cOImection.B.l.
lei resistance,is shown in figure 12-7.lfthe
istance PR385),the voltage will higher
drain outputs,and is pulled up to be a
by chip,we will analyze it in the
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YL
.....
2.2M_ ...
B+
vs
,..",
RTCVREF C>-----..::MK..'-vv''''''v-'-''-''_--4
PACIN 44.47
JlT--f-2-----o +5VAJ...W
the screenshot ofthe ignition loop circuit
1.35k",1!'t, ;l!tJtJ.li{i~UiL1E.t~ 15.2Y lJ,"f, ~£i1 Jt~£J.:5tff f~
Eli 3.3V. ~~. 7 JJt1J~I'±HE.tJtf, T~ AeON, MAINPWON
&PqR.\~IIDi&.
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MAINPWON Y.:J If (lJdliQ:; (i~J''iG ~l)tHt;r~ }.''X l' G~~' ';'6iJ)D.
When PACIN i high,+5VALW is produced.PQ7! is conducled,PQ69 is cut on:PR394 i nOt
I
grounded.as long a Bf is nol Ie than 6.6V.then it can make the comparator open drain olltputthc
bigh level.ACON and MAINPWON are not pulled Jow(the adapter mode.the ignition has been
completed).
00 12-8 JifT5F~JJILI:jgi~~rQ.llll.)§, B+D~~~~U~~11i, lfrj11jCX~+!'ht~ 14.8~ 15.9V, 'l!.YIM~h\
6.2-7.3V (~IlY. r:p fAJ 010
As the figure 12-8 shown,after adding the hysteresis resistance,the detection threshold value of
+ the adapter mode is 14.8V-I S.9V.the battery mode is 6.2V-7 .3V(select the intermediate value).
igure 12-8 the text screenshot of B+ threshold value voltage settings in the adapter and battery
D
ode
i=3[.m~, ~o ~~f¥H= l£f\itl MIt11k It llill1T ,j3Z IE ~iJ~ *,IJ 7f 18 ~ 1lkJJX It D~ 'tr.fi5L EC - f.R1:l:l1a;~-V-i¥J ACOFF, PQ6S ~~l!:, PACIN 7-J~, ACON IGfffi:b~~:M1iL11£, PQ63 gMft~
lfLtro G ~~IL PQ63 ~jffi, :tzoOO 12-9 JlJT5FD
About Compal machine,for example.non program controls the correction of the banery
and forces to open the battery discharge,EC always outputs the low level of ACOFF,PQ65
is high ACON is not pulled low by the comparator.PQ63 obtains the G pole
~el PQ63 is conductedJs shown in figure 12-9.
3
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Ugh the body diode of PQ51.through PR354 and PR361 then through
.toms partial pressure,produces about 8Y voltage to add to the G pole of
oonducted completely,YIN flows to B+.the common point of the large
in figure 12-10.
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[f,Ju1 PQ59 illn&.ll:. PQ58 n~ B il'2HJJl YIN tLi$. PQ58 ~illL PQ56 [5]fFill%J.ill, P2 ~£j:t
PQ56 (j~ E f&¥ilElnJ C fiL J§j~)JO~1j PQ51, PQ52 8~ G f&· f~Z. QJ1t~:jl~.lL
At the same lime.PQ59 is cut off,the B pole of PQ58 is pulled up by YIN,PQ58 is
conducted.PQ56 is also conducted,P2 flows to the C pole through the E pole of PQ56.then added to
the G pole of PQ51.PQ52.and make it cut off.
~¥I!!.~
m;ffl1i)[ ~ r:f!.lMHIO 00 12-11 J5JT7J':
0
The circuit of the battery isolation and discharge is shown in figure 12- I I.
00 12-11 toP, 3 PACIN f:J1Ji. PQ61 ~jffi, HLfE,l;; PDI2 B~iE;fl1, PDI2 t\\l.\:; ACOFF 1J:!.
~fE,l;;, P09 ~ll:; =fl1~ PQ57 B~ B :f)H~§*El:!.~.ElrtLf:JfE,l;;~-¥. PQ57 ~.t.l:. YIN ~Ht
PR352 -.till PQ53 ~ G f,bZ. PQ53 ~ll:, Et!1lJ!.~~~
In the figure 12-1 I,when PACIN is high,PQ61 is conducted,pulls low the positive pole of
0
POI2,POI2 is cut off;ACOFF is also low.PD9 is cut off;the B pole of the triode PQ57 is pulled
down to be the low level by its own resistance,PQ57 is cut off.YIN through PR352 to pull up the G
pole ofPQ53,PQ53 is cut off,the battery is isolated.
CD tlO:W-: YIN ~Et!, PQ53 B~ G f&~ PR352 rillt~±l!!., PQ53 ~~,
~1lliJ1)(~o
If YIN is no power,the G pole of PQ53 will pulled down to the grounded by PR352,PQ53 is
the batter discharge.
YIN lfEl!, ff!. PACIN ~f~Et!-¥, PQ61 tlGll:, POl2 iE:fl1:tl!i PR357 LtL~~,
Q57 -tB~ii!i, YIN ~i1 PR352 fO PR356 *ffi~~ PQ53 B~ G :f&, PQ53 ~iffi,
~
on,but PACIN is low Ievel,PQ61 is cut off,the positive of PO 12 is pulled up to
12 is conducted,PQ57 is also conducted,YIN through PR352 and PR356
to the G pole ofPQ53,PQ53 is conducted,the battery discharge.
iiuh::::t------~B~An+
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Figurc 12·11
the batlcry i 'olation circuit
-fACIN lliJg,*Ji{J.:ljZ, 1§ ACOFF tt!.7~1';;h (~FF~Hiu~..rElJ.it!!.5nlf~ufj)cl~
~~J!~-B:illi.
YIN t£u PR352 ;fIl PR356 7}ff~g- PQ53 R~ G :l'Jk,
ClN is high level.but ACOFF is also high(when the program control
battery),PD9 is conducted,PQ57 will also be conducted.YIN through
• to the voltage to the G pole of PQ53.PQ53 is conducted.the battery
dian of VA(the adapter mode and the battery mode)
S shown in figure 12-12,look at the following analysis.
VIN
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510 #li~JHIj 012 lil Q32, 3 11(-r 7f~,Fp, ON/OFFBTN# 7~1lt. ii!H1: 012 111'ft
o # M.ffij~j: VS. ~!J 00 12-13 JiffiJ;.
-.
SION# connects toOl2 and Q32.after pressing the switch.O /OFFBTN- is low.through DI2
pull 510N# low.then produces VS is shown in figure 12-13.
M2t7f*ff.J[iiJB1iI~~j: ON/OFF ~ EC, EC 1!}tztJj~rt-'ffI9 EC_O *~jlli 032. ~
510N#73{l\; It!. 4!
At the same time of triggering the switch.it will produce 0 IOFF to send to EC.then EC sends
0
'-
high level of EC_0 to conduct Q32.and keep 510 # to be low level.
(t3Lff.J1HJlfttE~.9::ff~~1liJ~rnc~~~~-r7:J 17V 1iti, It!.it!!.m~r7:J 10V 1iti < )
(before triggered the boot pin of Compal.the voltage is about 17V in the adapter mode.and the
~e is about IOV in the battery mode.)
.:I'IALW
_ _ <=1----,
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VL
0012-14
B+~~ PUI6 ~~
Figure 12-14 B+ supplies power to PU 16
jRjttT~Jii, .fI}Jtlli~ EN_LDO, ~llm 12-15 Jifr5F evs .R!J1i@ir
2.4V, .jij.1tlliJiif=1::(fj EN_LDO nr~*T 4 }jl;lJlr~1fi 1.6V)0
diode PD7 to reverse breakdown.then divided into pressure to
9.'18 as VS is higher than 7.5V,it will higher than 2.4V after reverse
dividing into pressure can be more than the threshold value
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~ 12-16
Figure 12-16
PU16 !fu"'trtl:l LOO *D VREF2
PUI6 outputs LOO and VREF2
RT8206 I¥J EN], 2VREF_lSL6237 }[:J3g1JlliV EN20 f~* RT8206 B~i]lm
tt13jtf=~+5VALW JE7f~Ef=~+3VALW,
t11J~ 12-17 J5f-r3Fo
EN] ofRT8206,2VREFJSL6237 is added to EN2.According to the pin
REF,sets that produce +5VALW first then to produce +3VALW.is
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is not pulled low by ignition circuit and also not pulled 10\\ by
H~~.....,l is high level.RT8206 opens PWM I first to control produce
being stable,then RT8206 opens PWM2 to produce +3VALWP(32 pin
ed,two path of PWM are set respectively fixed output 5V and 3.3V),is
the other path is connected to 3 A
control circuitwhen the
C).When reach a certain
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VI.
VI.
L-+~--------f------1~------------L-=>
MAINPWON
PU30 temperature chip circuit
~ renamed to be +3VALW through the isolation point,+5VALWP
isolation point,is shown in figure 12-20.
t-'-----<l +3VIILW
two voltages renamed
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~~IfiIli • .Q JS r:~+3V ~fJHJif~H~11LIf!IT (U14 *:iQ(J(J@~jf-lIt UI-l *;c
III U-22 Jifrij;.
1eCli;·"".3V through the isolation point J5 to supply the standby voltage( @ next to
not installed.JS is short connected) to the bridge,is shown in figure J 2-22.
VALW TO +3V(PCH AUX Power)
Short J5 for PCH VCCSUS3.3
~v
40mil
C393
C392
'--_-----, 10u_t_l0~':tO!10V4Z
.~ 12-22
+3V production circuit
~~jj:(J(J VSREF_SUS, ~IJI!l 12-23 jiJfij;.
169 to supply to V5REF_SUS of the bridge.is shown in
liS
*8_ tl:l SPOK, ~D 00 12-24 p!fiF.
SVALWP nonnally,open drain outputs SPOK.is
POK
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1'0"
TP06,oK.Tl-EJ SOT23-3
B+
....,....-1.....-,;;-3-+-ri~-r-I----<>+VSB
o---
S
lQ,
p
~§,
..
~
VL
111l111•.IN02..1%
00 12-25
Figure 12-25
+VSBP f'~
the production of +VSBP
~mlt!.ffiiE~J§, ,,~~Jb1m XI il9~, ~IlOO 12-26 JiJTlFo
by voltage of EC being normal,the external crystal starts oscillator,is shown in
00000
zzzzz
(!JelCH'el
o
z
~
KB926OFD3
20mil
..
~~~~~~PCIRST'IGPIOO5
ECRST.
SClI/GPIOOE
CU<RUNIIIGPIO' 0
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EC -L<J;!1X BIO n~c;lJJtjJ
00 12-28
Figure 12-28
EC reads the pin of BIOS
150mils
lJ:)I
EC SPICSlIFSELf
SPI wp,
I H
•
,0•.
RMerYed lor BIOS 01......
Foolprinl508
12-29 the screenshot ofthe place where U31 is
circuit,then EC will wait users to trigger the switch.and
w we don't detail.
pllotective isolation circuit
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PreCHG
PR16
1K t208 5"'TP081OK-T1·a SOTZ3-3
YIN
PRn
1K_12'08 5%
PA7Il
'tL1206_5%
PQ27
-
P07
B+
lL4148_ll34-2
..~
PAlll
'-<-'206_5%
00 12-30 1y!f:tteg B+
Figure 12-30
the power supply in advance B+
J:tr. ACOFF ~ffk. lIta1+5VALWP ill*f'=:±.. PD9 7Crtd~ PQ28 ~
it PR83 f.D PR86 7tffiJf~I1.M~X1ffki:E!.3f. +i:E!.:/frEB~ B+f'=:±.. i:Hj
ACOFF ~7fJj. £iJ(.1!f+5VALWP .lE~F:±'J§,
lIti:E!.~~:W~*I~o
wer supply,ACOFF is low,and +5VALW is not produced,PD9 can
30 will be conducted,to make PR83 and PR86 partial pressure to
I current B+ is produced. When the program control the battery
'gh,or after +5VALW producing normally,this circuit will be
~ PRECHG ~ ~~ *ltl'il f~ , I15l LL4148 ~1:t1}i ff ffl.
U148 ffi~ IV). PRECHG t}rl7tffi, ~i~ PU4
tpflttIlJl:~rrF :
~then PRECHG will also be pulled low,because of
CHG will be higher than B+ I V(after
through partial pressure.is sent to ACSET
as follows:
to a resistor divider from the AC
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1:1:1 PRECHG
~8gil1-t- 18.09V El:!-t- B+iJ?: PRECHG ~5:tt PD7 rz;j:.rfj .
0
•09Y. ~DOO 12-31 JiJT7Fo
open drain output pin,when ACSET is higher than 1.26V,ACPRN is
than 1.26V.ACPRN is pulled up.that is to say.the threshold value of
ation of partial pressure [1.26/PR47* (PR43+PR47)],it can conclude
than 18.09Y.Since B+ is produced by PRECHG through PD7,so the
ited to be 17.09V is shown in figure 12-31.
YIN
ACSET Jmtt 1.26V, ACPRN ~~ t±:J 111 ft!.."Sf,
PR74 7fffif~iU~It."Sf, ~a1 ACIN ~ft!.
CHG is nonnal,ACSET is higher than
off,fACIN obtains the high level through
el of ACIN is sent to EC,is shown in
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IClJrt!.fB~ PACIN ~i1 PR63 i~ PQ20B ~iill .. VIN ~~rl PQI2 i*=tJl~1""1:.n~ P2 ~iJ:
PR4I tl1 PR50 7t1li~ 8Y ft~:i, PQI2, PQI3 ~:iUl. YIN ~rli¥:!'PIWj;%F~*~¥iii B+, tm
~ 12-33 JifT~o
The high level of PACIN through PR63 to make PQ20B conducted.YIN produces P2 through
PQI2 body diode then through PR41 and PR50 partial pressure to be about 8Y.PQI2.PQI3 is
conducted,YIN crosses the protective isolation to produce the large current B+.is shown in figure
12-33.
P013
~7JU;08
P3
PR41
200IUMO:U
)i,
i!L1f£ PQ20 B~ G
'if. B f& Jt!.Il>J
~~ft;1i: ffi '
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s __
",,~co
••_Dducted.and conducts P2 to the G pole of PQ 12 and PQ 13 directly,two P
closed.YIN and B+ are isolated.
4
m/J". t= ACPRN Jgf~ Jt f)§, PQ 10 1itl1:, VS ~£i1 PR36 1!E PQ9 B:
, PQ8 mtlt. ENTRIPI 111 ENTRIP2 /F~!l!!. (1£:
vs H~-tE~j1JG~t~
~m~l'~!lH!k:&7f*J§;1-~tz:j::, i8:1'~ LA-S891 P ~1:lflK£U. If
, MAINPWON Jgf~, -1£%~.Ll: PQ9)0
MIl in figure 12-34,when ACPRN is low level,PQlO is cut off,YS makes PQ9
6 pulls the G pole of PQ8 low,PQ8 is cut off,ENTRlP I and ENTRIP2 are not
uced directly just in the adapter mode,and it needs to trigger the switch in
it will be produced,there is no difference with LA-S891 P,not to explain.lf it
,MAlNPWON is low,it will also cut off PQ9) 0
1 *0 ENTRlP2 1i1fl~H:fH~Jl!!., rm~illiJ1Eg~J3. PR27, PR28 1t!l!!.,
PI
-:r5YALWo
of RT820S are not grounded directlY,but through the resistance
't can produce +3VALW,+5VALW successfully.
~5( T ENTRIP JJt4J8911=ffl~1~~~,fo*lk~~Egyj[iiJE, ~lJ:tJjljJjl±l!!.
JtmN~:tI!!.H111=~flk~~Egmt:i&JEo ~J:tP-J$)A YREGS ':71
JJ.Jt1ml' •
1 and Current Limit setting Input. Connect resistor to GND
ous RDS(ON) sense. The GND-PHASEI current-limit
lover a O.5Y to 2V range. There is an internal J O~A
e logic current limit threshold is default to 200mY
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Figure 12-3-1
the enable signal and the control circuit of the standby voltage
• .3
Analysis of Compal LA-6751P protective isolation circuit
8;t~~reft1IDA. ~~tI:l VIN, ~DI!I 12-35 JiJT1Fo
First,insert the adapter,output VIN.is shown in figure 12-35.
VIN
DC0300D6JOO
'"
~
;;l
5,
00 12-35
Figure 12-35
'~"
-8
~~
-gi,
-~ Jl~'
-~
~~
~,
f-
f.
~I
~:'
VIN (j~1"~
the production orVIN
~Et!.~, ~ZD 00 12-36 Jiff/F
0
VIN Nrl PQ30 I f*=f&~F1
02 Jr-J~j!llr~ G t&~;f§)(11~J:E!.~o tBJlJt~i5?" l1tJtl,J~H~'~
~Jr-J ACOFF (BATT OUT ~LJ:E!.j§:t~!&JEj:J,f, JJUJ::f
h the common point B+,is shown in figure 12-36.VIN
little more than 18V,the conduction of PQ30 I and
tively.That is to say,there must have the high
AIT_OUT is high level after powering on.is
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B+
P2
65"':0.020
!IOW:O.OIS
CSIl.l
essp
8251 VOO
PR310
<~;J> FSTCHGC:>!F:!<S:!ll°~"''f-'"':(.."'' --4
PR]13
10K Oo&Cll%
C[US
~ I800P_0402_23V7'1(
pc,.
PR:111
IOK_l).I.Q1_I""
~i-"""'-""""'P:-VV--'---~~....Lj
D.01U_CWO'.J5V7K
......
NJP_I <:=J-
--'"
......
, ICM
R323
~OCU)Crz-' ..
0-",------"IlllM
-
5'" V
Z..21UMO:Cl
common point production
rBllfftro ACPRN ~A, PQ316 ;1-~
¢)~~ PR338 ~ PR342 7t [n~
,~·,........low level of ACPRN
eat voltage 5.075V)
dproduce
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6251 VDD
ACIN
PACIN
PR342
ACPRN
r-->-------"-\-w,'i\...
P0316
I~ 12-37
PACIN ~D ACTN Bgf"~
Figure 12-37 the production of PACrN and ACIN
ACOFF ~EI:J EC ~tU ~11~~-'f, P-fH£*m*~ff:~iM r:E!.¥tl!.5ffi.*IJJJ~~Bt, EC ;t~J.itili~
tf<J ACOFF.
GOFF is the low level sent by EC,only when the system program controls the battery forced
C will send the high level ofACOFF.
*jif ISL6251 8123 HtIJ, ~1J1!l12-38 JiJT7J'. llHM lSL625I rilJM=fn}}1~~Q, ~
V nt. ACPRN ~~~$jutl:\1kX;r:E!.-'fo ACSET *1mff YIN f.£tt PRJ06 f!l
pin of ISL625,is shown in figure 12-38.According to the data manual
• is higher than 1.26Y,ACPRN will output the low level.ACSET comes
PR306 and PQ312 partial pressure to obtain.
VIN
PreCHG
~
;;;,
!,
.. •'"CD
ACSEllN
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lanned to Use the mat . . ' .
• n
•
.
LIIe 19n1lton loop,but is not used in this machine((@
ot mstalIed),ls shown in figure 12-40.
Vl
vs
...
o
~
0=
"-.
}fflJ', VMB2 ~ft!.¥tJ!~rJ1j~~Jjl;p, 625 IVREF ~*§T
21t1.J.i11£T 9.08V J§, ~jj PR212 to PR215 7tlli
afi 2.39V, 7 JJt4J~iHtl11£ El! 3f, PQ20 I ~lJ:
0
12-42 VMB2 is the battery interface power
e 2.39 output of ISL6251. When the voltage of
15 partial pressure to send to 5 pin of the
6 pin,7 pin outputs the low level.PQ20 1 is
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Figure 12-41
BAn'_OUT control circuit
[i:iJ"tj£Mf~ EC Ltl±lnq1[Lt3f BATT_ LEN#, PQ205 :;ti;;~.1l:, +3VS ~Ji PR211 1+'1!L
BATT_OUT ~~rt!.3fo {g+3VS ~~m SO ;jfC01~1t, JijfL;l.Jl-tf§ Ij- .R~I:E7ffJL~i0T:tnr~
~*IH~HFIWi~, ::ftEJ!1R7HJT 7.
At the same time,it needs the low level of BATT_LEN# sent by EC,then PQ205 will be Cut
off.+3VS through PR211 to pull up BATT_OUT to be the high level.But +3V is the power SUpply in
the state of the system SO,so this signal can control the protective isolation only in the boot state,not
to analyze at here.
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~4~o -*--tl-J- DosXX Dunkel 1.0 (HP_6510b) 7g1J1JiJ}J1j!f-~.:tr.it6f;
fli5'i.il!L.l.*-~ Jt &.ft. 7(.1+;;t n\, EC 1ft:Y *-l:1 tt,ffi J:t ili'l. it ~t T ~ S] tt;i'~
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® VADP ~}ii R108, RI05 Ej RI04 :5HIi/ix 4.8V j!~ 5 Jj!jJ, {L\; f 6 ))'I4JB~ 7V, !tta"'tU
W~ft!.If ADP_EN#.
VADP through RI08.R I05 and R I04 partial pressure to be 4.8V to send to 5 pin.i less than 7V
of6 pin.the comparator outputs the 10\ level ADP_EN#.
® fa; ~ :;P: (8 ADP_EN# f~ Q7 ~.Ll:, ADP_EN 7~ tJj, ~ ~~ EC, 1EI11t n171:: jill eg ,
LP_S3#_3R ~fa;, Q545 ~.Ll:, BATCAL#d:IJ.!§:£:/t~[~lli~} R9252 J:.tLf~J?~,tJFI:!/rL.
The low level of ADP_EN# makes Q7 cut off,ADP_EN is high,sends to EC.because it's no
power at this time.SLP_S3_3R is low,Q545 is cut off,BATCAL# is pulled up to get the high level by
e adapter voltage through R9252.
~JIt. Q507 liID1~IJ~im, f'~+ADPBL.
Then,Q507 is conducted successfullY,and produces +ADPBL.
13-) 9='. Q514 ~iG:i:~W, rm!lH~~~ U5 (BQ24703) ~tJjB~f(l;;~:;P: ACDRV#, A
Q514 ti:jjjij+VADPBL ~ D, S ~z..fEi]B~1*=f~~& D510 fiH cg1m~i:~.~
IE 13-3 PJT7F.
13-1 ifQ514 is conducted completely.it needs the low level of ACDRV# sem by
ific process is that,+VADPBL in the left side ofQ514 through the body diode
and S pole and D510 supplies the small current to the common point
13-3.
Jii~~~+VBATP t:lt~*;fJ1.~~~I:ffi;~h TPS51120 B~ YfN i1=
~/'3~hB~ EN3, EN5 ~S::. t~1JiS TPS51120 B~iJIIlfIJI:EX,
VREG3 fll VREG5. VREG5 ~@!~ V5FILT titEg, f"1
after crossing the jumper wire PAD6.supplied to VIN ortlle
120 as the main power supply,is shown in figure 13in the air,according to the pin definition of
uce automatically VREG3 and YREG5.VREG5
e reference voltage with 2VREF.
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II :::
...
+VBATIl
&-~J.""'.1f...tJ..u-;r-
R111
150K_5%
+V3AL
RIll
•
10K 5%
·.l·.te-.n-......u-..;.:...,
1
IC38
%7UF_2SV
R82
100_'%
AC_AHO_CH
1~~ .z
•
u~
\/l
()
§
(l)
p..
~
z
~11
ALARM
ON_LM3930RZG_SOP_8P
\/l
~
( l)
""'!
..=.
R575 ~
lK ,,.~
-
1
_
-
RU1Ie
SSM3K7002F
[311
,
,
_.
....
r==
""".~
:::.
~
71 ACl'RD
__ ..••. _ . .lli
RIIo
I "~~
-,.
--I
,-
IRUT
11 AURM
247D3VREF
~
>:
r -:
021
...-..
- "
100K 5%
3
*t-
~.
1":-
ACSB.
n
S
~
R30
2[D.1UF_1 IV
1~~25V ----
o-----J
1K_5%
KeYlnNn..
R32
I ...
--j-,
r
..
~
t6
~
R8'
~,
~
~ 13-1
-0 J~ !,':it" 1: 4:!.~it
::::::;"\
,VADP
r
J'\1h~'t-.a2~1hI'l
.V3A
.VADP
CII
!lUF_:ZSV
OIIJ.1DI3D1l2G_80P_IP
Roll
IOK_1I%
RlGI
2ZAK_I"
U-
1
P_1l
....",."''''''... :p..M-H ......
2
t
,ua.
1._11%
1
Rl06
1.I11U"
~~
RU
41K..5llo
1 R!OI,
I._I"
RIO
22GK_1I%
P_E~
u7
-I"'.. . . . ~
------.....--.....--
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~
~-tt---H-H---;--Hi-'~~~
o
~
r----.--"'BI~
•
N
01')
C/l
c..
f-
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Figure 13-4
1'P 5112n circuit
(1lI1 lt1135 J,i/J··, IJ 1l!.¥~UI~·1 VBATR l,iJllJillrrt B024703 (I~ 22 )Jt~ VCC ff):J{jl:Eb" VADPBL
M rt!.1111 R27, R26, IU \ : 1\ l[H) Jl~ , JJII5i t~!iX ;f:* UI (1'J 5 IJtI!, ':ij 2VREF I Q.1I tU~. f\:
VADPBL IUHi,',:j r 10.87V, L~~x(,;* Ul (1107 IJtlI~:;Inrd~l!1j:Jjjilj:yq~*a.jillA.f.&~mH~ '% ADP]R.Es, UJ
+V3AL ~i R89 I::AJLPXr::jIU'Il.. ADP PRES ftjirum R9\ :iE~ BQ24703 iY-J ACDET 1Jl4], it'i-tJt
P9$1¥J I.246V 11l(](iL B024703 i;'~J;j~~:illf..IiC-6~jffiA~f(0, ~·6IjtL\1l£rt!.fO~ AC_DRV#, Q514 8~ ~
It ¥Urt!.~.Il R565 :frJ R575 'l}lliJRu<.J1\;Vl:!.3fJR~jrH,
j-i\:!.¥mU1i~~·t8+VBATR f'=::t (tt4X*~ifN\
llJi1J~tI:l1t:ruJFJF-lf~ 'J AC_AND_CHG, :i!~IJ B024703 U~ ENABLE, fF~1t:1:@.1~~M~ 5).
As shown in figure 13-5,the small current +VBATR is sent to 22 pin VCC of BQ24703 to be Ole
power supply,+VADPBL through the resistance R27,R26.R31 series partial pressure,and added to 5 pin
ofthe comparator Ul,to compare with the voltage of2VREF.lfthe voltage of +VADPBL is higherthan
lO.87V,the 7 pin of the comparator UI will open drain output and the adapter is inselied the detection
signal ADP]RES,is pulled up to be the high level by +V3AL through R89.ADP]RES through the
resistance R91 to send to ACDET pin of BQ24703,is higher than the intemal threshold value
.246V,BQ24703 is identified to be the state of the adapter inserted,and outputs the low level of
_DRV# the G pole of Q514 is conducted after getting the low level through the resistance R565 and
~Pf;Il~'aJ pressure,the large current common point +VBATR is produced(the comparator also outputs
signal AC_AND_CHG from 1 pin,sends to ENABLE of BQ24703.as the charging
...
-"-'"
,1UF
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DosXX Dunkel 1.0 l~fJLFl1K~7J\"~fi
• ofInventec DosXX DWlkel 1.0 standby circuit
Bt+VBATR {tt¥:~~tfLrg&~t-Jt TPS51120 (/j YrN JY.IJ, rD-f- EN3,
?apgm~t£~lli YREG3 ;fD YREG5. TPS51120 ~·(JtrtU+Y3AL.
(Be. SMC KBCI070) 1t=79Jt1~fJ1:(j~FQ., !.lIJI~ 13-6 f1fff;.
common point voltage +VBATR is supplied to the YIN pin of the standby
6ecat1Se EN3,EN5 is hung in the air,is set to be opened automatically the
VREG3 and VREGS.TPSSI120 outputs +V3AL,+VSAL.+Y3AL is
(1070) as its standby power supply.is shown in figure J 3-6.
..
~ ~
_.
<'II RTC 'tY1AL
-~
_,
J
0_"'
<OPEl
1
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1....
U1B_DATA
70
XTAL1
71
XTAL2
CLOCIO
5IlI
75
32KHZ_OUT_GPl022
10
nRESET_OUT
TEST_PIN
•
X1
32.7A~
-
TP721_
T7
VCC1_PWRGD
_
_1.£Il 113
nBAT_1.£Il
tt5
114
nFDD_LED
ttl
41.11
II II
~-~
r-- I
..!.~64
..oIIS_1.£Il
711
PWEGD
Il5
•
NC
NC
He
17
127
NC 121
II!
I~I! =
He
.!..-"
SIISC_KBC1070_VTQFP_128P
Figure 13-7
the standby clock of EC
EC (t-J 77 JJ!lJJg~fiL(§%o BB1=*1mit!: +V3AL g':i1 RI23 5¥O CSO ~nt~
~ UIO Jg/f!JrPJ~, ~M 4 Jj!p~')jI:JJ~EEl.fB1 VCCI_POR#_3. t1000 13-8
in ofEC is the reset signal.The origin is:+V3AL through R123 and
n high level of UIO,UIO is synthetic.it will output the high Ie elof
ill
own in figure 13-8.
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'( ('
In"
1111'
\\llell Illth
Vl . V A
llllltlh)
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B~
.~
~--_=-=-=------t----;j:!~l
C~
~
~'
~~
fl
~
~L.
lsi
I
.
. Ii
! ~lII'II'i::5
-
-,.Idlal -=
it
n.
Ii
,"7>
-0
<
>
'n
+
<t:
<'1
,2
>
+
0I
:::!
5,
~
~
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~1
igure 13-9
the production ofV3A. V5A
;)trJ-J t~lU rrfi:ft. f Wf1T GPIO f~ I,;, rll GPIOO? ~n1UJ RSMRST# e
··~~~T#Ej TPS51 120 ~ 30}j!p (y~ I~ 13-9) !hJiJ 111 (fJ f;; g ~1'I!=:j (;{H~:(£ -
~]~;T#JJt1J , jill r.il r*HJf lit [J·H!HJL 1l!.).f.IE 1(,'
of standby being satisfied. its internal procedure configures all of GPIO
by GPI007.is shown in figure 13-10.R MRST# phase with(connected
ut by 30 pin of TPS51120(as shown in figure 13-9).then to send to
~:$Qlttb bridge.to inform the South bridge that the standby voltage is normal at
~lD~~L~~~, ~~~~~~o
~!!91lIWJlete the subsequent trigger and power-
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1 . 3. 1
~
*li"
nal) i
ocp Fl:!.i~ n fFf
f
P ircuit
l~J.:9Ub~ D XX Dunkel 1.0 l HP_ :1 Ob) -'*.J I ~ fIT ocp E€.g~ ~ 13-11
+VBDC N:E€.$lE.Jlt~r:J, t£ii- I o,ol·~ag~~ift~; ~Et:!.~1lt". I -0*-\ BDCR, C5E€. (ft'
jJij1-tt!1liPJlJ.~J7X;f§raJ. (~~ ;t;:*!EJ(~;tP.1V-, ~
As In enlec Do
~. ~IIY,
' Dunkel 1.0 an :\ample to explain OCP ir uit in thi
13-11,+VBDC is the battery di charging p rt,thr ugh lh
make a new name -
It ~ . 7j'!.Cr-#:
BDCR.b cau
ulTenr
ns
rion.ln the fi",
i tor \\ith 0.01·~
I'
the re i tance value i vel') mall.rwo of\olta;:;e an be
nas
the same,(calculated as 3 core series bart 1')'.3*3. """ II ',take an integer,i com enient t cal ulat .
rn 13-12 r:p.
+V8DC
~,-19raJiiHiL
·0· ~-1 L r' :8. ~~Z:0~7.-.
~.
-~&ffi~':
T'->T'-Bt. ~JtI:J VCC ~~,
~,~
.3 r'-<r:.l!'t'. or- ,
G D ~~. ii~. -l ij!;JJag G
~:IF~~, I~
m¥IJ.,.-VBDCR EEl II , ili~si~3 r:..<rllt ..:.
tI:J 1\i7*~ llV. ~ 8 ~ B:J \'cc ~ eg ~­
MAX_LX5 agEt:!..!3iE]-v·S §~Tf-.!3i~*. tEl@~~
tt!~ C530 LF1:.- I {8 16V B:J~Ili. ' G'\D 3=
IIV f.litI:J7 :V, PJ~~~1.&·:J~~~;_· ~ 3 .='
B9+~~+VBDC B:J 11 \ •
B
In the figure
13-1-.U·O- is L\13 ·S.i
the
• vc;rting input terminal- is the inverted input terminal.\\11 n
o uts GND logic. ote,G D with 4 pin is not !!found d.-.
Y-i <Y- the output should be Il\'SCC po\\ r
5 lifting pressure. and produ e the
GND tenninal II V to -Y.it an
tenninal of 3 pin L II \' 0-
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,1o...'.'-..1J-,1"'~G-.3t~"',JI-,J",AS.~.47_.,S4..
,
U505
'OUT
BAJ~S~30Vj.2A· +~sS·
vee t"---+---J.
.
'.
2
+VBATR :
11N·
Q38
5-.1-.7-.....·, 1-.1J-,n
~M3K7002F
""-t------1l'IN.
'
ClND
09025
RLZ18
3
1"' 1
2
£1 ..
DP_PRES
"''',7·''''''''·
Q38
~SM3K7002F
o
17
7·
tHENKO_LL~f48_2p·
MAX LX5
-
'
. !,.Ia~~ .r.e~~ .L.14:
J&~E13+V5S ~ Q38 t~1~B~, J3.~2 Q39 ~ ADP]RES ~fjJIJ, ill
.~m~~, ~~n*ffi~, g~ill~I~o
circuit is provided by +V5S through Q38,and is controlled by
y~der the case of no power or the adapter inserted.it can not
orking.
tp#im~Jt U28 ~"trl±l+V5A Itffi~;ffi1}iMP. 7J~tnru
~ATP ~EI!.ffi. EI!¥t!!.mA~~1iltffi~T IIV
0
the phase pin of +V5A voltage output by the standby
~utP-titS.The voltage of pulse crest value produced by
~ the crest voltage is equal to 11 V in the battery
M''''''''U"'l'~'~'
+V5A
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1 iClII . I .-11
thl: ori:ill of' IA.· LX5
I, J.(Jnuli'l~ _.5 '1i1iJ 11\ 1'10 . [ ' I. IfiI){ I.::!..J. V IJ~J 431 L (~I R fl1 C
L' t ~ IJ IIJ, p .;;J ll!.lIZ IIMH!: ~;I~ Ill! 1.24 V) I~ qI A yiM Ii:i.I n~~t±fu.
B R. "ljl'llljTJ.O:U I \;iull!.lk·~ A+1.24V=12.24V (lb.iEJJ)(D~ vee }IFn~~
J'oII-J:
!lt~ R·T- 1;~1'J~ 1-._-1 tfii" I 1l!.IIIUU A tri[J. 1TJJi&I:!Pi-f7HII: 100kn
)j-1F. il ~H,Jj;u -05 I'J~ 2 JJ14179 II.095V. J:11*i-I-~J~[1.24V/(100~+
otJ
J1
:O~.
0
I o 7.6 k...,) 11 10
1 -I_.the hip 504 is n t -1 1 output by the ordinary 2.5V,is 431 L of 1.24V
nn t d t gether.it a t as an voltage-regulator diode,the voltage of R terminal
th n
t nninal t
1.24V).The A terminal is also not grounded in the
~VBDCRof II .0 we can know that the R tel111inal is A+1.24V=12.24V(VeC pin
liti through R516 to supply the electric power),12.24 of REF terminal
h to A tenninal.if there ha e the differential pressure,then there have
7.68kn series partial pressure.calculated that 2 pin of USOS is
.24V/(100~ + 619n+7.68k~)*(6l9n+7.68~)+ II V]o
JII(J(J 11.095V, V+< V., 1 J]!p~1!iI:B GND, wtfik 11V, ~
DCRllV, -f&~~~ii.!L )§~:f:$J11=o
in is less than Il.095V of 3 pin, V+< V-, I pin outputs
Je ofQ509,the B pole is +VBOCR 11 V,the triode is
m~.m.~*, M®~~2~~lli&~
vcc, ff)t~ l6Vo 16V Q509
..-ill
fu
~~M 017 -B:iID, ¥IJ)§[ffiB~~t!IXim
the R terminal of 43 IL is also
when the voltage of 2 pin is
r than 2 pin,and outputs
R,then the triode is
electric current
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OCP
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JIj
JEW-N. Q22 ~jI]HI\)KIY~Ill.J.f,t:fiU 1.88V nt. -Urt1* Q21 \j-M, FL1~ SRSET 'hil.
.tJ:ft:~, J~' -~~jJJl1J: U2 (I~ OCP :j;J.tATIl!,J#L )2Jt;JJ OCP_OC#o
In the figure 13-15,whcn the voltage of LIMIT_SIGNAL becomes higher(not original adapter)
r the voltage of VBIAS reduces a ccrtain extent,when the voltage from Q22 conducted is higher
1.88V,one path makes Q21 conducted,pulls the SRSET voltage low,stops charging,and another
reaches to OCP execution circuit of U2.starts OCP_OC#.
-_._
......
_-~.
__•.
17
3
1
2
1 C51S 1 CS18
2
2
•
RS84
0_5%
• n circuit of OCP_OC# in the adapter mode
tt!ffi. r*iilE~ 7V J.r.;;(:J VBIAS ~~iNG~ltffi
0
~f@.ffi 5.79V, ~[]OO 13-16 JiJT7J'o
o J!ge of the adapter,the manufacturer set it to be
m the adapter after through the resistance
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+VADP
1
R106 2
="1'l1oClN_U1313DR2G_SOP_8
a
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dB
FJ
l!-
tS
II
oul'.>ll-----+
~ON_~_SOfl
•-
~~ 2
,
~
~
~
~m
1041(_'%
~
OCP
+VBDC
o.1UF_25V 10UF_25V
1~25V1
lfJ
o
n..- ..!L -1 C
I
lli<&15.!1C516
§
21
R564
2"
RUe
1K_1%
0_5%
10UF_25V
0.-
n
S
o
§
lfJ
~
W
C30
(l)
~
I
-..= ~
D515
I
I CHEHIIKD_BAT54_3P
OR'
..... 12
UTP
••
BATURVI
I
..
I~I 13-17
:''c ~\YJ0 OCI' rl!.I,'ii /ff,1
V'
__
J~n
MJ
2
210l
~
~I of Big OR GATE circuit
.*t!Iliitfif "*~n" IM1l (1t--:tr1-A:x~·ttn~%,u:no
4~lJ~ S-SERIES
7ttIT "*~ n" Jt!.~& I!I 13-18 11 +V3S Jt:/f'~:iID.IU!JTi5HJ(] J:j.\l:
1
0
0
design of "Big OR GATE' circuit (called by the author) in many Inventec
section as S-SERIES(HP_6531 s) an example to explain the "Big OR GATE"
3-18 +V3S is not pull-up called usually.
ZllREF
-
1 R1Z7 2
>Y3S
1011K..n.
• IlI3 •
ofthe Big OR GATE" circuit
VSS iI~ R130 ~ RBI j!t§H.£-~, .J3}jij1Ji
-~l@.m"I:fHW?tlliJt~, lJJ~m II+h=h Sg0
Law)
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t +V3S can not be less than 2.727V.1he result is shown in figure 13-20.
1I4nlIitlJ
I
--,
VI
J.J
V
VI
2.727
V2
5
V
V2
5
HI
68.1
II
HI
6&.1
II
R2
102
II
R3
49.9
Q
V3
2
R2
102
II
RJ
49.9
II
IYJ 2.189
Vl
RJ:JI!
--===-~
~
~
\·2;r;
-
'3'1=
-
V
V
V
U
-
-------_.
computational process of the node voltage
putational process ofthe threshold value voltage of -V3S
VSS ::f"~{~T 4.141V, tmOO 13-21 pJr~o
culate that +V5S can not be less than 4.141 V.is shown in figure 133S ~ VSS l¥Jf'l!lliftB~, *00 13-22 rp VCCP]G ~Ia
rfl~73£ {~ (;It 1mfg -'% I5l 1:1 )•
oltage value of V3S and V5S.in the figure 13-__ .if
and Rl29 series.the value of resistance becom s
1
RlI7 2
10K 5%
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'lll\lIl'It,11t1 \ ullll'
11 111 "'III,'
11',u l,11I1I111 Ill' 11I~"'1'1 111.111 ) I{I I Ill!'
11 '1.(111 lit, 11'111" I iiI' \ dill' III I"" 1.1111 l' • ),/11 Itlo11011
••
VI
III
If'
I I
V
VJ
,
III
11111110
II
III
10JIIII0
II
"' n
VI
V
1111
II
11,11/"
V
ullnllhl' IItllle \ (llllll'e 11'11 'II VCt' "( i is lUll level
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14 ~ Intel P[H H~~ ( 13/15/17) B~fi
(Platfonn Controller Hub) fJr
-+ ~ J:i:'4i'J 'f ..:; Intel PCH ~ -1'- Intel /... 6) 6ry -*~ft-~
0
• --fJ{. PCH Dry f-"oo J:J Intel 5 ff. JIJ, -110 Intel HM55 if, ~t~e.--f-\ 13/15/17 CPU; ¥-=..,
JIll;,:] Intel 6, 7 ff. JIJ, ~t~e...=., -=--f-\ 13/15/17 CPU, i.!.r13'J-f-\JLf-.ff, CPU iill..m JiU~
-Pi. e..tf:.t. A'fJ, J:J Intel 8 ff. JIJ PCH $ J4 -A~ ~ :;ijUCH 6!; ~.g.~;:JJ fit. 5lA~ ~ *- MCH
0
0
.yJ£~I~;:}]fjL 4e. PCH ~jg~IAff-t1:.M, oftJ:Jm{ff-t1:.M, :1I~:lC.PJTi)1Jo ,*-"*..=t*1l'~g
If.1lJ,fo 6, 7 ff. J'J at jf. ..=t~~1'
14
e...
of Intel PCH sequence(I3/15/17)
,
the platfonn controller hub.lntel PCH is the single bridge chipset in the Intel
uct of the first generation PCH is Intel 5 series,such as Intel HM55 and so
generation 13/15/17 CPU;the second generation and the third generation is Intel 6
the second generation and the third generation 13/15/17 CPU,these two of
same,CPU is in common used.The newest fourth generation has been
chip has all functions of the original ICH,also has the function of
'ginal MCH.It dose not matter to call PCH the North bridge or the
. Iy introduce the main feature of Intel 5 series,6 series and 7
tel ME fIl Intel AMT
and Intel AMT
5'_, ~ij!dtf-AtE~tm~PCH 1*1 8g~9!iL
~~-l';t,Jtr:p,
f.!M1t§J~.:lL Intel
dware inset the North bridge or
t in the same chip,but they
wn in figure 14-1.
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00 14-) Intel ME,fJ] ME ~('f~~1;}lfI
the architecture figure oflntel ME and ME firmware
7-~f$~ "iAMT" D~<gJ~IHJ(*o Intel AMT (Intel Active
"J!~*) ~mt.t~-;rIJW:JJX;{£;t;Jt~.Il':jJ(1~*Ai(*~Jc.
~~fj~ilJlaXi'j:~jCD{JI!'IEJ
0
technology called "iAMT" in ICH7.lntei AMT(lntel
bedded system integrated in the chipset in effect.it does
ir!>it is the biggest difference between iAMT and the
*
as ~ Jt J:/=l , ;Jtr}] fiE EI3 ME ~m i~pjM5~>it iJJ
, :¥cmAH\@1~, ep1~tE-1 :9EtJL, lcfJLgX;
0
, l!A BIOS j1HTj;,H/:ili~~{£itr
0
~tes in the BIOS chip.the function is
e status of the hardware. it can start
in the system with crash,power
8lso can enter into BIOS to
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&M~I-~~mITW~A~~~B: mp~m~~~£~~B~m7~apCk~~i~
~~a#~~~~m~W~.~®~A, ~~~mpw~, ~~.~~fi~~*.
Intel AMT technology can appear as a subsystem been independent of existing operating
system,because of the environment independent of the operating system.when the operating sYStem
is broke down,the administrator can remote monitoring and manage client-side.By this
technology,the computer been controlled also can remote manage and detect system when the
operating system is damaged or the system is broke down.or when the system goes \"/Tong,it can
send the warning message ,to detect the software and hardware,remote update BIOS and virus code
and the operating system,even when the system is power off, it can also manage work by the
website then it has worked out the problem troubled IT manager:users closed the safety and
management software on the PC deliberately or by accident,which leads to unacceptable
anagement.These features can significantly reduce the administrative cost for the company user.
~*' AMT ag*mff S5 {*OlVI7C~61,
ME m~, B1~p~Jt, Intel PHY LAN, SPI
MEMORY (CHANNELO DlMMO) ~tm~1feg.
system supported AMT is in the S5 sleeping state,ME module,the clock chip.lnlel
lOS MEMORY (CHANNELO DIMMO) need to be powered on.
lCH8M lftlf:l, ACPI 1f1{*D~JZ~]j:~*Uf*-%~:iJDl-1- SLP_M#. SLP_Mil
4-2 JiJT7F.
ICH8M.in the ACPl.donnant logical control signal is added a
oshot ofSLP_M# is shown in figure 14-2.
......._b111ty SI. .p Stllte Control: 5LP_M# Is for power plane
contral. If no Management Engine firmware Is present, 5LP_M# will
the same timings as 5LP_53#.
the power of Inter AMT subsystem. When the ME
'Siconsistent with SLP_S3# (while generating
S4_STATE#. the pin
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Type
Description
:uSleep Control: 5LP_54# Is for power plane control. This signal
power to all non-critical systems when In the 54 (Suspend to
01 skts) or
55 (Soft Off) state.
o
NOTE: This pin must be used to control the DRAM power In order to
use the ICHB's DRAM power-cycling feature. Refer to
Chapter 5.13.10.2 for details
NOTE: In a system with Intel AMT support, this signal should be used
to control the DRAM power. In Ml state (where the host
platform Is In 53-55 states and the manageability sub-system
Is running) the signal is forced high along with 5LP_M# In order
to properly maintain power to the DIMM used for manageability
sUb-system.
14-3
the pin definition screenshot of SLP_S4#
~~tJc~T 84, 85 f*n~~~, fflTt£fM;l{PJTj:Qf~~89~ffiB97f*o
~ft", fflTj:Q~~~~ffiOO7f*o~Ml~~(~~~~~T
iilt"), 8LP_84#~ 8LP_M#~!iH~~tLit, fflT}f-~rr AMT tk:65r
: when the system is in the state of 84.85 sleeping.is used to control
iIl~ by itself.
~ the AMT function-is used to control the switch of the
~when the main platfonn is in the state of 83 -85 and the
is forced to be pulled up by 8LP _M#,is used to open the
ofAMT.
18111:fm m14-4 JiJT7F
0
ofICH8,ICH9 is shown in figure 14-4.
T S4 ~:tt 85 )jj\:65
~
0
~&d:T S3 ~~z. HU
0
means that the main
be used to
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~ 14 ~
Intel PCH Dg~ ( 13/15/17)
fltrr
Management Engine Power OK: When asserted, this signal
Indicates that power to the ME subsystem Is stable.
MEPWROK
[] 1-l-5
Figure 14-5
MEPWROK CJIIl!lJJEx.ri.\!OO
the pin definition screcnshot of MEPWROK
ME~.M: ~~ffi~~~M .~ME.~~~B~.~.
xplanation] ME Power Good:when this signal is effective,it means that ME module POwer
has been stable.
T Ji1fj~~liijlJ..t. ft[ljjWlH~~IM1§~B1ff*~tLDI!I 14-6 JiJT~. ffi!E~z..j§. SLP_55#:it
J6J1! SLP_S4#fO S4_STATE#.il~, f&j§~ SLP_S3#.m'.r'SJ, SLP_M#~D SLP_53#1!t
AMT function is closed.the sequential relationship of each sleeping control signal
14-6.After triggering.SLP_S5# is set up to be high first.then SLP_S4# and
to be high,SLP_S3# is set up to be high at last.the timing sequence of
e.
SLP_MMJHu m.;<Ji, SLP_54=
, :pJ."~ S4_STATE#f-\ffi
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I
I
1
I
I
I
I
I
~~I
_
I
1/1
1
1 1297 1
1
I
-----r:---------t--"i~
:I
:::
~I)
1
I
I
I
1l9~~(&\}
I
I
hen AMT function is opened.the timing sequence of each sleeping control signal
, ~IIiD~~iMf§-'%~~Il:m* 14-(
0
·on is opened,the logic of each sleeping control signal is shown in the table
is opened,the logic table of each sleeping control signal
S3
S4
S5
o
o
o
o
o
o
~p;j, SLP_S4#fflTt£f~U r"'J 1J Itlli(i~ (!?cOO,
1 PHY LAN, SPI BIOS ~ltlli01{*m
0
IT
state of S5 sleeping.SLP_S4# is used to
used to control the clock chip,part of Cvoltage.We can open or shield AMT
S4_STATE#.When the
to be supplied
-303-
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m1 ~ ~ Intel P[H IM~ ( 13/15/17) B~fi
1
~ j~fJlll1., :' ~;~;Yljfl\ 6 ~~u.c::J4·mjfj1;t1}JI] T SLP_LAN#. i51!J};IJ5ExJfJOO 14-8 fifr7.r-o
Th • scrie. chip et till retain. LP_M#.the 6 series chipset renamed it to be SLP_A#,but it
t 'ontrol the power upply of ME module.The 5 series and 6 series chipset also add
#.thc pin definition is shown in figure 14-8.
LP_LAN# /
GPI029
a
LAN Sub-System Sleep control: When SLP_LAN# is deassert:d it
indicates that the PHY device must be powered. When SLP_LAN". IS
asserted, power can be shut off to the PHY device: SLP_LAN # will
always be deasserted in 50 and anytime SLP_A# IS deasserted.
A SLP_LAN#/GPIO Select 50ft-Strap can be used for systems NOT
uSing SLP_LAN;;! functionality to revert to GPI029 usage. When soft~
strap Is 0 (default), pin function will be SLP_LAN#. When soft-strap IS
set to 1, the pin returns to its regular GPIO mode.
The pin behavior is summarized in Section 5.13.10.5.
Figure 1'+-8
th.: pin definition sere nshot of SLP_LAN#
tionl LAN subsystem sleeping control,when SLP_LAN# is ineffective,the power of
;:.~~'C8lrd must to be retained:when SLP_LAN# is effective,the power supply of the network
LP_LAN# is in the state of SO and SLP_M#/SLP_A# is ineffective it keeps to
detection signal and SUS_PWR_DN_ACK signal.is shown in
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pJ origin is altemating current or the system battery.The high level refers
supply.
. JAMEf11i*~t6 EC DtJ(*\~. 1~1:Q..:qz.~{;;f>'t-fim~:I1j~Fl:!.~Jjjf.
'the signal sent from ME module to EC.the high level means that it does
sis of Intel HM55 series chipset tinling sequence
1lJll¥l14-1O JiJT7j;, 1!Ii:j:I1*~fO~~~D~.
tel 5 series chipset is shown in figure 14-IO,rhe explanation of the
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m14 ~ Intel PCH 1Mf' (13/15/17) fltfi
aou.a
( ~)
Destination
( f:ll·j;}
SIgnal w..",.
(f;1 '.H,H;j
I!oI<\l
PCH
VCCRTC
8oar:l
PCH
RTCRSTti
SQTCRST'
3276Skh2 ---{L
80'"
PCH
~
--_0
PCH
POl
BOll'll
SUSClK
80'"
PCH
PVIRBT'l'
PCH
Boar.!
PCH
PCH
PCH
PCH
-------------------=_
V5REf.SUS
VCCSUS3_3 - - - - '
-'1
RSMRST.
=
(
-
---u
--'.-1---------------
Boa'll
_d
!loIu<:
-
I
_ _ _ _ _ _.L-_ _...J"
Vee ME
_ _ _ _..L./~_
C(lUU O"M I.Q I't ",,1111 bBliJe SLP_~
0' ala. ~SLP.S3a' bwl f'lOWa'
____'7
------_/
\ICC
-----------/
----------~!
~.~m..,~l.Q ...t l r PV.~ bA N) IOte<
\..AN_RST8 ~y~lloerterlJ'¥lOIl' .... Mr!'IeI",...AP" 'tOIl: 0 I
r-aybl:.:atI:llllt~b'parcm".sI'lClW"'9I~l. LA"
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: m*:it1(I(J 32.768kllz ,\1',11&, ~Jj:~ft~~·J)R1)~111, iIlWrHJl;1)1:iJ;~i:f~(1~Jj:
:32.768kHz cry tal next to the bridge.the bridge supplies the power to the
crystal supplies the frequency to the bridge.
3_3: '±~~MJf(l~q'j:~n1~~I@" 3.3V
0
:3_3:the motherboard supplies the power to the bridge.3.3V.
: '±~~fHMI~ 3.3V i'Jj1t!,-'lZ(J~ ACPI U1fL{J§%, ;I;i:}i!J,ff::jillj;n~ft,
l1:tM~~j-VL43)..f
:the motherboard sent the ACPl reset signal with 3.3V high level to the bridge,it
the bridge that the standby voltage has been n0n11al at this time.
: tff:&:tI:1fB 32.768kHz B1~rD !m* EC i*JB'~ld}f~O~, -rj~ SUSCLK *'*~~
bridge sends 32.768kHz clock. If EC is built-in crystal.SUSCLK is usually sent to
k.
.tror~7gM!l!:&:1J§ %, 3.3V-OV-3.3 V, jmf;r.I~~'fjJr 12)j~ tI:1 ft!lf~[HIC~
• e receives the falling edge trigger signal,3.3V-OV-3.3V,to infon11 the
0
I
\State.
m#~, .RiWi SLP_S5#JJX: 3.3V, */J\~tI:1:J.i:~n;jjC~
0
receiving PWRBTN#,set up SLP_S5# high to be 3.3V,it means that it
3.3V, ~/J\iJ!tI:11*O~;jjC~
0
S4# high to be 3.3V,it means that it exits the sleep state.
9.3V, ~7J'jJ!tI:1*m~~, illA SO 7ft:J1;jjC~o
83# high to be 3.3V,it means that it exits the standby state and
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~ 111 ~
SLP_LAN#:L
Intel P[H 1M ~ ( 13/15/17) fltfi
subsystem sleep control,controls the power supply of the network card.lfthe
motherboard not use Intel integrated network card.this signal is not to be used. If the motherboard
uses Intel integrated network card.and supports network awaken,then this signal is high in the
standby;when it not supports the network awaken.this signal follows SLP_M# or SLP_S3#.
VCCME: ME t~~Bj{ftE\:J. (ep~J.9i.\ AMT rJJ~~B%JtEt!.), ~~T SLP_M#. SLP_M#~~
1M" (:£t&X ME IflIftf), VCCME ][}1C*ffl SO ~~B~{t~r:@, ~ttlD,~,~~~"I:!.jfD VCC3_3.
VCCME:the power supply(power supply to achieve AMT function) of ME module.is
controlled
by SLP_M#.When
SLP_M#
is
hung up(there haven't ME module on the
motherboard).VCCME uses the power supply of SO state directly.such as the bus power supply and
VCC33.
VDIMM: tlfi~fHj.tE£!, ~~T SLP_S4#.
VDIMM:refers to the memory power supply,is controlled by SLP_S4#.
VCC: tlim~Jt~,~,~{ftEg~SO ;j)C~B~r:gEL
~f!lT SLP_S3#.
:€C:refers to the voltage in the SO state of the bridge power supply and the bus power
trolled by SLP_S3#.
±~~ CPU 1¥J~,c.,{ftJt, ~;lf:~f!lT SLP_S3#,
1fJjfB1.
therboard sends the core power supply to CPU,is also controlled by
99JtiJj'ifJl~Jt~~miJ~ 3.3V ~Jt.If, ~IEUT VRMPWRGD.
'gh level to the bridge by CPU power management chip.is equal to
Egolf, ~~ SO ;j)C~Jtlli:tfl).IE~ (#HIJ,~.~{~It).
¥ high level to the bridge, it means that the voltage of SO
~ply).
ME I~H1j:Bt, MEPWROK rn ME f~JR~Et\N
-~.
there have ME firmware,MEPWROK is
haven't ME firmware,MEPWROK
erboard sent the reset
wer good signal
is forced to
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bridge sent PO to CPU,it means that the memory module power supply of
outputs,it should be extemal pulled up.
ettML€i!itL 3.3V, ~i1~19c (-n9:~*~5tED itJ19 CPU !lift.
~:m reset 3.3V sent by the bridge.as CpU reset by conversing(is usually
chipset timing sequence above Intel HM65 series
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;g 1 ~ ~
•.
.....
_
_.
• ...
~CH
.....
--
PCH
-
pc"
PC •
PC"
Ole
13/15/17) fltfi
...
SA1CIt!U
~'}
7& k •
" cOM',J
PC"
OI'WROK
1:lI.rd
SLP~ 5JS.
"C _
1M" (
Intel pm
\~IS:l_3
PCri
ASMR:;t.
80"\1
SUSClK
PO<
r'.·.·RB1U.
,. . lUI
-..
-..
-..
--......
PO<
-- -- -
SLP_S5'
SJ'_SOO
SY)i.\f
- --
SJ'_'"
9.P_LNU
ws.'
\/D""
vee
PYIIDC
_ -
, - - - - - - """,.,_,..
-.-,.."4 _
I
.-
.........
RTC Et!~Et!, i?lf¥1¥ CMOS ~!!&,
otherboard,supplies the power to RTC of
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US3 3 Ji
otherboard
"JUl,
provides the
deep sleep wcll
power sllpply
to the
pports the deep slecp,lhis voltage connccts with VCC US3 3.
~1¥'.I3"3V "':JI~ 'I~, C{/j·· V CDSW3 3 (I{JIl!.1IJtH, 3.3Vo /Gjd#1;f-JJ1
T#ii ·JW.
rboard sent 3.3V high level to the bridge.refers to the VCCD5W3_3
not supports the deep leep,this signal connects with RSMR5T#.
1I&~~m/J':'1,·i\.1, IiJJ1J-f-Jr-Jri S5 ~R.UI~4:!.[Ii,
bt:tzO VCCSUS3_3o
SUs#g"~o
state indicator signal.it can be used to open the voltage of 55 state,such
ot supports the deep slcep,SLP_SUS# is hung up.
~m(f.j~1=fJl{jl.lg,
3.3V.
erboard sent the standby power supply to the bridge,3.3y'
fro 3.3V r rt! 5{l-(I~ ACPI U ffL1~ S-, klJ!HJ!jw9:n.ffl: , Jltr"H~A:Jl,rtU±
t ACPI reset signal of 3.3V high level of the bridge,to inform
ynow.
fJjj.;JI, ffi1'-J'EfHl.±:f&*rn.
olock,but it not necessarily be adopted by the motherboard.
~, 3.3V-OV-3.3V , jffi~n.fJr-pJ iJ,llil±\ rnIW~;[j(~.
ing edge trigger signal,3.3V-OV-3.3V,informed the
LP_S5#JiX. 3.3V, ~7Fi!!t±'I~~JL;[j(~.
#,set up SLP _S5# to be 3.3V,it means that it exits
eans that it exits the sleep state.
~~,
i£.l\ SO 7f.tJ1Af\~.
eans that it exits the standby state.and
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!m*3:.ffUC 1E~ft. if1Z:t#A n.
LP
.Lh'1,fJIJ
Ifthere haven't 1E finnwarc.i not support 1\ 1T. LP # hung not u. es.
-=t3f-tJtf*nltti::f!JIJ. t<t~jIJf(~{:fJ~ll!.o lllltr-. l ~Ri\! (Jf*)1J Inl I rl(JfllJ~I(~
Jltnl'%/F*ffl. W1.~ltt~f~Jfl Intel 80 1tJJJGi«J-.F· 1-1,H"Jf~119~nJII(10ir~. JILf,~~JfHnll'Jltt
. /F1:~~~~~lJ1. Jltl*-I5-N~Pill SLP_A#:!3j( LP_S3#
LP_LA ": LA
0
SLP_LAN#:LA
subsystem sleep control.control
the n Iwor" card power . uppl) .If the
rboard not uses Intel integrated network card.this signal i' not adopted.Ifthe motherboard liS
integrated network card.and upports the neh\ork awaken. this • ignal i high when it is in
LP_A# or SLP_ 3#.
;when it not supports the network awaken.thi signal follows
VCCASW:
±:~1M;9ltEt=!.~B%!teg..<:1.1£-'f SLP_A#. SLP_A#;{,,~"LIIJ U:.tJ{ 7C M 1,',1
1t**ffl
VCCASW
so ;jft;eB~{J:tIt.
VCCASW:the power supply of the active sleep circuit.i controlled by
LP_A#. When LP_A#
up(there haven't ME finnware on the motherboard).VCCASW adopls the power suppl) or
directly.
IMM: m~ff1ftlt! ~:j1T SLP_S4#.
:refers to the memory power supply.is controlled by SLP_S4#.
flCJ3:.~It~ SO :If(;eB~ltlL ~~-'f SLP_53#.
voltage of SO state or the main power supply or olhers or the bridge.i
8V ~Et!3f.
*jf- SO :~~F[1.&'Mlnti~H T ,jff*Il,~.g~1jlrh.
3.3V high level to the bridge. it means that the voltage of SO
power supply.
AMT JJJfmat, APWROK
d3 AMT Jtrr1£;~JJ, *I~
AMT function.APWROK is controlled by AMT
consistent with PWROK.
u, ~ffm*f:Jj;~(lE~H]".
CPU that memory module power supply is
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U_SVlD is a group of signal sent to CPU power supply chip by cPUjt consists
bus consisted of DATA and CLK and ALERT# signal with the function of
ntrol CPU core voltage and The integrated graphics power supply.
D 1:f~j§, CPU:&t±J SVIDo
GO being effective.CPU sent SVlD.
lJ: CPU 1't-J~1L.\f#Eto
U:the core voltage of CPU.
IE CPU I't-Jf#Et;t:Jt1H.g-ffi:D~ 3.3V ~Etf.
CPU t*1L.,{jlr:t!(1t~H7
U power supply chip sent 3.3V high level to the bridge.it means that CPU core
*7F
0
l:I:HJ'.JSP:€l~1iL 3.3V. ~:ct~¥jdFJg CPU 1fl f:fLo
dge sent the platfonn reset 3.3V,as CPU reset by conversing.
?"tlI¥JIJ'JFf, ~ Intel 6 *J~B~DtFf~*-f~o :it]FF.j3}~:~~J1iJj£o
of Intel 7 series and 8 series is almost consistent with Intel 6 series. We
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1 s~~fiDj K42--1R (HMSX) H~~fl~fi
.5Ji K42JR ,'Vr... Jfl Intel S !f; 7']Z j; iJl6~~1L~o $.1:4+71 ~Jf$iti5c.~~*A Ta~1HJL;fDJ:.
RTC ~ 3~ ffil 59 &. $. ~II .! :;r- ~, $. 1: I!J.&- ii :;r-i}f
0
15
is of ASUS K42JR(HM5x) timing sequence
US K42JR uses Intel S series chipseLWe will analyze the standby and the power-on timing
ce under the adapter mode,because RTC circuit is almost the same,so we don t explain in this
15.1
The standby state
!:I:i AID_DOCK_IN, ~o 00 IS-) JiJfjf-;
0
_DOCK_IN,is shown in figure IS-I.
,-------------,
: eumnt settlng::6A
, Depend on \he current
: of
.
COO03
I UFJ25V
C60!)4
O.lUF~V
GND
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CHO vce
CHG t-ATH lliJ'V
PCOO02
o lUF125
.0.002
,f'VVX
'----<:.......JCHG vee GATE
the production ofCIIG_VCC
Et!.~Jt MB39AI32 O~ ACOK JJ!p, ~nOO 15-3 fffiFo ACOK
TH_19 t~u PR8904 frJ PR8906 7tffi1.{j-iU 6V lr:;(:jB~A;E1x~-1e;;
:ACOK pin of the charging chip MB39A 132,is shown in
~el then it will make CHG PATH 19 through PR8904
evelof6Y.
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~ 15 ~ ~fijj Kl12JA (HM5x) D'.l~fl.fr
pR8903
2
2
,;,
a:
<
PR8IlO6
~
lIS
0
'"<>
CHG_VCC
Q.
~
lUFI2
N~m~)(m~ccn
'f b U 5'-'>SZ3
Cl
0
ol(~
VlN
CTl1
GND!
•
VREF
AT
CS
AOJ3
BAn
to output the low
. to say,AC!N
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CIN and ACOK is described a shown in figure 1'l-6.lhat is to say,if
ACOK will output the low level.
1II11ot!5
1II1eJ1I.¥
1.237
1250
1.263
V
1.227
1.240
1.253
V
_"'mill!
200
I'INC!
MJl!if.
ACQKollJIIlllll1
'l"1\l'l'1\l1li
I.....
VACOI(L
mV
10
V"
ACOK glJIIlflili
00 15-5
VlU'
V".
5
5
I'"
0
ACOK gllll- 25 V
0.9
ACOK glJII- 1 rnA
nA
1.1
V
MB39A 132 l'J~l~mf)llt9-J;<·j AC jli!!iC.6~+&iY!tltJ~
rt! '=( tJ t1 till ifr,£ r~
features ofAC adapter detection in the data manual of
4) "5tl'l' 1.24 V( A'l!). Jl'~ AC llIEDoIIffitl1l!MnYJ
Jllle ".24) ""UJiI'J-HlJlI&.
~".Ml.
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ff-fid! Kl12JA (HM5x) U~I~fl ij
IN.
th t th'l' 1\\ 'r uppl) ol"thl: chip is
G~D
CHO CEllS
C1lQ \'CC
~M.;'
I
.
J
V1\(f
.
At
(lA
PRUl
'(l(lI(Qm
C G
SVS
vee
.IINNCIC
~~:
-lr=i;;;~"~C~OB'iCI~N~'D~~
ACL~
to
COMP'
,
.
•
..--+--+--~ vee
1.--'
!
,
CI
p
'l-ao"; ~
PR89'e
euxClrm
o.ur v'
I
~
-----
'$'
CIIII
I
ACIN
-=-l:c
IN.'
('I
~
'0
AOJl
•
_1- r<:ell 2
I 'U78 CHG
MB3~A'32
V
P
GND
GNO
I I I
l'bl 0
OUTC' '0
PCHGCI
HG c
..
..-
~~
Co.
Figure 15-7
to
!.l
ff
u
the screen hot of AClN circuit
CHG_VCC r~i1 PR8911 {II PR8915 it ffiJ§ B~*, ~J1it~,
ACOK ~ ~~U tl:l1111t!. f
e CHG_VCC to through the PR8911 and PR8915 partial
0
e ofCHG_VCC is not less than 17.4V.ACOK will output
TE irlliJ£1L. PQ8902 ~im, rn:~*et!~mB~
Eli AC_BAT_SYS. ~IJ 00 15-8 J5ffJF 1EJil't
i@.7lkfilWi fllj
c
0
VCC_GATE
partial
pressure to be
t CHG_PATH_19V.through PR8903 to
wn in figure IS-8.At the same
cut off,the battery is isolated.
=----_----<: AC_"T.S'S
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hown in
P ·3VSU9 ~ EN to
i IOUF~
1'ClI'2ll
00 15-9 RT8205 f~~tl VfN 'fn EN
Figure 15·9
RT8205 gel VI and E
i:iil~J!~7g+3VA. tuJOO 15-10 fifr?F,
+3VA.i shown
in figure 15-
.......- - - - - - o . : N A
ImOO 15-11
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1,1
I'*! 15 L
Figure 15-12
13V
if-Hi KL'1 JR (11M x) n~Jllfl fi
IJ.!. ¥,J:J-I VA Fe
+3VJ\n:numcdt be+3VA I·
,~III~ 15-13 JiJT Ii'
VA_EC {ij.f7.ii JP300" II!: :gJ9_3V
VA_EC through JP3003 to r named t b
"'VA C.i
0
h wn in ligur 15-13.
~VPLL
C3OO6
~ l00F~
~VACC
GNO
00 15-13
+3V _EC :9!¥,T:J+3VA C
+3VA_EC renamed to be +3VACC
1) a9 74 Ill~JtJ!1~t~HJt rt1ffi.. "!,to 1*1 15-14 JiJT;F
voltage to 74 pin ofEQU300 I).is shown in figure 15-14.
0
GPAO
GPA1
PWM2IOPA2
PWtoI3IGPA3
~1IJ 00 15-15 fiJTiF
0
I oscillation send back the
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GPFO
EC
-==--""'--1
GPF1
PS2CLK1/GPF2
PS2DAT1/GPF3
---"><'-1 PS2CLK2IWUI20/GPF4
- - " " " ' - I PS2DAT2IWUI21/GPF5
Note:
Cl_12.SPF
pi_dose 10 EC
F.:C XOUT
SMCLKO/GPB3
SMDATO/GPB4
_--'-'-"L.. SMCLK1/GPC1
_...J...LI,'--I SMDAT1/GPC2
_ J - U - I WUI221GPF6
_...J...LI,'--I WUI23/GPF7
_-l...Ll.L
_....LL.JL-
en
s:
OJ
c
'"
1T8500E-L
the standby clock of EC
~~EC U!ifl'Lf§-5, ~D~ 15-16 J'i)l/j,o lJ;t1§-'%~
"~fjIf{Jta1. ~tL1~ EC O{J}l{l'L3kfjl;t,lfJT i:l3 °
circuit to supply the reset signal to EC,is shown in
,when it is lack of the voltage or the temperature
~e.
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dby voltage,controls PQ81 05B conducted,pulls 2 pin of PQ8 J 05A 100v.then PQ8105A keeps to
cut off,ENBL signal is not grounded and into the hung state.is shown in figure 15-17(@ means
the component is not installed).
VSUS ON
BA154CW
PD8I04
PR8118
1KOIwn
@
ENBL
o
PR8121l
IllOKOIwn
Pll8IOSA
UIl6KIN
PR8121
lllOhm
00 15-17
igure 15-17
ENBL f"1::rt\~ft
the production circuit ofENBL
~.l1:o *mlt!.¥Jl"g~~Jt RT8205 sj ENTRIPI, ENTRIP21l!!J
, ~WiJm PWM Bj:ctlm.I~{i, I5Jntf1=JgJl'J3~ PWM S~frJa1g
PWM 1f ft3 ffi %.IE JIt J§, ~"tr I±l Jl'J3 fi!~ PWM: +3VSUS,
1 be cut off.The standby power manages EN TRIP I pin and
8102 and R8103 grounded to set respectively the over
as the open signal of two path of PWM at the same
signal of RT8205 being nonnal then outputs MO
:standby voltage pin of the bridge.
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P-s
NN...JLL _ _
!!oll!lJJ~ll!!!o
cr ~
cr
4()
ffi... GN02
ffi
-t----'-=='f-"-=--~ VQ2
~1p!dtj VREQ3
vo,
-r;
!lOOn PGOOO
Ciiii;~=-""-l UGATE2 BOOT'
M-if~"'-L~ PHASE2 UGATE.
~=--..........y LGATE2 PHASE'
PU8tOlA
!.GATE.
(r-SOOkBZI
ATB2(PSCGQW
m
Ill
... 0-
V)
m
Cl u.
wu
iliiii~~~lIl
lbe production circuil of the open signal of RT8205
Sll1S_LG_20 OI~E1T 5VSUS E§.~8~~~ G 1'&, jg OV-5V
~ 12VSUS Jt!.ffi. ~ 00 15-19 r}T5F
0
d -.:*SVSUS..."LG_20( comes from the down tube G pole of
U!Ue wave) through twice bootstrap to produce +12VSUS
P
U3Zl
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rement,only have the instantaneous waveform.not the continuous waveform.
1£~~JE BIOS )5, ~+:@:~YW~re~, Af<1~~11 f¥I 15-21 J5fT/F: ~[!jc~ Eg)Jij-T 14.37V
~ PR893 I ;rn PR8932 ?-}ffFi~~t1~ PQ8907 %:iiJl, ti1~ AC_1N_OC#,
:i!rt5" EC f1=T:J~
.Ul5o WJ* EC fjbJU~Ij~Ij~re7,§.1illA (AC_IN_OC#:7~1~) , ~~~~ftl~ VSUS_ON n~
<moo 15-22) ; ~IJ~~ EC *:@:~Y1PF~Ij:@re~, ~~~:f.f~tL1~ VSUS_ON, ~~l
S
+5VSUS, ~*$, BIOS m;I~&ff7Itffo 00 15-23 pfT7J'Jg VSUS_ON *~E1i0.iit
50ms kE~iJUJIJ~Ij:@i'!C.@,
VSUS_ON ~tL1~B~~ff~OOo
EC reading BIOS,it will detect the adapter the specific is shown in figure 15-21 :after the
of adapter being higher than 14.37V,through PR893 I and PR8932 partial pressure to make
f7 conducted,pull AC_IN_OC# low,to send to EC as the adapter detection signal.If EC can
the adapter inserted(AC_IN_OC# is low),it will keep the high level ofVSUS_ON(shown in
<5-22);if EC doesn't detect the adapter,it will pull VSUS_ON low,and close +3VSUS and
tben,BIOS will be out of voltage.ln the figure 15-23,after VS US_ON being set up
Jy: it does not identify the adapter in 750ms,VSUS_ON is pulled low.
•
10.
C2IIQ2
1UFII6V
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PR8931
33OKOHM
1%
POI!907
•
PMllSJ904 2
PR8932
16.llKOhm
PC8923
Q.1UFI25V
cOOI2
Figure 15-21
the prOduction circuit oflhe adapter detection signal
Tck
..
.J'L
• ACQ COmpiele M Pos: 740.Dms
,J 1..
SAVE_REt
iM'F
>: [
J!~
:Zjt-~
Miff
011 I.OOV
~'M§~~A:\
11115-23
M250m,
T[J(0004.JPO
CHl .r 1.44V
.M~i9nlj~~~~lIt V US_ON V.!U~OO
detecting the adapter
not detect the adapter
WRGD ffi "% , ~n I!I 15-24 f!IT7F
1
0
after the standby voltage being stablc,is
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Figure 15-24
the circuit screcnsho( thaI RT8205 outputs PG
SUS]WRGD B3 PR8601 J:fi79i¥ri[~.If,
1m1ll 15-25 fiJTlF
lFdiiEiIJ7 EC, iiHQ EC Jltn;H'!ffll'tJI.iE
0
SUS]WRGD is pulled up to be high level by PR8602.and sent to EC at lastto inform Ec that
dby voltage is nonnal,is shown in figure 15-25.
PR8601
l00KOhm
GPIO
VelA AlBITI
BPI.
SUS_PWRGD
GP12
GPl3
_PI4
AIlCI5IW\JI2aIOPI5
ECGP16
ADCIIWUm'GPI& 1ii==i~P17t==::b
ADC71WUl311GP17
I-'
the circuit screenshot that EC received SUS]WRGD
T#~ PCH, im%1A**IlEE!.lliB~ff.Jt~o PCH 1~m*1tj:iE
1t!..3f ME_SusPwrDnAck ffi ~, 1st It ECo EC :& ill
j!~ PCH lItBtx¥jft@~~jffiA, ~D 00 15-26 ffT1F.
MRST# to PCH,infonns that its standby voltage has
aI,ME module in PCH internal outputs the high level
ds ME_ACPRESENT]CH signal to PCH,infonns
in figure 15-26.
PCH
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~15.2
Trigger
~7fmfe!ll;&f§~ PWR_SW#¥ EC 125 }jl.jJ, ~nOO 15-27 f:ff7J'o
keyprodueing the boot trigger signal PWR_SW# to 125 pin of EC.is
~------<::-lPWR_SW'(53)
~-----C=LD_SW'
('S,53)
EC received PWR_ W#
pWRBTN#. PCH :fjt1±J SLP_S5#, SLP_S4#
iLP_S4#, SLP_S3#7tJJIJ~i;:7g PM_SUSC#,
of PCH,PCH sends SLP_S5#.SLP_S4# and
SLP_S4# and SLP_S3# renamed to be
sure 15-28.
=------,c::::> ......... /3DI
::;::,----<::> "'_SYNCI m
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M15 ~ !ffiW K42JA (HM5x) D~~fl fi
=
RI1I1WU\M;POO ~_--"-PW-",R"-,,l ..
=rr,-,-._-,-,:Or,o:21115
R~~,g~~
~6~~~o#~ (45)
TACfO'GPll6
FAND_TACH (33)
TACH1/GP07
L8DH.ATIWU124'GPEO 1-..JlL.----'~"""-J'-'
WUl2&GPE1
WUI26'GPE2
WUI27/GPE3
iL
PWRSWIGPE4 ~-----<
a
JPWRJ;N' (53)
'k~~~
UD_SW'
l.8Cl.lATIWUI7/GPE7
(45,53)
~
GPGln07 1-1W:..
--<<=]PIoCSUSBt (22)
EC
Figure 15-29
EC received the power-on instruction
SUSC_EC#~~IJ PQ8504 B~ NPN .=.t!Hf.IiTJBL 6 Jji;p:flU:ft1~J§, PNP - ~~i'ill-ij:
=fi'f E ¥m.rPJ C, f=:t.+12V, ~IJOO 15-30 p!riFo +12V ~~ii PR8507 ~IIJ
8512 j£-i:~Jm, +5VSUS $t~:±l+5Vo
SUSC_EC# controls NPN triode of PQ8504 conducted,after 6 pin being
conducted,+12VSUS flows to C from the triode E,to produce +12Y.is
ugh PR8507 send to the G pole of PQ85l2,PQ8512 conducted
+5V.
+~-------__<lI5V
:-..,PR85D7
+.
(1. 29A/O, 33A)
PC850lI
4.1\JFJe.3V
'"'::t:;;-----.......r---------O+ 12V (0.0 12A)
RT8202A (PU91 01) O~
1¥J~r-g~/1. [1
Jtff~~Ll\
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1 of SUSC_EC# is also sent to PD91 0 I.makes it to be cut off.is shov.n in figure
()2A(PU9101 ) is hung up.according to the manual of RT8202A.the hung is
ply of RT8202A being satisfied and EN/DEM being hung up.RT8202A
er + 1.5 V being nonnal.the chip open drain outputs + 1.5V_PWRGD.and
3VS produced later.
PD9101
INc'
2
z
~--o
P 1.5V TON '0
'5VSlJSO
PD9102
1l',,=vI
?COlli!
¥ +"-'~='--''''---"'-i
f-2--
Q.1UFflSV
'5VSlJSO
COIlO3
+12VS, +12VS )UH~1j1JD~1j PQ8510,
.sVS,
!mOO 15-32 ?fr~o
~S +12VS is added respectively to the
VS +3VS,+1.5VS.is shown in figure
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SUSBtLPWR POWER
Tf'C28T
TI'C2lIT
PT1507
PTB50II
o
0
:J~~~gt;:~'5VS
Pfl8SlJ2
f'Cll5OC
o.D33l.tFnSV
M.CCI.,·lQ%
*
T
,.''5
I~:=:,cw
(1. 29A/O. 33A)
Tl'C28T
PmID
~~
o
--:~~~t.-----rL---,L---o.,2VS (0. 012A)
~f@.Ek, {E;t;)=H~¥~+1.5V 8~1~E@.l:J&+1.5V
\1115-33 JiJT~o
trot voltage,after the chip receiving +1.5V
:J...SV partial pressure. the chip outputs
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Jt
.75VS/O.5A
+15V
P
I
PAlI181
I ~125V
PCi'&C
101l0l""
GND
vs
EC#lii.Ip;Ji!~ UP7706 (PU8402A) . II] T-l'"i;b~tr.~+ I.BY , ?~
11115-34 ijflf- •
# to UP7706(PU8402A) at the same time.i u ed to
1.8VS PWRGD,is shown in figure J 5-34.
(1A/
l000rFI5OV
I'l\1o&81
in figure 15-
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~ 15 ~ ~Ml Ka2.JR (HM5x) lM~fl fi
+<lVSUSO
PR/lli03
l()(1(Otrn
PR851l2
Figure 15-35
the production circuit ofSY TE l_P\\'RGD
WRGO ~£j1 PR8301 i!r'& RT8202 (PU8301) , ~~tl~ ttl. TT_CP ,
1115-36 PJT~o ~lIr:~iE'ffi J§, ;L:;;Jt~tI:J-YTT_CPU_PWRGD.
GO through PR830 I send to RT8202(PU830 I).control outpUts
is shown in figure 15-36.A fter the voltage production being nonnal.the
WRGD.
~1t!~iI. PR865L PR8652 ?tffJ§, F~ H_ TTP\\ RGD J!~
CPU_PWRGD j1 eE!. ~ PL8650 £.g 7g ALL_SYSTEt-.l
resistance PR865 1 and PR865_ panial
e.pu is shown in figure 15-37.- TT_CPU_PWRGD
the
_SYSTEM_PWRGD to EC.
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Figure 15-36
the production circuit ofVTT_CPU.VTT_PCH
+3VS
1.IK~I~1
PRllllS2
PRll8!:oO
249Qhm
+Yn CPU PWIlCID
c:>--_+2!!!lli'L.2~-v--L~~--C::>H VTTl'WRGD ~
,,0--2----.----'1..-....::> AU._sYSTE"]WRGD ~
PUl650
L - - _.........
Figure t5-37
iE CPU
x EC
the differentiation circuit of+VTI_CPU]WRGD
~~tl+VTT_CPU *0 H_VTTPWRGD J§ ~tIJ GFX_VRON JJz GFX_VlD .3?: RT8152
) , 7fJi5J*J.I.~-FB~~{J'ItJ.I+VGFX_COR£' ~OI!l15-38 PJT~o
e!'U receiving +VTT_CPU and H_VTTPWRGD,sends GFX_VRON and GFX_VlD to
201A),opens the core voltage of the built-in graphics cards +VGFX_CORE,is shawn
8.
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]WRGD being sent to EC,EC delays 99ms send CPU core voltage open
signal is sent to VRON pin of RT8856(PU880 IA),is used to open CPU
VCORE.After +YCORE production being normal.the chip outputs
_EN#,is shown in figure 15-39.
.....
"
...
~ ffl T 3:J& Ag 'lz ffi f~Hf' r:g~~ , JI:
f*
VRM PWRGD ff:@:-jj!~.Af~1t
lA .1t. EC JXtlJAg 3.3V (Ig
, f.J 2.6s J§ PQ860 IB A~ G
F#. -tl?fJt~ijt. 2.6 J§,
~. lit It ~ ~t'- 4U:fL 1[1
;Eg EC_RST#ii!lu O~Fg
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FORCE_OFF# 10w.That is to say.after 2.6s.if ALL_SYSTEM_PWRGD and VRM_PWRGD have
not turned into the high level,this circuit will pull FORCE_OFF# low,then pull EC_RST# 10W,to
realize mandatory outages.(FORCE_OFF# and EC_RST#
0... resistance shown in the part ofEC reset circuit in 15.1 section.)
connect
together
through
..-
11KOHW
--
I'UII9I
L....-------lJ,;."''--'--..----1:=>AU,..SYSIBU'WllOO
""'" -..r- c:::::o_L
(JO)
----'--!4J--"-i--T--z ....."T
~l~
PTIIIlO1
It-t, G f.&7Crm...t*~~ 3.3V, llt:l:h~;:m:rgB<:I G *&I~{i~
I:I:iJiiillt!)§ Is $JlJt4i'~E[:!" )jJt:f&JJtE[:!,~%ijz:o MHlint
~8601, m~ PQ8601, m~~ PD8603 ~-=.f-W:~PiiIfJT
It!~~~e.pPJ
0
If the switch,the G pole does not need to rise to
tu
is about 1.2V.So,ASUS motherboard will
by this circuit.During repairing,we can
circuit PC860 I ,dismantling PQ8601
gradually to trace each power
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........ 0602
~~J$OOtli
+VGA_VCORE
uit of tile core power supply or the independent graphics cards
!lltJ Q7601 ~Jm, it R7603 MUIh. Q7602 B~ G t1kf~~IJ
1:.+3VSG, ~[]OO 15-42 JiJT5F.
iRE_EN controls Q7601 conducted.makes R7603
low level after +3 VS partial pressure.Q7602 is
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~ljH~IC.'iJtl:lUE1i~0 PU8201 ltW(l~ YGA_YCORE]WRGD ~£ UP7706 (PU8403A)
7fJa+1VS, :!lnl~ 15-43 lfriF.
After the core power supply of the independent graphics being nonna!.PU820 I send
GA VCORE_PWRGD to UP7706(PU8403A) to open + I VS.is shown in figure 15-43 .
•1
10
.-.....
'
~ 15-43
+IVS f=~F.€!.~
Figure 15-43 the production circuit or + IVS
~ ~ ~ PQ8560.
sent
~ it!f!t:t~ ~ *IJ +O.75YSG , + l .5 YSG,
to
PQ8560.by
conversing
to
control
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~~~~~~".5VSG
(O.79A/O.056A)
""
'--_ _
~~.z...,,'V'3V2lllJKQwn-..L-~'~~~
-,
1I10K0l1",
PRJ!S63
+12VS
send
to
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PARK_PECLK_REQMit PCI--(' iu*fttJj~ Fn1 100MHz }:;':,~~Mt.II'. ~nl*115-46 (if/Fc
VGA VCORE PWRGD is sent to Q7504 at the same time.makes it conducted.and produc
~
the 10 level of PARK)PECLK_REQ# to PCI J,requests to send 100M Hz bus clock of the graphics
cards is shown in figure 15-46.
N/II
OOhm
@
1.1 VS]WRGD
GND
the production figure of the graphics cards clock request signal
CLK_EN#~2i1 CQ2 &*F:lMr'&J E\!-fBj
27) ffJBAt~c
6 chip outputs CLK_EN# through
15-47.This signal is sent to the
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r the clock IC opening work,producing each clock to PCH,then produced each clock by
Jock to the peripheral.The block diagram of pel-] built-in clock is shown in figure 15-
..
PClc'" loe M err-n J
rCI loopbac.k
chip outputs VRM PWRGD to
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J.jgun: 15-50
PM PWROK renamed to be PM_PWROK]ClI
PM_PWROK_PCII ~~ PCII n~ MEPWROK, SYS_PWROK
PWROK J]/;Il,
.t!oOO 15-51
mmPM_PWROK]CH is sent to MEPWROK.SYS]WROK and PWROK pin of PCH.is shown
in figure 15-51.
PIA PWROK PCH
_ _
:!:::ROK
_ _- - - - - ' W - -. toAEPWROK
PCII ~UO-= l' PG
00 15-51
Figure 15-51
PCl-! received three PG
auc!lJ PWROK j§, ~tl1 DRAMPWROK f*Ji%~ CPU; 1:£ PCH i*Ji\il, PWROK lJ.
0K i!:.~.!:j, 1'= 1:: PROCPWRGD ~ CPU. PCH ;& tl1 PLTRST#, £ ~ 7:J
0318 R0319 irlliP.lt 1.\ V ~ CPU. 00 15-52 TJ CPU D~ PG :fD~fiI~
OK,sends
DRAMPWROK
signal
to
CPU;in
the PCH
OK Jogie,to produce PROCPWRGD to CPU .PCH sends
through R03I 8,R03 19 partial pressure to be 1.1 V to
wn in figure 15-52.
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