Signal Processing for
Software Defined Radio
Sample Slides for 2019
Software Defined Radio Signal Processing
Software Research Radio: Xilinx FPGA development system
VITA 57, FPGA Mezzanine Card (FMC) [G4]:
Analog Devices RF Agile Transceiver [G5]
Advantage: Low cost, state of the art technology
Disadvantage: Steep learning curve for custom
applications.
5/25/2024
John Reyland, PhD
2
Software Defined Radio Signal Processing
Software Research Radio : Nutaq PicoSDR
Advantage: Designed for FPGA
physical layer large scale algorithm
development. PC side can run GNU
Radio, C++ or Simulink
5/25/2024
John Reyland, PhD
3
AD9361 Demo
Analog Devices AD9361 (Catalina) Transmitter
70 MHz – 6GHz
P0_D[11:0]
Data_clk
Tx_Frame
FB_Clk
Programmable LPF
Halfband LPF 1
Halfband LPF 2
Interpolating LPF
DAC
Baseband Tx LPF
Secondary Tx LPF
12 bit parallel data input, CMOS or LVDS
Master data in/out clock, BBP (baseband processor) timing reference for data transfers
Input transmit data valid when high, zeros transmitted when low. Synced to FB_Clk
BBPclock, phase locked to Data_clk, times P0_D transfers
Interpolate by 1,2,4 or bypass. Gain 0 or -6dB. Taps = 16*(DAC/input clock).
Interpolate by 2 or bypass, coef = [-53 0 313 0 -1155 0 4989 8192 4989 0 -1155 0 313 0 -55]
Interpolate by 2 or bypass, coef = [-9 0 73 128 73 0 -9]
Interpolate by 2 or 3
12 bits
Third order Butterworth LPF, 3dB corner frequency programmable 625 KHz to 32 MHz
Third order Butterworth LPF, 3dB corner frequency programmable 2.7 MHz to 100 MHz
Derived from Analog Devices UG-570, “AD9361 Reference Manual” and AD9361 data sheet
5/25/2024
© John Reyland, PhD
4
Economy SDR
NooElec R820T SDR & DVB-T NESDR Mini
5/25/2024
© John Reyland, PhD
5
GNU Radio and Simulink
GNU Radio Companion signal flow graph details
Hardware
Source
Port
(complex data)
Parameter, seen
by all blocks
Parameter setup for
radio that drives port
5/25/2024
John Reyland, PhD
Port
(real data)
Hardware
Sink
Signal processing
block, usually
written in C++
Software
(GUI) Sink
6
GNU Radio and Simulink
Simulink VHDL code generation example
Key concept: Simulink BDE, VHDL, and FPGA logic are “Bit and cycle true”
Notice the very precise fixed point attribute (FPA) “sfix24_en12”, a twos complement
fixed point signed number with 24 total bits and 12 factional bits. FPA can be different
for every signal to minimize use of FPGA resources. This is a departure from the words
and bytes of processor based computing.
5/25/2024
John Reyland, PhD
7
Software Communications Architecture (SCA)
A goal of SCA is, from [S2a]:
“Provide for the portability of
applications between different
SCA compliant implementations.”
SCA seeks to save time and money by
enabling deployment of SCA compliant
waveform applications on radio
hardware manufactured by various
companies.
Any qualified company can produce
signal processing software for an SCA
radio – software becomes a commodity
and price to the government falls
5/25/2024
© John Reyland, PhD
8
Software Communications Architecture (SCA)
The SCA “Big picture”, the framework that sets up SDR applications
Note the similarity
between the CF
application factory and the
personal computer BIOS
5/25/2024
© John Reyland, PhD
9
Space Telecommunications Radio System (STRS)
Is SCA suitable for space flight radio
reconfiguration? Space communication
can have different constraints:
• Space flight radios tend to use
slightly older more “time proven”
technology – thus computational
resources and memory may be
limited .
• Deep space missions can extend
over many years - the ability to
reconfigure a waveform after
deployment may have significant
advantages for data collection.
5/25/2024
John Reyland, PhD
10
Space Telecommunications Radio System (STRS)
NASA’s Space Communications and Navigation (SCAN) Test Bed
Launched on
July 21,2012
Tanegashima
Space Center
of Japan on
the launch
vehicle H-IIB
http://spaceflightsystems.grc.nasa.gov/SOPO/SCO/SCaNTestbed/
5/25/2024
John Reyland, PhD
11
SDR Advantages
For a given Bit Error Rate, higher bandwidth efficiency requires higher Eb/N0
8
𝐶
𝑊
7
Bandwidth Efficiency
6
 Ps / R 
Eb
 10 log10 

N0
P
/
W
 n

Unattainable
Region
5
16QAM
4
8PSK
3
2
1
QPSK
BPSK
BER assumption = 10-5
~9.6 dB
5/25/2024
Eb/N0 (dB)
John Reyland, PhD
12
SDR Advantages
SDR facilitates Adaptive Coding and Modulation (ACM):
BER assumption = 10-5
5/25/2024
John Reyland, PhD
13
SDR Advantages
CPE
M
H
z
862
54 -
54
2
TV
Station
-86
6
-8
2M
54
CPE
Hz
SDR Cognitive Radio Application: IEEE 802.11af TVWS Network (see [H8])
MH
z
Inter
net
Spectrum
Sensing
Licensed Incumbent
Data Base: TV
signals, wireless
microphones, other
WRANS
BS-CPE protocol is DAMA
(Demand Assigned
Multiple Access). DL
supports 1.5 MBPS, UL
supports 384 KBPS
Spectrum
Manager
Base
Station
In
te
rn
e
100 Km max WRAN radius
255 max number of CPEs
t
TV
Station
Geolocation
Data Base
5/25/2024
CPE
CPE (Customer Premises
Equipment): Data Comm,
Spectrum Sensing,
Geolocation
John Reyland, PhD
A similar cognitive radio
application is [H9]
14
SDR Modulation Types
 F  
sin  2  c  k 


  Fs  
QPSK Quadrature
components at the
receiver
xI ( k )
p (k )
y (k )
 F  
cos  2  c  k 


  Fs  
xQ (k )
p (k )
 F   1
xi (k ) sin  2  c  k  0


  Fs  
Sine Local Osc.
 F  
sin  2  c  k 


  Fs  
xI (k )

n = 0
1
2
3
4
5
k = 0
8
16
24
32
40
6
7
48
8
56
64
 Fc  
 k 
 Fs  
Cosine Local Osc. cos  2 

0
0
5/25/2024
Tb
2Tb
3Tb
4Tb
© John Reyland, PhD
5Tb
6Tb
7Tb
8Tb
9Tb
15
SDR Modulation Types
OFDM starts by converting symbols indexed by n at rate 1/Ts
Into parallel blocks indexed by k at lower rate 1/T = 1/MTs
bi (n )  jbq (n )
In this example:
M=4 input symbols per output symbol
Symbol rate Fs
Symbols on separate frequency muxed channels
now exit at Fs . Each block is an OFDM “symbol” at
block rate Fs/M
b(4k )
b(4k  1)
b(4k  2)
IDFT
We clock in time domain symbols, however Inverse
FFT input bins correspond to the frequency domain.
b(4k  3)
Channel 0 Symbols
Channel 1 Symbols
Channel 2 Symbols
Channel 3 Symbols
n  0 1 2 3 4 5 6 7 8 9 10 11 12
k 0 0 0 0 1 1 1 1 2 2 2 2 3
5/25/2024
Input symbol indexing
© John Reyland, PhD
16
SDR Modulation Types
4 Output
samples:
First input symbol Second input symbol
modulated by 0
modulated by Fs/4
Third input symbol
modulated by Fs/2
Third input symbol
modulated by -Fs/4
s (4k )
 b(4k )e j 0  b(4k  1)e j 0
 b(4k  2)e j 0  b(4k  3)e j 0
s (4k  1)  b(4k )e j 0  b(4k  1)e j /2  b(4k  2)e j  b(4k  3)e  j /2
s (4k  2)  b(4k )e j 0  b(4k  1)e j
 b(4k  2)e j 2  b(4k  3)e  j
s (4k  3)  b(4k )e j 0  b(4k  1)e  j /2  b(4k  2)e  j  b(4k  3)e j /2
Here is the output spectrum showing orthogonal channels spaced 1/MTs apart. Note that
sampling is at the original symbol rate: Fs = 1/Ts
Important: Four time domain symbols in results in four samples out
The four samples out are four samples/symbol on 4 different orthogonal channels
5/25/2024
© John Reyland, PhD
17
SDR Modulation Types
The CCDF shows the
probability of peak
power exceeding
average power.
PAPR = peak to average
power ratio implies this
probability, usually 10-4
5/25/2024
© John Reyland, PhD
18
SDR Modulation Types
A modern Continuous Phase FSK (CPFSK) design:
 F  
cos  2  c  k 


  Fs  
xI ( k )
a ( n)
1  
0  
Antipodal
Mapping
b( n)
p ( k ) x(k )
Pulse
Forming
 
 (k )   (k  1)    x(k )
L
Phase Ramp
Recrusion
cos  (k ) 
sin (k)
y (k )
 F  
sin  2  c  k 


  Fs  
Phase to
Complex Baseband
xQ (k )
Modulator
Fb = Source bit rate
Fs = MFb = Pulse sampling rate (M = number of samples in the transmit pulse)
Fc = carrier (or intermediate) frequency
Fs = output sample frequency
2 Fc radians
2 radians Fc cycles seconds

cycle
second Fs sample
Fs sample
5/25/2024
© John Reyland, PhD
19
SDR Modulation Types
A closer look at the CPFSK antipodal mapping, pulse forming and phase ramp recursion:
       1 cycle 
 M    M    2 radians 



h
1
 1 
 
M 
x(k )
n = 0
k = 0
1
1
2
3
4
2
5
6
7
8
3
9
4
5
6
7
8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
2

 (k )

2
0
5/25/2024
M
2M
3M
4M
5M
© John Reyland, PhD
6M
7M
8M
9M
20
SDR Modulation Types
 F  
cos  2  c  k 


  Fs  
Let’s put it all together now:
y (k )
xI ( k )
a ( n)
p ( k ) x(k )
b( n)
1  
0  
Pulse
Forming
Antipodal
Mapping
 
 (k )   (k  1)    x(k )
L
Phase Ramp
Recrusion
k = 0
1
1
2
3
4
2
5
6
7
8
3
9
sin (k)
 F  
sin  2  c  k 


  Fs  
xQ (k )
Phase to
Complex Baseband
x(k )
n = 0
cos  (k ) 
Modulator
4
10 11 12 13 14 15 16 17 18 19

 (k )
-2Fb -Fb
0
Fb
0
Fb /2
2Fb

xI ( k )
xQ (k )
-Fb /2
y (k )
0
5/25/2024
M
2M
3M
4M
5M
© John Reyland, PhD
-Fc
0
Fc
21
SDR Modulation Types
As M is decreased, GMSK has less frequency fold back than RC filtered BPSK
Also, channelization is easier with GMSK due to tighter spectrum
Comparison of GMSK, BT - 0.3 with BPSK, 60% Excess BW, Samples/Symbol = 8
10
BT=0.3
Alpha=0.6, RC
0
Power Spectral Density
-10
-20
-30
-40
-50
-60
-70
5/25/2024
0
0.25 0.5 0.75
1
1.25 1.5 1.75 2 2.25 2.5 2.75
Normalized Frequency fT
© John Reyland, PhD
3
3.25 3.5 3.75
4
22
RF Propagation Channels
Simplest large scale path loss (fading): Large scale line of sight propagation
PTx  Transmit Power
Simplest case: Line of sight (LOS)
Friis equation (not dB):
PRx  Received Power
GTx  Transmit antenna gain
 2 
PRx  PTxGTxGRx 
2 n 
16

D 

with respect to isotropic gain
GRx  Receive antenna gain
n  2 for LOS, no obstructions
  Signal wavelength
5/25/2024
© John Reyland, PhD
23
RF Propagation Channels
Diffraction, reflection, scattering can all contribute to small scale multipath fading
Multipath: Multiple paths from transmitter to receiver. Small receiver or
reflector movements can cause variations in received signal power
5/25/2024
© John Reyland, PhD
24
RF Propagation Channels
For fixed receiver and reflectors, RMS delay spread and coherence BW describe
the channel time dispersion
tavg 
2
a
 k tk
k
a
2
k
k
t 2  
avg
 average excess delay
2 2
a
 k tk
k
a
2
k
 second moment
k
 t  t  avg   tavg 
2
 t = RMS Delay Spread
Coherence Bandwidth
5/25/2024
1
1
 Bcoh 
50 t
5 t
© John Reyland, PhD
2
See [R2], page 160
25
RF Propagation Channels
Doppler spectrum is brought about by multiple reflectors
Constant velocity, constant wavelength: multiple paths result in multiple Doppler shifts:
1 direct v cos  direct 
f direct 

2 t

1 reflect 0 v cos  reflect 0 
f reflect 0 

2 t

1 reflect1 v cos  reflect1 
f reflect1 

2 t

5/25/2024
© John Reyland, PhD
Assumption: reflections
come from point sources
26
Channel Equalization Techniques
Raised cosine pulses have an extremely important attribute: at the ideal
sampling points, they don’t interfere with each other
Over an ideal channel, delayed transmit signal will be observed at the receiver.
Ideal channel: sreceived (t )  stransmit (t   )
© John Reyland, PhD
5/25/2024
27
Channel Equalization Techniques
Center
Pre cursors
(occur before
the center)
Post cursors
(occur after
the center)
See [E1] and [E2]
6
5
4
3
2
1
0
Post cursors
Delay 1
u
Symbol
Delay 1
Symbol
Delay 1
Symbol
Delay 1
Symbol
c1
c2
c3
c4
A decision feedback
nonlinear adaptive
equalizer
Pre cursors
slicer
ylin ( n )
Weighted and summed
precursor decisions are
feedback to cancel
postcursor ISI
yeq (n )
-
Delay 1
Symbol
Delay 1
Symbol
c1
d
c2
d
c3
d
ynonlin (n )
© John Reyland, PhD
5/25/2024
Delay 1
u
Symbol
28
Channel Equalization Techniques
Receiver Summary
Known group delay distortion introduced by receiver analog processing:
Chebyshev 8th Order Low Pass Filter
Gain (dB)
Anti-alias LPF cleans up ADC
input, however group delay
variation is 66.5% of symbol
time
0
-20
-40
-60
0
400
600
800
1000 1200 1400 1600 1800 2000 2200 2400
Group delay variation = 1.33054 (nsec), Percent of symbol time = 66.5271
Group Dly (nsecs)
This will wreck QAM
5/25/2024
200
3
2
1
0
0
200
400
600
© John Reyland, PhD
800
1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
29
Channel Equalization Techniques
Frequency Domain Equalization of OFDM
OFDM requires 2-dimensional
Frequency/Time equalizer
LTE single antenna base station
transmits a reference symbol
every sixth subcarrier in the
frequency domain. In the time
domain, two symbols per slot
carry reference symbols, also
called pilots
MF = Frequency domain channel
spacing, MT = Time domain
channel spacing.
Subcarrier spacing is 15KHz so
pilot spacing is 90 KHz
© John Reyland, PhD
5/25/2024
30
Multiple Access Techniques
CDMA: Extra data symbols at a higher rate are overlayed for channelization Extra
symbols are called “Chips”. Random chip sequence results in a “Spread Spectrum”
Spreading by 4 Chips/Bit:
Two ways to implement spreading:
Exclusive OR
Customer
Spreading
Data
Code
0
0
0
1
1
0
1
1
5/25/2024
Spread
Sequence
0
1
1
0
Multiplication
Customer
Spreading
Data
Code
-1
-1
-1
+1
+1
-1
+1
+1
© John Reyland, PhD
Spread
Sequence
+1
-1
-1
+1
31
Multiple Access Techniques
IEEE 802.15.4 defines the TDMA physical layer for Wireless Sensor Networks (WSN):
Contention slots: Remotes randomly pick a slot, listen for activity and then
transmit a reservation request. This type of random access is called Carrier
Sense Multiple Access (CSMA). Collisions between remote signals are possible
Contention free slots: Network coordinator has assigned a slot for exclusive use
of a remote. Assignment is communicated to all remotes through the beacon.
5/25/2024
© John Reyland, PhD
32
Multiple Access Techniques
Basic idea behind phase array
antenna beamforming:
0 = extra distance the wavefront must travel to antenna element E1
L2= extra distance the wavefront must travel to antenna element E2
L2+L3 = extra distance the wavefront must travel to antenna element E3
For a given carrier frequency f and speed of light C, extra distance corresponds
to phase shift in radians, for example:3  2 f  L2  L3  / C
Element receivers compensate this phase to create a main lobe at any angle
5/25/2024
© John Reyland, PhD
33
Multiple Access Techniques
In general phased array antennas are
two dimensional.
Z
Y
 El
 Az
X
Antenna lies flat in the XY plane
Define azimuth and elevation angles for
any point on the incoming plane wave
5/25/2024
© John Reyland, PhD
34
Multiple Access Techniques
For nonzero elevation angle,
calculate the horizontal and vertical differential distances
  Dx cos  Az 
Lx
Lx  Dx cos  Az  cos  El 
In a similar way:
cos  El  


  El
 Az
  Dy sin  Az 
Ly
Dy
Lx Ly
Lx
cos  El  

 Dx cos  Az 
Dx
Ly
Dy sin  Az 
Ly  Dy sin  Az  cos  El 
5/25/2024
© John Reyland, PhD
35
Source and Channel Coding
Entropy coding removes redundancy, but not necessarily in real time.
Voice coding removes redundancy from, generally, real time sampled voice
Goal: Rout < Rin
Rin
Rout
The voice coder works continuously to reduce the data rate needed to represent
the sampled voice. Low latency may be important for phone conversations.
Let’s look at efficient ways to obtain the voice samples …
5/25/2024
© John Reyland, PhD
36
Source and Channel Coding
Shannon’s insight was that maximum bit rate is not limited by bandwidth alone
but rather a combination of bandwidth and signal to noise power ratio.
Channel, max
error free rate = C
Information
Source, R bits/sec
Encoder
 Ps 
C  WLog 2 1  
 Pn 
Signal and noise power are
measured within bandwidth W
AWGN
Channel
BW = W
Decoder
Information Sink
Shannon tells us for R<C an encoder exists that
allows error free transmission. He does not tell
us any other details about it.
In 1948, when data signals were simple ASK and FSK, Shannon and Hartley were able to
foresee the need for the complicated noise-like signals we use today. Good references for
Shannon limit are [C6] and [C7]
5/25/2024
© John Reyland, PhD
37
Source and Channel Coding
Shannon-Hartley Capacity Limits
Start with a BER requirement,
say 10e-5. Plot the required
EbN0 points for 4PSK, 8PSK
with no channel coding.
 W   C   
Eb
 10 Log10   2 W   1 

C
N0

 
For the same C/W, we can
operate at lower BER with
more complicated coding.
We can get close to, but
probably not reach, the
Shannon limit.
Here we show BW limited
signals. See [A19] for a more
detailed version of this chart
that also includes power
limited signals (e.g. FSK).
5/25/2024
© John Reyland, PhD
38
Source and Channel Coding
Concatenated coding for Voyager mission to Saturn and Uranus
Outer coder
Data
Source
Reed-Solomon
(255,223) block
code, 8 bit symbols
Inner coder
Interleaver
Rate ½ Viterbi
conv. code,
constraint length 7
BPSK
Modulator
Channel
Very good burst
error protection
BPSK
Demodulator
Rate ½ Viterbi
conv. code,
constraint length 7
Deinterleaver
Reed-Solomon
(255,223) block
code, 8 bit symbols
Data
Sink
Power efficiency is extremely important: Coding gain of 6dB can double the communications
range between spacecraft and earth ([C8], page 172)
Voyager telecommunications achieved 10-6 BER at EbN0 = 2.53dB, 2Mbits/sec [C23].
What system considerations are not very important?
Bandwidth efficiency and adjacent channel interference, not many other users out there.
Delay, waiting time for image reconstructions is OK
5/25/2024
© John Reyland, PhD
39
Analog Signal Processing
 Tnoise 
F  1 


Tref 

Tnoise  Tref  F  1
Tref
F
Noise Temperature:
N0
Tref = 290K = room temperature in Kelvin
F = Noise Factor of network: ratio of output to input signal to noise ratio
Tnoise= Contribution of network to overall noise. Amount by which the natural temperature
would need to increase to account for additional noise source:
1.
2.
3.
4.
5/25/2024
Measure noise power density as shown
Remove network
Raise temperature of the resister to get the same noise level
Tnoise = required temperature increase
© John Reyland, PhD
40
Analog Signal Processing
Practical application: Satellite receiving system front end noise
FLNA  1.17, GLNA  100
TLNA  290 * ( FLNA  1)  50 K
Tant  3K
Gant  20
LNA
Waveguide
Gwg  0.95
Fwg  1 / Gwg  1.053 WG reduces signal without affecting
noise; WG loss becomes SNR ratio
Tref  290 K
Twg  290(1.053  1)  15.3K
Gsys  Gant * Gwg * GLNA  1900
Gsys  20 * 0.95 *100  1900
Sat. comm.
figure of merit
Tsys  Tant  Twg  TLNA
Gsys
1900

 27.8
Tsys
68.3
 3K  15.3K  50 K  68.3K
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© John Reyland, PhD
41
Analog Signal Processing
For LO = 2472 MHz, High Side Injection: Image Frequency at 2542 MHz is low
side injected and lands in desired IF. Desired signal is spectrally inverted
Intermediate
Frequency = 60 MHz
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© John Reyland, PhD
42
Analog Signal Processing
1st Nyquist zone
100
Fs = 80
100
100
Frequency (MHz)
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Fs = 80
802.11g
40
20
0
60
40
After ADC sampling
802.11g
2nd Nyquist zone
frequency folding
inverts spectrum
20
Anti-alias BP filtered mixer output:
0
3rd Nyquist zone . . .
2nd Nyquist zone
© John Reyland, PhD
60
0
40
20
Mixer output:
80
60 802.11g
Anti-alias filter makes sampled signal much cleaner:
43
Analog Signal Processing
Noise power density (i.e. 1 Hz) at antenna input:
10 Log10 kTa  174dBm / Hz
k = Boltzman constant = 1.38e-23 Joules/degree Kelvin = 1.38e-23 (Watt-Sec)/Kelvin
Ta = Antenna noise temperature = 290 degree Kelvin (about 64 degree Fahrenheit)
For a parabolic dish, noise temp varies with pointing angle.
Total noise power in a bandwidth B:
Receiver
bandwidth
Pn  174dBm / Hz  10 Log10 B
For received signal power = -100 dBm, SNR at IF output:
10 Log10  Ps Pn   NFdB
 10 Log10  Ps   10 Log10  Pn   NFdB
Receiver
bandwidth
5/25/2024
 100dBm   174dBm  10 Log10 B   NFdB
NFdB
© John Reyland, PhD
44
Analog Signal Processing
ADC dynamic range details for one in-band signal:
Signal power must be
backed off by peak to
average power ratio (PAPR).
PAPR margin should also
account for expected
inband blocker power.
Minimum SNR required
by the modulation type:
 VADC min 
SNRRe q  20 log10 

 VNoiseFloorADC 
Note: ADC driver amplifier must also
have sufficient dynamic range
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© John Reyland, PhD
45
Analog Signal Processing
Voltage sampling in the time domain:
𝑥𝑠 (𝑛) = 𝑥(𝑡)
𝛿 𝑡 − 𝑛𝑇 = 𝑥 𝑛𝑇
𝑛
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46
Analog Signal Processing
Make the exponent a linear function of time (a ramp) and take the conjugate:
Now the complex exponential rotates CW and has a negative frequency spectrum
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47
Analog Signal Processing
A complex representation is required at baseband because the modulation will
cause the instantaneous phase to go positive or negation:
e j BB (t )  cos  BB (t )   j sin  BB (t ) 
After up-conversion, phase is always positive and complex exponential terms are redundant
e  RF
j 
t  BB ( t ) 
Signal now can be real:
 cos RF t   BB (t )   j sin RF t   BB (t ) 
cos RF t   BB (t )   e  RF
j 
t  BB ( t ) 
e
 j RF t  BB ( t ) 
This forces the existence of a negative RF image (ignored for most analog processing):
5/25/2024
© John Reyland, PhD
48
Analog Signal Processing
Closer look at 0 MHz intermediate frequency (IF) in a 40 MHz sampling BW
NZIF: 40 MHz IF required sampling at 80 MHz
- One ADC for one real valued signal
ZIF: 0 MHz IF requires sampling at 40 MHz
-Two ADCs for I and Q complex signal
Both NZIF and ZIF use a 40MHz sampling BW!
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© John Reyland, PhD
49
Analog Signal Processing
LO_Q
VGA2
ADC
Anti-alias LPF
VGA1
Anti-alias LPF
LNA
VGA2
ADC
Matching
VGA1
LO_I
Matching
LO leaking out the
antenna can turn the
receiver into a transmitter
that is more easily located
by direction finding (DF)
equipment!
Matching
A Static DC offset due to on channel local oscillator feeding back to RF input
Because RF and LO frequencies are the same, there is no filtering to
prevent LO from feeding back into receiver thru paths shown
Encode
PLL Synthesiser
Consider LO frequency 𝜔𝑅𝐹 mixing with a phase shifted version of itself:
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© John Reyland, PhD
50
Analog Signal Processing
IQ imbalance of quadrature
downconverting mixer causes
loss of image rejection
Quadrature mismatch can cause
interference between subcarriers
located at mirror image frequencies
in OFDM systems. See [A46]
Typical IQ imbalance spec
is 0.05 dB and 0.07 deg
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Analog Signal Processing
Summary, three main indicators of radio system quality:
5/25/2024
1.
Adjacent channel emissions; how much power are we dumping into
adjacent channels?
2.
EVM (Error Vector Magnitude). This is the average tightness of the
constellation points, a good indicator of overall system performance.
3.
Power efficiency; how much transmit power do we need to achieve
specified bit error rate (BER)?
© John Reyland, PhD
52
Digital Signal Processing
For our SDR DSP discussion, we assume packetized data
After the first packet is detected, the search window can be narrowed
If packet timing is known at receiver then, to help prevent false detection,
search window can be narrow after first packet detection.
Packetizing data is very common due to many advantages, among them:
• Fits in naturally with time division multiple access (TDMA)
• Symbol timing is re-estimated every packet preamble, for short packets
continuous symbol tracking throughout the packet may be unnecessary
• Interleaving and block coding may correspond to payload data size
Packetizing data generally requires a time reference, such as GPS or the NIST time
server, to stay synchronized within a network
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© John Reyland, PhD
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Digital Signal Processing
Let’s take a look at digital receiver color coded sampling rates:
•
•
•
•
FS = ADC sampling rate. FS is related to intermediate frequency location
FS/K = Complex baseband sample rate, K = 2 or 4 to reduce processing load
MFsym = Fixed number of samples/symbol. Often M = 2, 4 or 8.
Fsym = One sample/symbol. Final subsampling before decoding payload data.
FIF
ADC
FS
Automatic
Gain Control
Adjustment
IF to
Complex
Baseband
Timing
Reference
Generator
Preamble
Processing
Symbol
Rate
Resampler
Matched
Filter
FIFO
Equalizer
Carrier
Tracking
Hard/Soft
Decision
Slicing
Payload
Data
Decoding
Sample Ready
Wideband AGC to RF Front End
AGC
Control
Generally there is no integer relation between FS and Fsym.
The FIFO effects a transition between real time and non-real time processing
A DSP receiver can be looked at as a complicated downsampler!
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© John Reyland, PhD
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Digital Signal Processing
Closed
Loop
Timing
Closed loop transition tracking: A simple technique used for closed loop or
feedback timing recovery. Based on observation of detector output. See [D13] for
comparison.
• Advantage: Generally more suitable for DSP than timing tones because it does not
require large amounts of fixed point precision.
• Disadvantage: Requires good decisions from detector, sensitive to high error rates. Works
well for BPSK, QPSK. May not be suitable for more complicated modulations. Can only
tolerate small amounts of carrier frequency error.
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Digital Signal Processing
Closed
Loop
Timing
Band edge timing error: DTTL and Gardner are good for antipodal signaling such as
BPSK, QPSK. For higher order QAM, we can use band edge timing [D34, D32, D12]:
Shift up by Fsym
Shift down by Fsym
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© John Reyland, PhD
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Digital Signal Processing
Closed
Loop
Timing
Timing error loop filter controls acquisition time
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© John Reyland, PhD
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Costas
Carrier
Tracking
Digital Signal Processing
Costas loop for QPSK
LPF
(Fsym/2)
y(nTs )
+
cos(2 f c nTs  u(nTs ))
sin(2 f c nTs  u( nTs ))
I (nTs )
i (nTs )
Complex NCO
u( nTs )
v ( nTs )
Loop
Filter
_
LPF
(Fsym/2)
q(nTs )
Q (nTs )
 I (nTs )  jQ (nTs )  i (nTs )  jq(nTs )  
 I (nTs )i (nTs )  Q (nTs )q(nTs )   j  I (nTs )q(nTs )  Q (nTs )i(nTs ) 
v ( nTs )   I ( nTs ) q( nTs )  Q ( nTs )i (nTs ) 
© John Reyland, PhD
5/25/2024
58
Carrier
Tracking
Digital Signal Processing
Carrier tracking estimates the symbol by symbol
phase error by “remodulating” to produce an ideal
version of the received constellation point. The
radians of phase between the angle of actual
received symbol point – angle of corresponding
ideal point:  (k )   ( k )
From Euler’s equation
the phase error is represented by:
sin  (k )   ( k ) 
rx(k)+jry(k)
See [D12]
© John Reyland, PhD
5/25/2024
59
Carrier
Tracking
Digital Signal Processing
When loop is locked, we can linearly model carrier tracking by considering
only the phase (see [D43] and [D7], page 339)
 (k )
Z-4
I
 (k )
e( k )
KNCO
KP
Z-1
KDET
KI
Z-1
This model allows us to study the carrier tracking closed loop step response.
Note that we assume an ideal phase error detector:  ( k )   ( k )   ( k ) 
© John Reyland, PhD
5/25/2024
60
Carrier
Tracking
Digital Signal Processing
Final equation for input phase vs. feedback tracking phase:
K n K d z 4  K p  K i   K n K d K p z 5
 ( z)

 ( z ) 1  2 z 1  z 2  K n K d z 4  K p  K i   K n K d K p z 5
In Matlab code, set: Kp = 24.560, Ki =0.480, Kd = 1, Fs = 4096
PLLnum = [0 0 0 Kd*Kn*(Kp+Ki) -Kd*Kp*Kn ];
PLLden = [1 -2 1 0 Kd*Kn*(Kp+Ki) -Kd*Kp*Kn ];
PLLsys = tf(PLLnum,PLLden,Ts);
[Wn,zeta]=damp(PLLsys);
Pole
1
2
3
4
5
Frequency (Hz)
19.261
19.261
601.134
1598.34
1598.34
Damping Factor
0.707411
0.707411
1
0.46831
0.46831
Poles 1 and 2 are dominant, other poles have little effect on loop response. When damping
factor = 0.707, loop bandwidth = 4*dominant pole frequency. Thus loop bandwidth = 77 Hz
© John Reyland, PhD
5/25/2024
61
Carrier
Tracking
Digital Signal Processing
Response of
to a step change in
calculated and plotted from Matlab:
PLL for carrier tracking runs at the symbol rate.
0.3927 radians is about 22 deg.
© John Reyland, PhD
5/25/2024
62
Hard/Soft
Decision
Slicing
Digital Signal Processing
How about soft decisions for a complicated constellation like 16 APSK?
First step is to use absolute value (ABS) to map received point to first quadrant.
Keep track of original polarity to choose correct constellation points, See [D44]
Q
1000
0000
R2
Rmid
R0
1100
0100
I
© John Reyland, PhD
5/25/2024
63
Digital Signal Processing
AGC
Control
DSP gain adjustment has to wait for fast acting RF AGC to respond
Received signal envelope at ADC input
noise
Received signal envelope at DSP AGC gain output
ADC Saturation
Attack Threshold
Hang Threshold
Desired Range
Envelope Detect
RF Gain
DSP Gain
© John Reyland, PhD
5/25/2024
64
APSK Modem
APSK Modem Front End
Center Freq
= Fsss/4
IF to
complex
baseband
Ibb
Qbb
Inphase
Iadjust
Sample
interpolator
Sample
stacker
Qadjust
SampleRdy
Quad
Root raised
cosine filter
CenterIQ
UpIQ
SymRdy
Intersample
Interval
Timing loop
filter
TimingError
Timing error
generator
DnIQ
Red Sample Rate = Fsss
Green Sample Rate = Fss = Fsss/2
Critical Concept:
Blue blocks only execute when SymRdy pulses high
Blue blocks are idle when SymRdy = 0
Thus blue blocks process 4 sample/symbol vectors at the symbol rate
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© John Reyland, PhD
65
APSK Modem
Sample Interpolator: Intersample Interval
= 4.3 Input samples per output sample FTA = 0.5
Input
Output
4
5
FTA = 0.9
FTA = 0.3
5
FTA = 0.8
4
FTA = 0.2
FTA = 0.6
FTA = 0.1
4
4
4
4
FracAdj = 0.3
FracAdj = 0.9
FracAdj = 0.6
4
4
4
4
FracAdj = 0.2
FracAdj
FracAdj = 0.5
4
FracAdj = 0.8
4
FracAdj = 0.1
NextSample
FTA
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© John Reyland, PhD
66
APSK Modem
LMS Equalizer Signal Processing Diagram, let’s take this apart
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APSK Modem
Delay
Delay1/2
1
Symbol
Delay
Delay1/2
1
Symbol
Delay
Delay1/2
1
Symbol
Delay
Delay1/2
1
Symbol
Delay
Delay1/2
1
Symbol
Delay
Delay1/2
1
Symbol
c1
c2
c3
c41
c5
c6
Signal Processing Diagram
yeq (n )
Practical Implementation
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68
APSK Modem
Carrier frequency offset tracking
LMS EQ
From RC Filter
+ De-rotated constellation points
Tap Update
NCO
Loop Filter
Sin, Cos
Look Up
_
Slicer
KP
-1
KI
Z
Phase
Error
Baseband
Remodulate
Z-1
Conj
Ideal remodulated constellation points
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© John Reyland, PhD
69
APSK Modem
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QPSK Tracking (8PSK similar) showing PI Filter
© John Reyland, PhD
QPSK, 8PSK: These
constellations are the same
70
APSK Modem
Equalizer training stays simple until green line switches
Grn Line = 1, Equ uses all points
Grn Line = 0, Equ uses outer 4 points
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© John Reyland, PhD
71