L01
Properties and Definitions of
Digital ICs
VTC
Chapter 1
Properties and Definitions of Digital ICs
Thomas A. DeMassa and Zack Ciccone, Digital Integrated Circuits, 1st Edition, John Wiley and
Sons Press, 1996
Prepared by: Dr. Hani Jamleh, Electrical Engineering Department, The University of Jordan
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Introduction
• This chapter introduces the general properties and definitions of
digital circuits.
• These are common to all digital integrated circuit .
• Digital electronic circuits are represented by five basic logic
operations:
NOT
AND
OR
NAND
NOR
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Introduction
• The circuit that performs this logic function is referred to as a gate.
• Combinational gates are the logic gates that perform one or more of
the basic logical operations.
• In these cases, the outputs depend only upon the present value of the inputs.
• Sequential gates have output(s) that depend upon past values of
input(s), as well as present values.
• Implementation of these digital logic functions is also accomplished feasibly
using quite a few different digital electronic circuits.
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Combinational vs. Sequential Gates
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Introduction
• Generally speaking, the voltages (or currents) in digital logic circuits have
mainly two possible states indicating that the variables are binary.
• Considering voltage as a variable, the two possible states correspond to a
low voltage or a high voltage:
• The low voltage to correspond to a binary 𝟎 and
• The high voltage to correspond to a binary 𝟏.
• This is referred to as positive voltage logic and is used for all IC logic
families throughout this text.
• We begin by describing the basic building blocks of digital integrated
circuits:
• The inverter and the non-inverter.
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1.1 Inverting and Non-inverting Gates
Inverter
• Figure 1.1 displays circuit symbols that are used to represent gates that perform
logic inversion.
• This device is usually referred to as an inverter or NOT gate.
• Since it performs the logical NOT operation.
• The small circle in Figure 1.1a and b is referred to as:
• An inverting bubble or inverting circle.
(a)
(b)
Figure 1.1 Alternate Inverter Logic Symbols
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1.1 Inverting and Non-inverting Gates
Non-Inverter (Buffer)
• Another basic digital circuit device is the non-inverting gate which is
sometimes referred to as a buffer.
• Alternate circuit symbols for these devices are shown in Figure 1.2.
• Buffers are used to regenerate voltage levels:
• making degraded high levels higher and degraded low levels lower.
(a)
(b)
Figure 1.2 Alternate Non-Inverter Logic Symbols
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1.1 Inverting and Non-inverting Gates
Non-Inverter (Buffer)
• The inverting and non-inverting elements are the fundamental
building blocks for all digital logic families.
• The basic inverter and its operation are described for each logic
family.
(a)
(b)
Figure 1.2 Alternate Non-Inverter Logic Symbols
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1.2 Ideal Logic Elements
Ideal Static and Power Characteristic
• Figure 1.3a shows an ideal logic inverter.
• It operates with a single power supply (𝑉𝐶𝐶 in this
case).
• A typical operating voltage of many logic
families is 5𝑉.
• The current 𝐼𝐶𝐶 drawn from 𝑉𝐶𝐶 is ideally 𝑧𝑒𝑟𝑜.
• Giving a power dissipation 𝑃𝐶𝐶 of 𝑧𝑒𝑟𝑜.
• In actual digital circuits the power dissipated is
minimized for optimum design.
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Figure 1.3a
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1.2 Ideal Logic Elements
Ideal Static and Power Characteristic
• Figure 1.3b shows how voltage levels are
ideally used to represent the input and
output logical 𝟏 and logical 𝟎 states in
digital circuits.
• The logical 𝟏 output voltage is ideally at:
• The power supply voltage 𝑉𝐶𝐶 ·
• The logical 𝟎 output voltage is ideally at:
• Ground (0𝑉).
• Logic gates with output voltage transitions
from ground to the power supply voltage
are said to operate:
rail-to-rail
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Figure 1.3 (b)
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1.2 Ideal Logic Elements
Ideal Static and Power Characteristic
• The transition between output logic states
ideally occurs abruptly at an input of 𝑉𝐶𝐶 /2.
• Thus, logical 𝟎 input is represented by the
voltage range:
0 ≤ 𝑉𝐼𝑁 < 𝑉𝐶𝐶 /2
• An input in this range will generate a logical 1
output state.
• Similarly, logical 𝟏 input is represented by
the voltage range:
𝑉𝐶𝐶 /2 < 𝑉𝐼𝑁 ≤ 𝑉𝐶𝐶
• An input in this range will generate a logical 0
output state.
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Figure 1.3 (b)
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1.2 Ideal Logic Elements
Ideal Static and Power Characteristic
• The input voltage 𝑉𝐼𝑁 = 𝑉𝐶𝐶 /2 has an
undefined output and will cause
unpredictable results (uncertain).
• It is therefore avoided.
• As will be seen in Chapter 23, the CMOS
logic family comes closest to meeting
these ideal static characteristics.
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Figure 1.3 (b)
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1.2 Ideal Logic Elements
Ideal Transient Characteristic
• Figure 1.3c illustrates the transient
response of the ideal logic inverter.
• Upon transition of the input:
from logical 0 to logical 1
• the output without delay, switches from
logical 1 to logical 0.
• (As will be seen in section 1.7 the switching
speed is not instantaneous and a delay between
the output and input transitions is present.)
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Figure 1.3 (c)
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1.2 Ideal Logic Elements
Ideal Input and Output Gate Impedances
• The gate's input and output impedance will
affect:
• The transient response, and
• The driving ability (referred to as fan-out) of
logic gates.
• Figure 1.4a shows a model of the input and
output impedance of a logic inverter.
• The input can be modelled as:
• A parallel resistance and capacitance.
Figure 1.4 (a)
• The output is modelled as:
• Resistance in series with a complemented voltage
source.
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1.2 Ideal Logic Elements
Ideal Input and Output Gate Impedances
• Examining Figure 1.4b, which shows an inverter
driving multiple (identical) logic inverters.
• It is observed that the driving gate must provide enough
output current 𝐼𝑂𝑈𝑇 to drive all the load gates.
• Quantitatively speaking, for 𝑁 load gates, the output
current must be:
′
𝐼𝑂𝑈𝑇 = 𝑁 ∙ 𝐼𝐼𝑁
• where the primed terms of Figure 1.4 refer to the load
gates.
• For a very large input resistance, the input current is
𝑧𝑒𝑟𝑜 and the driving capabilities are maximized.
Figure 1.4 (b)
• Ideally, an infinite input resistance is desired  giving
infinite driving capability.
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1.2 Ideal Logic Elements
Ideal Input and Output Gate Impedances
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Figure 1.4 (b)
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1.2 Ideal Logic Elements
Ideal Input and Output Gate Impedances
• Referring to Figure 1.4c, which shows cascaded inverters with infinite
input resistance, it can be seen that the input capacitance of load gates
must be charged through the output resistance of the driving inverter.
Figure 1.4 (c)
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1.2 Ideal Logic Elements
Ideal Input and Output Gate Impedances
• Thus, a smaller output resistance will provide a larger charging current for
the load capacitance and a faster switching time, suggesting an ideal 𝑧𝑒𝑟𝑜
output resistance.
Figure 1.4 (c)
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1.2 Ideal Logic Elements
Ideal Input Capacitance
• Of course, a smaller input capacitance will also speed up the switching
time of load gates.
• This is provided when fewer gates are attached at the output.
Figure 1.4 (c)
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1.3 Inverter Voltage Transfer Characteristic
• The voltage transfer characteristic
(VTC) for logic inverters have been
standardized.
• Figure 1.5 displays the linearized
form of an idealized VTC.
• Indicated on the output (vertical)
axis are the voltages:
• 𝑉𝑂𝐻 corresponds to the output high
• 𝑉𝑂𝐿 , corresponds to the output low
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Figure 1.5
1.3 Inverter Voltage Transfer Characteristic
• On the input (horizontal) axis:
• The input low voltage is 𝑉𝐼𝐿 ,
• The input high voltage is 𝑉𝐼𝐻 .
• Note that as the input voltage is
increased from 0:
• 𝑉𝐼𝐿 is the maximum input voltage
that provides a high output voltage
(logical 𝟏 output).
• 𝑉𝐼𝐻 has the minimum input voltage
that provides a low output voltage
(logical 0 output).
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Figure 1.5
1.3 Inverter Voltage Transfer Characteristic
• The values 𝑉𝑂𝐻 , 𝑉𝑂𝐿 , 𝑉𝐼𝐿 , and 𝑉𝐼𝐻
are referred to as the critical
voltages of the VTC.
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Figure 1.5
1.3 Inverter Voltage Transfer Characteristic
• It is customary to list output
voltages 𝑉𝑂𝐿 and 𝑉𝑂𝐻 on the input
axis. Why?
• Because these outputs for the
present inverter will be inputs to the
next gate.
• In order that the high and low
voltage
levels
always
be
distinguishable, we must always
have:
𝑉𝑂𝐻 > 𝑉𝐼𝐻
𝑉𝑂𝐿 < 𝑉𝐼𝐿
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Figure 1.5
1.3 Inverter Voltage Transfer Characteristic
• Manufacturers usually specify
worst case values for the four
voltages:
𝑉𝑂𝐻 , 𝑉𝑂𝐿 , 𝑉𝐼𝐻 , 𝑎𝑛𝑑 𝑉𝐼𝐿
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Figure 1.5
1.3 Inverter Voltage Transfer Characteristic
• One final critical point labeled on the
VTC is the midpoint voltage 𝑉𝑀 .
• Sometimes referred to as the threshold
voltage 𝑉𝑡ℎ (not to be confused with the
MOSFET threshold voltage 𝑉𝑇 ).
• It is defined as the point on the transfer
characteristic where 𝑉𝑂𝑈𝑇 = 𝑉𝐼𝑁 .
• Ideally it appears at the center of the
transition region.
• 𝑉𝑀 can be found graphically by:
• Superimposing (the unity slope) 𝑉𝑂𝑈𝑇 =
𝑉𝐼𝑁 and finding its intersection with the
VTC.
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Figure 1.5
1.3 Inverter Voltage Transfer Characteristic
Example 1.1 Voltage Transfer Characteristic Critical Points
• What are the critical voltages
𝑉𝑂𝐻 , 𝑉𝑂𝐿 , 𝑉𝐼𝐻 , 𝑉𝐼𝐿 and 𝑉𝑀 for the
voltage transfer characteristic of
Figure 1.6?
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Figure 1.6
1.3 Inverter Voltage Transfer Characteristic
Example 1.1 Voltage Transfer Characteristic Critical Points
• What are the critical voltages
𝑉𝑂𝐻 , 𝑉𝑂𝐿 , 𝑉𝐼𝐻 , 𝑉𝐼𝐿 and 𝑉𝑀 for the
voltage transfer characteristic of
Figure 1.6?
• Solution:
• The highest and lowest output
voltages are 4.3𝑉 and 0.2𝑉 ,
respectively. Thus:
𝑉𝑂𝐻 = 4.3𝑉
𝑉𝑂𝐿 = 0.2𝑉
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Figure 1.6
1.3 Inverter Voltage Transfer Characteristic
Example 1.1 Voltage Transfer Characteristic Critical Points
• Solution:
• The input voltage at which the
output begins to drop is 0.7𝑉.
• The output reaches its lowest value
at an input of 0.9𝑉.
𝑉𝐼𝐿 = 0.7𝑉
𝑉𝐼𝐻 = 0.9𝑉
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Figure 1.6
1.3 Inverter Voltage Transfer Characteristic
Example 1.1 Voltage Transfer Characteristic Critical Points
• Solution:
• The point on the VTC at which the
input and output are equal is
calculated to be 0.87𝑉.
• The midpoint voltage is therefore:
𝑉𝑀 ≈ 0.9𝑉
• which is far from being ideal.
• Note the output low 𝑉𝑂𝐿 and high 𝑉𝑂𝐻
voltages are labeled on the input axis.
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Figure 1.6
1.4 Logic Swing and Transition Width
• Two important parameters obtained
from voltage differences of VTC
critical voltages are:
1. Logic Swing (output side)
• The magnitude of voltage difference
between the output high and low
voltage levels.
𝑉𝐿𝑆 = 𝑉𝑂𝐻 − 𝑉𝑂𝐿
2. Transition Width (input side)
• The amount of voltage change that is
required of the input voltage to cause a
change in the output voltage from the
high to the low level (or vice-versa).
𝑉𝑇𝑊 = 𝑉𝐼𝐻 − 𝑉𝐼𝐿
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Figure 1.5
1.4 Logic Swing and Transition Width
Example 1.2
• Determine the logic swing and transition
width for the VTC of Figure 1.6.
• Solution:
𝑉𝐿𝑆 = 𝑉𝑂𝐻 − 𝑉𝑂𝐿 = (4.3) − (0.2) = 4.1𝑉
𝑉𝑇𝑊 = 𝑉𝐼𝐻 − 𝑉𝐼𝐿 = (0.9) − (0.7) = 0 .2𝑉
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Figure 1.6
1.5 Noise in Digital Circuits
Noise
• Variations in the steady-state voltage levels of digital circuits (i.e. the
logical 𝟏 and the logical 𝟎 states) are undesirable and cause logic
errors if the fluctuation from the desired or specified voltage levels is
too great.
• This variation of steady state voltage levels in digital circuits is
referred to as voltage level degradation and is termed noise.
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1.5 Noise in Digital Circuits
Noise Margins
• Since variations in the high and low
logic levels occur, terminology is
used
to
describe
these
fluctuations.
• From the idealized inverter VTC of
Figure 1.5, the following definitions
are made:
𝑉𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻 (high noise margin)
𝑉𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿 (low noise margin )
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Figure 1.5
1.5 Noise in Digital Circuits
Noise Margins
• The voltage noise margins represent:
• A safety margin for the high and low
voltage levels.
• Unnecessary noise voltages must
have magnitudes less than the
voltage noise margins.
• The exact magnitudes of the high
and low voltage level is not
important.
• However, the high or low magnitude of
voltage must remain in the range of
voltages that provide positive noise
margins.
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Figure 1.5
1.5 Noise in Digital Circuits
Noise Margins
Image Courtesy:
www. allaboutcircuits.com
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1.5 Noise in Digital Circuits
Noise Sensitivities
• The effects of input variations are
quantified in terms of the noise
sensitivities.
• The high and low noise sensitivities
are defined as the difference
between the input and midpoint
voltage for 𝑉𝐼𝑁 at 𝑉𝑂𝐻 and 𝑉𝑂𝐿
respectively.
• Expressions for each are:
𝑉𝑁𝑆𝐻 = 𝑉𝑂𝐻 − 𝑉𝑀
• And:
𝑉𝑁𝑆𝐿 = 𝑉𝑀 − 𝑉𝑂𝐿
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Figure 1.5
1.5 Noise in Digital Circuits
Noise Immunities
• The quantity noise immunity is:
• The ability of a gate to reject noise.
• The high and low noise immunities
are quantitatively defined as the
quotient of the noise sensitivities
and the logic swing as follows:
𝑉𝑁𝑆𝐻
𝑉𝑁𝐼𝐻 =
𝑉𝐿𝑆
• and
𝑉𝑁𝑆𝐿
𝑉𝑁𝐼𝐿 =
𝑉𝐿𝑆
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Figure 1.5
1.5 Noise in Digital Circuits
Example 1.3
• Determine the noise margins, noise
sensitivities, and noise immunities for
the VTC displayed in Figure 1.6.
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Figure 1.6
1.5 Noise in Digital Circuits
Example 1.3
• Solution By direct substitution the noise margins
are:
𝑉𝑁𝑀𝐻 = (4.3) − (0.9) = 3.4 𝑉
𝑉𝑁𝑀𝐿 = (0.7) − (0.2) = 0.5 𝑉
• Using the results of Examples 1.1 and 1.2, the noise
sensitivities are by direct substitution:
𝑉𝑁𝑆𝐻 = (4.3) − (0.9) = 3.4 𝑉
𝑉𝑁𝑆𝐿 = (0.9) − (0.2) = 0.7 𝑉
• The noise immunities by direct substitution are
then:
3.4
𝑉𝑁𝐼𝐻 =
= 0.83 = 83%
4.1
0.7
𝑉𝑁𝐼𝐿 =
= 0.17 = 17%
4.1
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Figure 1.6
Datasheet Sample
Link
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