VLSI EDA Flow with OpenLane
Chair of Processor Design
Nima Kavand
Chair of
Processor
© Akash
Kumar
Design
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of
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Simplified EDA Flow for ASIC Design
2
HDL file
(.v)
Liberty file
(.lib)
Logic Synthesis Tool
Gate Netlist
(.v)
Liberty file
(.lib)
Verification
Physical Lib.
(.lef)
Physical Synthesis Tool
Physical Layout
(.gds)
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What is OpenLane?
3

OpenLane is an automated RTL to GDSII flow based on several open-source tools like
“abc” and “yosys”
*https://openlane.readthedocs.io/en/latest/flow_overview.html
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OpenLane Design Stages
4













RTL Synthesis, Technology Mapping, and Formal Verification : yosys + abc
Static Timing Analysis: OpenSTA
Floor Planning: init_fp, ioPlacer, pdn and tapcell
Placement: RePLace (Global), Resizer and OpenPhySyn (formerly), and OpenDP (Detailed)
Clock Tree Synthesis: TritonCTS
Fill Insertion: OpenDP/filler_placement
Routing: FastRoute or CU-GR (formerly) and TritonRoute (Detailed) or DR-CU
SPEF Extraction: OpenRCX or SPEF-Extractor (formerly)
GDSII Streaming out: Magic and Klayout
DRC Checks: Magic and Klayout
LVS check: Netgen
Antenna Checks: Magic
Circuit Validity Checker: CVC
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First Example
5
Start the Virtual Machine
 Open terminal and enable OpenLane environment:

 > Source /nfs/ehsd24/openlane/setting.sh
◼ This command also provides a local copy of “openlane” folder

Run an existing example:
 > cd openlane
 > ./flow.tcl –design spm
◼ In general: ./flow.tcl –design <design_name>
◼ This script does the whole flow and generates the final layout from HDL codes.
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First Example (Cont.)
6

The configuration of each design is in the
“OpenLane/designs/<design_name>/config.json”
 This file defines the parameters like
◼ CLOCK_PORT, CLOCK_PERIOD, SYNTH_STRATEGY, DIE_AREA, etc.

After synthesis, the folder “runs” will be created:
 “OpenLane/designs/<design_name>/runs/”
 This folder contains all the logs, reports, and results of each stage
 Check the content of this folder
 You can find an overall report in:
◼
“OpenLane/designs/<design_name>/runs/reports/metrics.csv”
◼ You can find the datapoint definitions here.
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Viewing Layouts: OpenRoad GUI
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
> python3 gui.py --viewer openroad ./designs/<design_name>/runs/RUN_*
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Viewing Layouts: KLayout
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
> python3 gui.py --viewer klayout ./designs/<design_name>/runs/RUN_*
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Viewing layouts: Options
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Argument
Description
--viewer <viewer>
(Optional)
The layout viewer (tool) to display the layout. Available viewers are openroad & klayout.
Default: Openroad.
Example: > python3 gui.py --viewer openroad ./designs/spm/runs/RUN_*
--stage <stage>
(Optional)
The flow stage to fetch the layout from. cts, floorplan, placement, routing and signoff.
Default: Latest layout produced by the flow.
Example: > python3 gui.py --viewer openroad --stage floorplan
./designs/spm/runs/RUN_*
--format <layout_format>
(Optional)
The layout format to use. Available formats are gds, def and odb. odb is only supported
by OpenROAD and gds is only supported by KLayout.
Default: odb for OpenROAD, gds for KLayout.
Example: > python3 gui.py --format def --viewer openroad --stage floorplan
./designs/spm/runs/RUN_*
Exercise: Open and compare the layouts of a design after each stage.
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OpenRoad GUI: Display Control
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
You can select the color/visibility/selectability of the:
 Layers, Nets, Instances, Blockages, rulers, etc.
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OpenRoad GUI: Heat Map
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
You can check the placement and power density, routing congestion,
and IR drop
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OpenRoad GUI: Heat Map (Options)
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
Double-click on a Heat map (e.g., Power Density) to see available options
 For example you can change the grid size for the power density map.
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OpenRoad GUI: Inspector
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
To see the information of each object (instance or net)
1) Select that object in the layout
 2) See the information in the Inspector bar
 3) You can also find the object using Find option (next slide)

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OpenRoad GUI: Find option
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
To find an object (Instance/Net/Port) in the layout
 Select “View -> Find” from the menu
 Or press “Crtl+F”
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OpenRoad GUI: Deselect an Object
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
Right click on the selected object to see options, then click on a “clear”
option
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OpenRoad GUI: Route Guides
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
To have a better visibility of a net
 Select the target net in the layout
 Click on Route Guides
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OpenRoad GUI: Walkthrough a Netlist
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
You can trace the netlist using blue lines in the Inspector
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OpenRoad GUI: Power Grid
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OpenRoad GUI: Clock Tree
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
You have two options to see the clock tree:
 Select “Clock” in the display control and deselect other objects
 Using “Windows->Clock Tree Viewer” from menu (More details are available)
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OpenRoad GUI: Timing Report
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OpenRoad GUI: Hierarchy Browser
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
To see the hierarchy of a design
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OpenRoad GUI: Ruler
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Find “Tools->Ruler” from the menu
 Measure the target part in the layout by clicking on start and end
points

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OpenRoad GUI: Adding a Button
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
To add a button with desired function enter this command:

>create_toolbar_button –text ‘<name>’ –script {<function>}
◼
Example: >create_toolbar_button –text ‘Hello’ –script {puts “Hello World!”}
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OpenRoad GUI: Reports
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
Enter these commands in the OpenRoad’s command line and see the result:
 report_design_area
 report_power
 report_worst_slack
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Adding a New Design
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
You can create a new design with a default configuration file “config.json” (or “config.tcl”)
 With JSON configuration file (default)
◼ ./flow.tcl –design <design_name> -init_design_config –add_to_designs
 With TCL configuration file
◼ ./flow.tcl –design <design_name> -init_design_config –add_to_designs –config_file config.tcl
 With Configuration file + Verilog (source) files
◼ ./flow.tcl –design <design_name> -init_design_config –add_to_designs –src “<list_verilog_files>”
◼ Note: You can also copy the Verilog files manually in “/OpenLane/designs/<design_name>/src/”, but
then you should modify the configuration file accordingly.

Now you can synthesis this design with the described commands.
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Adding a New Design: Configuration File
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You can edit the configuration file based on the requirements
 This file should at least contain these variables:

 DESIGN_NAME
 VERILOG_FILES
 CLOCK_PORT
 CLOCK_PERIOD
 FP_PDN_MULTILAYER (You may leave it empty if true)

Some of the most important variables are described in the following slides.
 Complete list: https://openlane.readthedocs.io/en/latest/reference/configuration.html
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Configuration Variables: General
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Variable
Description
DESIGN_NAME
The name of the top level module of the design
VERILOG_FILES
The path of the design’s Verilog files, provided as an array of files in JSON
or a whitespace-delimited list of files in Tcl. The files are evaluated in order,
i.e., if file B depends on file A, file A must be listed first.
CLOCK_PERIOD
The clock period used for clocks in the design, in nanoseconds.
CLOCK_PORT
The name of the design’s clock port.
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Configuration Variables: Synthesis
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Variable
SYNTH_STRATEGY
Description
Strategies for abc logic synthesis and technology mapping
Possible values are DELAY/AREA 0-4/0-3; the first part refers to the optimization
target of the synthesis strategy (area vs. delay) and the second one is an index.
(Default: AREA 0)
A flag that disables flattening the hierarchy during synthesis, only flattening it after
synthesis, mapping and optimizations.
SYNTH_NO_FLAT
Enabled = 1, Disabled = 0
(Default: 0)
Deprecated: Use the PDK’s MAX_FANOUT_CONSTRAINT value: The max load that
SYNTH_MAX_FANOUT
the output ports can drive.
Deprecated: Use the PDK’s MAX_TRANSITION_CONSTRAINT value: The max
SYNTH_MAX_TRAN
transition time (slew) from high to low or low to high on cell inputs in ns. If unset, the
library’s default maximum transition time will be used.
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Configuration Variables: Floorplan
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Variable
Description
FP_CORE_UTIL
The core utilization percentage.
(Default: 50 percent)
FP_ASPECT_RATIO
The core’s aspect ratio (height / width).
(Default: 1)
FP_SIZING
Whether to use relative sizing by making use of FP_CORE_UTIL or absolute one using
DIE_AREA.
(Default: "relative" - accepts "absolute" as well)
DIE_AREA
Specific die area to be used in floorplanning when FP_SIZING is set to absolute. Specified as
a 4-corner rectangle “x0 y0 x1 y1”. Units in μm
(Default: unset)
CORE_AREA
Specific core area (i.e. die area minus margins) to be used in floorplanning when FP_SIZING is
set to absolute. Specified as a 4-corner rectangle “x0 y0 x1 y1”. Units in μm
(Default: unset)
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Configuration Variables: Floorplan (cont.)
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Variable
Description
FP_PDN_CORE_RING
Enables adding a core ring around the design. More details on the control variables in the
pdk configurations documentation. 1 = Enabled, 0 = Disabled.
(Default: 0)
FP_PDN_MULTILAYER
Controls the layers used in the power grid. If set to 0 (Tcl)/false (JSON), only the lower,
vertical layer will be used, which is useful when hardening a macro for integrating into a
larger top-level design.
(Default: 1)
DESIGN_IS_CORE
Deprecated as even macros can have a full-stack PDN if core rings are used: New
variable is FP_PDN_MULTILAYER Controls the layers used in the power grid. Depending
on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is
a Macro
(Default: 1)
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Configuration Variables: Placement
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Variable
Description
PL_TARGET_DENSITY
The desired placement density of cells. It reflects how spread the cells would be on the
core area. 1 = closely dense. 0 = widely spread
(Default: ($::env(FP_CORE_UTIL) + 10 + (5 * $::env(GPL_CELL_PADDING)) ) / 100.0)
PL_BASIC_PLACEMENT
Specifies whether the placer should run basic placement. Basic placement is used for
extremely simple, low-density designs of only a few dozens of gates, and should be
disabled for most designs. 0 = false, 1 = true
(Default: 0)
PL_SKIP_INITIAL_PLACEMENT
Specifies whether the placer should run initial placement or not. 0 = false, 1 = true
(Default: 0)
PL_RANDOM_GLB_PLACEMENT
Specifies whether the placer should run random placement or not. This is useful if the
design is tiny (less than 100 cells). 0 = false, 1 = true
(Default: 0)
PL_RANDOM_INITIAL_PLACEMENT
Specifies whether the placer should run random placement or not followed by replace’s
initial placement. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true
Chair of
(Default: 0)
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Configuration Variables: Routing
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Variable
ROUTING_CORES
Description
Specifies the number of threads to be used in TritonRoute. Can be overriden
via environment variable.
(Default: 2)
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Synthesis Options
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
You can use different synthesis strategies to optimize the design in terms of Area/Delay

Before synthesis, you can select one of the existing strategies by changing

“SYNTH_STRATEGY”: “<strategy>” In “/OpenLane/designs/<design_name>/config.json”
Possible strategies: “AREA 0-3”, “DELAY 0-4”
◼ Usually lower value results in better optimization
◼


Run the flow with different strategies and compare the results.
You can also explore different strategies by this command:
>./flow.tcl –design <design_name> -synth_explore
 You can check the results in:

◼

“/OpenLane/designs/<design_name>/runs/RUN_*/reports/synthesis/0-exploration_analysis.html”
Default configuration:

“/OpenLane/configurations/synthesis.tcl”
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Synthesis Options (Behind the Scene)
34

The synthesis strategy selects one of the defined strategies in:
 “/OpenLane/scripts/yosys/synth.tcl”
 There are two lists in the file for delay- or area-based strategies
◼ Set delay_scripts [list “…” “…” “…” “…” “…”]
◼ Set area_scripts [list “…” “…” “…” “…”]
 You can change the scripts and define your strategy based on the things that
you learned in previous sessions.
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Regression and Exploration (Multiple Run)
35
“run_design.py” is a script to do multiple runs in parallel using different
configurations
 It can be used for:

 Running one or more designs
◼ > python3 run_designs.py --threads <#threads> <design1> <design2> <design3>…
◼
e.g.: > python3 run_designs.py --threads 2 spm xtea
 An exploration run of a design with different configurations
◼ > python3 run_designs.py --matrix ./designs/ci/wbqspiflash/matrix.json --threads 4 wbqspiflash
◼ The parameters should be provided in matrix.json file.

Help?
 > python3 ./run_designs.py --help
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Regression and Exploration: a Matrix.json File Example
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Regression and Exploration: Output
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
In addition to files produced inside ./designs/<design>/runs/config_<tag>_<timestamp>:
 regression_results/<tag>_<timestamp>/<tag>_<timestamp>.log
◼ A log file that describes start and stopping time of a given run.

regression_results/<tag>_<timestamp>/<tag>_<timestamp>.csv
◼
A report file that provides a summary of each run. The summary contains some metrics and the configuration of that run.
 regression_results/<tag>_<timestamp>/<tag>_<timestamp>_best.csv
◼
A report file that selects the best configuration per design based on number of violations
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Interactive Mode
38

To have more control over the flow, you can run it interactively using
the option -interactive.
 This allows you to add intermediate commands between the stages to gain
the desired functionality.
 Run interactive mode:
◼ > ./flow.tcl –interactive
 In the opend tcl shell:
◼ package require openlane
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Interactive Mode: Commands
39

These are the main commands of the flow
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
❑
prep -design <design> [-tag TAG] [-config CONFIG] [-init_design_config] [-overwrite]
run_synthesis
run_floorplan
run_placement
run_cts
run_routing
write_powered_verilog followed by set_netlist
$::env(routing_logs)/$::env(DESIGN_NAME).powered.v
run_magic
run_magic_spice_export
run_magic_drc
run_lvs
run_antenna_check
The Comprehensive list of supported commands: here
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Important “./flow.tcl” Arguments
40
Argument
Description
-design <folder path>
(Optional)
TSpecifies the design folder. A design folder should contain a config.json or config.tcl file
defining the design parameters.
If the folder is not found, ./designs directory is searched, and if this parameter is omitted,
the current working directory is treated as the design.
-config_file <file>
(Optional)
Specifies the design’s configuration file for running the flow.
For example, to run the flow using ./designs/spm/config2.tcl
Use run ./flow.tcl -design ./designs/spm -config_file ./designs/spm/config2.tcl
By default config.tcl is used, and if not found, config.json is used instead.
-tag <name>
(Optional)
Specifies a “name” for a specific run. If the tag is not specified, a timestamp is generated
for identification of that run.
-src <verilog_source_file>
(Optional)
Sets the verilog source code file(s) in case of using -init\_design\_config.
The default is that the source code files are under design_path/src/, where the design
path is the one passed to -design
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Important “./flow.tcl” Arguments (Cont.)
41
Argument
Description
-init_design_config
(Optional)
Creates a configuration file for a design. The config file is by default
openlane/config.json, but can be overriden using the value from -config_file.
-add_to_designs
(Optional)
Adds the design to the OpenLane folder instead of creating an openlane folder. This is the
default behavior on earlier versions of OpenLane.
-overwrite
(Optional)
Flag to overwrite an existing run with the same tag
-interactive
(Optional)
Flag to run openlane flow in interactive mode
-synth_explore
(Boolean)
If enabled, synthesis exploration will be run (only synthesis exploration), which will try out
the available synthesis strategies against the input design. The output will be the four
possible gate level netlists under <run_path/results/synthesis> and a summary report
under reports that compares the 4 outputs.
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Do You Need More Information?
42

https://github.com/The-OpenROAD-Project/OpenLane

https://openlane.readthedocs.io/en/latest/
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