FABRICATION OF MICROELECTRONIC DEVICES
Dr.-Ing. Rastee D. Ali
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Figure 36.4 Allowable particle size counts for different clean room classes.
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SPINNING OF ORGANIC COATING ON WAFER
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PATTERN TRANSFER BY PHOTOLITHOGRAPHY
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PN-JUNCTION
DIODE
FABRICATION
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THERMOSONIC WELDING OF GOLD WIRES
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IC PACKAGES
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Figure 28.27
Schematic
illustration of
various IC packages:
(a) dual-in-line
package (DIP); (b)
flat, ceramic
package; (c)
common surfacemount
configurations; (d)
ball-grid arrays.
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