IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 3, MARCH 2019
535
A Generic Power Management Circuit for Energy
Harvesters With Shared Components Between
the MPPT and Regulator
Gaurav Saini
and Maryam Shojaei Baghini, Senior Member, IEEE
Abstract— This paper presents a novel power management
circuit (PMC) for harvesting the energy from the ambient.
The proposed PMC comprises an energy harvester, a startup,
a dc–dc boost converter, and a dc–dc buck converter. The PMC
is capable of working with various low-power energy harvesters
and can track the maximum power point after every 4.5 s. To
achieve the maximum power point tracking (MPPT), an opencircuit-voltage-based method is used to transfer the maximum
power from the energy harvester to the power optimized boost
converter. The proposed MPPT scheme works for a wide range
of equivalent source resistance of the energy harvester in the
range of 20 –1 M. An auxiliary energy harvester is used
for the startup to avoid any external supply. Regulated voltage
across a load is provided by the buck converter which features
sharing the switches and inductor with the boost converter.
The complete circuit is designed, optimized, and simulated in
180-nm mixed-mode CMOS technology using three different
types of energy harvesters, which are precisely characterized and
modeled. Post-layout simulated results are presented for the input
power ranging from 150 nW to 500 μW for different values of
source resistances ranging from 20 to 1 M. For a source
resistance of 100 k, the efficiency of the boost converter is
39.91% and 89.91% at available power of 156 nW and 2.5 μW,
respectively. The buck converter is able to regulate the load
voltage to 1 V across the load resistance ranging from 100 to 2 k.
Index Terms— Battery-less system, boost converter, buck converter, maximum power point tracking (MPPT), power management circuit (PMC), radio frequency (RF) energy harvesting,
shared inductor, solar energy harvesting, synchronous rectification, vibration energy harvesting, wireless sensor nodes.
I. I NTRODUCTION
E
NERGY harvesting systems are used to charge handheld electronic devices and wireless sensor nodes, where
the system is in standby for most of the time and then
transmit/receive/process in short bursts of time [1]. Energy
harvester takes the energy from the ambient and stores it
on storage element, for example, a low-leakage capacitor or
Manuscript received August 2, 2018; revised October 26, 2018; accepted
November 27, 2018. Date of publication January 1, 2019; date of current
version February 22, 2019. This work was supported by MeitY, Government
of India through Chip-to-System Program (C2S). (Corresponding author:
Gaurav Saini.)
The authors are with the Department of Electrical Engineering, IIT Bombay,
Mumbai 400076, India (e-mail: gauraviec2010@gmail.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2018.2885928
a battery. The sources of energy in the ambient are radio frequencies (RFs), vibrations, and light. For storing the harvested
energy in a capacitor, a power management circuit (PMC) is
required which dissipates minimal power by itself. Since the
energy harvested from ambient sources is very low, the PMC
should work at low power and low voltage. Due to advances
in CMOS technology, low-power low-voltage CMOS circuits
can be designed. To make the system completely battery-less,
a startup circuit is also required.
Different power management techniques are reported in the
literature. In [2], a battery-less PMC requires only vibrations
for startup which limits its application. A transformer reuse
boost converter is designed in [3], but it needs an external
power supply. An integrated CMOS RF energy harvester with
impedance matching between the antenna and the rectifier is
reported in [4], but maximum power point tracking (MPPT)
is not used after the rectifier. Therefore, the efficiency of
the whole system is 40% at −11-dBm power received by
an antenna. A 300-nW sensitive dc–dc converter is designed
in [5], but it needs an external supply for startup. A batteryless RF energy harvesting system is reported in [6] and [7]
using the open-circuit-voltage (OCV)-based method and the
resistance emulation method as MPPT between the rectifier
and the boost converter. A boost converter is designed based on
the equation of its operation in the discontinuous conduction
mode in [8] and the overall power conversion efficiency
achieved is 44.1% at −12-dBm power received by an antenna.
A boost converter is designed with the peak inductor current
control method in [9] and the minimum input voltage that
can be harvested is 20 mV. An inductor sharing between the
buck converter and the boost converter is discussed in [10]
for piezo-electric energy harvesting application. A discrete
component-based system is designed in [11] using a resistor
emulation approach for RF energy harvesting application. The
focus in this paper is low-power energy harvesting in the order
of 100-nW range. At those input power levels, the losses in the
boost converter become comparable with the input power from
the energy harvester. Therefore, the boost converter is designed
to consume minimum power by modulating its switching frequency with respect to input power from the energy harvester.
The aforementioned energy harvesting systems [2]–[11] have
no control on the losses in the boost converter. The boost
converter is designed to consume minimum power in [12], but
the system needs relatively high power (500 nW) and relatively
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high voltage (1.3 V) to start. The following issues need to be
addressed in any energy harvesting system:
1) maximum power transfer from the energy source into
the PMC;
2) minimum power loss in the PMC;
3) no reverse flow of the power from the storage element
to the source.
In this paper, OCV-based MPPT is used between the energy
source and the boost converter. The input voltage of the boost
converter is maintained at some fraction of the OCV of the
energy source. This fraction is 45%–55% for an RF and
piezo energy harvester [12] and 75%–85% for a solar energy
harvester [13]. For providing a regulated voltage across the
load, the buck converter is designed. Switches and inductor are
shared between the boost converter and the buck converter. The
startup is used for providing the initial voltage and power to the
PMC so that the boost converter can start function. The MPPT
works for the wide range of source resistance and the boost
converter efficiency increases as source resistance increases.
Section II describes the different types of energy harvester.
Section III describes the overview of the proposed PMC. Optimization and timing control are discussed in Section IV. The
results and conclusion are described in Sections V and VI.
Fig. 1. (a) Schematic of the rectenna. M1ZVT_Thick and M2ZVT_Thick are
zero-threshold voltage (Vt ) thick oxide transistors. (b) Rectenna characteristics
with respect to the load voltage (Vload ).
II. D IFFERENT T YPES OF E NERGY H ARVESTER
A. RF Energy Harvester
The antenna is the front-end module for any RF energy harvester and used with matching network and rectifier, as shown
in Fig. 1(a). The entire circuit is called a rectenna. We use
one of the rectennas reported in [4] for the demonstration
of the proposed power management system. Zero-threshold
voltage (Vt ) thick oxide MOS transistors are used as a diodeconnected transistor in the design of the rectifier. The effective
impedance of the rectifier is found by taking the discrete
Fourier transform (DFT) of the voltage and current at the
input node of the rectifier at fundamental frequency (here,
950 MHz) for the received power of −30 dBm. From the
DFT, real and imaginary parts of the voltage and current are
found and their ratio gives the complex impedance. An L-type
matching network is designed between the antenna and the
rectifier for maximum power transfer into the input of rectifier,
as shown in Fig. 1(a). Energy conversion profile of the rectenna
is shown in Fig. 1(b) for various power values (Prf ) received
by the antenna at 950 MHz [6]. From the characteristics, it is
observed that the rectenna output power (Pavl ) is maximum at
the load voltage (Vload ), which is around half of the OCV.
The rectenna used in Fig. 1(a) is followed by a boost
converter such that the input voltage of the boost converter
is 45%–55% of the OCV of the rectenna [5]. Switching
frequency of the boost converter is very low as compared to
the input signal frequency. Hence, the rectenna is replaced by
its dc equivalent circuit so that simulation time is significantly
reduced [6].
Fig. 2.
Piezoelectric transducer and its electrical equivalent.
under mechanical vibration. I p is the piezoelectric current,
which depends on the magnitude of vibration. C p and R p are
dielectric capacitance and resistance of the transducer, respectively. Fig. 3(a) shows the piezoelectric harvester that consists
of a piezoelectric transducer followed by a two-stage rectifier.
For maximizing the efficiency of the piezo energy harvester,
its energy conversion characteristic is needed. Fig. 3(b) shows
one of the example setups we have prepared to characterize
the piezo energy harvester.
A pure sinusoidal sound vibration is generated in the laptop
using Audacity software [14] and given to a speaker. The
speaker diaphragm also vibrates with the same sinusoidal
frequency. The piezoelectric transducer and the accelerometer
IC (ADXL316) are attached to the diaphragm with the help of
adhesive, and hence, they also vibrate with the same frequency
as diaphragm. Accelerometer IC measures the acceleration
of the diaphragm. Digital multimeter is used to measure the
output voltage of the rectifier for variable resistance Rload
connected at the output of a rectifier. Fig. 3(c) shows the measured output power (Pavl ) with respect to the output voltage
of the rectifier for different mechanical vibration levels. The
characteristic shows that the output power is maximum around
half of the OCV for the corresponding acceleration.
B. Piezoelectric Energy Harvester
C. Indoor Light Energy Harvester
Fig. 2 shows the equivalent electrical model of a piezoelectric transducer [10]. These transducers generate ac power
Photovoltaic (PV) cell is used to harvest indoor light
energy [15], [16]. PV cell is a p-n junction diode in which
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SAINI AND BAGHINI: GENERIC PMC FOR ENERGY HARVESTERS WITH SHARED COMPONENTS
537
Fig. 4. (a) PV cell and its electrical equivalent. (b) Measured characteristics
of 4-cm2 reference silicon PV cell.
Fig. 3.
(a) Piezoelectric transducer followed by rectifier and load.
(b) Measurement setup for finding the characteristics of a piezoelectric
harvester. (c) Characteristics of a piezoelectric energy harvester.
n-type side is illuminated and the exited electrons flow through
a load, as shown in Fig. 4(a). For maximizing the efficiency of
PV cell, its energy conversion characteristic is needed under
different illumination conditions [13]. Fig. 4(b) shows the
measured characteristics for 4-cm2 RERA silicon PV cell [17],
tested in lab using ABET solar simulator (class AAA) instrument [18]. The characteristic shows that maximum output
power (Pavl ) occurs at 75%–85% of the OCV for a relatively
wide range of the input power.
III. OVERVIEW OF THE P ROPOSED P OWER
M ANAGEMENT C IRCUIT
The basic schematic of the proposed PMC for energy
harvesting is shown in Fig. 5. The equivalent circuit of all
types of energy harvesters is represented by a finite power
source modeled by a voltage source Vs in series with resistance
Rs and both in parallel with Cs . The startup is an auxiliary
energy harvester which will build up the storage voltage Vsto
up to 800 mV for the control circuit in the PMC to work.
As shown in Fig. 5, the proposed PMC also constitutes
voltage monitor circuits which monitor Vsto . One of them indicates, when Vsto crosses 800 mV, that energy can be harvested
from the main source, and the boost converter will be enabled.
The boost converter has one inductor L 1 and two switches M N
and M P , as shown in Fig. 5. For MPPT operation, the boost
converter maintains its input voltage Vemu as a fraction (α) of
the open circuit output voltage (Vs ) of the energy harvester.
The control circuit of the boost converter controls the switches
M N and M P . The storage capacitor Csto is further charged by
the boost converter until Vsto reaches 1.8 V. At that moment,
another voltage monitor circuit provides an indication to the
buck converter for providing a constant voltage of 1 V across
load resistance R L .
The buck converter uses the same inductor and switches as
used by the boost converter, as shown in Fig. 5. Input to the
buck converter is voltage Vsto and the supply for its control
circuit is provided by VDD_BUCK. Since the buck converter
takes energy from the capacitor Csto , voltage Vsto will decrease
until it reaches to 1 V, and the boost converter is again enabled.
There is a need of multiplexer circuit which will select the
corresponding control signals depending on whether a boost
converter or a buck converter is operational, as shown in Fig. 5.
This is done by MUX 1 and MUX 2 with the select signal as
the output of a voltage monitor circuit, as shown in Fig. 5.
A. Startup Operation and Voltage Monitor Circuits
In the beginning of the energy harvesting process, there
is no initial charge on Csto , as shown in Fig. 5, and hence,
all the signals in the PMC are LOW. One way of charging
Csto is using an auxiliary piezo energy harvester similar to the
harvester shown in Fig. 3(a). There is a pMOS switch (MPST )
connected between the auxiliary piezo energy harvester output
(Vout) and the capacitor Csto . MPST is controlled by the signal
PMBC , which is LOW until Vsto reaches around 800 mV.
Therefore, MPST is on during the startup phase, and hence,
Csto is charged by the auxiliary piezo energy harvester. The
maximum current consumed by the entire control circuit
during the startup is only 14 nA, which does not load the
auxiliary energy harvester much. From Fig. 3(c), it is observed
that for an acceleration of more than 3.5 g, the OCV is more
than 800 mV. Similarly, from Fig. 1(b), the considered RF
energy harvester with minimum available power of around
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538
Fig. 5.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 3, MARCH 2019
Basic schematic of the proposed PMC.
Fig. 6.
Voltage monitor circuits. (a) Voltage reference generator.
(b) Comparison of fraction of Vsto with Vref1 to generate PMBC .
(c) Comparison of fraction of Vsto with Vref2 to generate PL and PL .
−22 dBm may be used for the startup. When Vsto reaches
around 800 mV, signal PMBC goes HIGH and turns off switch
MPST .
Fig. 6 shows the voltage monitor circuit used for enabling
either the boost converter or the buck converter depending
on Vsto. Fig. 6(a) shows a voltage reference generator, which
generates Vref1 (≈240 mV) and Vref2 (≈480 mV) voltage
references [12], [19]. For reducing the current consumption of
the reference generator, gate and source of low-Vt transistor
MPLVT are shorted so that it will operate in subthreshold
region. The current flowing in MPLVT is independent of supply
Vsto . This current is passed through regular-Vt transistors
MPRVT1 and MPRVT2. The positive temperature coefficient of
the difference in threshold voltage of MPRVT1 and MPLVT
is balanced by the negative temperature coefficient produced
by the different sizing of transistors MPRVT1 and MPLVT to
produce temperature-independent voltage references. The size
of MPLVT is 2.5/50 μm and the size of both MPRVT1 and
MPRVT2 are 6/50 μm.
Fig. 7. Simulation results of the control operation by the voltage monitor
circuits of Fig. 6. (a) Signal PMBC goes HIGH when Vsto reaches 800 mV.
(b) Signal PL goes HIGH when Vsto reaches 1.8 V.
Voltage monitor circuits, shown in Fig. 6(b) or 6(c), are
required to monitor Vsto. Fig. 6(b) shows a hysteritic comparator [20] which compares a fraction (Vfr1 ) of Vsto with
Vref1 and generates the control signal PMBC which disables the
startup and enables the boost converter, whose simulated result
is shown in Fig. 7(a). Comparator COMP1 has a hysteresis
of around 200 mV. Fig. 6(c) shows another voltage monitor
circuit which makes PL go HIGH, as shown in Fig. 7(b), when
Vsto reaches 1.8 V to disable the boost converter and enable
the buck converter. Comparator COMP2 has a hysteresis of
around 800 mV.
B. DC–DC Boost Converter for MPPT
The dc–dc boost converter is used at the output of the
rectifier in the case of RF and piezo energy harvesters and
at the output of the solar cell in the case of solar energy
harvester, as shown in Fig. 8. The input voltage (Vemu ) of the
boost converter is maintained at a fraction (α) of the OCV (Vs )
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SAINI AND BAGHINI: GENERIC PMC FOR ENERGY HARVESTERS WITH SHARED COMPONENTS
539
Fig. 8. Energy harvester followed by a first storage capacitor Cpool and a boost converter. CggMN , CddMN , CssMP , and CggMP are the parasitic capacitances
associated with the boost converter. PEMU and PSR signals are generated by the control circuit.
of the respective energy harvester [5] for MPPT. Pavl (Vs2 /4Rs
for α = 0.5) is the maximum power that can be harvested from
the energy harvester and provided in the boost converter. Cpool
( Cs ) is a large capacitor connected between the harvester
and the boost converter to act as the first storage element.
The boost converter optimally transfers the energy from Cpool
to Csto and also boosts its input voltage Vemu . Cpool should
be large enough so that the ripple in voltage Vemu is kept
less than 10% of Vemu during the MPPT. The boost converter
switches are controlled by signals PEMU and PSR . PEMU helps
to achieve the MPPT at the input of the boost converter. PSR
helps in achieving the synchronous rectification in the boost
converter so that there is no reverse flow of current from Csto
to the energy harvester. The control circuits for the generation
of PEMU and PSR signals are powered by Vsto .
Fig. 9. Vemu is the input voltage of the boost converter. PEMU and PSR
signals controlling the switches of the boost converter and the inductor current
flowing in the boost converter.
B. Power Loss Calculation of the Boost Converter
C. DC–DC Buck Converter for Regulating the Output Voltage
Once the voltage Vsto reaches 1.8 V, the buck converter starts
working to provide a constant supply across the load, as shown
by resistor R L in Fig. 5. The buck converter is designed to
operate at the boundary of continuous conduction mode and
discontinuous conduction mode. For minimizing the number
of external components and the size of the circuit, inductor
and switches are shared between the boost converter and the
buck converter.
Energy dissipation in the boost converter is in two forms:
ohmic loss and switching loss [21].
1) Ohmic Loss Calculation: In Fig. 9, during 0 < t < D1 T ,
M N is on, and the energy is stored in the inductor L 1 . The
corresponding circuit diagram is shown in Fig. 10(a). Inductor
current i 1 will dissipate power PR1 in the dc series resistance
(Rind) of L 1 , ON resistance (R N ) of M N , and equivalent series
resistance (RC ) of Cpool , as given by
v emu
t
L1
d E R1
= i 12 R1 .
PR1 =
dt
i1 =
IV. O PTIMIZATION AND T IMING C ONTROL
For implementing the MPPT and synchronous rectification
technique, analysis of the boost converter is required. First,
the input resistance of the boost converter is calculated for
the discontinuous conduction mode [7]. After that, the power
loss in the boost converter is minimized, which gives the time
period and duty cycle of the signal PEMU and their dependence
on the boost ratio (B R = Vsto/Vemu ). Finally, the design of the
circuit realizing PEMU and PSR is presented.
A. Input Resistance of the Boost Converter
Fig. 9 shows the timing diagram of the PEMU and PSR
signals controlling the switches and the inductor current (i 1 )
of the boost converter. D1 and T are the duty cycle and time
period of PEMU signal. The input resistance Remu of the boost
converter is given by the following equation [7]:
1
Vemu
2L 1
1
−
.
(1)
Remu =
=
(D1 )2 T
BR
(i 1 )
(2)
(3)
In (3), R1 = Rind + R N + RC . Total loss (E R1 ) during this
time is calculated by integrating (3) and is given in
1
E R1 =
3
Vemu
L1
2
R1 (D1 T )3 .
(4)
Duty cycle D1 from (1) is substituted in (4) and the final
expression for E R1 during inductor energizing is given by
E R1 =
1
3
Vemu
L1
2
3
T2
2L 1
Remu
3
2
1
R1 .
1−
BR
(5)
In Fig. 9, during D1 T < t < (D1 + D2 )T , M N is off and
M P is on and the stored energy in L 1 is transferred to Csto ,
as shown in Fig. 10(b). Inductor current and power dissipated
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 3, MARCH 2019
Fig. 10. (a) Energy is stored in the inductor from the Cpool capacitor.
(b) Energy is transferred from the inductor to Csto . RC , Rind , R N , and R P
are series resistances associated with Cpool , L 1 , M N , and M P .
during this period is given by
v emu − Vsto
i 1 = i 1max −
(6)
(D1 T − t)
L1
d E R2
= i 12 R2 .
(7)
PR2 =
dt
Vsto is almost constant because of large value of Csto .
In (7), R2 = Rind + R P + RC , where R P is on resistance
of M P . The final expression for E R2 is given by
3 2
1 Vemu 2 3 2L 1
1
R2
E R2 =
T2
1−
. (8)
3
L1
Remu
BR
BR − 1
The average power loss PR = (E R1 + E R2 )/T is given by
3 2
1
1 Vemu 2 √
2L 1
R2
.
1−
R1 +
PR =
T
3 L1
Remu
BR
BR − 1
(9)
2) Switching Loss: The total effective capacitance
(Ceff ) will be the sum of all the parasitic capacitances
(CggM , Cdd M N , CggM , and CssM P ), as shown in Fig. 8. The
N
P
total switching loss is given by
2 1
PS W = Ceff Vsto
.
(10)
T
3) Minimizing Total Loss: Total power loss (Ploss ) in the
boost converter is given by the addition of (9) and (10).
With the increase in the switching time period T , ohmic loss
increases while switching loss decreases. The expression of T
at which the total loss is minimum is found by differentiating
Ploss with respect to T and is given by
⎞2
⎛
Fig. 11. Optimal power loss normalized with respect to available power and
plotted for different sizes of NMOS and PMOS switches.
C. MPPT Implementation by the Boost Converter
Maximum power needs to be harvested from the energy
harvester by the boost converter controlled by signals PEMU
and PSR , as shown in Fig. 8. Time period Topt of PEMU
signal helps in minimizing the loss in the boost converter.
(D1 T )opt is the ON time for M N and helps in achieving the
MPPT between the energy harvester and the boost converter.
(D2 T )opt is the ON time for M P and helps to stop the reverse
flow of energy from Csto to Cpool . Input voltage (Vemu ) of
the boost converter is compared with the reference voltage
(Vref = α × Vs ) using hysteritic comparator COMP3 [20].
The value of α lies between 0.45 and 0.55 for the RF and
piezo energy harvester and 0.75 and 0.85 for the solar energy
harvester. As soon as Vemu is more than Vref , M N is turned
on with the help of NMOS control circuit. The time duration
for which M N is on is given by (12). After M N is turned off,
M P is turned on and its ON time is given by (13).
Clearly, Topt ∝ (B R )(4/3), (D1 T )opt ∝ (B R )(2/3), and
(D2 T )opt ∝ ((B R )(2/3)/B R − 1). It is not easy to generate
these signals and hence, for simplicity, some approximations
are considered, which are given as Topt ∝ (B R )2 , (D1 T )opt ∝
B R , and (D2 T )opt ∝ (B R /B R − 1). Based on these approximations, the approximate relations for Topt, (D1 T )opt, and
(D2 T )opt are given by
⎟
6Ceff B R2 L 21
⎟
3 ⎠ .
2
B R −1
2L 1
R2
R1 + B R −1
Remu
BR
(11)
(D1 T )opt =
Substituting Topt in (1), (D1 T )opt can be found, which is given
by
(D1 T )opt =
6Ceff B R2 L 21
2
R1 + B RR−1
1
3
.
(12)
In addition, the time duration for which M P is on is given
by [D2 T = (D1 T )/(B R − 1)] [7] and finally is given
by
(D2 T )opt =
6Ceff L 21
2
R1 + B RR−1
1
3
2
B R3
.
BR − 1
(13)
3
⎜
Topt = ⎜
⎝
3
⎜
Topt = ⎜
⎝
⎞2
⎛
(D2 T )opt =
⎟
6Ceff L 21
2
⎟
3 ⎠ BR
2
B R −1
2L 1
2
R1 + B RR−1
Remu
BR
6Ceff L 21
1
3
BR ∝
2
R1 + B RR−1
6Ceff L 21
2
R1 + B RR−1
1
3
Vsto
Vemu
Vsto
BR
∝
.
BR − 1
Vsto − Vemu
(14)
(15)
(16)
The total minimal power loss (Ploss_min ) in the boost converter,
which is found by substituting (14) in the expression of Ploss ,
is given by
2 1
0.605
Vemu
Ceff 3
Ploss_min = 1.21 +
BR
Remu
L1
2
3
R2
× R1 +
(B R − 1).
(17)
BR − 1
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SAINI AND BAGHINI: GENERIC PMC FOR ENERGY HARVESTERS WITH SHARED COMPONENTS
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Fig. 12. (a) Circuit designed using switches and control signals S1 and S2 to sense fraction of OCV Vs . (b) Control circuit to generate signals S1 and S2 .
PL is HIGH until Vsto reaches 1.8 V. PMBC and PL are provided by the voltage monitor circuits.
With these approximations, for Remu = 65 k, the normalized
power loss with respect to the maximum available power
2 /R
[Pnorm = Ploss_min /(Vemu
emu )] in the boost converter will
increase from 8.31% to 12.54% for Pavl = 153 nW and from
4.42% to 5.07% for Pavl = 1.38 μW, without losing the
concept of MPPT.
For the commercial inductor L 1 = 820 μH, its dc series
resistance is Rind = 2.7 [22]. Ploss_min depends on the
resistance and parasitic capacitance of the switches, which,
in turn, depends on their size. Pnorm is plotted for different
sizes of M N and M P , as shown in Fig. 11. For plotting Fig. 11,
Vs = 2 × Vemu = 200 mV, Rs = Remu = 65 k, Vsto = 1
V, and RC = 1 is chosen. RC includes the equivalent series
resistance of Cpool = 10 μF [23] and switch resistance, which
are in series with Cpool. The reason for introducing switches
in series with Cpool will be discussed in Section III-G (see
Fig. 19). The sizes at which Pnorm is minimum (12.54%)
are 2.5 mm for M N and 1 mm for M P in the 180-nm MM
CMOS process. Therefore, R N = 2.31 , R P = 13.8 , and
Ceff = 17.06 pF at typical corner.
1) Sensing Vref Voltage: Vref is a fraction of the OCV of the
energy harvester. The circuit to sense Vref with the help of control signals S1 and S2 is shown in Fig. 12(a). Initially, the boost
converter is disconnected from the energy harvester and its
OCV (Vs ) gets accumulated over Cs1 by turning on SW1
using S1 for the duration of Ts = 10 ms. Ts should be around
five times of the time constant introduced by resistor Rs and
capacitor Cs1 . During this time, the voltage across Cs2 gets
discharged by SW3 . After 10 ms, SW1 and SW3 are turned
off and SW2 and SW4 are turned on by S2 . Therefore, Cs1 and
Cs2 come in parallel and the initial energy stored on Cs1 will
be distributed across Cs1 and Cs2 depending on their values.
S2 will remain HIGH for 4.5 s and provides the necessary Vref
across Cs1 for operation of the boost converter. Maintaining
Vemu equal to Vref helps in implementing the MPPT at the
input of the boost converter. The control circuit to generate S1
and S2 and its timing diagram is shown in Figs. 12(b) and 13.
Individual blocks used in Fig. 12(b) are shown in detail in
Fig. 14.
2) (D1 T )opt Implementation: The circuit to generate
(D1 T )opt is shown in Fig. 15. Operation of the complete circuit
consists of two phases: startup and MPPT. During startup, Vsto
is charged by the startup circuit and the control circuit shown
in Fig. 15(a)–(c) is off. During this phase, outputs of the SR
latches are LOW because PMBC is HIGH.
Fig. 13.
Timing diagram associated with the circuit in Fig. 12.
At the beginning of the MPPT phase, PMBC goes HIGH
which generates a monoshot pulse PMONO1 as shown
in Fig. 12(b), which resets SR latch 2 in Fig. 15(c). Hence,
no current is consumed by the circuit in Fig. 15(a) because
SGATE is LOW. Cpool is charged by the energy harvester and as
soon as Vemu reaches more than Vref , signal Vc goes HIGH,
as shown in Fig. 8. It indicates that M N should be turned
on for (D1 T )opt time. The rising edge of Vc sets the SR
Latch 1 and SR Latch 2 in Fig. 15(b) and (c) and signals
PEMU and SGATE go HIGH and SCHG1 goes LOW. PEMU turns
on M N and SGATE allows the circuit of Fig. 15(a) to work.
A fraction of Vemu is sensed and given as input to a differential
amplifier, as shown in Fig. 15(a), which generates a current
proportional to Vemu (Ipemu1 = Vemu /N R P ) passing through
the M P1 transistor. N = 6 is chosen here to reduce the loading
on Vemu , and R p = 333 k is chosen so that low current will
flow through the M P1 transistor. Current from M P1 is mirrored
into M P4 (Ipemu4 = Ipemu1 ) in Fig. 15(b). Since SCHG1 is
LOW, M P5 is on; therefore, Ipemu4 charges Cramp1 gradually
[Vramp1 = (Ipemu4 × t)/Cramp1 ]. As soon as the voltage across
Cramp1 reaches Vsto /2, output of Buffer 1 (R1) goes HIGH
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Fig. 14. (a) Current starved ring oscillator followed by frequency divider to generate TOSC = 4.5 s. Current reference for biasing is taken from [12].
(b) Monoshot pulse generator on the rising edge of POSC2 to produce 10-ms pulsewidth. (c) Monoshot pulse generator on the rising edge of PMBC .
(d) Monoshot pulse generator on the falling edge of PMONO2 . (e) SR latch with enable. (f) Charge pump.
Fig. 15. Implementation of (D1 T )opt . (a) Circuit designed to produce current proportional to Vemu . (b) Producing ON time of M N proportional to Vsto / Vemu .
(c) Circuit designed to generate a signal which will allow current flow in Fig. 15(a) and Fig. 16(a) only for [(D1 T )opt + (D2 T )opt ] time. (d) Timing diagram
associated with the complete circuit. Vsto is assumed constant for one cycle of MPPT.
and resets the SR Latch 1. Therefore, PEMU goes LOW and
M N turns off. Also SCHG1 goes HIGH and Cramp1 discharges
through M N5 from Vsto /2 to 0. The time for which PEMU is
HIGH is also the time for which Cramp1 is charged from 0 to
Vsto /2 and is given by
t0→Vsto/2 =
N
2
Cramp1 R p
Vsto
Vemu
Clearly, this time is proportional to the ratio Vsto /Vemu as
given in (15). From (15), for Vemu = 100 mV and Vsto = 1
V, (D1 T )opt is 20.52 μs. Therefore, t0→Vsto/2 should be equal
to 20.52 μs in (18). Substituting all the known parameters
in (18), Cramp1 is found to be 2.05 pF.
D. Synchronous Rectification Control for the Boost Converter
.
(18)
As soon as PEMU goes LOW, stored energy in the inductor should be transferred to Csto through M p (see Fig. 8).
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SAINI AND BAGHINI: GENERIC PMC FOR ENERGY HARVESTERS WITH SHARED COMPONENTS
543
Fig. 16. Implementation of (D2 T )opt . (a) Circuit designed to produce current proportional to Vsto − Vemu . (b) Producing ON time of M P proportional to
Vsto /(Vsto − Vemu ).
Therefore, PSR needs to go LOW as soon as PEMU goes
LOW [24]. The circuit to generate PSR is shown in Fig. 16
and the associated timing diagram is shown in Fig. 17. The
time for which PSR is LOW is given by (16). At the falling
edge of PEMU , monoshot signal PMONO6 is generated which
sets the SR Latch 3; therefore, PSR and SCHG2 go LOW.
A fraction of Vsto is sensed and is given as input to the
differential amplifier 2 in Fig. 16(a), which generates a current
equal to Ipsto3 = (Vsto − Vemu )/N R P and flows through M P3 .
Current from M P3 is mirrored into M P7 in Fig. 16(b). Since
SCHG2 is LOW, M P8 is on, and hence, Ipsto7 gradually charges
Cramp2 (Vramp2 = (Ipsto6 × t)/Cramp2 ). As soon as Vramp2
reaches Vsto2/2, the output of Buffer 2 (R3) goes HIGH
and resets the SR Latch 3. Therefore, PSR goes HIGH and
M P turns off. Also SCHG2 goes HIGH and Cramp2 discharges
through M N8 from Vsto/2 to 0. The time for which PSR is
LOW is also the time for which Cramp2 is charged from 0
to Vsto/2 and is given by
Vsto
N
t0→V
C
.
(19)
=
R
ramp2 p
sto/2
2
Vsto − Vemu
Clearly, this time is proportional to Vsto /(Vsto − Vemu ) as
given in (16). From (16), for Vemu = 100 mV and Vsto =
should also be
1 V, (D2 T )opt is 2.28 μs. Therefore, t0→V
sto/2
equal to 2.28 μs in (19). Substituting all the known parameters
in (19), Cramp2 is found to be 2.05 pF.
E. Calculation of the First Storage Capacitor, Cpool
During the time when both M N and M P are turned off, Cpool
is charged from Vmin to Vmax in time Topt [Topt (D1 T )opt +
(D2 T )opt ] and voltage Vemu is given by
−t
. (20)
Vemu (t) = Vmin + (Vs −Vmin) 1 − ex p
Cpool × Rs
For MPPT, average voltage of Vemu is a fraction (α) of the
OCV (Vs ) of the energy harvester. Cpool is large enough so that
the ripple in Vemu is kept less than 10% of Vemu . Therefore,
Vmin is equal to 0.9αVs . After substituting all the known
parameters in (20), Cpool is given by
Topt
.
(21)
Cpool =
Rs × ln 1−0.9α
1−α
Fig. 17.
Timing diagram associated with the circuit in Fig. 16
For the RF and piezo energy harvester, Remu ≈ Rs , Cs1 ≈
Cs2 , and α ≈ 0.5. Therefore, Topt /Rs is calculated from (14)
and substituted in (21) which gives
⎞2
⎛
3
⎟
6Ceff L 21
1 ⎜
⎟ B 2 . (22)
⎜
Cpool =
R
3 ⎠
⎝
0.0953
2
R2
2L 1 BBR −1
R
+
1
B R −1
R
For Vemu = 50 mV and Vsto =1 V, Cpool ≈ 13 μF.
For the solar energy harvester, Remu ≈ 4 × Rs , Cs1 ≈
4 × Cs2 , and α ≈ 0.8; however, source resistance Rs is
not constant and depends on the irradiance of light. The
minimum value of Cpool can be found from Fig. 4. For
Pirr = 0.9 mW/cm2 , the maximum value of Pavl is 342 μW at
Vemu = 355 mV. This gives Remu = 370 and Rs = 92 .
For Vsto = 1 V, Topt from (14) is 7.4 μs and Cpool from (21)
is 240 nF.
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Equating (24) and (25), the value of the capacitor C L is found
to be 40 nF.
The buck converter is designed for 1 mA of nominal
load current (I L ) and 1 V of nominal load voltage (VL ),
while its input voltage (Vsto) changes from 1.8 to 1.1 V. The
line regulation estimated for the designed buck converter is
31 mV/V. For the load current variations from 0.5 to 10 mA
and the input voltage equal to 1.8 V, the estimated load
regulation is 1.05 mV/mA.
Fig. 18. (a) Buck converter used as a regulator. (b) Buck converter waveforms
in steady state.
F. Design of the Buck Converter as Output Voltage Regulator
As soon as Vsto reaches 1.8 V, PL goes LOW. This turns
on the pMOS switch MPL to provide the supply voltage
VDD_BUCK (= Vsto) to the control circuit of the buck converter,
as shown in Fig. 18. This arrangement prevents the power
loss in the control circuit of the buck converter during MPPT.
The buck converter now provides a regulated voltage across
a load (R L ) connected at its output, as shown in Fig. 18(a).
The buck converter is designed to operate at the boundary
of the continuous conduction mode and the discontinuous
conduction mode. Here, inductor and switches are the same as
those used in the design of the boost converter. Now, the only
parameters that need to be found are the value of capacitor
C L and the delay of comparator COMP4 for a particular load
resistance R L . For the design purpose, nominal load (R L ) and
voltage (VL ) are assumed to be 1 k and 1 V, respectively.
The average value of the inductor current (I2avg ) is equal to the
load current, as shown in Fig. 18(b). Also, the average value of
inductor current in terms of maximum inductor current (I2max )
is given by (1/2)×I2max . Hence, I2max is equal to 2 mA. When
M P is on, inductor current will increase from 0 to I2max in
time T A , and voltage across the inductor remains at 0.8 V
given by
VL2 = L 1
di 2
I2max
= L1
.
dt
TA
(23)
After substitution, T A comes out to be 2.05 μs. Therefore,
delay of the comparator is 2.05 μs. When M N is on, inductor
current will decrease from I2max to 0 in time TB , and the
voltage across the inductor is −1 V. After substituting the
values in (23), TB comes out to be 1.64 μs. Because of finite
delay of the comparator, there is ripple across the load R L .
To have a moderate ripple in the range of 0.98–1.02 V, there is
a need of finite capacitance C L across R L . Energy consumed
by the load during time TB is given by
EL =
VL2
× TB .
RL
(24)
This energy is supplied by the capacitor C L , and the voltage
across C L will change from 1.02 to 0.98 V. Therefore, change
in energy in the capacitor is given by
δ EC =
1
× C L × (1.022 − 0.982 ).
2
(25)
G. Inductor Sharing Between MPPT and Voltage Regulator
During MPPT, inductor (L 1 ) and switches (M N and M P ) are
used by the boost converter and during voltage regulation by
the buck converter. Hence, there is a need for a control circuit
which will share them between the two converters shown
in Fig. 19. As already explained in Fig. 6, the boost converter
will work when Vsto is more than 800 mV but less than 1.8 V,
which means PMBC and PL signals are HIGH. As soon as Vsto
reaches 1.8 V, PL goes LOW and the buck converter starts
working which will bring the voltage Vsto down to 1 V and
PL will become HIGH again.
The boost converter needs two signals PEMU and PSR for
controlling the switches M N and M P , while the buck converter
needs only one signal PREG . Therefore, two multiplexers are
needed whose outputs control the gates of two switches as
shown in Fig. 19(b) and (c). PEMU is multiplexed with PREG
and PSR is multiplexed with PREG using multiplexers as shown
in Fig. 19(b) and (c); PL and PL are the control signals to these
multiplexers. When PL is HIGH, PN = PEMU and PP =
PSR and the boost converter will be activated. When PL is
LOW, PN = PP = PREG and the buck converter will be
activated.
During the operation of the boost converter, there is a need
to bring the noninverting input of comparator COMP3 to zero
after Vc goes HIGH due to the hysteresis. When Vc goes
HIGH, SGATE will be HIGH as shown in Fig. 15(c) and
transistor Mn8 will discharge the node Vnon_inv , bringing back
Vc to LOW. The sizes of the different switches used in Fig. 19
are given in Table I.
V. R ESULTS
A. Efficiency Definition
There are three blocks between the energy capture transducer and the final load. First one is energy harvester. The
energy harvesters give maximum efficiency when their load
voltage is some fraction of the OCV. There is little a circuit
designer can do to increase the efficiency of the energy
harvester module except to provide optimal load voltage.
The second block in the chain is the boost converter which
acts like a load for the energy harvester module and its input
voltage is a particular fraction of the OCV of the energy
harvester for MPPT. It receives the maximum available power
from the energy harvester and stores it in Csto . Power loss and
hence efficiency of the boost converter depend on its input
voltage, output voltage, and available power, as given in (17).
Efficiency of the boost converter is given by the ratio of change
in energy stored in Csto when the voltage across it is increased
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SAINI AND BAGHINI: GENERIC PMC FOR ENERGY HARVESTERS WITH SHARED COMPONENTS
545
Fig. 19. Top-level schematic showing the inductor (L 1 ) and switches (M N and M P ) shared between the boost converter and the buck converter. The body
of transistors Mn4 , Mn5 , and Mn6 in the switches SW4 , SW5 , and SW6 , respectively, is connected to the lowest of potential appears on source and drain of
the respective switch. The body of transistors M p4 , M p5 , and M p6 in the switches SW4 , SW5 , and SW6 , respectively, is connected to the highest of potential
appears on source and drain of the respective switch.
TABLE I
S WITCHES ’ S IZE U SED FOR THE C IRCUIT S HOWN IN F IG . 19
Fig. 21.
Sensing Vref voltage when S1 is HIGH.
TABLE II
P OWER L OSS O PTIMIZATION M ODEL VALIDATION
Fig. 20.
Layout of the complete energy harvesting system.
from Vsto1 to Vsto2 in time t1 to the product of the maximum
power available at the input of boost converter and time t1 ,
as given in
2 − 1C V 2
Csto Vsto2
2 sto sto1
(26)
Pavl × t1
where Vsto1 = 1 and Vsto2 = 1.8 V are chosen and t1
is obtained from simulation. Hence, an efficiency versus
1
η= 2
Pavl for different values of source resistance is obtained.
The third block is the regulator which takes energy from
Csto and supplies that to the load R L . Its efficiency is the
power across the load R L divided by the power taken from
capacitor Csto .
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TABLE III
P ERFORMANCE C OMPARISON W ITH O THER E NERGY H ARVESTING DC–DC C ONVERTERS
Fig. 23. Efficiency of the boost converter with respect to maximum available
power in the boost converter.
Fig. 22. Transient waveforms of Vsto , PMBC , PL , and VL for 153-nW
available power Pavl (Vs = 200 mV and Rs = 65 k).
B. Validation of the Boost Converter Model
The power loss optimization model of the boost converter
derived in Section-IV is validated using the transistor level
simulation in Cadence. The normalized power loss (Pnorm )
is calculated using the approximated model and compared
with the simulated loss in the boost converter in Table II.
The difference in Pnorm for the model and simulation is
because the model does not include the leakage power loss.
C. Post-Layout Simulation Results of the Complete PMC
A battery-less energy harvesting system using OCV-based
MPPT is designed and optimized in 180-nm MM CMOS
technology. Layout of the complete system is shown in Fig. 20.
Post-layout simulation results for Fig. 12 are shown in Fig. 21.
Cs1 and Cs2 are both equal and chosen to be 5 nF. Vref is
around half of Vs , as shown in Fig. 21. As shown in Fig. 22,
when Vsto reaches 1.8 V, the buck converter provides a
regulated supply of 1 V across a load resistance of 1 k for
approximately 1 ms. Efficiency of the boost converter is found
with respect to different values of available power according
to (26) and plotted for different source resistances, as shown
in Fig. 23. Efficiency of the boost converter increases with
the increase in maximum available power because the losses
in the control circuit of the boost converter become negligible as compared to maximum available power. In addition,
the efficiency is high for higher values of source resistance for
the same amount of available power. The input voltage of the
boost converter increases for higher value of source resistance
for the same amount of available power. This minimizes the
resistive loss of the boost converter, since optimal inductor
energize time is lower for obtaining a lower voltage boost
ratio. For small values of source impedance, the efficiency
starts to decrease for the higher values of available power. The
control circuit of the energy harvesting system is designed and
optimized to consume low power. For small values of source
resistance and higher values of available power, the pMOS
turn-on time increases. This leads to reverse current flow in
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547
in the boost converter, as the available power from the energy
harvester changes. The inductor is shared between the boost
converter and the buck converter to minimize the external
components.
VI. C ONCLUSION
Fig. 24.
(a) Effect of process and temperature variations on the boost
converter efficiency at 4 μW of Pavl . All the transistors are considered in
the same corner. (b) Effect of mismatch variations in tt-corner at 27 ◦ C.
A complete energy harvesting system with a novelintegrated circuit comprising of a self-startup, a boost converter, and a buck converter with MPPT for a wide range of
energy source resistance is presented. The same system can
be used for solar, piezoelectric, and RF energy harvesters. The
switches and inductor are shared between the boost converter,
which is used for MPPT, and the buck converter, which is used
for providing a regulated supply across a load. The minimum
available power that can be harvested is 30 nW.
R EFERENCES
Fig. 25. Post-layout simulation result for the buck converter showing constant
voltage of 1 V across 1-k load. The input of the buck converter is 1-muF
capacitor initially charged to 1.8 V.
the inductor, which degrades the efficiency. For Pavl = 1 μW
(Vs = 200 mV and Rs = 10 k), the power consumed by the
complete circuit during MPPT is 230 nW.
To quantify the effect of process and temperature on the
boost converter efficiency, corner simulations were performed
for different temperatures (−20 ◦ C, 27 ◦ C, and 60 ◦ C) and are
shown in Fig. 24(a). The worst case for the corner analysis
happens in ff-corner at 60 ◦ C. The efficiency of the boost
converter degrades in ff-corner at 60 ◦ C mainly due to the
leakage currents in the large size switches and the buffers
which are used to drive those large size switches. The effect
of transistor mismatches on the boost converter efficiency is
obtained by performing Monte Carlo analysis for 500 points
in tt-corner at 27 ◦ C and is shown in Fig. 24(b). For the plots
shown in Fig. 24, the available power considered is 4 μW
(Vs = 400 mV and Rs = 10 k), which is of typical value
for the energy harvesting sources considered in this paper. The
low value of efficiency for some points corresponds to nonoptimal generation of timing signals, which leads to increase
in ripple at the input of the boost converter which decreases
the efficacy of the MPPT.
Post-layout simulation results for the buck converter are
shown in Fig. 25. Voltage Vsto decreases when the buck
converter was working and the load voltage is 1 V with 60 mV
of ripple. VL is maintained at 1 V for time of approximately
1 ms when Csto is 1 μF and R L = 1 k. Efficiency of the
buck converter for R L equal to 1 k is found to be 94.32%.
Table III compares the efficiencies of different types of
energy harvesting systems. This paper is able to maintain
MPPT for a wide range of source resistances. The switching
frequency of the boost converter is varied to minimize the loss
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Gaurav Saini received the B.E. degree in
instrumentation and control engineering from the
Netaji Subhas Institute of Technology, New Delhi,
India, and the M.Tech. degree in electrical engineering from IIT Delhi, New Delhi. He is currently
working toward the Ph.D. degree in power management IC design for energy harvesting at IIT Bombay,
Mumbai, India.
His current research interests include energy harvesting and low power IC design.
Maryam Shojaei Baghini (M’00–SM’09) received
the M.S. and Ph.D. degrees in electrical engineering
from the Sharif University of Technology, Tehran,
Iran, in 1991 and 1999, respectively.
She is currently a Professor with the Department of
Electrical Engineering, IIT Bombay, Mumbai, India.
She worked in industry from 1991 to 1992 and
1999 to 2000 as a Senior Analog IC Design Engineer. In 2001, she joined IIT Bombay, Mumbai,
India, as a Post-Doctoral Fellow, where she is currently a Professor with the Department of Electrical
Engineering. She has authored or coauthored more than 200 international peer
reviewed journal and conference papers and invented or coinvented six issued
U.S. patents, one issued Indian patent, and 40 more patent applications. Her
current research interests include devices and sensors to the instrumentation
circuits and sensor systems, energy harvesting circuits and systems, and
analog, mixed-signal and RF circuit design.
Dr. Shojaei Baghini has served as a Technical Committee Member of the
IEEE A-SSCC for six years and the Track Chair for the IEEE Sensors
Conference 2018, INDICON, and IEEE iNIS. She was a joint recipient of
several awards, including the IIT Bombay Impactful Research Award.
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