SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
D
D
D
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
Meet or Exceed the Requirements of
TIA/EIA-422-B, TIA/EIA-485-A† and ITU
Recommendations V.11 and X.27
Operate at Data Rates up to 35 Mbaud
Four Skew Limits Available:
SN65ALS176 . . . 15 ns
SN75ALS176 . . . 10 ns
SN75ALS176A . . . 7.5 ns
SN75ALS176B . . . 5 ns
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
Low Supply-Current Requirements
. . . 30 mA Max
Wide Positive and Negative Input/Output
Bus-Voltage Ranges
Thermal Shutdown Protection
Driver Positive and Negative Current
Limiting
Receiver Input Hysteresis
Glitch-Free Power-Up and Power-Down
Protection
Receiver Open-Circuit Fail-Safe Design
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
description
The SN65ALS176 and SN75ALS176 series differential bus transceivers are designed for bidirectional data
communication on multipoint bus transmission lines. They are designed for balanced transmission lines and
meet TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendations V.11 and X.27.
The SN65ALS176 and SN75ALS176 series combine a 3-state, differential line driver and a differential input line
receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, that can be connected together externally to function as a direction control.
The driver differential outputs and the receiver differential inputs are connected internally to form a differential
input/output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or
VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device
suitable for party-line applications.
The SN65ALS176 is characterized for operation from –40°C to 85°C. The SN75ALS176 series is characterized
for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† These devices meet or exceed the requirements of TIA/EIA-485-A, except for the Generator Contention Test (para. 3.4.2) and the Generator
Current Limit (para. 3.4.3). The applied test voltage ranges are –6 V to 8 V for the SN75ALS176, SN75ALS176A, and SN75ALS176B and
–4 V to 8 V for the SN65ALS180.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
tsk(lim)†
SMALL OUTLINE
(D)‡
PLASTIC DIP
(P)
0°C to 70°C
10
7.5
5
SN75ALS176D
SN75ALS176AD
SN75ALS176BD
SN75ALS176P
SN75ALS176AP
SN75ALS176BP
–40°C to 85°C
15
SN65ALS176D
SN65ALS176P
† This is the maximum range that the driver or receiver delay times vary over
temperature, VCC, and process (device to device).
‡ The D package is available taped and reeled. Add the suffix R to the device
type (e.g., SN75ALS176DR).
Function Tables
DRIVER
INPUT
D
ENABLE
DE
H
H
L
X
OUTPUTS
A
B
H
L
H
L
H
L
Z
Z
H = high level, L = low level, X = irrelevant,
Z = high impedance
RECEIVER
DIFFERENTIAL
INPUTS
A–B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
–0.2 V < VID < 0.2 V
L
H
L
?
VID ≤ –0.2 V
X
L
L
H
Z
Inputs open
L
H
H = high level, L = low level, X = irrelevant,
Z = high impedance
logic symbol§
DE
RE
D
R
3
2
logic diagram (positive logic)
DE
EN1
D
EN2
4
1
1
6
7
A
RE
B
R
3
4
2
6
1
1
2
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
POST OFFICE BOX 655303
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7
A
B
Bus
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF A AND B I/O PORTS
VCC
VCC
R(eq)
85 Ω
NOM
180 kΩ
NOM
Connected
on A Port
Input
TYPICAL OF RECEIVER OUTPUT
VCC
3 kΩ
NOM
Output
A or B
18 kΩ
NOM
Driver Input: R(eq) = 3 kΩ NOM
Enable Inputs: R(eq) = 8 kΩ NOM
R(eq) = equivalent resistor
180 kΩ
NOM
Connected
on B Port
1.1 kΩ
NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 12 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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3
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
recommended operating conditions (unless otherwise noted)
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
Input voltage at any bus terminal (separately or common mode),
mode) VI or VIC
–7
High-level input voltage, VIH
D, DE, and RE
Low-level input voltage, VIL
D, DE, and RE
2
Low level output current
Low-level
current, IOL
V
±12
V
Driver
–60
mA
Receiver
–400
µA
Driver
60
Receiver
8
SN65ALS176
Operating free-air
free air temperature,
temperature TA
V
0.8
Differential input voltage, VID (see Note 3)
High level output current,
High-level
current IOH
SN75ALS176 series
–40
85
0
70
NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
4
POST OFFICE BOX 655303
V
• DALLAS, TEXAS 75265
mA
°C
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
TEST CONDITIONS†
PARAMETER
VIK
VO
Input clamp voltage
Output voltage
II = –18 mA
IO = 0
|VOD1|
Differential output voltage
IO = 0
|VOD2|
g
Differential output voltage
VOD3
Differential output voltage
∆|VOD|
MIN
TYP‡
MAX
UNIT
–1.5
V
0
6
V
1.5
6
V
RL = 100 Ω,
See Figure 1
1/2VOD1
or 2§
RL = 54 Ω,
See Figure 1
1.5
Vtest = –7 V to 12 V,
See Figure 2
1.5
Change in magnitude of
differential output voltage¶
RL = 54 Ω or 100 Ω,
VOC
Common-mode output voltage
∆|VOC|
V
5
V
5
V
See Figure 1
±0.2
V
RL = 54 Ω or 100 Ω,
See Figure 1
3
–1
V
Change in magnitude of
common-mode output voltage¶
RL = 54 Ω or 100 Ω,
See Figure 1
±0.2
V
IO
Output current
Outputs disabled
(see Note 4)
VO = 12 V
VO = –7 V
–0.8
IIH
IIL
High-level input current
Low-level input current
Short-circuit output current#
1
VI = 2.4 V
VI = 0.4 V
VO = –4 V
VO = –6 V
IOS
2.5
Supply current
No load
µA
–400
µA
–250
SN75ALS176
–250
–150
mA
250
VO = 8 V
ICC
20
SN65ALS176
VO = 0
VO = VCC
mA
250
Outputs enabled
23
30
Outputs disabled
19
26
mA
† The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡ All typical values are at VCC = 5 V and TA = 25°C.
§ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
¶ ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from one logic state to the
other.
# Duration of the short circuit should not exceed one second for this test.
NOTE 4: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a
combined driver and receiver terminal.
POST OFFICE BOX 655303
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5
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
SN65ALS176
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
15
ns
2
ns
15
ns
td(OD)
tsk(p)
Differential output delay time
Pulse skew‡
RL = 54 Ω,
CL = 50 pF,
See Figure 3
RL = 54 Ω,
CL = 50 pF,
See Figure 3
tsk(lim)
tt(OD)
Pulse skew§
RL = 54 Ω,
CL = 50 pF,
See Figure 3
Differential output transition time
RL = 54 Ω,
CL = 50 pF,
See Figure 3
tPZH
tPZL
Output enable time to high level
RL = 110 Ω,
CL = 50 pF,
See Figure 4
80
ns
Output enable time to low level
RL = 110 Ω,
CL = 50 pF,
See Figure 5
30
ns
tPHZ
tPLZ
Output disable time from high level
RL = 110 Ω,
CL = 50 pF,
See Figure 4
50
ns
Output disable time from low level
RL = 110 Ω,
CL = 50 pF,
See Figure 5
30
ns
UNIT
0
8
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
§ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
SN75ALS176, SN75ALS176A, SN75ALS176B
PARAMETER
TEST CONDITIONS
’ALS176
td(OD)
(
)
Differential
Diff
ti l output
t t
delay time
RL = 54 Ω,
’ALS176A
CL = 50 pF,
See Figure 3
’ALS176B
tsk(p)
Pulse skew‡
RL = 54 Ω,
CL = 50 pF,
See Figure 3
RL = 54 Ω,
CL = 50 pF,
See Figure 3
MIN
TYP†
MAX
3
8
13
4
7
11.5
5
8
10
0
2
’ALS176
tsk(lim)
( ) Pulse skew§
ns
10
’ALS176A
7.5
’ALS176B
ns
5
tt(OD)
tPZH
Differential output transition time
RL = 54 Ω,
CL = 50 pF,
See Figure 3
8
Output enable time to high level
RL = 110 Ω,
CL = 50 pF,
See Figure 4
23
50
ns
tPZL
tPHZ
Output enable time to low level
RL = 110 Ω,
CL = 50 pF,
See Figure 5
14
20
ns
Output disable time from high level
RL = 110 Ω,
CL = 50 pF,
See Figure 4
20
35
ns
8
17
ns
tPLZ
Output disable time from low level
RL = 110 Ω,
CL = 50 pF,
See Figure 5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
§ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
SYMBOL EQUIVALENTS
6
ns
DATA-SHEET
PARAMETER
TIA/EIA-422-B
TIA/EIA-485-A
VO
|VOD1|
Voa, Vob
Vo
Voa, Vob
Vo
|VOD2|
Vt (RL = 100 Ω)
|VOD3|
None
Vt (RL = 54 Ω)
Vt (test termination
measurement 2)
∆|VOD|
||Vt| – |Vt||
||Vt| – |Vt||
VOC
∆|VOC|
IOS
|Vos|
|Vos – Vos|
|Isa|, |Isb|
|Vos|
|Vos – Vos|
None
IO
|Ixa|, |Ixb|
Iia, Iib
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
VIT–
Positive-going input threshold voltage
Vhys
VIK
Hysteresis voltage (VIT+ – VIT–)
Enable-input clamp voltage
II = –18 mA
VOH
High level output voltage
High-level
VID = 200 mV,,
See Figure 6
IOH = –400 µ
µA,,
VOL
Low-level output voltage
VID = –200 mV,
See Figure 6
IOL = 8 mA,
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
Negative-going input threshold voltage
VO = 2.7 V,
VO = 0.5 V,
TYP†
MAX
UNIT
0.2
V
–0.2‡
V
60
Other input = 0 V
(see Note 5)
VI
Line input current
IIH
IIL
High-level-enable input current
rI
Input resistance
IOS
Short-circuit output current
VID = 200 mV,
ICC
Supply current
No load
Low-level-enable input current
IO = –0.4 mA
IO = 8 mA
MIN
mV
–1.5
27
2.7
V
VI = 12 V
VI = –7 V
0.45
V
±20
µA
1
–0.8
VIH = 2.7 V
VIL = 0.4 V
20
–100
12
VO = 0
Outputs enabled
Outputs disabled
V
20
–15
mA
µA
µA
kΩ
–85
23
30
19
26
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 5: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
SN65ALS176
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
25
ns
2
ns
15
ns
tpd
Propagation time
VID = –1.5 V to 1.5 V,
See Figure 7
CL = 15 pF,
tsk(p)
Pulse skew§
VID = –1.5 V to 1.5 V,
See Figure 7
CL = 15 pF,
tsk(lim)
Pulse skew¶
RL = 54 Ω,
See Figure 3
CL = 50 pF,
tPZH
tPZL
Output enable time to high level
CL = 15 pF,
See Figure 8
11
18
ns
Output enable time to low level
CL = 15 pF,
See Figure 8
11
18
ns
tPHZ
tPLZ
Output disable time from high level
CL = 15 pF,
See Figure 8
50
ns
30
ns
UNIT
0
Output disable time from low level
CL = 15 pF,
See Figure 8
† All typical values are at VCC = 5 V, TA = 25°C.
§ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
¶ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
SN75ALS176, SN75ALS176A, SN75ALS176B
PARAMETER
TEST CONDITIONS
’ALS176
tpd
Propagation time
’ALS176A
1 5 V to
t 1.5
1 5 V,
V
VID = –1.5
See Figure 7
F
CL = 15 pF,
’ALS176B
tsk(p)
Pulse skew‡
tsk(lim)
( )
Pulse skew§
’ALS176
’ALS176A
VID = –1.5 V to 1.5 V,
See Figure 7
CL = 15 pF,
RL = 54 Ω,
Ω
See Figure 3
CL = 50 pF,
F
MIN
TYP†
MAX
9
14
19
10.5
14
18
11.5
13
16.5
0
2
ns
10
7.5
’ALS176B
ns
5
tPZH
tPZL
Output enable time to high level
CL = 15 pF,
See Figure 8
7
14
ns
Output enable time to low level
CL = 15 pF,
See Figure 8
20
35
ns
tPHZ
tPLZ
Output disable time from high level
CL = 15 pF,
See Figure 8
20
35
ns
Output disable time from low level
CL = 15 pF,
See Figure 8
8
17
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
§ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
PARAMETER MEASUREMENT INFORMATION
VOD2
RL
2
RL
2
VOC
Figure 1. Driver VOD2 and VOC
8
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
375 Ω
60 Ω
VOD3
375 Ω
Vtest
Figure 2. Driver VOD3
3V
RL = 54 Ω
Generator
(see Note B)
CL = 50 pF
(see Note A)
0V
td(ODH)
(see Note C)
Output
50 Ω
1.5 V
1.5 V
Input
90% 90%
Output
3V
50%
10%
tt(OD)
TEST CIRCUIT
td(ODL)
(see Note C)
≈2.5 V
50%
10%
≈–2.5 V
tt(OD)
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
C. td(OD) = td(ODH) or td(ODL)
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
S1
3V
0 V or 3 V
Input
CL = 50 pF
(see Note A)
Generator
(see Note B)
RL = 110 Ω
1.5 V
1.5 V
0V
tPHZ
tPZH
50 Ω
VOH
Output
TEST CIRCUIT
2.3 V
Voff ≈ 0
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 4. Driver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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9
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
5V
RL = 110 Ω
S1
3V
1.5 V
Input
Output
1.5 V
0V
0 V or 3 V
CL = 50 pF
(see Note A)
Generator
(see Note B)
tPZL
tPLZ
50 Ω
5V
2.3 V
Output
0.5 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 5. Driver Test Circuit and Voltage Waveforms
VID
VOH
+ IOL
–IOH
VOL
Figure 6. Receiver VOH and VOL Test Circuit
3V
Input
1.5 V
1.5 V
0V
Generator
(see Note B)
Output
51 Ω
1.5 V
tPLH
(see Note C)
tPHL
(see Note C)
CL = 15 pF
(see Note A)
VOH
Output
1.3 V
1.3 V
0V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
C. tpd = tPLH or tPHL
Figure 7. Receiver Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
5V
S2
S1
1.5 V
2 kΩ
– 1.5 V
Output
CL = 15 pF
(see Note A)
Generator
(see Note B)
5 kΩ
1N916 or Equivalent
50 Ω
S3
TEST CIRCUIT
3V
Input
3V
S1 to 1.5 V
S2 Open
S3 Closed
1.5 V
S1 to –1.5 V
1.5 V S2 Closed
S3 Open
Input
0V
0V
tPZH
tPZL
≈4.5 V
VOH
Output
Output
1.5 V
0V
3V
Input
1.5 V
1.5 V
VOL
3V
S1 to 1.5 V
S2 Closed
S3 Closed
Input
1.5 V
0V
0V
tPHZ
tPLZ
≈1.3 V
VOH
Output
S1 to –1.5 V
S2 Closed
S3 Closed
0.5 V
Output
0.5 V
≈1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 8. Receiver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS†
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
VCC = 5 V
TA = 25°C
4.5
VCC = 5 V
TA = 25°C
4.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
5
DRIVER
4
3.5
3
2.5
2
1.5
1
4
3.5
3
2.5
2
1.5
1
0.5
0.5
0
0
0
–20
–40
–60
–80
–100
IOH – High-Level Output Current – mA
0
–120
20
40
60
80
100
IOL – Low-Level Output Current – mA
120
Figure 10
Figure 9
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOD – Differential Output Voltage – V
4
VCC = 5 V
TA = 25°C
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30 40 50 60 70 80
IO – Output Current – mA
90
100
Figure 11
† Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
RECEIVER TYPICAL CHARACTERISTICS†
RECEIVER
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
VID = 0.3 V
TA = 25°C
4.5
4.5
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
5
4
3.5
3
VCC = 5.25 V
2.5
VCC = 5 V
2
1.5
VCC = 4.75 V
1
4
VCC = 5 V
VID = 300 mV
IOH = –440 µA
3.5
3
2.5
2
1.5
1
0.5
0.5
0
0
0
–40
–5 –10 –15 –20 –25 –30 –35 –40 –45 –50
IOH – High-Level Output Current – mA
–20
0
20
40
60
80
TA – Free-Air Temperature – °C
Figure 12
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.6
VCC = 5 V
TA = 25°C
VID = –300 mV
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
0.6
0.4
0.3
0.2
0.1
0
0
15
20
25
10
IOL – Low-Level Output Current – mA
5
120
Figure 13
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.5
100
30
0.5
VCC = 5 V
VID = – 300 mA
IOL = 8 mA
0.4
0.3
0.2
0.1
0
–40
–20
80
100
0
20
40
60
TA – Free-Air Temperature – °C
120
Figure 15
Figure 14
† Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040H – AUGUST 1987 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS†
RECEIVER
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
5
VCC = 4.75 V
3
VID = 0.3 V
Load = 1 kΩ to VCC
TA = 25°C
5
VO – Output Voltage – V
VCC = 5.25 V
4
VO – Output Voltage – V
VID = 0.3 V
Load = 8 kΩ to GND
TA = 25°C
VCC = 5 V
2
1
VCC = 5.25 V
VCC = 4.75 V
4
VCC = 5 V
3
2
1
0
0
0
0.5
1
1.5
2
2.5
0
3
0.5
VI(en) – Enable Voltage – V
1
1.5
2
2.5
3
VI(en) – Enable Voltage – V
Figure 17
Figure 16
† Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
APPLICATION INFORMATION
RT
RT
Up to
53 Transceivers
NOTE A: The line should terminate at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short
as possible.
Figure 18. Typical Application Circuit
14
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