CMOS Digital Integrated Circuits
Chapter 3
MOS Transistor
S.M. Kang, Y. Leblebici, and
C. Kim
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Copyright © 2014 McGraw-Hill Education. Permission required for reproduction or display.
Introduction
 Focus on
 The general outline of the MOSFET operation
 Current-voltage characteristics of MOSFET
 Physical limitation of small device geometries
 Various second-order effects observed in MOSFETs
 MOS capacitances
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Transistor Invention (1948) to Integrated Circuit (1958)
2000 Nobel Prize, Physics
(Jack Kilby)
1956 Nobel Prize, Physics
(J. Bardeen, W. Shockley,
W. Brattain)
Germanium,1T, 1C, 3R, Oscillator,
0.04 inch X 0.06 inch
Jack Kilby’s Nobel Lecture
(Dec. 8, 2000)
“In 1958, my goals were simple: to lower the cost,
simplify the assembly, and make things smaller
and more reliable. And although I do not consider
myself responsible for all the activity that has
followed, it has been very satisfying to watch the
IC’s evolution. I’m pleased to have had even a
small part in helping turn the potential of human
creativity into practical reality.”
First Successful Operation of MOS Transistor
Dawon Kahng (May 4, 1931- May 13, 1992)





Simon Sze
SNU (BS), Ohio State Univ. (Ph.D. 1959)
Dr. Kahng, with M. Atalla, fabricated a
MOSFET using a gate insulator formed
from high quality SiO2 grown by a new
high-pressure steam oxidation process at
Bell Labs (1960)
First successful demonstration of
MOSFET was a major milestone in
semiconductor technology
Invented in 1967 a field effect memory, the
first nonvolatile silicon memory (floating
gate memory)
Became Founding President of NEC,
Princeton, NJ in 1988
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The Metal Oxide Semiconductor Structure (1)
 The MOS structure forms a capacitor.
 Gate and substrate acting as plates of capacitor.
 Oxide layer acting as the dielectric of capacitor.
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The Metal Oxide Semiconductor Structure (2)
 The carrier concentration and its local distribution
within the semiconductor substrate can be
manipulated by the external voltage applied to the
gate and the substrate terminal.
 Mass Action Law
 n and p denote the mobile carrier concentration.
 ni denotes the intrinsic carrier concentration of silicon.
n  p  ni 2
(3.1)
 Mass Action Law gives us the equilibrium
concentration of mobile carriers in semiconductor.
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The Metal Oxide Semiconductor Structure (3)
 Assuming the substrate doped uniformly with an
acceptor concentration NA.
 Typically, NA is much greater than ni .
• ni is approximately equal to 1.45Ⅹ1010 cm-3 at room temperature.
• NA is typically on the order of 1015 to 1016 cm-3
p po  N A
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 So we can write,
and
ni 2
n po 
NA
(3.2)
© CMOS Digital Integrated Circuits – 4th Edition
The Metal Oxide Semiconductor Structure (4)
 Equilibrium Fermi level (EF) within the band-gap is
determined by the doping type and doping
concentration
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The Metal Oxide Semiconductor Structure (5)
 Fermi potential ФF , given by (3.3) , is a function of
temperature and doping.
F 
For p-type
ni
kT
Fp 
ln
q
NA
11
EF  Ei
q
(3.3)
For n-type
(3.4)
Fn 
kT N D
ln
q
ni
(3.5)
© CMOS Digital Integrated Circuits – 4th Edition
 PN junction
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Energy Band Diagrams under Gate Voltage Bias
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The Metal Oxide Semiconductor Structure (6)
 The electron affinity of silicon ( q  ) is the potential
difference between conduction band level and vacuum
level.
 Work function ( q S ) is the energy required for an
electron to move from the Fermi level into free space.
q S  q   ( EC  EF )
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(3.6)
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The Metal Oxide Semiconductor Structure (8)
 There is a built-in voltage drop due to the work
function difference between metal and the
semiconductor.
 This built-in voltage drop occurs across the insulating
oxide layer and surface of semiconductor.
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The Metal Oxide Semiconductor Structure (7)
 Three separate components of MOSFET system have
different energy band diagram.
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Example 3.1
 Calculate the built-in potential difference across MOS.
 P-type doped
 qFp = 0.2eV
 Electron affinity & Work function (Al) – Fig. 3.3
 Sol.
 Calculate the work function(Si)
qs  4.15eV  0.75eV  4.9eV
 So, the built-in potential difference is
qM - qS  4.1eV  4.9eV  0.8eV
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The MOS System Under External Bias(1)
 If we assume that substrate of MOS system is set to
0V (GND), depending on the polarity and the
magnitude of the gate voltage (VG), MOS system
operate in three different operating region.
 Accumulation, Depletion, and Inversion.
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The MOS System Under External Bias(2)
 If a negative voltage applied to the gate electrode, the
holes in p-type substrate are attracted to the
semiconductor-oxide interface : Accumulate
 The oxide electric field is directed toward gate electrode.
 The energy bands to band upward near the surface.
 Electron(minority carrier) concentration decrease.
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The MOS System Under External Bias(3)
 If a small positive voltage applied to the gate
electrode, the oxide electric field is directed toward
substrate. : Depletion
 The energy bands to band downward near the surface.
 Holes(majority carrier) will be repelled back into substrate.
 A depletion region is created near the surface.
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The MOS System Under External Bias(4)
 The thickness of the depletion region (xd) on the
surface is the function of the surface potential S .
• Mobile hole charge in a thin horizontal layer parallel to surface is
dQ  q  N A  dx
(3.7)
• Using the Poisson equation, we can find the surface potential
change required to displace this charge sheet dQ by a distance xd
away from the surface
d S   x 
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dQ
 Si

q  NA  x
 Si
 dx
(3.8)
© CMOS Digital Integrated Circuits – 4th Edition
The MOS System Under External Bias(5)
 Integrating the previous equation, we can find the thickness of
depletion region

x qN x
(3.9)
 dS  0  SiA dx
S
d
F
q  N A  xd 2
S   F 
2 Si
xd 
(3.10)
2 Si  | S  F |
q  NA
(3.11)
 The charge density of depletion region is given by,
Q  q  N A  xd   2q  N A   Si  | S  F |
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(3.12)
© CMOS Digital Integrated Circuits – 4th Edition
The MOS System Under External Bias(7)
 Once the surface is inverted, the thickness of depletion
region dose not increase any more even if the positive
gate bias is further increased.
 We can find the maximum depletion region depth xdm
by using the inversion condition S  F .
xdm 
23
2   Si  | 2F |
q  NA
(3.13)
© CMOS Digital Integrated Circuits – 4th Edition
The MOS System Under External Bias(6)
 If we increase the positive gate bias, mid-gap energy
level Ei becomes smaller than the Fermi level EFp. Then
semiconductor in this region becomes n-type : Surface
inversion
 The n-type layer near the surface is called inversion layer
 Inversion layer will be used for channel of MOSFET devices.
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Structure and Operation of MOSFET (1)
 MOSFET is a four terminal device.
 Gate, Source, Drain, Substrate (or Body).
 The two n+ region will be the current-conducting terminal of
this device. (Source and Drain)
 Conducting channel will be formed by Gate Voltage.
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Structure and Operation of MOSFET (2)
 Type of MOSFETs
 Zero bias channel state
• Enhancement-type
– No conducting channel at zero gate bias.
• Depletion-type
– Conducting channel already exists at zero gate bias.
 Type of Channel
• N-channel MOSFET
– P-type substrate and with n+ source and drain region. And
with n-channel.
• P-channel MOSFET
– N-type substrate and with p+ source and drain region. And
with p-channel.
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Structure and Operation of MOSFET (3)
 Circuit Symbols of MOSFETs
 The source is the n+(p+) region which has a lower (higher)
potential than the other n+(p+) region in an n-channel
(p-channel) MOSFET device.
 All the terminal voltage of the device are defined with respect
to the source potential.
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Structure and Operation of MOSFET (4)
 Channel current is
controlled by external
bias of four terminals.
 Conducting channel has to be formed in order to
start current flow between the source and drain
region.
 In fig3.10. as gate-to-source voltage is increased, the
majority carriers (holes) are repelled back into the
substrate, and the p-type substrate is depleted.
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Structure and Operation of MOSFET (5)
 As surface potential in the channel region reaches , a
conducting n-type layer is formed between the source
and the drain.
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Structure and Operation of MOSFET (6)
 The conducting channel provides an electrical
connection between the two n+ regions : allow current
flows.
 VT0 ,Threshold voltage, denote the value of the gate-tosource voltage required to create conducting channel.
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The Threshold Voltage (1)
 Physical components of the threshold voltage of a
MOS structure
 The work function difference between the gate and the
channel.
 The gate component to change the surface potential.
 The gate voltage component to offset the depletion region
charge.
 The voltage component to offset the fixed charges in the gate
oxide and in the silicon-oxide interface.
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The Threshold Voltage (2)
 The work function difference  GC between the gate
and the channel determines the built-in potential of
the MOS system.
• For metal gate
 GC  F ( substrate)  M
(3.14)
• For polysilicon gate
 GC  F ( substrate)  F ( gate)
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(3.15)
© CMOS Digital Integrated Circuits – 4th Edition
The Threshold Voltage (3)
 Because of the fixed acceptor ions located in the
depletion region near the surface, depletion charge
exists.
• Depletion region charge
QB 0   2q  N A   Si  | 2F |
(3.16)
• Consider the voltage bias of the body.
QB   2q  N A   Si  | 2F  VSB |
(3.17)
 The component that offsets the depletion region
charge is equal to QB / COX.
COX 
33
 ox
tox
(3.18)
© CMOS Digital Integrated Circuits – 4th Edition
The Threshold Voltage (4)
 There always exists a fixed positive charge density Qox
at the interface between the gate oxide and the silicon
substrate.
 The gate voltage component that is necessary to
offset this positive charge at the interface is QOX / COX .
• For zero substrate bias
VT 0   GC  2F 
QB 0 Qox

Cox Cox
(3.19)
• For nonzero substrate bias
VT   GC  2F 
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QB Qox

Cox Cox
(3.20)
© CMOS Digital Integrated Circuits – 4th Edition
The Threshold Voltage (5)
 We can write the generalized form of threshold
voltage.
QB 0 Qox QB  QB 0
Q  QB 0


 VT 0  B
Cox Cox
Cox
Cox
VT   GC  2F 
(3.21)
 The most general expressing of the threshold voltage
VT  VT 0    ( | 2F  VSB |  | 2F |)
(3.23)
 Q C Q   2q CN    ( | 2  V |  | 2 |)
B0
B
A
Si
F
ox
ox
SB
F
(3.22)

2q  N A   Si
Cox
(3.24)
The Threshold Voltage (6)
 We can use the (3.23) for both n-channel device and
p-channel device.
 However, some of the terms and coefficient in (3.23)
have different polarities for the n-channel case and for
the p-channel case.
 The substrate Fermi potential F is negative in nMOS, positive
in pMOS.
 The depletion region charge density QB 0 and QB are negative
in nMOS, positive pMOS.
 The substrate bias coefficient  is positive in nMOS, negative
in pMOS.
 The substrate bias voltage VSB is positive in nMOS, negative in
pMOS.
Example 3.2 (1)
 Calculate the threshold voltage VT0 (@ VSB=0).
 NA = 4 x 1018 cm-3
 ND = 2 x 1020 cm-3
 tox = 26.3 Å
 Nox = 4 x 1010 cm-2
 Sol.
 Calculate the Fermi potentials
 1.45 1010 
kT  ni 
 0.51V
ln 
F ( substrate) 
  0.026V  ln 
18 

q  NA 
4
10


 Calculate the work function difference
 GC  F ( substrate)  F ( gate)  0.51V  0.55V  1.06V
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Example 3.2 (2)
 Sol.(Cont’d)
 The depletion region charge density at VSB = 0
QB 0   2  q  N A   Si  2F ( substrate)
  2 1.6 1019  (4  1018 ) 11.7  8.85 1014  2  0.51
 1.16 106 C/cm 2
 The oxide-interface charge
Qox  q  N ox  1.6  10 19 C  4 1010 cm -2  6.4 109 C/cm 2
 The gate oxide capacitance per unit area
 ox
3.97  8.85 10 14 F/cm

 2.2 106 F/cm 2
Cox 
7
1.6 10 cm
tox
 Combine all components
VT 0   GC  2F ( substrate) 
QB 0 Qox

Cox Cox
 1.06  ( 1.02)  (0.53)  (0.03)  0.46V
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© CMOS Digital Integrated Circuits – 4th Edition
The Threshold Voltage (7)
 The Threshold voltage can be made negative.
 The device which has a negative threshold voltage
called a depletion-type (or normally-on) n-channel
MOSFET.
 Except for this negative threshold voltage, depletiontype MOSFET has same electrical behavior as the
enhancement-type device.
Example 3.3 (1)
 Example- how a nonzero VSB affects VTH.
 the MOS transistor - long channel device
 Sol.
 Calculate the 
 
2  q  N A   si
C ox

1
2 1.6 10 19  4 1018 11.7  8.85 10 14
 0.52V 2
6
2.20  10
 Compute and plot the threshold voltage
VT  VT 0  
  2  V  2 
 0.48  0.52 
40
F
SB
F
 1.01  V  1.01 
SB
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.3 (2)
 Sol.(Cont’d)
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© CMOS Digital Integrated Circuits – 4th Edition
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MOSFET Operation : A Qualitative view(2)
 MOSFET operating in the saturation region
 As the inversion layer near the drain, effective channel length
is decreased.
 Voltage of channel-end remains constant and equal to VDSAT
 Pinched-off area of the channel absorbs most of the excess
voltage drop (VDS–VDSAT).
 A high-field is generated between the channel-end and the
drain boundary.
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MOSFET Operation : A Qualitative view(1)
 For VGS>VT0 , VDS=0
 Drain current ID equal to zero.
 For VGS>VT0 , 0 < VDS < VDSAT
 Drain current ID proportional to VDS
 Called the linear mode (or linear region).
 For VGS>VT0 , VDS = VDSAT
 Inversion charge at the drain is reduced to
zero : pinch-off point.
 For VGS>VT0 , VDSAT < VDS
 A depleted surface region forms adjacent
to the drain and grows toward source.
 Called Saturation mode (or saturation
region)
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MOSFET Current-Voltage Characteristics
 Analysis of the actual three-dimension MOS system is
very complex.
 We will use the gradual channel approximation(GCA)
for establishing the MOSFET current-flow problem.
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Gradual Channel Approximation (1)
 Analysis of the actual three-dimension MOS system is
very complex.
 We will use the gradual channel approximation(GCA)
for establishing the MOSFET current-flow problem.
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Gradual Channel Approximation (2)
 The boundary conditions for the channel voltage Vc are
Vc  y  0   VS  0
Vc  y  L   VDS
(3.25)
 It is assumed that the entire channel region between the source
and the drain is inverted
VGS  VT 0
VGD  VGS  VDS  VT 0
(3.26)
 Let QI(y) be the total mobile charge in the surface inversion layer.
 This charge can be expressed as follows,
QI ( y )  Cox  [VGS  VC ( y )  VT 0 ]
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(3.27)
© CMOS Digital Integrated Circuits – 4th Edition
Gradual Channel Approximation (3)
 Assume that all the mobile electron in the inversion
layer have a constant surface mobility μn. Then we can
express the incremental resistance as follows.
dR  
48
dy
W  n  QI ( y )
(3.28)
© CMOS Digital Integrated Circuits – 4th Edition
Gradual Channel Approximation (4)
 Assume that the channel current density is uniform
across this segment.
 Applying the Ohm’s law for this segment, we can write
the voltage drop along segment dy in the y-direction as
follows,
dVC  I D  dR  
ID
 dy
W  n  QI ( y )
(3.29)
 Integrate this equation along the channel.
L
VDS
0
0
 I D  dR  W  n  
49
QI ( y )  dVc
(3.30)
© CMOS Digital Integrated Circuits – 4th Edition
Gradual Channel Approximation (5)
 We can simplify left-hand side of (3.30) and replace QI(y)
with (3.27).
I D  L  W  n  C ox 
VDS
0
(VGS  VC  VT 0 )  dVC
(3.31)
 Assuming that the channel voltage VC is only variable and it
depends on the position y.
ID 
n  C ox W

2
 [2  (VGS  VT 0 )VDS  VDS
]
2
L
k W
2
I D    [2  (VGS  VT 0 )VDS  VDS
]
2 L
ID 
50
(3.33)
k
2
]
 [2  (VGS  VT 0 )VDS  VDS
2
where
k   n  Cox
and
(3.32)
(3.34)
k  k  W / L
(3.35),(3.36)
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.4 (1)
 Examine the relationship between ID and VDS.
 n = 76.3cm2/V∙s
 Cox=2.2∙10-2 F/m2
 W = 20m
 L = 2m
 VT0=0.48V
 Sol.
 Calculate the k
I D  0.84mA / V 2  2  (VGS  0.48)  VDS  VDS 2 
 ID equation
k  n  Cox 
51
W
20  m
 76.3cm 2 / V  s  2.2 106 F/cm 2 
 1.68mA/V 2
L
2 m
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.4 (2)
 Sol.(Cont’d)
-4
2.5x10
-4
Drain Current ID (A)
2.0x10
VGS=1.0V
-4
1.5x10
-4
1.0x10
VGS=0.8V
-5
5.0x10
0.0
0.0
VGS=0.6V
0.2
0.4
0.6
0.8
1.0
1.2
Drain Voltage VDS (V)
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© CMOS Digital Integrated Circuits – 4th Edition
Gradual Channel Approximation (6)
 We can find out that the drain current in (3.32) is not
valid beyond the boundary between the linear region
and the saturation region. i.e., for,
VDS  VDSAT  VGS  VT 0
(3.37)
 And we can see that the drain current remains
approximately constant around the peak value reached
for beyond the saturation boundary. This saturation
current level can be found simply as follows,
I D ( sat ) 

53
n  C ox W
2

L
n  C ox W
2

L
 [2  (VGS  VT 0 )  (VGS  VT 0 )  (VGS  VT 0 ) 2 ]
 (VGS  VT 0 )
2
(3.38)
© CMOS Digital Integrated Circuits – 4th Edition
Gradual Channel Approximation (7)
 Thus, drain current ,beyond saturation boundary, is a
function of VGS only.
 Figs. 3.17 and 3.18 show the basic current-voltage
characteristics.
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© CMOS Digital Integrated Circuits – 4th Edition
Channel Length Modulation (1)
 Beyond saturation boundary, the effective channel
length, the length of the inversion layer where GCA is
still valid, is different from the channel length L.
 So we have to examine the mechanisms of channel
pinch-off and current flow in saturation mode to
obtain the more exact drain current.
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© CMOS Digital Integrated Circuits – 4th Edition
Channel Length Modulation (2)
 The inversion layer charge at the source end of the
channel is,
QI ( y  0)  Cox  (VGS  VT 0 )
(3.39)
 The inversion layer charge at the drain end of the
channel is,
QI ( y  L)  Cox  (VGS  VT 0  VDS )
(3.40)
 At the edge of saturation,
VDS  VDSAT  VGS  VT 0
(3.41)
QI ( y  L)  0
(3.42)
 We can say the channel is pinched-off at the drain.
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© CMOS Digital Integrated Circuits – 4th Edition
Channel Length Modulation (3)
 If the VDS is increased beyond the edge of saturation,
more area of the channel become pinched-off.
 Then the effective channel length is reduced to,
L  L  L
(3.43)
where ΔL is the length of channel segment with QI=0
57
© CMOS Digital Integrated Circuits – 4th Edition
Channel Length Modulation (4)
 As drain-to-source voltage increased, pinch-off point
moves from the drain end of channel to source.
 The channel voltage at the pinch-off point remains equal
to V because inversion layer charge is zero for L  y  L .
Vc ( y  L)  VDSAT
(3.44)
 We can consider the inverted portion of the surface as a
shortened channel.
 The gradual channel approximation is valid in this region.
 Then we can find the drain current as follows,
I D ( sat ) 
58
n  Cox W
2

L
 (VGS  VT 0 ) 2
(3.45)
© CMOS Digital Integrated Circuits – 4th Edition
Channel Length Modulation (5)
 (3.45) corresponds to a MOSFET with effective channel
length L’, operating in saturation region.
 This phenomenon ,shortening of the effective channel,
called channel length modulation (CLM).
 As L’ decreases with increasing VDS, the saturation current
ID(sat) will also increase with.
 We can modify (3.45) to reflect this drain voltage
dependence.
I D ( sat ) 
59
 C W
1
 n ox   (VGS  VT 0 ) 2
L
L
2
1
L
(3.46)
© CMOS Digital Integrated Circuits – 4th Edition
Channel Length Modulation (6)
 The channel length shortening ΔL is proportional to the
square root of (VDS – VDSAT).
L  VDS  VDSAT
(3.47)
 For simplicity, we use the following empirical relation.
 λ is called channel length modulation coefficient.
L
 1    VDS
1
(3.48)
L
 Assuming that  VDS  1 the saturation current given in
(3.45) can be written as:
I D ( sat ) 
60
n  Cox W
2

L
 (VGS  VT 0 ) 2  (1   VDS )
(3.49)
© CMOS Digital Integrated Circuits – 4th Edition
Channel Length Modulation (7)
 Fig. 3.20 shows the effect of CLM.
 Drain current in saturation region increases linearly with
VDS instead of remaining constant.
61
© CMOS Digital Integrated Circuits – 4th Edition
Substrate Bias Effect (1)
 The derivation of linear-mode and saturation-mode
current-voltage characteristics in the previous pages
has been done under the condition of VSB = 0.
 Positive source-to-substrate voltage affects the
threshold voltage and consequently affects the drain
current.
62
© CMOS Digital Integrated Circuits – 4th Edition
Substrate Bias Effect (2)
 The general expression (3.23) for the threshold voltage
already includes the substrate bias term.
VT (VSB )  VT 0    ( | 2F | VSB  | 2F |)
(3.50)
 We can replace the threshold voltage terms with the
more general VT(VSB) term.
I D (lin) 
n  Cox W

2
 [2  (VGS  VT (VSB ))VDS  VDS
]
L
2
 C W
I D ( sat )  n ox   (VGS  VT (VSB )) 2  (1    VDS )
2
L
63
(3.51)
(3.52)
© CMOS Digital Integrated Circuits – 4th Edition
Substrate Bias Effect (3)
 Finally we arrive at a complete drain current as a
nonlinear function of the terminal voltages.
I D  f (VGS , VDS , VBS )
(3.53)
• Terminal voltages an currents of the nMOS and the pMOS.
64
© CMOS Digital Integrated Circuits – 4th Edition
Current-Voltage equation of the nMOS
ID  0
I D (lin) 
for VGS  VT
n  Cox W
I D ( sat ) 
2

L
2
]
 [2  (VGS  VT )VDS  VDS
n  Cox W
2

(3.54)
L
for
VGS  VT
and VDS  VGS  VT
(3.55)
 (VGS  VT ) 2  (1   VDS )
for
VGS  VT
and VDS  VGS  VT
(3.56)
65
© CMOS Digital Integrated Circuits – 4th Edition
Current-Voltage equation of the pMOS
ID  0
I D (lin) 
I D ( sat ) 
for VGS  VT
 p  Cox W
2

L
 p  Cox W
2

L
(3.57)
2
 [2  (VGS  VT )VDS  VDS
]
for
VGS  VT
and VDS  VGS  VT
(3.58)
 (VGS  VT ) 2  (1   VDS )
for
VGS  VT
and VDS  VGS  VT
(3.59)
66
© CMOS Digital Integrated Circuits – 4th Edition
MOSFET Scaling and Small-Geometry Effects (1)
 The VLSI technology requires high packing density and
small transistor size.
 The reduction of the size is commonly referred to as
scaling.
 There are two types of scaling strategies.
 Full scaling : constant-field scaling
 Constant-voltage scaling
 A constant scaling factor S > 1
Year
Feature Size (m)
Year
Feature Size (nm)
1985
2.5
1999
250
1987
1.7
2001
180
1989
1.2
2003
130
1991
1.0
2005
90
1993
0.8
2007
65
1995
0.5
2009
45
1997
0.35
2011
32
• Table 3.1 Reduction of minimum feature size
67
© CMOS Digital Integrated Circuits – 4th Edition
68
© CMOS Digital Integrated Circuits – 4th Edition
MOSFET Scaling and Small-Geometry Effects (2)
 The primed quantities in Fig 3.24 indicate the scaled
dimensions and doping density.
 The scaling of all dimensions by a factor of S > 1
leads to the reduction of the area occupied by the
transistor by factor of S2.
69
© CMOS Digital Integrated Circuits – 4th Edition
Full Scaling (1)
 This scaling option attempts to preserve the
magnitude if internal electric fields in the MOSFET.
 To achieve this goal, potentials must be scaled down
proportionally.
 Potential scaling affects the threshold voltage.
 Charge densities must be increased by a factor of S in
order to maintain the field condition.
70
© CMOS Digital Integrated Circuits – 4th Edition
Full Scaling (2)
 Table 3.2
Quantity
Channel length
Channel width
Gate oxide thickness
Junction depth
Power supply voltage
Threshold voltage
Before scaling
L
W
tox
xj
VDD
VT0
NA
ND
Doping density
After scaling
L’=L/S
W’=W/S
t’ox =tox /S
x’j = xj /S
V’DD = VDD /S
V’T0 = VT0/S
N’A = S∙NA
N’D = S∙ND
• Full scaling of MOSFET dimensions, potentials and doping
densities
 The gate oxide capacitance per unit area is changed as
follows.
 ox
 ox
Cox 
71

tox
S
tox
 S  Cox
(3.60)
© CMOS Digital Integrated Circuits – 4th Edition
Full Scaling (3)
 The aspect ratio W/L of the MOSFET will remain
unchanged under the scaling.
 The transconductance parameter kn will also be scaled
by factor of S.
 The linear-mode drain current of the scaled MOSFET
can be found as:
kn
  VT )  VDS
  V DS2 ]
 [2  (VGS
2
S  kn 1
I (lin)
2
] D

 2  [2  (VGS  VT ) VDS  VDS
S
2 S
I D (lin) 
72
(3.61)
© CMOS Digital Integrated Circuits – 4th Edition
Full Scaling (4)
 The saturation-mode drain current is also reduced by
the same scaling factor.
kn
  VT ) 2
 (VGS
2
S  kn 1
I D ( sat )
2

  (VGS  VT ) 
2 S2
S
I D ( sat ) 
(3.62)
 The power dissipation of the MOSFET before scaling
can be written as follows,
P  I D  VDS
(3.63)
 Full scaling reduces both current and voltage.
 
P  I D VDS
73
1
P

I

V

D
DS
S2
S2
(3.64)
© CMOS Digital Integrated Circuits – 4th Edition
Effects of Full Scaling
 Table 3.3
Quantity
Oxide capacitance
Drain current
Power dissipation
Power density
Before scaling
Cox
ID
P
P / Area
After scaling
C’ox = S ∙ Cox
I’D = ID / S
P’ = P / S2
P’ / Area’ = P / Area
• Effects of full scaling upon key device characteristics
 Scaling of voltage (full scaling) may not be very
practical in many cases.
74
© CMOS Digital Integrated Circuits – 4th Edition
Constant-Voltage Scaling (1)
 In constant-voltage scaling, all dimension of the
MOSFET are reduced by a factor of S.
 The power supply voltage dose not be changed.
 The doping densities must be increased by a factor of
S2 in order to preserve the charge-field relation.
 Table 3.4
Quantity
Dimensions
Voltages
Doping densities
Before scaling
W, L, tox ,xj
VDD , VT
N A , ND
After scaling
Reduced by S
Remain unchanged
Increased by S2
• Constant-voltage scaling of MOSFET dimensions, potentials, and
doping densities
75
© CMOS Digital Integrated Circuits – 4th Edition
Constant-Voltage Scaling (2)
 The gate oxide capacitance per unit area Cox is
increased by factor if S.
 The transconductance parameter is also increased by S
 The drain current under the constant-voltage scaling is
given by
kn
  VT )  VDS
  V DS2 ]
 [2  (VGS
2
S  kn
2
]  S  I D (lin)

 [2  (VGS  VT )  VDS  VDS
2
I D (lin) 
kn
S  kn
  VT ) 2 
 (VGS  VT ) 2  S  I D ( sat )
I D ( sat )   (VGS
2
2
76
(3.65)
(3.66)
© CMOS Digital Integrated Circuits – 4th Edition
Constant-Voltage Scaling (3)
 Table 3.5
Quantity
Oxide capacitance
Drain current
Power dissipation
Power density
Before scaling
Cox
After scaling
C’ox = S ∙ Cox
ID
P
P / Area
I’D = S ∙ID
P’ = S ∙ P
P’ / Area’ = S3 ∙ (P / Area)
• Effects of constant-voltage scaling upon key device characteristics
 The Power dissipation of the MOSFET increases by a
factor of S.
  ( S  I D )  VDS  S  P
P  I D VDS
77
(3.67)
© CMOS Digital Integrated Circuits – 4th Edition
Current-Voltage Equations for
Short Channel Devices (1)
 Short channel device
 Channel length is on the same order of magnitude as the
depletion region thickness of the source and drain junction.
 Effective channel length is approximately equal to the source
and drain junction depth.
 The limitations imposed on electron drift characteristics in the
channel.
 The modification of the threshold voltage due to the
shortening channel length.
78
© CMOS Digital Integrated Circuits – 4th Edition
Current-Voltage Equations for
Short Channel Devices (2)
 The dependence of the surface electron mobility on the
vertical electric field can be expressed by the following
empirical formula:
 n  eff  
 no
1    Ex

 no
 ox
1
 VGS  Vc  y  
tox Si
(3.68)
 Where n 0 is the low-field surface electron mobility and 
is an empirical factor.
 (3.68) can be approximated by
n (eff ) 
79
n 0
1    (VGS  VT )
(3.69)
© CMOS Digital Integrated Circuits – 4th Edition
Carrier Drift Velocity
vsat
Ec , n
Ec , p
 The lateral electric field Ey along the channel increases,
as the effective channel length decreased.
 Drift velocity tends to saturate at high electric fields.
80
© CMOS Digital Integrated Circuits – 4th Edition
Carrier Drift Velocity: Model 1
 Velocity saturation has very significant implications
upon the current-voltage characteristics of the shortchannel MOSFET.
vd  n (eff )  E y
for
E y  Ec
vd  vsat
for
E y  Ec
(3.70)
 This model1 is very simple but has bad behavior.
81
© CMOS Digital Integrated Circuits – 4th Edition
Carrier Drift Velocity: Model 2
 To overcome this, model2 can be derived.
vd  vsat 
E y / Ec
1
  E y   
1    
  Ec  
 n (eff ) 
Ey
1
  E y   
1    
  Ec  
(3.71)
 The disadvantage of model2 is that infinite electric
field at drain is required to have a velocity saturation.
82
© CMOS Digital Integrated Circuits – 4th Edition
Carrier Drift Velocity: Model 3 & This
book’s Model
 To overcome this drawback, model3 is given by
vd  n (eff ) 
Ey
 Ey 
1 

E
2
 c
vd  vsat
for E y  2 Ec
for E y  2 Ec
(3.72)
 For simplicity, (3.71) with α=1 will be used after this.
vd  n (eff ) 
Ey
 Ey 
1  
 Ec 
vd  vsat
for
E y  Ec
for
E y  Ec
(3.73)
(3.74)
 This model enough for hand analysis
83
© CMOS Digital Integrated Circuits – 4th Edition
Carrier Drift Velocity Models
vsat
Ec , n
84
Ec , p
© CMOS Digital Integrated Circuits – 4th Edition
Modified Equations for Short Channel Devices
 With velocity saturation, the current equation should
be modified.
I D (lin)  W  vd  
Leff
0
I D (lin)  W  n
q  n( x)  dx  W  vd  | QI |
Ey
(3.75)
 Cox (VGS  Vc ( y )  VT )
(3.76)
[Cox (VGS  V C ( y )  VT ) 
I D (lin)
]  dV ( y )
W  n  Ec
E 
1  y 
 Ec 
 Since Ey=dV(y)/dy
L
VDS
0
0
 I D (lin)  dy  W  n 
(3.77)
85
© CMOS Digital Integrated Circuits – 4th Edition
Modified Equation in Linear Region
 We can have current equation incorporating the
mobility variation.
I D (lin) 
n  Cox W
2

1
2
 [2  (VGS  VT ) VDS  VDS
]
L
 VDS 
1 

(3.78)
E
L
 c 

 This equation is very similar to (3.55) except one division term
due to mobility reduction.
86
© CMOS Digital Integrated Circuits – 4th Edition
Modified Equation in Saturation Region
 Consider the saturation-mode drain current under the
assumption that carrier velocity in the channel has
already reached its limit value.
I D ( sat )  W  vsat  
Leff
0
q  n( x)  dx  W  vsat  | QI |
(3.79)
 Since the channel-end voltage is equal to VDSAT , the
saturation current can be found as follows:
I D ( sat )  W  vsat  Cox  (VGS  VT  VDSAT )
87
(3.80)
© CMOS Digital Integrated Circuits – 4th Edition
VDSAT
 At the boundary of saturation and linear regions, the
drain-source voltage of MOS transistor is VDSAT and
ID(lin) = ID(sat).
VDSAT 
(VGS  VT )  Ec L
(VGS  VT )  Ec L
(3.81)
 Saturation current equation can be rewritten as
(VGS  VT ) 2
I D ( sat )  W  vsat  Cox 
(VGS  VT )  Ec L

88
nCox W Ec L  (VGS  VT ) 2
2


L (VGS  VT )  Ec L
(3.82)
(3.83)
© CMOS Digital Integrated Circuits – 4th Edition
Current-Voltage Equations for
Short Channel nMOS Transistor
I D  I leakage  0,
I D (lin) 
for VGS  VT
(3.84)
n  Cox W
2
1
2
 
 [2  (VGS  VT )  VDS  VDS
]
(3.85)
L
 VDS 
1 

E
L
 c 
(VGS  VT )  Ec L
V

V

V
for GS
and DS
T
(VGS  VT )  Ec L
(VGS  VT ) 2
I D ( sat )  W  vsat ,n  Cox 
 (1    VDS )
(VGS  VT )  Ec L
for
89
(3.86)
VGS  VT and V
DS 
(VGS  VT )  Ec L
(VGS  VT )  Ec L
© CMOS Digital Integrated Circuits – 4th Edition
Current-Voltage Equations for
Short Channel pMOS Transistor
I D  I leakage  0,
I D (lin) 
for VGS  VT
 p  Cox W
2

(3.87)
1
2
]
 [2  (VSG  | VT |)  VSD  VSD
(3.88)
L
 VSD 
1 

(VSG  | VT |)  Ec L
 Ec L 
V

V

V
for SG
SD
T and
(VSS  | VT |)  Ec L

(VSG  | VT |) 2
I D ( sat )  W  vsat , p  Cox 
 (1    VSD )
(VSG  | VT |)  Ec L
for
90
(3.89)
VSG  VT and V
SD 
(VSG  | VT |)  Ec L
(VSG  | VT |)  Ec L
© CMOS Digital Integrated Circuits – 4th Edition
Drain Current Variations for Long & Short
Channel Devices in 65nm CMOS Process
nMOS
91
pMOS
© CMOS Digital Integrated Circuits – 4th Edition
Measurement of Parameter(1)
 The MOSFET current-voltage equations (3.84) through
(3.89) are very useful for simple calculation.
 However, accuracy of these equations is fairly limited
because of several simplifications and approximations.
 To achieve maximum possible accuracy, we must
determine the parameters appearing in the equations
carefully.
92
© CMOS Digital Integrated Circuits – 4th Edition
Measurement of Parameter(2)
 The model parameters
 Zero-bias threshold voltage VT0 .
 The substrate-bias coefficient  .
 Channel length modulation coefficient  .
 Following transconductance parameters:
W
L
(3.90)
W
k p   p  Cox 
L
(3.91)
kn  n  Cox 
93
© CMOS Digital Integrated Circuits – 4th Edition
Measurement of Parameter(3)
 Drain current measured for different values of the
gate-to-source voltage VGS.
 Saturation condition is always satisfied.
94
© CMOS Digital Integrated Circuits – 4th Edition
Measurement of Parameter(4)
 Neglecting the channel length modulation effect for
simplicity, the drain current is described by
(VGS  VT 0 ) 2
kn EC L  (VGS  VT 0 ) 2
I D ( sat )  W  vsat  Cox 
 
(VGS  VT 0 )  EC L 2 (VGS  VT 0 )  EC L
(3.92)
 Now, the square root of the drain current can be
written as a linear function of the gate-to-source
voltage.
k
(3.93)
I D  n VGS  VT 0 
2
 If the square root of the measured drain current
valued is plotted against the VGS, we can find kn , VT0
and  .
95
© CMOS Digital Integrated Circuits – 4th Edition
Measurement of Parameter(5)
 By extrapolating the curves to zero-drain current
(voltage-axis intercept point), we can find the
threshold voltage VT that correspond the each VSB
value.
 The slope of each curves is equal to the square root of
kn/2.
 Using one of the available V values, the substrate bias
coefficient  can be found from

96
VT VSB   VT 0
2F  VSB 
2F
(3.94)
© CMOS Digital Integrated Circuits – 4th Edition
Measurement of Parameter(6)
 The drain current in the saturation region is given by
I D ( sat ) 
n  Cox W

 (VGS  VT ) 2  (1   VDS )
(3.95)
L
2
 The ratio of the measured drain current value is
I D 2 1    VDS 2

I D1 1    VDS 1
(3.96)
 We can calculate  from this equation.
97
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.5 (1)
 Determine the type of the device, and calculate the
parameters kn, VT0, VT,  and .
 F = –0.505 V
V GS (V)
0.6
0.6
0.65
0.65
0.9
1.2
V DS (V)
0.6
1.2
0.6
1.2
1.2
1.2
V SB (V)
0
0
0
0.3
0.3
0.3
I D ( μ A)
6
10
12
5
44
156
 Sol.
 Assume that the transistor is enhancement-type.
(VGS  VT ) 2
(1   VDS )
I D  W  vsat  Cox 
(VGS  VT )  Ec L
98
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.5 (2)
 Sol.(Cont’d)
 Using any two current-voltage pairs,
I D1 (VGS 1  VT 0 ) 2

 VT 0 
I D 2 (VGS 2  VT 0 ) 2
 kn :
 VT :
 
 
99
6 A
 0.65V  0.6V
12  A
6 A
1
12  A
 0.48V, I D 
kn
k
 (VGS  VT ) 2  I D  n  (VGS  VT )
2
2
I  ID2
12 A  6 A
kn
 D1

 20 103 A1/2 / V,
2
VGS1  VGS 2
0.65V  0.6V
kn  2  (20  10 3 ) 2  8  10 4 A / V 2  0.8mA/V 2
VT (VSB  0.3V)  VGS 

VT (VSB  0.3V)  VT 0
2F  VSB 
2F
2  ID
2  5 A
 0.65V 
 0.54V
0.8mA / V 2
kn

0.54V  0.48V
 0.43V1/ 2
1.01V  0.3V  1.01V
1   VDS1
I
I D1  I D 2
10 uA  6 uA

 3.33
 D1 ,  
1   VDS 2
ID2
VDS 1 I D 2  V DS 2 I D 1 1.2V  6 uA  0.6V  10 uA
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (1)
 Consider the modification of the threshold voltage in a
small geometry devices.
 Effects which cause threshold voltage shift.
 Non-uniform vertical and lateral doping concentration.
 Short channel.
 Narrow width.
 Drain induced barrier lowering.
 If a device has a non-uniform vertical doping
concentration, the γ term in (3.23) should be modified.
100
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (2)
 If there are two different substrate-bias coefficient, γ1
and γ2 with different doping concentration of Nch and
Nsub can be derived as below.
1 
2q  N ch   Si
Cox
,
2 
2q  N sub   Si
Cox
(3.97), (3.98)
 Using these two term, new substrate-bias coefficient
K1 and K2 can be defined as below.
K1   2  2  K 2  | 2F | VBS  max|
K2 
101
(3.99)
( 1   2 )( | 2F | VBS  | 2F |
2 | 2F |( | 2F | VBS  max|  | 2F |)  VBS  max
(3.100)
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (3)
 Using these equations, we can find the threshold
voltage considering non-uniform vertical doping
concentration.
VT  VT 0  K1( | 2F  VSB |  | 2F |)  K 2  VSB
102
(3.101)
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (4)
 In short channel MOS
transistors, the n+ drain
and source diffusion
regions in the p-type
substrate induce a
significant amount of
depletion charge.
 Threshold voltage value
found by using (3.23) is
larger than the actual
threshold voltage of
short-channel MOSFET.
103
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (5)
 Following the modification of the bulk charge term,
the threshold voltage of the short-channel MOSFET
can be written as
VT 0 ( short chnnel )  VT 0  VT 0
(3.102)
 The reduction term actually represents the amount of
charge differential between a rectangular depletion
region and a trapezoidal depletion region.
 The bulk depletion region charge contained within the
trapezoidal region is
LS  LD
)  2  q   Si  N A  | 2F |
QB 0  (1 
2L
104
(3.103)
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (5)
 The edges of the source and drain diffusion regions
are represented by quarter-circular arcs, each with
radius equal to the junction depth, xj.
 The vertical extent of the bulk depletion region into
the substrate is represented by xdm.
 The junction depletion region depths can be
approximated by
2   Si
xdS 
 0
q  NA
2   Si
xdD 
 (0  VDS )
q  NA
105
(3.104)
where
0 
(3.105)
N N
kT
 ln( D 2 A )
q
ni
(3.106)
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (5)
 We find the following relationship between ΔLD and
the depletion region depths.
2
( x j  xdD )2  xdm
 ( x j  LD ) 2
(3.107)
2
2
L2D  2  x j  LD  xdm
 xdD
 2  x j  xdD  0
(3.108)
2
2
LD   x j  x 2j  ( xdm
 xdD
)  2 x j xdD
2 xdD
 xj  ( 1
 1)
xj
106
(3.109)
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage for Small-Geometry Devices (6)
 Similarly,
LS  x j  ( 1 
2 xdS
 1)
xj
(3.110)
 The amount of threshold voltage reduction ΔVT0 due
to short-channel effect can be found as
xj
2 xdS
2 xdD
1
VT 0, SCE 
 2q Si N A | 2F | 
 [( 1 
 1)  ( 1 
 1)]
Cox
xj
xj
2L
(3.111)
107
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.6 (1)
 Plot the variation of the VT0 as a function of the
channel length.
 NA = 4 x 1018 cm-3,
 ND (gate) = 2 x 1020 cm-3,
 tox = 1.6 nm,
 Nox = 4 x 1010 cm-2,
 ND (diffusion)= 1017 cm-3.
 NI = 2 x 1011 cm-2
 xj = 32 nm.
 VDS = VSB = 0
 F = –0.505 V
108
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.6 (2)
 Sol.
 VT0 :
q  NI
1.6  1019  2  1017
VT 0  0.48V 
 0.48V 
 0.494V
Cox
2.2 106
 Junction built-in voltage:
 ND  N A 
 1017  4 1018 
kT
0 
 ln 
  0.026V  ln 
  0.91V
2
20
2.1
10
q
n



i


 Junction depletion regions :
2   Si
2 11.7  8.85 1014
xdS  xdD 
 0 
 0.91
q  NA
1.6 1019  4 1018
 1.72 106 cm  17.2nm
 VT0 :
VT 0 
 

x j 
2x
2x
1
 2q Si N A 2F 
  1  dS  1   1  dD  1 
 

Cox
xj
xj
2 L 
 


1.2  106 C/cm 2 32nm 
2 17.2nm 
1




 1

L 
2.2 106 F/cm 2
32nm

VT 0 ( shortchannel )  0.494 V  0.24 V
109
32
L[nm]
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.6 (3)
 Sol.(Cont’d)
0.630
0.615
THreshold Voltage (V)
0.600
0.585
0.570
0.555
0.540
0.525
0.510
0.0
0.5
1.0
1.5
2.0
Channel Length (m)
110
© CMOS Digital Integrated Circuits – 4th Edition
Narrow-Width Effects (1)
 Narrow-width devices
 Channel width W on the same order of magnitude as the
maximum depletion region thickness xdm
 The narrow-width MOSFETs also exhibit typical
characteristics which are not accounted for by the
conventional GCA analysis.
 Actual threshold voltage is larger than that predicted
by the (3.23)
111
© CMOS Digital Integrated Circuits – 4th Edition
Narrow-Width Effects (2)
 The gate electrode overlaps with the field oxide.
 Shallow depletion region forms underneath this FOXoverlap area.
 The actual threshold voltage increases as a result of
this extra depletion charge.
112
© CMOS Digital Integrated Circuits – 4th Edition
Narrow-Width Effects (3)
 The additional contribution to the threshold voltage
due to narrow-width effects can be modified as
follows:
VT 0 (narrow width)  VT 0  VT 0
VT 0, NWE 
  xdm
1
 2q Si N A | 2F | 
Cox
W
(3.112)
(3.113)
  is an empirical parameter depending on the shape of the
fringe depletion region.
 If the depletion region edges are modeled by quarter-circular
arcs, the parameter  can be found as

113

2
(3.114)
© CMOS Digital Integrated Circuits – 4th Edition
Narrow-Width Effects (4)
 Threshold voltage roll-up due to narrow width effect
114
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (1)
 In small-geometry MOSFET the potential barrier is
controlled by both the VGS and VDS.
 Drain-induced barrier lowering (DIBL)
 Increasing of VDS cause decreasing of potential barrier.
 The reduction of the potential barrier reduces the threshold
voltage.
 It allows electron flow between the source and the drain, even
if the gate-to-source voltage is lower than the threshold
voltage.
115
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (2)
 The channel current that flows under the condition of
VGS < VT0 is called subthreshold current.
qDnWxc n0 qkTr kTq ( AVGS  BVDS )
I D ( subthreshold ) 
e e
LB
(3.115)
 xc is the subthreshold channel depth.
 Dn is the electron diffusion coefficient.
 LB is the length of the barrier region in the channel.
 r is a reference potential.
116
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (3)
 To reduce threshold voltage roll-off and punch
through, a halo implant (Fig. 2.13) is used.
 As the channel length increases, the mid channel
dominates halo-doped region and the threshold
voltage of long channel device is lower : reverse short
channel effect (RSCE)
117
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (4)
 Another effects caused by halo implant are draininduced threshold shift (DITS) by ΔVT,DITS and low
output resistance in long channel devices.
 The overall threshold voltage shift in small geometry
devices can be expressed as
VT  VT 0  K1( | 2F  VSB |  | 2F |  K 2 VSB
(3.116)
VT , SCE  VT , NWE  VDIBL  VT , RSCE  VT , DITS
118
© CMOS Digital Integrated Circuits – 4th Edition
Threshold Voltage Variation : f(L, VDS)
119
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.7 (1)
 How a non-uniform doping, short-cannel effect and
DIBL affect the threshold voltage of the MOS Transistor.
 Sol.
 Calculate the depletion width Xdep and characteristic length lt
X dep 
2  si  2 F  V SB 
q  N D EP
 2.03  10  8 
lt 


2  1.04  10  10 1.02  V SB 
0.515  10 6
1.02  V SB 
 si  TO XE  X dep
E P SR O X
 1  D VT 2  V SB 
1.04  10  10  2.25  10  9  X dep
 2.45  10  10 
3.9
 1  (  0.032)  V SB 
X dep  1  0.032  V SB 
 2.45  10  10  4 1.02  V SB   1  0.032  V SB 
120
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.7 (2)
 Sol.(Cont’d)
X dep 0 
2 si 2 F
q  NDEP

2 1.04  10 10  1.02
0.515  10 6
 2.03  10 8
lt 0 
 si  TOXE  X dep 0
EPSROX
1.04  10 10  2.25  10 9  2.03  10 8

3.9
 3.49  10 14
121
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.7 (3)
 Sol.(Cont’d)
 Compute the threshold voltage shift by each contribution
VT  VT 0  K 1

  2  V
F
0 .5
L 

co sh  D S U B  eff   1
lt 0 

 0 .5 3  0 .6 7 3 
2 F

SB



DVT 0

  V  2
 K 2V S B  0 .5 
bi
F


L eff 

1

 co sh  D V T 1 



lt 





 E T A0 V DS
 1 .0 2  V
SB


1 .0 2  0 .0 1  V S B




0 .5
1
   0 .2 5 1  1 .0 2  
 0 .0 0 5 8  V D S
 0 .5  
9




4 0  1 0 9 
40  10 
co sh  0 .0 1 
1
 co sh  2 
  1 
14 
3
.4
9
1
0

l


t




 0 .5 3  0 .6 7 3 

 1 .0 2  V
0 .3 8
SB


1 .0 2  0 .0 1  V S B

0 .5
 0 .0 0 5 8  V D S
co sh 1 1 4 6 1   1


3 .2 6  1 0 2
 1
co sh 
 4 1 .0 2  V S B   1  0 .0 3 2  V S B  


 L o n g ch an n el m o d el  N o n -u n ifo rm later al d o p in g p ro file
 S h o rt ch an n eleffect  D IB L
122
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.7 (4)
 Sol.(Cont’d)
 When VDS = 1.2V and VSB = 0.1V
VT  0.53  0.673 

SB
SB
0.38


3.26  102
 1
cosh 
 4 1.02  VSB   1  0.032  VSB  


 0.53  0.673 

 1.02  V  1.02   0.01V

0.5
 0.0058  VDS
cosh 11461  1
 1.02  0.1  1.02   0.01 0.1
0.38

0.5
 0.0058 1.2
cosh 11461  1


3.26  102
 1
cosh 
 4 1.02  0.1  1  0.032  0.1 


 Long channel model  Non-uniform lateral doping profile
Shortchanneleffect  DIBL
 0.571  0.001  0  0  0.572
123
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.7 (5)
 Sol.(Cont’d)
 When VDS = 0.6V and VSB = 0.6V
VT  0.53  0.673 

SB
SB
0.38


3.26  102

 1
cosh
 4 1.02  VSB   1  0.032  VSB  


 0.53  0.673 

 1.02  V  1.02   0.01V

0.5
 0.0058  VDS
cosh 11461  1
 1.02  0.3  1.02   0.01 0.3
0.38

0.5
 0.0058  0.6
cosh 11461  1


3.26  102


cosh
1
 4 1.02  0.3  1  0.032  0.3 


 Long channel model  Non-uniform lateral doping profile
Shortchanneleffect  DIBL
 0.624  0.003  0  0  0.627
124
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (5)
 Punch-through
 For large drain-bias voltage, the depletion region surrounding
the drain and the source can merge.
 Gate voltage loses its control upon the drain current.
 Current rise sharply once it occurs.
 Pinhole
 Localized sites of non-uniform oxide growth.
 It may cause electrical shorts between the gate electrode and
substrate.
 Oxide breakdown
 The oxide electric field perpendicular to the surface larger
than a certain breakdown field.
 Silicon-dioxide layer sustain permanent damage.
125
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (7)
 Reliability problem
 Electrons and holes gaining high kinetic energies in the
electric field (hot carriers) may be injected into gate oxide.
• Degrading the current-voltage characteristics.
126
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (8)
 Reliability problem (cont)
 The channel hot-electron (CHE) effect
• Lateral electric field in the drain end of the channel accelerates
the electrons.
• The electron with enough kinetic energy are injected into the
oxide.
• Trapped in defect sites in the oxide or create interface states at
the silicon-oxide interface.
127
© CMOS Digital Integrated Circuits – 4th Edition
Other Limitations Imposed by SmallDevice Geometries (9)
 Reliability problem (cont)
 Nanometer-scale CMOS devices case
• Time-dependent dielectric breakdown (TDDB)
• Bias temperature instability (BTI)
 Other reliability concerns for small-geometry devices
• Interconnect damage through electromigration
• Electrostatic discharge (ESD)
• Electrical over-stress (EOS)
128
© CMOS Digital Integrated Circuits – 4th Edition
Supply Voltage Variations
core voltage contour
IBM Power6 voltage contour
129
© CMOS Digital Integrated Circuits – 4th Edition
Temperature Variations
Temperature contour of dual-core AMD Athlon II 240 processor
130
© CMOS Digital Integrated Circuits – 4th Edition
Variability in Nanometer-Scale Technologies (1)
 Integrated circuit designers are facing new challenge
of variability and aging.
 Source of transistor variability
 Process-induced
 Environmental uncertainties
 Physical limit-induced
131
© CMOS Digital Integrated Circuits – 4th Edition
Variability in Nanometer-Scale Technologies (2)
 Physical limited-induced source.
 Random dopant fluctuation (RDF)
 Line-edge roughness (LER) & Line-width roughness (LWR)
• Increase the subthreshold current
• Degrade the threshold voltage characteristics
132
© CMOS Digital Integrated Circuits – 4th Edition
Variability in Nanometer-Scale Technologies (3)
 Process-induced variability
 Transistor length variation
 Mobility variation
 Irregular chemical mechanical polishing (CMP)
 The Lithography-induced variation
 Optical proximity correction (OPC) error
 Mask process error
 Stepper error
 Layout irregularity
 Resist irregularity
133
© CMOS Digital Integrated Circuits – 4th Edition
Variability in Nanometer-Scale Technologies (4)
• Threshold variation of MOSFET transistor in 90nm technology
 The impact of variability in digital integrated circuits
can be found in many aspects such as yield, speed,
and power consumption.
134
© CMOS Digital Integrated Circuits – 4th Edition
Variability in Nanometer-Scale Technologies (5)
 The variation can be classified based on scale
 Within die (WID) variation
• Variation across a die
• Process induced, random, supply and temperature variation
• Layout dependent
 Die-to-die (D2D) variation
• Variation across a wafer, systematic.
 Wafer-to-wafer (W2W) variation
• Variation between wafers
 Lot-to-lot variation
• Variation between lots
135
© CMOS Digital Integrated Circuits – 4th Edition
Negative Bias Temperature Instability: NBTI
 If a negative voltage is applied to a pMOS gate, the
threshold voltage will be shifted and the current
through channel will be reduced due to trap : NBTI
 The threshold voltage increase reduces the noise
margin and the operating speed of the digital circuit.
136
© CMOS Digital Integrated Circuits – 4th Edition
MOSFET Capacitor (1)
 The on-chip capacitance found in MOS circuit are in
general complicated functions of the layout
geometries and the manufacturing processes.
 We will develop simple approximations for the on-chip
MOSFET capacitances.
137
© CMOS Digital Integrated Circuits – 4th Edition
MOSFET Capacitor (2)
 The channel length is
given by
L  LM  2  LD
(3.117)
 Additional p+ region is
to prevent the formation
of any unwanted
(parasitic) channels
between two
neighboring n+diffusion
region.
138
© CMOS Digital Integrated Circuits – 4th Edition
MOSFET Capacitor (3)
 Parasitic device capacitances
can be classified into two
major group
 Oxide-related capacitance
 Junction capacitance
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© CMOS Digital Integrated Circuits – 4th Edition
Oxide-related Capacitances (1)
 The gate electrode overlaps both the source region
and the drain region at the edges.
 The two overlap capacitances that arise as a result of this
structural arrangement.
• CGD(overlap)
• CGS(overlap)
 The overlap capacitances can be found as
CGS (overlap)  Cox W  LD
CGD (overlap)  Cox W  LD
with
140
Cox 
(3.118)
 ox
tox
(3.119)
© CMOS Digital Integrated Circuits – 4th Edition
Oxide-related Capacitances (2)
 Capacitances which
result from the
interaction between the
gate voltage and the
channel charge.
 Cgs ,Cgd ,Cgb
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Oxide-related Capacitances (2)
 Cut-off mode (Fig3.31.a)
 The surface is not inverted.
 No conducting channel between source and drain
• Cgs = Cgd = 0
 The gate-to-substrate capacitance can be approximated by
Cgb  Cox W  L
(3.120)
 Linear mode (Fig3.31.b)
 The inverted channel extends across the MOSFET.
 Conducting inversion layer shields the substrate from the gate
electric field : Cgb = 0
 The distributed gate-to-channel capacitance (equal S,D)
1
Cgs  Cgd   Cox W  L
2
142
(3.121)
© CMOS Digital Integrated Circuits – 4th Edition
Oxide-related Capacitances (3)
 Saturation mode (Fig3.31.c)
 The inversion region is pinched off.
 The gate-to-drain capacitance component is equal to zero
• Cgd = 0
 Source still linked to the conducting channel.
• Shielding effect still remain : Cgb = 0
 The distributed gate-to-channel capacitance as seen between
the gate and the source can be approximated by
2
Cgs   Cox W  L
3
143
(3.122)
© CMOS Digital Integrated Circuits – 4th Edition
Oxide-related Capacitances (4)
 Table 3.6
Capacitance
Cut-off
Linear
Cgb (total)
CoxWL
0
Saturation
0
Cgd (total)
CoxWLD
1/2CoxWL + CoxWLD
CoxWLD
Cgs (total)
CoxWLD
1/2CoxWL + CoxWLD
2/3CoxWL + CoxWLD
 Table 3.6 is lists a summary of the approximate oxide
capacitance values.
 We have to combine the distributed Cgs and Cgd values
found here with the relevant overlap capacitance
values, in order to calculate the total capacitance
between the external device terminals.
144
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Oxide-related Capacitances (5)
 Variation of the distributed (gate-to-channel) oxide
capacitances as function of gate-to-source voltage.
145
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Junction Capacitances (1)
Junction
Area
Type
1
W∙xj
n+/p
2
Y∙xj
n+/p+
3
W∙xj
n+/p+
4
Y∙xj
n+/p+
5
W∙Y
n+/p
 Consider the voltage-dependent source-substrate and
drain-substrate junction capacitances : Csb , Cdb
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© CMOS Digital Integrated Circuits – 4th Edition
Junction Capacitances (2)
 Csb and Cdb are due to the depletion charge
surrounding the respective source or drain diffusion
regions embedded in the substrate.
 both of these junctions are reverse-biased under normal
operating conditions.
 The amount of junction capacitance is a function of the
applied terminal voltages.
 Junction capacitances associated with sidewalls (2,3,4) will be
different from the other junction capacitance.
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Junction Capacitances (3)
 Assuming that the reverse bias voltage is given V.
 The depletion region thickness can be found as follows:
xd 
2   Si N A  N D

 (0  V )
q
N A  ND
(3.123)
 The built-in junction potential is calculated as
0 
N N
kT
 ln( A 2 D )
q
ni
(3.124)
 Junction is forward-biased for positive bias voltage V, and
reverse-biased for negative bias voltage.
 The depletion region charge stored in this area is:
Qj  A q  (
N A  ND
N N
)  xd  A 2   Si  q  A D  (0  V )
N A  ND
N A  ND
(3.125)
• A indicates the junction area.
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© CMOS Digital Integrated Circuits – 4th Edition
Junction Capacitances (4)
 The junction capacitance associated with the depletion region
is defined as
Cj 
dQ j
dV
(3.126)
 By differentiating (3.125) we can obtain the expression for the
junction capacitance as follows,
C j (V )  A
 Si  q
2
(
N A  ND
1
)
N A  ND
0  V
(3.127)
 This expression can be rewritten in more general form
C j (V ) 
A  C j0
V
(1  ) m
0
(3.128)
• The parameter m is called the grading coefficient.
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Junction Capacitances (5)
 The zero-bias junction capacitance per unit area Cj0 is defined
as :
 q N  N
1
C j 0  Si  ( A D ) 
(3.129)
2
N A  N D 0
 The value of the junction capacitance Cj given by (3.128)
ultimately depends on the external bias voltage that is applied
across the pn-junction.
 Equivalent large-signal capacitance can be defined as follows:
Ceq 
V2
Q Q j (V2 )  Q j (V1 )
1


  C j (V )  dV
V
V2  V1
V2  V1 V1
(3.130)
 By substituting (3.128) into (3.130)
1 m
1 m





V2
V1
  1     1   
Ceq  
(V2  V1 )(1  m) 
0 
0  



2  A  C j 0  0
150
(3.131)
© CMOS Digital Integrated Circuits – 4th Edition
Junction Capacitances (6)
 For special case of abrupt pn-junctions, (3.131) becomes,
2  A  C j 0  0 
V2
V1 
Ceq  
  1  1 
(V2  V1 ) 
0
0 
(3.132)
 This equation can be rewritten in a simpler form by defining a
dimensionless coefficient Keq as follows:
Ceq  A  C j 0  K eq
K eq  
2 0
V2  V1
 ( 0  V2  0  V1 )
(3.133)
(3.134)
• Keq is the voltage equivalence factor (0<Keq <1)
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© CMOS Digital Integrated Circuits – 4th Edition
Example 3.8 (1)
 Calculate the junction capacitance per unit area : Ceq
 ND = 2.2Ⅹ1018 cm-3
 NA = 1.6Ⅹ1018 cm-3
 A = 10umⅩ10um
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© CMOS Digital Integrated Circuits – 4th Edition
Example 3.8 (2)
 Sol.
 Junction built-in voltage
N A  ND
kT
1.6 1018  2.2 1018
 ln(
)  0.026V  ln(
)  0.97V
0 
q
ni 2
2.11020
 Calculate zero-bias junction capacitance : Cj0
C j0 
 si  q  N A  N D  1


2  N A  N D  0
11.7  8.85  1014 F/cm 1.6 1019 C  1.6 1018  2.2 1018 
1




18
18
2
 1.6 10  2.2 10  0.97V
 2.81 107 F/cm 2
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© CMOS Digital Integrated Circuits – 4th Edition
Example 3.8 (3)
 Sol.(Cont’d)
 Assume that the reverse bias voltage changes from V1=0V to
V2=-1V.
 Find the equivalent factor for this transition.
K eq  
2 0
 V   V 

V V
2


0
2
0
1
1
2 0.97

1
 0.97  (1)  0.97   0.82
 The average junction capacitance can be found as follows
Ceq  A  C j 0  K eq  100 108 cm 2  2.81107 F/cm 2  0.82  230fF
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© CMOS Digital Integrated Circuits – 4th Edition
Junction Capacitances (7)
 The sidewall zero-bias capacitance Cj0sw and the
sidewall voltage equivalence factor Keq(sw) are
different from those of the bottom junction
C j 0 sw 
155
 Si  q  N A ( sw)  N D  1


2  N A ( sw)  N D  0 sw
(3.135)
C jsw  C j 0 sw  xJ
(3.136)
2 0 sw
K eq  
 ( 0 sw  V2  0 sw  V1 )
V2  V1
(3.137)
Ceq ( sw)  P  C jsw  K eq ( sw)
(3.138)
© CMOS Digital Integrated Circuits – 4th Edition
Example 3.9 (1)
 Calculate the junction capacitance per unit area
 NA = 4Ⅹ1018 cm-3
 ND = 2Ⅹ1020 cm-3
 NA(sw) = 8Ⅹ1019 cm-3
 tox = 1.6nm
 Junction depth xj = 32nm
300nm
150nm
60nm
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© CMOS Digital Integrated Circuits – 4th Edition
Example 3.9 (2)
 Sol.
 Junction built-in voltages
 N A  ND 
 4 1018  2 1020 
kT
0 
 ln 
  0.026V  ln 
  1.11V
2
20
q
n
2.1
10



i


 N A ( sw)  N D 
 8 1019  2 1020 
kT
0 sw 
 ln 
  0.026V  ln 
  1.19V
2
20
q
n
2.1
10



i


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© CMOS Digital Integrated Circuits – 4th Edition
Example 3.9 (3)
 Sol.(Cont’d)
 Zero-bias junction capacitance per unit area
C j0

 Si  q  N A  N D  1


2  N A  N D  0

11.7  8.85 1014 F/cm 1.6 1019  4 1018  2  1020  1


18
20 



2
4
10
2
10

 1.11V
 54.1 108 F/cm 2
C j 0 sw

 Si  q  N A  N D  1


2  N A  N D  0
11.7  8.85 1014 F/cm 1.6 1019  8 1019  2 1020 
1



19
20 
2
 8  10  2 10  1.19V
 199.4 108 F/cm 2
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© CMOS Digital Integrated Circuits – 4th Edition
Example 3.9 (4)
 Sol.(Cont’d)
 The zero bias sidewall junction capacitance per unit area can
also be found as follows:
C jsw  C j 0 sw  x j  199.4 108 F/cm 2  32 107 cm  6.38pF/cm
 Calculate the voltage equivalence factor
K eq  
2 1.11

1  (0.1)
K eq ( sw)  
 1.11  1  1.11  0.1  0.675
2 1.19

1  (0.1)
 1.19  1  1.19  0.1  0.682  K
eq
 The total area of the n+/p junction
A  (0.3  0.15)  m 2  (0.15  0.032)  m 2  0.05 m 2
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© CMOS Digital Integrated Circuits – 4th Edition
Example 3.9 (5)
 Sol.(Cont’d)
 The combined equivalent (average) drain-substrate junction
capacitance :
Cdb  A  C j 0  K eq  P  C jsw  K eq ( sw)
 0.05 108 cm 2  54.1108 F/cm 2  0.675
 0.75 104 cm  6.38 1012 F/cm  0.682  0.509 1015 F  0.509fF
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